Freescale Semiconductor Data Sheet Document Number: MR1A16A Rev. 3, 11/2007 128K x 16-Bit 3.3-V Asynchronous Magnetoresistive RAM Introduction The MR1A16A is a 2,097,152-bit magnetoresistive random access memory (MRAM) device organized as 131,072 words of 16 bits. The MR1A16A is equipped with chip enable (E), write enable (W), and output enable (G) pins, allowing for significant system design flexibility without bus contention. Because the MR1A16A has separate byte-enable controls (LB and UB), individual bytes can be written and read. MRAM is a nonvolatile memory technology that protects data in the event of power loss and does not require periodic refreshing. The MR1A16A is the ideal memory solution for applications that must permanently store and retrieve critical data quickly. The MR1A16A is available in a 400-mil, 44-lead plastic small-outline TSOP type-II package with an industry-standard center power and ground SRAM pinout. The MR1A16A is available in Commercial (0C to 70C), Industrial (-40C to 85C) and Extended (-40C to 105C) ambient temperature ranges. (c) Freescale Semiconductor, Inc., 2007. All rights reserved. MR1A16A 44-TSOP Case 924A-02 Features * Single 3.3-V power supply * Commercial temperature range (0C to 70C), Industrial temperature range (-40C to 85C) and Extended temperature range (-40C to 105C) * Symmetrical high-speed read and write with fast access time (35 ns) * Flexible data bus control -- 8 bit or 16 bit access * Equal address and chip-enable access times * Automatic data protection with low-voltage inhibit circuitry to prevent writes on power loss * All inputs and outputs are transistor-transistor logic (TTL) compatible * Fully static operation * Full nonvolatile operation with 20 years minimum data retention Device Pin Assignment OUTPUT ENABLE BUFFER G UPPER BYTE OUTPUT ENABLE LOWER BYTE OUTPUT ENABLE 8 A[16:0] ADDRESS BUFFERS 17 9 ROW DECODER COLUMN DECODER CHIP ENABLE BUFFER E UB SENSE AMPS 8 LOWER BYTE OUTPUT BUFFER 128K x 16 BIT MEMORY ARRAY 16 UB 8 FINAL WRITE DRIVERS 8 UPPER BYTE WRITE ENABLE BYTE ENABLE BUFFER LB LB 8 16 WRITE ENABLE BUFFER W UPPER BYTE OUTPUT BUFFER 8 8 UPPER BYTE WRITE DRIVER 8 LOWER BYTE WRITE DRIVER DQU[15:8] 8 DQL[7:0] LOWER BYTE WRITE ENABLE Figure 1. Block Diagram Device Pin Assignment A0 A1 A2 A3 A4 E DQL0 DQL1 DQL2 DQL3 VDD VSS DQL4 DQL5 DQL6 DQL7 W A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A16 A15 A14 G UB LB DQU15 DQU14 DQU13 DQU12 VSS VDD DQU11 DQU10 DQU9 DQU8 NC VDD A13 A12 A11 A10 Table 1. Pin Functions Signal Name Function A Address input E Chip enable W Write enable G Output enable UB Upper byte select LB Lower byte select DQL Data I/O, lower byte DQU Data I/O, upper byte VDD Power supply VSS Ground NC Do not connect this pin Figure 2. MR1A16A in 44-Pin TSOP Type II Package MR1A16A Data Sheet, Rev. 3 2 Freescale Semiconductor Electrical Specifications Table 2. Operating Modes Mode VDD Current DQL[7:0]2 DQU[15:8]2 X Not selected ISB1, ISB2 Hi-Z Hi-Z X X Output disabled IDDR Hi-Z Hi-Z X H H Output disabled IDDR Hi-Z Hi-Z L H L H Lower byte read IDDR DOut Hi-Z L L H H L Upper byte read IDDR Hi-Z DOut L L H L L Word read IDDR DOut DOut L X L L H Lower byte write IDDW DIn Hi-Z L X L H L Upper byte write IDDW Hi-Z DIn L X L L L Word write IDDW DIn DIn E1 G1 W1 LB1 UB1 H X X X L H H L X L NOTES: 1 H = high, L = low, X = don't care 2 Hi-Z = high impedance Electrical Specifications Absolute Maximum Ratings This device contains circuitry to protect the inputs against damage caused by high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage greater than maximum rated voltages to these high-impedance (Hi-Z) circuits. The device also contains protection against external magnetic fields. Precautions should be taken to avoid application of any magnetic field more intense than the maximum field intensity specified in the maximum ratings. MR1A16A Data Sheet, Rev. 3 Freescale Semiconductor 3 Electrical Specifications Table 3. Absolute Maximum Ratings1 Parameter Supply voltage 2 Voltage on any pin 2 Symbol Value Unit VDD -0.5 to 4.0 V VIn -0.5 to VDD + 0.5 V Output current per pin IOut 20 mA Package power dissipation3 PD 0.600 W Temperature under bias MR1A16AYS35 (Commercial) MR1A16ACYS35 (Industrial) MR1A16AVYS35 (Extended) TBias Storage temperature Tstg -55 to 150 C TLead 260 C Lead temperature during solder (3 minute max) Maximum magnetic field during write MR1A16AYS35 (Commercial) MR1A16ACYS35 (Industrial) MR1A16AVYS35 (Extended) Hmax_write Maximum magnetic field during read or standby Hmax_read -10 to 85 -45 to 95 -45 to 110 15 25 25 C Oe 100 Oe NOTES: 1 Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to recommended operating conditions. Exposure to excessive voltages or magnetic fields could affect device reliability. 2 All voltages are referenced to V . SS 3 Power dissipation capability depends on package characteristics and use environment. Table 4. Operating Conditions Parameter Power supply voltage Symbol VDD Min Typ Max Unit 1 3.3 3.6 V 1 V 3.0 Write inhibit voltage VWI 2.5 2.7 3.0 Input high voltage VIH 2.2 -- VDD + 0.32 V Input low voltage VIL -0.53 -- 0.8 V Operating temperature MR1A16AYS35 (Commercial) MR1A16ACYS35 (Industrial) MR1A16AVYS35 (Extended) TA 0 -40 -40 70 85 105 C NOTES: 1 After power up or if V DD falls below VWI, a waiting period of 2 ms must be observed, and E and W must remain high for 2 ms. Memory is designed to prevent writing for all input pin conditions if VDD falls below minimum VWI. 2 V (max) = V IH DD + 0.3 Vdc; VIH (max) = VDD + 2.0 Vac (pulse width 10 ns) for I 20.0 mA. 3 V (min) = -0.5 Vdc; V (min) = -2.0 Vac (pulse width 10 ns) for I 20.0 mA. IL IL MR1A16A Data Sheet, Rev. 3 4 Freescale Semiconductor Electrical Specifications Direct Current (dc) Table 5. dc Characteristics Parameter Symbol Min Typ Max Unit Input leakage current Ilkg(I) -- -- 1 A Output leakage current Ilkg(O) -- -- 1 A Output low voltage (IOL = +4 mA) (IOL = +100 A) VOL -- -- 0.4 VSS + 0.2 V Output high voltage (IOH = -4 mA) (IOH = -100 mA) VOH 2.4 VDD - 0.2 -- -- V Table 6. Power Supply Characteristics Parameter Symbol Typ Max Unit IDDR 55 80 mA ac active supply current -- write modes1 (VDD = max) MR1A16AYS35 (Commercial) MR1A16ACYS35 (Industrial) MR1A16AVYS35 (Extended) IDDW 105 105 105 155 165 165 mA ac standby current (VDD = max, E = VIH) (no other restrictions on other inputs) ISB1 18 28 mA CMOS standby current (E VDD - 0.2 V and VIn VSS + 0.2 V or VDD - 0.2 V) (VDD = max, f = 0 MHz) ISB2 9 12 mA ac active supply current -- read (IOut = 0 mA, VDD = max) modes1 NOTES: 1 All active current measurements are measured with one address transition per cycle. Table 7. Capacitance1 Parameter Symbol Typ Max Unit Address input capacitance CIn -- 6 pF Control input capacitance CIn -- 6 pF Input/output capacitance CI/O -- 8 pF NOTES: 1 f = 1.0 MHz, dV = 3.0 V, T = 25C, periodically sampled rather than 100% tested. A MR1A16A Data Sheet, Rev. 3 Freescale Semiconductor 5 Electrical Specifications Table 8. ac Measurement Conditions Parameter Value Logic input timing measurement reference level 1.5 V Logic output timing measurement reference level 1.5 V Logic input pulse levels 0 or 3.0 V Input rise/fall time 2 ns Output load for low and high impedance parameters See Figure 3A Output load for all other timing parameters See Figure 3B +3.3 V ZD = 50 725 OUTPUT OUTPUT RL = 50 600 5 pF VL = 1.5 V A B Figure 3. Output Load for ac Test MR1A16A Data Sheet, Rev. 3 6 Freescale Semiconductor Electrical Specifications This page is intentionally blank. MR1A16A Data Sheet, Rev. 3 Freescale Semiconductor 7 Timing Specifications Timing Specifications Read Mode Table 9. Read Cycle Timing1, 2 Parameter Symbol Min Max Unit tAVAV 35 -- ns Address access time tAVQV -- 35 ns 3 Enable access time tELQV -- 35 ns Output enable access time tGLQV -- 15 ns Byte enable access time tBLQV -- 15 ns Output hold from address change tAXQX 3 -- ns tELQX 3 -- ns tGLQX 0 -- ns tBLQX 0 -- ns tEHQZ 0 15 ns tGHQZ 0 10 ns tBHQZ 0 10 ns Read cycle time Enable low to output active4, 5 4, 5 Output enable low to output active 4, 5 Byte enable low to output active Enable high to output Hi-Z4, 5 4, 5 Output enable high to output Hi-Z 4, 5 Byte high to output Hi-Z NOTES: 1 W is high for read cycle. 2 Due to product sensitivities to noise, power supplies must be properly grounded and decoupled, and bus contention conditions must be minimized or eliminated during read and write cycles. 3 Addresses valid before or at the same time E goes low. 4 This parameter is sampled and not 100% tested. 5 Transition is measured 200 mV from steady-state voltage. MR1A16A Data Sheet, Rev. 3 8 Freescale Semiconductor Timing Specifications tAVAV A (ADDRESS) tAXQX Q (DATA OUT) PREVIOUS DATA VALID DATA VALID tAVQV NOTES: Device is continuously selected (E VIL, G V IL). Figure 4. Read Cycle 1 tAVAV A (ADDRESS) tAVQV tELQV E (CHIP ENABLE) tEHQZ tELQX G (OUTPUT ENABLE) tGHQZ tGLQV tGLQX LB, UB (BYTE ENABLE) tBHQZ tBLQV tBLQX DATA VALID Q (DATA OUT) Figure 5. Read Cycle 2 MR1A16A Data Sheet, Rev. 3 Freescale Semiconductor 9 Timing Specifications Write Mode Table 10. Write Cycle Timing 1 (W Controlled)1, 2, 3, 4, 5 Parameter Symbol Min Max Unit tAVAV 35 -- ns Address set-up time tAVWL 0 -- ns Address valid to end of write (G high) tAVWH 18 -- ns Address valid to end of write (G low) tAVWH 20 -- ns Write pulse width (G high) tWLWH tWLEH 15 -- ns Write pulse width (G low) tWLWH tWLEH 15 -- ns Data valid to end of write tDVWH 10 -- ns Data hold time tWHDX 0 -- ns tWLQZ 0 12 ns tWHQX 3 -- ns tWHAX 12 -- ns Write cycle time6 Write low to data Hi-Z Write high to output Write recovery time 7, 8, 9 active7, 8, 9 NOTES: 1 A write occurs during the overlap of E low and W low. 2 Due to product sensitivities to noise, power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. 3 If G goes low at the same time or after W goes low, the output will remain in a high-impedance state. 4 After W, E, or UB/LB has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. 5 The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. 6 All write cycle timings are referenced from the last valid address to the first transition address. 7 This parameter is sampled and not 100% tested. 8 Transition is measured 200 mV from steady-state voltage. 9 At any given voltage or temperature, t WLQZ max < tWHQX min. MR1A16A Data Sheet, Rev. 3 10 Freescale Semiconductor Timing Specifications tAVAV A (ADDRESS) tAVWH tWHAX E (CHIP ENABLE) tWLEH tWLWH W (WRITE ENABLE) tAVWL LB, UB (BYTE ENABLE) tDVWH D (DATA IN) tWHDX DATA VALID tWLQZ Q (DATA OUT) Hi-Z Hi-Z tWHQX Figure 6. Write Cycle 1 (W Controlled) MR1A16A Data Sheet, Rev. 3 Freescale Semiconductor 11 Timing Specifications Table 11. Write Cycle Timing 2 (E Controlled)1, 2, 3, 4, 5 Parameter Symbol Min Max Unit tAVAV 35 -- ns Address set-up time tAVEL 0 -- ns Address valid to end of write (G high) tAVEH 18 -- ns Address valid to end of write (G low) tAVEH 20 -- ns Enable to end of write (G high) tELEH tELWH 15 -- ns Enable to end of write (G low)7, 8 tELEH tELWH 15 -- ns Data valid to end of write tDVEH 10 -- ns Data hold time tEHDX 0 -- ns Write recovery time tEHAX 12 -- ns Write cycle time 6 NOTES: 1 A write occurs during the overlap of E low and W low. 2 Due to product sensitivities to noise, power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. 3 If G goes low at the same time or after W goes low, the output will remain in a high-impedance state. 4 After W, E, or UB/LB has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. 5 The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. 6 All write cycle timings are referenced from the last valid address to the first transition address. 7 If E goes low at the same time or after W goes low, the output will remain in a high-impedance state. 8 If E goes high at the same time or before W goes high, the output will remain in a high-impedance state. MR1A16A Data Sheet, Rev. 3 12 Freescale Semiconductor Timing Specifications tAVAV A (ADDRESS) tAVEH tEHAX tELEH E (CHIP ENABLE) tAVEL tELWH W (WRITE ENABLE) LB, UB (BYTE ENABLE) tDVEH D (DATA IN) Q (DATA OUT) tEHDX DATA VALID Hi-Z Figure 7. Write Cycle 2 (E Controlled) MR1A16A Data Sheet, Rev. 3 Freescale Semiconductor 13 Timing Specifications Table 12. Write Cycle Timing 3 (LB/UB Controlled)1, 2, 3, 4, 5, 6 Parameter Symbol Min Max Unit tAVAV 35 -- ns Address set-up time tAVBL 0 -- ns Address valid to end of write (G high) tAVBH 18 -- ns Address valid to end of write (G low) tAVBH 20 -- ns Byte pulse width (G high) tBLEH tBLWH 15 -- ns Byte pulse width (G low) tBLEH tBLWH 15 -- ns Data valid to end of write tDVBH 10 -- ns Data hold time tBHDX 0 -- ns Write recovery time tBHAX 12 -- ns Write cycle time 7 NOTES: 1 A write occurs during the overlap of E low and W low. 2 Due to product sensitivities to noise, power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. 3 If G goes low at the same time or after W goes low, the output will remain in a high-impedance state. 4 After W, E, or UB/LB has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. 5 If both byte control signals are asserted, the two signals must have no more than 2 ns skew between them. 6 The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. 7 All write cycle timings are referenced from the last valid address to the first transition address. MR1A16A Data Sheet, Rev. 3 14 Freescale Semiconductor Timing Specifications tAVAV A (ADDRESS) tAVBH tBHAX E (CHIP ENABLE) tAVBL tBLEH tBLWH LB, UB (BYTE ENABLE) tBHDX W (WRITE ENABLE) tDVBH D (DATA IN) Q (DATA OUT) DATA VALID Hi-Z Hi-Z Figure 8. Write Cycle 3 (LB/UB Controlled) MR1A16A Data Sheet, Rev. 3 Freescale Semiconductor 15 Ordering Information Ordering Information This product is available in Commercial, Industrial, and Extended temperature versions. Freescale's semiconductor products can be classified into the following tiers: "Commercial", "Industrial" and "Extended." A product should only be used in applications appropriate to its tier as shown below. For questions, please contact a Freescale sales representative. * Commercial -- Typically 5 year applications - personal computers, PDA's, portable telecom products, consumer electronics, etc. * Industrial, Extended -- Typically 10 year applications - installed telecom equipment, workstations, servers, etc. These products can also be used in Commercial applications. Part Numbering System (Order by Full Part Number) MR 1 A 16 A V YS 35 Timing Set (35 = 35 ns) Package Type (YS = TSOP II) Operating Temperature Range (Missing = 0C to 70C, C = -40C to 85C, V = -40C to 105C) Revision (A = rev 1) I/O Configuration (08 = 8 bits, 16 = 16 bits) Freescale MRAM Memory Prefix Density Code (0 = 1 Mb, 1 = 2 Mb, 2 = 4 Mb, 4 = 16 Mb) Memory Type (A = async, S = sync) Package Information Table 13. Package Information Device Pin Count Package Type Designator Case No. Document No. RoHS Compliant MR1A16A 44 TSOP Type II YS 924A-02 98ASS23673W True MR1A16A Data Sheet, Rev. 3 16 Freescale Semiconductor Revision History Revision History Revision History Rev Date Description of Change 1 10 Aug 2007 Initial public release version. 2 21 Sep 2007 Table 6: Applied values to TBD's in IDD specifications. 3 12 Nov 2007 Table 2: Changed IDDA to IDDR or IDDW. Mechanical Drawing The following pages detail the package available to MR1A16A. MR1A16A Data Sheet, Rev. 3 Freescale Semiconductor 17 Mechanical Drawing MR1A16A Data Sheet, Rev. 3 18 Freescale Semiconductor Mechanical Drawing MR1A16A Data Sheet, Rev. 3 Freescale Semiconductor 19 Mechanical Drawing MR1A16A Data Sheet, Rev. 3 20 Freescale Semiconductor Mechanical Drawing MR1A16A Data Sheet, Rev. 3 Freescale Semiconductor 21 How to Reach Us: Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted USA/Europe/Locations not listed: Freescale Semiconductor Literature Distribution P.O. Box 5405, Denver, Colorado 80217 1-800-521-6274 or 480-768-2130 hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. 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Should Buyer purchase or use Learn More: For more information about Freescale Semiconductor products, please visit http://www.freescale.com Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc. 2007. MR1A16A Rev. 3, 11/2007