ISPGAL22V10C-10LJ - LATTICE SEMICONDUCTOR

ispGAL™22V10 Device Datasheet

June 2010

All Devices Discontinued!

Product Change Notifications (PCNs) have been issued to discontinue all devices in this

data sheet.

The original datasheet pages have not been modified and do not reflect those changes.

Please refer to the table below for reference PCN and current product status.

Product Line Ordering Part Number Product Status Reference PCN

ispGAL22V10C-7LJ

ispGAL22V10C-7LJN PCN#06-07

ispGAL22V10C-10LJ

ispGAL22V10C-10LJN

ispGAL22V10C-15LJ

ispGAL22V10C-15LJN

ispGAL22V10C-15LJI

ispGAL22V10C-7LK

ispGAL22V10C-10LK

ispGAL22V10C-15LK

ispGAL22V10C

ispGAL22V10C-15LKI

Discontinued PCN#09-10

5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone (503) 268-8000 z FAX (503) 268-8347

Internet: http://www.latticesemi.com

ispGAL22V10

In-System Programmable E2CMOS PLD

Generic Array Logic™

Description

The ispGAL22V10, at 7.5ns maximum propagation delay time,

combines a high performance CMOS process with Electrically Eras-

able (E2) floating gate technology to provide the industry's first in-

system programmable 22V10 device. E2 technology offers high

speed (<100ms) erase times, providing the ability to reprogram or

reconfigure the device quickly and efficiently.

The generic architecture provides maximum design flexibility by al-

lowing the Output Logic Macrocell (OLMC) to be configured by the

user. The ispGAL22V10 is fully function/fuse map/parametric com-

patible with standard bipolar and CMOS 22V10 devices. The stan-

dard PLCC package provides the same functional pinout as the

standard 22V10 PLCC package with No-Connect pins being used

for the ISP interface signals.

Unique test circuitry and reprogrammable cells allow complete AC,

DC, and functional testing during manufacture. As a result, Lat-

tice Semiconductor delivers 100% field programmability and func-

tionality of all GAL products. In addition, 10,000 erase/write cycles

and data retention in excess of 20 years are specified.

Features

• IN-SYSTEM PROGRAMMABLE™ (5-V ONLY)

— 4-Wire Serial Programming Interface

— Minimum 10,000 Program/Erase Cycles

— Built-in Pull-Down on SDI Pin Eliminates Discrete

Resistor on Board (ispGAL22V10C Only)

• HIGH PERFORMANCE E2CMOS® TECHNOLOGY

— 7.5 ns Maximum Propagation Delay

— Fmax = 1 11 MHz

— 5 ns Maximum from Clock Input to Data Output

— UltraMOS® Advanced CMOS Technology

• ACTIVE PULL-UPS ON ALL LOGIC INPUT AND I/O PINS

• COMPATIBLE WITH STANDARD 22V10 DEVICES

— Fully Function/Fuse-Map/Parametric Compatible

with Bipolar and CMOS 22V10 Devices

•E

2 CELL TECHNOLOGY

— In-System Programmable Logic

— 100% Tested/100% Y ields

— High Speed Electrical Erasure (<100ms)

— 20 Year Data Retention

• TEN OUTPUT LOGIC MACROCELLS

— Maximum Flexibility for Complex Logic Designs

• APPLICATIONS INCLUDE:

— DMA Control

— State Machine Control

— High Speed Graphics Processing

— Software-Driven Hardware Configuration

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

• LEAD-FREE PACKAGE OPTIONS

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. August 2004

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

PLCC

SDO

I/O/Q

228

MODE

11 14 16 19

12 18

I/O/Q

I/CLK

I/O/Q

Vcc

SCLK

I/O/Q

SDI

GND

Vcc

I/O/Q

SDO

I/O/Q

SDI

SCLK

I/CLK

MODE

GND

ispGAL

22V10

Top View

SSOP

ispGAL22V10

Top View

isp22v10_04

Functional Block Diagram

Pin Configuration

Lead-Free

Package

Options

Available!

PROGRAMMABLE

AND-ARRAY

(132X44)

I/O/Q

SDO

SDI

MODE

SCLK

I/CLK

RESET

PRESET

OLMC

PROGRAMMING

LOGIC

ALL DEVICES

DISCONTINUED

Specifications ispGAL22V10

Ordering Information

Conventional Packaging

Commercial Grade Specifications

Industrial Grade Specifications

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51018 561IJL51-C01V22LAGpsiCCLPdaeL-82

01V22LAGpsiC-51LIKdaeL-82POSS

Part Number Description

Blank = Commercial

I = Industrial

Grade

Package

PowerL = Low Power

Speed (ns)

XXXXXXXX XX X XX X

Device Name

J = PLCC

JN = Lead-Free PLCC

K = SSOP

ispGAL22V10C

Lead-Free Packaging

Commercial Grade Specifications

1. Discontinued per PCN #06-07. Contact Rochester Electronics for available inventory.

)sn(dpT)sn(usT)sn(ocT)Am(ccI#gniredrOegakcaP

5.75.65 041JL7-C01V22LAGpsi

CCLPdaeL-82

01V22LAGpsiCL7-K daeL-82POSS

0177 041JL01-C01V22LAGpsiCCLPdaeL-82

01V22LAGpsiC-01LK daeL-82POSS

51018 041JL51-C01V22LAGpsiCCLPdaeL-82

01V22LAGpsiC-51LK dae

L-82POSS

)sn(dpT)sn(usT)sn(ocT)Am(ccI#gniredrOegakcaP

5.75.65 041NJL7-C01V22LAGpsi

CCLPdaeL-82eerF-daeL

0177 041NJL01-C01V22LAGpsiCCLPdaeL-82eerF-daeL

51018 041NJL51-C01V22LAGpsiCCLPdaeL-82eerF-daeL

ALL DEVICES

DISCONTINUED

Specifications ispGAL22V10

ispGAL22V10 OUTPUT LOGIC MACROCELL (OLMC)

Each of the Macrocells of the ispGAL22V10 has two primary func-

tional modes: registered, and combinatorial I/O. The modes and

the output polarity are set by two bits (SO and S1), which are nor-

mally controlled by the logic compiler. Each of these two primary

modes, and the bit settings required to enable them, are described

below and on the following page.

REGISTERED

In registered mode the output pin associated with an individual

OLMC is driven by the Q output of that OLMC’s D-type flip-flop.

Logic polarity of the output signal at the pin may be selected by

specifying that the output buffer drive either true (active high) or

inverted (active low). Output tri-state control is available as an in-

dividual product-term for each OLMC, and can therefore be defined

by a logic equation. The D flip-flop’s /Q output is fed back into the

AND array, with both the true and complement of the feedback

available as inputs to the AND array.

NOTE: In registered mode, the feedback is from the /Q output of

the register, and not from the pin; therefore, a pin defined as reg-

istered is an output only, and cannot be used for dynamic

I/O, as can the combinatorial pins.

COMBINATORIAL I/O

In combinatorial mode the pin associated with an individual OLMC

is driven by the output of the sum term gate. Logic polarity of the

output signal at the pin may be selected by specifying that the output

buffer drive either true (active high) or inverted (active low). Out-

put tri-state control is available as an individual product-term for

each output, and may be individually set by the compiler as either

“on” (dedicated output), “off” (dedicated input), or “product-term

driven” (dynamic I/O). Feedback into the AND array is from the pin

side of the output enable buffer. Both polarities (true and inverted)

of the pin are fed back into the AND array.

The ispGAL22V10 has a variable number of product terms per

OLMC. Of the ten available OLMCs, two OLMCs have access to

eight product terms (pins 17 and 27), two have ten product terms

(pins 18 and 26), two have twelve product terms (pins 19 and 25),

two have fourteen product terms (pins 20 and 24), and two OLMCs

have sixteen product terms (pins 21 and 23). In addition to the

product terms available for logic, each OLMC has an additional

product-term dedicated to output enable control.

The output polarity of each OLMC can be individually programmed

to be true or inverting, in either combinatorial or registered mode.

This allows each output to be individually configured as either active

high or active low.

The ispGAL22V10 has a product term for Asynchronous Reset (AR)

and a product term for Synchronous Preset (SP). These two prod-

uct terms are common to all registered OLMCs. The Asynchronous

Reset sets all registers to zero any time this dedicated product term

is asserted. The Synchronous Preset sets all registers to a logic

one on the rising edge of the next clock pulse after this product term

is asserted.

NOTE: The AR and SP product terms will force the Q output of the

flip-flop into the same state regardless of the polarity of the output.

Therefore, a reset operation, which sets the register output to a zero,

may result in either a high or low at the output pin, depending on

the pin polarity chosen.

QCLK

4 TO 1

MUX

2 TO 1

MUX

Output Logic Macrocell (OLMC)

Output Logic Macrocell Configurations

ALL DEVICES

DISCONTINUED

Specifications ispGAL22V10

ACTIVE HIGHACTIVE LOW

S0 = 1

S1 = 1

S0 = 0

S1 = 1

S0 = 0

S1 = 0 S0 = 1

S1 = 0

CLK

Registered Mode

Combinatorial Mode

ALL DEVICES

DISCONTINUED

Specifications ispGAL22V10

OLMC

S0

5810

S1

5811

0440

.

0880

ASYNCHRONOUS RESET

(TO ALL REGISTERS)

0 4 8 1216202428323640

SYNCHRONOUS PRESET

(TO ALL REGISTERS)

0000

5764

0044

.

0396

S0

5808

S1

5809

OLMC

S0

5812

S1

5813

0924

.

1452

OLMC

S0

5814

S1

5815

1496

.

2112

OLMC

S0

5816

S1

5817

2156

.

2860

OLMC

S0

5818

S1

5819

2904

.

3608

OLMC

S0

5820

S1

5821

3652

.

4268

OLMC

S0

5822

S1

5823

4312

.

4840

OLMC

S0

5824

S1

5825

4884

.

5324

5368

.

5720

OLMC

S0

5826

S1

5827

13 16

8OLMC

Electronic Signature 5828, 5829 ... ... 5890, 5891

L

S

M

S

Byte 7 Byte 6 Byte 5 Byte 4 Byte 2 Byte 1 Byte 0Byte 3

ispGAL22V10 Logic Diagram/JEDEC Fuse Map

PLCC & SSOP Package Pinout

ALL DEVICES

DISCONTINUED

Specifications ispGAL22V10

VIL Input Low Voltage Vss – 0.5 — 0.8 V

VIH Input High Voltage 2.0 — Vcc+1 V

IIL Input or I/O Low Leakage Current10V ≤ VIN ≤ VIL (MAX.) — — –100 μA

SDI Low Leakage Current20V ≤ VIN ≤ VIL (MAX.) — — 250 μA

IIH Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC ——10μA

SDI High Leakage Current2VIN = VOH (MIN.) — — 1 mA

VOL Output Low Voltage IOL = MAX. Vin = VIL or VIH — — 0.5 V

VOH Output High Voltage IOH = MAX. Vin = VIL or VIH 2.4 — — V

IOL Low Level Output Current — — 16 mA

IOH High Level Output Current — — –3.2 mA

IOS3Output Short Circuit Current VCC = 5V VOUT = 0.5V TA = 25°C –30 — –130 mA

Recommended Operating Conditions

Commercial Devices:

Ambient Temperature (TA) ............................. 0 to +75°C

Supply voltage (VCC)

with Respect to Ground ..................... +4.75 to +5.25V

Industrial Devices:

Ambient Temperature (TA) ............................-40 to 85°C

Supply voltage (VCC)

with Respect to Ground ..................... +4.50 to +5.50V

SYMBOL PARAMETER CONDITION MIN. TYP.4MAX. UNITS

COMMERCIAL

ICC Operating Power VIL = 0.5V VIH = 3.0V L -7/-10/-15 — 90 140 mA

Supply Current ftoggle = 15MHz Outputs Open

Absolute Maximum Ratings(1)

Supply voltage VCC ....................................... -0.5 to +7V

Input voltage applied ........................... -2.5 to VCC +1.0V

Off-state output voltage applied .......... -2.5 to VCC +1.0V

Storage Temperature .................................-65 to 150°C

Ambient Temperature with

Power Applied .........................................-55 to 125°C

1. Stresses above those listed under the “Absolute Maximum

Ratings” may cause permanent damage to the device. These

are stress only ratings and functional operation of the device

at these or at any other conditions above those indicated in

the operational sections of this specification is not implied

(while programming, follow the programming specifications).

Specifications ispGAL22V10C

1) The leakage current is due to the internal pull-up on all pins (except SDI on ispGAL22V10C). See Input Buffer section for

more information.

2) The leakage current is due to the internal pull-down on the SDI pin (ispGAL22V10C only). See Input Buffer section for more

information.

3) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester

ground degradation. Characterized but not 100% tested.

4) Typical values are at Vcc = 5V and TA = 25 °C

INDUSTRIAL

ICC Operating Power VIL = 0.5V VIH = 3.0V L -15 — 90 165 mA

Supply Current ftoggle = 15MHz Outputs Open

DC Electrical Characteristics

Over Recommended Operating Conditions (Unless Otherwise Specified)

ALL DEVICES

DISCONTINUED

Specifications ispGAL22V10

-15

MIN. MAX.

-10

MIN. MAX.

-7

MIN. MAX.

tpd A Input or I/O to Combinatorial Output — 7.5 — 10 — 15 ns

tco A Clock to Output Delay — 5 — 7 — 8 ns

tcf2— Clock to Feedback Delay — 2.5 — 2.5 — 2.5 ns

tsu1— Setup Time, Input or Feedback before Clock↑6.5 — 7 10 — ns

tsu2— Setup Time, SP before Clock↑10 — 10 — 10 — ns

th — Hold Time, Input or Feedback after Clock↑0—0—0 — ns

A Maximum Clock Frequency with 87 — 71.4 — 55.5 — MHz

External Feedback, 1/(tsu + tco)

fmax3A Maximum Clock Frequency with 111 — 105 — 80 — MHz

Internal Feedback, 1/(tsu + tcf)

A Maximum Clock Frequency with 111 — 105 — 83.3 — MHz

No Feedback

twh — Clock Pulse Duration, High 4 — 4 — 6 — ns

twl — Clock Pulse Duration, Low 4 — 4 — 6 — ns

ten B Input or I/O to Output Enabled — 8 — 10 — 15 ns

tdis C Input or I/O to Output Disabled — 8 — 10 — 15 ns

tar A Input or I/O to Asynchronous Reset of Register — 13 — 13 — 20 ns

tarw — Asynchronous Reset Pulse Duration 8 — 8 — 15 — ns

tarr — Asynchronous Reset to Clock Recovery Time 8 — 8 — 10 — ns

tspr — Synchronous Preset to Clock Recovery Time 10 — 10 — 10 — ns

PARAMETER UNITS

TEST

COND.1DESCRIPTION

COM COM/INDCOM

1) Refer to Switching Test Conditions section.

2) Calculated from fmax with internal feedback. Refer to fmax Description section.

3) Refer to fmax Description section.

SYMBOL PARAMETER MAXIMUM* UNITS TEST CONDITIONS

CIInput Capacitance 8 pF VCC = 5.0V, VI = 2.0V

CI/O I/O Capacitance 8 pF VCC = 5.0V, VI/O = 2.0V

*Characterized but not 100% tested.

Specifications ispGAL22V10C

AC Switching Characteristics

Over Recommended Operating Conditions

Capacitance (TA = 25°C, f = 1.0MHz)

ALL DEVICES

DISCONTINUED

Specifications ispGAL22V10

Input or I/O to Output Enable/Disable

Registered Output

Combinatorial Output

fmax with Feedback

Clock Width

dis

INPUT or

I/O FEEDBACK

OUTPUT

CLK

(w/o fdbk)

max

INPUT or

I/O FEEDBACK

REGISTERED

OUTPUT

CLK

VALID INPUT

(external fdbk)

max

CLK

REGISTERED

FEEDBACK

max (internal fdbk)

REGISTERED

OUTPUT

CLK

arw

arr

INPUT or

I/O FEEDBACK

DRIVING AR

Asynchronous Reset

REGISTERED

OUTPUT

CLK

INPUT or

I/O FEEDBACK

DRIVING SP

spr

Synchronous Preset

VALID INPUT

INPUT or

I/O FEEDBACK

COMBINATORIAL

OUTPUT

Switching Waveforms

ALL DEVICES

DISCONTINUED

Specifications ispGAL22V10

Input Pulse Levels GND to 3.0V

Input Rise and Fall Times 3ns 10% – 90%

Input Timing Reference Levels 1.5V

Output Timing Reference Levels 1.5V

Output Load See Figure

3-state levels are measured 0.5V from steady-state active

level.

Output Load Conditions (see figure)

Test Condition R1R2CL

A 300Ω390Ω50pF

B Active High ∞390Ω50pF

Active Low 300Ω390Ω50pF

C Active High ∞390Ω5pF

Active Low 300Ω390Ω5pF

fmax with Internal Feedback 1/(tsu+tcf)

Note: tcf is a calculated value, derived by sub-

tracting tsu from the period of fmax w/internal

feedback (tcf = 1/fmax - tsu). The value of tcf is

used primarily when calculating the delay from

clocking a register to a combinatorial output

(through registered feedback), as shown above.

For example, the timing from clock to a combi-

natorial output is equal to tcf + tpd.

fmax with No Feedback

Note: fmax with no feedback may be less

than 1/twh + twl. This is to allow for a clock

duty cycle of other than 50%.

LOGIC

ARRAY

CLK

Note: fmax with external feedback is cal-

culated from measured tsu and tco.

fmax with External Feedback 1/(tsu+tco)

TEST POINT

C *

FROM OUTPUT (O/Q) 

UNDER TEST

+5V

INCLUDES TEST FIXTURE AND PROBE CAPACITANCE

CLK

LOGIC

ARRAY

LOGIC

ARRAY

CLK

tsu + th

fmax Descriptions

Switching Test Conditions

ALL DEVICES

DISCONTINUED

Specifications ispGAL22V10

Electronic Signature

An electronic signature (ES) is provided in every ispGAL22V10

device. It contains 64 bits of reprogrammable memory that can

contain user-defined data. Some uses include user ID codes,

revision numbers, or inventory control. The signature data is

always available to the user independent of the state of the

security cell.

The electronic signature is an additional feature not present in

other manufacturers' 22V10 devices. To use the extra feature of

the user-programmable electronic signature it is necessary to

choose a Lattice Semiconductor 22V10 device type when compil-

ing a set of logic equations. In addition, many device program-

mers have two separate selections for the device, typically an

ispGAL22V10 and a ispGAL22V10-UES (UES = User Electronic

Signature) or ispGAL22V10-ES. This allows users to maintain

compatibility with existing 22V10 designs, while still having the

option to use the GAL device's extra feature.

The JEDEC map for the ispGAL22V10 contains the 64 extra fuses

for the electronic signature, for a total of 5892 fuses. However, the

ispGAL22V10 device can still be programmed with a standard

22V10 JEDEC map (5828 fuses) with any qualified device pro-

grammer.

Security Cell

A security cell is provided in every ispGAL22V10 device to

prevent unauthorized copying of the array patterns. Once pro-

grammed, this cell prevents further read access to the functional

bits in the device. This cell can only be erased by re-programming

the device, so the original configuration can never be examined

once this cell is programmed. The Electronic Signature is always

available to the user, regardless of the state of this control cell.

Latch-Up Protection

ispGAL22V10 devices are designed with an on-board charge

pump to negatively bias the substrate. The negative bias is of

sufficient magnitude to prevent input undershoots from causing

the circuitry to latch. Additionally, outputs are designed with n-

channel pullups instead of the traditional p-channel pullups to

eliminate any possibility of SCR induced latching.

Device Programming

The ispGAL22V10 device uses a standard 22V10 JEDEC fusemap

file to describe the device programming information. Any third

party logic compiler can produce the JEDEC file for this device.

In-System Programmability

The ispGAL22V10 device features In-System Programmable

technology. By integrating all the high voltage programming

circuitry on-chip, programming can be accomplished by simply

shifting data into the device. Once the function is programmed,

the non-volatile E2CMOS cells will not lose the pattern even when

the power is turned off.

All necessary programming is done via four TTL level logic

interface signals. These four signals are fed into the on-chip

programming circuitry where a state machine controls the pro-

gramming. The interface signals are Serial Data In (SDI), Serial

Data Out (SDO), Serial Clock (SCLK) and Mode (MODE) control.

For details on the operation of the internal state machine and

programming of ispGAL22V10 devices please refer to the ISP

Architecture and Programming section in this Data Book.

Output Register Preload

When testing state machine designs, all possible states and state

transitions must be verified in the design, not just those required

in the normal machine operations. This is because certain events

may occur during system operation that throw the logic into an

illegal state (power-up, line voltage glitches, brown-outs, etc.). To

test a design for proper treatment of these conditions, a way must

be provided to break the feedback paths, and force any desired

(i.e., illegal) state into the registers. Then the machine can be

sequenced and the outputs tested for correct next state condi-

tions.

The ispGAL22V10 device includes circuitry that allows each

registered output to be synchronously set either high or low. Thus,

any present state condition can be forced for test sequencing. If

necessary, approved GAL programmers capable of executing

test vectors perform output register preload automatically.

Input Buffers

ispGAL22V10 devices are designed with TTL level compatible

input buffers. These buffers have a characteristically high imped-

ance, and present a much lighter load to the driving logic than

bipolar TTL devices.

All input and I/O pins (except SDI on the ispGAL22V10C) also

have built-in active pull-ups. As a result, floating inputs will float

to a TTL high (logic 1). The SDI pin on the ispGAL22V10C has a

built-in pull-down to keep the device out of the programming state

if the pin is not actively driven. However, Lattice Semiconductor

recommends that all unused inputs and tri-stated I/O pins be

connected to an adjacent active input, Vcc, or ground. Doing so

will tend to improve noise immunity and reduce Icc for the device.

(See equivalent input and I/O schematics on the following page.)

Typical Input Current

1.0 2.0 3.0 4.0 5.0

-60

-20

-40

Input Voltage (Volts)

Input Current (μA)

ALL DEVICES

DISCONTINUED

Specifications ispGAL22V10

Power-Up Reset

Vcc (min.)

tpr

Internal Register

Reset to Logic "0"

Device Pin

Reset to Logic "1"

twl

tsu

Device Pin

Reset to Logic "0"

Vcc

CLK

INTERNAL REGISTER

Q - OUTPUT

ACTIVE LOW

OUTPUT REGISTER

ACTIVE HIGH

OUTPUT REGISTER

system power-up, some conditions must be met to provide a valid

power-up reset of the ispGAL22V10. First, the Vcc rise must be

monotonic. Second, the clock input must be at static TTL level as

shown in the diagram during power up. The registers will reset within

a maximum of tpr time. As in normal system operation, avoid clock-

ing the device until all input and feedback path setup times have

been met. The clock must also meet the minimum pulse width

requirements.

Output

Input

(Vref Typical = 3.2V)

Vcc

Vref

Tri-State

Control

Active Pull-up

Circuit

Feedback

(To Input Buffer)

Feedback

Data

Output

(Vref Typical = 3.2V)

Vcc

Vcc Vref

Active Pull-up

Circuit (Except SDI

on ispGAL22V10C)

ESD

Protection

Circuit

ESD

Protection

Circuit

Vcc

Pull-down Resistor

(SDI on ispGAL22V10C Only)

Input/Output Equivalent Schematics

Circuitry within the ispGAL22V10 provides a reset signal to all reg-

isters during power-up. All internal registers will have their Q outputs

set low after a specified time (tpr, 1μs MAX). As a result, the state

on the registered output pins (if they are enabled) will be either high

or low on power-up, depending on the programmed polarity of the

output pins. This feature can greatly simplify state machine design

by providing a known state on power-up. The timing diagram for

power-up is shown below. Because of the asynchronous nature of

ALL DEVICES

DISCONTINUED

Specifications ispGAL22V10

ispGAL22V10C: Typical AC and DC Characteristic Diagrams

Normalized Tpd vs Vcc

Supply Voltage (V)

Normalized Tpd

0.8

0.9

1.1

1.2

4.50 4.75 5.00 5.25 5.50

Normalized Tco vs Vcc

Supply Voltage (V)

Normalized Tco

0.8

0.9

1.1

1.2

4.50 4.75 5.00 5.25 5.50

Normalized Tsu vs Vcc

Supply Voltage (V)

Normalized Tsu

0.8

0.9

1.1

1.2

4.50 4.75 5.00 5.25 5.50

Normalized Tpd vs Temp

Temperature (deg. C)

Normalized Tpd

0.7

0.8

0.9

1.1

1.2

1.3

-55 -25 0 25 50 75 100 125

Normalized Tco vs Temp

Temperature (deg. C)

Normalized Tco

0.7

0.8

0.9

1.1

1.2

1.3

-55 -25 0 25 50 75 100 125

Normalized Tsu vs Temp

Temperature (deg. C)

Normalized Tsu

0.7

0.8

0.9

1.1

1.2

1.3

1.4

-55 -25 0 25 50 75 100 125

Delta Tpd vs # of Outputs

Switching

Number of Outputs Switching

Delta Tpd (ns)

-1

-0.75

-0.5

-0.25

12345678910

Delta Tco vs # of Outputs

Switching

Number of Outputs Switching

Delta Tco (ns)

-1

-0.75

-0.5

-0.25

12345678910

Delta Tco vs Output Loading

Output Loading (pF)

Delta Tco (ns)

-2

0 50 100 150 200 250 300

RISE

FALL

Delta Tpd vs Output Loading

Output Loading (pF)

Delta Tpd(ns)

-2

0 50 100 150 200 250 300

RISE

FALL

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Specifications ispGAL22V10

Vol vs Iol

Iol (mA)

Vol (V)

0.5

1.5

2.5

0.00 20.00 40.00 60.00 80.00 100.00

Voh vs Ioh

Ioh(mA)

Voh (V)

0.00 10.00 20.00 30.00 40.00 50.00 60.00

Voh vs Ioh

Ioh(mA)

Voh (V)

3.5

3.75

4.25

4.5

0.00 1.00 2.00 3.00 4.00

Normalized Icc vs Vcc

Supply Voltage (V)

Normalized Icc

0.8

0.9

1.1

1.2

4.50 4.75 5.00 5.25 5.50

Normalized Icc vs Temp

Temperature (deg. C)

Normalized Icc

0.7

0.8

0.9

1.1

1.2

1.3

-55 -25 0 25 50 75 100 125

Normalized Icc vs Freq.

Frequency (MHz)

Normalized Icc

0.80

0.90

1.00

1.10

1.20

0 25 50 75 100

Delta Icc vs Vcc

Vin (V)

Delta Icc (mA)

0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00

Input Clamp (Vik)

Vik (V)

Iik (mA)

100

-2.00 -1.50 -1.00 -0.50 0.00

ispGAL22V10C: Typical AC and DC Characteristic Diagrams

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Notes

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