24VL024H/MNY - Microchip - Product.Network

24VL024H

Device Selection Table

Features:

• Single-Supply with Operation down to 1.5V

• Low-Power CMOS Technology:

- 400 μA active current, m axim um

-1 μA standby current, maximum

• 2-Wire Serial Interface Bus, I2C™ Compatible

• Schmitt Trigger Inputs for Noise Suppression

• Output Slope Control to eliminate Ground Bounce

• 100 kHz and 400 kHz Compatibility

• Page Write Buffer for up to 16 Bytes

• Self-Timed Write Cycle (including Aut o-Erase)

• Hardware Write Protection for Half Array

(80h-FFh)

• Cascadable up to Eight Devices

• More than 1 Million Erase/Write Cycles

• ESD Protection > 4,000V

• Data Retention > 200 Years

• Factory Programming (QTP) Available

• 8-pin PDIP, SOIC, TSSOP, TDFN and MSOP

Packages

• Temperature Range:

• Pb-Free and RoHS compliant

Description:

The Microchip Technology Inc. 24VL024H is a 2 Kbit

Serial Electrically Erasable PROM with operation

down to 1.5V. The device is organized as a single bl ock

of 256 x 8-bit memory with a 2-wire serial interface.

Low-current design permits operation with typical

standby and active currents of only 1 μA and 400 μA,

respect ively. The de vic e has a p age wri te c apability for

up to 16 bytes of data. Functional address lines allow

the con nectio n of u p to e ight 2 4VL024H devic es on the

same bus for up to 16 Kbits of contiguous EEPROM

memory. The devic e is available in the standard 8-pin

PDIP, 8-pin SOIC (150 mil), TSSOP, 2x3 TDFN and

MSOP packages.

Block Diagram

Package Types

Part Number VCC Range Max. Clock

24VL02 4H 1.5 to 3.6V 400 kHz(1)

Note 1: 100 kHz for VCC < 1.8V

- -20°C to +85°C

I/O

Control

Logic

Memory

Control

Logic XDEC

HV Generator

EEPROM

Array

Write-Protect

Circuitry

YDEC

VCC

VSS

Sense Amp.

R/W Control

SDA SCL

A0 A1 A2 WP

VSS

VCC

SCL

SDA

PDIP, MSOP SOIC, TSSOP

VSS

VCC

SCL

SDA

TDFN

VSS

SCL

SDA

VCC

2K I2C™ Serial EEPROM with Half-Array Write-Protect

24VL024H

1.0 ELECTRIC AL CHARACTERISTICS

Absolute Maximum Ratings (†)

VCC.............................................................................................................................................................................6.5V

All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied..................................................................................................-20°C to +85°C

ESD protection on all pins......................................................................................................................................................≥ 4 kV

TABLE 1-1: DC CHARACTERISTICS

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a s tres s rati ng only a nd fun ct ion al operat ion of the device at th ose or any o ther cond iti ons a bove th ose

indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

DC CHARACTERISTICS Electrical Characteristics:

VCC = +1.5V to 3.6V TA = -20°C to +85°C

Param.

No. Sym. Characteristic Min. Max. Units Conditions

D1 — A0, A1, A2, SCL, SDA

and WP pins: ————

D2 VIH High-level input voltage 0.7 VCC —V—

D3 VIL Low-level input voltage — 0.3 VCC V—

D4 VHYS Hysteresis of Schmitt

Trigger inputs

(SDA, SCL pins)

0.05 VCC —V(Note)

D5 VOL Low-level output voltage — 0.40 V IOL = 3.0 mA @ VCC = 3.6V

IOL = 2.1 mA @ VCC = 2.5V

D6 ILI Input leakage current — ±1 μAVIN = VSS or VCC, WP = VSS

D7 ILO Output leaka ge curre nt — ±1 μAVOUT = VSS or VCC

D8 CIN,

COUT Pin capacitance

(all inputs/ou tpu t s) —10pFVCC = 3.6V (Note)

TA = 25°C, f = 1 MHz

D9 ICC Read Operating current — 400 μAVCC = 3.6V, SCL = 400 kHz

ICC Write — 3 mA VCC = 3.6V

D10 ICCS Standby current — 1 μAVCC = 3.6V, SCL = SDA = VCC

WP = VSS, A0, A1, A2 = VSS

Note: This parameter is periodically sampled and not 100% tested.

24VL024H

TABLE 1-2: AC CHARACTERISTICS

AC CHARACTERISTICS Electrical Characteristics:

VCC = +1.5V to 3.6V TA = -20°C t o +85° C

Param.

No. Symbol Characteristic Min. Max. Units Conditions

CLK Clock frequency —

—100

400 kHz 1.5V ≤ VCC < 1.8V

1.8V ≤ VCC ≤ 3.6V

2THIGH Clock high time 4000

600 —

—ns 1.5V ≤ VCC < 1.8V

1.8V ≤ VCC ≤ 3.6V

LOW Clock low time 4700

1300 —

—ns 1.5V ≤ VCC < 1.8V

1.8V ≤ VCC ≤ 3.6V

4TRSDA and SCL rise time

(Note 1) —

—1000

300 ns 1.5V ≤ VCC < 1.8V

1.8V ≤ VCC ≤ 3.6V

5TFSDA and SCL fall time

(Note 1) —

—1000

300 ns 1.5V ≤ VCC < 1.8V

1.8V ≤ VCC ≤ 3.6V

HD:STA Start condition hold time 4000

600 —

—ns 1.5V ≤ VCC < 1.8V

1.8V ≤ VCC ≤ 3.6V

7TSU:STA Start condition setup time 4700

600 —

—ns 1.5V ≤ VCC < 1.8V

1.8V ≤ VCC ≤ 3.6V

8THD:DAT Data input hold time 0 — ns (Note 2)

9TSU:DAT Data input setup time 250

100 —

—ns 1.5V ≤ VCC < 1.8V

1.8V ≤ VCC ≤ 3.6V

10 TSU:STO Stop condition setup time 4000

600 —

—ns 1.5V ≤ VCC < 1.8V

1.8V ≤ VCC ≤ 3.6V

11 TSU:WP WP setup time 4000

600 —

—ns 1.5V ≤ VCC < 1.8V

1.8V ≤ VCC ≤ 3.6V

12 THD:WP WP hold time 4700

600 —

—ns 1.5V ≤ VCC < 1.8V

1.8V ≤ VCC ≤ 3.6V

13 TAA Output valid from clock

(Note 2) —

—3500

900 ns 1.5V ≤ VCC < 1.8V

1.8V ≤ VCC ≤ 3.6V

14 TBUF

Bus fre e tim e : Time the b us must

be fre e befo re a n e w transmis-

sion can start

1300

4700 —

—ns 1.5V ≤ VCC < 1.8V

1.8V ≤ VCC ≤ 3.6V

15 TSP Input filter spike suppression

(SDA and SC L pins) —50ns(Not e 1 and Note 3)

16 TWC Write cycle time (byte or page) — 5 ms —

17 — Endurance 1M — cycles 25°C, VCC = 3.6V, Block mode

(Note 4)

Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

3: The combi ned TSP and VHYS spec ifi cat ion s are due to new Sc hm itt Trigger inputs, wh ic h p r ovide impro ve d

noise spike suppression. This eliminates the need for a TI specification for standard operation.

4: This parame ter is not tested but en sure d by characterization. For endurance esti mates in a specif ic appli-

cation, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at

www.microchip.com.

24VL024H

FIGURE 1-1: BUS TIMING DAT A

(unprotected)

(protected)

SCL

SDA

Out

D4 4

11 12

24VL024H

2.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 2-1.

TABLE 2-1: PIN FUNCTION TABLE

2.1 SDA Serial Data

This is a bidirectional pin used to transfer addresses

and data into and out of the device. It is an open drain

terminal. Therefore, the SDA bus requires a pull-up

resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for

400 kHz).

For normal data transfer, SDA is allowed to change

only during SCL low. Changes during SCL high are

reserved for indicating the Start an d Stop condit ions.

2.2 SCL Serial Clock

The SCL in pu t is u se d to s ynchro ni ze th e da t a transfer

to and from the device.

2.3 A0, A1, A2

The A0, A1 and A2 inputs are used by the 24VL024H

for multiple device operations. The levels on these

inputs are compared with the corresponding bits in the

slave address. The chip is selected if the compare is

true.

Up to eight 24VL024H devices may be connected to

the same bus by using different Chip Select bit

combinations. These inputs must be connected to

either VCC or VSS.

In most applications the chip address inputs, A0, A1

and A2, are hard-wired to logic ‘0’ or logic ‘1’. For

applications in which these pins are controlled by a

microc ontroller or oth er programmabl e device, th e chip

address pins must be driven to logic ‘0’ or logic ‘1’

before normal device operation can proceed.

2.4 WP

WP is the hardware w rite - prot ec t pin. It mu st be tie d to

VCC or VSS. If tied to VCC, the hardware write protection

is enabled and will protect half of the array (80h-FFh).

If the WP pin is tied to VSS the hardware write

protection is disabled.

2.5 Noise Protection

The 24VL024H employs a VCC thresh old dete ctor cir -

cuit that disables the internal erase/write logic if the

VCC is below 1.2 volts at nominal conditions.

The SCL and SDA inputs have Schmitt Trigger and

filter circuits that suppress noise spikes to assure

proper device operation, even on a noisy bus.

Name 8-pin

PDIP 8-pin

SOIC 8-pin

TSSOP 8-pin

MSOP 8-pin

TDFN Function

A0 1 1 1 1 1 User Configurable Chip Select

A1 2 2 2 2 2 User Configurable Chip Select

A2 3 3 3 3 3 User Configurable Chip Select

VSS 44444Ground

SDA 5 5 5 5 5 Serial Data

SCL 6 6 6 6 6 Serial Clock

WP 7 7 7 7 7 Write-Protect Input

VCC 8 8 8 8 8 + 1.5V to 3.6V

24VL024H

3.0 FUNCTIONAL DESCRIPTION

The 24VL0 24H support s a bidirectio nal, 2-wire bu s and

data transmission protocol. A device that sends data

onto the bus is defined as a transmitter, and a device

receiving data as a receiver. The bus has to be con-

trolled by a master device that generates the Serial

Clock (SCL), controls the bus access and generates

the Start and Stop conditions, while the 24VL024H

works as slave. Both master and slave can operate as

a transmitter or receiver, but the master device

determines which mode is activated.

24VL024H

4.0 BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stab le when ever th e clock lin e is high . Change s in

the data line while the clock line is high will be

interpreted as a Start or Stop condition.

Accordingly, the following bus conditions have been

defined (Figure 4-1 ).

4.1 Bus Not Busy (A)

Both data and clock lines remain high.

4.2 Start Data Transfer (B)

A high-to-low transition of the SDA line while the clock

(SCL) is high determines a Start condition. All

commands must be preceded by a Start condition.

4.3 S top Data Transfer (C)

A low-to-high transition of the SDA line while the clock

(SCL) is high determines a Stop condition. All

operations must be ended with a Stop condition.

4.4 Data Valid (D)

The state of the data line represents valid data when,

after a Start condition, the data line is stable for the

duratio n of the high period of the clock signal.

The data on the line must be changed during the low

period of the clock signal. There is one bit of data per

clock pulse.

Each dat a transf er is initiated w ith a S tart condition an d

terminated with a Stop condition. The number of the

data bytes transferred between the Start and Stop

conditions is determined by the master device and is,

theoret ically, unlimite d, though only the la st sixte en wil l

be stored when doing a write operation. When an

overwrite does occur, it will replace data in a first-in

first- out fashion.

4.5 Acknowledge

Each receiving device, when addressed, is required to

generate an acknowledge after the reception of each

byte. Th e mast er device mus t ge nera te a n ex tra c lock

pulse which is associated with this Acknowledge bit.

The device that acknowledges has to pull down the

SDA line during the Acknowledge clock pulse in such a

way that the SDA line is stable low during the high

period of the acknowledge-related clock pulse. Of

course, setup and hold times must be taken into

account. A master must signal an end of data to the

slave b y not generating an Acknowledge bit on the last

byte that has been clocked out of the slave. In this case,

the slave must leave the data line high to enable the

master to generate the Stop condition (Figure 4-2).

FIGURE 4-1: D ATA TRANSFER SEQUENCE ON THE SERIAL BUS CHARACTERISTICS

FIGURE 4-2: ACKNOWLEDGE TIMING

Note: The 24VL024H does not generate any

Acknowledge bits if an internal

programming cycle is in progress.

(A) (B) (C) (D) (A)(C)

SCL

SDA

Start

Condition Address or

Acknowledge

Valid

Data

Allowed

to Change

Stop

Condition

SCL 987654321 123

The transmitter must release the SDA line at this point

allowing the receiver to pull the SDA line low to acknowl-

edge the previous eight bits of data.

The receiver must release the SDA line at

this point so the transmitter can continue

sending data.

SDA

Acknowledge

Bit

Data fro m tr a nsmitterData from transmitter

24VL024H

5.0 DEVICE ADDRESSING

A control byte is the first byte received following the

Start condition from the master device (Figure 5-1).

The con tr ol by te cons ists of a fou r-bi t co ntro l code ; for

the 24VL024H this is set as ‘1010’ binary for read and

write op erat ion s. Th e ne xt three bit s of th e co ntro l by te

are t he C hip Sele ct b its (A 2, A1 , A0) . Th e C hip S ele ct

bits allow the use of up to eight 24VL024H devices on

the same bus and are used to select which device is

accessed. The Chip Select bits in the control byte must

corresp ond to the logic lev els on the corresp onding A2,

A1 and A0 pins for the device to respond. These bits

are in effect the three Most Significant bits of the word

address.

The last bit of the control byte defines the operation to

be performed. When set to a ‘1’, a read operation is

selected. When set to a ‘0’, a write operation is

selected. Following the Start condition, the 24VL024H

monitors the SDA bus, checking the control byte being

transmitted. Upon receiving a ‘1010’ code and appro-

priate Chip Select bits, the slave device outputs an

Acknowledge signal on the SDA line. Depending on the

stat e of the R /W bit, the 24VL024 H will select a rea d or

write operation.

FIGURE 5-1: CONTROL BYTE FORMAT

5.1 Contiguous Addressing Across

Multi ple Devices

The Chip Select bits (A2, A1, A0) can be used to

expa nd the contiguo us address sp ace for up to 16K bits

by adding up to eight 24VL024H devices on the same

bus. In this case, software can use A0 of the control

byte as address bit A9, A1 as address bit A10, and A2

as address bit A11. It is not possible to sequentially

read across device boundaries.

1010A2 A1 A0SACKR/W

Control Code Chip Select

Bits

Slave Address

Acknowledge Bit

Start Bit

Read/Write Bit

24VL024H

6.0 WRITE OPERATIONS

6.1 Byte Write

Following the Start signal from the master, the device

code (4 bits), the Chip Select bits (3 bits) and the R/W

bit (which is a logic low) are placed onto the bus by the

master transmitter. The device will acknowledge this

control by te during the ninth clock pulse. The ne xt byte

tran smit ted by the ma ster is the word add res s and wi ll

be written into the Address Pointer of the 24VL024H.

After receiving another Acknowledge signal from the

24VL024H, the master device will transmit the data

word to be wr itten into the addressed mem ory locatio n.

The 24VL024H acknowledges again and the master

generates a Stop condition. This initiates the internal

write cycle and the 24VL024H will not

generate Acknowledge signals during this time

(Figure 6-1). If an attempt is made to write to the

protected portion of the array when the hardware write

protection has been enabled, the device will

acknowl edge the co mmand, bu t no data will be wr itten.

The write cycle time must be observed even if write

protection is ena ble d.

6.2 Page Write

The write-control byte, word address and the first data

byte are tr ans mi tted to the 24 VL02 4H in the sam e wa y

as in a byte write. But instead of generating a Stop

conditi on, the maste r transmit s up to 15 addi tional data

bytes to the 24VL024H that are temporarily stored in

the on-chip page buffer and will be written into the

memory once the master has transmitted a Stop

condition. Upon receipt of each word, the four lower

order Address Pointer bits are internally incremented

by on e.

The higher order four bits of the word address remain

constant. If the master should transmit more than 16

bytes prior to generating the Stop condition, the

address counter will roll over and the previously

receive d dat a will be overwri tten. As w ith the by te write

operation, once the Stop condition is received, an

internal write cyc le will begin (Figure 6-2). If an att empt

is made to write to the protected portion of the array

when the hardware write protection has been enabled,

the devi ce wi ll ack nowled ge the c omma nd, but no dat a

will be written. The write cycle time must be observed

even if write protection is enabled.

6.3 Write Protection

The W P pi n m us t be t ie d t o VCC or VSS. If tied to VCC,

half of t he array wil l be write-protec ted (8 0h-FFh). If th e

WP pin is tied to VSS, write operations to all address

loc ations are allowed.

FIGURE 6-1: BYTE WRITE

FIGURE 6-2: PAGE WRITE

Note: Page write opera tions are l imited to wri ting

bytes within a single physical page,

regardless of the number of bytes

actually being written. Physical page

boundaries start at addresses that are

integer multiples of the page buffer size (or

‘page siz e’ ) an d end at ad dres s es that are

integer multiples of [page size – 1]. If a

Page Write command attempts to write

across a physical page boundary, the

result is that the data wraps around to the

beginning of the current page (overwriting

data previously stored there), instead of

being w ritten to the next page, as migh t be

expected. It is therefore necessary that the

application software prevent page write

operations that would attempt to cross a

page boundary.

S P

Bus Activit y

Master

SDA Line

Bus Activity

Control

Byte Word

Address Data

S P

Bus Activit y

Master

SDA Line

Bus Activity

Control

Byte Word

Address (n) Data (n) Data (n + 15)

Data (n +1)

24VL024H

7.0 ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write

cycle, this can be used to determine when the cycle is

complete (this feature can be used to maximize bus

throughput). Once the Stop condition for a Write

comma nd has been is sued from the master , the device

initiate s the internall y-timed write cycle and ACK polling

can be initiated immediately. This involves the master

sending a Start condition followed by the control byte

for a Write command (R/W = 0). If the device is still

busy wi th t he write cycl e, no ACK wil l be re turned. If no

ACK is returned, the Start bit and control byte must be

re-sent. If the cycle is complete, the device will return

the ACK and the mast er can then pro ceed with the next

Read or Write command. See Figure 7-1 for a flow

diagram of this operation.

FIGURE 7-1: ACKNOWLEDGE POLLING

FLOW

Send

Wri te Co mm an d

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

Operation

Yes

24VL024H

8.0 READ OPERATIONS

Read operations are initiated in the same way as write

operations, with the exception that the R/W bit of the

slave address is set to ‘1’. There are three basic types

of read operat ions: current address read , rand om rea d

and sequential read.

8.1 Current Address Read

The 24VL0 24H co ntains an addres s count er that main-

tains the address of the last word accessed, internally

incremented by one. Therefore, if the previous read

access was to address n, the next current ad dress read

operatio n wou ld acc ess dat a f rom add ress n + 1. U pon

receipt of the slave address with the R/W bit set to ‘1’,

the 24VL024H issues an acknowledge and transmits

the 8-bit data word. The master will not acknowledge

the transfer , but do es generate a S top condition and the

24VL024H discontinues transmission (Figure 8-1).

8.2 Random Read

Random read operations allow the master to access

any memory location in a random manner. To perform

this typ e of re ad ope ratio n, the word add res s mus t firs t

be set. This is done b y sendi ng the word address to the

24VL024H as part of a write operation.

Once the word address is s ent, the master ge nerates a

Start condition following the acknowledge. This

terminates the write operation, but not before the

internal Address Pointer is set. Th e mast er then i ssues

the control byte again but with the R/W bit se t to a ‘ 1’.

The 24VL024H will then issue an acknowledge and

transmits the eight-bit data word. The master will not

acknowledge the transfer, but does generate a Stop

condition and the 24VL024H discont inues transmission

(Fig ure 8-2 ). After this comm and, th e interna l addre ss

counter will point to the address location following the

one that was jus t read.

8.3 Sequentia l Read

Sequential reads are initiated in the same way as a

random rea d ex ce pt that af ter th e 24VL024H tran sm its

the first data byte, the master issues an acknowledge

as opposed to a Stop condition in a random read. This

dire cts t h e 24V L 0 24H t o tr an s mi t th e n ex t se qu ent i al ly

addressed 8-bit word (Figure 8-3).

To provide sequential reads, the 24VL024H contains

an internal Address Pointer which is incremented by

one at the completion of each operation. This Address

Pointer al lows the entire me mory contents to b e serially

read during one operation. The internal Address

Pointer will automatically roll over from address FFh to

address 00h.

FIGURE 8-1: CURRENT ADDRESS READ

Bus Acti vity

Master

SDA Line

Bus Acti vity

Control

Byte

TData

24VL024H

FIGURE 8-2: RANDOM READ

FIGU RE 8-3 : SEQU ENT I AL REA D

S P

Bus Acti vity

Master

SDA Line

Bus Acti vity

Control

Byte

Word

Address (n) Control

Byte

TData (n)

Bus Activity

Master

SDA Line

Bus Activity

Control

Byte Data (n) Data (n + 1) Data (n + 2) Data (n + X)

24VL024H

9.0 PACKAGING INFORMATION

9.1 Package Marking Information

XXXXXXXX

T/XXXNNN

YYWW

8-Lead PDIP (300 mil) Example:

8-Lead SOIC (3.90 mm) Example:

XXXXXXXT

XXXXYYWW

NNN

8-Lead TS SOP Example:

24VL024H

P 112F

0821

24VL24H

SN 0821

12F

8-Lead MSOP Example:

XXXX

TYWW

NNN

V24H

821

12F

4V24H

82112F

XXXXXT

YWWNNN

8-Lead 2x3 TDFN Example:

AF3

821

XXX

YWW

24VL024H

Legend: XX...X Part number or part number code

T Temperature (I, E)

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week c ode (week of Janu ary 1 is week ‘01’)

NNN Alphanumeric traceability code (2 characters for small packages)

Pb-free JEDEC designator for Matte Tin (Sn)

Note: For very small packages with no room for the Pb-free JEDEC designator

, the marking will only appear on the outer carton or reel label.

Note: In the event the ful l Micro chip p ar t numbe r canno t be marke d on one li ne, it w ill

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

Note: Please visit www.microchip.com/Pbfree for the latest information on Pb-free conversion.

*Standard OTP marking consists of Microchip part number, year code, week code, and traceability code.

24VL024H

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 +%&,&!&

- '!!#.#&"#'#%!&"!!#%!&"!!!&$#/!#

 '!#&.0

1,21!'!&$& "!**&"&&!

 3&'!&"&4#*!(!!&4%&&#&

&&255***''54

6&! 7,8.

'!9'&! 7 7: ;

7"')%! 7 <

&  1,

&&  = = 

##44!!   - 

1!&&   = =

"#&"#>#& .  - -

##4>#& .   <

: 9&  -< -? 

&& 9  - 

9#4!!  <  

69#>#& )  ? 

9*9#>#& )  < 

: *+ 1 = = -

NOTE 1

  * ,<1

24VL024H

 ! ""#$%& !'



  !"#$%&"' ()"&'"!&)&#*&&&#

 +%&,&!&

- '!!#.#&"#'#%!&"!!#%!&"!!!&$#''!#

 '!#&.0

1,2 1!'!&$& "!**&"&&!

.32 %'!("!"*&"&&(%%'&"!!

&&255***''54

6&! 99..

'!9'&! 7 7: ;

7"')%! 7 <

&  1,

: 8&  = = 

##44!!   = =

&#%%+  = 

: >#& . ?1,

##4>#& . -1,

: 9&  1,

,'%@&A   = 

3&9& 9  = 

3&& 9 .3

3& IB = <B

9#4!!   = 

9#>#& ) - = 

#%& DB = B

#%&1&&' EB = B

NOTE 1

12 3

  * ,1

24VL024H

 ! ""#$%& !'

&&255***''54

24VL024H

() )"* ! (+%+( !



  !"#$%&"' ()"&'"!&)&#*&&&#

 '!!#.#&"#'#%!&"!!#%!&"!!!&$#''!#

- '!#&.0

1,2 1!'!&$& "!**&"&&!

.32 %'!("!"*&"&&(%%'&"!!

&&255***''54

6&! 99..

'!9'&! 7 7: ;

7"')%! 7 <

&  ?1,

: 8&  = = 

##44!!  <  

&#%%   = 

: >#& . ?1,

##4>#& . -  

##49&   - -

3&9& 9  ? 

3&& 9 .3

3& IB = <B

9#4!!   = 

9#>#& )  = -

NOTE 1

L1 L

  * ,<?1

24VL024H

," !*-, , !



  !"#$%&"' ()"&'"!&)&#*&&&#

- '!#&.0

1,2 1!'!&$& "!**&"&&!

.32 %'!("!"*&"&&(%%'&"!!

&&255***''54

6&! 99..

'!9'&! 7 7: ;

7"')%! 7 <

&  ?1,

: 8&  = = 

##44!!   < 

&#%%   = 

: >#& . 1,

##4>#& . -1,

: 9&  -1,

3&9& 9  ? <

3&& 9 .3

3& B = <B

9#4!!  < = -

9#>#& )  = 

NOTE 1

L1 L

  * ,1

24VL024H

.$*-,/00%12(.

&&255***''54

24VL024H

.$*-,/00%12(.

&&255***''54

24VL024H

REVISION HISTORY

Revision A (10/2008)

Original release.

24VL024H

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Microc hip pro vides onl ine s upport v ia our W WW site at

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24AA024H/24LC024H

READER RESP ONSE

It is ou r intentio n to provide you w it h th e b es t do cument ation po ss ib le to ensure suc c es sfu l u se of y ou r M ic roc hip prod-

uct. If you wi sh to prov ide you r comment s on org aniza tion, clar ity, subj ect matte r , and ways i n which o ur docum entatio n

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RE: Reader Response Total Pages Sent ________

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DS22109A24VL024H

1. What are the best featur es of t his document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

24VL024H

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Device: 24VL024H = 1.5V, 2 Kbit Addressable Serial EEPROM

24VL024HT = 1.5V, 2 Kbit Addressable Serial EEPROM

(Ta pe and Reel)

Temperature Range: = -20°C to +85°C

Package: P = Plastic DIP, (300 mil Body), 8-lead

SN = Plastic SOIC, (3.90 mm Body)

ST = TSSOP, (4.4 mm Body), 8-lead

MS = MSOP, (Plastic Micro Small Outline), 8-lead

MNY(1) = TDFN, (2x3x0.75 mm Body), 8-lead

PART NO. X/XX

PackageTemperature

Range

Device

Examples:

a) 24VL02 4H/P: 1.5V, PDIP Package.

b) 24VL02 4H/SN: 1.5V, SOIC Package.

c) 24VL024HT/ST: 1.5V, TSSOP Package,

Tape and Reel

d) 24VL02 4HT/MNY: 1. 5V, T DFN P ackage,

Tape and Reel

Note 1: “Y” indicates a Nickel Palladium Gold (NiPdAu) finish.

24VL024H

NOTES:

Information contained in this publication regarding device

applications a nd t he like is pro vid ed only f or yo ur convenience

and may be su persed ed by updates . I t is your res ponsibil it y to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICm icro,

PICSTA RT, rfPI C, SmartShunt and UNI/O are registered

trademarks of Microchip Technology Inc orporated in the

U.S.A. and other countries.

FilterLab, Linear Active Thermistor, MXDEV, MXLAB,

SEEV AL, SmartSensor and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, In-Circuit Serial

Prog ra m ming, IC SP, ICE P I C , Mi n d i , M iW i , M PASM, M P L A B

Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,

PICDEM.net, PICtail , PIC32 logo, PowerCal, PowerInfo,

PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total

Endurance, WiperLock and ZENA are trademarks of

Microchip Technology Incorporat ed in the U.S.A. and other

countries.

SQTP is a service mark of Microchip T echnology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on t he market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our

products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such act s

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopp ing

devices, Serial EEPROMs, microperiph erals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

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