High Speed, Dual, 4 A MOSFET Driver
with Thermal Protection
ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635
Rev. A
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FEATURES
Industry-standard-compatible pinout
High current drive capability
Precise threshold shutdown comparator
UVLO with hysteresis
Overtemperature warning signal
Overtemperature shutdown
3.3 V-compatible inputs
10 ns typical rise time and fall time @ 2.2 nF load
Matched propagation delays between channels
Fast propagation delay
9.5 V to 18 V supply voltage (ADP3633/ADP3634/ADP3635)
4.5 V to 18 V supply voltage (ADP3623/ADP3624/ADP3625)
Parallelable dual outputs
Rated from −40°C to +85°C ambient temperature
Thermally enhanced packages, 8-lead SOIC_N_EP and
8-lead MINI_SO_EP
APPLICATIONS
AC-to-dc switch mode power supplies
DC-to-dc power supplies
Synchronous rectification
Motor drives
GENERAL DESCRIPTION
The ADP362x/ADP363x is a family of high current and dual high
speed drivers, capable of driving two independent N-channel
power MOSFETs. The family uses the industry-standard foot-
print but adds high speed switching performance and improved
system reliability.
The family has an internal temperature sensor and provides
two levels of overtemperature protection, an overtemperature
warning, and an overtemperature shutdown at extreme junction
temperatures.
The SD function, generated from a precise internal comparator,
provides fast system enable or shutdown. This feature allows
redundant overvoltage protection, complementing the protec-
tion inside the main controller device, or provides safe system
shutdown in the event of an overtemperature warning.
The wide input voltage range allows the driver to be compatible
with both analog and digital PWM controllers.
Digital power controllers are supplied from a low voltage
supply, and the driver is supplied from a higher voltage supply.
The ADP362x/ADP363x family adds UVLO and hysteresis
functions, allowing safe startup and shutdown of the higher
voltage supply when used with low voltage digital controllers.
The device family is available in thermally enhanced SOIC_N_EP
and MINI_SO_EP packaging to maximize high frequency and
current switching in a small printed circuit board (PCB) area.
FUNCTIONAL BLOCK DIAGRAM
18
27
36
45
OVERTEMPERATURE
PROTECTION
NONINVERTING
INA,
INA
PGND
INB,
INB
SD
OUTA
VDD
OUTB
OTW
V
DD
V
DD
INVERTING
NONINVERTING
INVERTING
UVLO
V
EN
08132-101
ADP3623/ADP3624/ADP3625
ADP3633/ADP3634/ADP3635
Figure 1.
ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635
Rev. A | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing %JBHSBNT ................................................................ 4
Absolute Maximum Ratings ............................................................ 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 9
Test Circ uit ...................................................................................... 11
Theory of Operation ...................................................................... 12
Input Drive Requirements (INA, INA, INB,
INB, and SD) .. 12
Low-Side Drivers (OUTA, OUTB) .......................................... 12
Shutdown (SD) Function .......................................................... 12
Overtemperature Protections ................................................... 12
Supply Capacitor Selection ....................................................... 13
PCB Layout Considerations ...................................................... 13
Parallel Operation ...................................................................... 13
Thermal Considerations ............................................................ 14
Outline Dimensions ....................................................................... 15
Ordering Guide .......................................................................... 16
REVISION HISTORY
7/09—Rev. 0 to Rev. A
Added ADP3623, ADP3625, ADP3633, and
ADP3635 .............................................................................. Universal
Changes to Features Section, General Description Section,
and Figure 1 ....................................................................................... 1
Changes to Table 1 ............................................................................ 3
Added Figure 4; Renumbered Sequentially .................................. 4
Added Figure 7 .................................................................................. 7
Added Table 3; Renumbered Sequentially .................................... 7
Added Figure 9 and Table 5 ............................................................. 8
Changes to Figure 10 ........................................................................ 9
Changes to Figure 16 to Figure 19 Captions ............................... 10
Changes to Figure 20 ...................................................................... 11
Changes to Figure 21, Input Drive Requirements (INA,
INA, INB,
5/09—Revision 0: Initial Version
INB, and SD) Section, and Figure 22 ........................ 12
Changes to Figure 23 and Parallel Operation Section ............... 13
Changes to Design Example Section ........................................... 14
Changes to Ordering Guide .......................................................... 16
ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635
Rev. A | Page 3 of 16
SPECIFICATIONS
VDD = 12 V, TJ = −40°C to +125°C, unless otherwise noted.1
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
SUPPLY
Supply Voltage Range VDD ADP3633/ADP3634/ADP3635 9.5 18 V
VDD ADP3623/ADP3624/ADP3625 4.5 18 V
Supply Current IDD No switching, INA, INA, INB, and
INB disabled 1.2 3 mA
Standby Current ISBY SD = 5 V 1.2 3 mA
UVLO
Turn-On Threshold Voltage VUVLO_ON VDD rising, TA = 25°C, ADP3633/ADP3634/ADP3635 8.0 8.7 9.5 V
VUVLO_ON VDD rising, TA = 25°C, ADP3623/ADP3624/ADP3625 3.8 4.2 4.5 V
Turn-Off Threshold Voltage VUVLO_OFF VDD falling, TA = 25°C, ADP3633/ADP3634/ADP3635 7.0 7.7 8.5 V
VUVLO_OFF VDD falling, TA = 25°C, ADP3623/ADP3624/ADP3625 3.5 3.9 4.3 V
Hysteresis ADP3633/ADP3634/ADP3635 1.0 V
ADP3623/ADP3624/ADP3625 0.3 V
DIGITAL INPUTS (INA, INA, INB,
INB, SD)
Input Voltage High VIH 2.0 V
Input Voltage Low VIL 0.8 V
Input Current IIN 0 V < VIN < VDD −20 +20 µA
SD Threshold High V
SD_H
1.19 1.28 1.38 V
VSD_H TA = 25°C 1.21 1.28 1.35 V
SD Threshold Low VSD_L TA = 25°C 0.95 1.0 1.05 V
SD Hysteresis VSD_HYST TA = 25°C 240 280 320 mV
Internal Pull-Up/Pull-Down Current 6 µA
OUTPUTS (OUTA, OUTB)
Output Resistance, Unbiased VDD = PGND 80 kΩ
Peak Source Current See Figure 20 4 A
Peak Sink Current See Figure 20 −4 A
SWITCHING TIME
OUTA, OUTB Rise Time tRISE CLOAD = 2.2 nF, see Figure 3 and Figure 4 10 25 ns
OUTA, OUTB Fall Time t
FALL
C
LOAD
= 2.2 nF, see Figure 3 and Figure 4 10 25 ns
OUTA, OUTB Rising Propagation Delay tD1 CLOAD = 2.2 nF, see Figure 3 and Figure 4 14 30 ns
OUTA, OUTB Falling Propagation Delay tD2 CLOAD = 2.2 nF, see Figure 3 and Figure 4 22 35 ns
SD Propagation Delay Low tdL_SD See Figure 2 32 45 ns
SD Propagation Delay High tdH_SD See Figure 2 48 75 ns
Delay Matching Between Channels 2 ns
OVERTEMPERATURE PROTECTION
Overtemperature Warning Threshold TW See Figure 6 120 135 150 °C
Overtemperature Shutdown Threshold T
SD
See Figure 6 150 165 180 °C
Temperature Hysteresis for Shutdown THYS_SD See Figure 6 30 °C
Temperature Hysteresis for Warning THYS_W See Figure 6 10 °C
Overtemperature Warning Low VOTW_OL Open drain, −500 µA 0.4 V
1 All limits at temperature extremes guaranteed via correlation using standard statistical quality control (SQC) methods.
ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635
Rev. A | Page 4 of 16
TIMING %*"(3".4
SD
OUTA,
OUTB
90%
tdL_SD
10%
tdH_SD
08132-002
Figure 2. Shutdown Timing Diagram
INA,
INB
OUTA,
OUTB
tD1 tRISE
10%
90%
10%
90%
V
IH
V
IL
tD2 tFALL
08132-003
Figure 3. Output Timing Diagram (Noninverting)
INA,
INB
OUTA,
OUTB
tD1 tRISE
10%
90%
10%
90%
V
IL
V
IH
tD2 tFALL
08132-003
Figure 4. Output Timing Diagram (Inverting)
NORMAL OPERATIONUVLO MODE
OUTPUTS DISABLE D
V
DD
V
UVLO_ON
VUVLO_OFF
UVLO MODE
OUTPUTS DISABLE D
08132-005
Figure 5. UVLO Function
ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635
Rev. A | Page 5 of 16
OT SHUTDOWN
OUTPUTS
DISABLED
NORMAL OPERATION NORMAL OPERATION
TJ
TW
TSD
TSD
–
T
HYS_SD
T
W
–
T
HYS_W
OT WARNING
OUTPUTS
ENABLED
OT WARNING
OUTPUTS
ENABLED
OTW
08132-006
Figure 6. Overtemperature Warning and Shutdown
ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635
Rev. A | Page 6 of 16
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
VDD −0.3 V to +20 V
OUTA, OUTB
DC −0.3 V to VDD + 0.3 V
<200 ns −2 V to VDD + 0.3 V
INA, INA, INB, −0.3 V to VDD + 0.3 V
INB, and SD
ESD
Human Body Model (HBM) 3.5 kV
Field Induced Charged Device Model
(FICDM)
SOIC_N_EP 1.5 kV
MINI_SO_EP 1.0 kV
θ
JA
, JEDEC 4-Layer Board
SOIC_N_EP1 59°C/W
MINI_SO_EP1 43°C/W
Junction Temperature Range −40°C to +150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature
Soldering (10 sec) 300°C
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 260°C
1 θJA is measured per JEDEC standards, JESD51-2, JESD51-5, and JESD51-7, as
appropriate with the exposed pad soldered to the PCB.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635
Rev. A | Page 7 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SD 1
INA2
PGND 3
INB 4
OTW
8
OUTA
7
VDD
6
OUTB
5
ADP3623/
ADP3633
TOP VIEW
(Not t o Scale)
NOTES
1. THE EXPOSED PAD O F THE PACKAGE IS NOT DI RE CT LY
CONNECTED TO ANY PIN OF THEPACKAGE , BUT I T IS
ELECTRICALLY AND T HE RM ALLY CO NNE CTED TO THE DIE
SUBST RATE, WHICH I S THE GROUND OF THE DEVICE.
08132-008
Figure 7. ADP3623/ADP3633 Pin Configuration
Table 3. ADP3623/ADP3633 Pin Function Descriptions
Pin No. Mnemonic Description
1 SD Output Shutdown. When high, this pin disables normal operation, forcing OUTA and OUTB low.
2 INA Inverting Input Pin for Channel A Gate Driver.
3 PGND Ground. This pin should be closely connected to the source of the power MOSFET.
4 INB Inverting Input Pin for Channel B Gate Driver.
5 OUTB Output Pin for Channel B Gate Driver.
6 VDD Power Supply Voltage. Bypass this pin to PGND with a ~1 µF to 5 µF ceramic capacitor.
7 OUTA Output Pin for Channel A Gate Driver.
8 OTW Overtemperature Warning Flag. Open drain, active low.
SD 1
INA2
PGND 3
INB 4
OTW
8
OUTA
7
VDD
6
OUTB
5
ADP3624/
ADP3634
TOP VIEW
(Not t o Scale)
NOTES
1. THE EXPOSED PAD O F THE PACKAGE IS NOT DI RE CT LY
CONNECTED TO ANY PIN OF THEPACKAGE , BUT I T IS
ELE CTRICALLY AND THE RM ALLY CO NNE CTED TO THE DIE
SUBST RATE, WHICH I S THE GROUND OF THE DEVICE.
08132-001
Figure 8. ADP3624/ADP3634 Pin Configuration
Table 4. ADP3624/ADP3634 Pin Function Descriptions
Pin No. Mnemonic Description
1 SD Output Shutdown. When high, this pin disables normal operation, forcing OUTA and OUTB low.
2 INA Input Pin for Channel A Gate Driver.
3 PGND Ground. This pin should be closely connected to the source of the power MOSFET.
4 INB Input Pin for Channel B Gate Driver.
5 OUTB Output Pin for Channel B Gate Driver.
6 VDD Power Supply Voltage. Bypass this pin to PGND with a ~1 µF to 5 µF ceramic capacitor.
7 OUTA Output Pin for Channel A Gate Driver.
8 OTW Overtemperature Warning Flag. Open drain, active low.
ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635
Rev. A | Page 8 of 16
SD 1
INA2
PGND 3
INB 4
OTW
8
OUTA
7
VDD
6
OUTB
5
ADP3625/
ADP3635
TOP VIEW
(Not t o Scale)
NOTES
1. THE EXPOSED PAD O F THE PACKAGE IS NOT DI RE CT LY
CONNECTED TO ANY PIN OF THEPACKAGE , BUT I T IS
ELE CTRICALLY AND THE RM ALLY CO NNE CTED TO THE DIE
SUBST RATE, WHICH I S THE GROUND OF THE DEVICE.
08132-009
Figure 9. ADP3625/ADP3635 Pin Configuration
Table 5. ADP3625/ADP3635 Pin Function Descriptions
Pin No. Mnemonic Description
1 SD Output Shutdown. When high, this pin disables normal operation, forcing OUTA and OUTB low.
2 INA Inverting Input Pin for Channel A Gate Driver.
3 PGND Ground. This pin should be closely connected to the source of the power MOSFET.
4 INB Input Pin for Channel B Gate Driver.
5 OUTB Output Pin for Channel B Gate Driver.
6 VDD Power Supply Voltage. Bypass this pin to PGND with a ~1 µF to 5 µF ceramic capacitor.
7 OUTA Output Pin for Channel A Gate Driver.
8 OTW Overtemperature Warning Flag. Open drain, active low.
ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635
Rev. A | Page 9 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
3
4
5
6
7
8
9
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
UVLO (V)
VUVLO_ON
VUVLO_OFF
VUVLO_ON
VUVLO_OFF
ADP3633/ADP3634/ADP3635
ADP3623/ADP3624/ADP3625
08132-022
Figure 10. UVLO vs. Temperature
0
2
4
6
8
10
12
14
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
tFALL
tRISE
TIME (n s)
08132-010
Figure 11. Rise and Fall Times vs. Temperature
0
10
20
30
40
50
60
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
TIME (n s)
VDD = 12V tdH_SD
tdL_SD
tD2
tD1
08132-011
Figure 12. Propagation Delay vs. Temperature
0
5
10
15
20
25
0 5 10 15 20
V
DD
(V)
TIME (n s)
t
FALL
t
RISE
08132-012
Figure 13. Rise and Fall Times vs. VDD
0
10
20
30
40
50
60
70
0 5 10 15 20
t
dL_SD
t
D2
t
D1
t
dH_SD
V
DD
(V)
TIME (n s)
08132-013
Figure 14. Propagation Delay vs. VDD
0
200
400
600
800
1000
1200
1400
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
SHUT DOWN THRE S HOLD (mV )
SD THRESHOLD HYSTERESIS
SD T HRE S HOLD HIGH
SD T HRE S HOLD LOW
08132-014
Figure 15. Shutdown Threshold vs. Temperature
ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635
Rev. A | Page 10 of 16
08132-023
1
2
OUTA/OUTB
INA/INB
V
DD
= 12V
TIME = 20ns/DIV
Figure 16. Typical Rise Propagation Delay (Noninverting)
08132-024
1
2
V
DD
= 12V
TIME = 20ns/DIV
OUTA/OUTB
INA/INB
Figure 17. Typical Fall Propagation Delay (Noninverting)
08132-025
1
2
V
DD
= 12V
TIME = 20ns/DIV
OUTA/OUTB
INA/INB
Figure 18. Typical Rise Time (Noninverting)
08132-026
1
2
V
DD
= 12V
TIME = 20ns/DIV
OUTA/OUTB
INA/INB
Figure 19. Typical Fall Time (Noninverting)
ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635
Rev. A | Page 11 of 16
TEST CIRCUIT
V
DD
SD OTW
1
3
8
7
6
5
2
4
CLOAD
100nF
CERAMIC
4.7µF
CERAMIC
SCOPE
PROBE
08132-007
ADP3623/ADP3624/ADP3625
ADP3633/ADP3634/ADP3635
VDDPGND
OUTA
OUTB
B
NONINVERTING
INVERTING
A
NONINVERTING
INVERTING
INA,
INA
INB,
INB
Figure 20. Test Circuit
ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635
Rev. A | Page 12 of 16
THEORY OF OPERATION
The ADP362x/ADP363x family of dual drivers is optimized for
driving two independent enhancement N-channel MOSFETs or
insulated gate bipolar transistors (IGBTs) in high switching
frequency applications.
These applications require high speed, fast rise and fall times, as
well as short propagation delays. The capacitive nature of the
aforementioned gated devices requires high peak current
capability as well.
VDD
V
DD
PGND
OUTA
OUTB
SD OTW
1
3
8
7
6
5
2
4
V
DS
V
DS
08132-017
ADP3623/ADP3624/ADP3625
ADP3633/ADP3634/ADP3635
B
NONINVERTING
INVERTING
A
NONINVERTING
INVERTING
INA,
INA
INB,
INB
Figure 21. Typical Application Circuit
INPUT DRIVE REQUIREMENTS (INA, INA, INB,
The ADP362x/ADP363x family inputs are designed to meet the
requirements of modern digital power controllers; the signals
are compatible with 3.3 V logic levels. At the same time, the
input structure allows for input voltages as high as VDD.
The signals applied to the inputs (INA,
INB,
AND SD)
INA, INB, and
The SD input has a precision comparator with hysteresis and is
therefore suitable for slow changing signals (such as a scaled
down output voltage); see the
INB)
should have steep and clean fronts. It is not recommended to
apply slow changing signals to drive these inputs because they
can result in multiple switching when the thresholds are
crossed, causing damage to the power MOSFET or IGBT.
An internal pull-down resistor is present at the input, which
guarantees that the power device is off in the event that the
input is left floating.
Shutdown (SD) Function section
for more details on this comparator.
LOW-SIDE DRIVERS (OUTA, OUTB)
The ADP362x/ADP363x family of dual drivers is designed to
drive ground referenced N-channel MOSFETs. The bias is
internally connected to the VDD supply and PGND.
When the ADP362x/ADP363x family is disabled, both low-side
gates are held low. An internal impedance is present between
the OUTA/OUTB pins and GND, even when VDD is not present;
this feature ensures that the power MOSFET is normally off
when bias voltage is not present.
When interfacing the ADP362x/ADP363x family to external
MOSFETs, the designer should consider ways to make a robust
design that minimizes stresses on both the driver and the
MOSFETs. These stresses include exceeding the short time
duration voltage ratings on the OUTA and OUTB pins, as well
as the external MOSFET.
Power MOSFETs are usually selected to have a low on resistance
to minimize conduction losses, which usually implies a large
input gate capacitance and gate charge.
SHUTDOWN (SD) FUNCTION
The ADP362x/ADP363x family features an advanced shutdown
function, with accurate threshold and hysteresis.
The SD signal is an active high signal. An internal pull-up is
present on this pin and, therefore, it is necessary to pull down
the pin externally for drivers to operate normally.
In some power systems, it is sometimes necessary to provide an
additional overvoltage protection (OVP) or overcurrent protection
(OCP) shutdown signal to turn off the power devices (MOSFETs
or IGBTs) in case of failure of the main controller.
An accurate internal reference is used for the SD comparator so
that it can be used to detect OVP or OCP fault conditions.
AC
INPUT
DC
OUTPUT
+
–
OUTA PGND
VEN
SD
08132-018
ADP3623/ADP3624/ADP3625
ADP3633/ADP3634/ADP3635
Figure 22. Shutdown Function Used for Redundant OVP
OVERTEMPERATURE PROTECTIONS
The ADP362x/ADP363x family provides two levels of
overtemperature protections:
• Overtemperature warning (OTW)
• Overtemperature shutdown
The overtemperature warning is an open-drain logic signal and
is active low. In normal operation, when no thermal warning is
present, the signal is high, whereas when the warning threshold
is crossed, the signal is pulled low.
ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635
Rev. A | Page 13 of 16
ADP1043A
3.3V
VDD
PGND
PGND
FLAGIN
VDD
OTW
OTW
08132-019
ADP3623/ADP3624/ADP3625/
ADP3633/ADP3634/ADP3635
ADP3623/ADP3624/ADP3625/
ADP3633/ADP3634/ADP3635
Figure 23. OTW
The
Signaling Scheme Example
OTW
The overtemperature shutdown turns off the device to protect it
in the event that the die temperature exceeds the absolute maxi-
mum limit in
open-drain configuration allows connection of
multiple devices to the same warning bus in a wire-O R’e d
configuration, as shown in Figure 23.
Table 2.
SUPPLY CAPACITOR SELECTION
For the supply input (VDD) of the ADP362x/ADP363x family, a
local bypass capacitor is recommended to reduce the noise and
to supply some of the peak currents that are drawn.
An improper decoupling can dramatically increase the rise
times, cause excessive resonance on the OUTA and OUTB pins,
and, in some extreme cases, even damage the device, due to
inductive overvoltage on the VDD or OUTA/OUTB pins.
The minimum capacitance required is determined by the size
of the gate capacitances being driven, but as a general rule, a
4.7 µF, low ESR capacitor should be used. Multilayer ceramic
chip (MLCC) capacitors provide the best combination of low
ESR and small size. Use a smaller ceramic capacitor (100 nF)
with a better high frequency characteristic in parallel to the
main capacitor to further reduce noise.
Keep the ceramic capacitor as close as possible to the ADP362x/
ADP363x device, and minimize the length of the traces going
from the capacitor to the power pins of the device.
PCB LAYOUT CONSIDERATIONS
Use the following general guidelines when designing printed
circuit boards (PCBs):
• Trace out the high current paths and use short, wide
(>40 mil) traces to make these connections.
• Minimize trace inductance between the OUTA and OUTB
outputs and MOSFET gates.
• Connect the PGND pin of the ADP362x/ADP363x device
as closely as possible to the source of the MOSFETs.
• Place the VDD bypass capacitor as close as possible to the
VDD and PGND pins.
• Use vias to other layers, when possible, to maximize
thermal conduction away from the IC.
Figure 24 shows an example of the typical layout based on the
preceding guidelines.
08132-027
Figure 24. External Component Placement Example
Note that the exposed pad of the package is not directly
connected to any pin of the package, but it is electrically and
thermally connected to the die substrate, which is the ground of
the device.
PARALLEL OPERATION
The two driver channels present in the ADP3623/ADP3633 or
ADP3624/ADP3634 devices can be combined to operate in
parallel to increase drive capability and minimize power
dissipation in the driver.
The connection scheme for the ADP3624/ADP3634 devices is
shown in Figure 25. In this configuration, INA and INB are
connected together, and OUTA and OUTB are connected
together.
Particular attention must be paid to the layout in this case to
optimize load sharing between the two drivers.
INA
VDD
VDD
PGND
ADP3624/ADP3634
OUTA
OUTBINB
SD OTW
1
3
8
7
6
5
A
B
2
4
VDS
08132-021
Figure 25. Parallel Operation
ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635
Rev. A | Page 14 of 16
THERMAL CONSIDERATIONS
When designing a power MOSFET gate drive, the maximum
power dissipation in the driver must be considered to avoid
exceeding maximum junction temperature.
Data on package thermal resistance is provided in Table 2 to
help the designer in this task.
There are several equally important aspects that must be
considered.
• Gate charge of the power MOSFET being driven
• Bias voltage value used to power the driver
• Maximum switching frequency of operation
• Value of external gate resistance
• Maximum ambient (and PCB) temperature
• Type of package
All of these factors influence and limit the maximum allowable
power dissipated in the driver.
The gate of a power MOSFET has a nonlinear capacitance
characteristic. For this reason, although the input capacitance
is usually reported in the MOSFET data sheet as CISS, it is not
useful to calculate power losses.
The total gate charge necessary to turn on a power MOSFET
device is usually reported on the device data sheet under QG.
This parameter varies from a few nanocoulombs (nC) to several
hundreds of nC, and is specified at a specific VGS value (10 V
or 4.5 V).
The power necessary to charge and then discharge the gate of a
power MOSFET can be calculated as:
PGATE = VGS × QG × fSW
where:
VGS is the bias voltage powering the driver (VDD).
QG is the total gate charge.
fSW is the maximum switching frequency.
The power dissipated for each gate (PGATE) still needs to be multip-
lied by the number of drivers (in this case, 1 or 2) being used
in each package, and it represents the total power dissipated in
charging and discharging the gates of the power MOSFETs.
Not all of this power is dissipated in the gate driver because part
of it is actually dissipated in the external gate resistor, RG. The
larger the external gate resistor is, the smaller the amount of
power that is dissipated in the gate driver.
In modern switching power applications, the value of the gate
resistor is kept at a minimum to increase switching speed and
minimize switching losses.
In all practical applications where the external resistor is in the
order of a few ohms, the contribution of the external resistor
can be neglected, and the extra loss is assumed in the driver,
providing a good guard band to the power loss calculations.
In addition to the gate charge losses, there are also dc bias
losses, due to the bias current of the driver. This current is
present regardless of the switching.
PDC = VDD × IDD
The total estimated loss is the sum of PDC and PGATE.
PLOSS = PDC + (n × PGATE)
where n is the number of gates driven.
When the total power loss is calculated, the temperature
increase can be calculated as
ΔTJ = PLOSS × θJA
Design Example
For example, consider driving two IRFS4310Z MOSFETs with a
VDD of 12 V at a switching frequency of 300 kHz, using an
ADP3624 in the SOIC_N_EP package.
The maximum PCB temperature considered for this design is 85°C.
From the MOSFET data sheet, the total gate charge is QG = 120 nC.
PGATE = 12 V × 120 nC × 300 kHz = 432 mW
PDC = 12 V × 1.2 mA = 14.4 mW
PLOSS = 14.4 mW + (2 × 432 mW) = 878.4 mW
From the MOSFET data sheet, the SOIC_N_EP thermal
resistance is 59°C/W.
ΔTJ = 878.4 mW × 59°C/W = 51.8°C
TJ = TA + ΔTJ = 136.8°C ≤ TJMAX
This estimated junction temperature does not factor in the
power dissipated in the external gate resistor and, therefore,
provides a certain guard band.
If a lower junction temperature is required by the design,
the MINI_SO_EP package can be used, which provides a
thermal resistance of 43°C/W, so that the maximum junction
temperature is
ΔTJ = 878.4 mW × 43°C/W = 37.7°C
TJ = TA + ΔTJ = 122.7°C ≤ TJMAX
Other options to reduce power dissipation in the driver include
reducing the value of the VDD bias voltage, reducing switching fre-
quency, and choosing a power MOSFET with smaller gate charge.
ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635
Rev. A | Page 15 of 16
OUTLINE DIMENSIONS
COMPLIANT TO JE DE C S TANDARDS MS-012-AA
CONTROLLING DIMENSIONSARE I N M ILL IMET E R; INCH DIME NS IONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REF E RE NCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
072808-A
0.25 ( 0.0098)
0.17 ( 0.0067)
1.27 ( 0.050)
0.40 ( 0.016)
0.50 ( 0.020)
0.25 ( 0.010) 45°
8°
0°
1.75 ( 0.069)
1.35 ( 0.053) 1.65 ( 0.065)
1.25 ( 0.049)
SEATING
PLANE
8 5
41
5.00 ( 0.197)
4.90 ( 0.193)
4.80 ( 0.189)
4.00 ( 0.157)
3.90 ( 0.154)
3.80 ( 0.150)
1.27 ( 0.05)
BSC
6.20 ( 0.244)
6.00 ( 0.236)
5.80 ( 0.228)
0.51 ( 0.020)
0.31 ( 0.012)
COPLANARITY
0.10
TOP VIEW
2.29 (0.090)
BOTTOM VIEW
(PINS UP)
2.29 (0.090)
0.10 ( 0.004)
MAX
FOR PROPE R CONNECTION O F
THE EXPOSED PAD, REFER TO
THE P IN CONFIGURAT ION AND
FUNCTION DE S CRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 26. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP]
Narrow Body (RD-8-1)
Dimensions shown in millimeters and (inches)
071008-A
COMPLIANT TO JE DE C S TANDARDS MO-187- AA- T
0.70
0.55
0.40
8°
0°
0.94
0.86
0.78
SEATING
PLANE
1.10 M AX
0.15
0.10
0.05
0.40
0.33
0.25
5.05
4.90
4.75
2.26
2.16
2.06
1.83
1.73
1.63
3.10
3.00
2.90
3.10
3.00
2.90
85
4
1
0.65 BS C 0.525 BSC
PI N 1
INDICATOR
COPLANARITY
0.10
0.23
0.18
0.13
TOP
VIEW
BOTTOM VIEW
EXPOSED
PAD
FOR PROPE R CONNECTION O F
THE EXPOSED PAD, REFER TO
THE P IN CONFIGURAT ION AND
FUNCTION DE S CRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 27. 8-Lead Mini Small Outline Package with Exposed Pad [MINI_SO_EP]
(RH-8-1)
Dimensions shown in millimeters
ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635
Rev. A | Page 16 of 16
ORDERING GUIDE
Model
UVLO
Option
Temperature
Range Package Description
Package
Option
Ordering
Quantity Branding
ADP3623ARDZ-RL1 4.5 V −40°C to +85°C 8-Lead Standard Small Outline Package
(SOIC_N_EP), 13“ Tape and Reel
RD-8-1 2,500
ADP3623ARHZ-RL1 4.5 V −40°C to +85°C 8-Lead Mini Small Outline Package (MINI_SO_EP),
13” Tape and Reel
RH-8-1 3,000 P3
ADP3624ARDZ1 4.5 V −40°C to +85°C
8-Lead Standard Small Outline Package
(SOIC_N_EP)
RD-8-1
ADP3624ARDZ-RL1 4.5 V −40°C to +85°C 8-Lead Standard Small Outline Package
(SOIC_N_EP), Tape Reel
RD-8-1 2,500
ADP3624ARHZ1 4.5 V −40°C to +85°C 8-Lead Mini Small Outline Package (MINI_SO_EP) RH-8-1 P4
ADP3624ARHZ-RL1 4.5 V −40°C to +85°C 8-Lead Mini Small Outline Package (MINI_SO_EP),
Tape Reel
RH-8-1 3,000 P4
ADP3625ARDZ-RL1 4.5 V −40°C to +85°C 8-Lead Standard Small Outline Package
(SOIC_N_EP), 13” Tape and Reel
RD-8-1 2,500
ADP3625ARHZ-RL1 4.5 V −40°C to +85°C 8-Lead Mini Small Outline Package (MINI_SO_EP),
13” Tape and Reel
RH-8-1 3,000 P5
ADP3633ARDZ-RL1 9.5 V −40°C to +85°C 8-Lead Standard Small Outline Package
(SOIC_N_EP), 13” Tape and Reel
RD-8-1 2,500
ADP3633ARHZ-RL1 9.5 V −40°C to +85°C 8-Lead Mini Small Outline Package (MINI_SO_EP),
13” Tape and Reel
RH-8-1 3,000 L3
ADP3634ARDZ1 9.5 V −40°C to +85°C
8-Lead Standard Small Outline Package
(SOIC_N_EP)
RD-8-1
ADP3634ARDZ-RL1 9.5 V −40°C to +85°C 8-Lead Standard Small Outline Package
(SOIC_N_EP), 13” Tape and Reel
RD-8-1 2,500
ADP3634ARHZ1 9.5 V −40°C to +85°C 8-Lead Mini Small Outline Package (MINI_SO_EP) RH-8-1 L4
ADP3634ARHZ-RL1 9.5 V −40°C to +85°C 8-Lead Mini Small Outline Package (MINI_SO_EP),
13” Tape and Reel
RH-8-1 3,000 L4
ADP3635ARDZ-RL1 9.5 V −40°C to +85°C 8-Lead Standard Small Outline Package
(SOIC_N_EP), 13” Tape and Reel
RD-8-1 2,500
ADP3635ARHZ-RL1 9.5 V −40°C to +85°C 8-Lead Mini Small Outline Package (MINI_SO_EP),
13” Tape and Reel
RH-8-1 3,000 L5
1 Z = RoHS Compliant Part.
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08132-0-7/09(A)
