LT3063
1
3063f
For more information www.linear.com/LT3063
Typical applicaTion
FeaTures DescripTion
45V VIN, Micropower,
Low Noise, 200mA LDO
with Output Discharge
The LT
®
3063 is a micropower, low dropout (LDO) linear
regulator that operates over a 1.6V to 45V supply range.
The device supplies 200mA of output current with a typi-
cal dropout voltage of 300mV. A single external capacitor
provides programmable low noise reference performance
and output soft-start functionality. The LT3063’s quiescent
current is merely 45μA and provides fast transient response
with a minimum 3.3μF output capacitor. In shutdown,
quiescent current is less than 3μA and the reference soft
start capacitor is reset.
The LT3063 features an NMOS pull-down that discharges
the output if SHDN or IN is driven low.
Internal protection circuitry includes reverse-battery protec-
tion, reverse-current protection, current limit with foldback
and thermal shutdown.
The LT3063 is available as an adjustable device with an
output voltage range from the 600mV reference up to 19V.
The LT3063 is offered in the thermally enhanced 8-lead
2mm × 3mm DFN and MSOP packages.
1.8V Low Noise Regulator
applicaTions
n Input Voltage Range: 1.6V to 45V
n Output Current: 200mA
n Output Discharge
n Quiescent Current: 45µA
n Dropout Voltage: 300mV
n Low Noise: 30µVRMS (10Hz to 100kHz)
n Adjustable Output (VREF = 600mV)
n Output Tolerance: ±2% Over Load, Line, and
Temperature
n Single Capacitor Soft-Starts Reference and Lowers
Output Noise
n Shutdown Current < 3µA
n Reverse Battery Protection
n Current Limit Foldback and Thermal Limit Protection
n 8-Lead 2mm × 3mm DFN and MSOP Packages
n Battery Powered Systems
n Automotive Power Supplies
n Industrial Power Supplies
n Avionic Power Supplies
n Portable Instruments
n Medical Instruments
L, LT, LT C , LT M, Linear Technology and the Linear logo are registered trademarks and
ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners.
3063 TA01
IN
SHDN
OUT
ADJ
GND BYP
LT3063
VIN
2.3V
VOUT
1.8V
200mA
1µF 10µF
118k
1%
59k
1%
0.01µF
Output Discharge vs VOUT
CREF/BYP = 0
1ms/DIV
SHDN: 0 TO 1V
2V/DIV
12V
10V
8V
6V
5V
2V
1.2V
3.3V
0V
3063 TA01a
VIN = VOUT +1V
COUT = 10µF
IFB-DIVIDER = 10µA
LT3063
2
3063f
For more information www.linear.com/LT3063
pin conFiguraTion
absoluTe MaxiMuM raTings
IN Pin Voltage .........................................................±50V
OUT Pin Voltage .............................................. +20V, –1V
Input to Output Differential Voltage (Note 2) ...........±50V
ADJ Pin Voltage ......................................................±50V
SHDN Pin Voltage ...................................................±50V
REF/BYP Pin Voltage .................................... –0.3V to 1V
Output Short-Circuit Duration .......................... Indefinite
(Note 1)
TOP VIEW
GND
SHDN
IN
IN
REF/BYP
ADJ
OUT
OUT
DCB PACKAGE
8-LEAD (2mm × 3mm) PLASTIC DFN
9
GND
3
4
2
1
6
5
7
8
TJMAX = 150°C, θJA = 38°C/W TO 45°C/W, θJC = 3.5°C/W
EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB
1
2
3
4
REF/BYP
ADJ
OUT
OUT
8
7
6
5
GND
SHDN
IN
IN
TOP VIEW
MS8E PACKAGE
8-LEAD PLASTIC MSOP
9
GND
TJMAX = 150°C, θJA = 29°C/W TO 45°C/W, θJC = 5°C/W to 10°C/W
EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB
orDer inForMaTion
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT3063EDCB#PBF LT3063EDCB#TRPBF LGMZ 8-Lead (2mm × 3mm) Plastic DFN –40°C to 125°C
LT3063IDCB#PBF LT3063IDCB#TRPBF LGMZ 8-Lead (2mm × 3mm) Plastic DFN –40°C to 125°C
LT3063HDCB#PBF LT3063HDCB#TRPBF LGMZ 8-Lead (2mm × 3mm) Plastic DFN –40°C to 150°C
LT3063MPDCB#PBF LT3063MPDCB#TRPBF LGMZ 8-Lead (2mm × 3mm) Plastic DFN –55°C to 150°C
LT3063EMS8E#PBF LT3063EMS8E#TRPBF LTGNB 8-Lead Plastic MSOP –40°C to 125°C
LT3063IMS8E#PBF LT3063IMS8E#TRPBF LTGNB 8-Lead Plastic MSOP –40°C to 125°C
LT3063HMS8E#PBF LT3063HMS8E#TRPBF LTGNB 8-Lead Plastic MSOP –40°C to 150°C
LT3063MPMS8E#PBF LT3063MPMS8E#TRPBF LTGNB 8-Lead Plastic MSOP –55°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
Operating Junction Temperature (Notes 3, 5, 12)
LT3063E, LT3063I ............................. –40°C to 125°C
LT3063MP ......................................... –55°C to 150°C
LT3063H ............................................–40°C to 150°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
MS8E Package Only ..........................................300°C
LT3063
3
3063f
For more information www.linear.com/LT3063
elecTrical characTerisTics
PARAMETER CONDITIONS MIN TYP MAX UNITS
Minimum Input Voltage (Note 4) ILOAD = 200mA l1.6 2.1 V
ADJ Pin Voltage (Notes 4, 5) VIN = 2.1V, ILOAD = 1mA
2.1V < VIN < 45V, 1mA < ILOAD < 200mA (E-, I-Grades)
2.1V < VIN < 45V, 1mA < ILOAD < 200mA (MP-, H-Grades)
l
l
594
588
585
600
600
600
606
612
612
mV
mV
mV
Line Regulation (Note 4) ΔVIN = 2.1V to 45V, ILOAD = 1mA (E-, I-Grades)
ΔVIN = 2.1V to 45V, ILOAD = 1mA (MP-, H-Grades)
l
l
0.5 4
6
mV
mV
Load Regulation (Note 4) VIN = 2.1V, ΔILOAD = 1mA to 200mA (E-, I-Grades)
VIN = 2.1V, ΔILOAD = 1mA to 200mA (MP-, H-Grades)
l
l
0.3 4
9
mV
mV
Dropout Voltage
VIN = VOUT(NOMINAL)
(Notes 6, 7)
ILOAD = 1mA
ILOAD = 1mA
l
65 110
180
mV
mV
ILOAD = 10mA
ILOAD = 10mA
l
130 180
270
mV
mV
ILOAD = 100mA
ILOAD = 100mA
l
250 290
430
mV
mV
ILOAD = 200mA
ILOAD = 200mA
l
300 360
530
mV
mV
GND Pin Current
VIN = VOUT(NOMINAL) + 0.6V
(Notes 6, 8)
ILOAD = 0
ILOAD = 1mA
ILOAD = 10mA
ILOAD = 100mA
ILOAD = 200mA
l
l
l
l
l
45
70
225
2
5
90
120
500
4
10
µA
µA
µA
mA
mA
Output Voltage Noise COUT = 10µF, ILOAD = 200mA, CREF/BYP = 0.01µF
VOUT = 600mV, BW = 10Hz to 100kHz
30 µVRMS
ADJ Pin Bias Current (Notes 4, 9) l15 60 nA
Shutdown Threshold VOUT = Off to On
VOUT = On to Off
l
l
0.3
0.8
0.7
1.5 V
V
SHDN Pin Current (Note 10) VSHDN = 0V
VSHDN = 45V
l
l
1.2
<1
3
µA
µA
Quiescent Current in Shutdown VIN = 45V, VSHDN = 0V 1.25 3 µA
Ripple Rejection (Note 4) VIN – VOUT = 1.5V (AVG), VRIPPLE = 0.5VP-P,
fRIPPLE = 120Hz, ILOAD = 200mA
70 85 dB
Current Limit VIN = 7V, VOUT = 0
VIN = VOUT(NOMINAL) + 1V (Note 11), ΔVOUT = –5%
l
220
320 mA
mA
Input Reverse Leakage Current VIN = -45V, VOUT = 0 l1 mA
Output Discharge Time (Note 6) VOUT Discharged to 10% of Nominal, COUT = 10μF l0.75 2 ms
Reverse Output Current VOUT = 3.3V, VIN = VSHDN = 2.1V 2.5 15 µA
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
LT3063
4
3063f
For more information www.linear.com/LT3063
elecTrical characTerisTics
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Absolute maximum input to output differential voltage is not
achievable with all combinations of rated IN pin and OUT pin voltages.
With the IN pin at 50V, the OUT pin may not be pulled below 0V. The total
measured voltage from IN to OUT must not exceed ±50V.
Note 3: The LT3063 is tested and specified under pulse load conditions
such that TJ ≅ TA. The LT3063E regulators are 100% tested at TA = 25°C
and performance is guaranteed from 0°C to 125°C. Performance at
–40°C to 125°C is assured by design, characterization and correlation
with statistical process controls. The LT3063I regulators are guaranteed
over the full –40°C to 125°C operating junction temperature range. The
LT3063MP regulators are 100% tested over the –55°C to 150°C operating
junction temperature. The LT3063H regulators are 100% tested at the
150°C operating junction temperature. High junction temperatures degrade
operating lifetimes. Operating lifetime is derated at junction temperature
greater than 125°C.
Note 4: The LT3063 is tested and specified for these conditions with the
ADJ connected to the OUT pin.
Note 5: Maximum junction temperature limits operating conditions. The
regulated output voltage specification does not apply for all possible
combinations of input voltage and output current. Limit the output current
range if operating at the maximum input voltage. Limit the input-to-output
voltage differential if operating at maximum output current. Current limit
foldback limits the maximum output current as a function of input-to-
output voltage. See Current Limit vs VIN – VOUT in the Typical Performance
Characteristics section.
Note 6: To satisfy minimum input voltage requirements, the LT3063 is
tested and specified for these conditions with an external resistor divider
(bottom 60k, top 230k) for an output voltage of 2.9V. The external resistor
divider adds 10µA of DC load on the output. The external current is not
factored into GND pin current.
Note 7: Dropout voltage is the minimum input-to-output voltage
differential needed to maintain regulation at a specified output current. In
dropout, the output voltage equals: (VIN – VDROPOUT).
Note 8: GND pin current is tested with VIN = VOUT(NOMINAL) + 0.6V and a
current source load. GND pin current will increase in dropout. See GND pin
current curves in the Typical Performance Characteristics section.
Note 9: ADJ pin bias current flows out of the ADJ pin.
Note 10: SHDN pin current flows into the SHDN pin.
Note 11: To satisfy requirements for minimum input voltage, current limit
is tested at VIN = VOUT(NOMINAL) + 1V or VIN = 2.1V, whichever is greater.
Note 12: This IC includes thermal limit which protects the device during
momentary overload conditions. Junction temperature exceeds 125°C
(LT3063E, LT3063I) or 150°C (LT3063MP, LT3063H) when thermal limit
is active. Continuous operation above the specified maximum junction
temperature may impair device reliability.
LT3063
5
3063f
For more information www.linear.com/LT3063
Typical perForMance characTerisTics
Quiescent Current ADJ Pin Voltage Quiescent Current
GND Pin Current, VOUT = 0.6V GND Pin Current vs ILOAD SHDN Pin Threshold
Typical Dropout Voltage Guaranteed Dropout Voltage Dropout Voltage
OUTPUT CURRENT (mA)
0
0
DROPOUT VOLTAGE (mV)
350
300
250
200
150
100
50
550
400
450
500
100 125 150 175 20025 50
3063 G01
75
TJ = 125°C
TJ = 25°C
TJ = 150°C
OUTPUT CURRENT (mA)
0
0
DROPOUT VOLTAGE (mV)
350
300
250
200
150
100
50
550
500
450
400
25 125 150 175 20050 75
3063 G02
100
TJ = 25°C
TJ = 150°C
= TEST POINTS
TEMPERATURE (°C)
–75
0
DROPOUT VOLTAGE (mV)
350
400
300
250
200
150
100
50
550
450
500
–50 75 100 125 150 175–25 0 25
3063 G03
50
IL = 200mA
IL = 50mA
IL = 10mA
IL = 100mA
TEMPERATURE (°C)
–75
0
QUIESCENT CURRENT (µA)
60
50
40
30
20
10
80
70
–50 75 100 125 150 175–25 0 25
3063 G04
50
VIN = VSHDN = 6V
VOUT = 5V
IL = 10µA
VIN = 6V
ALL OTHER PINS = 0V
TEMPERATURE (°C)
–75
588
ADJ PIN VOLTAGE (mV)
608
606
604
594
596
598
600
602
592
590
612
610
–50 75 100 125 150 175–25 0 25
3063 G05
50
IL = 1mA
VIN (V)
0
0
QUIESCENT CURRENT (µA)
100
90
80
30
40
50
60
70
20
10
120
110
5 25 30 35 40 4510 15
3063 G06
20
TJ = 25°C
VOUT = 5V
IL = 10mA
VSHDN = 0V, RL = 0
RL = 3Ω, IL = 200mA
RL = 6Ω, IL = 100mA
RL = 12Ω, IL = 50mA
RL = 600Ω, IL = 1mA
VIN (V)
0
0
GND PIN CURRENT (mA)
4.0
3.5
3.0
0.5
1.0
1.5
2.0
2.5
5.0
4.5
21 6 7 8 9 103 4
3063 G07
5
ILOAD (mA)
0
0
GND PIN CURRENT (mA)
9
8
3
2
1
4
5
6
7
10
25 100 125 150 175 20050
3063 G08
75
VIN = VOUT(NOMINAL) +1V
TEMPERATURE (°C)
–75
0
SHDN PIN THRESHOLD (V)
1.4
1.3
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.9
1.0
1.1
1.2
1.5
–25–50 75 100 125 150 1750 25
3063 G09
50
OFF TO ON
ON TO OFF
TA = 25°C, unless otherwise noted.
LT3063
6
3063f
For more information www.linear.com/LT3063
Typical perForMance characTerisTics
Internal Current Limit Internal Current Limit Output Discharge Time
Output Discharge Time
COUT = 10µF, VIN = VOUT + 1V
Output Discharge vs VOUT
CREF/BYP = 0
Output Discharge vs VOUT
CREF/BYP = 0
SHDN Pin Input Current SHDN Pin Input Current ADJ Pin Bias Current
TA = 25°C, unless otherwise noted.
SHDN PIN VOLTAGE (V)
0
0
SHDN PIN INPUT CURRENT (µA)
2.0
2.5
1.5
1.0
0.5
3.0
5 30 35 40 4510 15 20
3063 G10
25
TEMPERATURE (°C)
–75
0
SHDN PIN INPUT CURRENT (µA)
2.0
2.5
1.5
1.0
0.5
3.0
–50 75 100 125 150 175–25 0 25
3063 G11
50
SHDN = 45V
TEMPERATURE (°C)
–75
–50
ADJ PIN BIAS CURRENT (nA)
30
10
0
–10
–20
–30
–40
20
50
40
–25–50 75 100 125 150 1750 25
3063 G12
50
INPUT/OUTPUT VOLTAGE DIFFERENTIAL (V)
0
0
CURRENT LIMIT (mA)
300
250
200
50
100
150
400
350
5 25 30 35 40 4510 15
3063 G13
20
TJ = –55°C
TJ = –40°C
TJ = 25°C
TJ = 125°C
TJ = 150°C
TEMPERATURE (°C)
–75
0
CURRENT LIMIT (mA)
450
400
250
300
150
200
100
50
350
500
–25–50 75 100 125 150 1750 25
3063 G14
50
VIN = 7V
VOUT = 0V
OUTPUT VOLTAGE (V)
0
0
OUTPUT DISCHARGE TIME (ms)
3.5
1.0
1.5
2.0
2.5
3.0
0.5
4.0
2 10 12 14 16 18 204 6
3063 G15
8
COUT = 10µF
VIN = VOUT + 1V
OUTPUT DISCHARGE
FOLDBACK STARTS
TEMPERATURE (°C)
–75
0
OUTPUT DISCHARGE TIME (ms)
5
4
3
1
2
7
6
–25–50 75 100 125 150 1750 25
3063 G16
50
OUT = 1.2V
OUT = 3.3V
OUT = 5V
OUT = 12V
OUT = 20V
1ms/DIV
2V/DIV
12V
0V
3063 G17
VIN = VOUT +1V
COUT = 10µF
IFB-DIVIDER = 10µA
12V
10V
8V
6V
5V
2V
3.3V
1.2V
SHDN: 0 TO 1V
1ms/DIV
5V/DIV
20V
20V
15V
12V
0V
3063 G18
VIN = VOUT +1V
COUT = 10µF
IFB-DIVIDER = 10µA
SHDN: 0 TO 1V
LT3063
7
3063f
For more information www.linear.com/LT3063
Input Ripple RejectionReverse Current
TA = 25°C, unless otherwise noted.
Typical perForMance characTerisTics
Minimum Input Voltage
Load Regulation
5V Transient Response
CFF = 0, IOUT = 20mA to 200mA
Reverse Current
Input Ripple Rejection Input Ripple Rejection
TEMPERATURE (°C)
–75
0
OUTPUT CURRENT (µA)
130
140
120
60
70
80
90
100
110
40
50
10
20
30
150
–50 75 100 125 150 175–25 0 25
3063 G20
50
VOUT = VADJ = 3.3V
VIN = VSHDN = 2.1V
IADJ
IOUT
FREQUENCY (Hz)
10
0
RIPPLE REJECTION (dB)
50
40
10
20
30
90
60
70
80
10k 100k 1M 10M100
3063 G21
1k
ILOAD = 200mA
CREF/BYP = CFF = 0
VIN = VOUT +1.5V +50mVRMS
VOUT = 0.6V
VOUT = 5V
COUT = 10µF
COUT = 3.3µF
VOUT (V)
0
0
OUTPUT CURRENT (µA)
45
40
30
35
20
25
5
10
15
50
2 12 14 16 18 204 6 8
3063 G19
10
VIN = VSHDN = 2.1V
VADJ = VOUT
5V Transient Response
CFF = 10nF, IOUT = 20mA to 200mA
FREQUENCY (Hz)
10
0
RIPPLE REJECTION (dB)
50
40
10
20
30
100
60
70
80
90
10k 100k 1M 10M100
3063 G22
1k
CREF/BYP = CFF = 0
CREF/BYP = 10nF, CFF = 0
CREF/BYP = 10nF, CFF = 10nF
VIN = 6.5V +50mVRMS RIPPLE
ILOAD = 200mA
COUT = 10µF
VOUT = 5V
TEMPERATURE (°C)
–75
0
RIPPLE REJECTION (dB)
60
70
80
90
40
50
10
20
30
100
–50 75 100 125 150 175–25 0 25
3063 G23
50
CREF/BYP = 10nF
CREF/BYP = 0
ILOAD = 200mA
VOUT = 0.6V
VIN = 2.6V +0.5VP-P RIPPLE, f = 120Hz
TEMPERATURE (°C)
–75
0.0
MINIMUM INPUT VOLTAGE (V)
1.4
1.6
1.8
2.0
1.0
1.2
0.2
0.4
0.6
0.8
2.2
–50 75 100 125 150 175–25 0 25
3063 G24
50
ILOAD = 200mA
ILOAD = 100mA
TEMPERATURE (°C)
–75
–10
–9
LOAD REGULATION (mV)
–1
0
–2
–8
–7
–6
–5
–4
–3
1
–50 75 100 125 150 175–25 0 25
3063 G25
50
∆IL = 1mA TO 200mA
VOUT = 0.6V
VIN = 2.1V
100µs/DIV 3063 G26
VIN = 6V
COUT = 10µF
IFB-DIVIDER = 10µA
VOUT
100mV/DIV
IOUT
100mA/DIV
20µs/DIV 3063 G27
VIN = 6V
COUT = 10µF
IFB-DIVIDER = 10µA
VOUT
50mV/DIV
IOUT
100mA/DIV
LT3063
8
3063f
For more information www.linear.com/LT3063
Typical perForMance characTerisTics
Output Noise Spectral Density
vs CFF, CREF/BYP = 10nF
Output Noise Spectral Density
CREF/BYP = 0, CFF = 0
RMS Output Noise
vs Feedforward Capacitor (CFF)
5V 10Hz to 100kHz Output Noise
CREF/BYP = 10nF, CFF = 0
5V 10Hz to 100kHz Output Noise
CREF/BYP = 10nF, CFF = 10nF
Output Noise Spectral Density
vs CREF/BYP, CFF = 0
RMS Output Noise
vs CREF/BYP, VOUT = 0.6V
RMS Output Noise vs Load Current
CREF/BYP = 10nF, CFF = 0
FREQUENCY (Hz)
10
0.01
OUTPUT NOISE SPECTRAL DENSITY (µV/√Hz)
1
0.1
10
100 10k 100k
3063 G28
1k
0.6V
1.2V
2.5V
3.3V
5V
COUT = 10µF
IL = 200mA
FREQUENCY (Hz)
10
0.01
OUTPUT NOISE SPECTRAL DENSITY (µV/√Hz)
1
0.1
10
100 10k 100k
3063 G29
1k
COUT = 10µF
IL = 200mA
VOUT = 5V CREF/BYP = 100pF
CREF/BYP = 10nF
CREF/BYP = 1nF
VOUT = 0.6V
FREQUENCY (Hz)
10
0.01
OUTPUT NOISE SPECTRAL DENSITY (µV/√Hz)
1
0.1
10
100 10k 100k
3063 G30
1k
CFF = 100pF
CFF = 1nF
CFF = 0
CFF = 10nF
VOUT = 5V
COUT = 10µF
IL = 100mA
LOAD CURRENT (mA)
0.01
0
OUTPUT NOISE VOLTAGE (µVRMS)
70
80
90
100
40
50
60
30
20
10
110
0.1 10 100
3063 G31
1
CREF/BYP = 10nF
CREF/BYP = 100pF
CREF/BYP = 10pF
CREF/BYP = 0
CREF/BYP = 1nF
f = 10Hz TO 100kHz
COUT = 10µF
LOAD CURRENT (mA)
0.01
0
OUTPUT NOISE VOLTAGE (µVRMS)
70
80
90
100
110
120
130
140
150
40
50
60
30
20
10
160
0.1 10 100
3063 G32
1
f = 10Hz TO 100kHz
COUT = 10µF
VOUT = 0.6V
VOUT = 1.2V
VOUT = 2.5V
VOUT = 3.3V
VOUT = 5V
FEEDFORWARD CAPACITOR, CFF (nF)
0.01
0
OUTPUT NOISE VOLTAGE (µVRMS)
70
80
90
100
110
120
40
50
60
30
20
10
130
0.1 10
3063 G33
1
f = 10Hz TO 100kHz
CREF/BYP = 10nF
COUT = 10µF
IFB-DIVIDER = 10µA
ILOAD = 200mA
VOUT = 5V
VOUT = 0.6V
VOUT = 3.3V
VOUT = 1.2V
VOUT = 2.5V
1ms/DIV 3063 G34
COUT = 10µF
ILOAD = 200mA
VOUT
100µV/DIV
1ms/DIV 3063 G35
COUT = 10µF
ILOAD = 200mA
VOUT
100µV/DIV
TA = 25°C, unless otherwise noted.
LT3063
9
3063f
For more information www.linear.com/LT3063
Typical perForMance characTerisTics
SHDN Transient Response
CREF/BYP = 10nF
Start-Up Time
vs REF/BYP Capacitor
Transient Response, VOUT = 5V
Load Dump, VIN = 12V to 45V
SHDN Transient Response
CREF/BYP = 0
1ms/DIV
12V
45V
3063 G36
COUT = 10µF
CREF/BYP = CFF = 10nF
IFB-DIVIDER = 10µA
VOUT
5mV/DIV
VIN
10V/DIV
2ms/DIV 3063 G37
COUT = 10µF
CFF = 0
VOUT
2V/DIV
RL = 500k
REF/BYP
500mV/DIV
SHDN
1V/DIV
2ms/DIV 3063 G38
COUT = 10µF
CFF = 0
VOUT
2V/DIV
RL = 500k
REF/BYP
500mV/DIV
SHDN
1V/DIV
REF/BYP CAPACITOR (nF)
0.01
0.01
START-UP TIME (ms)
10
0.1
1
100
10 1000.1
3063 G39
1
CFF = 0
TA = 25°C, unless otherwise noted.
LT3063
10
3063f
For more information www.linear.com/LT3063
pin FuncTions
REF/BYP (Pin 1): Reference/ Bypass. Connecting a single
capacitor from this pin to GND bypasses the LT3063’s
reference noise and soft-starts the reference. A 10nF by-
pass capacitor typically reduces output voltage noise to
30μVRMS in a 10Hz to 100kHz bandwidth. Soft-start time
is directly proportional to the REF/BYP capacitor value.
If the LT3063 is placed in shutdown, REF/BYP is actively
pulled low by an internal device to reset soft-start. If low
noise or soft-start performance is not required, this pin
must be left floating (unconnected). Do not drive this pin
with any active circuitry.
ADJ (Pin 2): Adjust. This pin is the error amplifier’s invert-
ing terminal. Its typical bias current of 15nA flows out of
the pin (see curve of ADJ Pin Bias Current vs Temperature
in the Typical performance Characteristics section). The
ADJ pin voltage is 600mV referenced to GND.
OUT (Pins 3, 4): Output. These pins supply power to the
load. A minimum output capacitor of 3.3µF is required
to prevent oscillations. Large load transient applications
require larger output capacitors to limit peak voltage
transients. See the Applications Information section for
more information on reverse output characteristics. The
output voltage range is 600mV to 19V. If the LT3063 is
placed in shutdown, OUT is actively discharged by an
internal NMOS device. Gate drive is controlled to insure
that a 10μF capacitor is discharged 90% in 2mS or less.
If IN is driven low, OUT is actively discharged to ~800mV.
For OUT voltages greater than 6V, current limit foldback is
implemented to protect the NMOS device and discharge
rates increase. See the Applications Information section
for more information.
IN (Pins 5, 6): Input. These pins supply power to the
device. The LT3063 requires a bypass capacitor at IN if
the device is located more than six inches from the main
input filter capacitor. In general, the output impedance of
a battery rises with frequency, so it is advisable to include
a bypass capacitor in battery-powered circuits. A bypass
capacitor in the range of 1µF to 10µF suffices. See Input
Capacitance and Stability in the Application Information
section for more information.
The LT3063 withstands reverse voltages on the IN pin
with respect to the GND and OUT pins. In a reversed input
situation, such as the battery plugged in backwards, the
LT3063 behaves as if a large value resistor is in series with
its input. Limited reverse current flows into the LT3063
and no reverse voltage appears at the load. The device
protects itself and the load.
SHDN (Pin 7): Shutdown. Pulling the SHDN pin low puts
the LT3063 into a low power state and turns the output
off. Drive the SHDN pin with either logic or an open collec-
tor/drain with a pull-up resistor. The resistor supplies the
pull-up current to the open collector/drain logic, normally
several microamperes, and the SHDN pin current, typi-
cally less than 3µA. If unused, connect the SHDN pin to
VIN. The LT3063 does not function if the SHDN pin is not
connected. The SHDN pin cannot be driven below GND
unless tied to the IN pin. If the SHDN pin is driven below
GND while IN is powered, the output will turn on. SHDN
pin logic cannot be referenced to a negative rail.
GND (Pin 8, Exposed Pad Pin 9): Ground. Connect the
bottom of the external resistor divider that sets the output
voltage directly to GND for optimum regulation. Tie the
exposed pad Pin 9 directly to Pin 8 and the PCB ground.
This exposed pad provides enhanced thermal performance
with its connection to the PCB ground. See the Applica-
tions Information section for thermal considerations and
calculating junction temperature.
LT3063
11
3063f
For more information www.linear.com/LT3063
The LT3063 is a 200mA low dropout regulator with
shutdown. The device is capable of supplying 200mA at
a typical dropout voltage of 300mV and operates over a
1.6V to 45V input range.
A single external capacitor provides programmable low
noise reference performance and output soft-start func-
tionality. For example, connecting a 10nF capacitor from
the REF/BYP pin to GND lowers output noise to 30µVRMS
over a 10Hz to 100kHz bandwidth. This capacitor also
soft-starts the reference and prevents output voltage
overshoot at turn-on.
The LT3063’s quiescent current is merely 45μA, while
providing fast transient response with a 3.3µF minimum
low ESR ceramic output capacitor. In shutdown, quies-
cent current is less than 3μA and the reference soft-start
capacitor and output are reset.
The LT3063 optimizes stability and transient response
with low ESR, ceramic output capacitors. The LT3063
does not require the addition of ESR as is common with
other regulators. The LT3063 has an adjustable output
and typically provides 0.1% line regulation and 0.1%
load regulation. A curve of load regulation appears in the
Typical Performance Characteristics section.
The LT3063 discharges the output in shutdown. Internal
protection circuitry includes reverse-battery protection,
reverse-current protection, current limit with foldback
and thermal shutdown.
Adjustable Operation
The LT3063 has an output voltage range of 0.6V to 19V.
The output voltage is set by the ratio of two external resis-
tors as shown in Figure 1. The device servos the output to
maintain the ADJ pin voltage at 0.6V referenced to ground.
The current in R1 is then equal to 0.6V/R1 and the current
in R2 is the current in R1 plus the ADJ pin bias current.
The ADJ pin bias current, 15nA at 25ºC, flows through R2
into the ADJ pin. Calculate the output voltage using the
formula in Figure 1. The value of R1 should be no greater
than 61.9k to provide a minimum 10µA load current for
stability. The divider does not add to quiescent current in
applicaTions inForMaTion
Figure 1. Adjustable Operation
shutdown because the output is turned off and the divider
current is zero. Curves of ADJ Pin Voltage vs Temperature
and ADJ Pin Bias Current vs Temperature appear in the
Typical Performance Characteristics.
3063 F01
IN
SHDN
OUT
ADJ
GND REF/BYP
LT3063
VIN
VOUT
R2
R1
VOUT =0.6V 1+R2
R1
!
"
#$
%
&– IADJ •R2
( )
VADJ =0.6V
IADJ =15nA at 25°C
OUTPUT RANGE =0.6V to 19V
The LT3063 is tested and specified with the ADJ pin tied to
the OUT pin for an output voltage of 0.6V. Specifications
for output voltages greater than 0.6V are proportional to
the ratio of the desired output voltage to 0.6V: VOUT/0.6V.
For example, load regulation for an output current change
of 1mA to 200mA is –0.3mV typical at VOUT = 0.6V. At
VOUT = 12V, load regulation is:
12V
0.6V
•–0.3mV
( )
=–6mV
Table 1 shows 1% resistor divider values for some common
output voltages with a resistor divider current of 10µA.
Table 1. Output Voltage Resistor Divider Values
VOUT R1 R2
1.2V 60.4k 60.4k
1.5V 59k 88.7k
1.8V 59k 118k
2.5V 60.4k 191k
3V 59k 237k
3.3V 61.9k 280k
5V 59k 432k
LT3063
12
3063f
For more information www.linear.com/LT3063
applicaTions inForMaTion
Bypass Capacitance, Output Voltage Noise and
Transient Response
The LT3063 regulator provides low output voltage noise
over the 10Hz to 100kHz bandwidth while operating at full
load with the addition of a bypass capacitor (CREF/BYP)
from the REF/BYP pin to GND. A good quality low leak-
age capacitor is recommended. This capacitor bypasses
the reference of the regulator, providing a low frequency
noise pole for the internal reference. With the use of 10nF
for CREF/BYP, the output voltage noise decreases to as
low as 30µVRMS when the output voltage is set for 0.6V.
For higher output voltages (generated by using a resistor
divider), the output voltage noise gains up accordingly
when using CREF/BYP by itself.
To lower the output voltage noise for higher output volt-
ages, include a feedforward capacitor (CFF) from VOUT
to the ADJ pin. A good quality, low leakage capacitor is
recommended. This capacitor bypasses the error amplifier
of the regulator, providing a low frequency noise pole. With
the use of 10nF for both CFF and CREF/BYP, output voltage
noise decreases to 30µVRMS when the output voltage is
set to 5V by a 10µA feedback resistor divider. If the cur-
rent in the feedback resistor divider is doubled, CFF must
also be doubled to achieve equivalent noise performance.
Higher values of output voltage noise may be measured
if care is not exercised with regard to circuit layout and
testing. Crosstalk from nearby traces can induce unwanted
noise onto the LT3063’s output. Power supply ripple rejec-
tion must also be considered. The LT3063 regulator does
not have unlimited power supply rejection and will pass
a small portion of the input noise through to the output.
Using a feedforward capacitor (CFF) from VOUT to the ADJ
pin has the added benefit of improving transient response
for output voltages greater than 0.6V. With no feedforward
capacitor, the settling time will increase as the output
voltage is raised above 0.6V. Use the equation in Figure 2
to determine the minimum value of CFF to achieve a
transient response that is similar to 0.6V output voltage
performance regardless of the chosen output voltage (see
Figure 3 and Transient Response in the Typical Performance
Characteristics section).
During start-up, the internal reference soft-starts if a refer-
ence bypass capacitor is present. Regulator startup time
is directly proportional to the size of the bypass capacitor,
slowing to 6ms with a 10nF bypass capacitor (See SHDN
Transient Response vs REF/BYP Capacitor in the Typical
Performance Characteristics section). The reference by-
pass capacitor is actively pulled low during shutdown to
reset the internal reference.
Start-up time is also affected by the use of a feedforward
capacitor. Start-up time is directly proportional to the size
of the feedforward capacitor and output voltage, and is
inversely proportional to the feedback resistor divider cur-
rent, slowing to 15ms with a 10nF feedforward capacitor
and a 10µF output capacitor for an output voltage set to
5V by a 10µA feedback resistor divider.
Output Capacitance
The LT3063 regulator is stable with a wide range of output
capacitors. The ESR of the output capacitor affects stabil-
ity, most notably with small capacitors. Use a minimum
output capacitor of 3.3µF with an ESR of 3Ω or less to
prevent oscillations. The LT3063 is a micropower device
3063 F02
IN
SHDN
OUT
ADJ
GND REF/BYP
LT3063
VIN
VOUT
CREF/BYP
CFF COUT
R2
R1
CFF
10nF
10µA •IFB–DIVIDER
( )
IFB–DIVIDER =VOUT
R1+R2
100µs/DIV
VOUT = 5V
COUT = 10µF
IFB-DIVIDER = 10µA
0
1nF
10nF
LOAD CURRENT
200mA/DIV
FEEDFORWARD
CAPACITOR, CFF
100pF
3063 F03
VOUT
100mV/DIV
Figure 2. Feedforward Capacitor for Fast Transient Response
Figure 3. Transient Response vs Feedforward Capacitor
LT3063
13
3063f
For more information www.linear.com/LT3063
and output load transient response is a function of output
capacitance. Larger values of output capacitance decrease
the peak deviations and provide improved transient re-
sponse for larger load current changes. Bypass capacitors,
used to decouple individual components powered by the
LT3063, will increase the effective output capacitor value.
For applications with large load current transients, a low
ESR ceramic capacitor in parallel with a bulk tantalum
capacitor often provides an optimally damped response.
Give extra consideration to the use of ceramic capacitors.
Manufacturers make ceramic capacitors with a variety of
dielectrics, each with different behavior across tempera-
ture and applied voltage. The most common dielectrics
are specified with EIA temperature characteristic codes
of Z5U, Y5V, X5R and X7R. The Z5U and Y5V dielectrics
provide high C-V products in a small package at low cost,
but exhibit strong voltage and temperature coefficients as
shown in Figures 4 and 5. When used with a 5V regulator,
a 16V 10µF Y5V capacitor can exhibit an effective value
as low as 1µF to 2µF for the DC bias voltage applied and
over the operating temperature range. The X5R and X7R
dielectrics yield much more stable characteristics and are
more suitable for use as the output capacitor. The X7R
type works over a wider temperature range and has better
temperature stability, while the X5R is less expensive and is
available in higher values. Care still must be exercised when
using X5R and X7R capacitors; the X5R and X7R codes
only specify operating temperature range and maximum
capacitance change over temperature. Capacitance change
due to DC bias with X5R and X7R capacitors is better than
Y5V and Z5U capacitors, but can still be significant enough
to drop capacitor values below appropriate levels. Capaci-
tor DC bias characteristics tend to improve as component
case size increases, but expected capacitance at operating
voltage should be verified.
Voltage and temperature coefficients are not the only
sources of problems. Some ceramic capacitors have a
piezoelectric response. A piezoelectric device generates
voltage across its terminals due to mechanical stress,
similar to the way a piezoelectric accelerometer or micro-
phone works. For a ceramic capacitor, the stress can be
induced by vibrations in the system or thermal transients.
The resulting voltages produced can cause appreciable
amounts of noise. A ceramic capacitor produced the trace
applicaTions inForMaTion
in Figure 6 in response to light tapping from a pencil.
Similar vibration induced behavior can masquerade as
increased output voltage noise.
DC BIAS VOLTAGE (V)
CHANGE IN VALUE (%)
3063 F04
20
0
–20
–40
–60
–80
–100 04810
2 6 12 14
X5R
Y5V
16
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
TEMPERATURE (°C)
–50
40
20
0
–20
–40
–60
–80
–100 25 75
3063 F05
–25 0 50 100 125
Y5V
CHANGE IN VALUE (%)
X5R
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
Figure 4. Ceramic Capacitor DC Bias Characteristics
Figure 5. Ceramic Capacitor Temperature Characteristics
Figure 6. Noise Resulting from Tapping on a Ceramic Capacitor
4ms/DIV
3063 F06
VOUT
500µV/DIV
VOUT = 0.6V
COUT = 10µF
CREF/BYP = 10nF
ILOAD = 100mA
LT3063
14
3063f
For more information www.linear.com/LT3063
applicaTions inForMaTion
Input Capacitance and Stability
Low ESR, ceramic input bypass capacitors are acceptable
for applications without long input leads. However, appli-
cations connecting a power supply to an LT3063 circuit’s
IN and GND pins with long input wires combined with a
low ESR, ceramic input capacitor are prone to voltage
spikes, reliability concerns and application-specific board
oscillations.
The input wire inductance found in many battery-powered
applications, combined with the low ESR ceramic input
capacitor, forms a high Q LC resonant tank circuit. In
some instances this resonant frequency beats against the
output current dependent LDO bandwidth and interferes
with proper operation. Simple circuit modifications/solu-
tions are then required. This behavior is not indicative of
LT3063 instability, but is a common ceramic input bypass
capacitor application issue.
The self-inductance, or isolated inductance, of a wire is
directly proportional to its length. Wire diameter is not a
major factor on its self-inductance. For example, the self-
inductance of a 2-AWG isolated wire (diameter = 0.26") is
about half the self-inductance of a 30-AWG wire (diameter
= 0.01"). One foot of 30-AWG wire has approximately
465nH of self-inductance.
Tw o methods can reduce wire self-inductance. One method
divides the current flowing towards the LT3063 between
two parallel conductors. In this case, the farther apart the
wires are from each other, the more the self-inductance is
reduced; up to a 50% reduction when placed a few inches
apart. Splitting the wires connects two equal inductors in
parallel, but placing them in close proximity creates mutual
inductance adding to the self-inductance. The second and
most effective way to reduce overall inductance is to place
both forward and return current conductors (the input
and GND wires) in very close proximity. Tw o 30-AWG
wires separated by only 0.02”, used as forward and return
current conductors, reduce the overall self-inductance
to approximately one-fifth that of a single isolated wire.
If a battery, mounted in close proximity, powers the LT3063,
a 1µF input capacitor suffices for stability. However, if a
distant supply powers the LT3063, use a larger value input
capacitor. Use a rough guideline of 1µF (in addition to the
1µF minimum) per 8 inches of wire length. The minimum
input capacitance needed to stabilize the application also
varies with power supply output impedance variations.
Placing additional capacitance on the LT3063’s output
also helps. However, this requires an order of magnitude
more capacitance in comparison with additional LT3063
input bypassing. Series resistance between the supply
and the LT3063 input also helps stabilize the applica-
tion; as little as 0.1Ω to 0.5Ω suffices. This impedance
dampens the LC tank circuit at the expense of dropout
voltage. A better alternative is to use higher ESR tantalum
or electrolytic capacitors at the LT3063 input in place of
ceramic capacitors.
Overload Recovery
Like many IC power regulators, the LT3063 has safe oper-
ating area protection. The safe area protection decreases
current limit as input-to-output voltage increases and keeps
the power transistor inside a safe operating region for all
values of input-to-output voltage. The protective design
provides some output current at all values of input-to-
output voltage up to the device breakdown.
When power is first applied, as input voltage rises, the
output follows the input, allowing the regulator to start up
into very heavy loads. During start-up, as the input voltage
is rising, the input-to-output voltage differential is small,
allowing the regulator to supply large output currents. With
a high input voltage, a problem can occur wherein removal
of an output short will not allow the output to recover.
The problem occurs with a heavy output load when the
input voltage is high and the output voltage is low. Com-
mon situations include immediately after the removal of a
short-circuit or if the shutdown pin is pulled high after the
input voltage has already been turned on. The load line for
such a load may intersect the output current curve at two
points. If this happens, there are two stable output operat-
ing points for the regulator. With this double intersection,
the input power supply may need to be cycled down to
zero and brought up again to make the output recover.
LT3063
15
3063f
For more information www.linear.com/LT3063
Thermal Considerations
The power handling capability of the device will be limited
by the maximum rated junction temperature (125°C for
LT3063E, LT3063I or 150°C for LT3063MP, LT3063H). Tw o
components comprise the power dissipated by the device:
1. Output current multiplied by the input/output voltage
differential: IOUT • (VIN – VOUT), and
2. GND pin current multiplied by the input voltage:
IGND • VIN
GND pin current is determined using the GND Pin Current
curves in the Typical Performance Characteristics section.
Power dissipation equals the sum of the two components
listed above.
The LT3063 regulator has internal thermal limiting that pro-
tects the device during overload conditions. For continuous
normal conditions, the maximum junction temperature of
125°C (E-grade, I-grade) or 150°C (MP-grade, H-grade)
must not be exceeded. Carefully consider all sources of
thermal resistance from junction to ambient including
other heat sources mounted in proximity to the LT3063.
The undersides of the LT3063 packages have exposed metal
from the lead frame to the die attachment. The package
allows heat to directly transfer from the die junction to the
printed circuit board metal to control maximum operating
junction temperature. The dual-in-line pin arrangement
allows metal to extend beyond the ends of the package
on the topside (component side) of a PCB. Connect this
metal to GND on the PCB. The multiple IN and OUT pins
of the LT3063 also assist in spreading heat to the PCB.
For surface mount devices, heat sinking is accomplished
by using the heat spreading capabilities of the PC board
and its copper traces. Copper board stiffeners and plated
through-holes can also be used to spread the heat gener-
ated by power devices.
applicaTions inForMaTion
The following tables list thermal resistance for several
different board sizes and copper areas. All measurements
were taken in still air on a 4 layer FR-4 board with 1oz
solid internal planes and 2oz top/bottom external trace
planes with a total board thickness of 1.6mm. The four
layers were electrically isolated with no thermal vias
present. PCB layers, copper weight, board layout and
thermal vias will affect the resultant thermal resistance.
For more information on thermal resistance and high
thermal conductivity test boards, refer to JEDEC standard
JESD51, notably JESD51-12 and JESD51-7. Achieving
low thermal resistance necessitates attention to detail and
careful PCB layout.
Table 2. Measured Thermal Resistance for DFN Package
COPPER AREA
BOARD AREA
(mm2)
THERMAL RESISTANCE
(JUNCTION-TO-AMBIENT)
TOPSIDE*
(mm2)
BACKSIDE
(mm2)
2500 2500 2500 38°C/W
1000 2500 2500 38°C/W
225 2500 2500 40°C/W
100 2500 2500 45°C/W
*Device is mounted on topside
Table 3. Measured Thermal Resistance for MSOP Package
COPPER AREA
BOARD AREA
(mm2)
THERMAL RESISTANCE
(JUNCTION-TO-AMBIENT)
TOPSIDE*
(mm2)
BACKSIDE
(mm2)
2500 2500 2500 29°C/W
1000 2500 2500 30°C/W
225 2500 2500 32°C/W
100 2500 2500 45°C/W
*Device is mounted on topside
LT3063
16
3063f
For more information www.linear.com/LT3063
applicaTions inForMaTion
Calculating Junction Temperature
Example: Given an output voltage of 2.5V, an input volt-
age range of 12V ±5%, an output current range of 0mA
to 50mA and a maximum ambient temperature of 85°C,
what will the maximum junction temperature be?
The power dissipated by the device equals:
IOUT(MAX) • (VIN(MAX)–VOUT) + IGND • VIN(MAX)
where,
IOUT(MAX) = 50mA
VIN(MAX) = 12.6V
IGND at (IOUT = 50mA, VIN = 12V) = 1mA
So,
P = 50mA • (12.6V – 2.5V) + 1mA • 12.6V = 0.518W
Using a DFN package, the thermal resistance will be in
the range of 38°C/W to 45°C/W depending on the copper
area. So the junction temperature rise above ambient is
approximately equal to:
0.518W • 45°C/W = 23.3°C
The maximum junction temperature equals the maximum
ambient temperature plus the maximum junction tempera-
ture rise above ambient or:
TJMAX = 85°C + 23.3°C = 108.3°C
Output Discharge
The LT3063 includes a low resistance NMOS device which
rapidly discharges the output voltage if the part is put in
shutdown mode. For a 2.9V output with a 10μF decoupling
capacitor, the NMOS discharges the output to 290mV in
750µs if SHDN is driven low.
Control circuitry drives the gate of the NMOS high if either
the SHDN pin or the IN pin are driven low. In the case
where the IN pin is driven to ground, the NMOS rapidly
discharges the OUT pin to the threshold voltage of the
NMOS, approximately 800mV. From 800mV, the external
load discharges the OUT pin at a reduced rate.
The control circuitry implements protection features which
allow the OUT pin to be driven from –1V to 20V without
damaging the LT3063. Current limit foldback for output
voltages greater than 6V protects the NMOS pull-down,
but increases discharge times for higher output voltages.
Figure 7. Discharge Time vs Output Voltage
OUTPUT VOLTAGE (V)
0
0
OUTPUT DISCHARGE TIME (ms)
3.5
1.0
1.5
2.0
2.5
3.0
0.5
4.0
2 10 12 14 16 18 204 6
3063 F07
8
COUT = 10µF
VIN = VOUT + 1V
OUTPUT DISCHARGE
FOLDBACK STARTS
Protection Features
The LT3063 incorporates several protection features that
make it ideal for use in battery-powered circuits. In ad-
dition to the normal protection features associated with
monolithic regulators, such as current limiting and thermal
limiting, the device also protects against reverse-input
voltages and reverse output-to-input voltages.
Current limit protection and thermal overload protection
protect the device against current overload conditions at
the output of the device. The typical thermal shutdown
temperature is 165°C. For normal operation, do not exceed
a junction temperature of 125°C (LT3063E, LT3063I) or
150°C (LT3063MP, LT3063H).
LT3063
17
3063f
For more information www.linear.com/LT3063
The LT3063 IN pin withstands reverse voltages of 50V. The
device limits current flow to less than 1mA (typically less
than 250µA) and no negative voltage appears at OUT. The
device protects both itself and the load against batteries
that are plugged in backwards.
The SHDN pin cannot be driven below GND unless tied to
the IN pin. If the SHDN pin is driven below GND while IN
is powered, the output will turn on. SHDN pin logic cannot
be referenced to a negative rail.
The LT3063 incurs no damage if the ADJ pin is pulled
above or below ground by 50V. If the input is left open
circuit or grounded, the ADJ pin performs like a large
resistor (typically 30k) in series with a diode when pulled
above or below ground.
Several different input/output conditions can occur, some
temporarily until the output capacitor is discharged by the
LT3063. The output voltage may be held up temporarily
or otherwise while the input is pulled to ground, pulled
to some intermediate voltage or left open-circuit. Current
applicaTions inForMaTion
flow back into the OUT pin follows the curve shown in
Figure 8. If the LT3063's IN pin is forced below the OUT
pin or the OUT pin is pulled above the IN pin, regardless of
the state of the SHDN pin, input current typically drops to
less than 3µA. If IN is pulled near 0V, the output discharge
pull-down NMOS turns on, regardless of the state of the
SHDN pin. The gate drive for the pull-down is supplied
by the output voltage.
Figure 8. LT3603 Reverse Output Current
VOUT (V)
0
0
REVERSE CURRENT (µA)
45
40
30
35
20
25
5
10
15
50
2 12 14 16 18 204 6 8
3063 F08
10
VIN = VSHDN = 2.1V
VADJ = VOUT
IOUT
LT3063
18
3063f
For more information www.linear.com/LT3063
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
3.00 ±0.10
(2 SIDES)
2.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 ±0.10
BOTTOM VIEW—EXPOSED PAD
0.75 ±0.05
R = 0.115
TYP
R = 0.05
TYP
1.35 REF
1
4
85
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DCB8) DFN 0106 REV A
0.23 ±0.05
0.45 BSC
PIN 1 NOTCH
R = 0.20 OR 0.25
× 45° CHAMFER
0.25 ±0.05
1.35 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
2.10 ±0.05
0.70 ±0.05
3.50 ±0.05
PACKAGE
OUTLINE
0.45 BSC
1.35 ±0.10
1.35 ±0.05
1.65 ±0.10
1.65 ±0.05
DCB Package
8-Lead Plastic DFN (2mm × 3mm)
(Reference LTC DWG # 05-08-1718 Rev A)
LT3063
19
3063f
For more information www.linear.com/LT3063
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
MSOP (MS8E) 0213 REV K
0.53 ±0.152
(.021 ±.006)
SEATING
PLANE
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD
SHALL NOT EXCEED 0.254mm (.010") PER SIDE.
0.18
(.007)
0.254
(.010)
1.10
(.043)
MAX
0.22 – 0.38
(.009 – .015)
TYP
0.86
(.034)
REF
0.65
(.0256)
BSC
0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
1 2 34
4.90 ±0.152
(.193 ±.006)
8
8
1
BOTTOM VIEW OF
EXPOSED PAD OPTION
765
3.00 ±0.102
(.118 ±.004)
(NOTE 3)
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
0.52
(.0205)
REF
1.68
(.066)
1.88
(.074)
5.10
(.201)
MIN
3.20 – 3.45
(.126 – .136)
1.68 ±0.102
(.066 ±.004)
1.88 ±0.102
(.074 ±.004) 0.889 ±0.127
(.035 ±.005)
RECOMMENDED SOLDER PAD LAYOUT
0.65
(.0256)
BSC
0.42 ±0.038
(.0165 ±.0015)
TYP
0.1016 ±0.0508
(.004 ±.002)
DETAIL “B”
DETAIL “B”
CORNER TAIL IS PART OF
THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
NO MEASUREMENT PURPOSE
0.05 REF
0.29
REF
MS8E Package
8-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1662 Rev K)
LT3063
20
3063f
For more information www.linear.com/LT3063
LINEAR TECHNOLOGY CORPORATION 2014
LT 0614 • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LT3063
Typical applicaTion
relaTeD parTs
PART
NUMBER DESCRIPTION COMMENTS
LT1761 100mA, Low Noise LDO 300mV Dropout Voltage, Low Noise: 20µVRMS, VIN = 1.8V to 20V, ThinSOT™ Package
LT1762 150mA, Low Noise LDO 300mV Dropout Voltage, Low Noise: 20µVRMS, VIN = 1.8V to 20V, MS8 Package
LT1763 500mA, Low Noise LDO 300mV Dropout Voltage, Low Noise: 20µVRMS, VIN = 1.8V to 20V, SO8, 3mm × 4mm DFN-12 Package
LT1962 300mA, Low Noise LDO 270mV Dropout Voltage, Low Noise: 20µVRMS, VIN = 1.8V to 20V, MS8 Package
LT1964 200mA, Low Noise, Negative LDO 340mV Dropout Voltage, Low Noise 30µVRMS, VIN = –1.8V to –20V, ThinSOT, 3mm × 3mm DFN-8
Packages
LT3008 20mA, 45V, 3µA IQ Micropower LDO 300mV Dropout Voltage, Low IQ: 3µA, VIN = 2V to 45V, VOUT = 0.6V to 44.5V; ThinSOT and
2mm × 2mm DFN-6 Packages
LT3009 20mA, 3µA IQ Micropower LDO 280mV Dropout Voltage, Low IQ: 3µA, VIN = 1.6V to 20V, 2mm × 2mm DFN-6 and SC70 Packages
LT3050 100mA, Low Noise Linear Regulator
with Precision Current Limit and
Diagnostic Functions.
340mV Dropout Voltage, Low Noise: 30µVRMS, VIN: 1.6V to 45V, VOUT: 0.6V to 44.5V, Programmable
Precision Current Limit: ±5%, Programmable Minimum IOUT Monitor, Output Current Monitor, Fault
Indicator, Reverse Protection; 12-Lead 3mm × 2mm DFN and MSOP Packages.
LT3060 45V VIN, Micropower, Low Noise,
100mA Low Dropout Linear
Regulator
Input Voltage Range: 1.6V to 45V, Quiescent Current: 40μA, Dropout Voltage: 300mV, Low Noise:
30μVRMS (10Hz to 100kHz), Adjustable Output: VREF = 600mV, 8-Lead 2mm x 2mm DFN and 8-Lead
ThinSOT
LT3082 200mA, Parallelable, Single
Resistor, Low Dropout Linear
Regulator
Outputs May Be Paralleled for Higher Output, Current or Heat Spreading, Wide Input Voltage Range:
1.2V to 40V Low Value Input/Output Capacitors Required: 0.22μF, Single Resistor Sets Output Voltage,
Initial Set Pin Current Accuracy: 1%, Low Output Noise: 40μVRMS (10Hz to 100kHz) Reverse-Battery
Protection, Reverse-Current Protection; 8-Lead SOT-23, 3-Lead SOT-223 and
8-Lead 3mm × 3mm DFN Packages
LT3085 500mA, Parallelable, Low Noise,
Low Dropout Linear Regulator
275mV Dropout Voltage (2-Supply Operation), Low Noise: 40µVRMS, VIN: 1.2V to 36V,
VOUT: 0V to 35.7V, Current-Based Reference with 1-Resistor VOUT Set, Directly Parallelable
(No Op Amp Required), Stable with Ceramic Capacitors; MS8E and 2mm × 3mm DFN-6 Packages
LT3092 200mA 2-Terminal Programmable
Current Source
Programmable 2-Terminal Current Source, Maximum Output Current: 200mA, Wide Input Voltage
Range: 1.2V to 40V, Resistor Ratio Sets Output Current, Initial Set Pin Current Accuracy: 1%, Current
Limit and Thermal Shutdown Protection, Reverse-Voltage Protection, Reverse-Current Protection;
8-Lead SOT-23, 3-Lead SOT-223 and 8-Lead 3mm × 3mm DFN Packages
3063 TA02
IN
SHDN
OUT
ADJ
GND BYP
LT3063
VIN
2.3V
VOUT
1.8V
200mA
1µF 10µF
118k
1%
59k
1%
0.01µF
1.8V Low Noise Regulator
