NT1GC64BH4B0NF / NT2GC64B88B0NF / NT4GB8HB0NF 1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64 PC3-8500 / PC3-10600 Unbuffered DDR3 SDRAM DIMM Based on DDR3-1066/1333 128Mx16 (1GB) / 256Mx8 (2GB/4GB) SDRAM B-Die Features *Performance: Speed Sort PC3-8500 PC3-10600 -BE -CG Unit DIMM CAS Latency 7 9 fck - Clock Freqency 533 667 tck - Clock Cycle 1.875 1.5 ns fDQ - DQ Burst Freqency 1066 1333 Mbps MHz * 240-Pin Dual In-Line Memory Module (UDIMM) * 128Mx64 (1GB) / 256Mx64 (2GB) / 512Mx64 (4GB) DDR3 Unbuffered DIMM based on 256Mx8 DDR3 SDRAM B-Die devices. * Intended for 533MHz/667MHz applications * Inputs and outputs are SSTL-15 compatible * VDD = VDDQ = 1.5V 0.075V * SDRAMs have 8 internal banks for concurrent operation * Differential clock inputs * Data is read or written on both clock edges * DRAM DLL aligns DQ and DQS transitions with clock transitions. * Address and control signals are fully synchronous to positive clock edge * Nominal and Dynamtic On-Die Termination support * Halogen free product * Programmable Operation: - DIMM Latency: 6,7,8,9 - Burst Type: Sequential or Interleave - Burst Length: BC4, BL8 - Operation: Burst Read and Write * Two different termination values (Rtt_Nom & Rtt_WR) * 14/10/1 (row/column/rank) Addressing for 1GB * 14/10/1 (row/column/rank) Addressing for 2GB * 15/10/2 (row/column/rank) Addressing for 4GB * Extended operating temperature rage * Auto Self-Refresh option * Serial Presence Detect * Gold contacts *1GB: SDRAMs are in 96-ball BGA Package * 2GB: SDRAMs are in 78-ball BGA Package * 4GB: SDRAMs are in 78-ball BGA Package * RoHS compliance and Halogen free Description NT1GC64BH4B0NF / NT2GC64B88B0NF / NT4GC64B8HB0NF are 240-Pin Double Data Rate 3 (DDR3) Synchronous DRAM Unbuffered Dual In-Line Memory Module (UDIMM), organized as one rank of 128Mx64 (1GB) / 256Mx64 (2GB) and two ranks of 512Mx64 (4GB) high-speed memory array. Modules use four 128Mx16 (1GB) 96-ball BGA packaged devices and eight 256Mx8 (2GB) 78-ball BGA packaged devices and sixteen 256Mx8 (4GB) 78-ball BGA packaged devices . These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between suppliers. All NANYA DDR3 SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25" long space-saving footprint. The DIMM is intended for use in applications operating of 533MHz/667MHz clock speeds and achieves high-speed data transfer rates of 1066Mbps/1333Mbps. Prior to any access operation, the device latency and burst/length/operation type must be programmed into the DIMM by address inputs A0-A13 (1GB/2GB) / A0-A14 (4GB) and I/O inputs BA0~BA2 using the mode register set cycle. The DIMM uses serial presence-detect implemented via a serial EEPROM using a standard IIC protocol. The first 128 bytes of SPD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer. REV 0.1 01/2010 1 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC64BH4B0NF / NT2GC64B88B0NF / NT4GB8HB0NF 1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64 PC3-8500 / PC3-10600 Unbuffered DDR3 SDRAM DIMM Ordering Information Part Number Speed Organization NT1GC64BH4B0NF-BE DDR3-1066 PC3-8500 533MHz (1.875ns @ CL = 7) NT1GC64BH4B0NF-CG DDR3-1333 PC3-10600 NT2GC64B88B0NF-BE DDR3-1066 PC3-8500 533MHz (1.875ns @ CL = 7) NT2GC64B88B0NF- CG DDR3-1333 PC3-10600 NT4GC64B8HB0NF-BF DDR3-1066 PC3-8500 533MHz (1.875ns @ CL = 8) NT4GC64B8HB0NF -CG DDR3-1333 PC3-10600 Power Leads 1.5V Gold Note 128Mx64 667MHz (1.5ns @ CL = 9) 256Mx64 667MHz (1.5ns @ CL = 9) 512Mx64 667MHz (1.5ns @ CL = 9) Pin Description Pin Name Description Pin Name Description CK0, CK1 Clock Inputs, positive line DQ0-DQ63 , Clock Inputs, negative line DQS0-DQS8 Data strobes Clock Enable - Data strobes complement CKE0, CKE1 Row Address Strobe Column Address Strobe , DM0-DM8 Data input/output Data Masks Temperature event pin Write Enable Reset pin Chip Selects VREFDQ , VREFCA A0-A9, A11, A13-A15 Address Inputs A10/AP Address Input/Auto-Precharge A12/ Address Input/Burst Chop VDDSPD Input/Output Reference SPD and Temp sensor power SA0, SA1 Serial Presence Detect Address Inputs Vtt Termination voltage BA0-BA2 SDRAM Bank Address Inputs VSS Ground ODT0, ODT1 Active termination control lines VDD Core and I/O power SCL Serial Presence Detect Clock Input NC No Connect SDA Serial Presence Detect Data input/output REV 0.1 01/2010 2 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC64BH4B0NF / NT2GC64B88B0NF / NT4GB8HB0NF 1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64 PC3-8500 / PC3-10600 Unbuffered DDR3 SDRAM DIMM DDR3 SDRAM Pin Assignment Pin 1 Front Pin VREFDQ 121 Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back VSS 31 DQ25 151 VSS 61 A2 181 A1 91 DQ41 211 VSS DM5, 212 DQS14, TDQS14 NC, 213 , 2 VSS 122 DQ4 32 VSS 152 DM3,DQS12,T DQS12 62 VDD 182 VDD 92 VSS 3 DQ0 123 DQ5 33 153 NC, 63 CK1,NC 183 VDD 93 4 DQ1 124 VSS 34 DQS3 154 VSS 64 ,NC 184 CK0 94 DQS5 214 VSS 35 VSS 155 DQ30 65 VDD 185 95 VSS 215 DQ46 36 DQ26 156 DQ31 66 VDD 186 VDD 96 DQ42 216 DQ47 97 DQ43 217 VSS 5 6 7 VSS 125 126 DQS0 127 DM0,DQS9, TDQS9 NC, VSS 37 DQ27 157 VSS 67 VREFCA 187 , NC VSS 158 CB4,NC 68 PAR_IN, NC 188 A0 98 VSS 218 DQ52 8 VSS 128 DQ6 38 9 DQ2 129 DQ7 39 CB0,NC 159 CB5,NC 69 VDD 189 VDD 99 DQ48 219 DQ53 10 DQ3 130 VSS 40 CB1,NC 160 VSS 70 A10/AP 190 BA1 100 DQ49 220 VSS DM6, 221 DQS15, TDQS15 NC, 222 , 11 VSS 131 DQ12 41 VSS 161 DM8,DQS17, TDQS17,NC 71 BA0 191 VDD 101 VSS 12 DQ8 132 DQ13 42 162 NC,, , 72 VDD 192 102 13 DQ9 133 VSS 43 DQS8 163 VSS 73 193 103 DQS6 223 VSS 44 VSS 164 CB6,NC 74 194 VDD 104 VSS 224 DQ54 45 CB2,NC 165 CB7,NC 75 VDD 195 ODT0 105 DQ50 225 DQ55 VSS 46 CB3,NC 166 VSS 76 ,NC 196 A13 106 DQ51 226 VSS DM1, DQS10, 134 TDQS10 NC, 135 14 VSS 15 16 DQS1 136 17 137 DQ14 47 VSS 167 NC(TEST) 77 ODT1,NC 197 VDD 107 VSS 227 DQ60 18 DQ10 138 VSS DQ15 48 VTT,NC 168 78 VDD 198 ,NC 108 DQ56 228 DQ61 19 DQ11 139 VSS 49 VTT,NC 169 CKE1/NC 79 ,NC 199 VSS 109 DQ57 229 VSS 20 VSS DM7, 230 DQS16, TDQS16 NC, 231 , 140 DQ20 50 CKE0 170 VDD 80 VSS 200 DQ36 110 VSS 21 DQ16 141 DQ21 51 VDD 171 A15,NC 81 DQ32 201 DQ37 111 22 DQ17 142 VSS 52 BA2 172 A14 82 DQ33 202 VSS 112 DQS7 232 VSS VSS 233 DQ62 DQ58 234 DQ63 23 VSS 143 DM2, DQS11, TDQS11 53 ERR_OUT 173 ,NC VDD 83 VSS DM4, 203 DQS13, 113 TDQS13 NC, 204 , 114 24 144 NC, 54 VDD 174 A12/ 84 25 DQS2 145 VSS 55 A11 175 A9 85 DQS4 205 VSS 115 DQ59 235 VSS 146 DQ22 56 A7 176 VDD 86 VSS 206 DQ38 116 VSS 236 VDDSPD 27 DQ18 147 DQ23 57 VDD 177 A8 87 DQ34 207 DQ39 117 SA0 237 SA1 28 DQ19 148 26 VSS VSS 58 A5 178 A6 88 DQ35 208 VSS 118 SCL 238 SDA 149 DQ28 59 A4 179 VDD 89 VSS 209 DQ44 119 SA2 239 VSS DQ24 150 DQ29 60 VDD 180 A3 90 DQ40 210 DQ45 120 VTT 240 VTT 29 30 VSS Note: CK1, , CKE1, and ODT1 are for 4GB modules only. REV 0.1 01/2010 3 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC64BH4B0NF / NT2GC64B88B0NF / NT4GB8HB0NF 1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64 PC3-8500 / PC3-10600 Unbuffered DDR3 SDRAM DIMM Input/Output Functional Description Symbol Type Polarity Function CK0, CK1 , Input Cross point The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and falling edge of . A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. CKE0, CKE1 Input Active High Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode. , Input Active Low Enables the associated DDR3 SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue, Rank 0 is selected by ; Rank 1 is selected by , , Input Active Low When sampled at the positive rising edge of CK and falling edge of , signals , , define the operation to be executed by the SDRAM. ODT0, ODT1 Input Active High Asserts on-die termination for DQ, DM, DQS, and signals if enabled via the DDR3 SDRAM mode register. DM0 - DM8 Input Active High The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. The data strobes, associated with one data byte, sourced with data transfers. In Write mode, the data strobe is sourced by the controller and is centered in the data window. In Read mode, the data strobe is sourced by the DDR3 SDRAM and is sent at the leading edge of the data window. signals are complements, and timing is relative to the cross point of respective DQS and . If the module is to be operated in single ended strobe mode, all signals must be tied on the system board to VSS and DDR3 SDRAM mode registers programmed appropriately. DQS0 - DQS8 - I/O Cross point BA0, BA1, BA2 Input - Selects which DDR3 SDRAM internal bank of four or eight is activated. Input - During a Bank Activate command cycle, defines the row address when sampled at the cross point of the rising edge of CK and falling edge of . During a Read or Write command cycle, defines the column address when sampled at the cross point of the rising edge of CK and falling edge of . In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to precharge. A0 - A9 A10/AP A11 A12/ A13-A15 DQ0 - DQ63 Input - Data Input/Output pins. VDD, VDDSPD, VSS Supply - Power supplies for core, I/O, Serial Presence Detect, Temp sensor, and ground for the module. VREFDQ, VREFCA Supply - Reference voltage for SSTL15 inputs SDA I/O - This is a bidirectional pin used to transfer data into or out of the SPD EEPROM and temp sensor. A resistor must be connected from the SDA bus line to VDDSPD on the system planar to act as a pull up. SCL Input - This signal is used to clock data into and out of the SPD EEPROM and Temp sensor. SA0 - SA2 Input - Address pins used to select the Serial Presence Detect and Temp sensor base address. Output - The pin is reserved for use to flag critical module temperature. Input - This signal resets the DDR3 SDRAM REV 0.1 01/2010 4 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC64BH4B0NF / NT2GC64B88B0NF / NT4GB8HB0NF 1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64 PC3-8500 / PC3-10600 Unbuffered DDR3 SDRAM DIMM Functional Block Diagram [1GB - 1 Rank, 128Mx16 DDR3 SDRAMs] DQS0 DM0 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 I/O I/O I/O I/O I/O I/O I/O I/O DQS 0 1 2 3 4 5 6 7 D0 ZQ DQS1 DM1 DM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 I/O I/O I/O I/O I/O I/O I/O I/O DQS 0 1 2 3 4 5 6 7 D1 ZQ DQS2 DM2 DM DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 I/O I/O I/O I/O I/O I/O I/O I/O DQS 0 1 2 3 4 5 6 7 D2 ZQ DQS3 DM3 DM DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 SCL SA0 SA1 I/O I/O I/O I/O I/O I/O I/O I/O DQS 0 1 2 3 4 5 6 7 SCL A0 A1 A2 D3 ZQ SPD SDA WP DDR3 SDRAM CKE0, A[13:0], , , , ODT0, BA[2:0], VTT DDR3 SDRAM CK REV 0.1 01/2010 VDD VDDSPD VDD/VDDQ VREFDQ VSS VREFCA BA0-BA2 A0-A13 CKE0 ODT0 CK0 SPD D0-D7 D0-D7 D0-D7 D0-D7 BA0-BA2: SDRAMs D0-D7 A0-A13: SDRAMs D0-D7 : SDRAMs D0-D7 : SDRAMs D0-D7 CKE: SDRAMs D0-D7 : SDRAMs D0-D7 ODT: SDRAMs D0-D7 CK: SDRAMs D0-D7 : SDRAMs D0-D7 : SDRAMs D0-D7 Notes : 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be maintained as shown. 3. For each DRAM, a unique ZQ resistor is connected to ground. The ZQ resistor is 2401%. 4. One SPD exists per module. 5 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC64BH4B0NF / NT2GC64B88B0NF / NT4GB8HB0NF 1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64 PC3-8500 / PC3-10600 Unbuffered DDR3 SDRAM DIMM Functional Block Diagram [2GB - 1 Rank, 256Mx8 DDR3 SDRAMs] DQS0 DM0 DQS4 DM4 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 I/O I/O I/O I/O I/O I/O I/O I/O DQS 0 1 2 3 4 5 6 7 DM DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 D0 ZQ DQS1 DM1 I/O I/O I/O I/O I/O I/O I/O I/O DQS 0 1 2 3 4 5 6 7 DM DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 D1 ZQ DQS2 DM2 I/O I/O I/O I/O I/O I/O I/O I/O DQS 0 1 2 3 4 5 6 7 SA0 SA1 D2 ZQ I/O I/O I/O I/O I/O I/O I/O I/O DQS 0 1 2 3 4 5 6 7 SCL A0 A1 A2 D3 ZQ SPD SDA WP CKE0, A[13:0], , , , ODT0, BA[2:0], VTT DDR3 SDRAM CK 01/2010 D4 ZQ 0 1 2 3 4 5 6 7 I/O I/O I/O I/O I/O I/O I/O I/O DQS D5 ZQ 0 1 2 3 4 5 6 7 DM DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DDR3 SDRAM REV 0.1 DQS D6 ZQ DQS7 DM7 DM SCL I/O I/O I/O I/O I/O I/O I/O I/O DM DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS DQS6 DM6 DM DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 0 1 2 3 4 5 6 7 DQS5 DM5 DM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 I/O I/O I/O I/O I/O I/O I/O I/O VDD VDDSPD VDD/VDDQ VREFDQ VSS VREFCA BA0-BA2 A0-A13 CKE0 ODT0 CK0 I/O I/O I/O I/O I/O I/O I/O I/O 0 1 2 3 4 5 6 7 DQS D7 ZQ SPD D0-D7 D0-D7 D0-D7 D0-D7 BA0-BA2: SDRAMs D0-D7 A0-A13: SDRAMs D0-D7 : SDRAMs D0-D7 : SDRAMs D0-D7 CKE: SDRAMs D0-D7 : SDRAMs D0-D7 ODT: SDRAMs D0-D7 CK: SDRAMs D0-D7 : SDRAMs D0-D7 : SDRAMs D0-D7 Notes : 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be maintained as shown. 3. For each DRAM, a unique ZQ resistor is connected to ground. The ZQ resistor is 2401%. 4. One SPD exists per module. 6 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC64BH4B0NF / NT2GC64B88B0NF / NT4GB8HB0NF 1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64 PC3-8500 / PC3-10600 Unbuffered DDR3 SDRAM DIMM Functional Block Diagram [4GB - 2 Ranks, 256Mx8 DDR3 SDRAMs] DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS4 DM4 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 D0 I/O 4 I/O 5 I/O 6 I/O 7 DQS DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 D8 I/O 4 I/O 5 I/O 6 I/O 7 ZQ DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 ZQ DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 D1 I/O 4 I/O 5 I/O 6 I/O 7 DQS DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 D9 I/O 4 I/O 5 I/O 6 I/O 7 ZQ DQS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 ZQ DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS D4 ZQ DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 D12 I/O 4 I/O 5 I/O 6 I/O 7 DQS DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 D13 I/O 4 I/O 5 I/O 6 I/O 7 DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS ZQ DQS DQS D5 ZQ ZQ DQS6 DQS6 DM6 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 D2 I/O 4 I/O 5 I/O 6 I/O 7 DQS DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 D10 I/O 4 I/O 5 I/O 6 I/O 7 ZQ DQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 ZQ DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 CS DQS5 DM5 DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 D6 I/O 4 I/O 5 I/O 6 I/O 7 DQS DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 D7 I/O 4 I/O 5 I/O 6 I/O 7 DQS ZQ CS DQS D14 ZQ DQS7 DM7 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 D3 I/O 4 I/O 5 I/O 6 I/O 7 DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 ZQ CS DQS DQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 D11 ZQ VDDSPD VDD/VDDQ VREFDQ VSS VREFCA BA0-BA2 A0-A13 CKE0 CKE1 ODT0 ODT1 CK0 CK1 DDR3 SDRAM CKE[1:0], A[13:0], , , , ODT[1:0], BA[2:0], [1:0] VTT DDR3 SDRAM CK SCL SA0 SA1 VDD SCL A0 A1 A2 SPD SDA WP ZQ DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 D15 I/O 4 I/O 5 I/O 6 I/O 7 DQS ZQ SPD D0-D15 D0-D15 D0-D15 D0-D15 BA0-BA2: SDRAMs D0-D15 A0-A13: SDRAMs D0-D15 : SDRAMs D0-D15 : SDRAMs D0-D15 : SDRAMs D0-D15 CKE: SDRAMs D0-D7 CKE: SDRAMs D8-D15 ODT: SDRAMs D0-D7 ODT: SDRAMs D8-D15 CK: SDRAMs D0-D7 : SDRAMs D0-D7 CK: SDRAMs D8-D15 : SDRAMs D8-D15 : SDRAMs D8-D15 Notes : 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be maintained as shown. 3. For each DRAM, a unique ZQ resistor is connected to ground. The ZQ resistor is 2401%. 4. One SPD exists per module. REV 0.1 01/2010 7 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC64BH4B0NF / NT2GC64B88B0NF / NT4GB8HB0NF 1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64 PC3-8500 / PC3-10600 Unbuffered DDR3 SDRAM DIMM Serial Presence Detect (Part 1 of 2) [NT1GC64BH4B0NF, 1GB - 1 Rank, 128Mx16 DDR3 SDRAMs] SPD Entry Value Byte Serial PD Data Entry (Hex.) Description 0 CRC range, EEPROM bytes, bytes used 1 SPD revision 2 DRAM device type 3 Module type (form factor) 4 SDRAM Device density and banks 5 SDRAM device row and column count 6 Module minimum nominal voltage 7 Module ranks and device DQ count 8 ECC tag and module memory Bus width 9 Fine timebase dividend/divisor (in ps) 10 -BE -CG -BE -CG CRC Covers Bytes: 0~116, Total SPD Bytes: 256, SPD Bytes Used: 176, CRC Covers Bytes: 0~116, Total SPD Bytes: 256, SPD Bytes Used: 176, -- -- Revision 1.0 Revision 1.0 -- -- DDR3 SDRAM DDR3 SDRAM -- -- UDIMM UDIMM -- -- 8 banks, 2Gb 8 banks, 2Gb -- -- 14 rows, 10 columns 14 rows, 10 columns -- -- 1.5 V 1.5 V -- -- 1 rank, 16 bits 1 rank, 16 bits -- -- Non ECC, 64bits Non ECC, 64bits -- -- 2.5ps 2.5ps -- -- Medium timebase dividend 1ns 1ns -- -- 11 Medium timebase divisor 8ns 8ns -- -- 12 Minimum SDRAM cycle time (tCKmin) 1.875ns 1.5ns -- -- 13 Reserved Undefined Undefined -- -- 14 CAS latencies supported 6,7,8 6,7,8,9 -- -- 15 CAS latencies supported Undefined Undefined -- -- 16 Minimum CAS latency time (tAAmin) 13.125ns 13.125ns -- -- 17 Minimum write recovery time (tWRmin) 15ns 15ns -- -- 18 Minimum -to- delay (tRCDmin) 13.125ns 13.125ns -- -- 19 Minimum Row Active to Row Active delay (tRRDmin) 7.5ns 6ns -- -- 20 Minimum row Precharge delay (tRPmin) 13.125ns 13.125ns -- -- 21 Upper nibble for tRAS and tRC 22 Minimum Active-to-Precharge delay (tRASmin) 23 Minimum Active-to-Active/Refresh delay (tRCmin) 24 1,1 1,1 -- -- 37.5ns 36ns -- -- 50.625ns 49.125ns -- -- Minimum refresh recovery delay (tRFCmin) LSB (Combo bytes 24,25) (Combo bytes 24,25) -- -- 25 Minimum refresh recovery delay (tRFCmin) MSB 110ns 110ns -- -- 26 Minimum internal Write-to-Read command delay (tWTRmin) 7.5ns 7.5ns -- -- 27 7.5ns 7.5ns -- -- 28 Minimum internal Read-to-Precharge command delay (tRTPmin) Minimum four active window delay (tFAWmin) LSB (Combo byte 28, 29) (Combo byte 28, 29) -- -- 29 Minimum four active window delay (tFAWmin) MSB 37.5ns 30ns -- -- RZQ / 6, RZQ / 7, DLL-Off Mode Support, RZQ / 6, RZQ / 7, DLL-Off Mode Support, -- -- Extended Temperature Range, ASR, ODTS, PASR, Extended Temperature Range, ASR, ODTS, PASR, -- -- Non Thermal Sensor Support Non Thermal Sensor Support -- -- Standard Monolithic Device Standard Monolithic Device -- -- Undefined Undefined -- -- 30 SDRAM device output drivers suported 31 SDRAM device thermal and refresh options 32 Module Thermal Sensor 33 SDRAM Device Type 34-59 Reserved 60 Module height (nominal) 29 height 30 mm 29 height 30 mm -- -- 61 Module thickness (Max) Back: 1 < thickness 2 mm, Front: 1 < thickness 2 mm, Back: 1 < thickness 2 mm, Front: 1 < thickness 2 mm, -- -- 62 Raw Card ID reference Raw Card A Raw Card A -- -- 63 DRAM address mapping edge connector Undefined Undefined -- -- Reserved Undefined Undefined -- -- Nanya Technology Nanya Technology -- -- Undefined Undefined -- -- Calculated Value Calculated Value -- -- 64-116 117-118 Module manufacture ID 119-121 Module manufacturer Information 126-127 CRC REV 0.1 01/2010 8 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC64BH4B0NF / NT2GC64B88B0NF / NT4GB8HB0NF 1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64 PC3-8500 / PC3-10600 Unbuffered DDR3 SDRAM DIMM Serial Presence Detect (Part 2 of 2) [NT1GC64BH4B0NF, 1GB - 1 Rank, 128Mx16 DDR3 SDRAMs] SPD Entry Value Byte Serial PD Data Entry (Hex.) Description 128-145 Module part number -BE -CG -BE -CG ASCII values ASCII values -- -- 146 Module die revision Undefined Undefined -- -- 147 Module PCB revision Undefined Undefined -- -- 148-149 DRAM device manufacturer ID Nanya Technology Nanya Technology -- -- 150-175 Manufacturer reserved Undefined Undefined -- -- 176-255 Customer reserved Undefined Undefined -- -- REV 0.1 01/2010 9 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC64BH4B0NF / NT2GC64B88B0NF / NT4GB8HB0NF 1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64 PC3-8500 / PC3-10600 Unbuffered DDR3 SDRAM DIMM Serial Presence Detect (Part 1 of 2) [NT2GC64B88B0NF, 2GB - 1 Rank, 256Mx8 DDR3 SDRAMs] SPD Entry Value Byte Serial PD Data Entry (Hex.) Description 0 CRC range, EEPROM bytes, bytes used 1 SPD revision 2 DRAM device type 3 Module type (form factor) 4 SDRAM Device density and banks 5 SDRAM device row and column count 6 Module minimum nominal voltage 7 Module ranks and device DQ count 8 ECC tag and module memory Bus width 9 Fine timebase dividend/divisor (in ps) 10 -BE -CG -BE -CG CRC Covers Bytes: 0~116, Total SPD Bytes: 256, SPD Bytes Used: 176, CRC Covers Bytes: 0~116, Total SPD Bytes: 256, SPD Bytes Used: 176, -- -- Revision 1.0 Revision 1.0 -- -- DDR3 SDRAM DDR3 SDRAM -- -- UDIMM UDIMM -- -- 8 banks, 2Gb 8 banks, 2Gb -- -- 14 rows, 10 columns 14 rows, 10 columns -- -- 1.5 V 1.5 V -- -- 1 rank, 8 bits 1 rank, 8 bits -- -- Non ECC, 64bits Non ECC, 64bits -- -- 2.5ps 2.5ps -- -- Medium timebase dividend 1ns 1ns -- -- 11 Medium timebase divisor 8ns 8ns -- -- 12 Minimum SDRAM cycle time (tCKmin) 1.875ns 1.5ns -- -- 13 Reserved Undefined Undefined -- -- 14 CAS latencies supported 6,7,8 6,7,8,9 -- -- 15 CAS latencies supported Undefined Undefined -- -- 16 Minimum CAS latency time (tAAmin) 13.125ns 13.125ns -- -- 17 Minimum write recovery time (tWRmin) 15ns 15ns -- -- 18 Minimum -to- delay (tRCDmin) 13.125ns 13.125ns -- -- 19 Minimum Row Active to Row Active delay (tRRDmin) 7.5ns 6ns -- -- 20 Minimum row Precharge delay (tRPmin) 13.125ns 13.125ns -- -- 21 Upper nibble for tRAS and tRC 22 Minimum Active-to-Precharge delay (tRASmin) 23 Minimum Active-to-Active/Refresh delay (tRCmin) 24 1,1 1,1 -- -- 37.5ns 36ns -- -- 50.625ns 49.125ns -- -- Minimum refresh recovery delay (tRFCmin) LSB (Combo bytes 24,25) (Combo bytes 24,25) -- -- 25 Minimum refresh recovery delay (tRFCmin) MSB 110ns 110ns -- -- 26 Minimum internal Write-to-Read command delay (tWTRmin) 7.5ns 7.5ns -- -- 27 7.5ns 7.5ns -- -- 28 Minimum internal Read-to-Precharge command delay (tRTPmin) Minimum four active window delay (tFAWmin) LSB (Combo byte 28, 29) (Combo byte 28, 29) -- -- 29 Minimum four active window delay (tFAWmin) MSB 37.5ns 30ns -- -- RZQ / 6, RZQ / 7, DLL-Off Mode Support, RZQ / 6, RZQ / 7, DLL-Off Mode Support, -- -- Extended Temperature Range, ASR, ODTS, PASR, Extended Temperature Range, ASR, ODTS, PASR, -- -- Non Thermal Sensor Support Non Thermal Sensor Support -- -- Standard Monolithic Device Standard Monolithic Device -- -- Undefined Undefined -- -- 30 SDRAM device output drivers suported 31 SDRAM device thermal and refresh options 32 Module Thermal Sensor 33 SDRAM Device Type 34-59 Reserved 60 Module height (nominal) 29 height 30 mm 29 height 30 mm -- -- 61 Module thickness (Max) Back: 1 < thickness 2 mm, Front: 1 < thickness 2 mm, Back: 1 < thickness 2 mm, Front: 1 < thickness 2 mm, -- -- 62 Raw Card ID reference Raw Card B Raw Card B -- -- 63 DRAM address mapping edge connector Undefined Undefined -- -- Reserved Undefined Undefined -- -- Nanya Technology Nanya Technology -- -- Undefined Undefined -- -- Calculated Value Calculated Value -- -- 64-116 117-118 Module manufacture ID 119-121 Module manufacturer Information 126-127 CRC REV 0.1 01/2010 10 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC64BH4B0NF / NT2GC64B88B0NF / NT4GB8HB0NF 1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64 PC3-8500 / PC3-10600 Unbuffered DDR3 SDRAM DIMM Serial Presence Detect (Part 2 of 2) [NT2GC64B88B0NF, 2GB - 1 Rank, 256Mx8 DDR3 SDRAMs] SPD Entry Value Byte Serial PD Data Entry (Hex.) Description 128-145 Module part number -BE -CG -BE -CG ASCII values ASCII values -- -- 146 Module die revision Undefined Undefined -- -- 147 Module PCB revision Undefined Undefined -- -- 148-149 DRAM device manufacturer ID Nanya Technology Nanya Technology -- -- 150-175 Manufacturer reserved Undefined Undefined -- -- 176-255 Customer reserved Undefined Undefined -- -- REV 0.1 01/2010 11 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC64BH4B0NF / NT2GC64B88B0NF / NT4GB8HB0NF 1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64 PC3-8500 / PC3-10600 Unbuffered DDR3 SDRAM DIMM Serial Presence Detect (Part 1 of 2) [NT4GC64B8HB0NF, 4GB - 2 Ranks, 256Mx8 DDR3 SDRAMs] SPD Entry Value Byte Serial PD Data Entry (Hex.) Description 0 CRC range, EEPROM bytes, bytes used 1 SPD revision 2 DRAM device type 3 Module type (form factor) 4 SDRAM Device density and banks 5 SDRAM device row and column count 6 Module minimum nominal voltage 7 Module ranks and device DQ count 8 ECC tag and module memory Bus width 9 Fine timebase dividend/divisor (in ps) 10 -BE -CG -BE -CG CRC Covers Bytes: 0~116, Total SPD Bytes: 256, SPD Bytes Used: 176, CRC Covers Bytes: 0~116, Total SPD Bytes: 256, SPD Bytes Used: 176, -- -- Revision 1.0 Revision 1.0 -- -- DDR3 SDRAM DDR3 SDRAM -- -- UDIMM UDIMM -- -- 8 banks, 2Gb 8 banks, 2Gb -- -- 15 rows, 10 columns 15 rows, 10 columns -- -- 1.5 V 1.5 V -- -- 2 ranks, 8 bits 2 ranks, 8 bits -- -- Non ECC, 64bits Non ECC, 64bits -- -- 2.5ps 2.5ps -- -- Medium timebase dividend 1ns 1ns -- -- 11 Medium timebase divisor 8ns 8ns -- -- 12 Minimum SDRAM cycle time (tCKmin) 1.875ns 1.5ns -- -- 13 Reserved Undefined Undefined -- -- 14 CAS latencies supported 6,7,8 6,7,8,9 -- -- 15 CAS latencies supported Undefined Undefined -- -- 16 Minimum CAS latency time (tAAmin) 13.125ns 13.125ns -- -- 17 Minimum write recovery time (tWRmin) 15ns 15ns -- -- 18 Minimum -to- delay (tRCDmin) 13.125ns 13.125ns -- -- 19 Minimum Row Active to Row Active delay (tRRDmin) 7.5ns 6ns -- -- 20 Minimum row Precharge delay (tRPmin) 13.125ns 13.125ns -- -- 21 Upper nibble for tRAS and tRC 22 Minimum Active-to-Precharge delay (tRASmin) 23 Minimum Active-to-Active/Refresh delay (tRCmin) 24 1,1 1,1 -- -- 37.5ns 36ns -- -- 50.625ns 49.125ns -- -- Minimum refresh recovery delay (tRFCmin) LSB (Combo bytes 24,25) (Combo bytes 24,25) -- -- 25 Minimum refresh recovery delay (tRFCmin) MSB 110ns 110ns -- -- 26 Minimum internal Write-to-Read command delay (tWTRmin) 7.5ns 7.5ns -- -- 27 7.5ns 7.5ns -- -- 28 Minimum internal Read-to-Precharge command delay (tRTPmin) Minimum four active window delay (tFAWmin) LSB (Combo byte 28, 29) (Combo byte 28, 29) -- -- 29 Minimum four active window delay (tFAWmin) MSB 37.5ns 30ns -- -- RZQ / 6, RZQ / 7, DLL-Off Mode Support, RZQ / 6, RZQ / 7, DLL-Off Mode Support, -- -- Extended Temperature Range, ASR, ODTS, PASR, Extended Temperature Range, ASR, ODTS, PASR, -- -- Non Thermal Sensor Support Non Thermal Sensor Support -- -- Standard Monolithic Device Standard Monolithic Device -- -- Undefined Undefined -- -- 30 SDRAM device output drivers suported 31 SDRAM device thermal and refresh options 32 Module Thermal Sensor 33 SDRAM Device Type 34-59 Reserved 60 Module height (nominal) 29 height 30 mm 29 height 30 mm -- -- 61 Module thickness (Max) Back: 1 < thickness 2 mm, Front: 1 < thickness 2 mm, Back: 1 < thickness 2 mm, Front: 1 < thickness 2 mm, -- -- 62 Raw Card ID reference Raw Card B Raw Card B -- -- 63 DRAM address mapping edge connector Undefined Undefined -- -- Reserved Undefined Undefined -- -- Nanya Technology Nanya Technology -- -- Undefined Undefined -- -- Calculated Value Calculated Value -- -- 64-116 117-118 Module manufacture ID 119-121 Module manufacturer Information 126-127 CRC REV 0.1 01/2010 12 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC64BH4B0NF / NT2GC64B88B0NF / NT4GB8HB0NF 1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64 PC3-8500 / PC3-10600 Unbuffered DDR3 SDRAM DIMM Serial Presence Detect (Part 2 of 2) [NT4GC64B8HB0NF, 4GB - 2 Ranks, 256Mx8 DDR3 SDRAMs] SPD Entry Value Byte Serial PD Data Entry (Hex.) Description 128-145 Module part number -BE -CG -BE -CG ASCII values ASCII values -- -- 146 Module die revision Undefined Undefined -- -- 147 Module PCB revision Undefined Undefined -- -- 148-149 DRAM device manufacturer ID Nanya Technology Nanya Technology -- -- 150-175 Manufacturer reserved Undefined Undefined -- -- 176-255 Customer reserved Undefined Undefined -- -- REV 0.1 01/2010 13 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC64BH4B0NF / NT2GC64B88B0NF / NT4GB8HB0NF 1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64 PC3-8500 / PC3-10600 Unbuffered DDR3 SDRAM DIMM Environmental Requirements Symbol Rating Units Note TOPR Module Operating Temperature Range (ambient) Parameter 0 to 55 C 3 HOPR Operating Humidity (relative) 10 to 90 % 1 TSTG Storage Temperature (Plastic) -55 to 100 C 1 HSTG Storage Humidity (without condensation) 5 to 95 % 1 PBAR Barometric Pressure (operating & storage) 105 to 69 K Pascal 1, 2 Note: 1. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only and device functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Up to 9850 ft. 3. The component maximum case temperature shall not exceed the value specified in the component spec. Absolute Maximum DC Ratings Symbol VDD VDDQ VIN, VOUT TSTG Parameter Rating Units Note Voltage on VDD pins relative to Vss -0.4 V ~ 1.975 V V 1, 3 Voltage on VDDQ pins relative to Vss -0.4 V ~ 1.975 V V 1, 3 Voltage on I/O pins relative to Vss -0.4 V ~ 1.975 V V 1 -55 to +100 C 1, 2 Storage Temperature Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 3. VDD and VDDQ must be within 300 mV of each other at all times;and VREF must be not greater Operating temperature Conditions Symbol TOPER Rating Units Note Normal Operating Temperature Range Parameter 0 to 85 C 1, 2 Extended Temperature Range 85 to 95 C 1, 3 Note: 1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measurement conditions, please refer to the JEDEC document JESD51-2. 2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0 to 85 C under all operating conditions 3. Some applications require operation of the DRAM in the Extended Temperature Range between 85 C and 95 C case temperature. Full specifications are supported in this range, but the following additional conditions apply: a) Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 s. It is also possible to specify a component with 1X refresh (tREFI to 7.8s) in the Extended Temperature Range. Please refer to supplier data sheet and/or the DIMM SPD for option availability. b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b) or enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b). Please refer to the supplier data sheet and/or the DIMM SPD for Auto Self-Refresh option availability, Extended Temperature Range support and tREFI requirements in the Extended Temperature Range. REV 0.1 01/2010 14 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC64BH4B0NF / NT2GC64B88B0NF / NT4GB8HB0NF 1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64 PC3-8500 / PC3-10600 Unbuffered DDR3 SDRAM DIMM DC Electrical Characteristics and Operating Conditions Symbol VDD VDDQ Min Typ Max Units Notes Supply Voltage Parameter 1.425 1.5 1.575 V 1,2 Output Supply Voltage 1.425 1.5 1.575 V 1,2 Note: 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together. Single-Ended AC and DC Input Levels for Command and Address Symbol Parameter DDR3-1066 (-BE/-BF) Min. DDR3-1333 (-CG) Max. Min. Max. Units Note VIH.CA(DC) DC Input Logic High Vref + 0.100 VDD Vref + 0.100 VDD V 1 VIL.CA(DC) DC Input Logic Low VSS Vref - 0.100 VSS Vref - 0.100 V 1 VIH.CA(AC) AC Input Logic High Vref + 0.175 Note 2 Vref + 0.175 Note 2 V 1, 2 VIL.CA(AC) AC Input Logic Low Note 2 Vref - 0.175 Note 2 Vref - 0.175 V 1, 2 VIH.CA(AC150) AC Input Logic High Vref + 0.15 Note 2 Vref + 0.15 Note 2 V 1, 2 VIL.CA(AC150) AC Input Logic Low Note 2 Vref - 0.15 Note 2 Vref - 0.15 V 1, 2 0.49 x VDD 0.51 x VDD 0.49 x VDD 0.51 x VDD V 3, 4 VRefCA(DC) Reference Voltage for ADD, CMD Inputs Note: 1. For input only pins except RESET#. Vref = VrefCA(DC). 2. See "Overshoot and Undershoot Specifications" in the device datasheet. 3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 15 mV). 4. For reference: approx. VDD/2 +/- 15 mV. Single-Ended AC and DC Input Levels for DQ and DM Symbol Parameter VIH.DQ(DC) DC Input Logic High DDR3-1066 (-BE/-BF) DDR3-1333 (-CG) Units Note VDD V 1 Min. Max. Min. Max. Vref + 0.100 VDD Vref + 0.100 VIL.DQ(DC) DC Input Logic Low VSS Vref - 0.100 VSS Vref - 0.100 V 1 VIH.DQ(AC) AC Input Logic High Vref + 0.175 Note 2 Vref + 0.15 Note 2 V 1, 2, 5 VIL.DQ(AC) AC Input Logic Low Note 2 Vref - 0.175 Note 2 Vref - 0.15 V 1, 2, 5 0.49 x VDD 0.51 x VDD 0.49 x VDD 0.51 x VDD V 3, 4 VRefDQ(DC) Reference Voltage for DQ, DM Inputs Note: 1. For input only pins except RESET#. Vref = VrefDQ(DC). 2. See "Overshoot and Undershoot Specifications" in the device datasheet. 3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 15 mV). 4. For reference: approx. VDD/2 +/- 15 mV. 5. Single-ended swing requirement for DQS, DQS# is 350 mV (peak to peak). Differential swing requirement for DQS - DQS# is 700 mV (peak to peak). REV 0.1 01/2010 15 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC64BH4B0NF / NT2GC64B88B0NF / NT4GB8HB0NF 1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64 PC3-8500 / PC3-10600 Unbuffered DDR3 SDRAM DIMM Operating, Standby, and Refresh Currents TCASE = 0 C ~ 85 C; VDDQ = VDD = 1.5V 0.075V [1GB - 1 Rank, 128Mx16 DDR3 SDRAMs] Symbol Parameter/Condition PC3-8500 PC3-10600 (-BE/-BF) (-CG) Unit IDD0 Operating One Bank Active-Precharge Current -- -- mA IDD1 Operating One Bank Active-Read-Precharge Current -- -- mA IDD2P0 Precharge Power-Down Current Slow Exit -- -- mA IDD2P1 Precharge Power-Down Current Fast Exit -- -- mA IDD2Q Precharge Quiet Standby Current -- -- mA IDD2N Precharge Standby Current -- -- mA IDD3P Active Power-Down Current -- -- mA IDD3N Active Standby Current -- -- mA IDD4R Operating Burst Read Current -- -- mA IDD4W Operating Burst Write Current -- -- mA IDD5B Burst Refresh Current -- -- mA Self Refresh Current: Normal Temperature Range -- -- mA Operating Bank Interleave Read Current -- -- mA PC3-8500 PC3-10600 (-BE/-BF) (-CG) IDD6 IDD7 Operating, Standby, and Refresh Currents TCASE = 0 C ~ 85 C; VDDQ = VDD = 1.5V 0.075V [2GB - 1 Rank, 256Mx8 DDR3 SDRAMs] Symbol Unit IDD0 Operating One Bank Active-Precharge Current -- -- mA IDD1 Operating One Bank Active-Read-Precharge Current -- -- mA IDD2P0 Precharge Power-Down Current Slow Exit -- -- mA IDD2P1 Precharge Power-Down Current Fast Exit -- -- mA IDD2Q Precharge Quiet Standby Current -- -- mA IDD2N Precharge Standby Current -- -- mA IDD3P Active Power-Down Current -- -- mA IDD3N Active Standby Current -- -- mA -- mA IDD4R Operating Burst Read Current -- IDD4W Operating Burst Write Current -- -- mA IDD5B Burst Refresh Current -- -- mA IDD6 Self Refresh Current: Normal Temperature Range -- -- mA IDD7 Operating Bank Interleave Read Current -- -- mA REV 0.1 01/2010 Parameter/Condition 16 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC64BH4B0NF / NT2GC64B88B0NF / NT4GB8HB0NF 1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64 PC3-8500 / PC3-10600 Unbuffered DDR3 SDRAM DIMM Operating, Standby, and Refresh Currents TCASE = 0 C ~ 85 C; VDDQ = VDD = 1.5V 0.075V [4GB - 2 Ranks, 256Mx8 DDR3 SDRAMs] Symbol PC3-8500 PC3-10600 (-BE/-BF) (-CG) Unit IDD0 Operating One Bank Active-Precharge Current -- -- mA IDD1 Operating One Bank Active-Read-Precharge Current -- -- mA IDD2P0 Precharge Power-Down Current Slow Exit -- -- mA IDD2P1 Precharge Power-Down Current Fast Exit -- -- mA IDD2Q Precharge Quiet Standby Current -- -- mA IDD2N Precharge Standby Current -- -- mA IDD3P Active Power-Down Current -- -- mA IDD3N Active Standby Current -- -- mA IDD4R Operating Burst Read Current -- -- mA IDD4W Operating Burst Write Current -- -- mA IDD5B Burst Refresh Current -- -- mA Self Refresh Current: Normal Temperature Range -- -- mA Operating Bank Interleave Read Current -- -- mA IDD6 IDD7 REV 0.1 01/2010 Parameter/Condition 17 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC64BH4B0NF / NT2GC64B88B0NF / NT4GB8HB0NF 1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64 PC3-8500 / PC3-10600 Unbuffered DDR3 SDRAM DIMM Speed Bins Speed Bin DDR3-1066 (-BE) DDR3-1333 (-CG) 7-7-7 9-9-9 Unit CL - tRCD - tRP Parameter Symbol Min Max Min Max tAA 13.125 20 13.5 20 ns tRCD 13.125 - 13.5 - ns tRP 13.125 - 13.5 - ns tRC 50.625 - 49.5 - ns tRAS 37.5 9*tREFI 36 9*tREFI ns CWL=5 tCK(AVG) 3 3.3 3 3.3 CWL=6, 7 tCK(AVG) Reserved CWL=5 tCK(AVG) CWL=6, 7 tCK(AVG) Reserved Reserved CWL=5 tCK(AVG) Reserved Reserved CWL=6 tCK(AVG) CWL=7 tCK(AVG) Reserved Reserved CWL=5 tCK(AVG) Reserved Reserved CWL=6 tCK(AVG) CWL=7 tCK(AVG) Reserved Reserved CWL=5, 6 tCK(AVG) Reserved Reserved CWL=7 tCK(AVG) Reserved CWL=5, 6 tCK(AVG) Reserved CWL=7 tCK(AVG) Reserved Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period ns CL = 5 2.5 3.3 Reserved 2.5 3.3 ns CL = 6 CL = 7 CL = 8 1.875 <2.5 1.875 <2.5 1.875 1.875 <2.5 <2.5 1.5 <1.875 Reserved ns CL = 10 01/2010 ns ns CL = 9 REV 0.1 ns 1.5 <1.875 Supported CL settings 5, 6, 7, 8 5, 6, 7, 8, 9, (10) nCK Supported CWL Settings 5, 6 5, 6, 7 nCK 18 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC64BH4B0NF / NT2GC64B88B0NF / NT4GB8HB0NF 1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64 PC3-8500 / PC3-10600 Unbuffered DDR3 SDRAM DIMM AC Timing Specifications for DDR3 SDRAM Devices Used on Module Symbol Clock Timing tCK(DLL_OF tCK(avg) tCH(avg) tCL(avg) Minimum Clock Cycle Time (DLL off mode) Average Clock Period(Refer to "Standard Speed Average high pulse width Average low pulse width tCK(abs) Absolute Clock Period tCH(abs) tCL(abs) JIT(per) tJIT(per,lck) tJIT(cc) tJIT(cc,lck) tERR(2per) tERR(3per) tERR(4per) tERR(5per) tERR(6per) tERR(7per) tERR(8per) tERR(9per) tERR(10per) tERR(11per) tERR(12per) Absolute high pulse width Absolute low pulse width Clock Period Jitter Clock Period Jitter during DLL locking period Cycle to Clcyle Period Jitter Cycle to Cycle Period Jitter Cumulative error accross 2 cycles Cumulative error accross 3 cycles Cumulative error accross 4cycles Cumulative error accross 5cycles Cumulative error accross 6 cycles Cumulative error accross 7 cycles Cumulative error accross 8 cycles Cumulative error accross 9 cycles Cumulative error accross 10 cycles Cumulative error accross 11 cycles Cumulative error accross 12 cycles tERR(nper) Cumulative error accross n=13,14,..,49,50 cycles Data Timing tDQSQ DQS, DQS to DQ skew per group, per access tQH DQ output hold time from DQS, DQS tLZ(DQ) DQ low-impedence time from CK / tHZ(DQ) DQ high-impedence time from CK / tDS(base) Data Setup time to DQS, DQS referenced to AC175 Vih(ac)/ Vil(ac) levels tDS(base) Data Setup time to DQS, DQS referenced to AC150 Vih(ac)/ Vil(ac) levels tDH(base) Data Hold time to DQS, DQS referenced to Vih(dc)/ DC100 Vil(dc) levels tDIPW DQ and DM Input pulse width for each input Data Strobe Timing tRPRE DQS, DQS differential READ Preamble tRPST DQS, DQS differential READ Postamble tQSH DQS, DQS differential output high time tQSL DQS, DQS differential output low time tWPRE DQS, DQS differential WRITE Preamble tWPST DQS, DQS differential WRITE Postamble DQS, DQS rising edge output access time from tDQSCK rising CK, tLZ(DQS) DQS, DQS low-impedance time (Referenced from DQS, DQS high-impedance time (Referenced from tHZ(DQS) RL+BL/2) tDQSL DQS, DQS differential input low pulse width tDQSH DQS, DQS differential input high pulse width tDQSS DQS, DQS rising edge to CK, rising edge DQS, DQS falling edge setup time to CK, rising tDSS edge tDSH DQS, DQS falling edge hold time to CK, rising REV 0.1 01/2010 DDR3-1066 (-BE) min max Parameter DDR3-1333 (-CG) min max Unit 8 - 8 - ns 0.47 0.47 0.53 0.53 0.47 0.47 0.53 0.53 tCK(avg) tCK(avg) tCK(avg)min + tJIT(per)min tCK(avg)max + tCK(avg)min + tCK(avg)max + tJIT(per)max tJIT(per)min tJIT(per)max 0.43 0.43 -90 -80 90 80 0.43 0.43 -80 -70 180 160 -132 -157 -175 -188 -200 -209 -217 -224 -231 -237 -242 80 70 160 140 132 157 175 188 200 209 217 224 231 237 242 -118 118 -140 140 -155 155 -168 168 -177 177 -186 186 -193 193 -200 200 -205 205 -210 210 -215 215 tERR(npr)min tERR(npr)max tERR(npr)min = tERR(npr)max = = (1+ = (1+ (1+ 0.68In(n)) * (1+ 0.68In(n)) * 0.68In(n)) * 0.68In(n)) * tJIT(per)min tJIT(per)max tJIT(per)min tJIT(per)max ps tCK(avg) tCK(avg) ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps 0.38 -500 - 125 250 250 ps tCK(avg) ps ps 25 - - ps 75 30 - 100 65 - 490 400 - 0.38 -600 - 150 300 300 ps 0.9 0.3 0.38 0.38 0.9 0.3 Note 19 Note 11 - 0.9 0.3 0.4 0.4 0.9 0.3 Note 19 Note 11 - tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg) -300 300 -255 255 ps -600 300 -500 250 ps - 300 - 250 ps 0.45 0.45 -0.25 0.55 0.55 0.25 0.45 0.45 -0.25 0.55 0.55 0.25 tCK(avg) tCK(avg) tCK(avg) 0.2 - 0.2 - tCK(avg) 0.2 - 0.2 - tCK(avg) 19 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC64BH4B0NF / NT2GC64B88B0NF / NT4GB8HB0NF 1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64 PC3-8500 / PC3-10600 Unbuffered DDR3 SDRAM DIMM Symbol DDR3-1066 (-BE) min max Parameter Command and Address Timing tDLLK DLL Locking time Internal READ command to PRECHARGE tRTP Command delay Delay from start of internal write transaction to tWTR internal read command tWR WRITE recovery time tMRD Mode Register Set command cycle time tMOD Mode Register Set command update delay tCCD CAS to CAS command delay 512 max(4nCK, 7.5ns) max(4nCK, 7.5ns) 15 4 max(12nCK, 15ns) 4 tDAL Auto Precharge write recovery + precharge time WR + roundup (tRP/tCK(avg)) tMPRR End of MPR Read burst to MSR for MPR (exit) ACTIVE to PRECHARGE command period Refer to "Standard Speed Bins" ACTIVE to ACTIVE command period (1k page size tRRD -x4/x8) ACTIVE to ACTIVE command period (2k page size tRRD -x16) tFAW Four activate window (1k page size - x4/x8) tFAW Four activate window (2k page size - x16) Command and Address setup time to CK, tIS(base) referenced Vih(ac) / Vil(ac) levels Command and Address hold time from CK, tIH(base) referenced Vih(ac) / Vil(ac) levels tIS(base) Commad and Address setup time to CK, AC150 referenced to Vih(ac) / Vil(ac) levels Calibration Timing tZQinit Power-up and RESET calibration time tZQoper Normal operation Full calibration time tZQCS normal operation Short calibration time Reset Timing 1 - - DDR3-1333 (-CG) min max 512 max(4nCK, 7.5ns) max(4nCK, 7.5ns) 15 4 max(12nCK, 15ns) 4 - nCK - ns nCK - WR + roundup (tRP/tCK(avg)) 1 Unit - nCK nCK nCK tRAS tXPR Exit Reset from CKE HIGH to a valid command max(4nCK, 7.5ns) max(4nCK, 10ns) 37.5 50 - max(4nCK, 6ns) max(4nCK, 7.5ns) 30 45 0 0 ns ns 125 65 ps 200 140 ps ps - - 65+125 512 256 64 - 512 256 64 - max(5nCK, tRFC(min) +10ns) - max(5nCK, tRFC(min) +10ns) - nCK nCK nCK Self RefreshTimings max(5nCK, tRFC(min) +10ns) tXSDLL Exit Self Refresh to Commands requiring a locked tDLLK(min) Minimum CKE low width for Self Refresh entry to tCKE(min)+1nC tCKESR exit timing K Valid Clock Requirement after Self Refresh Entry max(5nCK, tCKSRE (SRE) or Power Down Entry (PDE) 10ns) Valid Clock Requirement before Self Refresh max(5nCK, tCKSRX Exit(SRX) or Power-Down Exit (PDX) or Reset Exit 10ns) Power Down Timings Exit Power Down with DLL on to any valid max(3nCK, tXP command; Exit Precharge Power Down with DLL 7.5ns) frozen to commands not requiring a locked DLL Exit Precharge Power Down with DLL frozen to max(10nCK, tXPDLL commands requiring a locked DLL 24ns) max(3nCK, tCKE CKE minimm pulse width 5.625ns) tCPDED Command Pass disable delay 1 tPD Power Down Entry to Exit Timing tCKE(min) tACTPDEN Timing of ACT command to Power Down entry 1 tPRPDEN Timing of PRE or PREA command to Power Down 1 tRDPDEN Timing of RD/RDA command to Power Down entry RL + 4 + 1 tXS REV 0.1 01/2010 Exit Self Refresh to Commands not requiring a locked DLL - 9tREFI - max(5nCK, tRFC(min) +10ns) tDLLK(min) tCKE(min)+1n CK max(5nCK, 10ns) max(5nCK, 10ns) max(3nCK, 6ns) max(10nCK, 24ns) max(3nCK, 5.625ns) 1 tCKE(min) 1 1 RL + 4 + 1 - nCK - 9tREFI - nCK nCK nCK nCK 20 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC64BH4B0NF / NT2GC64B88B0NF / NT4GB8HB0NF 1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64 PC3-8500 / PC3-10600 Unbuffered DDR3 SDRAM DIMM Symbol DDR3-1066 (-BE) min max Parameter tWRPDEN Timing of WR command to Power Down entry (BL8OTF, BL8MRS, BC4OTF) WL + 4 + (tWR/tCK(avg)) - tWRAPDEN Timing of WRA command to Power Down entry (BL8OTF, BL8MRS, BC4OTF) WL + 4 + WR + 1 - tWRPDEN Timing of WR command to Power Down entry (BC4MRS) WL + 2 + (tWR/tCK(avg)) - Timing of WRA command to Power Down entry (BC4MRS) Timing of REF command to Power Down entry Timing of MRS command to Power Down entry WL + 2 + WR + 1 1 tMOD(min) tWRAPDEN tREFPDEN tMRSPDEN ODT Timings ODT high time without write command or with write command and BC4 tODTH8 ODT high time without write command oand BL8 Asynchronous RTT turn-on delay (Power-Down with tAONPD DLL frozen) Asynchronous RTT turn-off delay (Power Down with tAOFPD DLL frozen) tAON RTT turn-on RTT_NOM and RTT_WR turn-off time from tAOF ODTLoff reference tADC RTT dynamic change skew Write Leveling Timings First DQS/DQS rising edge after write leveling tWLMRD mode is programmed tWLDQSEN DQS/DQS delay after write leveling mode is Write leveling setup time from rising CK, CK tWLS crossing to rising DQS, DQS crossing Write leveling hold time from rising DQS, DQS tWLH crossing to rising CK, CK crossing tWLO Write leveling output delay tWLOE Write levleing output error tRFC REF command to ACT or REF command time tREFI Average period refresh interval (0CtCASE85C) tREFI Average period refresh interval (85C<tCASE95C) tODTH4 REV 0.1 01/2010 4 - DDR3-1333 (-CG) min max WL + 4 + (tWR/tCK(avg) ) WL + 4 + WR +1 WL + 2 + (tWR/tCK(avg) ) WL + 2 + WR +1 1 tMOD(min) - - 4 6 - 2 8.5 Unit nCK nCK nCK nCK nCK - nCK 6 - nCK 2 8.5 ns ns 2 8.5 2 8.5 -300 300 -250 250 ps 0.3 0.7 0.3 0.7 tCK(avg) 0.3 0.7 0.3 0.7 tCK(avg) 40 - 40 - nCK 25 - 25 - nCK 245 - 195 - ps 245 - 195 - ps 0 0 9 2 0 0 9 2 ns ns ns us us 110 7.8 3.9 110 7.8 3.9 21 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC64BH4B0NF / NT2GC64B88B0NF / NT4GB8HB0NF 1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64 PC3-8500 / PC3-10600 Unbuffered DDR3 SDRAM DIMM Package Dimensions [NT1GC64BH4B0NF, 1GB - 1 Rank, 128Mx16 DDR3 SDRAMs] FRONT 133.35 +/- 0.15 2.57 Max. Detail B Detail A 5.175 30.00 +0.5/-0.15 17.30 9.50 3.0 (x4) SIDE 47.00 71.00 5.00 1.27 +0.07/-0.10 BACK 2.50 Detail B 4.00 3.80 Detail A 0.80 +/- 0.05 1.00 Pitch 1.50 +/- 0.10 Units: Millimeters Note: Device position and scale are only for reference. REV 0.1 01/2010 22 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC64BH4B0NF / NT2GC64B88B0NF / NT4GB8HB0NF 1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64 PC3-8500 / PC3-10600 Unbuffered DDR3 SDRAM DIMM Package Dimensions [NT2GC64B88B0NF, 2GB - 1 Rank, 256Mx8 DDR3 SDRAMs] FRONT 133.35 +/- 0.15 2.57 Max. Detail B Detail A 5.175 30.00 +0.5/-0.15 17.30 9.50 3.0 (x4) SIDE 47.00 71.00 5.00 1.27 +0.07/-0.10 BACK 2.50 Detail B 4.00 3.80 Detail A 0.80 +/- 0.05 1.00 Pitch 1.50 +/- 0.10 Units: Millimeters REV 0.1 01/2010 23 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC64BH4B0NF / NT2GC64B88B0NF / NT4GB8HB0NF 1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64 PC3-8500 / PC3-10600 Unbuffered DDR3 SDRAM DIMM Package Dimensions [NT4GC64B8HB0NF, 4GB - 2 Ranks, 256Mx8 DDR3 SDRAMs] FRONT 133.35 +/- 0.15 4.00 Max. Detail B Detail A 5.175 30.00 +0.5/-0.15 17.30 9.50 3.0 (x4) SIDE 47.00 71.00 5.00 1.27 +0.07/-0.10 BACK 2.50 Detail B 4.00 3.80 Detail A 0.80 +/- 0.05 1.00 Pitch 1.50 +/- 0.10 Units: Millimeters Note: Device position and scale are only for reference. REV 0.1 01/2010 24 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT1GC64BH4B0NF / NT2GC64B88B0NF / NT4GB8HB0NF 1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64 PC3-8500 / PC3-10600 Unbuffered DDR3 SDRAM DIMM Revision Log Rev Date 0.1 01/2010 Modification Preliminary Release Nanya Technology Corporation Hwa Ya Technology Park 669 Fu Hsing 3rd Rd., Kueishan, Taoyuan, 333, Taiwan, R.O.C. Tel: +886-3-328-1688 Please visit our home page for more information: www.nanya.com Printed in Taiwan (c) 2010 REV 0.1 01/2010 25 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice.