HCPL-0611E - AVAGO TECHNOLOGIES

April, 2014 − Rev. 7 1Publication Order Number:

MC100EP14/D

MC100EP14

3.3V / 5V 1:5 Differential

ECL/PECL/HSTL Clock Driver

Description

The MC100EP14 is a low skew 1−to−5 differential driver , designed with

clock distribution in mind, accepting two clock sources into an input

multiplexer. The ECL/PECL input signals can be either differential or

single−ended (if the V BB output is used). HSTL inputs can be used when

the LVEP14 is operating under PECL conditions.

The EP14 specifically guarantees low output−to−output skew. Optimal

design, layout, and processing minimize skew within a device and from

device to device.

To ensure that the tight skew specification is realized, both sides of

any differential output need to be terminated even if only one output is

being used. If an output pair is unused, both outputs may be left open

(unterminated) without affecting skew.

The common enable (EN) is synchronous, outputs are enabled/

disabled in the LOW state. This avoids a runt clock pulse when the

device is enabled/disabled as can happen with an asynchronous

control. The internal flip flop is clocked on the falling edge of the input

clock, therefore all associated specification limits a re r ef er en ce d to th e

negative edge of the clock input.

The VBB pin, an internally generated voltage supply, is available to

this device only. For single−ended input conditions, the unused

differential input is connected to VBB as a switching reference voltage.

VBB may also rebias AC coupled inputs. When used, decouple VBB

and VCC via a 0.01 mF capacitor and limit current sourcing or sinking

to 0.5 mA. When not used, VBB should be left open.

Features

•400 ps Typical Propagation Delay

•100 ps Device−to−Device Skew

•25 ps Within Device Skew

•Maximum Frequency > 2 GHz Typical

•The 100 Series Contains Temperature Compensation

•PECL and HSTL Mode:

VCC = 3.0 V to 5.5 V with VEE = 0 V

•NECL Mode:

VCC = 0 V with VEE = −3.0 V to −5.5 V

•Open Input Default State

•These are Pb−Free Devices

TSSOP−20

DT SUFFIX

CASE 948E

MARKING DIAGRAM*

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

G= Pb−Free Package

http://onsemi.com

100

EP14

ALYWG

*For additional marking information, refer to

Application Note AND8002/D.

See detailed ordering and shipping information in the package

dimensions section on page 6 of this data sheet.

ORDERING INFORMATION

(Note: Microdot may be in either location)

MC100EP14

http://onsemi.com

Figure 1. TSSOP−20 (Top View) and Logic Diagram

W ARNING: All V CC and VEE pins must be externally connected

to Power Supply to guarantee proper operation.

Q2Q1 Q3Q1

1718 16 15 14 13 12

43 56789

CLK1 CLK0 CLK0

1920

Q2Q0 Q3 Q4Q4

CLK1

VCC VCC VBB VEE

CLK_SEL

Table 1. PIN DESCRIPTION

Pin Function

CLK0*, CLK0** ECL/PECL/HSTL CLK Input

CLK1*, CLK1** ECL/PECL/HSTL CLK Input

Q0:4, Q0:4 ECL/PECL Outputs

CLK_SEL* ECL/PECL Active Clock Select Input

EN* ECL Sync Enable

VBB Reference Voltage Output

VCC Positive Supply

VEE Negative Supply

* Pins will default low when left open.

** Pins will default to VCC/2 when left open.

Table 2. FUNCTION TABLE

CLK0 CLK1 CLK_SEL EN Q

* On next negative transition of CLK0 or CLK1

MC100EP14

http://onsemi.com

Table 3. ATTRIBUTES

Characteristics Value

Internal Input Pulldown Resistor 75 kW

Internal Input Pullup Resistor 37.5 kW

ESD Protection Human Body Model

Machine Model

Charged Device Model

> 4 kV

> 200 V

> 2 kV

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb Pkg Pb−Free Pkg

TSSOP−8 Level 1 Level 1

Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in

Transistor Count 357 Devices

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.

Table 4. MAXIMUM RATINGS

Symbol Parameter Condition 1 Condition 2 Rating Unit

VCC PECL Mode Power Supply VEE = 0 V 6 V

VEE NECL Mode Power Supply VCC = 0 V −6 V

VIPECL Mode Input Voltage

NECL Mode Input Voltage VEE = 0 V

VCC = 0 V VI  VCC

VI  VEE

−6 V

Iout Output Current Continuous

Surge 50

100 mA

IBB VBB Sink/Source ± 0.5 mA

TAOperating Temperature Range −40 to +85 °C

Tstg Storage Temperature Range −65 to +150 °C

qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm TSSOP−20

TSSOP−20 140

100

°C/W

qJC Thermal Resistance (Junction−to−Case) Standard Board TSSOP−20 23 to 41 °C/W

Tsol Wave Solder <2 to 3 sec @ 248°C 265 °C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

MC100EP14

http://onsemi.com

Table 5. 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 2)

Symbol Characteristic

−40°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

IEE Power Supply Current 45 55 65 48 58 68 52 62 72 mA

VOH Output HIGH Voltage (Note 3) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV

VOL Output LOW Voltage (Note 3) 1305 1480 1605 1305 1480 1605 1305 1480 1605 mV

VIH Input HIGH Voltage (Single−Ended) 2075 2420 2075 2420 2075 2420 mV

VIL Input LOW Voltage (Single−Ended) 1305 1675 1305 1675 1305 1675 mV

VBB Output Voltage Reference 1775 1875 1975 1775 1875 1975 1775 1875 1975 mV

VIHCMR Input HIGH Voltage Common Mode

Range (Differential Configuration)

(Note 4)

1.2 3.3 1.2 3.3 1.2 3.3 V

IIH Input HIGH Current 150 150 150 mA

IIL Input LOW Current D

D0.5

−150 0.5

−150 mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

2. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V.

3. All loading with 50 W to VCC − 2.0 V.

4. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential

input signal.

Table 6. 100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 5)

Symbol Characteristic

−40°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

IEE Power Supply Current 45 55 65 48 58 68 52 62 72 mA

VOH Output HIGH Voltage (Note 6) 3855 3980 4105 3855 3980 4105 3855 3980 4105 mV

VOL Output LOW Voltage (Note 6) 3005 3180 3305 3005 3180 3305 3005 3180 3305 mV

VIH Input HIGH Voltage (Single−Ended) 3775 4120 3775 4120 3775 4120 mV

VIL Input LOW Voltage (Single−Ended) 3005 3375 3005 3375 3005 3375 mV

VBB Output Voltage Reference 3475 3575 3675 3475 3575 3675 3475 3575 3675 mV

VIHCMR Input HIGH Voltage Common Mode

Range (Differential Configuration)

(Note 7)

1.2 5.0 1.2 5.0 1.2 5.0 V

IIH Input HIGH Current 150 150 150 mA

IIL Input LOW Current D

D0.5

−150 0.5

−150 mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

5. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V.

6. All loading with 50 W to VCC − 2.0 V.

7. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential

input signal.

MC100EP14

http://onsemi.com

Table 7. 100EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = −5.5 V to −3.0 V (Note 8)

Symbo

Characteristic

−40°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

IEE Power Supply Current 45 55 65 48 58 68 52 62 72 mA

VOH Output HIGH Voltage (Note 9) −1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895 mV

VOL Output LOW Voltage (Note 9) −1995 −1820 −1695 −1995 −1820 −1695 −1995 −1820 −1695 mV

VIH Input HIGH Voltage (Single−Ended) −1225 −880 −1225 −880 −1225 −880 mV

VIL Input LOW Voltage (Single−Ended) −1995 −1625 −1995 −1625 −1995 −1625 mV

VBB Output Reference Voltage −1525 −1425 −1325 −1525 −1425 −1325 −1525 −1425 −1325 mV

VIHCMR Input HIGH Voltage Common Mode

Range (Differential Configuration)

(Note 10)

VEE+1.2 0.0 VEE+1.2 0.0 VEE+1.2 0.0 V

IIH Input HIGH Current 150 150 150 mA

IIL Input LOW Current CLK

CLK 0.5

−150 0.5

−150 mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

8. Input and output parameters vary 1:1 with VCC.

9. All loading with 50 W to VCC − 2.0 V.

10.VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential

input signal.

Table 8. AC CHARACTERISTICS VCC = 0 V; VEE = −3.0 V to −5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 11)

Symbo

Characteristic

−40°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

VOPP Output Voltage Amplitude @ 2 GHz

(Figure 2) 440 540 420 520 380 480 GHz

tPLH

tPHL Propagation Delay to

Output Differential 275 330 400 275 375 450 280 380 480 ps

tskew Within−Device Skew

Device−to−Device Skew

(Note 12)

100 35

125 30

150 45

175 40

175 50

200 ps

thSetup Time to CLK EN to CLK

Hold Time EN to CLK 100

200 50

140 100

200 50

140 100

200 50

140 ps

tJITTER Cycle−to−Cycle Jitter (Figure 2) 0.2 < 1 0.2 < 1 0.2 < 1 ps

VPP Minimum Input Swing 150 800 1200 150 800 1200 150 800 1200 mV

tr/tfOutput Rise/Fall Time (20%−80%) 105 155 205 145 200 270 150 225 300 ps

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

11.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V.

12.Skew is measured between outputs under identical transitions.

MC100EP14

http://onsemi.com

400

450

500

550

600

650

700

750

800

850

900

0.0 0.5 1.0 1.5 2.0 2.5

Figure 2. Fmax/Jitter

FREQUENCY (MHz)

(JITTER)

ÉÉÉÉÉÉÉÉÉÉÉÉ

VOUTpp (mV)

JITTEROUT ps (RMS)

ÉÉ

ÉÉÉ

3.3 V

5.0 V

Figure 3. Typical Termination for Output Driver and Device Evaluation

(See Application Note AND8020/D − Termination of ECL Logic Devices.)

Driver

Device Receiver

Device

Q D

Zo = 50 W

50 W50 W

VTT

VTT = VCC − 2.0 V

ORDERING INFORMATION

Device Package Shipping†

MC100EP14DTG TSSOP−20

(Pb−Free) 75 Units / Rail

MC100EP14DTR2G TSSOP−20

(Pb−Free) 2500 / Tape & Rail

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

MC100EP14

http://onsemi.com

Resource Reference of Application Notes

AN1405/D − ECL Clock Distribution Techniques

AN1406/D − Designing with PECL (ECL at +5.0 V)

AN1503/D −ECLinPSt I/O SPiCE Modeling Kit

AN1504/D − Metastability and the ECLinPS Family

AN1568/D − Interfacing Between LVDS and ECL

AN1672/D − The ECL Translator Guide

AND8001/D − Odd Number Counters Design

AND8002/D − Marking and Date Codes

AND8020/D − Termination of ECL Logic Devices

AND8066/D − Interfacing with ECLinPS

AND8090/D − AC Characteristics of ECL Devices

MC100EP14

http://onsemi.com

PACKAGE DIMENSIONS

TSSOP−20

CASE 948E−02

ISSUE C

DIM

MIN MAX MIN MAX

INCHES

6.60 0.260

MILLIMETERS

B4.30 4.50 0.169 0.177

C1.20 0.047

D0.05 0.15 0.002 0.006

F0.50 0.75 0.020 0.030

G0.65 BSC 0.026 BSC

H0.27 0.37 0.011 0.015

J0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L6.40 BSC 0.252 BSC

M0 8 0 8

____

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD

FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH OR GATE BURRS SHALL NOT

EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION

SHALL NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08

(0.003) TOTAL IN EXCESS OF THE K

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE

DETERMINED AT DATUM PLANE −W−.

ÍÍÍÍ

110

1120

PIN 1

IDENT

−T−

0.100 (0.004)

DGH

SECTION N−N

JJ1

−W−

SEATING

PLANE

−V−

−U−

0.10 (0.004) V S

20X REFK

L/2

U0.15 (0.006) T

DETAIL E

0.25 (0.010)

DETAIL E

6.40 0.252

--- ---

U0.15 (0.006) T

7.06

16X

0.36 16X

1.26

0.65

DIMENSIONS: MILLIMETERS

PITCH

SOLDERING FOOTPRINT

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,

copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC

reserves the r ight t o m ake c hanges wit hout f urt her n ot ice t o a ny p roduct s h erein. SCILLC makes no w arranty, representation o r g uar antee regarding the s uitability o f i ts p roducts f or a ny

particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without

limitation s pecial, c onsequential o r i ncidental d amages. “T ypical” p arameters w hich m ay b e p rovided i n S CILLC d ata s heets a nd/or s pecificat ions c a n a nd d o v ary in dif ferent a pplications

and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC

does not convey any license under i ts p at ent rights nor the rights of others. SCILLC pr oduct s ar e n ot d esigned, intended, or authorized for use as components in systems intended for

surgical implant i nto t he b ody, or o ther a pplications i ntended t o s upport o r s u stain life, or f or a ny o ther a pplication i n whic h t he f ailure o f t he S CILLC p roduct c ould creat e a s it uation w here

personal injury or death may occur. Should Buyer purchase or use SCILLC products f or any such unintended or unauthorized application, Buyer s hall i ndemnif y and hold SCILLC and

its o f ficers, e mployees, s ubsidiaries, a ff iliates, and d istributors h armless against a ll c laims, c osts, d amages, a nd expenses, a nd r easonable a tt orney f ees a rising o ut o f, d irectly o r i ndirectly,

any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCI LLC was negligent regarding t he design or manufacture

of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

UBLICATION ORDERING INFORMATION

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5817−1050

MC10EP56/D

ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).

LITERATURE FULFILLMENT:

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

For additional information, please contact your loc

Sales Representative