USB3320C-EZK-TR - Standard Microsystems

SMSC USB3320 Revision 1.0 (07-14-09)

DATASHEET

Datasheet

PRODUCT FEATURES

USB3320

Highly Integrated Full Featured

Hi-Speed USB 2.0 ULPI

Transceiver

Integrated ESD protection circuits

— Up to ±15kV IEC Air Discharge without external

devices

Over-Voltage Protection circuit (OVP) protects the

VBUS pin from continuous DC voltages up to 30V

Integrated USB Switch

— No degradation of Hi-Speed electrical

characteristics

— Allows single USB port of connection by

providing switching function for:

– Battery charging

– Stereo and mono/mic audio

– USB Full-Speed/Low-Speed data

flexPWR® Technology

— Low current design ideal for battery powered

applications

— “Sleep” mode tri-states all ULPI pins and places

the part in a low current state

— 1.8V to 3.3V IO Voltage (±10%)

Integrated battery to 3.3V regulator

— 2.2uF bypass capacitor

— 100mV dropout voltage

“Wrapper-less” design for optimal timing performance

and design ease

— Low Latency Hi-Speed Receiver (43 Hi-Speed

clocks Max) allows use of legacy UTMI Links with

a ULPI bridge

Selectable Reference Clock Frequency

— Frequencies: 12, 13, 19.2, 24, 26, 27, 38.4, 52 or

60MHz - pin selectable

External Reference Clock operation available

— ULPI Input Clock Mode (60MHz sourced by Link)

— 0 to 3.6V input drive tolerant

— Able to accept “noisy” clock sources as reference

to internal, low-jitter PLL

Internal Oscillator operation available

— This mode requires external Quartz Crystal or

Ceramic Resonator

Smart detection circuits allow identification of USB

charger, headset, or data cable insertion

Includes full support for the optional On-The-Go

(OTG) protocol detailed in the On-The-Go

Supplement Revision 2.0 specification

Supports Headset Audio Mode

Supports the OTG Host Negotiation Protocol (HNP)

and Session Request Protocol (SRP)

UART mode for non-USB serial data transfers

Internal 5V cable short-circuit protection of ID, DP

and DM lines to VBUS or ground

Industrial Operating Temperature -40°C to +85°C

32 pin, QFN Lead-free RoHS Compliant Package

(5 x 5 x 0.90 mm height)

Applications

The USB3320 is targeted for any application where a Hi-

Speed USB connection is desired and when board

space, power, and interface pins must be minimized.

The USB3320 is well suited for:

Networking

Audio Video

Medical

Industrial Computers

Printers

Repeaters

Communication

ORDER NUMBER(S):

USB3320C-EZK for 32 pin, QFN Lead-Free RoHS Compliant Package

USB3320C-EZK-TR for 32 pin, QFN Lead-Free RoHS Compliant Package (tape and reel)

Reel size is 4000 pieces.

Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver

Datasheet

Revision 1.0 (07-14-09) 2 SMSC USB3320

DATASHEET

80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123

Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for

construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC

reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications

before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent

rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated

version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors

known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not

designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property

damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of

this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered

trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.

SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY,

FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE

OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL

DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT;

TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD

TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver

Datasheet

SMSC USB3320 3 Revision 1.0 (07-14-09)

DATASHEET

0.1 Reference Documents

Universal Serial Bus Specification, Revision 2.0, April 27, 2000

On-The-Go Supplement to the USB 2.0 Specification, Revision 2.0, May 8, 2009

USB Specification Revision 2.0 "Pull-up/pull-down resistors" ECN (27% Resistor ECN)

USB 2.0 Transceiver Macrocell Interface (UTMI) Specification, Version 1.02, May 27, 2000

UTMI+ Specification, Revision 1.0, February 25, 2004

UTMI+ Low Pin Interface (ULPI) Specification, Revision 1.1, October 20th, 2004

Technical Requirements and Test Methods of Charger and Interface for Mobile Telecommunication

Terminal Equipment (Chinese Charger Specification Approval Draft 11/29/2006)

Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver

Datasheet

Revision 1.0 (07-14-09) 4 SMSC USB3320

DATASHEET

Table of Contents

0.1 Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Chapter 2 USB3320 Pin Locations and Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1 USB3320 Pin Locations and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1.1 Package Diagram with Pin Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1.2 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Chapter 3 Limiting Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.2 Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Chapter 4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.1 Operating Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.2 Clock Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.3 ULPI Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.4 Digital IO Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.5 DC Characteristics: Analog I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.6 Dynamic Characteristics: Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.7 OTG Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.8 USB Audio Switch Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.9 Regulator Output Voltages and Capacitor Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.10 Piezoelectric Resonator for Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Chapter 5 Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.1 ULPI Digital Operation and Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.2 USB 2.0 Hi-Speed Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.2.1 USB Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.2.2 Termination Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.3 Bias Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.4 Integrated Low Jitter PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.4.1 REFCLK Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.4.2 REFCLK Amplitude . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.4.3 REFCLK Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.4.4 REFCLK Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.5 Internal Regulators and POR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.5.1 Integrated Low Dropout Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.5.2 Power On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.5.3 Recommended Power Supply Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.5.4 Start-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.6 USB On-The-Go (OTG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.6.1 ID Resistor Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.6.2 VBUS Monitor and Pulsing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.6.3 Driving External VBUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.7 USB UART Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.8 USB Charger Detection Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.9 USB Audio Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.10 Reference Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Chapter 6 ULPI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

6.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver

Datasheet

SMSC USB3320 5 Revision 1.0 (07-14-09)

DATASHEET

6.1.1 ULPI Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

6.1.2 ULPI Interface Timing in Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

6.2 ULPI Register Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

6.2.1 ULPI Register Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

6.2.2 ULPI Register Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

6.2.3 ULPI RXCMD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.2.4 USB3320 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

6.2.5 USB Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

6.3 Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

6.3.1 Entering Low Power/Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

6.3.2 Exiting Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

6.3.3 Interface Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

6.3.4 Minimizing Current in Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

6.4 Full Speed/Low Speed Serial Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

6.5 Carkit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

6.5.1 USB UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

6.5.2 USB Audio Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

6.6 RID Converter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

6.7 Headset Audio Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Chapter 7 ULPI Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

7.1 ULPI Register Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

7.1.1 ULPI Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

7.1.2 Carkit Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

7.1.3 Vendor Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Chapter 8 Application Notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

8.1 Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

8.2 Reference Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

8.3 ESD Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

8.3.1 Human Body Model (HBM) Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

8.3.2 EN/IEC 61000-4-2 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

8.3.3 Air Discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

8.3.4 Contact Discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Chapter 9 Package Outline, Tape & Reel Drawings, Package Marking . . . . . . . . . . . . . . 78

Chapter 10 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver

Datasheet

Revision 1.0 (07-14-09) 6 SMSC USB3320

DATASHEET

List of Figures

Figure 1.1 USB3320 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 2.1 USB3320 Pin Locations - Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 5.1 USB3320 Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 5.2 Configuring the USB332X for ULPI Input Clock Mode (60 MHz) . . . . . . . . . . . . . . . . . . . . . . 27

Figure 5.3 Configuring the USB332X for ULPI Output Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 5.4 ULPI Output Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 5.5 Example of Circuit Used to Shift a Reference Clock Common-mode Voltage Level . . . . . . . 28

Figure 5.6 Powering the USB3320 from a Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 5.7 Powering the USB3320 from a 3.3V Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 5.8 Powering the USB3320 from VBUS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 5.9 ULPI Start-up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 5.10 USB3320 ID Resistor Detection Circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 5.11 USB3320 OTG VBUS Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 5.12 USB3320 Drives Control Signal (CPEN) to External Vbus Switch. . . . . . . . . . . . . . . . . . . . . 39

Figure 6.1 ULPI Digital Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 6.2 ULPI Single Data Rate Timing Diagram in Synchronous Mode. . . . . . . . . . . . . . . . . . . . . . . 44

Figure 6.3 ULPI Register Write in Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 6.4 ULPI Extended Register Write in Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 6.5 ULPI Register Read in Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 6.6 ULPI Extended Register Read in Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 6.7 ULPI Transmit in Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 6.8 ULPI Receive in Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 6.9 Entering Low Power Mode from Synchronous Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 6.10 Exiting Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 8.1 USB3320 Application Diagram (Device, ULPI Output Clock mode, 24MHz) . . . . . . . . . . . . . 74

Figure 8.2 USB3320 Application Diagram (Device, ULPI Input Clock mode, 60MHz) . . . . . . . . . . . . . . 75

Figure 8.3 USB3320 Application Diagram (Host or OTG, ULPI Output Clock Mode, 24MHz) . . . . . . . . 76

Figure 9.1 USB3320 32 Pin QFN Package Outline, 5 x 5 x 0.9 mm Body (Lead-Free) . . . . . . . . . . . . . 78

Figure 9.2 QFN, 5x5 Taping Dimensions and Part Orientation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Figure 9.3 Reel Dimensions for 12mm Carrier Tape. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 9.4 Tape Length and Part Quantity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 9.5 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver

Datasheet

SMSC USB3320 7 Revision 1.0 (07-14-09)

DATASHEET

List of Tables

Table 2.1 USB3320 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 3.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 3.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 4.1 Electrical Characteristics: Operating Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 4.2 ULPI Clock Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 4.3 ULPI Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 4.4 Digital IO Characteristics: RESETB, CLKOUT, STP, DIR, NXT, DATA[7:0] & REFCLK Pins. 17

Table 4.5 DC Characteristics: Analog I/O Pins (DP/DM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 4.6 Dynamic Characteristics: Analog I/O Pins (DP/DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 4.7 OTG Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 4.8 USB Audio Switch Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 4.9 Regulator Output Voltages and Capacitor Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 4.10 ESD and LATCH-UP Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 4.11 USB3320 Quartz Crystal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 4.12 USB3320 Ceramic Resonator Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 5.1 DP/DM Termination vs. Signaling Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 5.2 REFCLK Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 5.3 Operating Mode vs. Power Supply Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 5.4 Valid Values of ID Resistance to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 5.5 IdGnd and IdFloat vs. ID Resistance to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 5.6 External VBUS Indicator Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 5.7 Required RVBUS Resistor Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 5.8 USB Weak Pull-up Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 5.9 USB Audio Switch Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 5.10 Configuration to Select Reference Clock Frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 6.1 ULPI Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 6.2 ULPI TXD CMD Byte Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 6.3 ULPI RX CMD Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 6.4 Interface Signal Mapping During Low Power Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 6.5 Pin Definitions in 3 Pin Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 6.6 Pin Definitions in 6 Pin Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 6.7 ULPI Register Programming Example to Enter UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 6.8 Pin Definitions in Carkit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 6.9 ULPI Register Programming Example to Enter Audio Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 6.10 Pin Definitions in Headset Audio Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 7.1 ULPI Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 8.1 Component Values in Application Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 8.2 Capacitance Values at VBUS of USB Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 9.1 32 Terminal QFN Package Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 10.1 Customer Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver

Datasheet

Revision 1.0 (07-14-09) 8 SMSC USB3320

DATASHEET

Chapter 1 General Description

The SMSC USB3320 is a Hi-Speed USB 2.0 Transceiver that provides a configurable physical layer

(PHY) solution and is an excellent match for a wide variety of products. Both commercial and industrial

temperature applications are supported.

The frequency of the reference clock is user selectable. The USB3320 includes an internal oscillator

that may be used with either a quartz crystal or a ceramic resonator. Alternatively, the crystal input can

be driven by an external clock oscillator. Another option is the use of a 60MHz external clock when

using the ULPI Input Clock mode.

Several advanced features make the USB3320 the transceiver of choice by reducing both electrical

bill of material (eBOM) part count and printed circuit board (PCB) area. Outstanding ESD robustness

eliminates the need for external ESD protection devices in typical applications. The internal Over-

Voltage Protection circuit (OVP) protects the USB3320 from voltages up to 30V. By using a reference

clock from the Link, the USB3320 removes the cost of a dedicated crystal reference from the design.

And the integrated USB switch enables unique product features with a single USB port of connection.

The USB3320 meets all of the electrical requirements to be used as a Hi-Speed USB Host, Device,

or an On-the-Go (OTG) transceiver. In addition to the supporting USB signaling, the USB3320 also

provides USB UART mode and USB Audio mode.

USB3320 uses the industry standard UTMI+ Low Pin Interface (ULPI) to connect the USB Transceiver

to the Link. ULPI uses a method of in-band signaling and status byte transfers between the Link and

transceiver to facilitate a USB session with only 12 pins.

The USB3320 uses SMSC’s “wrapper-less” technology to implement the ULPI interface. This “wrapper-

less” technology allows the transceiver to achieve a low latency transmit and receive time. SMSC’s

low latency transceiver allows an existing UTMI Link to be reused by adding a UTMI to ULPI bridge.

By adding a bridge to the ASIC the existing and proven UTMI Link IP can be reused.

Figure 1.1 USB3320 Block Diagram

OTG

Hi-Speed

USB

Transceiver

ULPI Interface

ULPI

Registers

and State

Machine

BIAS

Crystal

Oscillator and

Low Jitter

Integrated

PLL

Integrated

Power

Management

VBUS

RBIAS

REFCLK

ESD Protection

DATA[7:0]

CPEN

RESETB

VDD18

VDD33

VBAT

DIR

NXT

STP

CLKOUT

USB

DP/DM

Switch

SPK_L

SPK_R

VDDIO

REFSEL[2:0]

Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver

Datasheet

SMSC USB3320 9 Revision 1.0 (07-14-09)

DATASHEET

The USB3320 includes an integrated 3.3V Low Drop Out (LDO) regulator that may optionally be used

to generate 3.3V from power applied at the VBAT pin. The voltage on the VBAT pin can range from

3.1 to 5.5V. The regulator dropout voltage is less than 100mV which allows the transceiver to continue

USB signaling when the voltage on VBAT drops to 3.1V. The USB transceiver will continue to operate

at lower voltages, although some parameters may be outside the limits of the USB specifications. If

the user would like to provide a 3.3V supply to the USB3320, the VBAT and VDD33 pins should be

connected together as described in Section 5.5.1.

The USB3320 also includes integrated pull-up resistors that can be used for detecting the attachment

of a USB Charger. By sensing the attachment to a USB Charger, a product using the USB3320 can

charge its battery at more than the 500mA allowed when charging from a USB Host. Please see SMSC

Application Note AN 19.7 - Battery Charging Using SMSC USB Transceivers for more information on

battery charging.

In USB UART mode, the USB3320 DP and DM pins are redefined to enable pass-through of

asynchronous serial data. The USB3320 can only enter UART mode when the user programs the part

into this mode, as described in Section 6.5.1.

In USB audio mode, a switch connects the DP pin to the SPK_R pin, and another switch connects he

DM pin to the SPK_L pin. These switches are shown in the lower left-hand corner of Figure 5.1. The

USB3320 can be configured to enter USB audio mode as described in Section 6.5.2. In addition, these

switches are on when the RESETB pin of the USB3320 is asserted. The USB audio mode enables

audio signalling from a single USB port of connection, and the switches may also be used to connect

Full Speed USB from another transceiver onto the USB cable.

Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver

Datasheet

Revision 1.0 (07-14-09) 10 SMSC USB3320

DATASHEET

Chapter 2 USB3320 Pin Locations and Definitions

2.1 USB3320 Pin Locations and Descriptions

2.1.1 Package Diagram with Pin Locations

The illustration below is viewed from the top of the package.

2.1.2 Pin Definitions

The following table details the pin definitions for the figure above.

Figure 2.1 USB3320 Pin Locations - Top View

Table 2.1 USB3320 Pin Description

PIN NAME

DIRECTION/

TYPE

ACTIVE

LEVEL DESCRIPTION

1CLKOUT

Output,

CMOS

N/A ULPI Output Clock Mode:

60MHz ULPI clock output. All ULPI

signals are driven synchronous to the

rising edge of this clock.

ULPI Input Clock Mode:

This pin is connected to VDDIO to

configure 60MHz ULPI Input Clock mode

as described in Section 5.4.1.

Following POR or hardware reset, the

voltage at CLKOUT must not exceed

VIH_ED as provided inTa b l e 4. 4.

CLKOUT

NXT

DATA0

DATA1

DATA2

DATA3

REFSEL0

DATA4

DATA5

DATA6

REFSEL1

N/C

DATA7

REFSEL2

SPK_R

SPK_L

RBIAS

CPEN

VBUS

VBAT

VDD33

VDDIO

RESETB

REFCLK

VDD18

STP

VDD18

DIR

USB3300

Hi-Speed USB2

ULPI PHY

32 Pin QFN

Hi-Speed USB

ULPI PHY

32 Pin QFN

GND FLAG

Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver

Datasheet

SMSC USB3320 11 Revision 1.0 (07-14-09)

DATASHEET

2NXT

Output,

CMOS

High The transceiver asserts NXT to throttle

the data. When the Link is sending data

to the transceiver, NXT indicates when

the current byte has been accepted by

the transceiver. The Link places the next

byte on the data bus in the following

clock cycle.

3 DATA[0] I/O,

CMOS

N/A ULPI bi-directional data bus.

4 DATA[1] I/O,

CMOS

N/A ULPI bi-directional data bus.

5 DATA[2] I/O,

CMOS

N/A ULPI bi-directional data bus.

6 DATA[3] I/O,

CMOS

N/A ULPI bi-directional data bus.

7 DATA[4] I/O,

CMOS

N/A ULPI bi-directional data bus.

8 REFSEL[0] Input,

CMOS

N/A This signal, along with REFSEL[1] and

REFSEL[2] selects one of the available

reference frequencies as defined in

Table 5.10.

Note: This signal must be tied to VDDIO

when in ULPI 60MHz REFCLK IN mode.

9 DATA[5] I/O,

CMOS

N/A ULPI bi-directional data bus.

10 DATA[6] I/O,

CMOS

N/A ULPI bi-directional data bus.

11 REFSEL[1] Input,

CMOS

N/A This signal, along with REFSEL[0] and

REFSEL[2] selects one of the available

reference frequencies as defined in

Table 5.10.

Note: This signal must be tied to VDDIO

when in ULPI 60MHz REFCLK IN mode.

12 N/C N/A This pin must not be connected.

13 DATA[7] I/O,

CMOS

N/A ULPI bi-directional data bus.

14 REFSEL[2] Input,

CMOS

N/A This signal, along with REFSEL[0] and

REFSEL[1] selects one of the available

reference frequencies as defined in

Table 5.10.

Note: This signal must be tied to VDDIO

when in ULPI 60MHz REFCLK IN mode.

15 SPK_L I/O,

Analog

N/A USB switch in/out for DM signals

16 SPK_R I/O,

Analog

N/A USB switch in/out for DP signals

Table 2.1 USB3320 Pin Description (continued)

PIN NAME

DIRECTION/

TYPE

ACTIVE

LEVEL DESCRIPTION

Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver

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Revision 1.0 (07-14-09) 12 SMSC USB3320

DATASHEET

17 CPEN Output,

CMOS

N/A External 5V supply enable. Controls the

external VBUS power switch. CPEN is low

on POR.

18 DP I/O,

Analog

N/A D+ pin of the USB cable.

19 DM I/O,

Analog

N/A D- pin of the USB cable.

20 VDD33 Power N/A 3.3V Regulator Output. A 2.2uF (<1 ohm

ESR) bypass capacitor to ground is

required for regulator stability. The

bypass capacitor should be placed as

close as possible to the USB3320.

21 VBAT Power N/A Regulator input.

22 VBUS I/O,

Analog

N/A This pin connects to an external resistor

(RVBUS) connected to the VBUS pin of

the USB cable. This pin is used for the

VBUS comparator inputs and for VBUS

pulsing during session request protocol.

See Table 5.7, "Required RVBUS

Resistor Value".

23 ID Input,

Analog

N/A ID pin of the USB cable. For applications

not using ID this pin can be connected to

VDD33. For an A-Device ID is grounded.

For a B-Device ID is floated.

24 RBIAS Analog,

CMOS

N/A Bias Resistor pin. This pin requires an

8.06kΩ (±1%) resistor to ground, placed

as close as possible to the USB3320.

Nominal voltage during ULPI operation is

0.8V.

25 XO Output,

CMOS

N/A External resonator pin. When using an

external clock on REFCLK, this pin

should be floated.

26 REFCLK Input,

CMOS

N/A ULPI Output Clock Mode:

Reference frequency as defined in

Table 5.10.

ULPI Input Clock Mode:

60MHz ULPI clock input.

27 RESETB Input,

CMOS,

Low When low, the part is suspended with all

ULPI outputs tri-stated. When high, the

USB3320 will operate as a normal ULPI

device, as described in Section 5.5.2.

The state of this pin may be changed

asynchronously to the clock signals.

When asserted for a minimum of 1

microsecond and then de-asserted, the

ULPI registers are reset to their default

state and all internal state machines are

reset.

28 VDD18 Power N/A External 1.8V Supply input pin. This pad

needs to be bypassed with a 0.1uF

capacitor to ground, placed as close as

possible to the USB3320.

Table 2.1 USB3320 Pin Description (continued)

PIN NAME

DIRECTION/

TYPE

ACTIVE

LEVEL DESCRIPTION

Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver

Datasheet

SMSC USB3320 13 Revision 1.0 (07-14-09)

DATASHEET

29 STP Input,

CMOS

High The Link asserts STP for one clock cycle

to stop the data stream currently on the

bus. If the Link is sending data to the

transceiver, STP indicates the last byte of

data was on the bus in the previous

cycle.

30 VDD18 Power N/A External 1.8V Supply input pin. This pad

needs to be bypassed with a 0.1uF

capacitor to ground, placed as close as

possible to the USB3320.

31 DIR Output,

CMOS

N/A Controls the direction of the data bus.

When the transceiver has data to transfer

to the Link, it drives DIR high to take

ownership of the bus. When the

transceiver has no data to transfer it

drives DIR low and monitors the bus for

commands from the Link.

32 VDDIO Power N/A External 1.8V to 3.3V ULPI supply input

pin. This voltage sets the value of VOH for

the ULPI signals. This pad needs to be

bypassed with a 0.1uF capacitor to

ground, placed as close as possible to

the USB3320.

FLAG GND Ground N/A Ground.

Table 2.1 USB3320 Pin Description (continued)

PIN NAME

DIRECTION/

TYPE

ACTIVE

LEVEL DESCRIPTION

Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver

Datasheet

Revision 1.0 (07-14-09) 14 SMSC USB3320

DATASHEET

Chapter 3 Limiting Values

3.1 Absolute Maximum Ratings

Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent

damage to the device. Exposure to absolute maximum rating conditions for extended periods

may affect device reliability.

3.2 Recommended Operating Conditions

Table 3.1 Absolute Maximum Ratings

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

VBUS, VBAT, ID, CPEN,

DP, DM, SPK_L, and

SPK_R voltage to GND

VMAX_5V Voltage measured at pin.

VBUS tolerant to 30V with

external RVBUS.

-0.5 +6.0 V

Maximum VDD18 voltage

to Ground

VMAX_18V -0.5 2.5 V

Maximum VDDIO voltage

to Ground

VMAX_IOV VDD18 = VDD18 -0.5 4.0 V

Maximum VDDIO voltage

to Ground

VMAX_IOV VDD18 = 0V -0.5 0.7 V

Maximum VDD33 voltage

to Ground

VMAX_33V -0.5 4.0 V

Maximum I/O voltage to

Ground

VMAX_IN -0.5 VDDIO + 0.7 V

Operating Temperature TMAX_OP -40 85 °C

Storage Temperature TMAX_STG -55 150 °C

Table 3.2 Recommended Operating Conditions

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

VBAT to GND VVBAT 3.1 5.5 V

VDD33 to GND VDD33 3.0 3.3 3.6 V

VDDIO to GND VDDIO 1.6 1.8-3.3 3.6 V

VDD18 to GND VDD18 1.6 1.8 2.0 V

Input Voltage on Digital

Pins (RESETB, STP,

DIR, NXT, DATA[7:0])

VI0.0 VDDIO V

Voltage on Analog I/O

Pins (DP, DM, ID, CPEN,

SPK_L, SPK_R)

VI(I/O) 0.0 VDD33 V

VBUS to GND VVMAX 0.0 5.5 V

Ambient Temperature TA-40 85 °C

VDDIO VDD18 min()≥

Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver

Datasheet

SMSC USB3320 15 Revision 1.0 (07-14-09)

DATASHEET

Chapter 4 Electrical Characteristics

The following conditions are assumed unless otherwise specified:

VVBAT = 3.1 to 5.5V; VDD18 = 1.6 to 2.0V; VDDIO = 1.6 to 2.0V; VSS = 0V; TA = -40°C to +85°C

The current for 3.3V circuits is sourced at the VBAT pin, except when using an external 3.3V supply

as shown in Figure 5.7.

4.1 Operating Current

Note 4.1 ClockSuspendM bit = 0.

Note 4.2 SessEnd, VbusVld, and IdFloat comparators disabled. STP Interface protection disabled.

Table 4.1 Electrical Characteristics: Operating Current

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Synchronous Mode Current

(Default Configuration)

I33AVG(SYNC) Start-up sequence defined

in Section 5.5.4 has

completed.

7.5 mA

I18AVG(SYNC) 28.0 mA

IIOAVG(SYNC) 4.1 mA

Synchronous Mode Current

(HS USB operation)

I33AVG(HS) Active USB Transfer 11.1 mA

I18AVG(HS) 29.4 mA

IIOAVG(HS) 5.9 mA

Synchronous Mode Current

(FS/LS USB operation)

I33AVG(FS) Active USB Transfer 6.3 mA

I18AVG(FS) 22.5 mA

IIOAVG(FS) 5.0 mA

Serial Mode Current

(FS/LS USB)

Note 4.1

I33AVG(FS_S) 5.6 mA

I18AVG(FS_S) 2.4 mA

IIOAVG(FS_S) 86 uA

USB UART Current

Note 4.1

I33AVG(UART) 5.6 mA

I18AVG(UART) 2.4 mA

IIOAVG(UART) 58 uA

Low Power Mode

Note 4.2

IDD33(LPM) VVBAT = 4.2V

VDD18 = 1.8V

VDDIO = 1.8V

18.8 uA

IDD18(LPM) 0.7 uA

IDDIO(LPM) 30 uA

Standby Mode IDD33(RSTB) RESETB = 0

VVBAT = 4.2V

VDD18 = 1.8V

VDDIO = 1.8V

18 uA

IDD18(RSTB) 0.6 uA

IDDIO(RSTB) 0.1 uA

Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver

Datasheet

Revision 1.0 (07-14-09) 16 SMSC USB3320

DATASHEET

4.2 Clock Specifications

Note 4.3 The Suspend Recovery Time is measured from the start of the REFCLK to when the

USB3320 de-asserts DIR.

Note: The USB3320 uses the AutoResume feature, Section 6.2.4.4, to allow a host start-up time of

less than 1ms

4.3 ULPI Interface Timing

Note: VDD18 = 1.6 to 2.0V; VSS = 0V; TA = -40°C to +85°C

Note 4.4 REFCLK does not need to be aligned in any way to the ULPI signals.

Table 4.2 ULPI Clock Specifications

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Suspend Recovery Time

Note 4.3

TSTART 26MHz REFCLK 1.03 2.28 ms

12MHz REFCLK 2.24 3.49 ms

52MHz REFCLK 0.52 1.77 ms

24MHz REFCLK 1.12 2.37 ms

19.2MHz REFCLK 1.40 2.65 ms

27MHz REFCLK 1.00 2.25 ms

38.4MHz REFCLK 0.70 1.95 ms

13MHz REFCLK 2.07 3.32 ms

PHY Preparation Time TPREP 60MHz REFCLK

ULPI Input Clock Mode

0.40.450.5ms

CLKOUT Duty Cycle DCCLKOUT ULPI Input Clock Mode 45 55 %

REFCLK Duty Cycle DCREFCLK 20 80 %

REFCLK Frequency Accuracy FREFCLK -500 +500 PPM

Table 4.3 ULPI Interface Timing

PARAMETER SYMBOL CONDITIONS MIN MAX UNITS

60MHz ULPI Output Clock Note 4.4

Setup time (STP, data in) TSC, TSD Model-specific REFCLK 5.0 ns

Hold time (STP, data in) THC, THD Model-specific REFCLK 0.0 ns

Output delay (control out, 8-bit data out) TDC, TDD Model-specific REFCLK 1.0 3.5 ns

60MHz ULPI Input Clock

Setup time (STP, data in) TSC, TSD 60MHz REFCLK 1.5 ns

Hold time (STP, data in) THC, THD 60MHz REFCLK -0.5 ns

Output delay (control out, 8-bit data out) TDC, TDD 60Mhz REFCLK 1.5 6.0 ns

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DATASHEET

4.4 Digital IO Pins

4.5 DC Characteristics: Analog I/O Pins

Table 4.4 Digital IO Characteristics: RESETB, CLKOUT, STP, DIR, NXT, DATA[7:0] & REFCLK Pins

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Low-Level Input Voltage VIL VSS 0.4 *

VDDIO

High-Level Input Voltage VIH 0.68 *

VDDIO

VDDIO V

High-Level Input Voltage

REFCLK only

VIH 0.68 *

VDD18

VDD33 V

Low-Level Output Voltage VOL IOL = 8mA 0.4 V

High-Level Output Voltage VOH IOH = -8mA VDDIO

0.4

High-Level Output Voltage

CPEN Only

VOH IOH = -8mA VDD33

- 0.4

Input Leakage Current ILI VDD33

- 0.4

±10 uA

Pin Capacitance Cpin 4 pF

STP pull-up resistance RSTP InterfaceProtectDisable = 0 55 67 77 kΩ

DATA[7:0] pull-dn

resistance

RDATA_PD ULPI Synchronous Mode 55 67 77 kΩ

CLKOUT External Drive VIH_ED At start-up or following reset 0.4 *

VDDIO

Table 4.5 DC Characteristics: Analog I/O Pins (DP/DM)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

LS/FS FUNCTIONALITY

Input levels

Differential Receiver Input

Sensitivity

VDIFS | V(DP) - V(DM) | 0.2 V

Differential Receiver

Common-Mode Voltage

VCMFS 0.8 2.5 V

Single-Ended Receiver Low

Level Input Voltage

VILSE Note 4.6 0.8 V

Single-Ended Receiver High

Level Input Voltage

VIHSE Note 4.6 2.0 V

Single-Ended Receiver

Hysteresis

VHYSSE 0.050 0.150 V

Output Levels

Low Level Output Voltage VFSOL Pull-up resistor on DP;

RL = 1.5kΩ to VDD33

0.3 V

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High Level Output Voltage VFSOH Pull-down resistor on DP,

DM; Note 4.6

RL = 15kΩ to GND

2.8 3.6 V

Termination

Driver Output Impedance for

HS and FS

ZHSDRV Steady state drive 40.5 45 49.5 Ω

Input Impedance ZINP RX, RPU, RPD disabled 1.0 MΩ

Pull-up Resistor Impedance RPU Bus Idle, Note 4.5 0.900 1.24 1.575 kΩ

Pull-up Resistor Impedance RPU Device Receiving,

Note 4.5

1.425 2.26 3.09 kΩ

Pull-dn Resistor Impedance RPD Note 4.5 14.25 16.9 20 kΩ

Weak Pull-up Resistor

Impedance

RCD Configured by bits 4 and 5

in USB IO & Power

Management register.

128 170 212 kΩ

HS FUNCTIONALITY

Input levels

HS Differential Input

Sensitivity

VDIHS | V(DP) - V(DM) | 100 mV

HS Data Signaling Common

Mode Voltage Range

VCMHS -50 500 mV

High-Speed Squelch

Detection Threshold

(Differential Signal Amplitude)

VHSSQ

Note 4.7 100 150 mV

Output Levels

Hi-Speed Low Level

Output Voltage (DP/DM

referenced to GND)

VHSOL 45Ω load -10 10 mV

Hi-Speed High Level

Output Voltage (DP/DM

referenced to GND)

VHSOH 45Ω load 360 440 mV

Hi-Speed IDLE Level

Output Voltage (DP/DM

referenced to GND)

VOLHS 45Ω load -10 10 mV

Chirp-J Output Voltage

(Differential)

VCHIRPJ HS termination resistor

disabled, pull-up resistor

connected. 45Ω load.

700 1100 mV

Chirp-K Output Voltage

(Differential)

VCHIRPK HS termination resistor

disabled, pull-up resistor

connected. 45Ω load.

-900 -500 mV

Leakage Current

OFF-State Leakage Current ILZ ±10 uA

Table 4.5 DC Characteristics: Analog I/O Pins (DP/DM) (continued)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

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Note 4.5 The resistor value follows the 27% Resistor ECN published by the USB-IF.

Note 4.6 The values shown are valid when the USB RegOutput bits in the USB IO & Power

Management register are set to the default value.

Note 4.7 An automatic waiver up to 200mV is granted to accommodate system-level elements such

as measurement/test fixtures, captive cables, EMI components, and ESD suppression.

4.6 Dynamic Characteristics: Analog I/O Pins

Port Capacitance

Transceiver Input

Capacitance

CIN Pin to GND 5 10 pF

Table 4.6 Dynamic Characteristics: Analog I/O Pins (DP/DM)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

FS Output Driver Timing

FS Rise Time TFR CL = 50pF; 10 to 90% of

|VOH - VOL|

420ns

FS Fall Time TFF CL = 50pF; 10 to 90% of

|VOH - VOL|

420ns

Output Signal Crossover

Voltage

VCRS Excluding the first

transition from IDLE state

1.3 2.0 V

Differential Rise/Fall Time

Matching

TFRFM Excluding the first

transition from IDLE state

90 111.1 %

LS Output Driver Timing

LS Rise Time TLR CL = 50-600pF;

10 to 90% of

|VOH - VOL|

75 300 ns

LS Fall Time TLF CL = 50-600pF;

10 to 90% of

|VOH - VOL|

75 300 ns

Differential Rise/Fall Time

Matching

TLRFM Excluding the first

transition from IDLE state

80 125 %

HS Output Driver Timing

Differential Rise Time THSR 500 ps

Differential Fall Time THSF 500 ps

Driver Waveform

Requirements

Eye pattern of Template 1

in USB 2.0 specification

Hi-Speed Mode Timing

Receiver Waveform

Requirements

Eye pattern of Template 4

in USB 2.0 specification

Data Source Jitter and

Receiver Jitter Tolerance

Eye pattern of Template 4

in USB 2.0 specification

Table 4.5 DC Characteristics: Analog I/O Pins (DP/DM) (continued)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

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4.7 OTG Electrical Characteristics

Note 4.8 The RVPD and RVPU values include the required 1kΩ external RVBUS resistor.

4.8 USB Audio Switch Characteristics

Table 4.7 OTG Electrical Characteristics

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

SessEnd trip point VSessEnd 0.2 0.5 0.8 V

SessVld trip point VSessVld 0.8 1.4 2.0 V

VbusVld trip point VVbusVld 4.4 4.58 4.75 V

A-Device Impedance RIdGnd Maximum A device

Impedance to ground on ID

100 kΩ

ID Float trip point VIdFloat 1.9 2.2 2.5 V

VBUS Pull-Up RVPU VBUS to VDD33 Note 4.8

(ChargeVbus = 1)

1.29 1.34 1.45 kΩ

VBUS Pull-down RVPD VBUS to GND Note 4.8

(DisChargeVbus = 1)

1.55 1.7 1.85 kΩ

VBUS Impedance RVB VBUS to GND 40 75 100 kΩ

ID pull-up resistance RID IdPullup = 1 80 100 120 kΩ

ID weak pull-up resistance RIDW IdPullup = 0 1 MΩ

ID pull-dn resistance RIDPD IdGndDrv = 1 1000 Ω

Table 4.8 USB Audio Switch Characteristics

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Minimum “ON” Resistance RON_Min 0 < Vswitch < VDD33 2.7 5 5.8 Ω

Maximum “ON” Resistance RON_Max 0 < Vswitch < VDD33 4.5 7 10 Ω

Minimum “OFF”

Resistance

ROFF_Min 0 < Vswitch < VDD33 1MΩ

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4.9 Regulator Output Voltages and Capacitor Requirement

Note 4.9 REFCLK, XO, SPK_L and SPK_R pins: ±5kV Human Body Model.

Table 4.9 Regulator Output Voltages and Capacitor Requirement

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Regulator Output Voltage VDD33 6V > VBAT > 3.1V 3.0 3.3 3.6 V

Regulator Output Voltage VDD33 USB UART Mode & UART

RegOutput[1:0] = 01

6V > VBAT > 3.1V

2.7 3.0 3.3 V

Regulator Output Voltage VDD33 USB UART Mode & UART

RegOutput[1:0] = 10

6V > VBAT > 3.1V

2.47 2.75 3.03 V

Regulator Output Voltage VDD33 USB UART Mode & UART

RegOutput[1:0] = 11

6V > VBAT > 3.1V

2.25 2.5 2.75 V

Regulator Bypass Capacitor COUT 2.2 uF

Bypass Capacitor ESR CESR 1Ω

Table 4.10 ESD and LATCH-UP Performance

PARAMETER CONDITIONS MIN TYP MAX UNITS COMMENTS

ESD PERFORMANCE

Note 4.9 Human Body Model ±8 kV Device

System EN/IEC 61000-4-2 Contact

Discharge

±8 kV 3rd party system test

System EN/IEC 61000-4-2 Air-gap

Discharge

±15 kV 3rd party system test

LATCH-UP PERFORMANCE

All Pins EIA/JESD 78, Class II 150 mA

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4.10 Piezoelectric Resonator for Internal Oscillator

The internal oscillator may be used with an external quartz crystal or ceramic resonator as described

in Section 5.4.1.2. See Table 4.11 for the recommended crystal specifications. See Table 4.12 for the

ceramic resonator part numbers for commercial temperature applications. At this time, the ceramic

resonator does not offer sufficient temperature stability to operate over the industrial temperature

range.

Note 4.10 The required bit rate accuracy for Hi-Speed USB applications is ±500 ppm as provided in

the USB 2.0 Specification. This takes into account the effect of voltage, temperature, aging,

etc.

Note 4.11 0oC for commercial applications, -40oC for industrial applications.

Note 4.12 +70oC for commercial applications, +85oC for industrial applications.

Note 4.13 This number includes the pad, the bond wire and the lead frame. Printed Circuit Board

(PCB) capacitance is not included in this value. The PCB capacitance value and the

capacitance value of the XO and REFCLK pins are required to accurately calculate the

value of the two external load capacitors.

Note 4.14 This is a generic part number assigned by Murata. The oscillating frequency is affected by

stray capacitance on the Printed Circuit Board (PCB). Murata will assign the final part

number for each customer’s PCB after characterizing the customer’s PCB design.

Table 4.11 USB3320 Quartz Crystal Specifications

PARAMETER SYMBOL MIN NOM MAX UNITS NOTES

Crystal Cut AT, typ

Crystal Oscillation Mode Fundamental Mode

Crystal Calibration Mode Parallel Resonant Mode

Frequency Ffund -Table 5.10 -MHz

Total Allowable PPM Budget - - ±500 PPM Note 4.10

Shunt Capacitance CO-7 typ-pF

Load Capacitance CL- 20 typ - pF

Drive Level PW0.5 - - mW

Equivalent Series Resistance R1--30Ohm

Operating Temperature Range Note 4.11 -Note 4.12 oC

USB3320 REFCLK Pin

Capacitance

-3 typ-pFNote 4.13

USB3320 XO Pin Capacitance - 3 typ - pF Note 4.13

Table 4.12 USB3320 Ceramic Resonator Part Numbers

FREQUENCY MURATA PART NUMBER NOTES

24 MHz CSTCE24M0XK1***-R0 Commercial Temp Only, Note 4.14

26 MHz CSTCE26M0XK1***-R0 Commercial Temp Only, Note 4.14

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Chapter 5 Architecture Overview

The USB3320 consists of the blocks shown in the diagram below. All pull-up resistors shown in this

diagram are connected internally to the VDD33 pin.

Figure 5.1 USB3320 Internal Block Diagram

5.1 ULPI Digital Operation and Interface

This section of the USB3320 is covered in detail in Chapter 6, ULPI Operation.

5.2 USB 2.0 Hi-Speed Transceiver

The blocks in the lower left-hand corner of Figure 5.1 interface to the DP/DM pins.

5.2.1 USB Transceiver

The USB3320 includes the receivers and transmitters that are compliant to the Universal Serial Bus

Specification Rev 2.0. The DP/DM signals in the USB cable connect directly to the receivers and

transmitters.

The RX block consists of a differential receiver for HS and separate receivers for FS/LS mode.

Depending on the mode, the selected receiver provides the serial data stream through the multiplexer

to the RX Logic block. For HS mode support, the HS RX block contains a squelch circuit to insure that

noise is not interpreted as data. The RX block also includes a single-ended receiver on each of the

data lines to determine the correct FS linestate.

Data from the TX Logic block is encoded, bit stuffed, serialized and transmitted onto the USB cable

by the TX block. Separate differential FS/LS and HS transmitters are included to support all modes.

The USB3320 TX block meets the HS signalling level requirements in the USB 2.0 Specification when

the PCB traces from the DP and DM pins to the USB connector have very little loss. In some systems,

BIAS

Integrated

Low Jitter

PLL

RBIAS

ESD Protection

RCD

RPD

RPU

RPU RID

RIDW

RVPU

RVB

DIR

NXT

STP

CLKOUT

DATA7

DATA6

DATA5

DATA4

DATA3

DATA2

DATA0

DATA1

REFCLK

VDDIO

VBAT

VDD33

VBUS

LDO

ID ULPI

Digitial

Digital IO

OTG Module

HS/FS/LS

TX Encoding

HS/FS/LS

RX Decoding

RESETB

TX Data

RX Data

IdGnd

IdFloat

Rid Value

SessEnd

SessValid

VbusValid

SPK_L

SPK_R

RVPD

OVP

VDD18

REFSEL0

REFSEL1

REFSEL2

CPEN

DrvVbus or’d with DrvVbusExternal

VDD33

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DATASHEET

it may be desirable to compensate for loss by adjusting the HS transmitter amplitude. The Boost bits

in the HS TX Boost register may be configured to adjust the HS transmitter amplitude at the DP and

DM pins.

5.2.2 Termination Resistors

The USB3320 transceiver fully integrates all of the USB termination resistors on both DP and DM. This

includes 1.5kΩ pull-up resistors, 15kΩ pull-down resistors and the 45Ω high speed termination

resistors. These resistors require no tuning or trimming by the Link. The state of the resistors is

determined by the operating mode of the transceiver when operating in synchronous mode.

The XcvrSelect[1:0], TermSelect and OpMode[1:0] bits in the Function Control register, and the

DpPulldown and DmPulldown bits in the OTG Control register control the configuration. The possible

valid resistor combinations are shown in Table 5.1, and operation is guaranteed in only the

configurations shown. If a ULPI Register Setting is configured that does not match a setting in the

table, the transceiver operation is not guaranteed and the settings in the last row of Tab l e 5 .1 will be

used.

RPU_DP_EN activates the 1.5kΩ DP pull-up resistor

RPU_DM_EN activates the 1.5kΩ DM pull-up resistor

RPD_DP_EN activates the 15kΩ DP pull-down resistor

RPD_DM_EN activates the 15kΩ DM pull-down resistor

HSTERM_EN activates the 45Ω DP and DM high speed termination resistors

The USB3320 also includes two DP and DM pull-up resistors described in Section 5.8.

Table 5.1 DP/DM Termination vs. Signaling Mode

SIGNALING MODE

ULPI REGISTER SETTINGS

USB3320 TERMINATION

RESISTOR SETTINGS

XCVRSELECT[1:0]

TERMSELECT

OPMODE[1:0]

DPPULLDOWN

DMPULLDOWN

RPU_DP_EN

RPU_DM_EN

RPD_DP_EN

RPD_DM_EN

HSTERM_EN

General Settings

Tri-State Drivers XXbXb01bXbXb0b0b0b0b0b

Power-up or VBUS < VSESSEND 01b0b00b1b1b0b0b1b1b0b

Host Settings

Host Chirp 00b0b10b1b1b0b0b1b1b1b

Host Hi-Speed 00b0b00b1b1b0b0b1b1b1b

Host Full Speed X1b1b00b1b1b0b0b1b1b0b

Host HS/FS Suspend 01b1b00b1b1b0b0b1b1b0b

Host HS/FS Resume 01b1b10b1b1b0b0b1b1b0b

Host low Speed 10b1b00b1b1b0b0b1b1b0b

Host LS Suspend 10b 1b 00b 1b 1b 0b 0b 1b 1b 0b

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DATASHEET

Note: This is the same as Table 40, Section 4.4 of the ULPI 1.1 specification.

Note: USB3320 does not support operation as an upstream hub port. See Section 6.2.4.3, "UTMI+

Level 3".

Note 5.1 The transceiver operation is not guaranteed in a combination that is not defined.

The USB3320 uses the 27% resistor ECN resistor tolerances. The resistor values are shown in

Table 4.5.

Host LS Resume 10b1b10b1b1b0b0b1b1b0b

Host Test J/Test_K 00b0b10b1b1b0b0b1b1b1b

Peripheral Settings

Peripheral Chirp 00b 1b 10b 0b 0b 1b 0b 0b 0b 0b

Peripheral HS 00b 0b 00b 0b 0b 0b 0b 0b 0b 1b

Peripheral FS 01b 1b 00b 0b 0b 1b 0b 0b 0b 0b

Peripheral HS/FS Suspend 01b 1b 00b 0b 0b 1b 0b 0b 0b 0b

Peripheral HS/FS Resume 01b 1b 10b 0b 0b 1b 0b 0b 0b 0b

Peripheral LS 10b 1b 00b 0b 0b 0b 1b 0b 0b 0b

Peripheral LS Suspend 10b 1b 00b 0b 0b 0b 1b 0b 0b 0b

Peripheral LS Resume 10b 1b 10b 0b 0b 0b 1b 0b 0b 0b

Peripheral Test J/Test K 00b 0b 10b 0b 0b 0b 0b 0b 0b 1b

OTG device, Peripheral Chirp 00b 1b 10b 0b 1b 1b 0b 0b 1b 0b

OTG device, Peripheral HS 00b 0b 00b 0b 1b 0b 0b 0b 1b 1b

OTG device, Peripheral FS 01b 1b 00b 0b 1b 1b 0b 0b 1b 0b

OTG device, Peripheral HS/FS Suspend 01b 1b 00b 0b 1b 1b 0b 0b 1b 0b

OTG device, Peripheral HS/FS Resume 01b 1b 10b 0b 1b 1b 0b 0b 1b 0b

OTG device, Peripheral Test J/Test K 00b 0b 10b 0b 1b 0b 0b 0b 1b 1b

Any combination not defined above

Note 5.1

0b 0b 0b 0b 0b

Table 5.1 DP/DM Termination vs. Signaling Mode (continued)

SIGNALING MODE

ULPI REGISTER SETTINGS

USB3320 TERMINATION

RESISTOR SETTINGS

XCVRSELECT[1:0]

TERMSELECT

OPMODE[1:0]

DPPULLDOWN

DMPULLDOWN

RPU_DP_EN

RPU_DM_EN

RPD_DP_EN

RPD_DM_EN

HSTERM_EN

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5.3 Bias Generator

This block consists of an internal bandgap reference circuit used for generating the driver current and

the biasing of the analog circuits. This block requires an external 8.06KΩ, 1% tolerance, reference

resistor connected from RBIAS to ground. This resistor should be placed as close as possible to the

USB3320 to minimize the trace length. The nominal voltage at RBIAS is 0.8V +/- 10% and therefore

the resistor will dissipate approximately 80μW of power.

5.4 Integrated Low Jitter PLL

The USB3320 uses an integrated low jitter phase locked loop (PLL) to provide a clean 480MHz clock

required for HS USB signal quality. This clock is used by the transceiver during both transmit and

receive. The USB3320 PLL requires an accurate frequency reference to be driven on the REFCLK pin.

5.4.1 REFCLK Mode Selection

The USB3320 is designed to operate in one of two available modes as shown in Table 5.2. In the first

mode, a 60MHz ULPI clock is driven on the REFCLK pin as described in Section 5.4.1.1. In the second

mode, the USB3320 generates the ULPI clock as described in Section 5.4.1.2. When using the second

mode, the frequency of the reference clock is configured by REFSEL[2], REFSEL[1] and REFSEL[0]

as described in Section 5.10.

During start-up, the USB3320 monitors the CLKOUT pin to determine which mode has been

configured as described in Section 5.4.1.1.

The system must not drive voltage on the CLKOUT pin following POR or hardware reset that exceeds

the value of VIH_ED provided in Ta b l e 4 . 4 .

5.4.1.1 ULPI Input Clock Mode (60MHz REFCLK Mode)

When using ULPI Input Clock Mode, the Link must supply the 60MHz ULPI clock to the USB3320. As

shown in Figure 5.2, the 60MHz ULPI Clock is connected to the REFCLK pin, and the CLKOUT pin

is tied high to VDDIO. A simplified schematic using the ULPI Input Clock Mode is shown in Figure 8.2.

After the PLL has locked to the correct frequency, the USB3320 will de-assert DIR and the Link can

begin using the ULPI interface. The USB3320 is guaranteed to start the clock within the time specified

in Table 4.2. For Host applications, the ULPI AutoResume bit should be enabled. This is described in

Section 6.2.4.4.

REFSEL[2], REFSEL[1] and REFSEL[0] should all be tied to VDDIO for ULPI Input Clock Mode.

Table 5.2 REFCLK Modes

MODE

REFCLK

FREQUENCY ULPI CLOCK DESCRIPTION

ULPI Input Clock

Mode

60Mhz Sourced by Link, driven on the REFCLK pin

ULPI Output Clock

Mode

Table 5.10 Sourced by USB3320 at the CLKOUT pin

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DATASHEET

5.4.1.2 ULPI Output Clock

When using ULPI Output Clock Mode, the USB3320 generates the 60MHz ULPI clock used by the

Link. The frequency of the reference clock is configured by REFSEL[2], REFSEL[1] and REFSEL[0]

as described in Table 5.10. As shown in Figure 5.3, the CLKOUT pin sources the 60MHz ULPI clock

to the Link.

In this mode, the REFCLK pin may be driven at the reference clock frequency. Alternatively, the

internal oscillator may be used with an external crystal or resonator as shown in Figure 5.4.

An example of ULPI Output Clock Mode is shown in Figure 8.1.

Figure 5.2 Configuring the USB332X for ULPI Input Clock Mode (60 MHz)

Figure 5.3 Configuring the USB332X for ULPI Output Clock Mode

CLKOUT

REFCLK

SMSC PHY

Clock

Source

To PLL

Link

ULPI Clk Out

Reference Clk In

VDDIO

CLKOUT

REFCLK

SMSC PHY

From PLL

Clock

Source To PLL

Link

ULPI Clk In

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After the PLL has locked to the correct frequency, the USB3320 generates the 60MHz ULPI clock on

the CLKOUT pin, and de-asserts DIR to indicate that the PLL is locked. The USB3320 is guaranteed

to start the clock within the time specified in Tab le 4 . 2 , and it will be accurate to within ±500ppm. For

Host applications the ULPI AutoResume bit should be enabled. This is described in Section 6.2.4.4.

When using ULPI Output Clock Mode, the edges of the reference clock do not need to be aligned in

any way to the ULPI interface signals; in other words, there is no need to align the phase of the

REFCLK and the CLKOUT.

5.4.2 REFCLK Amplitude

The reference clock is connected to the REFCLK pin as shown in the application diagrams, Figure 8.1,

Figure 8.2 and Figure 8.3. The REFCLK pin is designed to be driven with a square wave from 0V to

VDD18, but can be driven with a square wave from 0V to as high as 3.6V. The USB3320 uses only the

positive edge of the REFCLK.

If a digital reference is not available, the REFCLK pin can be driven by an analog sine wave that is

AC coupled into the REFCLK pin. If using an analog clock, the DC bias should be set at the mid-point

of the VDD18 supply using a bias circuit as shown in Figure 5.5. The amplitude must be greater than

300mV peak to peak. The component values provided in Figure 5.5 are for example only. The actual

values should be selected to satisfy system requirements.

The REFCLK amplitude must comply with the signal amplitudes shown in Ta b l e 4 . 4 and the duty cycle

in Ta b l e 4 . 2 .

Figure 5.4 ULPI Output Clock Mode

Figure 5.5 Example of Circuit Used to Shift a Reference Clock Common-mode Voltage Level

CLKOUT

REFCLK

SMSC PHY

From PLL

Link ULPI Clk In

Resonator

Crystal

and Caps

- or - XO

CLOAD

Internal

Oscillator To PLL

Clock

47k 47k

0.1uF

VDD18

To REFCLK pin

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Datasheet

SMSC USB3320 29 Revision 1.0 (07-14-09)

DATASHEET

5.4.3 REFCLK Jitter

The USB3320 is tolerant to jitter on the reference clock. The REFCLK jitter should be limited to a peak

to peak jitter of less than 1nS over a 10uS time interval. If this level of jitter is exceeded when

configured for either ULPI Input Clock Mode or ULPI Output Clock Mode, the USB3320 Hi-Speed eye

diagram may be degraded.

The frequency accuracy of the REFCLK must meet the +/- 500ppm requirement as shown in Ta b l e 4 . 2 .

5.4.4 REFCLK Enable/Disable

The REFCLK should be enabled when the RESETB pin is brought high. The ULPI interface will start

running after the time specified in Ta b le 4 .2 . If the REFCLK enable is delayed relative to the RESETB

pin, the ULPI interface will start operation delayed by the same amount. The REFCLK can be run at

anytime the RESETB pin is low without causing the USB3320 to start-up or draw current.

When the USB3320 is placed in Low Power Mode or Carkit Mode, the REFCLK can be stopped after

the final ULPI register write is complete. The STP pin is asserted to bring the USB3320 out of Low

Power Mode. The REFCLK should be started at the same time STP is asserted to minimize the

USB3320 start-up time.

If the REFCLK is stopped while CLKOUT is running, the PLL will come out of lock and the frequency

of the CLKOUT signal will decrease to the minimum allowed by the PLL design. If the REFCLK is

stopped during a USB session, the session may drop.

5.5 Internal Regulators and POR

The USB3320 includes integrated power management functions, including a Low-Dropout regulator

that can be used to generate the 3.3V USB supply, and a POR generator described in Section 5.5.2.

5.5.1 Integrated Low Dropout Regulator

The USB3320 has an integrated linear regulator. Power sourced at the VBAT pin is regulated to 3.3V

and the regulator output is on the VDD33 pin. To ensure stability, the regulator requires an external

bypass capacitor (COUT) as specified in Ta b l e 4 . 9 placed as close to the pin as possible.

The USB3320 regulator is designed to generate a 3.3 volt supply for the USB3320 only. Using the

regulator to provide current for other circuits is not recommended and SMSC does not guarantee USB

performance or regulator stability.

During USB UART mode the regulator output voltage can be changed to allow the USB3320 to work

with UARTs operating at different operating voltages. The regulator output is configured to the voltages

shown in Ta b l e 4 . 9 with the UART RegOutput[1:0] bits in the USB IO & Power Management register.

The USB3320 regulator can be powered in the three methods as shown below.

For USB Peripheral, Host, and OTG operations the regulator can be connected as shown in Figure 5.6

or Figure 5.7 below. For OTG operation, the VDD33 supply on the USB3320 must be powered to

detect devices attaching to the USB connector and detect a SRP during an OTG session. When using

a battery to supply the USB3320, the battery voltage must be within the range of 3.1V to 5.5V.

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The USB3320 can be powered from an external 3.3V supply as shown below in Figure 5.7. When

using the external supply, both the VBAT and VDD33 pins are connected together. The bypass

capacitor, CBYP

, is recommended when using the external supply.

Figure 5.6 Powering the USB3320 from a Battery

Figure 5.7 Powering the USB3320 from a 3.3V Supply

VBUS

VDD33

VBAT

GND

LDO

SMSC PHY

To OTG

COUT

VBUS

To USB Con.

RVBUS

VBUS

VDD33

VBAT

GND

LDO

SMSC PHY

To OTG

CBYP

Vdd

3.3V

VBUS

To USB Con.

RVBUS

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For peripheral only or host only operation, the VBAT supply shown below in Figure 5.8 may be

connected to the VBUS pin of the USB connector for bus powered applications. In this configuration,

external overvoltage protection is required to protect the VBAT supply from any transient voltage

present at the VBUS pin of the USB connector.

The VBAT input must never be exposed to a voltage that exceeds VVBAT

. (See Tab le 3 . 2 )

5.5.2 Power On Reset (POR)

The USB3320 provides a POR circuit that generates an internal reset pulse after the VDD18 supply

is stable. After the internal POR goes high and the RESETB pin is high, the USB3320 will release from

reset and begin normal ULPI operation as described in Section 5.5.4.

The ULPI registers will power up in their default state summarized in Table 7.1 when the 1.8V supply

is brought up. Cycling the 1.8 volt power supply will reset the ULPI registers to their default states.

The RESETB pin can also be used to reset the ULPI registers to their default state (and reset all

internal state machines) by bringing the pin low for a minimum of 1 microsecond and then high.

The Link is not required to assert the RESETB pin. A pull-down resistor is not present on the RESETB

pin and therefore the Link must drive the RESETB pin to the desired state at all times (including

system start-up) or connect the RESETB pin to VDDIO.

5.5.3 Recommended Power Supply Sequence

For USB operation the USB3320 requires the VBAT, VDD33, VDDIO and VDD18 supples. VBAT,

VDD33, and VDD18 can be applied in any order. The VDD18 supply must be turned on and stable

before the VDDIO supply is applied. This does not apply in cases where the VDD18 and VDDIO supply

pins are tied together.

When the VBAT supply is applied, the integrated regulator will automatically start-up and regulate

VBAT to VDD33. If the VDD33 supply is powered and the VDD18 supply is not powered, the 3.3V

circuits are powered off and the VDD33 current will be limited as shown in Ta b l e 4. 1.

The ULPI interface will start operating after the VDD18 and VDDIO supplies are applied and the

RESETB pin is brought high. The RESETB pin must be held low until the VDD18 and VDDIO supplies

are stable. If the Link is not ready to interface the USB3320, the Link may choose to hold the RESETB

pin low until it is ready to control the ULPI interface.

Figure 5.8 Powering the USB3320 from VBUS

VBUS

VDD33

VBAT

GND

LDO

SMSC PHY

To OTG

COUT

OVP

VBUS

To USB Con.

RVBUS

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DATASHEET

Note: Anytime VBAT is powered per Tab le 3 . 2 , the VDD33 pin will be powered up.

Note 5.2 VDDIO must be powered to tri-state the ULPI interface in this configuration.

5.5.4 Start-Up

The power on default state of the USB3320 is ULPI Synchronous mode. The USB3320 requires the

following conditions to begin operation: the power supplies must be stable, the REFCLK must be

present and the RESETB pin must be high. After these conditions are met, the USB3320 will begin

ULPI operation that is described in Chapter 6.

Figure 5.9 below shows a timing diagram to illustrate the start-up of the USB3320. At T0, the supplies

are stable and the USB3320 is held in reset mode. At T1, the Link drives RESETB high after the

REFCLK has started. The RESETB pin may be brought high asynchronously to REFCLK. At this point

the USB3320 will drive idle on the data bus and assert DIR until the internal PLL has locked. After the

PLL has locked, the USB3320 will check that the Link has de-asserted STP and at T2 it will de-assert

DIR and begin ULPI operation.

The ULPI bus will be available as shown in Figure 5.9 in the time defined as TSTART given in Ta b l e 4 . 2 .

If the REFCLK signal starts after the RESETB pin is brought high, then time T0 will begin when

REFCLK starts. TSTART also assumes that the Link has de-asserted STP. If the Link has held STP

high the USB3320 will hold DIR high until STP is de-asserted. When the LINK de-asserts STP, it must

drive a ULPI IDLE one cycle after DIR de-asserts.

Table 5.3 Operating Mode vs. Power Supply Configuration

VDD33 VDD18 RESETB OPERATING MODES AVAILABLE

0 0 0 Powered Off

0 1 0 RESET Mode.

0 1 1 In this configuration the ULPI interface is available and can

be programed into all operating modes described in

Chapter 6. All USB signals will read 0.

1 0 X In this mode the ULPI interface is not active and the circuits

powered from the VDD33 supply are turned off and the

current will be limited to the RESET Mode current.

(Note 5.2)

1 1 0 RESET Mode

1 1 1 Full USB operation as described in Chapter 6.

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5.6 USB On-The-Go (OTG)

The USB3320 provides full support for USB OTG protocol. OTG allows the USB3320 to be dynamically

configured as a host or device depending on the type of cable inserted into the receptacle. When the

Micro-A plug of a cable is inserted into the Micro-AB receptacle, the USB device becomes the A-

device. When a Micro-B plug is inserted, the device becomes the B-device. The OTG A-device

behaves similar to a Host while the B-device behaves similar to a peripheral. The differences are

covered in the “On-The-Go Supplement to the USB 2.0 Specification”. In applications where only Host

or Device is required, the OTG Module is unused.

5.6.1 ID Resistor Detection

The ID pin of the USB connector is monitored by the ID pin of the USB3320 to detect the attachment

of different types of USB devices and cables. For device only applications that do not use the ID signal

the ID pin should be connected to VDD33. The block diagram of the ID detection circuitry is shown in

Figure 5.10 and the related parameters are given in Ta b l e 4. 7.

Figure 5.9 ULPI Start-up Timing

DIR

RESETB

STP

TSTART

REFCLK

T1 T2

SUPPLIES

STABLE

PHY Drives Idle

DATA[7:0]

REFCLK valid

PHY Tri-States

PHY Tri-States PHY Drives High

LINK Drives Low

RXCMDIDLE IDLE

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5.6.1.1 USB OTG Operation

The USB3320 can detect ID grounded and ID floating to determine if an A or B cable has been

inserted. The A plug will ground the ID pin while the B plug will float the ID pin. These are the only

two valid states allowed in the OTG Protocol.

To monitor the status of the ID pin, the Link activates the IdPullup bit in the OTG Control register, waits

50mS and then reads the status of the IdGnd bit in the USB Interrupt Status register. If an A cable has

been inserted the IdGnd bit will read 0. If a B cable is inserted, the ID pin is floating and the IdGnd bit

will read 1.

The USB3320 provides an integrated weak pull-up resistor on the ID pin, RIDW. This resistor is present

to keep the ID pin in a known state when the IdPullup bit is disabled and the ID pin is floated. In

addition to keeping the ID pin in a known state, it enables the USB3320 to generate an interrupt to

inform the link when a cable with a resistor to ground has been attached to the ID pin. The weak pull-

up is small enough that the largest valid Rid resistor pulls the ID pin low and causes the IdGnd

comparator to go low.

After the link has detected an ID pin state change, the RID converter can be used to determine the

resistor value as described in Section 5.6.1.2.

5.6.1.2 Measuring ID Resistance to Ground

The Link can used the integrated resistance measurement capabilities to determine the value of an ID

resistance to ground. Table 5.4 lists the valid values of resistance, to ground, that the USB3320 can

detect.

Figure 5.10 USB3320 ID Resistor Detection Circuitry

IdPullup

IdGnd

Vref IdGnd

RID=100K

RIDW>1M

IdFloat

OTG Module

VDD33

To USB Con.

RidValue

Vref IdFloat

IdGnd Rise or

IdGnd Fall

IdFloatRise or

IdFloatFall

Rid ADC

IdGndDrv

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Note: IdPullUp = 0

The Rid resistance can be read while the USB3320 is in Synchronous Mode. When a resistor to

ground is attached to the ID pin, the state of the IdGnd comparator will change. After the Link has

detected ID transition to ground, it can use the methods described in Section 6.6 to operate the Rid

converter.

5.6.1.3 Using IdFloat Comparator

Note: The ULPI specification details a method to detect a 102kΩ resistance to ground using the

IdFloat comparator. This method can only detect 0ohms, 102kΩ, and floating terminations of

the ID pin. Due to this limitation it is recommended to use the RID Converter as described in

Section 5.6.1.2.

The ID pin can be either grounded, floated, or connected to ground with a 102kΩ external resistor. To

detect the 102K resistor, set the idPullup bit in the OTG Control register, causing the USB3320 to apply

the 100K internal pull-up connected between the ID pin and VDD33. Set the idFloatRise and idFloatFall

bits in both the USB Interrupt Enable Rising and USB Interrupt Enable Falling registers to enable the

IdFloat comparator to generate an RXCMD to the Link when the state of the IdFloat changes. As

described in Figure 6.3, the alt_int bit of the RXCMD will be set. The values of IdGnd and IdFloat are

shown for the three types cables that can attach to the USB Connector in Table 5.5.

Note: The ULPI register bits IdPullUp, IdFloatRise, and IdFloatFall should be enabled.

To save current when an A Plug is inserted, the internal 102kΩ pull-up resistor can be disabled by

clearing the IdPullUp bit in the OTG Control register and the IdFloatRise and IdFloatFall bits in both

the USB Interrupt Enable Rising and USB Interrupt Enable Falling registers. If the cable is removed

the weak RIDW will pull the ID pin high.

The IdGnd value can be read using the ULPI USB Interrupt Status register, bit 4. In host mode, it can

be set to generate an interrupt when IdGnd changes by setting the appropriate bits in the USB Interrupt

Enable Rising and USB Interrupt Enable Falling registers. The IdFloat value can be read by reading

the ULPI Carkit Interrupt Status register bit 0.

Table 5.4 Valid Values of ID Resistance to Ground

ID RESISTANCE TO GROUND RID VALUE

Ground 000

75Ω +/-1% 001

102kΩ +/-1% 010

200kΩ+/-1% 011

440kΩ +/-1% 100

Floating 101

Table 5.5 IdGnd and IdFloat vs. ID Resistance to Ground

ID RESISTANCE IDGND IDFLOAT

Float 1 1

102K 1 0

GND 0 0

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Note: The IdGnd switch has been provided to ground the ID pin for future applications.

5.6.2 VBUS Monitor and Pulsing

The USB3320 includes all of the VBUS comparators required for OTG. The VBUSVld, SessVld, and

SessEnd comparators shown in Figure 5.11 are fully integrated into the USB3320. These comparators

are used to monitor changes in the VBUS voltage, and the state of each comparator can be read from

the USB Interrupt Status register.

The VbusVld comparator is used by the Link, when configured as an A device, to ensure that the

VBUS voltage on the cable is valid. The SessVld comparator is used by the Link when configured as

both an A or B device to indicate a session is requested or valid. Finally the SessEnd comparator is

used by the B-device to indicate a USB session has ended.

Also included in the VBUS Monitor and Pulsing block are the resistors used for VBUS pulsing in SRP.

The resistors used for VBUS pulsing include a pull-down to ground and a pull-up to VDD33.

In some applications, voltages much greater than 5.5V may be present at the VBUS pin of the USB

connector. The USB3320 includes an overvoltage protection circuit that protects the VBUS pin of the

USB3320 from excessive voltages as described in Section 5.6.2.6, and shown in Figure 5.11.

5.6.2.1 SessEnd Comparator

The SessEnd comparator is designed to trip when VBUS is less than 0.5 volts. When VBUS goes

below 0.5 volts the USB session is considered to be ended, and SessEnd will transition from 0 to 1.

The SessEnd comparator can be disabled by clearing this bit in both the USB Interrupt Enable Rising

and USB Interrupt Enable Falling registers. When disabled, the SessEnd bit in the USB Interrupt Status

Figure 5.11 USB3320 OTG VBUS Block

RVPD

VbusValid

SessValid

SessEnd

DischrgVbus

0.5V

1.4V

4.575V

VBUS

VDD33

SMSC PHY

To USB Con.

SessEnd Rise or

SessEnd Fall

VbusValid Rise or

VbusValid Fall

RXCMD VbusValid

IndicatorComplement

[UseExternalVbusindicator, IndicatorPassThru]

[0, X]

[1, 0]

[1, 1]

EXTVBUS (logic 1)

RVB

RVPU

ChrgVbus

VBUS

Overvoltage

Protection

RVBUS

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5.6.2.2 SessVld Comparator

The SessVld comparator is used when the transceiver is configured as both an A and B device. When

configured as an A device, the SessVld is used to detect Session Request protocol (SRP). When

configured as a B device, SessVld is used to detect the presence of VBUS. The SessVld interrupts

can be disabled by clearing this bit in both the USB Interrupt Enable Rising and USB Interrupt Enable

Falling registers. When the interrupts are disabled, the SessVld comparator is not disabled and its state

can be read in the USB Interrupt Status register. The SessVld comparator trip point is detailed in

Table 4.7.

Note: The OTG Supplement specifies a voltage range for A-Device Session Valid and B-Device

Session Valid comparator. The USB3320 transceiver combines the two comparators into one

and uses the narrower threshold range.

5.6.2.3 VbusVld Comparator

The final VBUS comparator is the VbusVld comparator. This comparator is only used when the

USB3320 is configured as an A-device. In the USB protocol the A-device supplies the VBUS voltage

and is responsible to ensure it remains within a specified voltage range. The VbusVld comparator can

be disabled by clearing this bit in both the USB Interrupt Enable Rising and USB Interrupt Enable

Falling registers. When disabled, bit 1 of the USB Interrupt Status register will return a 0. The VbusVld

comparator trip points are detailed in Tabl e 4. 7.

The internal VbusValid comparator is designed to ensure the VBUS voltage remains above 4.4V.

The USB3320 includes the external vbus valid indicator logic as detail in the ULPI Specification. The

external vbus valid indicator is tied to a logic one. The decoding of this logic is shown in Tab le 5 .6

below. By default this logic is disabled.

Note 5.3 A peripheral should not use VbusVld to begin operation. The peripheral should use

SessVld because the internal VbusVld threshold can be above the VBUS voltage required

for USB peripheral operation.

Table 5.6 External VBUS Indicator Logic

TYPICAL

APPLICATION

USE

EXTERNAL

VBUS

INDICATOR

PASS THRU

INDICATOR

COMPLEMENT

RXCMD VBUS VALID

ENCODING SOURCE

OTG Device 0 X X Internal VbusVld comparator (Default)

1 1 0 Fixed 1

1 1 1 Fixed 0

1 0 0 Internal VbusVld comparator.

1 0 1 Fixed 0

Standard Host 1 1 0 Fixed 1

1 1 1 Fixed 0

Standard

Peripheral

0 X X Internal VbusVld comparator. This

information should not be used by the

Link. (Note 5.3)

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5.6.2.4 VBUS Pulsing with Pull-up and Pull-down Resistors

In addition to the internal VBUS comparators, the USB3320 also includes the integrated VBUS pull-up

and pull-down resistors used for VBUS Pulsing during OTG Session Request Protocol. To discharge

the VBUS voltage so that a Session Request can begin, the USB3320 provides a pull-down resistor

from VBUS to Ground. This resistor is controlled by the DischargeVbus bit 3 of the OTG Control

VBUS above 2.1 volts so that the A-Device knows that a USB session has been requested. The state

of the pull-up resistor is controlled by the bit 4 ChargeVbus of the OTG Control register. The Pull-Up

and Pull-Down resistor values are detailed in Ta b l e 4 . 7 .

The internal VBUS Pull-up and Pull-down resistors are designed to include the RVBUS external resistor

in series. This external resistor is used by the VBUS Overvoltage protection described below.

5.6.2.5 VBUS Input Impedance

The OTG Supplement requires an A-Device that supports Session Request Protocol to have a VBUS

input impedance less than 100kΩ and greater the 40kΩ to ground. The USB3320 provides a 75kΩ

resistance to ground, RVB. The RVB resistor tolerance is detailed in Ta b l e 4 . 7 .

5.6.2.6 VBUS Overvoltage Protection

The USB3320 provides an integrated overvoltage protection circuit to protect the VBUS pin from

excessive voltages that may be present at the USB connector. The overvoltage protection circuit works

with an external resistor (RVBUS) by drawing current across the resistor to reduce the voltage at the

VBUS pin.

When voltage at the VBUS pin exceeds 5.5V, the Overvoltage Protection block will sink current to

ground until VBUS is below 5.5V. The current drops the excess voltage across RVBUS and protects the

USB3320 VBUS pin. The required RVBUS value is dependent on the operating mode of the USB3320

as shown in Table 5.7.

The Overvoltage Protection circuit is designed to protect the USB3320 from continuous voltages up to

30V on the RVBUS resistor.

The RVBUS resistor must be sized to handle the power dissipated across the resistor. The resistor

power can be found using the equation below:

Table 5.7 Required RVBUS Resistor Value

OPERATING MODE RVBUS

Device only 10kΩ ±5%

OTG Capable 1kΩ ±5%

Host

UseExternalVbusIndicator = 1

10kΩ ±5%

PRVBUS

Vprotect 5.0–()

RVBUS

--------------------------------------------=

Where:

Vprotect is the VBUS protection required

RVBUS is the resistor value, 1kΩ or 10kΩ.

PRVBUS is the required power rating of RVBUS

Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver

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For example, protecting a peripheral or device only application to 15V would require a 10kΩ R

VBUS

resistor with a power rating of 0.01W. To protect an OTG product to 15V would require a 1kΩ RVBUS

resistor with a power rating of 0.1W.

5.6.3 Driving External VBUS

The USB3320 monitors VBUS as described in VBUS Monitor and Pulsing. For OTG and Host

applications, the system is required to source 5 volts on VBUS. The USB3320 fully supports VBUS

power control using an external VBUS switch as shown in Figure 8.3. The USB3320 provides an active

high control signal, CPEN, that is dedicated to controlling the Vbus supply when configured as an A-

Device.

CPEN is asserted by setting the DrvVbus or DrvVbusExternal bit of the OTG Control register. To be

compatible with Link designs that support both internal and external Vbus supplies the DrvVbus and

DrvVbusExternal bits in the OTG Control Register are or’d together. This enables the Link to set either

bit to access the external Vbus enable (CPEN). This logic is shown in Figure 5.12. DrvVbus and

DrvVbusExternal are set to 0 on Power On Reset (POR) as shown in Section 7.1.1.7.

5.7 USB UART Support

The USB3320 provides support for the USB UART interface as detailed in the ULPI specification and

the former CEA-936A specification. The USB3320 can be placed in UART Mode using the method

described in Section 6.5, and the regulator output will automatically switch to the value configured by

the UART RegOutput bits in the USB IO & Power Management register. While in UART mode, the

Linestate signals cannot be monitored on the DATA[0] and DATA[1] pins.

5.8 USB Charger Detection Support

To support the detection and identification of different types of USB chargers the USB3320 provides

integrated pull-up resistors, RCD, on both DP and DM. These pull-up resistors along with the single

ended receivers can be used to help determine the type of USB charger attached. Reference

information on implementing charger detection is provided in SMSC Application Note AN 19.7 - Battery

Charging Using SMSC USB Transceivers.

Figure 5.12 USB3320 Drives Control Signal (CPEN) to External Vbus Switch

VBUS

Switch

OUT

USB Transceiver

VBUS

USB

Connector

VBUS

RVBUS

CPEN

Link

Controller

CPEN Logic

DrvVbusExternal

DrvVbus

ULPI

+5V

VBUS

Supply

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Note: ChargerPullupEnableDP and ChargerPullupEnableDM are enabled in the USB IO & Power

Management register.

5.9 USB Audio Support

Note: The USB3320 supports “USB Digital Audio” through the USB protocol in ULPI and USB Serial

modes described in Section 6.

The USB3320 provides two low resistance analog switches that allow analog audio to be multiplexed

over the DP and DM terminals of the USB connector. The audio switches are shown in Figure 5.1. The

electrical characteristics of the USB Audio Switches are provided in Ta bl e 4. 8.

During normal USB operation the switches are off. When USB Audio is desired the switches can be

turned “on” by enabling the SpkLeftEn, SpkRightEn, or MicEn bits in the Carkit Control register as

described in Section 6.5.2. These bits are disabled by default. The USB Audio Switches can also be

enabled by asserting the RESETB pin or removing the voltage at VDD18 as shown in Ta bl e 5. 9 . While

using the USB switches, VDD18 is not required, but 3.3V must be present at VDD33. The integrated

3.3V LDO regulator may be used to generate VDD33 from power applied at the VBAT pin.

Note: SpkLeftEn, SpkRightEn, and MicEn are enabled in the Carkit Control register.

In addition to USB Audio support the switches can also be used to multiplexed a second FS USB

transceiver to the USB connector. The signal quality will be degraded slightly due to the “on” resistance

of the switches. The USB3320 single-ended receivers described in Section 5.2.1 are disabled when

either USB Audio switch is enabled.

The USB3320 does not provide the DC bias for the audio signals. The SPK_R and SPK_L pins should

be biased to 1.65V when audio signals are routed through the USB3320. This DC bias is necessary

to prevent the audio signal from swinging below ground and being clipped by ESD Diodes.

When the system is not using the USB Audio switches, the SPK_R and SPK_L pins should not be

connected.

Table 5.8 USB Weak Pull-up Enable

RESETB DP PULLUP ENABLE DM PULLUP ENABLE

00 0

1ChargerPullupEnableDP ChargerPullupEnableDM

Table 5.9 USB Audio Switch Enable

RESETB VDD18 DP SWITCH ENABLE DM SWITCH ENABLE

X011

0111

11SpkLeftEn SpkRightEn or MicEn

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5.10 Reference Frequency Selection

The USB3320 is configured for the desired reference frequency by the REFSEL[2], REFSEL[1] and

REFSEL[0] pins. If a pin is connected to VDDIO, the value of “1” is assigned. Connect the pin to

ground to assign a “0.” When using the ULPI Input Clock Mode (60MHz REFCLK Mode), the reference

frequency is always fixed at 60 MHz. Eight reference clock frequencies are available as described in

Table 5.10.

Table 5.10 Configuration to Select Reference Clock Frequency

CONFIGURATION PINS DESCRIPTION

REFSEL[2] REFSEL[1] REFSEL[0] REFERENCE FREQUENCY

0 0 0 52 MHz

0 0 1 38.4 MHz

0 1 0 12 MHz

0 1 1 27 MHz

1 0 0 13 MHz

1 0 1 19.2 MHz

1 1 0 26 MHz

1 1 1 24 MHz

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Chapter 6 ULPI Operation

6.1 Overview

The USB3320 uses the industry standard ULPI digital interface to facilitate communication between

the USB Transceiver (PHY) and Link (device controller). The ULPI interface is designed to reduce the

number of pins required to connect a discrete USB Transceiver to an ASIC or digital controller. For

example, a full UTMI+ Level 3 OTG interface requires 54 signals while a ULPI interface requires only

12 signals.

The ULPI interface is documented completely in the “UTMI+ Low Pin Interface (ULPI) Specification

Revision 1.1”. The following sections describe the operating modes of the USB3320 digital interface.

Figure 6.1 illustrates the block diagram of the ULPI digital functions. It should be noted that this

USB3320 does not use a “ULPI wrapper” around a UTMI+ PHY core as the ULPI specification implies.

The advantage of a “wrapper less” architecture is that the USB3320 has a lower USB latency than a

design which must first register signals into the PHY’s wrapper before the transfer to the PHY core. A

Figure 6.1 ULPI Digital Block Diagram

NOTE:

The ULPI interface

is a wrapperless

design.

POR

ULPI Register Array

Interrupt Control

6pinSerial Mode

XcvrSelect[1:0]

TermSelect

OpMode[1:0]

Reset

SuspendM

3pinSerial Mode

ClockSuspendM

AutoResume

DischrgVbus

ChrgVbus

IdGndDrv

SpkLeftEn

SpkRightEn/MicEn

DpPulldown

DmPulldown

SwapDP/DM

CarkitMode

RegOutput[1:0]

ChargerPullupEnDP

ChargerPullupEnDM

TxdEn

RxdEn

Indicator Complement

Indicator Pass Thru

UseExternal Vbus Indicator

IdPullUp

Linestates[1:0]

HostDisconnect

Interface Protect Disable

VbusValid

SessionValid

SessionEnd

IdGnd

IdFloat

RidCon...Start

RidValue[2:0]

RidCon...Done

Data[7:0] High Speed TX

Full Speed TX

Low Speed TX

High Speed Data

Recovery

Full / Low Speed

Data Recovery

ULPI Protocol

Block

HS Tx Data

FS/LS Tx Data

HS RX Data

FS/LS Data

DIR

NXT

STP

Tx Data

Rx Data

USB Transmit and Receive Logic

ULPI Register Access

RESETB

ULPI Interupt

Rid State

Machi ne

To RX

Analog

To TX

Analog

Transceiver Control

OTG

Analog

To USB

Audio

Analog

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low latency PHY allows a Link to use a wrapper around a UTMI Link and still make the required USB

turn-around timing given in the USB 2.0 specification.

RxEndDelay maximum allowed by the UTMI+/ULPI for 8-bit data is 63 high speed clocks. USB3320

uses a low latency high speed receiver path to lower the RxEndDelay to 43 high speed clocks. This

low latency design gives the Link more cycles to make decisions and reduces the Link complexity. This

is the result of the “wrapper less” architecture of the USB3320. This low RxEndDelay should allow

legacy UTMI Links to use a “wrapper” to convert the UTMI+ interface to a ULPI interface.

In Figure 6.1, a single ULPI Protocol Block decodes the ULPI 8-bit bi-directional bus when the Link

addresses the PHY. The Link must use the DIR output to determine direction of the ULPI data bus.

The USB3320 is the “bus arbitrator”. The ULPI Protocol Block will route data/commands to the

transmitter or the ULPI register array.

6.1.1 ULPI Interface Signals

The UTIM+ Low Pin Interface (ULPI) uses twelve pins to connect a full OTG Host / Device USB

Transceiver to an SOC. A reduction of external pins on the transceiver is accomplished by realizing

that many of the relatively static configuration pins (xcvrselect[1:0], termselect, opmode[1:0], and

DpPullDown DmPulldown to list a few,) can be implemented by having an internal static register array.

An 8-bit bi-directional data bus clocked at 60MHz allows the Link to access this internal register array

and transfer USB packets to and from the transceiver. The remaining 3 pins function to control the

data flow and arbitrate the data bus.

Direction of the 8-bit data bus is controlled by the DIR output from the transceiver. Another output,

NXT, is used to control data flow into and out of the device. Finally, STP, which is in input to the

transceiver, terminates transfers and is used to start up and resume from Low Power Mode.

The twelve signals are described below in Ta bl e 6. 1.

USB3320 implements a Single Data Rate (SDR) ULPI interface with all data transfers happening on

the rising edge of the 60MHz ULPI Clock while operating in Synchronous Mode. The direction of the

data bus is determined by the state of DIR. When DIR is high, the transceiver is driving DATA[7:0].

When DIR is low, the Link is driving DATA[7:0].

Table 6.1 ULPI Interface Signals

SIGNAL DIRECTION DESCRIPTION

CLK I/O 60MHz ULPI clock. All ULPI signals are driven synchronous to the rising edge of

this clock. This clock can be either driven by the transceiver or the Link as

described in Section 5.4.1

DATA[7:0] I/O 8-bit bi-directional data bus. Bus ownership is determined by DIR. The Link and

transceiver initiate data transfers by driving a non-zero pattern onto the data bus.

ULPI defines interface timing for a single-edge data transfers with respect to rising

edge of the ULPI clock.

DIR OUT Controls the direction of the data bus. When the transceiver has data to transfer

to the Link, it drives DIR high to take ownership of the bus. When the transceiver

has no data to transfer it drives DIR low and monitors the bus for commands from

the Link. The transceiver will pull DIR high whenever the interface cannot accept

data from the Link, such as during PLL start-up.

STP IN The Link asserts STP for one clock cycle to stop the data stream currently on the

bus. If the Link is sending data to the transceiver, STP indicates the last byte of

data was on the bus in the previous cycle.

NXT OUT The transceiver asserts NXT to throttle the data. When the Link is sending data to

the transceiver, NXT indicates when the current byte has been accepted by the

transceiver. The Link places the next byte on the data bus in the following clock

cycle.

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Each time DIR changes, a “turn-around” cycle occurs where neither the Link nor transceiver drive the

data bus for one clock cycle. During the “turn–around“cycle, the state of DATA[7:0] is unknown and

the transceiver will not read the data bus.

Because USB uses a bit-stuffing encoding, some means of allowing the transceiver to throttle the USB

transmit data is needed. The ULPI signal NXT is used to request the next byte to be placed on the

data bus by the Link layer.

The ULPI interface supports the two basic modes of operation: Synchronous Mode and asynchronous

modes that include Low Power Mode, Serial Modes, and Carkit Mode. In Synchronous Mode, all

signals change synchronously with the 60MHz ULPI clock. In asynchronous modes the clock is off and

the ULPI bus is redefined to bring out the signals required for that particular mode of operations. The

description of synchronous Mode is described in the following sections while the descriptions of the

asynchronous modes are described in Section 6.3, Section 6.4, and Section 6.5.

6.1.2 ULPI Interface Timing in Synchronous Mode

The control and data timing relationships are given in Figure 6.2 and Tab l e 4. 3. All timing is relative to

the rising clock edge of the 60MHz ULPI Clock.

6.2 ULPI Register Access

A command from the Link begins a ULPI transfer from the Link to the USB3320. Before reading a

ULPI register, the Link must wait until DIR is low, and then send a Transmit Command Byte (TXD

CMD) byte. The TXD CMD byte informs the USB3320 of the type of data being sent. The TXD CMD

is followed by a data transfer to or from the USB3320. Table 6.2 gives the TXD command byte (TXD

CMD) encoding for the USB3320. The upper two bits of the TX CMD instruct the transceiver as to

what type of packet the Link is transmitting. The ULPI registers retain their contents when the

transceiver is in Low Power Mode, Full Speed/Low Speed Serial Mode, or Carkit Mode.

Figure 6.2 ULPI Single Data Rate Timing Diagram in Synchronous Mode

60MHz ULPI -

CLK

Control In -

STP

Data In -

DATA[7:0]

Control Out -

DIR, NXT

Data Out -

DATA[7:0]

TSC

TSD

THC

THD

TDC TDC

TDD

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6.2.1 ULPI Register Write

A ULPI register write operation is given in Figure 6.3. The TXD command with a register write

DATA[7:6] = 10b is driven by the Link at T0. The register address is encoded into DATA[5:0] of the

TXD CMD byte.

To write a register, the Link will wait until DIR is low, and at T0, drive the TXD CMD on the data bus.

At T2 the transceiver will drive NXT high. On the next rising clock edge, T3, the Link will write the

Table 6.2 ULPI TXD CMD Byte Encoding

COMMAND NAME

CMD

BITS[7:6] CMD BITS[5:0] COMMAND DESCRIPTION

Idle 00b 000000b ULPI Idle

Transmit 01b 000000b USB Transmit Packet with No Packet Identifier

(NOPID)

00XXXXb USB Transmit Packet Identifier (PID) where DATA[3:0]

is equal to the 4-bit PID. P3P2P1P0 where P3 is the

MSB.

DATA[5:0] = 6-bit register address

101111b Extended Register Write Command where the 8-bit

DATA[5:0] = 6-bit register address

101111b Extended Register Read Command where the 8-bit

Figure 6.3 ULPI Register Write in Synchronous Mode

DIR

CLK

DATA[7:0]

STP

NXT

TXD CMD

(reg write)

Idle Reg Data[n] Idle

ULPI Register Reg Data [n-1] Reg Data [n]

T0 T1 T2 T3 T5T4 T6

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an Idle on the bus and drive STP high to signal the end of the data packet. Finally, at T5, the

transceiver will latch the data into the register and the Link will pull STP low.

NXT is used to control when the Link drives the register data on the bus. DIR is low throughout this

transaction since the transceiver is receiving data from the Link. STP is used to end the transaction

and data is registered after the de-assertion of STP. After the write operation completes, the Link must

drive a ULPI Idle (00h) on the data bus or the USB3320 may decode the bus value as a ULPI

command.

A ULPI extended register write operation is shown in Figure 6.4. To write an extended register, the Link

will wait until DIR is low, and at T0, drive the TXD CMD on the data bus. At T2 the transceiver will

drive NXT high. On the next clock T3 the Link will drive the extended address. On the next rising clock

edge, T4, the Link will write the register data. At T5, the transceiver will accept the register data and

drive NXT low. The Link will drive an Idle on the bus and drive STP high to signal the end of the data

packet. Finally, at T5, the transceiver will latch the data into the register. The Link will pull STP low.

Figure 6.4 ULPI Extended Register Write in Synchronous Mode

DIR

CLK

DATA[7:0]

STP

NXT

TXD CMD

(extended reg write)

Idle Reg Data[n] Idle

ULPI Register Reg Data [n-1] Reg Data [n]

T0 T1 T2 T3 T5T4 T6

Extended

address

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6.2.2 ULPI Register Read

A ULPI register read operation is given in Figure 6.5. The Link drives a TXD CMD byte with DATA[7:6]

= 11h for a register read. DATA[5:0] of the ULPI TXD command bye contain the register address.

At T0, the Link will place the TXD CMD on the data bus. At T2, the transceiver will bring NXT high,

signaling the Link it is ready to accept the data transfer. At T3, the transceiver reads the TXD CMD,

determines it is a register read, and asserts DIR to gain control of the bus. The transceiver will also

de-assert NXT. At T4, the bus ownership has transferred back to the transceiver and the transceiver

drives the requested register onto the data bus. At T5, the Link will read the data bus and the

transceiver will drop DIR low returning control of the bus back to the Link. After the turn around cycle,

the Link must drive a ULPI Idle command at T6.

A ULPI extended register read operation is shown in Figure 6.6.To read an extended register, the Link

writes the TX CMD with the address set to 2Fh. At T2, the transceiver will assert NXT, signaling the

Link it is ready to accept the extended address. At T3, the Link places the extended register address

on the bus. At T4, the transceiver reads the extended address, and asserts DIR to gain control of the

bus. The transceiver will also de-assert NXT. At T5, the bus ownership has transferred back to the

transceiver and the transceiver drives the requested register onto the data bus. At T6, the Link will

read the data bus and the transceiver will de-assert DIR returning control of the bus back to the Link.

After the turn around cycle, the Link must drive a ULPI Idle command at T6.

Figure 6.5 ULPI Register Read in Synchronous Mode

DIR

CLK

DATA[7:0]

STP

NXT

TXD CMD

reg read

Idle

Reg DataTurn around Turn around

T1 T2 T3 T4 T5 T6

Idle

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6.2.3 ULPI RXCMD

The ULPI Link needs information which was provided by the following pins in a UTMI implementation:

linestate[1:0], rxactive, rxvalid and rxerror. When implementing the OTG functions, the VBUS and ID

pin states must also be transferred to the Link.

ULPI defines a Receive Command Byte (RXCMD) that contains this information. The Encoding of the

RXCMD byte is given in the Table 6.3.

Transfer of the RXCMD byte occurs in Synchronous Mode when the transceiver has control of the bus.

The ULPI Protocol Block shown in Figure 6.1 determines when to send an RXCMD.

A RXCMD can occur:

When a linestate change occurs.

When VBUS or ID comparators change state.

During a USB receive when NXT is low.

After the USB3320 deasserts DIR and STP is low during start-up

After the USB3320 exits Low Power Mode, Serial Modes, or Carkit Mode after detecting that the

Link has de-asserted STP, and DIR is low.

When a USB Receive is occurring, RXCMD’s are sent whenever NXT = 0 and DIR = 1. During a USB

Transmit, the RXCMD’s are returned to the Link after STP is asserted.

If an RXCMD event occurs during a USB transmit, the RXCMD is blocked until STP de-asserts at the

end of the transmit. The RXCMD contains the status that is current at the time the RXCMD is sent.

Figure 6.6 ULPI Extended Register Read in Synchronous Mode

DIR

CLK

DATA[7:0]

STP

NXT

TXD CMD

extended reg read

Idle

Reg DataTurn around Turn around

T1 T2 T3 T4 T5 T6

Idle

Extended

address

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Notes:

1. An ‘X’ is a do not care and can be either a logic 0 or 1.

2. The value of VbusValid is defined in Ta b l e 5. 6.

Note 6.1 LineState: These bits in the RXCMD byte reflect the current state of the Full-Speed single

ended receivers. LineState[0] directly reflects the current state of DP. LineState[1] directly

reflects the current state of DM. When DP=DM=0 this is called "Single Ended Zero" (SE0).

When DP=DM=1, this is called "Single Ended One" (SE1).

6.2.4 USB3320 Transmitter

The USB3320 ULPI transmitter fully supports HS, FS, and LS transmit operations. Figure 6.1 shows

the high speed, full speed, and low speed transmitter block controlled by ULPI Protocol Block.

Encoding of the USB packet follows the bit-stuffing and NRZI outlined in the USB 2.0 specification.

Many of these functions are re-used between the HS and FS/LS transmitters. When using the

USB3320, Tab l e 5 . 1 should always be used as a guideline on how to configure for various modes of

operation. The transmitter decodes the inputs of XcvrSelect[1:0], TermSelect, OpMode[1:0],

DpPulldown, and DmPulldown to determine what operation is expected. Users must strictly adhere to

the modes of operation given in Tab le 5 .1 .

Table 6.3 ULPI RX CMD Encoding

DATA[7:0] NAME DESCRIPTION AND VALUE

[1:0] Linestate UTMI Linestate Signals Note 6.1

[3:2] Encoded

VBUS

State

ENCODED VBUS VOLTAGE STATES

VALUE VBUS VOLTAGE SESSEND SESSVLD VBUSVLD2

00 VVBUS < VSESS_END 100

01 VSESS_END < VVBUS <

VSESS_VLD

000

10 VSESS_VLD < VVBUS <

VVBUS_VLD

X1 0

11 VVBUS_VLD < VVBUS XX 1

[5:4] Rx Event

Encoding ENCODED UTMI EVENT SIGNALS

VALUE RXACTIVE RXERROR HOSTDISCONNECT

00 0 0 0

01 1 0 0

11 1 1 0

10 X X 1

[6] State of

ID pin

Set to the logic state of the ID pin. A logic low indicates an A device. A logic high

indicates a B device.

[7] alt_int Asserted when a non-USB interrupt occurs. This bit is set when an unmasked event

occurs on any bit in the Carkit Interrupt Latch register. The Link must read the Carkit

Interrupt Latch register to determine the source of the interrupt. Section 5.6.1.3

describes how a change on the ID pin can generate an interrupt. Section 6.6

describes how an interrupt can be generated when the RidConversionDone bit is set.

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Several important functions for a device and host are designed into the transmitter blocks.

The USB3320 transmitter will transmit a 32-bit long high speed sync before every high speed packet.

In full and low speed modes a 8-bit sync is transmitted.

When the device or host needs to chirp for high speed port negotiation, the OpMode = 10b setting in

the Function Control register will turn off the bit-stuffing and NRZI encoding in the transmitter. At the

end of a chirp, the USB3320 OpMode bits should be changed only after the RXCMD linestate encoding

indicates that the transmitter has completed transmitting. Should the opmode be switched to normal

bit-stuffing and NRZI encoding before the transmit pipeline is empty, the remaining data in the pipeline

may be transmitted in an bit-stuff encoding format.

Please refer to the ULPI specification for a detailed discussion of USB reset and HS chirp.

6.2.4.1 High Speed Long EOP

When operating as a Hi-Speed host, the USB3320 will automatically generate a 40 bit long End of

Packet (EOP) after a SOF PID (A5h). The USB3320 determines when to send the 40-bit long EOP by

decoding the ULPI TXD CMD bits [3:0] for the SOF. The 40-bit long EOP is only transmitted when the

DpPulldown and DmPulldown bits in the OTG Control register are asserted. The Hi-Speed 40-bit long

EOP is used to detect a disconnect in high speed mode.

In device mode, the USB3320 will not send a long EOP after a SOF PID.

6.2.4.2 Low Speed Keep-Alive

Low speed keep alive is supported by the USB3320. When in Low speed (XcvrSelect = 10b in the

Function Control register), the USB3320 will send out two Low speed bit times of SE0 when a SOF

PID is received.

6.2.4.3 UTMI+ Level 3

Pre-amble is supported for UTMI+ Level 3 compatibility. When XcvrSelect = 11b in the Function Control

speed pre-amble before the low speed packet. Full speed rise and fall times are used in this mode.

The pre-amble consists of the following: Full speed sync, the encoded pre-PID (C3h) and then full

speed idle (DP=1 and DM = 0). A low speed packet follows with a sync, data and a LS EOP.

The USB3320 will only support UTMI+ Level 3 as a host. The USB3320 does not support UTMI+ Level

3 as a peripheral. A UTMI+ Level 3 peripheral is an upstream hub port. The USB3320 will not decode

a pre-amble packet intended for a LS device when the USB3320 is configured as the upstream port

of a FS hub, XcvrSelect = 11b, DpPulldown = 0b, DmPulldown =0b.

6.2.4.4 Host Resume K

Resume K generation is supported by the USB3320. When the USB3320 exits the suspended (Low

Power Mode), the USB3320, when operating as a host, will transmit a K on DP/DM. The transmitters

will end the K with SE0 for two Low Speed bit times. If the USB3320 was operating in high speed

mode before the suspend, the host must change to high speed mode before the SE0 ends. SE0 is

two low speed bit times which is about 1.2 us. For more details please see sections 7.1.77 and 7.9 of

the USB Specification.

In device mode, the resume K will not append an SE0, but release the bus to the correct idle state,

depending upon the operational mode as shown in Tab le 5 .1 .

The ULPI specification includes a detailed discussion of the resume sequence and the order of

operations required. To support Host start-up of less than 1mS the USB3320 implements the ULPI

AutoResume bit in the Interface Control register. The default AutoResume state is 0 and this bit should

be enabled for Host applications.

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6.2.4.5 No SYNC and EOP Generation (OpMode = 11)

UTMI+ defines OpMode = 11 where no sync and EOP generation occurs in Hi-Speed operation. This

is an option to the ULPI specification and not implemented in the USB3320.

6.2.4.6 Typical USB Transmit with ULPI

Figure 6.7 shows a typical USB transmit sequence. A transmit sequence starts by the Link sending a

TXD CMD where DATA[7:6] = 01b, DATA[5:4] = 00b, and Data[3:0] = PID. The TX CMD with the PID

is followed by transmit data.

During transmit the transceiver will use NXT to control the rate of data flow into the transceiver. If the

USB3320 pipeline is full or bit-stuffing causes the data pipeline to overfill NXT is de-asserted and the

Link will hold the value on Data until NXT is asserted. The USB Transmit ends when the Link asserts

STP while NXT is asserted.

Note: The Link cannot assert STP with NXT de-asserted since the USB3320 is expecting to fetch

another byte from the Link.

After the USB3320 completes transmitting, the DP and DM lines return to idle and a RXCMD is

returned to the Link so the inter-packet timers may be updated by linestate.

While operating in Full Speed or Low Speed, an End-of-Packet (EOP) is defined as SE0 for

approximately two bit times, followed by J for one bit time. The transceiver drives a J state for one bit

time following the SE0 to complete the EOP. The Link must wait for one bit time following line state

indication of the SE0 to J transition to allow the transceiver to complete the one bit time J state. All bit

times are relative to the speed of transmission.

In the case of Full Speed or Low Speed, after STP is asserted each FS/LS bit transition will generate

a RXCMD since the bit times are relatively slow.

6.2.5 USB Receiver

The USB3320 ULPI receiver fully supports HS, FS, and LS transmit operations. In all three modes the

receiver detects the start of packet and synchronizes to the incoming data packet. In the ULPI protocol,

a received packet has the priority and will immediately follow register reads and RXCMD transfers.

Figure 6.8 shows a basic USB packet received by the USB3320 over the ULPI interface.

Figure 6.7 ULPI Transmit in Synchronous Mode

DATA[7:0]

DP/DM

DIR

CLK

STP

NXT

TXD CMD

(USB tx)

Idle D0 D2 D3 IDLE

SE0 !SQUELCH SE0

Turn

Around

Turn

Around

RXD

CMD

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In Figure 6.8 the transceiver asserts DIR to take control of the data bus from the Link. The assertion

of DIR and NXT in the same cycle contains additional information that Rxactive has been asserted.

When NXT is de-asserted and DIR is asserted, the RXCMD data is transferred to the Link. After the

last byte of the USB receive packet is transferred to the transceiver, the linestate will return to idle.

The ULPI full speed receiver operates according to the UTMI / ULPI specification. In the full speed

case, the NXT signal will assert only when the Data bus has a valid received data byte. When NXT is

low with DIR high, the RXCMD is driven on the data bus.

In full speed, the USB3320 will not issue a Rxactive de-assertion in the RXCMD until the DP/DM

linestate transitions to idle. This prevents the Link from violating the two full speed bit times minimum

turn around time.

6.2.5.1 Disconnect Detection

A High Speed host must detect a disconnect by sampling the transmitter outputs during the long EOP

transmitted during a SOF packet. The USB3320 only looks for a high speed disconnect during the long

EOP where the period is long enough for the disconnect reflection to return to the host transceiver.

When a high speed disconnect occurs, the USB3320 will return a RXCMD and set the host disconnect

bit in the USB Interrupt Status register.

When in FS or LS modes, the Link is expected to handle all disconnect detection.

6.3 Low Power Mode

Low Power Mode is a power down state to save current when the USB session is suspended. The

Link controls when the transceiver is placed into or out of Low Power Mode. In Low Power Mode all

of the circuits are powered down except the interface pins, full speed receiver, VBUS comparators,

and IdGnd comparator.

Before entering Low Power Mode, the USB3320 must be configured to set the desired state of the

USB transceiver. The XcvrSelect[1:0], Ter mSelect and OpMode[1:0] bits in the Function Control

configuration as shown in Table 5.1. The DP and DM pins are configured to a high impedance state

by configuring OpMode[1:0] = 01. Pull-down resistors with a value of approximately 2MΩ are present

Figure 6.8 ULPI Receive in Synchronous Mode

DIR

CLK

DATA[7:0]

STP

NXT

Rxd

Cmd

Idle Turn

around PID D1 Rxd

Cmd D2 Turn

around

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on the DP and DM pins to avoid false linestate indications that could result if the pins were allowed to

float.

6.3.1 Entering Low Power/Suspend Mode

To enter Low Power Mode, the Link will write a 0 or clear the SuspendM bit in the Function Control

rising edges of CLKOUT, drive the clock low. After the clock is stopped, the transceiver will enter a

low power state to conserve current. Placing the transceiver in Suspend Mode is not related to USB

Suspend. To clarify this point, USB Suspend is initiated when a USB host stops data transmissions

and enters Full-Speed mode with 15KΩ pull-down resistors on DP and DM. The suspended device

goes to Full-Speed mode with a pull-up on DP. Both the host and device remain in this state until one

of them drives DM high (this is called a resume).

While in Low Power Mode, the Data interface is redefined so that the Link can monitor Linestate and

the VBUS voltage. In Low Power Mode DATA[3:0] are redefined as shown in Ta b le 6 .4 . Linestate[1:0]

is the combinational output of the Single-Ended Receivers. The “int” or interrupt signal indicates an

unmasked interrupt has occurred. When an unmasked interrupt or linestate change has occurred, the

Link is notified and can determine if it should wake-up the transceiver.

Figure 6.9 Entering Low Power Mode from Synchronous Mode

Table 6.4 Interface Signal Mapping During Low Power Mode

SIGNAL MAPS TO DIRECTION DESCRIPTION

linestate[0] DATA[0] OUT Combinatorial LineState[0] driven directly by the Full-Speed single

ended receiver. Note 6.2

linestate[1] DATA[1] OUT Combinatorial LineState[1] driven directly by the Full-Speed single

ended receiver. Note 6.2

reserved DATA[2] OUT Driven Low

int DATA[3] OUT Active high interrupt indication. Must be asserted whenever any

unmasked interrupt occurs.

reserved DATA[7:4] OUT Driven Low

DIR

CLK

DATA[7:0]

STP

NXT

TXD CMD

(reg write)

Idle Reg Data[n] Idle

T0 T1 T2 T3 T5T4 T6 T10

Turn

Around Low Power Mode

SUSPENDM

(ULPI Register Bit)

...

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Note 6.2 LineState: These signals reflect the current state of the Full-Speed single ended receivers.

LineState[0] directly reflects the current state of DP. LineState[1] directly reflects the current

state of DM. When DP=DM=0 this is called "Single Ended Zero" (SE0). When DP=DM=1,

this is called "Single Ended One" (SE1).

An unmasked interrupt can be caused by the following comparators changing state: VbusVld, SessVld,

SessEnd, and IdGnd. If any of these signals change state during Low Power Mode and the bits are

enabled in either the USB Interrupt Enable Rising or USB Interrupt Enable Falling registers, DATA[3]

will assert. During Low Power Mode, the VbusVld and SessEnd comparators can have their interrupts

masked to lower the suspend current as described in Section 6.3.4.

While in Low Power Mode, the Data bus is driven asynchronously because all of the transceiver clocks

are stopped during Low Power Mode.

6.3.2 Exiting Low Power Mode

To exit Low Power Mode, the Link will assert STP. Upon the assertion of STP, the USB3320 will begin

its start-up procedure. After the transceiver start-up is complete, the transceiver will start the clock on

CLKOUT and de-assert DIR. After DIR has been de-asserted, the Link can de-assert STP when ready

and start operating in Synchronous Mode. The transceiver will automatically set the SuspendM bit to

a 1 in the Function Control register.

The value for TSTART is given in Ta b l e 4 . 2 .

Should the Link de-assert STP before DIR is de-asserted, the USB3320 will detect this as a false

resume request and return to Low Power Mode. This is detailed in section 3.9.4 of the ULPI 1.1

specification.

6.3.3 Interface Protection

ULPI protocol assumes that both the Link and transceiver will keep the ULPI data bus driven by either

the Link when DIR is low or the transceiver when DIR is high. The only exception is when DIR has

changed state and a turn around cycle occurs for 1 clock period.

In the design of a USB system, there can be cases where the Link may not be driving the ULPI bus

to a known state while DIR is low. Two examples where this can happen is because of a slow Link

start-up or a hardware reset.

Figure 6.10 Exiting Low Power Mode

DIR

CLK

DATA[7:0]

STP

TURN

AROUND

LOW

POWER MODE

DATA BUS IGNORED (SLOW LINK)

IDLE (FAST LINK) IDLE

T0 T1 T2 T3 T5T4

Slow Link Drives Bus

Idle and STP low

Fast Link Drives Bus

Idle and STP low

...

Note: Not to Scale

TSTART

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6.3.3.1 Start up Protection

Upon start-up, when the transceiver de-asserts DIR, the Link must be ready to receive commands and

drive Idle on the data bus. If the Link is not ready to receive commands or drive Idle, it must assert

STP before DIR is de-asserted. The Link can then de-assert STP when it has completed its start-up.

If the Link doesn’t assert STP before it can receive commands, the transceiver may interpret the data

bus state as a TX CMD and transmit invalid data onto the USB bus, or make invalid register writes.

When the USB3320 sends a RXCMD the Link is required to drive the data bus back to idle at the end

of the turn around cycle. If the Link does not drive the databus to idle the USB3320 may take the

information on the data bus as a TXCMD and transmit data on DP and DM until the Link asserts stop.

If the ID pin is floated the last RXCMD from the USB3320 will remain on the bus after DIR is de-

asserted and the USB3320 will take this in as a TXCMD.

A Link should be designed to have the default POR state of the STP output high and the data bus tri-

stated. The USB3320 has weak pull-downs on the data bus to prevent these inputs from floating when

not driven. These resistors are only used to prevent the ULPI interface from floating during events

when the link ULPI pins may be tri-stated. The strength of the pull down resistors can be found in

Table 4.4. The pull downs are not strong enough to pull the data bus low after a ULPI RXCMD, the

Link must drive the data bus to idle after DIR is de-asserted.

In some cases, a Link may be software configured and not have control of its STP pin until after the

transceiver has started. In this case, the USB3320 has in internal pull-up on the STP input pad which

will pull STP high while the Link’s STP output is tri-stated. The STP pull-up resistor is enabled on POR

and can be disabled by setting the InterfaceProtectDisable bit 7 of the Interface Control register.

The STP pull-up resistor will pull-up the Link’s STP input high until the Link configures and drives STP

high. After the Link completes its start-up, STP can be synchronously driven low.

A Link design which drives STP high during POR can disable the pull-up resistor on STP by setting

InterfaceProtectDisable bit to 1. A motivation for this is to reduce the suspend current. In Low Power

Mode, STP is held low, which would draw current through the pull-up resistor on STP.

6.3.3.2 Warm Reset

Designers should also consider the case of a warm restart of a Link with a transceiver in Low Power

Mode. After the transceiver enters Low Power Mode, DIR is asserted and the clock is stopped. The

USB3320 looks for STP to be asserted to re-start the clock and then resume normal synchronous

operation.

Should the USB3320 be suspended in Low Power Mode, and the Link receives a hardware reset, the

transceiver must be able to recover from Low Power Mode and start its clock. If the Link asserts STP

on reset, the transceiver will exit Low Power Mode and start its clock.

If the Link does not assert STP on reset, the interface protection pull-up can be used. When the Link

is reset, its STP output will tri-state and the pull-up resistor will pull STP high, signaling the transceiver

to restart its clock.

6.3.4 Minimizing Current in Low Power Mode

In order to minimize the suspend current in Low Power Mode, the OTG comparators can be disabled

to reduce suspend current. In Low Power Mode, the VbusVld and SessEnd comparators are not

needed and can be disabled by clearing the associated bits in both the USB Interrupt Enable Rising

and USB Interrupt Enable Falling registers. By disabling the interrupt in BOTH the rise and fall

registers, the SessEnd and VbusVld comparators are turned off. The IdFloatRise and IdFloatFall bits

in Carkit Interrupt Enable register should also be disabled if they were set. When exiting Low Power

Mode, the Link should immediately re-enable the VbusVld and SessEnd comparators if host or OTG

functionality is required.

In addition to disabling the OTG comparators in Low Power Mode, the Link may choose to disable the

Interface Protect Circuit. By setting the InterfaceProtectDisable bit high in the Interface Control register,

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the Link can disable the pull-up resistor on STP. When RESETB is low the Interface Protect Circuit

will be disabled.

6.4 Full Speed/Low Speed Serial Modes

The USB3320 includes two serial modes to support legacy Links which use either the 3pin or 6pin

serial format. To enter either serial mode, the Link will need to write a 1 to the 6-pin FsLsSerialMode

or the 3-pin FsLsSerialMode bits in the Interface control register. Serial Mode may be used to conserve

power when attached to a device that is not capable of operating in Hi-Speed.

The serial modes are entered in the same manner as the entry into Low Power Mode. The Link writes

the Interface Control register bit for the specific serial mode. The USB3320 will assert DIR and shut

off the clock after at least five clock cycles. Then the data bus goes to the format of the serial mode

selected. Before entering Serial Mode the Link must set the ULPI transceiver to the appropriate mode

as defined in Ta b l e 5. 1.

In ULPI Output Clock Mode, the transceiver will shut off the 60MHz clock to conserve power. Should

the Link need the 60MHz clock to continue during the serial mode of operation, the ClockSuspendM

bit[3] of the Interface Control Register should be set before entering a serial mode. If set, the 60 MHz

clock will be present during serial modes.

In serial mode, interrupts are possible from unmasked sources. The state of each interrupt source is

sampled prior to the assertion of DIR and this is compared against the asynchronous level from

interrupt source.

Exiting the serial modes is the same as exiting Low Power Mode. The Link must assert STP to signal

the transceiver to exit serial mode. When the transceiver can accept a command, DIR is de-asserted

and the transceiver will wait until the Link de-asserts STP to resume synchronous ULPI operation. The

RESETB pin can also be pulsed low to reset the USB3320 and return it to Synchronous Mode.

6.4.0.1 3pin FS/LS Serial Mode

Three pin serial mode utilizes the data bus pins for the serial functions shown in Table 6.5.

Table 6.5 Pin Definitions in 3 Pin Serial Mode

SIGNAL

CONNECTED

TO DIRECTION DESCRIPTION

tx_enable DATA[0] IN Active High transmit enable.

data DATA[1] I/O TX differential data on DP/DM when tx_enable is high.

RX differential data from DP/DM when tx_enable is low.

SE0 DATA[2] I/O TX SE0 on DP/DM when tx_enable is high.

RX SE0_b from DP/DM when tx_enable is low.

interrupt DATA[3] OUT Asserted when any unmasked interrupt occurs. Active high.

Reserved DATA[7:4] OUT Driven Low.

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6.4.0.2 6Pin FS/LS Serial Mode

Six pin serial mode utilizes the data bus pins for the serial functions shown in Table 6.6.

6.5 Carkit Mode

The USB3320 includes Carkit Mode to support a USB UART and USB Audio Mode.

By entering Carkit Mode, the USB3320 current drain is minimized. When operating in ULPI Input Clock

Mode (60MHz REFCLK Mode), the CLKOUT is stopped to conserve power by default. The Link may

configure the 60MHz clock to continue by setting the ClockSuspendM bit of the Interface Control

operation.

In Carkit Mode, interrupts are possible if they have been enabled in the Carkit Interrupt Enable register.

The state of each interrupt source is sampled prior to the assertion of DIR and this is compared against

the asynchronous level from interrupt source. In Carkit Mode, the Linestate signals are not available

per the ULPI specification.

Exiting Carkit Mode is the same as exiting Low Power Mode as described in Section 6.3.2. The Link

must assert STP to signal the transceiver to exit serial mode. When the transceiver can accept a

command, DIR is de-asserted and the transceiver will wait until the Link de-asserts STP to resume

synchronous ULPI operation. The RESETB pin can also be pulsed low to reset the USB3320 and

return it to Synchronous Mode.

Table 6.6 Pin Definitions in 6 Pin Serial Mode

SIGNAL

CONNECTED

TO DIRECTION DESCRIPTION

tx_enable DATA[0] IN Active High transmit enable.

tx_data DATA[1] IN Tx differential data on DP/DM when tx_enable is high.

tx_se0 DATA[2] IN Tx SE0 on DP/DM when tx_enable is high.

interrupt DATA[3] OUT Asserted when any unmasked interrupt occurs. Active high.

rx_dp DATA[4] OUT Single ended receive data on DP.

rx_dm DATA[5] OUT Single ended receive data on DM.

rx_rcv DATA[6] OUT Differential receive data from DP and DM.

Reserved DATA[7] OUT Driven Low.

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6.5.1 USB UART Mode

The USB3320 can be placed into UART Mode by first setting the TxdEn and RxdEn bits in the Carkit

Control register. Then the Link can set the CarkitMode bit in the Interface Control register. The TxdEn

and RxdEn bits must be written before the CarkitMode bit.

After the CarkitMode bit is set, the ULPI interface will become redefined as described in Ta bl e 6 . 8 , and

the USB3320 will transmit data through the DATA[0] to DM of the USB connector and receive data on

DP and pass the information the Link on DATA[1].

When entering UART mode, the regulator output will automatically switch to the value configured by

the UART RegOutput bits in the USB IO & Power Management register and a pull-up will be applied

internally to DP and DM. This will hold the UART in its default operating state.

While in UART mode, the transmit edge rates can be set to either the Full Speed USB or Low Speed

USB edge rates by using the XcvrSelect[1:0] bits in the Function Control register.

Table 6.7 ULPI Register Programming Example to Enter UART Mode

R/W

ADDRESS

(HEX)

VALUE

(HEX) DESCRIPTION RESULT

W 04 49 Configure Non-Driving mode

Select FS transmit edge rates

OpMode=01

XcvrSelect=01

W 39 00 Set regulator to 3.3V UART RegOutput=00

W 19 0C Enable UART connections RxdEn=1

TxdEn=1

W 07 04 Enable carkit mode CarkitMode=1

Table 6.8 Pin Definitions in Carkit Mode

SIGNAL

CONNECTED

TO DIRECTION DESCRIPTION

txd DATA[0] IN UART TXD signal that is routed to the DM pin if the TxdEn

is set in the Carkit Control register.

rxd DATA[1] OUT UART RXD signal that is routed to the DP pin if the RxdEn

bit is set in the Carkit Control register.

reserved DATA[2] OUT Driven Low.

int DATA[3] OUT Asserted when any unmasked interrupt occurs. Active high.

reserved DATA[4:7] OUT Driven Low.

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6.5.2 USB Audio Mode

When the USB3320 is powered in Synchronous Mode, the Audio switches can be enabled by asserting

the SpkLeftEn, or SpkRightEn bits in the Carkit Control register. After the register write is complete,

the USB3320 will immediately enable or disable the audio switch. Then the Link can set the

CarkitMode bit in the Interface Control register. The SpkLeftEn, or SpkRightEn bits must be written

before the CarkitMode bit.

After the CarkitMode bit is set, the ULPI interface will become redefined as described in Table 6.8.

6.6 RID Converter Operation

The RID converter is designed to read the value of the ID resistance to ground and report back its

value through the ULPI interface.

When a resistor to ground is applied to the ID pin the state of the IdGnd comparator will change from

a 1 to a 0 as described in Section 5.6.1. If the USB3320 is in ULPI mode, an RXCMD will be generated

with bit 6 low. If the USB3320 is in Low Power Mode (or one of the other non-ULPI modes), the

DATA[3] interrupt signal will go high.

After the USB3320 has detected the change of state on the ID pin, the RID converter can be used to

determine the value of ID resistance. To start a ID resistance measurement, the RidConversionStart

bit is set in the Vendor Rid Conversion register.

The Link can use one of two methods to determine when the RID Conversion is complete. One method

is polling the RidConversionStart bit as described in Section 7.1.3.3. The preferred method is to set

the RidIntEn bit in the Vendor Rid Conversion register. When RidIntEn is set, an RXCMD will be

generated after the RID conversion is complete. As described in Table 6.3, the alt_int bit of the RXCMD

will be set.

After the RID Conversion is complete, the Link can read RidValue from the Vendor Rid Conversion

6.7 Headset Audio Mode

This mode is designed to allow a user to view the status of several signals while using an analog audio

headset with a USB connector. This feature, exclusive to SMSC, is provided as an alternate mode to

the CarKit Mode defined in Section 6.5. In the CarKit Mode, the Link is unable to view the source of

the interrupt on ID, except by returning to synchronous mode to read the ULPI registers. This forces

the audio switches to be deactivated, and may glitch the audio signals. In addition, the Link cannot

change the resistance on the ID pin without starting up the PHY to access the ULPI registers.

The Headset Audio Mode is entered by writing to the Headset Audio Mode register, and allows the

Link access to the state of the VBUS and ID pins during audio without glitching the audio connection.

The Headset Audio mode also enables the Link to change the resistance on the ID pin and to change

the audio headset attached from mono to stereo.

Table 6.9 ULPI Register Programming Example to Enter Audio Mode

R/W

ADDRESS

(HEX)

VALUE

(HEX) DESCRIPTION RESULT

W 04 48 Configure Non-Driving mode OpMode=01

W 19 30 Enable Audio connections SpkrRightEn=1, SpkrLeftEn=1

W 07 04 Enable carkit mode CarkitMode=1

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The ULPI interface is redefined as shown in Table 6.10 when Headset Audio Mode is entered.

Exiting Headset Audio Mode is the same as exiting Low Power Mode as described in Section 6.3.2.

The Link must assert STP to signal the PHY to exit. When the PHY can accept a command, DIR is

de-asserted and the PHY will wait until the Link de-asserts STP to resume synchronous ULPI

operation. The RESETB pin can also be pulsed low to reset the USB3320 and return it to Synchronous

Mode.

Table 6.10 Pin Definitions in Headset Audio Mode

SIGNAL

CONNECTED

TO DIRECTION DESCRIPTION

SessVld DATA[0] OUT Output of SessVld comparator

VbusVld DATA[1] OUT Output of VbusVld Comparator (interrupt must be enabled)

IdGndDrv DATA[2] IN Drives ID pin to ground when asserted

0b: Not connected

1b: Connects ID to ground.

DATA[3] OUT Driven low

IdGround DATA[4] OUT Asserted when the ID pin is grounded.

0b: ID pin is grounded

1b: ID pin is floating

IdFloat DATA[5] OUT Asserted when the ID pin is floating. IdPullup or

d_pullup330 must be enabled as shown below.

IdPullup330 DATA[6] IN When enabled a 330kΩpullup is applied to the ID pin. This

bit will also change the trip point of the IdGnd comparator

to the value shown in Ta bl e 4. 7.

0b: Disables the pull-up resistor

1b: Enables the pull-up resistor

IdPullup DATA[7] IN Connects the 100kΩ pull-up resistor from the ID pin to

VDD3.3

0b: Disables the pull-up resistor

1b: Enables the pull-up resistor

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Chapter 7 ULPI Register Map

7.1 ULPI Register Array

The USB3320 Transceiver implements all of the ULPI registers detailed in the ULPI revision 1.1

specification. The complete USB3320 ULPI register set is shown in Table 7.1. All registers are 8 bits.

This table also includes the default state of each register upon POR or de-assertion of RESETB, as

described in Section 5.5.2. The RESET bit in the Function Control Register does not reset the bits of

the ULPI register array. The Link should not read or write to any registers not listed in this table.

The USB3320 supports extended register access. The immediate register set (00-3Fh) can be

accessed through either a immediate address or an extended register address.

Table 7.1 ULPI Register Map

DEFAULT

STATE

ADDRESS (6BIT)

READ WRITE SET CLEAR

Vendor ID Low 24h00h---

Vendor ID High 04h01h---

Product ID Low 07h02h---

Product ID High 00h03h---

Function Control 41h 04-06h 04h 05h 06h

Interface Control 00h 07-09h 07h 08h 09h

OTG Control 06h 0A-0Ch 0Ah 0Bh 0Ch

USB Interrupt Enable Rising 1Fh 0D-0Fh 0Dh 0Eh 0Fh

USB Interrupt Enable Falling 1Fh 10-12h 10h 11h 12h

USB Interrupt Status (Note 7.1) 00h13h---

USB Interrupt Latch 00h14h---

Debug 00h15h---

Scratch Register 00h 16-18h 16h 17h 18h

Carkit Control 00h 19-1Bh 19h 1Ah 1Bh

Reserved 00h 1Ch

Carkit Interrupt Enable 00h 1D-1Fh 1Dh 1Eh 1Fh

Carkit Interrupt Status 00h20h---

Carkit Interrupt Latch 00h21h---

Reserved 00h 22-30h

HS TX Boost 00h 31h 31h - -

Reserved 00h 32h 32h - -

Headset Audio Mode 00h 33h 33h - -

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Note 7.1 Dynamically updates to reflect current status of interrupt sources.

7.1.1 ULPI Register Set

The following registers are used for the ULPI interface.

7.1.1.1 Vendor ID Low

Address = 00h (read only)

7.1.1.2 Vendor ID High

Address = 01h (read only)

7.1.1.3 Product ID Low

Address = 02h (read only)

7.1.1.4 Product ID High

Address = 03h (read only)

Reserved 00h 34-35h

Vendor Rid Conversion 00h 36-38h 36h 37h 38h

USB IO & Power Management 04h 39-3Bh 39h 3Ah 3Bh

Reserved 00h 3C-3Fh

FIELD NAME BIT ACCESS DEFAULT DESCRIPTION

Vendor ID Low 7:0 rd 24h SMSC Vendor ID

FIELD NAME BIT ACCESS DEFAULT DESCRIPTION

Vendor ID High 7:0 rd 04h SMSC Vendor ID

FIELD NAME BIT ACCESS DEFAULT DESCRIPTION

Product ID Low 7:0 rd 07h SMSC Product ID

Table 7.1 ULPI Register Map (continued)

DEFAULT

STATE

ADDRESS (6BIT)

READ WRITE SET CLEAR

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7.1.1.5 Function Control

Address = 04-06h (read), 04h (write), 05h (set), 06h (clear)

7.1.1.6 Interface Control

Address = 07-09h (read), 07h (write), 08h (set), 09h (clear)

FIELD NAME BIT ACCESS DEFAULT DESCRIPTION

Product ID High 7:0 rd 00h SMSC Product ID

FIELD NAME BIT ACCESS DEFAULT DESCRIPTION

XcvrSelect[1:0] 1:0 rd/w/s/c 01b Selects the required transceiver speed.

00b: Enables HS transceiver

01b: Enables FS transceiver

10b: Enables LS transceiver

11b: Enables FS transceiver for LS packets (FS

preamble automatically pre-pended)

TermSelect 2 rd/w/s/c 0b Controls the DP and DM termination depending on

XcvrSelect, OpMode, DpPulldown, and DmPulldown.

The DP and DM termination is detailed in Tab le 5 .1 .

OpMode 4:3 rd/w/s/c 00b Selects the required bit encoding style during

transmit.

00b: Normal Operation

01b: Non-Driving

10b: Disable bit-stuff and NRZI encoding

11b: Reserved

Reset 5 rd/w/s/c 0b Active high transceiver reset. This reset does not

reset the ULPI interface or register set. Automatically

clears after reset is complete.

SuspendM 6 rd/w/s/c 1b Active low PHY suspend. When cleared the

transceiver will enter Low Power Mode as detailed in

6.3. Automatically set when exiting Low Power Mode.

Reserved 7 rd 0b Read only, 0.

FIELD NAME BIT ACCESS DEFAULT DESCRIPTION

6-pin FsLsSerialMode 0 rd/w/s/c 0b When asserted the ULPI interface is redefined to the

6-pin Serial Mode. The transceiver will automatically

clear this bit when exiting serial mode.

3-pin FsLsSerialMode 1 rd/w/s/c 0b When asserted the ULPI interface is redefined to the

3-pin Serial Mode. The transceiver will automatically

clear this bit when exiting serial mode.

CarkitMode 2 rd/w/s/c 0b When asserted the ULPI interface is redefined to the

Carkit interface. The transceiver will automatically

clear this bit when exiting Carkit Mode.

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7.1.1.7 OTG Control

Address = 0A-0Ch (read), 0Ah (write), 0Bh (set), 0Ch (clear)

ClockSuspendM 3 rd/w/s/c 0b Enables Link to turn on 60MHz CLKOUT in Serial

Mode or Carkit Mode.

0b: Disable clock in serial or Carkit Mode.

1b: Enable clock in serial or Carkit Mode.

AutoResume 4 rd/w/s/c 0b Only applicable in Host mode. Enables the

transceiver to automatically transmit resume

signaling. This function is detailed in Section 6.2.4.4.

IndicatorComplement 5 rd/w/s/c 0b Inverts the EXTVBUS signal. This function is detailed

in Section 5.6.2.

Note: The EXTVBUS signal is always high on the

USB3320.

IndicatorPassThru 6 rd/w/s/c 0b Disables and’ing the internal VBUS comparator with

the EXTVBUS signal when asserted. This function is

detailed in Section 5.6.2.

Note: The EXTVBUS signal is always high on the

USB3320.

InterfaceProtectDisable 7 rd/w/s/c 0b Used to disable the integrated STP pull-up resistor

used for interface protection. This function is detailed

in Section 6.3.3.

FIELD NAME BIT ACCESS DEFAULT DESCRIPTION

IdPullup 0 rd/w/s/c 0b Connects a 100kΩ pull-up resistor from the ID pin to

VDD33

0b: Disables the pull-up resistor

1b: Enables the pull-up resistor

DpPulldown 1 rd/w/s/c 1b Enables the 15k Ohm pull-down resistor on DP.

0b: Pull-down resistor not connected

1b: Pull-down resistor connected

DmPulldown 2 rd/w/s/c 1b Enables the 15k Ohm pull-down resistor on DM.

0b: Pull-down resistor not connected

1b: Pull-down resistor connected

DischrgVbus 3 rd/w/s/c 0b This bit is only used during SRP. Connects a resistor

from VBUS to ground to discharge VBUS.

0b: disconnect resistor from VBUS to ground

1b: connect resistor from VBUS to ground

ChrgVbus 4 rd/w/s/c 0b This bit is only used during SRP. Connects a resistor

from VBUS to VDD33 to charge VBUS above the

SessValid threshold.

0b: disconnect resistor from VBUS to VDD33

1b: connect resistor from VBUS to VDD33

DrvVbus 5 rd/w/s/c 0b Enables external 5 volt supply to drive 5 volts on

VBUS. This signal is or’ed with DrvVbusExternal.

0b: Do not drive Vbus, CPEN driven low.

1b: Drive Vbus, CPEN driven high.

FIELD NAME BIT ACCESS DEFAULT DESCRIPTION

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7.1.1.8 USB Interrupt Enable Rising

Address = 0D-0Fh (read), 0Dh (write), 0Eh (set), 0Fh (clear)

7.1.1.9 USB Interrupt Enable Falling

Address = 10-12h (read), 10h (write), 11h (set), 12h (clear)

DrvVbusExternal 6 rd/w/s/c 0b Enables external 5 volt supply to drive 5 volts on

VBUS. This signal is or’ed with DrvVbus.

0b: Do not drive Vbus, CPEN driven low.

1b: Drive Vbus, CPEN driven high.

UseExternalVbus

Indicator

7 rd/w/s/c 0b Tells the transceiver to use an external VBUS over-

current or voltage indicator. This function is detailed

in Section 5.6.2.

0b: Use the internal VbusValid comparator

1b: Use the EXTVBUS input as for VbusValid signal.

Note: The EXTVBUS signal is always high on the

USB3320.

FIELD NAME BIT ACCESS DEFAULT DESCRIPTION

HostDisconnect Rise 0 rd/w/s/c 1b Generate an interrupt event notification when

Hostdisconnect changes from low to high. Applicable

only in host mode.

VbusValid Rise 1 rd/w/s/c 1b Generate an interrupt event notification when

Vbusvalid changes from low to high.

SessValid Rise 2 rd/w/s/c 1b Generate an interrupt event notification when

SessValid changes from low to high.

SessEnd Rise 3 rd/w/s/c 1b Generate an interrupt event notification when

SessEnd changes from low to high.

IdGnd Rise 4 rd/w/s/c 1b Generate an interrupt event notification when IdGnd

changes from low to high.

Reserved 7:5 rd 000b Read only, 0.

FIELD NAME BIT ACCESS DEFAULT DESCRIPTION

HostDisconnect Fall 0 rd/w/s/c 1b Generate an interrupt event notification when

Hostdisconnect changes from high to low. Applicable

only in host mode.

VbusValid Fall 1 rd/w/s/c 1b Generate an interrupt event notification when

Vbusvalid changes from high to low.

SessValid Fall 2 rd/w/s/c 1b Generate an interrupt event notification when

SessValid changes from high to low.

SessEnd Fall 3 rd/w/s/c 1b Generate an interrupt event notification when

SessEnd changes from high to low.

IdGnd Fall 4 rd/w/s/c 1b Generate an interrupt event notification when IdGnd

changes from high to low.

FIELD NAME BIT ACCESS DEFAULT DESCRIPTION

Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver

Datasheet

Revision 1.0 (07-14-09) 66 SMSC USB3320

DATASHEET

7.1.1.10 USB Interrupt Status

Address = 13h (read only)

This register dynamically updates to reflect current status of interrupt sources.

Note: The default conditions will match the current status of the comparators. The values shown are

for an unattached OTG device.

7.1.1.11 USB Interrupt Latch

Address = 14h (read only with auto clear)

Note 7.2 rd: Read Only with auto clear.

Reserved 7:5 rd 000b Read only, 0.

FIELD NAME BIT ACCESS DEFAULT DESCRIPTION

HostDisconnect 0rd 0b Current value of the UTMI+ Hi-Speed Hostdisconnect

output. Applicable only in host mode.

VbusValid 1 rd 0b Current value of the UTMI+ Vbusvalid output.

SessValid 2 rd 0b Current value of the UTMI+ SessValid output.

SessEnd 3 rd 0b Current value of the UTMI+ SessEnd output.

IdGnd 4 rd 0b Current value of the UTMI+ IdGnd output.

Reserved 7:5 rd 000b Read only, 0.

FIELD NAME BIT ACCESS DEFAULT DESCRIPTION

HostDisconnect Latch 0rd

(Note 7.2)

0b Set to 1b by the transceiver when an unmasked

event occurs on Hostdisconnect. Cleared when this

VbusValid Latch 1rd

(Note 7.2)

0b Set to 1b by the transceiver when an unmasked

event occurs on VbusValid. Cleared when this

SessValid Latch 2rd

(Note 7.2)

0b Set to 1b by the transceiver when an unmasked

event occurs on SessValid. Cleared when this

SessEnd Latch 3rd

(Note 7.2)

0b Set to 1b by the transceiver when an unmasked

event occurs on SessEnd. Cleared when this register

is read.

IdGnd Latch 4rd

(Note 7.2)

0b Set to 1b by the transceiver when an unmasked

event occurs on IdGnd. Cleared when this register is

read.

Reserved 7:5 rd 000b Read only, 0.

FIELD NAME BIT ACCESS DEFAULT DESCRIPTION

Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver

Datasheet

SMSC USB3320 67 Revision 1.0 (07-14-09)

DATASHEET

7.1.1.12 Debug

Address = 15h (read only)

7.1.1.13 Scratch Register

Address = 16-18h (read), 16h (write), 17h (set), 18h (clear)

7.1.2 Carkit Control Registers

The following registers are used to set-up and enable the USB UART and USB Audio functions.

7.1.2.1 Carkit Control

Address = 19-1Bh (read), 19h (write), 1Ah (set), 1Bh (clear)

This register is used to program the USB3320 into and out of the Carkit Mode. When entering the

UART mode the Link must first set the desired TxdEn and the RxdEn bits and then transition to Carkit

Mode by setting the CarkitMode bit in the Interface Control Register. When RxdEn is not set then the

DATA[1] pin is held to a logic high.

Note: If SpkRightEn or MicEn are asserted the DP pin will be connected to SPK_R. To disconnect

the DP pin from the SPK_R pin both SpkrRightEn and MicEn must be set to de-asserted.

FIELD NAME BIT ACCESS DEFAULT DESCRIPTION

Linestate0 0 rd 0b Contains the current value of Linestate[0].

Linestate1 1 rd 0b Contains the current value of Linestate[1].

Reserved 7:2 rd 000000b Read only, 0.

FIELD NAME BIT ACCESS DEFAULT DESCRIPTION

Scratch 7:0 rd/w/s/c 00h Empty register byte for testing purposes. Software

can read, write, set, and clear this register and the

transceiver functionality will not be affected.

FIELD NAME BIT ACCESS DEFAULT DESCRIPTION

CarkitPwr 0 rd 0b Read only, 0.

IdGndDrv 1 rd/w/s/c 0b Drives ID pin to ground

TxdEn 2 rd/w/s/c 0b Connects UART TXD (DATA[0]) to DM

RxdEn 3 rd/w/s/c 0b Connects UART RXD (DATA[1]) to DP

SpkLeftEn 4 rd/w/s/c 0b Connects DM pin to SPK_L pin

SpkRightEn 5 rd/w/s/c 0b Connects DP pin to SPK_R pin. See Note below.

MicEn 6 rd/w/s/c 0b Connects DP pin to SPK_R pin. See Note below.

Reserved 7 rd 0b Read only, 0.

Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver

Datasheet

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DATASHEET

If using USB UART mode the UART data will appear at the SPK_L and SPK_R pins if the

corresponding SpkLeftEn, SpkRightEn, or MicEn switches are enabled.

If using USB Audio the TxdEn and RxdEn bits should not be set when the SpkLeftEn, SpkRightEn, or

MicEn switches are enabled. The USB single-ended receivers described in Section 5.2.1 are disabled

when either SpkLeftEn, SpkRightEn, or MicEn are set.

7.1.2.2 Carkit Interrupt Enable

Address = 1D-1Fh (read), 1Dh (write), 1Eh (set), 1Fh (clear)

7.1.2.3 Carkit Interrupt Status

Address = 20h (read only)

FIELD NAME BIT ACCESS DEFAULT DESCRIPTION

IdFloatRise 0 rd/w/s/c 0b When enabled an interrupt will be generated on the

alt_int of the RXCMD byte when the ID pin transitions

from non-floating to floating. The IdPullup bit in the

OTG Control register should be set.

IdFloatFall 1 rd/w/s/c 0b When enabled an interrupt will be generated on the

alt_int of the RXCMD byte when the ID pin transitions

from floating to non-floating. The IdPullup bit in the

OTG Control register should be set.

CarIntDet 2 rd 0b Not Implemented. Reads as 0b.

CarDpRise 3 rd 0b Not Implemented. Reads as 0b.

CarDpFall 4 rd 0b Not Implemented. Reads as 0b.

RidIntEn 5 rd/w/s/c 0b When enabled an interrupt will be generated on the

alt_int of the RXCMD byte when RidConversionDone

bit is asserted.

Note: This register bit is or’ed with the RidIntEn bit

of the Vendor Rid Conversion register

described in Section 7.1.3.3.

Reserved 7:6 rd 00b Read only, 0.

FIELD NAME BIT ACCESS DEFAULT DESCRIPTION

IdFloat 0 rd 0b Asserted when the ID pin is floating. IdPullup must be

enabled.

CarIntDet 1 rd 0b Not Implemented. Reads as 0b.

CarDp 2 rd 0b Not Implemented. Reads as 0b.

Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver

Datasheet

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DATASHEET

7.1.2.4 Carkit Interrupt Latch

Address = 21h (read only with auto-clear)

Note 7.3 rd: Read Only with auto clear

RidValue 5:3 rd 000b Conversion value of Rid resistor

000: 0 ohms

001: 75 ohms

010: 102K ohms

011: 200K ohms

100: 440K ohms

101: ID floating

111: Error

Note: RidValue can also be read from the Vendor

Rid Conversion register described in

Section 7.1.3.3.

RidConversionDone 6 rd 0b Automatically asserted by the USB3320 when the

Rid Conversion is finished. The conversion will take

282uS. This bit will auto clear when the RidValue is

read from the Rid Conversion Register. Reading the

RidValue from the Carkit Interrupt Status register will

not clear either RidConversionDone status bit.

Note: RidConversionDone can also be read from

the Vendor Rid Conversion register

described in Section 7.1.3.3.

Reserved 7 rd 0b Read only, 0.

FIELD NAME BIT ACCESS DEFAULT DESCRIPTION

IdFloat Latch 0rd

(Note 7.3)

0b Asserted if the state of the ID pin changes from non-

floating to floating while the IdFloatRise bit is enabled

or if the state of the ID pin changes from floating to

non-floating while the IdFloatFall bit is enabled.

CarIntDet Latch 1 rd 0b Not Implemented. Reads as 0b.

CarDp Latch 2 rd 0b Not Implemented. Reads as 0b.

RidConversionLatch 3rd

(Note 7.3)

0b If RidIntEn is set and the state of the

RidConversionDone bit changes from a 0 to 1 this bit

will be asserted.

Reserved 7:4 rd 0000b Read only, 0.

FIELD NAME BIT ACCESS DEFAULT DESCRIPTION

Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver

Datasheet

Revision 1.0 (07-14-09) 70 SMSC USB3320

DATASHEET

7.1.3 Vendor Register Access

The vendor specific registers include the range from 30h to 3Fh. These can be accessed by the ULPI

immediate register read / write.

7.1.3.1 HS TX Boost

Address = 31h (read / write)

7.1.3.2 Headset Audio Mode

Address = 33h (read / write)

7.1.3.3 Vendor Rid Conversion

Address = 36-38h (read), 36h (write), 37h (set), 38h (clear)

FIELD NAME BIT ACCESS DEFAULT DESCRIPTION

Reserved 4:0 rd 00000b Read only, 0.

Boost 6:5 rd/w 00b Sets the HS transmitter amplitude as described in

Section 5.2.1.

00b: Nominal

01b: Enables 11.1% increased drive strength

10b: Enables 7.4% increased drive strength

11b: Enables 3.7% increased drive strength

Reserved 7 rd 0b Read only, 0.

FIELD NAME BIT ACCESS DEFAULT DESCRIPTION

HeadsetAudioEn 3:0 rd/w 0000b When this field is set to a value of 1010, the Headset

Audio Mode is enabled as described in Section 6.7.

Reserved 7:4 rd 0h Read only, 0.

FIELD NAME BIT ACCESS DEFAULT DESCRIPTION

RidValue 2:0 rd/w 000b Conversion value of Rid resistor

000: 0 ohms

001: 75 ohms

010: 100K ohms

011: 200K ohms

100: 440K ohms

101: ID floating

111: Error

Note: RidValue can also be read from the Carkit

Interrupt Status Register.

Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver

Datasheet

SMSC USB3320 71 Revision 1.0 (07-14-09)

DATASHEET

Note 7.4 rd: Read Only with auto clear.

7.1.3.4 USB IO & Power Management

Address = 39-3Bh (read), 39h (write), 3Ah (set), 3Bh (clear)

RidConversionDone 3rd

(Note 7.4)

0b Automatically asserted by the USB3320 when the

Rid Conversion is finished. The conversion will take

282uS. This bit will auto clear when the RidValue is

read from the Rid Conversion Register. Reading the

RidValue from the Carkit Interrupt Status Register will

not clear either RidConversionDone status bit.

Note: RidConversionDone can also be read from

the Carkit Interrupt Status Register.

RidConversionStart 4 rd/w/s/c 0b When this bit is asserted either through a register

write or set, the Rid converter will read the value of

the ID resistor. When the conversion is complete this

bit will auto clear.

Reserved 5 rd/w/s/c 0b This bit must remain at 0.

RidIntEn 6 rd/w/s/c 0b When enabled an interrupt will be generated on the

alt_int of the RXCMD byte when RidConversionDone

bit is asserted.

Note: This register bit is or’ed with the RidIntEn bit

of the Carkit Interrupt Status register.

Reserved 7 rd 0b Read only, 0.

FIELD NAME BIT ACCESS DEFAULT DESCRIPTION

Reserved 0 rd/w/s/c 0b Read only, 0.

SwapDP/DM 1 rd/w/s/c 0b When asserted, the DP and DM pins of the USB

transceiver are swapped. This bit can be used to

prevent crossing the DP/DM traces on the board. In

UART mode, it swaps the routing to the DP and DM

pins. In USB Audio Mode, it does not affect the

SPK_L and SPK_R pins.

UART RegOutput 3:2 rd/w/s/c 01b Controls the output voltage of the VBAT to VDD33

regulator in UART mode. When the transceiver is

switched from USB mode to UART mode regulator

output will automatically change to the value

specified in this register when TxdEn is asserted.

00: 3.3V

01: 3.0V (default)

10: 2.75V

11: 2.5V

Note: When in USB Audio Mode the regulator will

remain at 3.3V. When using this register it is