83026BMI-01 www.icst.com/products/hiperclocks.html REV. A JANUARY 16, 2006
1
Integrated
Circuit
Systems, Inc.
ICS83026I-01
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
GENERAL DESCRIPTION
The ICS83026I-01 is a low skew, 1-to-2 Dif-
ferential-to-LVCMOS/LVTTL Fanout Buffer and
a member of the HiPerClockS™ family of
High Performance Clock Solutions from
ICS. The differential input can accept most dif-
ferential signal types (LVPECL, LVDS, LVHSTL, HCSL and
SSTL) and translate to two single-ended LVCMOS/LVTTL out-
puts. The small 8-lead SOIC footprint makes this device ideal
for use in applications with limited board space.
FEATURES
•Two LVCMOS / LVTTL outputs
•Differential CLK, nCLK input pair
•CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
•Maximum output frequency: 350MHz
•Output skew: 15ps (maximum)
•Part-to-part skew: 600ps (maximum)
•Additive phase jitter, RMS: 0.03ps (typical)
•Small 8 lead SOIC package saves board space
•3.3V core, 3.3V, 2.5V or 1.8V output operating supply
•-40°C to 85°C ambient operating temperature
•Available in both standard and lead-free RoHS compliant
packages
BLOCK DIAGRAM PIN ASSIGNMENT
ICS83026I-01
8-Lead SOIC
3.8mm x 4.8mm, x 1.47mm package body
M Package
Top View
VDD
CLK
nCLK
OE
1
2
3
4
Q0
Q1
CLK
nCLK
OE
HiPerClockS™
ICS
VDDO
Q0
Q1
GND
8
7
6
5
ICS83026I-01
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
G Package
Top View
VDD
CLK
nCLK
OE
1
2
3
4
VDDO
Q0
Q1
GND
8
7
6
5
83026BMI-01 www.icst.com/products/hiperclocks.html REV. A JANUARY 16, 2006
2
Integrated
Circuit
Systems, Inc.
ICS83026I-01
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
rebmuNemaNepyTnoitpircseD
1V
DD
rewoP.nipylppusevitisoP
2KLCtupnInwodlluP.tupnikcolclaitnereffidgnitrevni-noN
3KLCntupnI /pulluP
nwodlluP V.tupni
kcolclaitnereffidgnitrevnI
DD
.gnitaolftfelnehwtluafed2/
4EOtupnIpulluP nierastuptuo,WOLnehW.delbaneerastuptuo,HGIHnehW.elbanetuptuO
.sle
velecafretniLTTVL/SOMCVL.etatSecnadepmIhgiH
5DNGrewoP.dnuorgylppusrewoP
61QtuptuO.slevelecafretniLTTVL/SOMCVL
.tuptuokcolC
70QtuptuO.slevelecafretniLTTVL/SOMCVL.tuptuokcolC
8V
ODD
rewoP.nipylppustuptuO
:ETON pulluP dna nwodlluP .seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertup
nilanretniotrefer
tupnIstuptuO
EO1Q,0Q
0ZiH
1evitcA
TABLE 3. CONTROL FUNCTION TABLE
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
C
NI
ecnaticapaCtupnI 4Fp
C
DP
ecnaticapaCnoitapissiDrewoP
)tuptuorep(
V
DD
V,
ODD
V564.3=71Fp
V
DD
V,V564.3=
ODD
V526.2=61Fp
V
DD
V,V564.3=
ODD
V59.1=51Fp
R
PULLUP
rotsiseRpulluPtupnI 15kΩ
R
NWODLLUP
rotsiseRnwodlluPtupnI 15kΩ
R
TUO
ecnadepmItuptuO
V
DD
V,
ODD
V3.3=7
Ω
V
DD
V,V3.3=
ODD
V5.2=8
Ω
V
DD
V,V3.3=
ODD
V8.1=01Ω
83026BMI-01 www.icst.com/products/hiperclocks.html REV. A JANUARY 16, 2006
3
Integrated
Circuit
Systems, Inc.
ICS83026I-01
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 1.71V TO 3.465V, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
DD
egatloVylppuSevitisoP 531.33.3564.3V
V
ODD
egatloVylppuStuptuO
531.33.3564.3V
573.25.2526.2V
17.18.198.1V
I
DD
tnerruCylppuSrewoP 01Am
I
ODD
tnerruCylppuStuptuO 3Am
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 2.375V TO 3.465V, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HI
egatloVhgiHtupnIEO2V
DD
3.0+V
V
LI
egatloVwoLtupnIEO3.0-8.0V
I
HI
tnerruChgiHtupnIEOV
DD
V=
NI
V564.3=5Aµ
I
LI
tnerruCwoLtupnIEOV
DD
V,V564.3=
NI
V0=051-Aµ
V
HO
;egatloVhgiHtuptuO1ETON V
ODD
V531.3=6.2V
V
ODD
V573.2=8.1V
V
LO
;egatloVwoLtuptuO1ETON 5.0V
05htiwdetanimretstuptuO:1ETON ΩVot
ODD
,noitcesnoitamrofnItnemerusaeMretemaraPeeS.2/
.smargaid"tiucriCtseTdaoLtuptuO"
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
DD 4.6V
Inputs, VI-0.5V to VDD + 0.5 V
Outputs, VO-0.5V to VDDO + 0.5V
Package Thermal Impedance, θ
JA
8 Lead SOIC 112.7°C/W (0 lfpm)
8 Lead TSSOP 101.7°C/W (0 lfpm)
Storage Temperature, T
STG -65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 3C. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 1.8V ± 5%, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HI
egatloVhgiHtupnIEO2V
DD
3.0+V
V
LI
egatloVwoLtupnIEO3.0-8.0V
I
HI
tnerruChgiHtupnIEOV
DD
V=
NI
V564.3=5Aµ
I
LI
tnerruCwoLtupnIEOV
DD
V,V564.3=
NI
V0=051-Aµ
V
HO
egatloVhgiHtuptuO I
HO
Aµ001-=V
ODD
2.0-V
I
HO
Am2-=V
ODD
54.0-V
V
LO
egatloVwoLtuptuO I
LO
Aµ001=2.0V
I
LO
Am2=54.0V
83026BMI-01 www.icst.com/products/hiperclocks.html REV. A JANUARY 16, 2006
4
Integrated
Circuit
Systems, Inc.
ICS83026I-01
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 4A. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 3.3V ± 5%, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
XAM
ycneuqerFtuptuO 053zHM
t
DP
1ETON;yaleDnoitagaporPIJzHM0533.19.15.2sn
t)o(ks4,2ETON;wekStuptuO 51sp
t)pp(ks4,3ETON;wekStraP-ot-traP 009sp
ttij o
trefer,SMR,rettiJesahPevitiddAreffuB
noitceSrettiJesahPevitiddA 30.0sp
t
R
t/
F
emiTllaF/esiRtuptuO%08ot%02051008sp
cdoelcyCytuDtuptuO
IJzHM668425%
zHM76 ≤ƒ≤zHM6615455%
zHM761 ≤ƒ≤zHM0530406%
Vottniopgni
ssorctupnilaitnereffidehtmorfderusaeM:1ETON
ODD
.tuptuoehtfo2/
.snoitidnocdaollauqehtiwdnaegatlovylppusemasehttastuptuoneewtebwekssadenifeD:2ETON
Vtade
rusaeM
ODD
.2/
htiwdnasegatlovylppusemasehttagnitareposecivedtnereffidnostuptuoneewtebwekssadenifeD:3ETON
Vtaderusaemerastuptuoeht,ecivedhcaenostupnifoepytemasehtgnisU.snoitidnocdaollauqe
ODD
.2/
.6dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT:4ETON
TABLE 3D. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 1.71V TO 3.465V, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
I
HI
tnerruChgiHtupnI KLCnV
NI
V=
DD
V564.3=051Aµ
KLCV
NI
V=
DD
V564.3=051Aµ
I
LI
tnerruCwoLtupnI KLCnV
NI
V,V0=
DD
V564.3=051-Aµ
KLCV
NI
V,V0=
DD
V564.3=5-Aµ
V
PP
1ETON;egatloVtupnIkaeP-ot-kaeP 51.03.1V
V
RMC
3,2ETON;egatloVtupnIedoMnommoC 5.0+DNGV
DD
58.0-V
V:1ETON
PP
VpeekotleveltesffotneiciffussierehttahtdedivorpV3.1deecxenac
LI
.V0>
snoitacilppadedneelgnisroF:2ETON ,VsiKLCn,KLCrofegatlovtupnimumixameht
DD
.V3.0+
siegatlovedomnommoC:3ETONVsadenifed
HI
.
83026BMI-01 www.icst.com/products/hiperclocks.html REV. A JANUARY 16, 2006
5
Integrated
Circuit
Systems, Inc.
ICS83026I-01
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 4B. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40°C TO 85°C
TABLE 4C. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 1.8V ± 5%, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
XAM
ycneuqerFtuptuO 053zHM
t
DP
1ETON;yaleDnoitagaporPIJzHM0535.10.26.2sn
t)o(ks4,2ETON;wekStuptuO 51sp
t)pp(ks4,3ETON;wekStraP-ot-traP 057sp
ttij
,
rettiJesahPevitiddAreffuB
esahPevitiddAotrefer,SMR
noitceSrettiJ
30.0sp
t
R
t/
F
emiTllaF/esiRtuptuO%08ot%02051008sp
cdoelcyCytuDtuptuO
IJzHM668425%
zHM76 ≤ƒ≤zHM6616445%
zHM761 ≤ƒ≤zHM0530406%
Vottniopgni
ssorctupnilaitnereffidehtmorfderusaeM:1ETON
ODD
.tuptuoehtfo2/
.snoitidnocdaollauqehtiwdnaegatlovylppusemasehttastuptuoneewtebwekssadenifeD:2ETON
Vtade
rusaeM
ODD
.2/
htiwdnasegatlovylppusemasehttagnitareposecivedtnereffidnostuptuoneewtebwekssadenifeD:3ETON
Vtaderus
aemerastuptuoeht,ecivedhcaenostupnifoepytemasehtgnisU.snoitidnocdaollauqe
ODD
.2/
.56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT:4ETON
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
XAM
ycneuqerFtuptuO 053zHM
t
DP
1ETON;yaleDnoitagaporPIJzHM0539.15.21.3sn
t)o(ks4,2ETON;wekStuptuO 51sp
t)pp(ks4,3ETON;wekStraP-ot-traP 006sp
ttij
,
rettiJesahPevitiddAreffuB
esahPevitiddAotrefer,SMR
noitceSrettiJ
30.0sp
t
R
t/
F
emiTllaF/esiRtuptuO%08ot%02002009sp
cdoelcyCytuDtuptuO
IJzHM668425%
zHM76 ≤ƒ≤zHM6613475%
zHM761 ≤ƒ≤zHM0530406%
Vottniopgni
ssorctupnilaitnereffidehtmorfderusaeM:1ETON
ODD
.tuptuoehtfo2/
.snoitidnocdaollauqehtiwdnaegatlovylppusemasehttastuptuoneewtebwekssadenifeD:2ETON
Vtade
rusaeM
ODD
.2/
htiwdnasegatlovylppusemasehttagnitareposecivedtnereffidnostuptuoneewtebwekssadenifeD:3ETON
Vtaderus
aemerastuptuoeht,ecivedhcaenostupnifoepytemasehtgnisU.snoitidnocdaollauqe
ODD
.2/
.56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT:4ETON
83026BMI-01 www.icst.com/products/hiperclocks.html REV. A JANUARY 16, 2006
6
Integrated
Circuit
Systems, Inc.
ICS83026I-01
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
ADDITIVE PHASE JITTER
Input/Output Additive
Phase Jitter at 155.52MHz
= 0.03ps typical
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k 10k 100k 1M 10M 100M
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise . This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
OFFSET FROM CARRIER FREQUENCY (HZ)
SSB PHASE NOISE dBc/HZ
83026BMI-01 www.icst.com/products/hiperclocks.html REV. A JANUARY 16, 2006
7
Integrated
Circuit
Systems, Inc.
ICS83026I-01
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
SCOPE
Qx
LVCMOS
3.3VCORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
2.4±0.125V
VDDO
-0.9V±0.45V
VDD
0.9V±0.45V
SCOPE
Qx
LVCMOS
3.3VCORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
2.05V±0.103V
VDDO
-1.25V±5%
VDD
1.25V±5%
3.3VCORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
SCOPE
Qx
LVCMOS
1.65V±5%
-1.65V±5%
DIFFERENTIAL INPUT LEVEL
OUTPUT SKEW PART-TO-PART SKEW
V
CMR
Cross Points
V
PP
GND
CLK
nCLK
VDD
tsk(o)
V
DDO
2
V
DDO
2
Qy
Qx
tsk(pp)
V
DDO
2
V
DDO
2
Qy
Qx
PART 1
PART 2
VDD,
VDDO
GND
GND
GND
83026BMI-01 www.icst.com/products/hiperclocks.html REV. A JANUARY 16, 2006
8
Integrated
Circuit
Systems, Inc.
ICS83026I-01
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
PROPAGATION DELAY
Q0, Q1
OUTPUT RISE/FALL TIME
Clock
Outputs
20%
80% 80%
20%
t
R
t
F
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
t
PD
V
DDO
2
CLK
nCLK
tPERIOD
tPW
tPERIOD
odc =
V
DDO
2
x 100%
tPW
Q0, Q1
83026BMI-01 www.icst.com/products/hiperclocks.html REV. A JANUARY 16, 2006
9
Integrated
Circuit
Systems, Inc.
ICS83026I-01
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
APPLICATION INFORMATION
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
V_REF
R1
1K
C1
0.1u
R2
1K
Single Ended Clock Input
CLK
nCLK
VDD
OUTPUTS:
LVCMOS OUTPUT:
All unused LVCMOS output can be left floating. We recommend
that there is no trace attached.
RECOMMENDATIONS FOR UNUSED OUTPUT PINS
83026BMI-01 www.icst.com/products/hiperclocks.html REV. A JANUARY 16, 2006
10
Integrated
Circuit
Systems, Inc.
ICS83026I-01
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
FIGURE 2C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 2B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 2D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 2A to 2E show inter-
face examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
FIGURE 2A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in Figure 2A, the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
FIGURE 2E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
Zo = 50 Ohm
R3
125
HiPerClockS
CLK
nCLK
3.3V
R5
100 - 200
3.3V
R2
84
3.3V
R6
100 - 200
Input
R5,R6 locate near the driver pin.
Zo = 50 Ohm
R1
84
R4
125
C2
LVPECL C1
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
83026BMI-01 www.icst.com/products/hiperclocks.html REV. A JANUARY 16, 2006
11
Integrated
Circuit
Systems, Inc.
ICS83026I-01
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
SCHEMATIC EXAMPLE
Figure 3 shows an application schematic example of ICS83026I-
01. The ICS83026I-01 CLK/nCLK input can directly accepts
various types of differential signal. In this example, the input is
driven by an LVDS driver. The ICS83026I-01 outputs are
VDDO R1 43
LVDS
VDD
R4
100
VD D =3 .3 V
LVCMOS
Zo = 50 Ohm
R3
1K
C2
0.1u
3.3V
Zo = 50 Ohm
VDDO= 3.3V, 2.5V or 1.8V
Zo = 50 Ohm
U1 ICS83026I-01
1
2
3
4
8
7
6
5
VDD
CLK
nCLK
OE
VDDO
Q0
Q1
GND
LVCMOS
R2 43
C1
0.1u
VDD
Zo = 50 Ohm
FIGURE 3. ICS83026I-01 SCHEMATIC EXAMPLE
LVCMOS drivers. In this example, series termination approach
is shown. Additional termination approaches are shown in the
LVCMOS Termination Application Note.
TRANSISTOR COUNT
The transistor count for ICS83026I-0I is: 260
TABLE 5A. θJAVS. AIR FLOW TABLE FOR 8 LEAD SOIC
θθ
θθ
θJA by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 153.3°C/W 128.5°C/W 115.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 112.7°C/W 103.3°C/W 97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
RELIABILITY INFORMATION
TABLE5B. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP
θθ
θθ
θJA by Velocity (Linear Feet per Minute)
0 200 500
Multi-Layer PCB, JEDEC Standard Test Boards 101.7°C/W 90.5°C/W 89.8°C/W
83026BMI-01 www.icst.com/products/hiperclocks.html REV. A JANUARY 16, 2006
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Circuit
Systems, Inc.
ICS83026I-01
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 6A. PACKAGE DIMENSIONS
Reference Document: JEDEC Publication 95, MS-012
PACKAGE OUTLINE - SUFFIX M FOR 8 LEAD SOIC
LOBMYS sretemilliM
MUMINIMMUMIXAM
N8
A53.157.1
1A01.052.0
B33.015.0
C91.052.0
D08.400.5
E08.300.4
eCISAB72.1
H08.502.6
h52.005.0
L04.07
2.1
α°0°8
PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP
TABLE 6B. PACKAGE DIMENSIONS
Reference Document: JEDEC Publication 95, MO-153
LOBMYS sretemilliM
muminiMmumixaM
N8
A--02.1
1A50.051.0
2A08.050.1
b91.003.0
c90.002.0
D09.201.3
ECISAB04.6
1E03.405.4
eCISAB56.0
L54
.057.0
α°0°8
aaa--01.0
83026BMI-01 www.icst.com/products/hiperclocks.html REV. A JANUARY 16, 2006
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Integrated
Circuit
Systems, Inc.
ICS83026I-01
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 7. ORDERING INFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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83026BMI-01 www.icst.com/products/hiperclocks.html REV. A JANUARY 16, 2006
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Integrated
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Systems, Inc.
ICS83026I-01
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
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