LP62S16512-T Series
512K X 16 BIT LOW VOLTAGE CMOS SRAM
(August, 2004, Version 1.3) AMIC Technology, Corp.
Document Title
512K X 16 BIT LOW VOLTAGE CMOS SRAM
Revision History
Rev. No. History Issue Date Remark
0.2 Add Product Family and 55ns specification March 20, 2002 Preliminary
1.0 Change ICC2 from 15mA to 8mA May 26, 2003 Final
Final version release
1.1 Modify 48LD CSP outline dimensions November 19, 2003
1.2 Error Correction: July 23, 2004
P1: Modify operating temperature from “-40°C ~ +85°C” to
“-25°C ~ +85°C”
1.3 Add Pb-Free package type August 19, 2004
LP62S16512-T Series
512K X 16 BIT LOW VOLTAGE CMOS SRAM
(August, 2004, Version 1.3) 1 AMIC Technology, Corp.
Features
Operating voltage: 2.7V to 3.6V
Access times: 55/70 ns (max.)
Current:
Very low power version: Operating: 50mA (max.)
Standby: 20µA (max.)
Full static operation, no clock or refreshing required
All inputs and outputs are directly TTL-compatible
Common I/O using three-state output
Data retention voltage: 2.0V (min.)
Available in 48-ball CSP (8×10mm) packages
General Description
The LP62S16512-T is a low operating current 8,388,608-bit
static random access memory organized as 524,288 words
by 16 bits and operates on low power voltage from 2.7V to
3.6V. It is built using AMIC's high performance CMOS
process.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
Two chip enable input is provided for POWER-DOWN,
device enable. Two byte enable inputs and an output
enable input are included for easy interfacing.
Data retention is guaranteed at a power supply voltage as
low as 2.0V.
Product Family
Power Dissipation
Product
Family Operating
Temperature VCC
Range Speed Data Retention
(ICCDR, Typ.) Standby
(ISB1, Typ.) Operating
(ICC2, Typ.)
Package
Type
LP62S16512 -25°C ~ +85°C2.7V~3.6V 55ns / 70ns 0.3µA 0.5µA 4mA 48 CSP
1. Typical values are measured at VCC = 3.0V, TA = 25°C and not 100% tested.
2. Data retention current VCC = 2.0V.
Pin Configurations
CSP (Chip Size Package)
48-pin Top View
I/O
9
I/O
10
GND
VCC
I/O
15
I/O
16
A18 A8
NC
A9
A12
A10 A11 NC
A13
A14 A15
I/O
8
I/O
7
I/O
3
I/O
1
GND
VCC
A0
A3
A5 A6
A4
A1 A2 CS
2
654321
A
B
C
D
E
F
G
H
I/O
14
I/O
13
I/O
12
I/O
11
A17
NC
A7
A16
I/O
2
I/O
4
I/O
5
I/O
6
LB
HB
WE
OE
CS
1
LP62S16512-T Series
(August, 2004, Version 1.3) 2 AMIC Technology, Corp.
Block Diagram
DECODER 1024 X 8192
MEMORY ARRAY
COLUMN I/O
INPUT
DATA
CIRCUIT
CONTROL
CIRCUIT
VCC
GND
I/O
8
I/O
1
A18
A17
A0
INPUT
DATA
CIRCUIT
I/O
9
I/O
16
LB
WE
OE
HB
LB
CS
2
CS
1
LP62S16512-T Series
(August, 2004, Version 1.3) 3 AMIC Technology, Corp.
Pin Description - CSP
Symbol Description Symbol Description
A0 - A18 Address Inputs HB Higher Byte Enable Input
(I/O9 - I/O16)
1CS , CS2 Chip Enable OE Output Enable
I/O1 - I/O16 Data Input/Output VCC Power Supply
WE Write Enable Input GND Ground
LB Byte Enable Input
(I/O1 - I/O8) NC No Connection
Recommended DC Operating Conditions
(TA = -25°C to + 85°C)
Symbol Parameter Min. Typ. Max. Unit
VCC Supply Voltage 2.7 3 3.6 V
GND Ground 0 0 0 V
VIH Input High Voltage 2.0 - VCC + 0.3 V
VIL Input Low Voltage -0.3 - +0.6 V
CL Output Load - - 30 pF
TTL Output Load - - 1 -
LP62S16512-T Series
(August, 2004, Version 1.3) 4 AMIC Technology, Corp.
Absolute Maximum Ratings*
VCC to GND..............................................-0.5V to +4.0V
IN, IN/OUT Volt to GND................... -0.5V to VCC + 0.5V
Operating Temperature, Topr...................-25°C to +85°C
Storage Temperature, Tstg.....................-55°C to +125°C
Power Dissipation, PT.......................................................................0.7W
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may affect
device reliability.
DC Electrical Characteristics (TA = -25°C to + 85°C, VCC = 2.7V to 3.6V, GND = 0V)
Symbol Parameter LP62S16512-55/70LLT Unit Conditions
Min. Max.
⏐ILI⏐ Input Leakage Current - 1 µA VIN = GND to VCC
⏐ILO⏐
Output Leakage Current
-
1
µA
1CS = VIH or CS2 = VIL or
LB = HB = VIH
VI/O = GND to VCC
ICC Active Power Supply
Current - 5 mA 1CS = VIL , CS2 = VIH ,
LB = VIL or HB = VIL , II/O = 0mA
ICC1
Dynamic Operating
- 50 mA Min. Cycle, Duty = 100%, 1CS = VIL ,
CS2 = VIH , LB = VIL or HB = VIL
II/O = 0mA
ICC2
Current
- 8 mA
1CS ≤ 0.2V, CS2 ≥ VCC-0.2V ,
LB ≤ 0.2V or HB ≤ 0.2V
f = 1MHz , II/O = 0mA
ISB - 1 mA 1CS = VIH or CS2 = VIL or
LB = HB = VIH
ISB1
Standby Current
- 20
µA1CS ≥ VCC - 0.2V or CS2 ≤ 0.2V or
LB = HB ≥ VCC-0.2V
VIN ≥ VCC-0.2V or VIN ≤ 0.2V
VOL Output Low Voltage - 0.4 V IOL = 2.1 mA
VOH Output High Voltage 2.2 - V IOH = -1.0 mA
LP62S16512-T Series
(August, 2004, Version 1.3) 5 AMIC Technology, Corp.
Truth Table
1CS CS2 OE WE LB HB I/O1 to I/O8 Mode I/O9 to I/O16 Mode VCC Current
H X X X X X High - Z High - Z ISB1, ISB
X L X X X X High - Z High - Z ISB1, ISB
X X X X H H High - Z High - Z ISB1, ISB
L L Read Read ICC1, ICC2, ICC
L H L H L H Read High - Z ICC1, ICC2, ICC
H L High - Z Read ICC1, ICC2, ICC
L L Write Write ICC1, ICC2, ICC
L H X L L H Write High - Z ICC1, ICC2, ICC
H L High - Z Write ICC1, ICC2, ICC
L H H H L X High - Z High - Z ICC1, ICC2, ICC
L H H H X L High - Z High - Z ICC1, ICC2, ICC
Note: X = H or L
Capacitance (TA = 25°C, f = 1.0MHz)
Symbol Parameter Min. Max. Unit Conditions
CIN* Input Capacitance 6 pF VIN = 0V
CI/O* Input/Output Capacitance 8 pF VI/O = 0V
* These parameters are sampled and not 100% test ed.
LP62S16512-T Series
(August, 2004, Version 1.3) 6 AMIC Technology, Corp.
AC Characteristics (TA = -25°C to +85°C, VCC = 2.7V to 3.6V)
Symbol Parameter LP62S16512-55LLT LP62S16512-70LLT Unit
Min. Max. Min. Max.
Read Cycle
tRC Read Cycle Time 55 - 70 - ns
tAA Address Access Time - 55 - 70 ns
tAcs1 , tAcs2 Chip Enable Access Time - 55 - 70 ns
tBE Byte Enable Access Time - 55 - 70 ns
tOE Output Enable to Output Valid - 25 - 35 ns
tCLZ1 , tCLZ2 Chip Enable to Output in Low Z 10 - 10 - ns
tBLZ Byte Enable to Output in Low Z 10 - 10 - ns
tOLZ Output Enable to Out put in Low Z 5 - 5 - ns
tCHZ1 , tCHZ2 Chip Disable to Output in High Z - 20 - 25 ns
tBHZ Byte Disable to Output in High Z - 20 - 25 ns
tOHZ Output Disable to Output in High Z - 20 - 25 ns
tOH Output Hold from Address Change 5 - 5 - ns
Write Cycle
tWC Write Cycle Time 55 - 70 - ns
tCW1 , tCW2 Chip Enable to End of Write 50 - 60 - ns
tBW Byte Enable to End of Write 50 - 60 - ns
tAS Address Setup Time 0 - 0 - ns
tAW Address Valid to End of Write 50 - 60 - ns
tWP Write Pulse Width 40 - 50 - ns
tWR Write Recovery Time 0 - 0 - ns
tWHZ Write to Output in High Z - 25 - 25 ns
tDW Data to Write Time Overlap 25 - 30 - ns
tDH Data Hold from Write Time 0 - 0 - ns
tOW Output Active from End of Write 5 - 5 - ns
Note: tCLZ1 , tCLZ2 , tBLZ , tOLZ , tCHZ1, tCHZ2 , tBHZ and tOHZ and tWHZ are defined as the time at which the outputs achieve the open
circuit condition and are not referred to output voltage levels.
LP62S16512-T Series
(August, 2004, Version 1.3) 7 AMIC Technology, Corp.
Timing Waveforms
Read Cycle 1(1, 2, 4)
t
RC
t
OH
t
AA
t
OH
Address
D
OUT
Read Cycle 2(1, 2, 3)
t
RC
t
AA
Address
CS1
t
ACS1 ,
t
ACS2
t
CHZ1
,
t
CHZ2
HB, LB
t
BHZ
5
OE
t
BE
t
BLZ
5
t
OE
t
OLZ
5
t
OHZ
5
D
OUT
t
CLZ1 ,
t
CLZ2
CS2
Notes: 1.
WE is high for Read Cycle.
2. Device is continuously enabled 1CS = VIL, or CS2 = VIH ,HB = VIL and, or LB = VIL.
3. Address valid prior to or coincident with 1CS and (HB and, or LB ) transition low or CS2 transition High.
4.
OE = VIL.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
LP62S16512-T Series
(August, 2004, Version 1.3) 8 AMIC Technology, Corp.
Timing Waveforms (continued)
Write Cycle 1
(Write Enable Controlled)
tWC
tAW
Address
CS1
tWR3
tCW
DATA IN
DATA OUT
WE
HB, LB
tBW
tAS1tWP2
tDW tDH
tOW
tWHZ4
CS2
Write Cycle 2
(Chip Enable Controlled)
tWC
tAW
Address
CS1
tWR3
tCW1 , tCW2
tAS1
DATA IN
DATA OUT
WE
HB, LB
tBW
tWP
tDW tDH
tOW
tWHZ4
CS2
LP62S16512-T Series
(August, 2004, Version 1.3) 9 AMIC Technology, Corp.
Timing Waveforms (continued)
Write Cycle 3
(Byte Enable Controlled)
t
WC
t
AW
Address
CS
1
t
WR
3
t
CW1 ,
t
CW2
t
BW
2
t
AS
1
DATA IN
DATA OUT
WE
HB, LB
t
WP
t
DW
t
DH
t
OW
t
WHZ
4
CS
2
Notes: 1. tAS is measured from the address valid t o the beginning of Write.
2. A W r ite occurs during the overlap (tWP, tBW) of a low 1CS , WE and (HB and , or LB ) or a high CS2.
3. tWR is measured from the earliest of 1CS or WE or (HB and , or LB ) going high or CS2 going Low to the end of the
Write cycle.
4.
OE level is high or low.
5. Transition is measured ±500mV from steady state. T his parameter is sampled and not 100% tested.
LP62S16512-T Series
(August, 2004, Version 1.3) 10 AMIC Technology, Corp.
AC Test Conditions
Input Pulse Levels 0.4V to 2.4V
Input Rise And Fall Time 5 ns
Input and Output Timing Reference Levels 1.5V
Output Load See Figures 1 and 2
30pF
* Including scope and jig. * Including scope and jig.
C
L
TTL
5pF
C
L
TTL
Figure 1. Output Load Figure 2. Output Load for tCLZ1, tCLZ2 , tBHZ , tBLZ ,
tOLZ, tCHZ1, tCHZ2 , tOHZ, tWHZ, and tOW
Data Retention Characteristics (TA = -25°C to 85°C)
Symbol Parameter Min. Max. Unit Conditions
VDR VCC for Dat a Retention 2.0 3.6 V 1CS ≥ VCC - 0.2V or
CS2 ≤ 0.2V or
LB = HB ≥ VCC-0.2V
ICCDR Data Retention Current - 6* µA
VCC = 2.0V,
1CS ≥ VCC - 0.2V or
CS2 ≤ 0.2V or
LB = HB ≥ VCC-0.2V
VIN ≥ VCC-0.2V or VIN ≤ 0.2V
tCDR Chip Disable to Data Retention Time 0 - ns
tR Operation Recovery Time tRC - ns
See Retention Waveform
tVR VCC Rising Time from Data Retention
Voltage to Operating Voltage 5 - ms
* LP62S16512-55/70LLT ICCDR: max. 1µA at TA = 25°C
(3µA at TA = 0°C to + 40°C )
LP62S16512-T Series
(August, 2004, Version 1.3) 11 AMIC Technology, Corp.
Low VCC Data Retention Waveform (1) (CS1 Controlled)
VCC
CS1
t
CDR
V
IH
2.7V
t
R
V
IH
2.7V
DATA RETENTION MODE
t
VR
V
DR
≥
2.0V
CS1
≥
V
DR
- 0.2V
Low VCC Data Retention Waveform (2) (CS2 Controlled)
VCC
CS2
t
CDR
V
IL
2.7V
t
R
V
IL
2.7V
DATA RETENTION MODE
t
VR
V
DR
≥
2.0V
0.2VCS2≤
Ordering Information
Part No. Access Time (ns) Operating Current
Max. (mA) Standby Current
Max. (uA) Package
LP62S16512U-55LLT 50 20 48L CSP
LP62S16512U-55LLTF 55 50 20 48L Pb-Free CSP
LP62S16512U-70LLT 50 20 48L CSP
LP62S16512U-70LLTF 70 50 20 48L Pb-Free CSP
LP62S16512-T Series
(August, 2004, Version 1.3) 12 AMIC Technology, Corp.
Package Information
48LD CSP ( 8 x 10 mm ) Outline Dimensions unit: mm
(48TFBGA)
Dimensions in mm
Symbol MIN. NOM. MAX.
A 1.00 1.10 1.20
A1 0.20 0.25 0.30
A2 0.48 0.53 0.58
D 7.90 8.00 8.10
E 9.90 10.00 10.10
D1 --- 3.75 ---
E1 --- 5.25 ---
e --- 0.75 ---
b 0.30 0.35 0.40
Notes:
1. THE BALL DIAMETER, BALL PITCH, STAND-OFF & PACKAGE THICKNESS
ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY).
2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS
OF THE SOLDER BALLS.
3. DIMENSION b IS MEASURED AT THE MAXIMUM.
4. THERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF THE
SOLDER BALL AND THE BODY EDGE.
5. BALL PAD OPENING OF SUBST RATE IS Φ 0.3mm (SMD)
SUGGEST TO DESIGN THE PCB LAND SIZE AS Φ 0.3mm (NSMD)
A
1
A
2
A
B
C
D
E
F
G
H
TOP VIEW
Ball#A1 CORNER
SIDE VIEW
C SEATING PLANE
// 0.25 C
A
(0.36)
123456 123456
b (48X)
BOTTOM VIEW
Ball #A1 CORNER
E
E
1
e
D
1
0.10 C
C
0.10 C
S
0.25
S
A B
e
D
A
0.20(4X)
B
A
B
C
D
E
F
G
H
