204pin DDR3 SDRAM SODIMMs DDR3 SDRAM Unbuffered SODIMMs Based on 1Gb A version HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C ** Contents are subject to change without prior notice. Rev. 0.2 / Dec. 2008 1 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C Revision History Revision No. History Draft Date Remark 0.01 Initial draft Sep. 2007 preliminary 0.02 Added IDD, corrected typos Mar. 2008 preliminary 0.03 Halogen-free added May. 2008 preliminary 0.1 Initial Specification Release May 2008 0.2 Added outline: DIMMs with thermal sensor. Corrected typo on package ball feature. Dec. 2008 Rev. 0.2 / Dec. 2008 2 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C Table of Contents 1. Description 1.1 Device Features and Ordering Information 1.1.1 Features 1.1.2 Ordering Information 1.2 Speed Grade & Key Parameters 1.3 Address Table 2. Pin Architecture 2.1 Pin Definition 2.2 Input/Output Functional Description 2.3 Pin Assignment 3. Functional Block Diagram 3.1 512MB, 64Mx64 Module(1Rank of x16) 3.2 1GB, 128Mx64 Module(2Rank of x16) 3.3 2GB, 256Mx64 Module(2Rank of x8) 4. Absolute Maximum Ratings 4.1 Absolute Maximum DC Ratings 4.2 Operating Temperature Range 5. AC & DC Operating Conditions 5.1 Recommended DC Operating Conditions 5.2 DC & AC Logic Input Levels 5.2.1 For Single-ended Signals 5.2.2 For Differential Signals 5.2.3 Differential Input Cross Point 5.3 Slew Rate Definition 5.3.1 For Ended Input Signals 5.3.2 For Differential Input Signals 5.4 DC & AC Output Buffer Levels 5.4.1 Single Ended DC & AC Output Levels 5.4.2 Differential DC & AC Output Levels 5.4.3 Single Ended Output Slew Rate 5.4.4 Differential Ended Output Slew Rate 5.5 Overshoot/Undershoot Specification 5.5.1 Address and Control Overshoot and Undershoot Specifications 5.5.2 Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications 5.6 Input/Output Capacitance & AC Parametrics 5.7 IDD Specifications & Measurement Conditions 6. Electrical Characteristics and AC Timing 6.1 Refresh Parameters by Device Density 6.2 DDR3 Standard speed bins and AC para 7. DIMM Outline Diagram 7.1 512MB, 64Mx64 Module(1Rank of x16) 7.2 1GB, 128Mx64 Module(2Rank of x16) 7.3 2GB, 256Mx64 Module(2Rank of x8) Rev. 0.2 / Dec. 2008 3 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C 1. Description This Hynix unbuffered Small Outline Dual In-Line Memory Module (SODIMM) series consists of 1Gb A version. DDR3 SDRAMs in Fine Ball Grid Array (FBGA) packages on a 204 pin glass-epoxy substrate. This DDR3 Unbuffered SODIMM series based on 1Gb A version provide a high performance 8 byte interface in 67.60mm width form factor of industry standard. It is suitable for easy interchange and addition. 1.1 Device Features & Ordering Information 1.1.1 Features * VDD=VDDQ=1.5V * 8 banks * VDDSPD=3.0V to 3.6V * 8K refresh cycles /64ms * Fully differential clock inputs (CK, /CK) operation * Differential Data Strobe (DQS, /DQS) * DDR3 SDRAM Package: JEDEC standard 78ball FBGA(x4/x8), 96ball FBGA(x16) * On chip DLL align DQ, DQS and /DQS transition with CK transition * Driver strength selected by EMRS * Dynamic On Die Termination supported * DM masks write data-in at the both rising and falling edges of the data strobe * Asynchronous RESET pin supported * All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock * TDQS (Termination Data Strobe) supported (x8 only) * Programmable CAS latency 5, 6, 7, 8, 9, 10, and (11) supported * ZQ calibration supported * Write Levelization supported * Auto Self Refresh supported * 8 bit pre-fetch * Programmable additive latency 0, CL-1 and CL-2 supported * Programmable CAS Write latency (CWL) = 5, 6, 7, 8 * Programmable burst length 4/8 with both nibble sequential and interleave mode * BL switch on the fly Rev. 0.2 / Dec. 2008 4 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C 1.1.2 Ordering Information Density Organization # of DRAMs # of ranks Materials HMT164S6AFP6C-S6/S5/G8/G7/H9/H8 512MB 64Mx64 4 1 Lead free HMT164S6AFR6C-S6/S5/G8/G7/H9/H8 512MB 64Mx64 4 1 Halogen free HMT112S6AFP6C-S6/S5/G8/G7/H9/H8 1GB 128Mx64 8 2 Lead free HMT112S6AFR6C-S6/S5/G8/G7/H9/H8 1GB 128Mx64 8 2 Halogen free HMT125S6AFP8C-S6/S5/G8/G7/H9/H8 2GB 256Mx64 16 2 Lead free HMT125S6AFR8C-S6/S5/G8/G7/H9/H8 2GB 256Mx64 16 2 Halogen free Part Name Two types, with integrated thermal sensor and with no thermal sensor, exist in each configuration. Rev. 0.2 / Dec. 2008 5 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C 1.2 Speed Grade & Key Parameters MT/S DDR3-800 DDR3-1066 DDR3-1333 Unit Grade -S6 tCK (min) -S5 -G8 2.5 -G7 -H9 1.875 -H8 1.5 ns CAS Latency 6 5 8 7 9 8 tCK tRCD (min) 15 12.5 15 13.125 13.5 12 ns tRP (min) 15 12.5 15 13.125 13.5 12 ns tRAS (min) 37.5 37.5 37.5 37.5 36 36 ns tRC (min) 52.5 50 52.5 50.625 49.5 48 ns CL-tRCD-tRP 6-6-6 5-5-5 8-8-8 7-7-7 9-9-9 8-8-8 tCK 1.3 Address Table 512MB 1GB 2GB Organization 64M x 64 128M x 64 256M x 64 Refresh Method 8K/64ms 8K/64ms 8K/64ms Row Address A0-A12 A0-A12 A0-A13 Column Address A0-A9 A0-A9 A0-A9 Bank Address BA0-BA2 BA0-BA2 BA0-BA2 Page Size 2KB 2KB 1KB # of Rank 1 2 2 # of Device 4 8 16 Rev. 0.2 / Dec. 2008 6 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C 2. Pin Architecture 2.1 Pin Definition Pin Name Description Pin Name Description CK[1:0] Clock Inputs, positive line 2 DQ[63:0] Data Input/Output 64 CK[1:0] Clock Inputs, negative line 2 DM[7:0] Data Masks 8 CKE[1:0] Clock Enables 2 DQS[7:0] Data strobes 8 RAS Row Address Strobe 1 DQS[7:0] Data strobes complement 8 CAS Column Address Strobe 1 RESET Reset pin 1 WE Write Enable 1 TEST Logic Analyzer specific test pin (No 1 connect on SODIMM) S[1:0] Chip Selects 2 EVENT Address Inputs 14 Address Input/Autoprecharge A[9:0], A11, A[15:13] A10/AP Temperature event pin 1 VDD Core and I/O power 18 1 VSS Ground 52 Input/Output Reference 2 SPD and Temp sensor power 1 A12/BC Address Input/Burst Stop 1 VREFDQ BA[2:0] SDRAM Bank Address 3 VREFCA On-die termination control 2 VDDSPD ODT[1:0] SCL Serial Presence Detect (SPD) Clock 1 input Vtt Termination voltage 2 SDA SPD Data Input/Output 1 NC Reserved for future use 2 SPD address 2 SA[1:0] Rev. 0.2 / Dec. 2008 Total 204 7 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C 2.2 Input/Output Functional Description Symbol Type Polarity Function The system clock inputs. All address and command lines are sampled on the cross CK0/CK0 CK1/CK1 Input Cross point point of the rising edge of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when CKE[1:0] Input Active High low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode. Enables the associated DDR3 SDRAM command decoder when low and disables the S[1:0] Input Active Low command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1. RAS, CAS, WE Input Active Low BA[2:0] Input - ODT[1:0] Input Active High When sampled at the cross point of the rising edge of CK and falling edge of CK, signals CAS, RAS, and WE define the operation to be executed by the SDRAM. Selects which DDR3 SDRAM internal bank of eight is activated. Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the DDR3 SDRAM mode register. During a Bank Activate command cycle, defines the row address when sampled at the cross point of the rising edge of CK and falling edge of CK. During a Read or Write command cycle, defines the column address when sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to the column address, A[9:0], A10/AP, A11, A12/BC, A[15:13] AP is used to invoke autoprecharge operation at the end of the burst read or write Input - cycle. If AP is high, autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0BAn inputs. If AP is low, then BA0-BAn are used to define which bank to precharge. A12(BC) is sampled during READ and WRITE commands to determine if burst chop (on-thefly) will be performed (HIGH, no burst chop; LOW, burst chopped) DQ[63:0] In/Out - DM[7:0] Input Active High Data Input/Output pins. The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. The data strobes, associated with one data byte, sourced with data transfers. In DQS[7:0], DQS[7:0] Write mode, the data strobe is sourced by the controller and is centered in the data In/Out Cross Point window. In Read mode, the data strobe is sourced by the DDR3 SDRAMs and is sent at the leading edge of the data window. DQS signals are complements, and timing is relative to the crosspoint of respective DQS and DQS. Rev. 0.2 / Dec. 2008 8 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C Symbol Type VDD,VDDSPD, VSS, Supply Power supplies for core, I/O, Serial Presence Detect, Temp sensor, and ground for the module. Supply Reference voltage for SSTL15 inputs. VREFDQ, VREFCA Polarity Function This is a bidirectional pin used to transfer data into or out of the SPD EEPROM and SDA In/Out SCL Input This signal is used to clock data into and out of the SPD EEPROM and Temp sensor. SA[1:0] Input Address pins used to select the Serial Presence Detect and Temp sensor base address. TEST In/Out EVENT Wire OR Out Active Low RESET In Active Low Temp sensor. A resistor must be connected from the SDA bus line to VDDSPD on the system planar to act as a pull up. Rev. 0.2 / Dec. 2008 The TEST pin is reserved for bus analysis tools and is not connected on normal memory modules (SO-DIMMs). The EVENT pin is reserved for use to flag critical module temperature. A resistor may be connected from EVENT bus line to VDDSPD on the system planar to act as a pullup. This signal resets the DDR3 SDRAM 9 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C 2.3 Pin Assignment Pin # Front Side Pin # Back Side Pin # Front Side Pin # Back Side Pin # Front Side Pin # Back Side Pin # Front Side Pin # Back Side 1 VREFDQ 2 VSS 53 DQ19 54 VSS 105 VDD 106 VDD 157 DQ42 158 DQ46 3 VSS 4 DQ4 55 VSS 56 DQ28 107 A10/AP 108 BA1 159 DQ43 160 DQ47 5 DQ0 6 DQ5 57 DQ24 58 DQ29 109 BA0 110 RAS 161 VSS 162 VSS 7 DQ1 8 VSS 59 DQ25 60 VSS 111 VDD 112 VDD 163 DQ48 164 DQ52 9 VSS 10 DQS0 61 VSS 62 DQS3 113 WE 114 S0 165 DQ49 166 DQ53 11 DM0 12 DQS0 63 DM3 64 DQS3 115 CAS 116 ODT0 167 VSS 168 VSS 13 VSS 14 VSS 65 VSS 66 VSS 117 VDD 118 VDD 169 DQS6 170 DM6 15 DQ2 16 DQ6 67 DQ26 68 DQ30 119 A132 120 ODT1 171 DQS6 172 VSS 17 DQ3 18 DQ7 69 DQ27 70 DQ31 121 S1 122 NC 173 VSS 174 DQ54 19 VSS 20 VSS 71 VSS 72 VSS 123 VDD 124 VDD 175 DQ50 176 DQ55 21 DQ8 22 DQ12 73 CKE0 74 CKE1 125 TEST 126 VREFCA 177 DQ51 178 VSS 23 DQ9 24 DQ13 75 VDD 76 VDD 127 VSS 128 VSS 179 VSS 180 DQ60 25 VSS 26 VSS 77 NC 78 A152 129 DQ32 130 DQ36 181 DQ56 182 DQ61 27 DQS1 28 DM1 79 BA2 80 A142 131 DQ33 132 DQ37 183 DQ57 184 VSS 29 DQS1 30 RESET 81 VDD 82 VDD 133 VSS 134 VSS 185 VSS 186 DQS7 31 VSS 32 VSS 83 A12/BC 84 A11 135 DQS4 136 DM4 187 DM7 188 DQS7 33 DQ10 34 DQ14 85 A9 86 A7 137 DQS4 138 VSS 189 VSS 190 VSS 35 DQ11 36 DQ15 87 VDD 88 VDD 139 VSS 140 DQ38 191 DQ58 192 DQ62 37 VSS 38 VSS 89 A8 90 A6 141 DQ34 142 DQ39 193 DQ59 194 DQ63 39 DQ16 40 DQ20 91 A5 92 A4 143 DQ35 144 VSS 195 VSS 196 VSS 41 DQ17 42 DQ21 93 VDD 94 VDD 145 VSS 146 DQ44 197 SA0 198 EVENT 43 VSS 44 VSS 95 A3 96 A2 147 DQ40 148 DQ45 199 VDDSPD 200 SDA 45 DQS2 46 DM2 97 A1 98 A0 149 DQ41 150 VSS 201 SA1 202 SCL 47 DQS2 48 VSS 99 VDD 100 VDD 151 VSS 152 DQS5 203 VTT 204 VTT 49 VSS 50 DQ22 101 CK0 102 CK1 153 DM5 154 DQS5 51 DQ18 52 DQ23 103 CK0 104 CK1 155 VSS 156 VSS NC = No Connect; RFU = Reserved Future Use 1. TEST (pin 125) is reserved for bus analysis probes and is NC on normal memory modules. 2. This address might be connected to NC balls of the DRAMs (depending on density); either way they will be connected to the termination resistor. Rev. 0.2 / Dec. 2008 10 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C 3. Functional Block Diagram SPD/TS VREFCA VREFDQ D0-D3 VDD D0-D3 D0-D3 VSS D0-D3, SPD, Temp sensor CK0 D0-D3 CK0 D0-D3 Terminated at near card edge ODT1 NC S1 NC EVENT Temp Sensor RESET D0-D3 D0 D1 D2 D3 Vtt A[O:N]/BA[O:N] ODT Vtt VDDSPD CK1 A[O:N]/BA[O:N] ODT SDA WP CK1 240ohm +/-1% ODT CKE Address and Control Lines A[O:N]/BA[O:N] CK CKE (SPD) Vtt 240ohm +/-1% D3 CK A[O:N]/BA[O:N] ODT CK CKE CK CKE CK CK A[O:N]/BA[O:N] ODT0 CK0 CKE0 WE CK0 CK WE CAS CAS WE ZQ SCL A0 A1 A2 SCL SA0 SA1 240ohm +/-1% D2 WE CK CAS ZQ SDA The SPD may be integrated with the Temp Sensor or may be a separate component EVENT D1 WE CAS RAS CS LDQS LDQS LDM DQ [0:7] UDQS UDQS UDM DQ [8:15] CS DQS6 DQS6 DM6 DQ [48:55] DQS7 DQS7 DM7 DQ [56:63] ZQ SCL Sensor A0 Temp (with SPD) A1 A2 EVENT SCL SA0 SA1 240ohm +/-1% D0 LDQS LDQS LDM DQ [0:7] UDQS UDQS UDM DQ [8:15] CS DQS4 DQS4 DM4 DQ [32:39] DQS5 DQS5 DM5 DQ [40:47] ZQ LDQS LDQS LDM DQ [0:7] UDQS UDQS UDM DQ [8:15] RAS DQS2 DQS2 DM2 DQ [16:23] DQS3 DQS3 DM3 DQ [24:31] RAS CS LDQS LDQS LDM DQ [0:7] UDQS UDQS UDM DQ [8:15] RAS DQS0 DQS0 DM0 DQ [0:7] DQS1 DQS1 DM1 DQ [8:15] CAS S0 RAS 3.1 512MB, 64Mx64 Module(1Rank of x16) NOTES 1. DQ wiring may differ from that shown however, DQ, DM, DQS, and DQS relationships are maintained as shown Rank 0 Vtt Vtt VDD Rev. 0.2 / Dec. 2008 11 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C ODT1 240ohm +/-1% SDA The SPD may be integrated with the Temp Sensor or may be a separate component EVENT ODT CK CKE D4 SCL A0 A1 A2 SCL SA0 SA1 (SPD) SDA WP Vtt SPD/TS VREFCA VREFDQ D0-D7 VDD D0-D7 VSS D0-D7, SPD, Temp sensor D0-D7 CK0 D0-D3 CK1 D0-D7 CK0 D0-D3 CK1 D0-D7 EVENT Temp Sensor RESET D0-D7 D4 V1 D0 V2 V2 D5 D1 V3 V3 D6 D2 V4 V4 D7 Vtt A[O:N]/BA[O:N] ODT ODT CK CKE CK A[O:N]/BA[O:N] 240ohm +/-1% D7 WE A[O:N]/BA[O:N] ODT CK CKE V1 CK CKE CK ZQ Vtt VDDSPD 240ohm +/-1% D6 LDQS LDQS LDM DQ [0:7] UDQS UDQS UDM DQ [8:15] CAS CK ZQ WE CAS RAS CS 240ohm +/-1% D5 WE CAS RAS CS ZQ LDQS LDQS LDM DQ [0:7] UDQS UDQS UDM DQ [8:15] RAS ODT CK D3 LDQS LDQS LDM DQ [0:7] UDQS UDQS UDM DQ [8:15] CS ODT 240ohm +/-1% A[O:N]/BA[O:N] CK CKE CK A[O:N]/BA[O:N] 240ohm +/-1% D2 ZQ A[O:N]/BA[O:N] ODT CK CKE CK WE ZQ CKE CAS RAS CS D1 WE LDQS LDQS LDM DQ [0:7] UDQS UDQS UDM DQ [8:15] CAS DQS6 DQS6 DM6 DQ [48:55] DQS7 DQS7 DM7 DQ [56:63] RAS LDQS LDQS LDM DQ [0:7] UDQS UDQS UDM DQ [8:15] CS DQS4 DQS4 DM4 DQ [32:39] DQS5 DQS5 DM5 DQ [40:47] ZQ WE CK CAS RAS LDQS LDQS LDM DQ [0:7] UDQS UDQS UDM DQ [8:15] CS DQS2 DQS2 DM2 DQ [16:23] DQS3 DQS3 DM3 DQ [24:31] 240ohm +/-1% D3 Vtt WE SCL A0 Temp Sensor (with SPD) A1 A2 EVENT SCL SA0 SA1 A[O:N]/BA[O:N] CK1 ZQ CK CAS CK1 CKE1 S1 RAS LDQS LDQS LDM DQ [0:7] UDQS UDQS UDM DQ [8:15] CS ODT CK CKE A[O:N]/BA[O:N] 240ohm +/-1% D0 CK A[O:N]/BA[O:N] ODT0 CK0 CKE0 WE CK0 ZQ WE CAS RAS LDQS LDQS LDM DQ [0:7] UDQS UDQS UDM DQ [8:15] CS DQS0 DQS0 DM0 DQ [0:7] DQS1 DQS1 DM1 DQ [8:15] CAS S0 RAS 3.2 1GB, 128Mx64 Module(2Rank of x16) Address and Control Lines NOTES 1. DQ wiring may differ from that shown however, DQ, DM, DQS, and DQS relationships are maintained as shown Rank 0 Rank 1 Vtt Vtt Vtt VDD Rev. 0.2 / Dec. 2008 VDD 12 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C VDD SCL A0 A1 A2 (SPD) V4 D0 EVENT Rev. 0.2 / Dec. 2008 V9 D12 V8 D1 V5 D10 D5 V5 D2 V1 V3 Rank 0 Rank 1 D6 V7 V4 SDA NOTES 1. DQ wiring may differ from that shown however, DQ, DM, DQS, and DQS relationships are maintained as shown V1 V3 SDA WP SCL A0 Temp Sensor (with SPD) A1 A2 EVENT D3 V2 D11 D13 V6 V6 Vtt V1 D7 D15 V7 V9 V8 D4 D14 DQS7 DQS7 DM7 DQ[56:43] A[O:N]/BA[O:N] ODT DQS6 DQS6 DM6 DQ[48:55] A[O:N]/BA[O:N] ODT CK CKE CK CKE CK D7 WE 240ohm +/-1% DQS DQS DM DQ [0:7] ZQ A[O:N]/BA[O:N] ODT CK CKE WE D5 CK CAS CK WE 240ohm +/-1% ZQ Vtt V2 D9 DQS4 DQS4 DM4 DQ[32:39] A[O:N]/BA[O:N] ODT WE CK CAS RAS CS CK CKE 240ohm +/-1% D6 CAS RAS CS ZQ DQS DQS DM DQ [0:7] RAS 240ohm +/-1% D12 CAS A[O:N]/BA[O:N] ODT CK CKE CK CAS D13 ZQ DQS DQS DM DQ [0:7] CS A[O:N]/BA[O:N] ODT CK CKE 240ohm +/-1% ZQ DQS DQS DM DQ [0:7] RAS A[O:N]/BA[O:N] ODT CK CKE CK CK CAS D15 Vtt CS A[O:N]/BA[O:N] ODT CK CKE WE CK CAS WE CAS 240ohm +/-1% ZQ WE RAS CS CS RAS RAS CS CS A[O:N]/BA[O:N] ODT RAS ODT A[O:N]/BA[O:N] A[O:N]/BA[O:N] ODT CK CKE CK CKE WE 240ohm +/-1% D14 DQS DQS DM DQ [0:7] D10 D8 SCL SA0 SA1 ZQ DQS DQS DM DQ [0:7] 240ohm +/-1% The SPD may be integrated with the Temp Sensor or may be a separate component SCL SA0 SA1 A[O:N]/BA[O:N] ODT CK CKE CK CK ZQ CK CAS WE WE CAS 240ohm +/-1% 240ohm +/-1% D4 DQS DQS DM DQ [0:7] D8 LDQS LDQS LDM DQ [0:7] ZQ WE ODT0 CK0 CK0 CKE0 CK CKE WE CK CAS RAS CS CS RAS RAS 240ohm +/-1% ZQ Cterm Vtt DQS DQS DM DQ [0:7] D9 CAS A[O:N]/BA[O:N] ODT CK CKE CK WE CAS D2 240ohm +/-1% ZQ VDD Vtt D3 LDQS LDQS LDM DQ [0:7] CS A[O:N]/BA[O:N] ODT CK CK CKE 240ohm +/-1% ZQ LDQS LDQS LDM DQ [0:7] RAS ODT A[O:N]/BA[O:N] A[O:N]/BA[O:N] ODT CK WE CAS CK CKE 240ohm +/-1% D0 ZQ S0 A[O:N]/BA[O:N] CKE1 ODT1 WE CK1 CK WE CK CKE 240ohm +/-1% ZQ DQS DQS DM DQ [0:7] RAS LDQS LDQS LDM DQ [0:7] D1 CAS RAS CS ZQ Cterm CS DQS DQS DM DQ [0:7] RAS DQS0 DQS0 DM0 DQ[0:7] CS DQS DQS DM DQ [0:7] CS 240ohm +/-1% D11 DQS1 DQS1 DM1 DQ[8:15] DQS2 DQS2 DM2 DQ[6:23] CK1 ZQ CAS CS RAS DQS DQS DM DQ [0:7] WE RAS S1 DQS3 DQS3 DM3 DQ[24:31] CAS 3.3 2GB, 256Mx64 Module(2Rank of x8) DQS5 DQS5 DM5 DQ[40:47] Vtt VDDSPD SPD/TS VREFCA VREFDQ D0-D15 VDD D0-D15 D0-D15 VSS D0-D15, SPD, Temp sensor CK0 D0-D7 CK1 D8-D15 CK0 D0-D7 CK1 D8-D15 CKE0 D0-D7 CKE1 D8-D15 S0 D0-D7 S1 D8-D15 ODT0 D0-D7 ODT1 D8-D15 EVENT Temp Sensor RESET D0-D15 13 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C 4. ABSOLUTE MAXIMUM RATINGS 4.1 Absolute Maximum DC Ratings Symbol Parameter VDD VDDQ VIN, VOUT TSTG Rating Units Notes Voltage on VDD pin relative to Vss - 0.4 V ~ 1.975 V V 1,3 Voltage on VDDQ pin relative to Vss - 0.4 V ~ 1.975 V V 1,3 Voltage on any pin relative to Vss - 0.4 V ~ 1.975 V V 1 -55 to +100 1, 2 Storage Temperature 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must be not greater than 0.6XVDDQ,When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV. 4.2 DRAM Component Operating Temperature Range Symbol TOPER Parameter Rating Units Notes Normal Temperature Range 0 to 85 ,2 Extended Temperature Range 85 to 95 1,3 1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measurement conditions, please refer to the JEDEC document JESD51-2. 2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating conditions 3. Some applications require operation of the DRAM in the Extended Temperature Range between 85... and 95... case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply: a) Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 s. (This double refresh requirement may not apply for some devices.) It is also possible to specify a component with 1X refresh (tREFI to 7.8s) in the Extended Temperature Range. Please refer to supplier data sheet and/ or the DIMM SPD for option avail ability. b) If Self-Refresh operation is required in the Extended Temperature Range, than it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0band MR2 A7 = 1b) or enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b). Rev. 0.2 / Dec. 2008 14 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C 5. AC & DC Operating Conditions 5.1 Recommended DC Operating Conditions Symbol Parameter VDD VDDQ Rating Units Notes 1.575 V 1,2 1.575 V 1,2 Min. Typ. Max. Supply Voltage 1.425 1.500 Supply Voltage for Output 1.425 1.500 1. Under all conditions, VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD. AC parameters are measured with VDD bad VDDQ tied together. 5.2 DC & AC Logic Input Levels 5.2.1 DC & AC Logic Input Levels for Single-Ended Signals DDR3-800, DDR3-1066, DDR3-1333 Symbol Parameter Unit Notes - V 1, 2 Vref - 0.100 V 1, 2 - V 1, 2 Vref - 0.175 V 1, 2 Min Max Vref + 0.100 VIH(DC) DC input logic high VIL(DC) DC input logic low VIH(AC) AC input logic high VIL(AC) AC input logic low VRefDQ (DC) Reference Voltage for DQ, DM inputs 0.49 * VDD 0.51 * VDD V 3, 4 VRefCA (DC) Reference Voltage for ADD, CMD inputs 0.49 * VDD 0.51 * VDD V 3, 4 VTT Termination voltage for DQ, DQS outputs VDDQ/2 - TBD VDDQ/2 + TBD V Vref + 0.175 1. For DQ and DM, Vref = VrefDQ. For input only pins except RESET#, Vref = VrefCA. 2. The "t.b.d." entries might change based on overshoot and undershoot specification. 3. The ac peak noise on VRef may not allow VRef to deviate from VRef (DC) by more than +/-1% VDD (for reference: approx. +/- 15 mV). For reference: approx. VDD/2 +/- 15 mV. The dc-tolerance limits and ac-noise limits for the reference voltages VRefCA and VRefDQ are illustrated in figure 6.2.1. It shows a valid reference voltage VRef (t) as a function of time. (VRef stands for VRefCA and VRefDQ likewise).VRef(DC) is the linear average of VRef (t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirements in Table 1. Furthermore VRef (t) may temporarily deviate from VRef (DC) by no more than +/- 1% VDD. Rev. 0.2 / Dec. 2008 15 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C voltage VDD VRef(t) VRef ac-noise VRef(DC)max VRef(DC) VDD/2 VRef(DC)min VSS time < Figure 6.2.1: Illustration of Vref (DC) tolerance and Vref AC-noise limits > The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on VRef. "VRef" shall be understood as VRef (DC), as defined in Figure 6.2.1 This clarifies, that dc-variations of VRef affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured. System timing and voltage budgets need to account for VRef (DC) deviations from the optimum position within the data-eye of the input signals. This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VRef ac-noise. Timing and voltage effects due to ac-noise on VRef up to the specified limit (+/-1% of VDD) are included in DRAM timings and their associated deratings. 5.2.2 DC & AC Logic Input Levels for Differential Signals Symbol Parameter VIHdiff Differential input logic high VILdiff Differential input logic low DDR3-800, DDR3-1066, DDR3-1333, DDR3-1600 Unit Notes - V 1 - 0.200 V 1 Min Max + 0.200 Note1: Refer to "Overshoot and Undershoot Specification section 6.5 on 26 page Rev. 0.2 / Dec. 2008 16 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C 5.2.3 Differential Input Cross Point Voltage To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK, CK# and DQS, DQS#) must meet the requirements in Table 6.2.3 The differential input cross point voltage VIX is measured from the actual cross point of true and complement signal to the midlevel between of VDD and VSS. VDD CK#, DQS# VIX VDD/2 VIX VIX CK, DQS VSS < Figure 5.2.3 Vix Definition > DDR3-800, DDR3-1066, DDR3-1333, DDR3-1600 Symbol VIX Parameter Differential Input Cross Point Voltage relative to VDD/2 Unit Min Max - 150 + 150 Notes mV < Table 5.2.3: Cross point voltage for differential input signals (CK, DQS) > Rev. 0.2 / Dec. 2008 17 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C 5.3 Slew Rate Definitions 5.3.1 For Single Ended Input Signals - Input Slew Rate for Input Setup Time (tIS) and Data Setup Time (tDS) Setup (tIS and tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VRef and the first crossing of VIH (AC) min. Setup (tIS and tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VRef and the first crossing of VIL (AC) max. - Input Slew Rate for Input Hold Time (tIH) and Data Hold Time (tDH) Hold nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL (DC) max and the first crossing of VRef. Hold (tIH and tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH (DC) min and the first crossing of VRef. Measured Description Input slew rate for rising edge Min Max Vref VIH (AC) min Input slew rate for falling edge Vref VIL (AC) max Input slew rate for rising edge VIL (DC) max Vref Input slew rate for falling edge VIH (DC) min Vref Defined by Applicable for VIH (AC) min-Vref Delta TRS Vref-VIL (AC) max Setup (tIS, tDS) Delta TFS Vref-VIL (DC) max Delta TFH VIH (DC) min-Vref Hold (tIH, tDH) Delta TRH < Table 5.3.1: Single-Ended Input Slew Rate Definition > Part A: Set up Single Ended input Voltage(DQ,ADD, CMD) Delta TRS vIH(AC)min vIH(DC)min vRefDQ or vRefCA vIL(DC)max vIL(AC)max Delta TFS Rev. 0.2 / Dec. 2008 18 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C P a rt B : H o ld Single Ended input Voltage(DQ,ADD, CMD) D e lta T R H v IH (A C )m in v IH (D C )m in v R e fD Q o r v R e fC A v IL (D C )m a x v IL (A C )m a x D e lta T F H < Figure 5.3.1: Input Nominal Slew Rate Definition for Single-Ended Signals > 5.3.2 Differential Input Signals Input slew rate for differential signals (CK, CK# and DQS, DQS#) are defined and measured as shown in below Table and Figure . Description Differential input slew rate for rising edge (CK-CK and DQS-DQS) Differential input slew rate for falling edge (CK-CK and DQS-DQS) Measured Min Max VILdiffmax VIHdiffmin VIHdiffmin VILdiffmax Defined by VIHdiffmin-VILdiffmax DeltaTRdiff VIHdiffmin-VILdiffmax DeltaTFdiff Note: The differential signal (i.e. CK-CK and DQS-DQS) must be linear between these thresholds. Rev. 0.2 / Dec. 2008 19 Differential Input Voltage (i.e. DQS-DQS; CK-CK) HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C D e lta T R d iff vIH d iffm in 0 vILd iffm a x D e lta T F d iff < Figure 5.3.2: Differential Input Slew Rate Definition for DQS,DQS# and CK,CK# > 5.4 DC & AC Output Buffer Levels 5.4.1 Single Ended DC & AC Output Levels Below table shows the output levels used for measurements of single ended signals. Symbol VOH(DC) VOM(DC) VOL(DC) VOH(AC) VOL(AC) Parameter DC output high measurement level (for IV curve linearity) DC output mid measurement level (for IV curve linearity) DC output low measurement level (for IV curve linearity) AC output high measurement level (for output SR) DDR3-800, 1066, 1333 Unit 0.8 x VDDQ V 0.5 x VDDQ V 0.2 x VDDQ V VTT + 0.1 x VDDQ V Notes 1 AC output low measurement level VTT - 0.1 x VDDQ V 1 (for output SR) 1. The swing of 0.1 x VDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40 and an effective test load of 25 to VTT = VDDQ / 2. Rev. 0.2 / Dec. 2008 20 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C 5.4.2 Differential DC & AC Output Levels Below table shows the output levels used for measurements of differential signals. Symbol VOHdiff (AC) Parameter DDR3-800, 1066, 1333 Unit Notes + 0.2 x VDDQ V 1 AC differential output high measurement level (for output SR) VOLdiff (AC) AC differential output low - 0.2 x VDDQ V 1 measurement level (for output SR) 1. The swing of ae 0.2 x VDDQ is based on approximately 50% of the static differential output high or low swing with a driver impedance of 40Y and an effective test load of 25Y to VTT = VDDQ/2 at each of the differential output 5.4.3 Single Ended Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for single ended signals as shown in below Table and Figure 6.4.3. Description Measured From To Single ended output slew rate for rising edge VOL(AC) VOH(AC) Single ended output slew rate for falling edge VOH(AC) VOL(AC) Defined by VOH(AC)-VOL(AC) DeltaTRse VOH(AC)-VOL(AC) DeltaTFse Note: Output slew rate is verified by design and characterisation, and may not be subject to production test. Single Ended Output Voltage(l.e.DQ) D e lt a T R s e vO H (A C ) V vO L(A C ) D e lt a T F s e < Figure 5.4.3: Single Ended Output Slew Rate Definition > Rev. 0.2 / Dec. 2008 21 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C Parameter Symbol Single-ended Output Slew Rate SRQse DDR3-800 DDR3-1066 DDR3-1333 Min Max Min Max Min Max 2.5 5 2.5 5 2.5 5 Units V/ns *** Description: SR: Slew Rate Q: Query Output (like in DQ, which stands for Data-in, Query-Output) For Ron = RZQ/7 setting < Table 5.4.3: Output Slew Rate (single-ended) > 5.4.4 Differential Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff (AC) and VOHdiff (AC) for differential signals as shown in below Table and Figure 5.4.4 Description Measured Defined by From To Differential output slew rate for rising edge VOLdiff (AC) VOHdiff (AC) Differential output slew rate for falling edge VOHdiff (AC) VOLdiff (AC) VOHdiff (AC)-VOLdiff (AC) DeltaTRdiff VOHdiff (AC)-VOLdiff (AC) DeltaTFdiff Note: Output slew rate is verified by design and characterization, and may not be subject to production test.. Differential Output Voltage(i.e. DQS-DQS) D e lta T R d iff v O H d iff(A C ) O v O L d iff(A C ) D e lta T F d iff < Figure 5.4.4: Differential Output Slew Rate Definition > Rev. 0.2 / Dec. 2008 22 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C DDR3-800 Parameter Differential Output Slew Rate Symbol SRQdiff DDR3-1066 DDR3-1333 Min Max Min Max Min Max 5 10 5 10 5 10 Units V/ns ***Description: SR: Slew Rate Q: Query Output (like in DQ, which stands for Data-in, Query-Output) diff: Differential Signals For Ron = RZQ/7 setting < Table 5.4.4: Differential Output Slew Rate > 5.5 Overshoot and Undershoot Specifications 5.5.1 Address and Control Overshoot and Undershoot Specifications Description Maximum peak amplitude allowed for overshoot area (see Figure) Maximum peak amplitude allowed for undershoot area (see Figure) Maximum overshoot area above VDD (See Figure) Maximum undershoot area below VSS (See Figure) Specification DDR3-800 DDR3-1066 DDR3-1333 0.4V 0.4V 0.4V 0.4V 0.4V 0.4V 0.67 V-ns 0.5 V-ns 0.4 V-ns 0.67 V-ns 0.5 V-ns 0.4 V-ns < Table 5.5.1: AC Overshoot/Undershoot Specification for Address and Control Pins > < Figure 5.5.1: Address and Control Overshoot and Undershoot Definition > Maximum Amplitude Overshoot Area Volts (V) VDD VSS Undershoot Area Maximum Amplitude Time (ns) Rev. 0.2 / Dec. 2008 23 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C 5.5.2 Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications Description Maximum peak amplitude allowed for overshoot area (see Figure) Maximum peak amplitude allowed for undershoot area (see Figure) Maximum overshoot area above VDDQ (See Figure) Maximum undershoot area below VSSQ (See Figure) Specification DDR3-800 DDR3-1066 DDR3-1333 0.4V 0.4V 0.4V 0.4V 0.4V 0.4V 0.25 V-ns 0.19 V-ns 0.15 V-ns 0.25 V-ns 0.19 V-ns 0.15 V-ns < Table 5.5.2: AC Overshoot/Undershoot Specification for Clock, Data, Strobe and Mask > M a x im u m A m p litu d e O v e rsh o o t A re a V o lts (V ) VDDQ VSSQ U n d e rsh o o t A re a M a x im u m A m p litu d e T im e (n s) C lo c k , D a ta S tro b e a n d M a sk O v e rsh o o t a n d U n d e rsh o o t D e fin itio n < Figure 5.5.2: Clock, Data, Strobe and Mask Overshoot and Undershoot Definition > Rev. 0.2 / Dec. 2008 24 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C 5.6 Pin Capacitance Parameter Symbol DDR3-800 DDR3-1066 DDR3-1333 Min Max Min Max Min Max Units Notes Input/output capacitance (DQ, DM, DQS, DQS#, TDQS, TDQS#) CIO TBD TBD TBD TBD TBD TBD pF 1,2,3 Input capacitance, CK and CK# CCK TBD TBD TBD TBD TBD TBD pF 2,3,5 Input capacitance delta CK and CK# CDCK TBD TBD TBD TBD TBD TBD pF 2,3,4 CI TBD TBD TBD TBD TBD TBD pF 2,3,6 CDDQS TBD TBD TBD TBD TBD TBD pF 2,3,12 CDI_CTRL TBD TBD TBD TBD TBD TBD pF 2,3,7,8 TBD TBD TBD TBD TBD TBD pF 2,3,9,1 0 TBD TBD TBD TBD TBD TBD pF 2,3,11 Input capacitance (All other input-only pins) Input capacitance delta, DQS and DQS# Input capacitance delta (All CTRL input-only pins) Input capacitance delta (All ADD/CMD input-only pins) CDI_ADD_C Input/output capacitance delta (DQ, DM, DQS, DQS#) MD CDIO Notes: 1. TDQS/TDQS# are not necessarily input function but since TDQS is sharing DM pin and the parasitic characterization of TDQS/TDQS# should be close as much as possible, Cio & Cdio requirement is applied (recommend deleting note or changing to "Although the DM, TDQS and TDQS# pins have different functions, the loading matches DQ and DQS.") 2. This parameter is not subject to production test. It is verified by design and characterization. Input capacitance is measured according to JEP147("PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER(VNA)") with VDD, VDDQ, VSS,VSSQ applied and all other pins floating (except the pin under test, CKE, RESET# and ODT as necessary). VDD=VDDQ=1.5V, VBIAS=VDD/2 and on-die termination off. 3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here 4. Absolute value of CCK-CCK#. 5. The minimum CCK will be equal to the minimum CI. 6. Input only pins include: ODT, CS, CKE, A0-A15, BA0-BA2, RAS#, CAS#, WE#. 7. CTRL pins defined as ODT, CS and CKE. 8. CDI_CTRL=CI(CNTL) - 0.5 * CI(CLK) + CI(CLK#)) 9. ADD pins defined as A0-A15, BA0-BA2 and CMD pins are defined as RAS#, CAS# and WE#. 10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK#)) 11. CDIO=CIO(DQ) - 0.5*(CIO(DQS)+CIO(DQS#)) 12. Absolute value of CIO(DQS) - CIO(DQS#) Rev. 0.2 / Dec. 2008 25 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C 5.7 IDD Specifications (TCASE: 0 to 95oC) 512MB, 64M x 64 SO-DIMM: HMT164S6AFP6C Symbol DDR3 800 DDR3 1066 DDR3 1333 Unit note IDD0 360 420 480 mA IDD1 480 540 620 mA IDD2P(F) 100 120 140 mA IDD2P(S) 40 40 40 mA IDD2Q 180 240 280 mA IDD2N 200 240 300 mA IDD3P 140 180 200 mA IDD3N 220 280 340 mA IDD4W 700 880 1060 mA IDD4R 700 860 1020 mA IDD5B 740 780 840 mA IDD6(D) 40 40 40 mA 1 IDD6(S) 24 24 24 mA 1 IDD7 1300 1420 1720 mA 1GB, 128M x 64 SO-DIMM: HMT112S6AFP6C Symbol DDR3 800 DDR3 1066 DDR3 1333 Unit IDD0 560 660 780 mA IDD1 680 780 960 mA IDD2P(F) 200 240 280 mA IDD2P(S) 80 80 80 mA IDD2Q 360 480 560 mA IDD2N 400 480 600 mA IDD3P 280 360 400 mA IDD3N 440 560 680 mA IDD4W 900 1120 1360 mA IDD4R 900 1100 1320 mA IDD5B 940 1020 1140 mA IDD6(D) 80 80 80 mA 1 IDD6(S) 48 48 48 mA 1 IDD7 1500 1660 2020 mA Rev. 0.2 / Dec. 2008 note 26 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C 2GB, 256M x 64 SO-DIMM: HMT125S6AFP8C Symbol DDR3 800 DDR3 1066 DDR3 1333 Unit IDD0 1040 1240 1440 mA IDD1 1160 1360 1560 mA IDD2P(F) 400 480 560 mA IDD2P(S) 160 160 160 mA IDD2Q 720 960 1120 mA IDD2N 800 960 1200 mA IDD3P 560 720 800 mA IDD3N 880 1120 1360 mA IDD4W 1520 1920 2160 mA IDD4R 1440 1800 2280 mA IDD5B 1880 2040 2320 mA IDD6(D) 160 160 160 mA 1 IDD6(S) 96 96 96 mA 1 IDD7 2200 2480 3040 mA Rev. 0.2 / Dec. 2008 note 27 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C 5.7 IDD Measurement Conditions Within the tables provided further down, an overview about the IDD measurement conditions is provided as follows: Table 1 -- Overview of Tables providing IDD Measurement Conditions and DRAM Behavior Table number Measurement Conditions Table 5 on page 33 IDD0 and IDD1 Table 6 on page 36 IDD2N, IDD2Q, IDD2P(0), IDD2P(1) Table 7 on page 38 IDD3N and IDD3P Table 8 on page 39 IDD4R, IDD4W, IDD7 Table 9 on page 42 IDD7 for different Speed Grades and different tRRD, tFAW conditions Table 10 on page 43 IDD5B Table 11 on page 44 IDD6, IDD6ET Within the tables about IDD measurement conditions, the following definitions are used: - LOW is defined as VIN <= VILAC (max.); HIGH is defined as VIN >= VIHAC (min.). - STABLE is defined as inputs are stable at a HIGH or LOW level. - FLOATING is defined as inputs are VREF = VDDQ / 2. - SWITCHING is defined as described in the following 2 tables. Table 2 -- Definition of SWITCHING for Address and Command Input Signals SWITCHING for Address (row, column) and Command Signals (CS, RAS, CAS, WE) is defined as: If not otherwise mentioned the inputs are stable at HIGH or LOW during 4 clocks and change Address (row, column): then to the opposite value (e.g. Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax ..... please see each IDDx definition for details Bank address: If not otherwise mentioned the bank addresses should be switched like the row/column addresses - please see each IDDx definition for details Define D = {CS, RAS, CAS, WE}:= {HIGH, LOW, LOW, LOW} Define D = {CS, RAS, CAS, WE}:= {HIGH, HIGH,HIGH,HIGH} Command (CS, RAS, CAS, WE): Define Command Background Pattern = D D D D D D D D D D D D... If other commands are necessary (e.g. ACT for IDD0 or Read for IDD4R), the Background Pattern Command is substituted by the respective CS, RAS, CAS, WE levels of the necessary command. See each IDDx definition for details and figures 1,2,3 as examples. Rev. 0.2 / Dec. 2008 28 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C Table 3 -- Definition of SWITCHING for Data (DQ) SWITCHING for Data (DQ) is defined as Data DQ is changing between HIGH and LOW every other data transfer (once per clock) for DQ signals, which means that data DQ is stable during one clock; see each IDDx definition for exceptions from this rule and for further details. See figures 1,2,3 as examples. Data (DQ) Data Masking (DM) NO Switching; DM must be driven LOW all the time Timing parameters are listed in the following table: Table 4 -- For IDD testing the following parameters are utilized. Parameter Bin DDR3-800 5-5-5 tCKmin(IDD) 6-6-6 DDR3-1066 6-6-6 2.5 CL(IDD) 7-7-7 DDR3-1333 8-8-8 7-7-7 1.875 8-8-8 9-9-9 1.5 Unit ns 5 6 6 7 8 7 8 9 clk tRCDmin(IDD) 12.5 15 11.25 13.13 15 10.5 12 13.5 ns tRCmin(IDD) 50 52.5 48.75 50.63 52.50 46.5 48 49.5 ns tRASmin(IDD) 37.5 37.5 37.5 37.5 37.5 36 36 36 ns tRPmin(IDD) 12.5 15 11.25 13.13 15 10.5 12 13.5 ns x4/x8 40 40 37.5 37.5 37.5 30 30 30 ns x16 50 50 50 50 50 45 45 45 ns x4/x8 10 10 7.5 7.5 7.5 6.0 6.0 6.0 ns x16 10 10 10 10 10 7.5 7.5 7.5 ns tRFC(IDD) - 90 90 90 90 90 90 90 90 ns tRFC(IDD) - 1 110 110 110 110 110 110 110 110 ns tRFC(IDD) - 2 160 160 160 160 160 160 160 160 ns tRFC(IDD) - 4 tbd tbd tbd tbd tbd tbd tbd tbd ns tFAW(IDD) tRRD(IDD) 512Mb Gb Gb Gb The following conditions apply: - IDD specifications are tested after the device is properly initialized. - Input slew rate is specified by AC Parametric test conditions. - IDD parameters are specified with ODT and output buffer disabled (MR1 Bit A12). Rev. 0.2 / Dec. 2008 29 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C Table 5 -- IDD Measurement Conditions for IDD0 and IDD1 IDD0 Current Operating Current 0 Name -> One Bank Activate -> Precharge IDD1 Operating Current 1 -> One Bank Activate -> Read -> Precharge Measurement Condition Timing Diagram Example Figure 1 CKE HIGH HIGH External Clock on on tCK tCKmin(IDD) tCKmin(IDD) tRC tRCmin(IDD) tRCmin(IDD) tRAS tRASmin(IDD) tRASmin(IDD) tRCD n.a. tRCDmin(IDD) tRRD n.a. n.a. CL n.a. CL(IDD) AL n.a. 0 CS HIGH between. Activate and Precharge HIGH between Activate, Read and Commands Precharge Command Inputs SWITCHING as described in Table 2 SWITCHING as described in Table 2; only (CS,RAS, CAS, WE) only exceptions are Activate and exceptions are Activate, Read and Precharge commands; example of IDD0 Precharge commands; example of IDD1 pattern: pattern: A0DDDDDDDDDDDDDD P0 A0DDDDR0DDDDDDDDD P0 (DDR3-800: tRAS = 37.5ns between (DDR3-800 -555: tRCD = 12.5ns between (A)ctivate and (P)recharge to bank 0; (A)ctivate and (R)ead to bank 0; Definition of D and D: see Table 2 Definition of D and D: see Table 2) Rev. 0.2 / Dec. 2008 30 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C Table 5 -- IDD Measurement Conditions for IDD0 and IDD1 IDD0 Current Operating Current 0 Name -> One Bank Activate -> Precharge Row, Column Addresses IDD1 Operating Current 1 -> One Bank Activate -> Read -> Precharge Row addresses SWITCHING as described Row addresses SWITCHING as described in Table 2; in Table 2; Address Input A10 must be LOW all the Address Input A10 must be LOW all the time! time! Bank Addresses bank address is fixed (bank 0) bank address is fixed (bank 0) Data I/O SWITCHING as described in Table 3 Read Data: output data switches every clock, which means that Read data is stable during one clock cycle. To achieve Iout = 0mA, the output buffer should be switched off by MR1 Bit A12 set to "1". When there is no read data burst from DRAM, the DQ I/O should be FLOATING. Output Buffer DQ,DQS off / 1 off / 1 ODT disabled disabled / MR1 bits [A6, A2] / [0,0] / [0,0] Burst length n.a. 8 fixed / MR0 Bits [A1, A0] = {0,0} Active banks one one ACT-PRE loop ACT-RD-PRE loop all other all other / MR1 bit A12 Idle banks Precharge Power Down Mode / n.a. n.a. Mode Register Bit 12 Rev. 0.2 / Dec. 2008 31 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T12 T14 T16 T18 CK 000 BA[2:0] ADDR_a[9:0] 000 3FF 000 3FF 000 00 11 00 11 00 3F ADDR_b[10] ADDR_c[12:11] CS RAS CAS WE CMD ACT D DQ DM D# D# D RD D# D# D D D# D# D D D# PRE D D D# 0 0 1 1 0 0 1 1 IDD1 Measurment Loop < Figure 1. IDD1 Example > (DDR3-800-555, 512Mb x8): Data DQ is shown but the output buffer should be switched off (per MR1 Bit A12 ="1") to achieve Iout = 0mA. Address inputs are split into 3 parts. Rev. 0.2 / Dec. 2008 32 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C Table 6 -- IDD Measurement Conditions for IDD2N, IDD2P(1), IDD2P(0) and IDD2Q Name IDD2P(1) a IDD2N Current Precharge Power Precharge Standby Down Current Current Fast Exit MRS A12 Bit = 1 IDD2P(0) IDD2Q Precharge Power Down Current Slow Exit MRS A12 Bit = 0 Precharge Quiet Standby Current Measurement Condition Timing Diagram Example Figure 2 CKE HIGH LOW LOW HIGH External Clock on on on on tCK tCKmin(IDD) tCKmin(IDD) tCKmin(IDD) tCKmin(IDD) tRC n.a. n.a. n.a. n.a. tRAS n.a. n.a. n.a. n.a. tRCD n.a. n.a. n.a. n.a. tRRD n.a. n.a. n.a. n.a. CL n.a. n.a. n.a. n.a. AL n.a. n.a. n.a. n.a. CS HIGH STABLE STABLE HIGH Bank Address, Row Addr. and Command Inputs SWITCHING as described in Table 2 STABLE STABLE STABLE Data inputs SWITCHING FLOATING FLOATING FLOATING Output Buffer DQ,DQS / MR1 bit A12 off / 1 off / 1 off / 1 off / 1 ODT / MR1 bits [A6, A2] disabled / [0,0] disabled / [0,0] disabled / [0,0] disabled / [0,0] Burst length n.a. n.a. n.a. n.a. Active banks none none none none Idle banks all all all all Fast Exit / 1 (any valid command after tXPb) Slow Exit / 0 Slow exit (RD and n.a. ODT commands must satisfy tXPDLL-AL) Precharge Power Down Mode / Mode Register Bit a n.a. a. a. In DDR3, the MRS Bit 12 defines DLL on/off behaviour ONLY for precharge power down. There are 2 different b. Precharge Power Down states possible: one with DLL on (fast exit, bit 12 = 1) and one with DLL off (slow exit, bit 12 = 0). b. Because it is an exit after precharge power down, the valid commands are: Activate, Refresh, Mode-Register Set, Enter - Self Refresh Rev. 0.2 / Dec. 2008 33 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 CK BA[2:0] ADDR[12:0] 0 7 0 0 7 0 CS RAS CAS WE D# CMD DQ[7:0] FF 00 D# 00 FF D FF 00 D 00 FF D# FF 00 D# 00 FF D FF 00 D 00 FF D# FF 00 D# 00 FF FF DM <Figure 2. IDD2N / IDD3N Example > (DDR3-800-555, 512Mb x8) Rev. 0.2 / Dec. 2008 34 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C Table 7 -- IDD Measurement Conditions for IDD3N and IDD3P(fast exit) Current IDD3N Name Active Standby Current IDD3P Active Power-Down Currenta Always Fast Exit Measurement Condition Timing Diagram Example Figure 2 CKE HIGH LOW External Clock on on tCK tCKmin(IDD) tCKmin(IDD) tRC n.a. n.a. tRAS n.a. n.a. tRCD n.a. n.a. tRRD n.a. n.a. CL n.a. n.a. AL n.a. n.a. CS HIGH STABLE Addr. and cmd Inputs SWITCHING as described in Table 2 STABLE Data inputs SWITCHING as described in Table 3 FLOATING off / 1 off / 1 ODT disabled disabled / MR1 bits [A6, A2] / [0,0] / [0,0] Burst length n.a. n.a. Active banks all all Idle banks none none Output Buffer DQ,DQS / MR1 bit A12 Precharge Power Down Mode / Mode Register Bit a n.a. n.a. (Active Power Down Mode is always "Fast Exit" with DLL on a. DDR3 will offer only ONE active power down mode with DLL on (-> fast exit). MRS bit 12 will not be used for active power down. Instead bit 12 will be used to switch between two different precharge power down modes. Rev. 0.2 / Dec. 2008 35 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C Table 8 -- IDD Measurement Conditions for IDD4R, IDD4W and IDD7 Current IDD4R IDD4W IDD7 Name Operating Current Burst Read Operating Current Burst Write All Bank Interleave Read Current Measurement Condition Timing Diagram Example Figure 3 CKE HIGH HIGH HIGH External Clock on on on tCK tCKmin(IDD) tCKmin(IDD) tCKmin(IDD) tRC n.a. n.a. tRCmin(IDD) tRAS n.a. n.a. tRASmin(IDD) tRCD n.a. n.a. tRCDmin(IDD) tRRD n.a. n.a. tRRDmin(IDD) CL CL(IDD) CL(IDD) CL(IDD) AL 0 0 tRCDmin - 1 tCK CS HIGH btw. valid cmds HIGH btw. valid cmds HIGH btw. valid cmds Command Inputs (CS, RAS, CAS, WE) SWITCHING as described in Table 2; exceptions are Read commands => IDD4R Pattern: SWITCHING as described in Table 2; exceptions are Write commands => IDD4W Pattern: For patterns see Table 9 R0DDDR1DDDR2DDDR3.DD W0DDDW1DDDW2DDDW3 DDD W4... D R4..... Rx = Read from bank x; Wx = Write to bank x; Definition of D and D: see Definition of D and D: see Table 2 Table 2 Rev. 0.2 / Dec. 2008 36 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C Table 8 -- IDD Measurement Conditions for IDD4R, IDD4W and IDD7 Current IDD4R IDD4W IDD7 Name Operating Current Burst Read Operating Current Burst Write All Bank Interleave Read Current column addresses column addresses SWITCHING as described in SWITCHING as described in Table 2; Table 2; Address Input A10 must be Address Input A10 must be LOW all the time! LOW all the time! Row, Column Addresses Bank Addresses bank address cycling (0 -> 1 - bank address cycling (0 -> 1 > 2 -> 3...) Seamless Read Data Burst (BL8): output data switches every clock, which means that Read data is stable during one DQ I/O clock cycle. To achieve Iout = 0mA the output buffer should be > 2 -> 3...) STABLE during DESELECTs bank address cycling (0 -> 1 > 2 -> 3...), see pattern in Table 9 Seamless Write Data Burst Read Data (BL8): output data (BL8): input data switches switches every clock, which every clock, which means that means that Read data is Write data is stable during one stable during one clock cycle. clock cycle. To achieve Iout = 0mA the DM is low all the time. output buffer should be switched off by MR1 Bit A12 switched off by MR1 Bit A12 set to "1". set to "1". Output Buffer DQ,DQS off / 1 off / 1 off / 1 ODT disabled disabled disabled / MR1 bits [A6, A2] / [0,0] / [0,0] / [0,0] 8 fixed / MR0 Bits [A1, A0] = 8 fixed / MR0 Bits [A1, A0] = 8 fixed / MR0 Bits [A1, A0] = {0,0} {0,0} {0,0} Active banks all all all, rotational Idle banks none none none n.a. n.a. n.a. / MR1 bit A12 Burst length Precharge Power Down Mode / Mode Register Bit Rev. 0.2 / Dec. 2008 37 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CK BA[2:0] ADDR[12:0] 000 001 010 011 000 3FF 000 3FF 00 11 00 11 ADDR_b[10] ADDR_c[12:11] CS RAS CAS WE CMD[2:0] DQ[7:0] DM RD D D# D# RD D D# 00 00 FF D# FF 00 RD 00 FF D FF D# 00 00 FF D# FF 00 RD 00 FF FF -> Start of Measurement Loop < Figure 3. IDD4R Example > (DDR3-800-555, 512Mb x8): data DQ is shown but the output buffer should be switched off (per MR1 Bit A12="1") to achieve Iout = 0mA. Address inputs are split into 3 parts. Rev. 0.2 / Dec. 2008 38 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C Table 9 -- Speed IDD7 Pattern for different Speed Grades and different tRRD, tFAW conditions Bin Org. Mb/s IDD7 Patterna tFAW tFAW tRRD tRRD [ns] [CLK] [ns] [CLK] (Note this entire sequence is repeated.) all x4/x8 40 16 10 4 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D all x16 50 20 10 4 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D DDDD all x4/x8 37.5 20 7.5 4 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D DDDD all x16 50 27 10 6 A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D D D D A3 RA3 D D D D D D D A4 RA4 D D D D A5 RA5 D D D D A6 RA6 D D D D A7 RA7 D D D D D D D all x4/x8 30 20 6 4 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D DDDD all x16 45 30 7.5 5 A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3 RA3 D D D D D D D D D D D D D A4 RA4 D D D A5 RA5 D D D A6 RA6 D D D A7 RA7 D D D D D D D D D D D D D all x4/x8 30 24 6 5 A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3 RA3 D D D D D D D A4 RA4 D D D A5 RA5 D D D A6 RA6 D D D A7 RA7 D D D D D D D 6 A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D D D D A3 RA3 D D D D D D D D D D D D A4 RA4 D D D D A5 RA5 D D D D A6 RA6 D D D D A7 RA7 D D D D D D D D D DDD 800 1066 1333 1600 all x16 40 32 7.5 a. A0 = Activation of Bank 0; RA0 = Read with Auto-Precharge of Bank 0; D = Deselect Rev. 0.2 / Dec. 2008 39 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C Table 10 -- IDD Measurement Conditions for IDD5B IDD5B Current Name Burst Refresh Current Measurement Condition CKE HIGH External Clock on tCK tCKmin(IDD) tRC n.a. tRAS n.a. tRCD n.a. tRRD n.a. tRFC tRFCmin(IDD) CL n.a. AL n.a. CS HIGH btw. valid cmds Addr. and cmd Inputs SWITCHING Data inputs SWITCHING Output Buffer DQ,DQS / MR1 bit A12 off / 1 ODT / MR1 bits [A6, A2] disabled / [0,0] Burst length n.a. Active banks Refresh command every tRFC = tRFCmin Idle banks none Precharge Power Down Mode / Mode Register Bit n.a. Rev. 0.2 / Dec. 2008 40 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C Table 11 -- IDD Measurement Conditions for IDD6 and IDD6ET Current IDD6 IDD6ET Name Self-Refresh Current Normal Temperature Range TCASE = 0.. 85 C Self-Refresh Current Extended Temperature Range a TCASE = 0 .. 95 C Measurement Condition Temperature TCASE = 85 C TCASE = 95 C Auto Self Refresh (ASR) / MR2 Bit A6 Disabled / "0" Disabled / "0" Self Refresh Temperature Range (SRT) / MR2 Bit A7 Normal / "0" Extended / "1" CKE LOW LOW External Clock OFF; CK and CK at LOW OFF; CK and CK at LOW tCK n.a. n.a. tRC n.a. n.a. tRAS n.a. n.a. tRCD n.a. n.a. tRRD n.a. n.a. CL n.a. n.a. AL n.a. n.a. CS FLOATING FLOATING Command Inputs (RAS, CAS, WE) FLOATING FLOATING Row, Column Addresses FLOATING FLOATING Bank Addresses FLOATING FLOATING Data I/O FLOATING FLOATING Output Buffer DQ,DQS / MR1 bit A12 off / 1 off / 1 ODT / MR1 bits [A6, A2] disabled / [0,0] disabled / [0,0] Burst length n.a. n.a. Active banks all during self-refresh actions all during self-refresh actions Idle banks all btw. Self-Refresh actions all btw. Self-Refresh actions Precharge Power Down Mode / MR0 bit A12 n.a. n.a. a. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3 SDRAM devices support the following options or requirements referred to in this material. Rev. 0.2 / Dec. 2008 41 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C 6. Electrical Characteristics and AC Timing 6.1 Refresh Parameters by Device Density Parameter Symbol 512Mb 1Gb 2Gb 4Gb 8Gb Units tRFC 90 110 160 300 350 ns 0 xC < TCASE < 85 xC 7.8 7.8 7.8 7.8 7.8 ms 85 xC < TCASE < 95 xC 3.9 3.9 3.9 3.9 3.9 ms REF command to ACT or REF command time Average periodic refresh interval tREFI 6.2 DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin DDR3 800 Speed Bin DDR3-800D DDR3-800E 5-5-5 6-6-6 CL - nRCD - nRP Unit Symbol min max min max Internal read command to first data tAA 12.5 20 15 20 ns ACT to internal read or write delay time tRCD 12.5 -- 15 -- ns PRE command period tRP 12.5 -- 15 -- ns ACT to ACT or REF command period tRC 50 -- 52.5 -- ns ACT to PRE command period tRAS 37.5 9 * tREFI 37.5 9 * tREFI ns Parameter CL = 5 CWL = 5 tCK(AVG) 2.5 3.3 CL = 6 CWL = 5 tCK(AVG) 2.5 3.3 Supported CL Settings Supported CWL Settings Rev. 0.2 / Dec. 2008 Reserved 2.5 3.3 Notes ns 1)2)3)4) ns 1)2)3) 5, 6 6 nCK 5 5 nCK 42 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C DDR3 1066 Speed Bin DDR3-1066E DDR3-1066F DDR3-1066G CL - nRCD - nRP 6-6-6 7-7-7 8-8-8 Unit Parameter Symbol min max min max min max Internal read command to first data tAA 11.25 20 13.125 20 15 20 ns ACT to internal read or write delay time tRCD 11.25 -- 13.125 -- 15 -- ns PRE command period tRP 11.25 -- 13.125 -- 15 -- ns ACT to ACT or REF command period tRC 48.75 -- 50.625 -- 52.5 -- ns ACT to PRE command period tRAS 37.5 9 * tREFI 37.5 9 * tREFI 37.5 9 * tREFI ns CWL = 5 tCK(AVG) 2.5 3.3 CWL = 6 tCK(AVG) CWL = 5 tCK(AVG) 2.5 CWL = 6 tCK(AVG) 1.875 CWL = 5 tCK(AVG) CWL = 6 tCK(AVG) CWL = 5 tCK(AVG) CWL = 6 tCK(AVG) CL = 5 CL = 6 CL = 7 CL = 8 Reserved 3.3 < 2.5 Reserved 1.875 < 2.5 Reserved 1.875 < 2.5 Reserved Reserved ns 1)2)3)4)6) Reserved Reserved ns 4) ns 1)2)3)6) 2.5 3.3 2.5 3.3 Reserved Reserved ns 1)2)3)4) Reserved Reserved ns 4) Reserved ns 1)2)3)4) Reserved ns 4) ns 1)2)3) 1.875 < 2.5 Reserved 1.875 < 2.5 1.875 < 2.5 Supported CL Settings 5, 6, 7, 8 6, 7, 8 6, 8 nCK Supported CWL Settings 5, 6 5, 6 5, 6 nCK Rev. 0.2 / Dec. 2008 Note 43 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C DDR3 1333 Speed Bin DDR3-1333F DDR3-1333J DDR3-1333G DDR3-1333H (optional) (optional) Unit CL - nRCD - nRP 7-7-7 8-8-8 9-9-9 Parameter Symbol min max min max min max min max Internal read command to first tAA 10.5 20 12 20 13.5 20 15 20 ns ACT to internal read or write delay time tRCD 10.5 -- 12 -- 13.5 -- 15 -- ns PRE command period tRP 10.5 -- 12 -- 13.5 -- 15 -- ns ACT to ACT or REF command period tRC 46.5 -- 48 -- 49.5 -- 51 -- ns ACT to PRE command period tRAS 36 9* tREFI 36 9* tREFI 36 9* tREFI 36 9* tREFI ns tCK(AVG) 2.5 3.3 2.5 3.3 CL = 5 CL = 6 CL = 7 CWL = 5 CWL = 6, 7 tCK(AVG) Reserved CWL = 5 tCK(AVG) 2.5 3.3 CWL = 6 tCK(AVG) 1.875 < 2.5 CWL = 7 tCK(AVG) CWL = 5 tCK(AVG) CWL = 6 tCK(AVG) Reserved 2.5 3.3 Note 10-10-10 Reserved Reserved ns 1,2,3,4,7 Reserved Reserved ns 4 ns 1,2,3,7 2.5 3.3 2.5 3.3 Reserved Reserved Reserved ns 1,2,3,4,7 Reserved Reserved Reserved Reserved ns 4 Reserved Reserved Reserved Reserved ns 4 Reserved ns 1,2,3,4,7 Reserved ns 4 ns 1,2,3,7 1.875 1.875 < 2.5 1.875 < 2.5 < 2.5 (Optional) Note 9.10 CL = 8 CL = 9 CWL = 5 tCK(AVG) CWL = 6 tCK(AVG) 1.875 < 2.5 1.875 < 2.5 CWL = 7 tCK(AVG) 1.5 <1.875 1.5 <1.875 CWL = 5, 6 tCK(AVG) CWL = 7 tCK(AVG) CWL = 5, 6 tCK(AVG) CL = 10 CWL = 7 tCK(AVG) Reserved Reserved 1.5 <1.875 Reserved 1.5 <1.875 Reserved Reserved 1.5 <1.875 Reserved 1.5 <1.875 Reserved 1.875 < 2.5 1.875 < 2.5 Reserved Reserved ns 1,2,3,4 Reserved Reserved ns 4 Reserved ns 1,2,3,4 Reserved ns 4 ns 1,2,3 ns 5 1.5 <1.875 Reserved 1.5 <1.875 1.5 <1.875 (Optional) (Optional) (Optional) Supported CL Settings 5, 6, 7, 8, 9 5, 6, 7, 8, 9 6, 7, 8, 9 6, 8, 10 nCK Supported CWL Settings 5, 6, 7 5, 6, 7 5, 6, 7 5, 6, 7 nCK Rev. 0.2 / Dec. 2008 44 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C *Speed Bin Table Notes* Absolute Specification (TOPER; VDDQ = VDD = 1.5V +/- 0.075 V); Notes: 1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK (AVG), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting. 2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guaranteed. An application should use the next smaller JEDEC standard tCK (AVG) value (2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] = tAA [ns] / tCK (AVG) [ns], rounding up to the next `Supported CL'. 3. tCK(AVG).MAX limits: Calculate tCK (AVG) = tAA.MAX / CLSELECTED and round the resulting tCK (AVG) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is tCK(AVG).MAX corresponding to CLSELECTED. 4. `Reserved' settings are not allowed. User must program a different value. 5. `Optional' settings allow certain devices in the industry to support this setting, however, it is not a mandatory feature. Refer to supplier's data sheet and SPD information if and how this setting is supported. 6. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization. 7. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization. 8. It is not a mandatory bin. Refer to supplier's data sheet and/or the DIMM SPD information. 9. If it's supported, the minimum tAA/tRCD/tRP that this device support is 13.125ns. Therefore, In Module application, tAA/tRCD/tRP should be programed with minimum supported values. For example, DDR3-1333H supporting downshift to DDR3-1066F should program SPD as 13.125ns for tAAmin(Byte16)/tRCDmin(Byte18)/tRP(Byte20). DDR31600K supporting down-shift to DDR3-1333H and/or DDR3-1066F should program SPD as 13.125ns for tAAmin(Byte16)/tRCDmin(Byte18)/tRP(Byte20). Rev. 0.2 / Dec. 2008 45 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C 7. DIMM Outline Diagram 7.1 64Mx64 - HMT164S6AFP(R)6C Front View Side 67.60mm 3.80mm max Detail-B pin 1 2.15 2 X 1.80 0.10 20.0mm Detail- A 6.00 30.0mm 2.0 pin 203 21.00 1.00 0.08 mm 39.00 1.65 0.10 3.00 Back View SPD Detail of Contacts A Detail of Contacts B 2.55 0.3 0.15 4.00 2.55 0.20 0.45 0.10 0.3~1.0 0.60 1.00 0.05 3.00 Rev. 0.2 / Dec. 2008 46 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C 64Mx64 - HMT164S6AFP(R)6C (with temperature sensor) Front View Side 3.80mm max 67.60mm 2.0 30.0mm 4.00 0.10 Detail-B pin 1 2.15 2 X 1.80 0.10 20.0mm Detail- A 6.00 SPD (TS) 1.00 0.08 mm pin 203 21.00 39.00 1.65 0.10 3.00 Back View Detail of Contacts A Detail of Contacts B 2.55 0.3 0.15 4.00 2.55 0.20 0.45 0.10 0.3~1.0 0.60 1.00 0.05 3.00 Rev. 0.2 / Dec. 2008 47 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C 7.2 128Mx64 - HMT112S6AFP(R)6C Front View Side 3.80mm max 67.60mm 2.0 30.0mm 4.00 0.10 Detail-B pin 1 20.0mm Detail- A 6.00 SPD 1.00 0.08 mm pin 203 21.00 2.15 2 X 1.80 0.10 39.00 1.65 0.10 3.00 Back View Detail of Contacts A Detail of Contacts B 2.55 0.3 0.15 4.00 2.55 0.20 0.45 0.10 0.3~1.0 0.60 1.00 0.05 3.00 Rev. 0.2 / Dec. 2008 48 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C 128Mx64 - HMT112S6AFP(R)6C (with temperature sensor) Front View Side 3.80mm max 67.60mm 2.0 Detail-B pin 1 2.15 2 X 1.80 0.10 20.0mm Detail- A 6.00 30.0mm 4.00 0.10 1.00 0.08 mm pin 203 21.00 39.00 1.65 0.10 3.00 Back View SPD (TS) Detail of Contacts A Detail of Contacts B 2.55 0.3 0.15 4.00 2.55 0.20 0.45 0.10 0.3~1.0 0.60 1.00 0.05 3.00 Rev. 0.2 / Dec. 2008 49 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C 7.3 256Mx64 - HMT125S6AFP(R)8C Front View Side 67.60mm 3.80mm max 2.0 Detail-B pin 1 20.0mm Detail- A 6.00 30.0mm 4.00 0.10 1.00 0.08 mm pin 203 21.00 1.65 0.10 2.15 2 X 1.80 0.10 39.00 3.00 Bacl View SPD Detail of Contacts A Detail of Contacts B 2.55 0.3 0.15 4.00 2.55 0.20 0.45 0.10 0.3~1.0 0.60 1.00 0.05 3.00 Rev. 0.2 / Dec. 2008 50 HMT164S6AFP(R)6C HMT112S6AFP(R)6C HMT125S6AFP(R)8C 256Mx64 - HMT125S6AFP(R)8C (with temperature sensor) Front View Side 67.60mm 3.80mm max SPD (TS) 2.0 Detail-B pin 1 20.0mm Detail- A 6.00 30.0mm 4.00 0.10 1.00 0.08 mm pin 203 21.00 1.65 0.10 2.15 2 X 1.80 0.10 39.00 3.00 Back View Detail of Contacts A Detail of Contacts B 2.55 0.3 0.15 4.00 2.55 0.20 0.45 0.10 0.3~1.0 0.60 1.00 0.05 3.00 Rev. 0.2 / Dec. 2008 51