RoboClock
CY7B993V, CY7B994V
High Speed Multi Phase PLL Clock Buffer
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-07127 Rev. *J Revised April 26, 2011
Features
■500 ps Max Total Timing Budget (TTB™) window
■12 MHz to 100 MHz (CY7B993V), or 24 MHz to 200 MHz
(CY7B994V) Input/Output Operation
■Matched Pair Output Skew < 200 ps
■Zero Input-to-Output Delay
■18 LVTTL Outputs Driving 50 Terminated Lines
■16 Outputs at 200 MHz: Commercial Temperature
■6 Outputs at 200 MHz: Industrial Temperature
■3.3V LVTTL/LVPECL, Fault-tolerant, and Hot Insertable
Reference Inputs
■Phase Adjustments in 625 ps/1300 ps Steps Up to ± 10.4 ns
■Multiply/Divide Ratios of 1–6, 8, 10, 12
■Individual Output Bank Disable
■Output High Impedance Option for Testing Purposes
■Fully Integrated Phase Locked Loop (PLL) with Lock Indicator
■<50-ps Typical Cycle-to-Cycle Jitter
■Single 3.3V ± 10% Supply
■100-pin TQFP Package
■100-pin BGA Package
Functional Description
The CY7B993V and CY7B994V High-speed Multi-phase PLL
Clock Buffers offer user selectable control over system clock
functions. This multiple output clock driver provides the system
integrator with functions necessary to optimize the timing of
high-performance computer and communication systems.
These devices feature a guaranteed maximum TTB window
specifying all occurrences of output clocks with respect to the
input reference clock across variations in output frequency,
supply voltage, operating temperature, input edge rate, and
process.
Eighteen configurable outputs each drive terminated
transmission lines with impedances as low as 50 while delivering
minimal and specified output skews at LVTTL levels. The outputs are
arranged in five banks. Banks 1 to 4 of four outputs allow a divide
function of 1 to 12, while simultaneously allowing phase
adjustments in 625 ps to 1300 ps increments up to 10.4 ns. One
of the output banks also includes an independent clock invert
function. The feedback bank consists of two outputs, which
allows divide-by functionality from 1 to 12 and limited phase
adjustments. Any one of these eighteen outputs can be
connected to the feedback input as well as driving other inputs.
Selectable reference input is a fault tolerance feature that allows
smooth change-over to secondary clock source, when the
primary clock source is not in operation. The reference inputs
and feedback inputs are configurable to accommodate both
LVTTL or Differential (LVPECL) inputs. The completely
integrated PLL reduces jitter and simplifies board layout.
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RoboClock
CY7B993V, CY7B994V
Document #: 38-07127 Rev. *J Page 2 of 18
Logic Block Diagram
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
FS
OUTPUT_MODE
FBF0
FBDS0
FBDS1
FBDIS
4F0
4F1
4DS0
4DS1
DIS4
3F0
3F1
3DS0
3DS1
DIS3
2F0
2F1
2DS0
2DS1
DIS2
1F0
1F1
1DS0
1DS1
DIS1
QFA0
QFA1
4QA0
4QA1
4QB0
4QB1
3QA0
3QA1
3QB0
3QB1
2QA0
2QA1
2QB0
2QB1
1QA0
1QA1
1QB0
1QB1
LOCK
FBKA+
FBKA–
FBKB+
FBKB–
FBSEL
REFA+
REFA–
REFB+
REFB–
REFSEL
3
INV3
Divide and
Phase
Select
Matrix
Divide and
Phase
Select
Matrix
Divide and
Phase
Select
Matrix
Divide and
Phase
Select
Matrix
Divide and
Phase
Select
Matrix
Phase
Freq.
Detector
Filter VCO
Control Logic
Divide and Phase
Generator
Feedback Bank
Bank 4
Bank 3
Bank 2
Bank 1
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RoboClock
CY7B993V, CY7B994V
Document #: 38-07127 Rev. *J Page 3 of 18
Contents
Features ............................................................................... 1
Functional Description ....................................................... 1
Logic Block Diagram .......................................................... 2
Contents .............................................................................. 3
Pinouts ................................................................................ 4
Block Diagram Description ................................................ 6
Phase Frequency Detector and Filter............................ 6
VCO, Control Logic, Divider, and Phase Generator...... 6
Time Unit Definition ....................................................... 7
Divide and Phase Select Matrix .................................... 7
Output Disable Description............................................ 8
INV3 Pin Function ......................................................... 9
Lock Detect Output Description..................................... 9
Factory Test Mode Description ..................................... 9
Safe Operating Zone ..................................................... 9
Absolute Maximum Conditions ........................................10
Operating Range ................................................................10
Electrical Characteristics...................................................10
Switching Characteristics .................................................11
AC Timing Diagrams ..........................................................13
Ordering Information .........................................................14
Package Diagrams .............................................................15
Document History Page ....................................................17
Sales, Solutions, and Legal Information .........................18
Worldwide Sales and Design Support.......................... 18
Products ....................................................................... 18
PSoC Solutions ............................................................ 18
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CY7B993V, CY7B994V
Document #: 38-07127 Rev. *J Page 4 of 18
Pinouts
Figure 1. Pin Diagram – 100-Pin TQFP
1
3
2
92 91 90 848587 868889 83 82 81 7678 77798093949596979899100
59
60
61
67
66
64
65
63
62
68
69
70
75
73
74
72
71
VCCQ
REFA+
REFA –
REFSEL
REFB–
REFB+
VCCN
FS
2QA0
GND
GND
2QB1
GND
GND
2F0
2QB0
VCCN
FBF0
1F0
GND
VCCQ
FBDIS
DIS4
DIS3
2QA1
58
57
56
55
54
53
52
51
GND
3F1
4F1
3F0
4F0
4DS1
4QB0
GND
VCCN
GND
4QA1
GND
2DS1
4QB1
3DS1
VCCN
4QA0
1DS1
VCCQ
4DS0
3DS0
2DS0
1DS0
GND
GND
17
16
15
9
10
12
11
13
14
8
7
6
4
5
18
19
20
21
22
23
24
25
LOCK
FBDS1
FBDS0
GND
1QB1
VCCN
VCCN
GND
1QA1
GND
GND
QFA1
GND
GND
1QB0
QFA0
VCCN
GND
FBKB+
FBKB–
FBSEL
FBKA–
FBKA+
VCCQ
1QA0
34 35 36 424139 403837 43 44 45 5048 494746
GND
VCCQ
OUTPUT_MODE
GND
INV3
3QB0
GND
VCCN
3QA1
VCCN
DIS2
DIS1
3QB1
VCCQ
3QA0
GND
1F1
2F1
VCCQ
VCCQ
GND
GND
GND
GND
3332313029282726
CY7B993/4V
GND
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CY7B993V, CY7B994V
Document #: 38-07127 Rev. *J Page 5 of 18
Figure 2. Pin Diagram – 100-Pin BGA
Table 1. Pin Definition [1]
Pin Name I/O Pin Type Pin Description
FBSEL Input LVTTL Feedback Input Select. When LOW, FBKA inputs are selected. When HIGH, the FBKB
inputs are selected. This input has an internal pull-down.
FBKA+, FBKA–
FBKB+, FBKB–
Input LVTTL/
LVDIFF
Feedback Inputs. One pair of inputs selected by the FBSEL is used to feedback the clock
output xQn to the phase detector. The PLL operates such that the rising edges of the
reference and feedback signals are aligned in both phase and frequency. These inputs
can operate as differential PECL or single-ended TTL inputs. When operating as a
single-ended LVTTL input, the complementary input must be left open.
REFA+, REFA–
REFB+, REFB–
Input LVTTL/
LVDIFF
Reference Inputs. These inputs can operate as differential PECL or single-ended TTL
reference inputs to the PLL. When operating as a single-ended LVTTL input, the comple-
mentary input must be left open.
REFSEL Input LVTTL Reference Select Input. The REFSEL input controls how the reference input is
configured. When LOW, it uses the REFA pair as the reference input. When HIGH, it uses
the REFB pair as the reference input. This input has an internal pull-down.
FS Input 3-level
Input
Frequency Select. This input must be set according to the nominal frequency (fNOM) (see
Table 2).
FBF0 Input 3-level
Input
Feedback Output Phase Function Select. This input determines the phase function of
the Feedback bank’s QFA[0:1] outputs (see Ta b l e 4 ).
Note
1. For all three-state inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination
circuitry holds an unconnected input to VCC/2.
Pinouts (continued)
12345678910
A1QB1 1QB0 1QA1 1QA0 QFA0 QFA1 FBKB+ VCCQ FBKA– FBKA+
BVCCN VCCN VCCN VCCN VCCN VCCN VCCQ FBKB– FBSEL REFA+
CGND GND GND GND GND GND VCCQ GND GND REFA–
DLOCK 4F0
(3_level)
3F1
(3_level) GND FBDS1
(3_level)
FBDS0
(3_level)
2F0
(3_level) VCCQ REFSEL REFB–
E4QB1 VCCN 4DS1
(3_level) GND 3F0
(3_level)
4F1
(3_level) GND FS
(3_level) VCCN REFB+
F4QB0 VCCN 3DS1
(3_level) GND GND GND GND FBF0
(3_level) VCCN 2QA0
G4QA1 2DS1
(3_level) VCCQ GND GND GND GND VCCQ 1F0
(3_level) 2QA1
H4QA0 1DS1
(3_level)
1DS0
(3_level) VCCQ GND GND VCCQ
OUTPUT
MODE
(3_level)
FBDIS 2QB0
J
4DS0
(3_level)
3DS0
(3_level)
2DS0
(3_level) DIS1 VCCN VCCN GND INV3
(3_level) DIS3 2QB1
K
2F1
(3_level)
1F1
(3_level) DIS2 VCCN 3QA0 3QA1 GND 3QB0 3QB1 DIS4
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RoboClock
CY7B993V, CY7B994V
Document #: 38-07127 Rev. *J Page 6 of 18
Block Diagram Description
Phase Frequency Detector and Filter
These two blocks accept signals from the REF inputs (REFA+,
REFA–, REFB+, or REFB–) and the FB inputs (FBKA+, FBKA–,
FBKB+, or FBKB–). Correction information is then generated to
control the frequency of the voltage-controlled oscillator (VCO).
These two blocks, along with the VCO, form a PLL that tracks
the incoming REF signal.
The CY7B993V/994V have a flexible REF and FB input scheme.
These inputs allow the use of either differential LVPECL or
single-ended LVTTL inputs. To configure as single-ended LVTTL
inputs, the complementary pin must be left open (internally pulled
to 1.5V). The other input pin can then be used as an LVTTL input.
The REF inputs are also tolerant to hot insertion.
The REF inputs can be changed dynamically. When changing
from one reference input to the other of the same frequency, the
PLL is optimized to ensure that the clock output period is not less
than the calculated system budget (tMIN = tREF (nominal
reference clock period) – tCCJ (cycle-to-cycle jitter) – tPDEV (Max
period deviation)) while reacquiring the lock.
VCO, Control Logic, Divider, and Phase Generator
The VCO accepts analog control inputs from the PLL filter block.
The FS control pin setting determines the nominal operational
frequency range of the divide by one output (fNOM) of the device.
fNOM is directly related to the VCO frequency. There are two
versions: a low-speed device (CY7B993V) where fNOM ranges
from 12 MHz to 100 MHz, and a high-speed device (CY7B994V)
that ranges from 24 MHz to 200 MHz. The FS setting for each
device is shown in Ta b le 2 .
The fNOM frequency is seen on “divide-by-one” outputs. For the
CY7B994V, the upper fNOM range extends from 96 MHz to
200 MHz.
FBDS[0:1] Input 3-level
Input
Feedback Divider Function Select. These inputs determine the function of the QFA0
and QFA1 outputs (see Ta b l e 5 ).
FBDIS Input LVTTL Feedback Disable. This input controls the state of QFA[0:1]. When HIGH, the QFA[0:1]
is disabled to the “HOLD-OFF” or “High Z” state; the disable state is determined by
OUTPUT_MODE. When LOW, the QFA[0:1] is enabled (see Ta b l e 6 ). This input has an
internal pull-down.
[1:4]F[0:1] Input 3-level
Input
Output Phase Function Select. Each pair controls the phase function of the respective
bank of outputs (see Tab l e 4 ).
[1:4]DS[0:1] Input 3-level
Input
Output Divider Function Select. Each pair controls the divider function of the respective
bank of outputs (see Tab l e 5 ).
DIS[1:4] Input LVTTL Output Disable. Each input controls the state of the respective output bank. When HIGH,
the output bank is disabled to the “HOLD-OFF” or “High Z” state; the disable state is
determined by OUTPUT_MODE. When LOW, the [1:4]Q[A:B][0:1] is enabled (see
Table 6). These inputs each have an internal pull-down.
INV3 Input 3-level
Input
Invert Mode. This input only affects Bank 3. When this input is LOW, each matched output
pair becomes complementary (3QA0+, 3QA1–, 3QB0+, 3QB1–). When this input is HIGH,
all four outputs in the same bank are inverted. When this input is MID all four outputs are
non inverting.
LOCK Output LVTTL PLL Lock Indicator. When HIGH, this output indicates the internal PLL is locked to the
reference signal. When LOW, the PLL is attempting to acquire lock.
OUTPUT_MODE Input 3-Level
Input
Output Mode. This pin determines the clock outputs’ disable state. When this input is
HIGH, the clock outputs disable to high impedance (High Z). When this input is LOW, the
clock outputs disable to “HOLD-OFF” mode. When in MID, the device enters factory test
mode.
QFA[0:1] Output LVTTL Clock Feedback Output. This pair of clock outputs is intended to be connected to the
FB input. These outputs have numerous divide options and three choices of phase adjust-
ments. The function is determined by the setting of the FBDS[0:1] pins and FBF0.
[1:4]Q[A:B][0:1] Output LVTTL Clock Output. These outputs provide numerous divide and phase select functions deter-
mined by the [1:4]DS[0:1] and [1:4]F[0:1] inputs.
VCCN PWR Output Buffer Power. Power supply for each output pair.
VCCQ PWR Internal Power. Power supply for the internal circuitry.
GND PWR Device Ground.
Table 1. Pin Definition (continued)[1]
Pin Name I/O Pin Type Pin Description
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CY7B993V, CY7B994V
Document #: 38-07127 Rev. *J Page 7 of 18
Time Unit Definition
Selectable skew is in discrete increments of time unit (tU). The
value of a tU is determined by the FS setting and the maximum
nominal output frequency. The equation to be used to determine
the tU value is as follows:
tU = 1/(fNOM*N)
N is a multiplication factor which is determined by the FS setting.
fNOM is nominal frequency of the device. N is defined in Table 3.
Divide and Phase Select Matrix
The Divide and Phase Select Matrix is comprised of five
independent banks: four banks of clock outputs and one bank for
feedback. Each clock output bank has two pairs of low-skew,
high-fanout output buffers ([1:4]Q[A:B][0:1]), two phase function
select inputs ([1:4]F[0:1]), two divider function selects
([1:4]DS[0:1]), and one output disable (DIS[1:4]).
The feedback bank has one pair of low-skew, high-fanout output
buffers (QFA[0:1]). One of these outputs may connect to the
selected feedback input (FBK[A:B]±). This feedback bank also
has one phase function select input (FBF0), two divider function
selects FSDS[0:1], and one output disable (FBDIS).
The phase capabilities that are chosen by the phase function
select pins are shown in Ta b le 4. The divide capabilities for each
bank are shown in Ta b l e 5 .
Figure 3 illustrates the timing relationship of programmable skew
outputs. All times are measured with respect to REF with the
output used for feedback programmed with 0tU skew. The PLL
naturally aligns the rising edge of the FB input and REF input. If
the output used for feedback is programmed to another skew
position, then the whole tU matrix shifts with respect to REF. For
example, if the output used for feedback is programmed to shift
–8tU, then the whole matrix is shifted forward in time by 8tU. Thus
an output programmed with 8tU of skew is effectively skewed
16tU with respect to REF.
Table 2. Frequency Range Select
FS[2]
CY7B993V CY7B994V
fNOM (MHz) fNOM (MHz)
Min Max Min Max
LOW12262452
MID 24 52 48 100
HIGH 48 100 96 200
Table 3. N Factor Determination
FS
CY7B993V CY7B994V
NfNOM (MHz) at
which tU =1.0 ns NfNOM (MHz) at
which tU =1.0 ns
LOW 64 15.625 32 31.25
MID 32 31.25 16 62.5
HIGH 16 62.5 8 125
Table 4. Output Skew Select Function
Function
Selects Output Skew Function
[1:4]F1
[1:4]F0
and
FBF0
Bank1 Bank2 Bank3 Bank4
Feed-
back
Bank
LOW LOW –4tU–4tU–8tU–8tU–4tU
LOW MID –3tU–3tu –7tU–7tUNA
LOW HIGH –2tU–2tU–6tU–6tUNA
MID LOW –1tU–1tUBK1[3] BK1[3] NA
MID MID 0tU0tU0tU0tU0tu
MID HIGH +1tU+1tUBK2[3] BK2[3] NA
HIGH LOW +2tU+2tU+6tU+6tUNA
HIGH MID +3tU+3tU+7tU+7tUNA
HIGH HIGH +4tU+4tU+8tU+8tU+4tU
Table 5. Output Divider Function
Function
Selects Output Divider Function
[1:4]DS1
and
FBDS1
[1:4]DS0
and
FBDS0
Bank1 Bank2 Bank3 Bank4
Feed-
back
Bank
LOW LOW /1 /1 /1 /1 /1
LOW MID /2 /2 /2 /2 /2
LOW HIGH /3 /3 /3 /3 /3
MID LOW /4 /4 /4 /4 /4
MID MID /5 /5 /5 /5 /5
MID HIGH /6 /6 /6 /6 /6
HIGHLOW/8/8/8/8 /8
HIGH MID /10 /10 /10 /10 /10
HIGH HIGH /12 /12 /12 /12 /12
Notes
2. The level to be set on FS is determined by the “nominal” operating frequency (fNOM) of the VCO and Phase Generator. fNOM always appears on an output when
the output is operating in the undivided mode. The REF and FB are at fNOM when the output connected to FB is undivided.
3. BK1, BK2 denotes following the skew setting of Bank1 and Bank2, respectively.
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CY7B993V, CY7B994V
Document #: 38-07127 Rev. *J Page 8 of 18
Output Disable Description
The feedback Divide and Phase Select Matrix Bank has two
outputs, and each of the four Divide and Phase Select Matrix
Banks have four outputs. The outputs of each bank can be
independently put into a HOLD-OFF or high impedance state.
The combination of the OUTPUT_MODE and DIS[1:4]/FBDIS
inputs determines the clock outputs’ state for each bank. When
the DIS[1:4]/FBDIS is LOW, the outputs of the corresponding
bank is enabled. When the DIS[1:4]/FBDIS is HIGH, the outputs
for that bank is disabled to a high impedance (High Z) or
HOLD-OFF state depending on the OUTPUT_MODE input.
Table 6 defines the disabled output functions.
The HOLD-OFF state is intended to be a power saving feature.
An output bank is disabled to the HOLD-OFF state in a maximum
of six output clock cycles from the time when the disable input
(DIS[1:4]/FBDIS) is HIGH. When disabled to the HOLD-OFF
state, non-inverting outputs are driven to a logic LOW state on
its falling edge. Inverting outputs are driven to a logic HIGH state
on its rising edge. This ensures the output clocks are stopped
without glitch. When a bank of outputs is disabled to High Z state,
the respective bank of outputs go High Z immediately.
Figure 3. Typical Outputs with FB Connected to a Zero-Skew Output[]
t
0– 6t U
t
0– 5t U
t
0– 4t U
t
0– 3t U
t
0– 2t U
t
0– 1t U
t
0
t
0+1t U
t
0
t
0
t
0
t
0
t
0
+2t U
+3t U
+4t U
+5t U
+6t U
FBInput
REFInput
–8tU
–7tU
–6tU
–4tU
–3tU
–2tU
–1tU
0t U
+1t U
+2t U
+3t U
LL
LM
LH
(N/A)
(N/A)
(N/A)
(N/A)
MM
(N/A)
(N/A)
(N/A)
(N/A)
HL
3F[1:0]
4F[1:0]
(N/A)
LL
LM
LH
ML
MH
MM
HM
HH
(N/A)
(N/A)
(N/A)
1F[1:0]
2F[1:0]
+4tU
+6t U
+7t U
+8t U
t
0– 8t U
t
0– 7t U
t
0+7t U
t
0+8t U
HM
HH
HL
(N/A)
(N/A)
Table 6. DIS[1:4]/FBDIS Pin Functionality
OUTPUT_MODE DIS[1:4]/FBDIS Output Mode
HIGH/LOW LOW ENABLED
HIGH HIGH HIGH Z
LOW HIGH HOLD-OFF
MID X FACTORY TEST
Note
4. FB connected to an output selected for “Zero” skew (i.e., FBF0 = MID or XF[1:0] = MID).
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CY7B993V, CY7B994V
Document #: 38-07127 Rev. *J Page 9 of 18
INV3 Pin Function
Bank3 has signal invert capability. The four outputs of Bank3 act
as two pairs of complementary outputs when the INV3 pin is
driven LOW. In complementary output mode, 3QA0 and 3QB0
are non-inverting; 3QA1and 3QB1 are inverting outputs. All four
outputs are inverted when the INV3 pin is driven HIGH. When
the INV3 pin is left in MID, the outputs do not invert. Inversion of
the outputs are independent of the skew and divide functions.
Therefore, clock outputs of Bank3 can be inverted, divided, and
skewed at the same time.
Lock Detect Output Description
The LOCK detect output indicates the lock condition of the
integrated PLL. Lock detection is accomplished by comparing
the phase difference between the reference and feedback
inputs. Phase error is declared when the phase difference
between the two inputs is greater than the specified device
propagation delay limit (tPD).
When in the locked state, after four or more consecutive
feedback clock cycles with phase-errors, the LOCK output is
forced LOW to indicate out-of-lock state.
When in the out-of-lock state, 32 consecutive phase-errorless
feedback clock cycles are required to allow the LOCK output to
indicate lock condition (LOCK = HIGH).
If the feedback clock is removed after LOCK has gone HIGH, a
“Watchdog” circuit is implemented to indicate the out-of-lock
condition after a time-out period by deasserting LOCK LOW. This
time out period is based upon a divided down reference clock.
This assumes that there is activity on the selected REF input. If
there is no activity on the selected REF input then the LOCK
detect pin may not accurately reflect the state of the internal PLL.
Factory Test Mode Description
The device enters factory test mode when the OUTPUT_MODE
is driven to MID. In factory test mode, the device operates with
its internal PLL disconnected; input level supplied to the
reference input is used in place of the PLL output. In TEST mode
the selected FB input(s) must be tied LOW. All functions of the
device are still operational in factory test mode except the
internal PLL and output bank disables. The OUTPUT_MODE
input is designed to be a static input. Dynamically toggling this
input from LOW to HIGH may temporarily cause the device to go
into factory test mode (when passing through the MID state).
Factory Test Reset
When in factory test mode (OUTPUT_MODE = MID), the device
can be reset to a deterministic state by driving the DIS4 input
HIGH. When the DIS4 input is driven HIGH in factory test mode,
all clock outputs go to High Z; after the selected reference clock
pin has five positive transitions, all the internal finite state
machines (FSM) are set to a deterministic state. The determin-
istic state of the state machines depend on the configurations of
the divide selects, skew selects, and frequency select input. All
clock outputs stay in high impedance mode and all FSMs stay in
the deterministic state until DIS4 is deasserted. When DIS4 is
deasserted (with OUTPUT_MODE still at MID), the device
re-enters factory test mode.
Safe Operating Zone
Figure 4 illustrates the operating condition at which the device
does not exceed its allowable maximum junction temperature of
150 °C. Figure 4 shows the maximum number of outputs that can
operate at 185 MHz (with 25 pF load and no air flow) or 200 MHz
(with 10 pF load and no air flow) at various ambient tempera-
tures. At the limit line, all other outputs are configured to
divide-by-two (i.e., operating at 92.5 MHz) or lower frequencies.
The device operates below maximum allowable junction temper-
ature of 150 °C when its configuration (with the specified
constraints) falls within the shaded region (safe operating zone).
Figure 4 shows that at 85 °C, the maximum number of outputs
that can operate at 200 MHz is 6; and at 70 °C, the maximum
number of outputs that can operate at 185 MHz is 16 (with 25 pF
load and 0-m/s air flow).
Figure 4. Typical Safe Operating Zone
Typical Safe Operating Zone
(25-pF Load, 0-m /s air flow )
50
55
60
65
70
75
80
85
90
95
100
24681012141618
Num ber of Outputs at 185 MHz
Ambient Temperature (C)
Safe Operating Zone
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CY7B993V, CY7B994V
Document #: 38-07127 Rev. *J Page 10 of 18
Absolute Maximum Conditions
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.[5]
Storage Temperature ................................. –50C to +125C
Ambient Temperature with
Power Applied ............................................ –40C to +125C
Supply Voltage to Ground Potential................–0.5V to +4.6V
DC Input Voltage ..................................... –0.3V to VCC+0.5V
Output Current into Outputs (LOW)............................. 40 mA
Static Discharge Voltage........................................... > 1100V
(per MIL-STD-883, Method 3015)
Latch up Current................................................... > ±200 mA
Operating Range
Range Ambient Temperature VCC
Commercial 0C to +70C 3.3V 10%
Industrial –40C to +85C 3.3V 10%
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions Min Max Unit
LVTTL Compatible Output Pins (QFA[0:1], [1:4]Q[A:B][0:1], LOCK)
VOH LVTTL HIGH Voltage QFA[0:1], [1:4]Q[A:B][0:1] VCC = Min, IOH = –30 mA 2.4 –V
LOCK IOH = –2 mA, VCC = Min 2.4 – V
VOL LVTTL LOW Voltage QFA[0:1], [1:4]Q[A:B][0:1] VCC = Min, IOL= 30 mA – 0.5 V
LOCK IOL= 2 mA, VCC = Min – 0.5 V
IOZ High impedance State Leakage Current –100 100 A
LVTTL Compatible Input Pins (FBKA±, FBKB±, REFA±, REFB±, FBSEL, REFSEL, FBDIS, DIS[1:4])
VIH LVTTL Input HIGH FBK[A:B]±, REF[A:B]± Min < VCC < Max 2.0 VCC + 0.3 V
REFSEL, FBSEL, FBDIS,
DIS[1:4]
2.0 VCC + 0.3 V
VIL LVTTL Input LOW FBK[A:B]±, REF[A:B]± Min < VCC < Max –0.3 0.8 V
REFSEL, FBSEL, FBDIS, DIS[1:4] –0.3 0.8 V
IILVTTL VIN >VCC FBK[A:B]±, REF[A:B]± VCC = GND, VIN = 3.63V – 100 A
IlH LVTTL Input HIGH
Current
FBK[A:B]±, REF[A:B]± VCC = Max, VIN = VCC – 500 A
REFSEL, FBSEL, FBDIS, DIS[1:4] VIN = VCC – 500 A
IlL LVTTL Input LOW
Current
FBK[A:B]±, REF[A:B]± VCC = Max, VIN = GND –500 – A
REFSEL, FBSEL, FBDIS, DIS[1:4] –500 – A
Three-level Input Pins (FBF0, FBDS[0:1], [1:4]F[0:1], [1:4]DS[0:1], FS, OUTPUT_MODE(TEST))
VIHH Three-level Input HIGH[6] Min < VCC < Max 0.87*VCC –V
VIMM Three-level Input MID[6] Min < VCC < Max 0.47*VCC 0.53*VCC V
VILL Three-level Input LOW[6] Min < VCC < Max – 0.13*VCC V
IIHH Three-level Input
HIGH Current
Three-level input pins excl. FBF0 VIN = VCC – 200 A
FBF0 – 400 A
IIMM Three-level Input
MID Current
Three-level input pins excl. FBF0 VIN = VCC/2 –50 50 A
FBF0 –100 100 A
IILL Three-level Input
LOW Current
Three-level input pins excl. FBF0 VIN = GND –200 – A
FBF0 –400 – A
LVDIFF Input Pins (FBK[A:B]±, REF[A:B]±)
VDIFF Input Differential Voltage 400 VCC mV
VIHHP Highest Input HIGH Voltage 1.0 VCC V
VILLP Lowest Input LOW Voltage GND VCC – 0.4 V
VCOM Common Mode Range (crossing voltage) 0.8 VCC V
Notes
5. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power up. Power supply sequencing is NOT required.
6. These inputs are normally wired to VCC, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold
the unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time
before all data sheet limits are achieved.
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Operating Current
ICCI Internal Operating
Current
CY7B993V VCC = Max, fMAX[7] – 250 mA
CY7B994V – 250 mA
ICCN Output Current
Dissipation/Pair[8] CY7B993V VCC = Max,
CLOAD = 25 pF,
RLOAD = 50 at VCC/2,
fMAX
–40mA
CY7B994V – 50 mA
Electrical Characteristics Over the Operating Range (continued)
Parameter Description Test Conditions Min Max Unit
Capacitance
Parameter Description Test Conditions Min Max Unit
CIN Input Capacitance TA = 25C, f = 1 MHz, VCC = 3.3V – 5 pF
Switching Characteristics Over the Operating Range[9, 10, 11, 12, 13]
Parameter Description CY7B993/4V-2 CY7B993/4V-5 Unit
Min Typ Max Min Typ Max
fIN Clock Input Frequency CY7B993V 12 – 100 12 – 100 MHz
CY7B994V 24 – 200 24 – 200 MHz
fOUT Clock Output Frequency CY7B993V 12 – 100 12 – 100 MHz
CY7B994V 24 – 200 24 – 200 MHz
tSKEWPR Matched-Pair Skew[14, 15] – – 200 – – 200 ps
tSKEWBNK Intrabank Skew[14, 15] – – 200 – – 250 ps
tSKEW0 Output-Output Skew (same frequency and phase, rise to
rise, fall to fall)[14, 15] – – 250 – – 550 ps
tSKEW1 Output-Output Skew (same frequency and phase, other
banks at different frequency, rise to rise, fall to fall)[14, 15] – – 250 – – 650 ps
tSKEW2 Output-Output Skew (invert to nominal of different banks,
compared banks at same frequency, rising edge to falling
edge aligned, other banks at same frequency)[14, 15]
– – 250 – – 700 ps
tSKEW3 Output-Output Skew (all output configurations outside of
tSKEW1and tSKEW2)[14, 15] – – 500 – – 800 ps
tSKEWCPR Complementary Outputs Skew (crossing to crossing,
complementary outputs of the same bank)[14, 15, 16, 17] – – 200 – – 300 ps
tCCJ1-3 Cycle-to-Cycle Jitter (divide by 1 output frequency,
FB = divide by 1, 2, 3)
– 50 150 – 50 150 ps Peak
tCCJ4-12 Cycle-to-Cycle Jitter (divide by 1 output frequency,
FB = divide by 4, 5, 6, 8, 10, 12)
– 50 100 – 50 100 ps Peak
tPD Propagation Delay, REF to FB Rise –250 – 250 –500 – 500 ps
Notes
7. ICCI measurement is performed with Bank1 and FB Bank configured to run at maximum frequency (fNOM = 100 MHz for CY7B993V, fNOM = 200 MHz for
CY7B994V), and all other clock output banks to run at half the maximum frequency. FS and OUTPUT_MODE are asserted to the HIGH state.
8. This is dependent upon frequency and number of outputs of a bank being loaded. The value indicates maximum ICCN at maximum frequency and maximum
load of 25 pF terminated to 50 at VCC/2.
9. This is for non-three level inputs.
10. Assumes 25 pF Max load capacitance up to 185 MHz. At 200 MHz the Max load is 10 pF.
11. Both outputs of pair must be terminated, even if only one is being used.
12. Each package must be properly decoupled.
13. AC parameters are measured at 1.5V unless otherwise indicated.
14. Test Load CL= 25 pF, terminated to VCC/2 with 50up to185 MHz and 10 pF load to 200 MHz.
15. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same phase delay has been selected when
all outputs are loaded with 25 pF and properly terminated up to 185 MHz. At 200 MHz the max load is 10 pF.
16. Complementary output skews are measured at complementary signal pair intersections.
17. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
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Figure 5. AC Test Loads and Waveform[26]
Notes
18. TTB is the window between the earliest and the latest output clocks with respect to the input reference clock across variations in output frequency, supply voltage,
operating temperature, input clock edge rate, and process. The measurements are taken with the AC test load specified and include output-output skew, cycle-cycle
jitter, and dynamic phase error. TTB is equal to or smaller than the maximum specified value at a given frequency.
19. Tested initially and after any design or process changes that may affect these parameters.
20. Rise and fall times are measured between 2.0V and 0.8V.
21. fNOM must be within the frequency range defined by the same FS state.
22. tPWH is measured at 2.0V. tPWL is measured at 0.8V.
23. UI = Unit Interval. Examples: 1 UI is a full period. 0.1UI is 10% of period.
24. Measured at 0.5V deviation from starting voltage.
25. For tOZA minimum, CL = 0 pF. For tOZA maximum, CL= 25 pF to 185 MHz or 10 pF to 200 MHz.
26. These figures are for illustrations only. The actual ATE loads may vary.
TTB Total Timing Budget window (same frequency and phase)[17,
18] – – 500 – – 700 ps
tPDDELTA Propagation Delay difference between two devices[17] – – 200 – – 200 ps
tREFpwh REF input (Pulse Width HIGH)[19] 2.0 – – 2.0 – – ns
tREFpwl REF input (Pulse Width LOW)[19] 2.0 – – 2.0 – – ns
tr/tfOutput Rise/Fall Time[20] 0.15 – 2.0 0.15 – 2.0 ns
tLOCK PLL Lock Time from Power up – – 10 – – 10 ms
tRELOCK1 PLL Relock Time (from same frequency, different phase)
with Stable Power Supply
– 500 – 500 s
tRELOCK2 PLL Relock Time (from different frequency, different phase)
with Stable Power Supply[21] – 1000 – 1000 s
tODCV Output duty cycle deviation from 50%[13] –1.0 1.0 –1.0 1.0 ns
tPWH Output HIGH time deviation from 50%[22] –1.5– 1.5ns
tPWL Output LOW time deviation from 50%[22] –2.0– 2.0ns
tPDEV Period deviation when changing from reference to
reference[23] – 0.025 – 0.025 UI
tOAZ DIS[1:4]/FBDIS HIGH to output high impedance from
ACTIVE[14, 24] 1.0 10 1.0 10 ns
tOAZ DIS[1:4]/FBDIS LOW to output ACTIVE from output high
impedance [24, 25] 0.5 14 0.5 14 ns
Switching Characteristics Over the Operating Range[9, 10, 11, 12, 13] (continued)
Parameter Description CY7B993/4V-2 CY7B993/4V-5 Unit
Min Typ Max Min Typ Max
2.0V
0.8V
3.3V
GND
2.0V
0.8V
3.3V
OUTPUT
(a) LVTTL AC Test Load
<1ns < 1ns
(b) TTL Input Test Waveform
R1
R2
CL
R1 = 910
R2 = 910
CL<30pF
(Includes fixture and
probe capacitance)
R1 = 100
R2 = 100
CL< 25 pF to 185 MHz
For LOCK output only For all other outputs
or 10 pF at 200 MHz
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Document #: 38-07127 Rev. *J Page 13 of 18
AC Timing Diagrams[13]
tPWL
tPWH
REF
FB
Q
Q
INVERTED Q
tREFpwh
tREFpwl
tPD
tCCJ1-3,4-12
COMPLEMENTARY B
COMPLEMENTARY A
tSKEWCPR
tSKEW2
[1:4]Q[A:B]0
[1:4]Q[A:B]1
tSKEWPR
[1:4]QA[0:1]
[1:4]QB[0:1]
tSKEWBNK
tSKEWPR
tSKEWBNK
tSKEW2
Q
Other Q
tSKEW0,1 tSKEW0,1
2.0V
0.8V
QFA0 or
QFA1 or
tODCV
tODCV
REF TO DEVICE 1 and 2
FB DEVICE1
FB DEVICE2
tPD
tPDELTA
tPDELTA
crossing
crossing
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Ordering Code Definitions
Ordering Information
Propagation
Delay (ps)
Max Speed
(MHz) Ordering Code Package Type Operating Range
250 200 CY7B994V-2BBI 100-Ball Thin Ball Grid Array Industrial, –40 °C to 85 °C
250 200 CY7B994V-2BBIT 100-Ball Thin Ball Grid Array -Tape and Reel Industrial, –40 °C to 85 °C
500 200 CY7B994V-5BBC 100-Ball Thin Ball Grid Array Commercial, 0 °C to 70 °C
500 200 CY7B994V-5BBCT 100-Ball Thin Ball Grid Array - Tape and Reel Commercial, 0 °C to 70 °C
Pb-free
250 100 CY7B993V-2AXC 100-Pin Thin Quad Flat Pack Commercial, 0 °C to 70 °C
250 100 CY7B993V-2AXCT 100-Pin Thin Quad Flat Pack - Tape and Reel Commercial, 0 °C to 70 °C
250 100 CY7B993V-2AXI 100-Pin Thin Quad Flat Pack Industrial, –40 °C to 85 °C
250 200 CY7B994V-2AXC 100-Pin Thin Quad Flat Pack Commercial, 0 °C to 70 °C
250 200 CY7B994V-2AXCT 100-Pin Thin Quad Flat Pack - Tape and Reel Commercial, 0 °C to 70 °C
250 200 CY7B994V-2BBXC 100-Ball Thin Ball Grid Array Commercial, 0 °C to 70 °C
250 200 CY7B994V-2BBXCT 100-Ball Thin Ball Grid Array - Tape and Reel Commercial, 0 °C to 70 °C
250 200 CY7B994V-2AXI 100-Pin Thin Quad Flat Pack Industrial, –40 °C to 85 °C
250 200 CY7B994V-2AXIT 100-Pin Thin Quad Flat Pack - Tape and Reel Industrial, –40 °C to 85 °C
250 200 CY7B994V-2BBXI 100-Ball Thin Ball Grid Array Industrial, –40 °C to 85 °C
250 200 CY7B994V-2BBXIT 100-Ball Thin Ball Grid Array -Tape and Reel Industrial, –40 °C to 85 °C
500 100 CY7B993V-5AXC 100-Pin Thin Quad Flat Pack Commercial, 0 °C to 70 °C
500 100 CY7B993V-5AXCT 100-Pin Thin Quad Flat Pack - Tape and Reel Commercial, 0 °C to 70 °C
500 100 CY7B993V-5AXI 100-Pin Thin Quad Flat Pack Industrial, –40 °C to 85 °C
500 100 CY7B993V-5AXIT 100-Pin Thin Quad Flat Pack - Tape and Reel Industrial, –40 °C to 85 °C
500 200 CY7B994V-5AXC 100-Pin Thin Quad Flat Pack Commercial, 0 °C to 70 °C
500 200 CY7B994V-5AXCT 100-Pin Thin Quad Flat Pack - Tape and Reel Commercial, 0 °C to 70 °C
500 200 CY7B994V-5BBXI 100-Ball Thin Ball Grid Array Industrial, –40 °C to 85 °C
500 200 CY7B994V-5BBXIT 100-Ball Thin all Grid Array - Tape and Reel Industrial, –40 °C to 85 °C
500 200 CY7B994V-5AXI 100-Pin Thin Quad Flat Pack Industrial, –40 °C to 85 °C
500 200 CY7B994V-5AXIT 100-Pin Thin Quad Flat Pack - Tape and Reel Industrial, –40 °C to 85 °C
T = Tape and Reel, Blank = Standard
Temperature Range
C = Commercial = 0 °C to 70 °C
I = Industrial = –40 °C to 85 °C
X = Pb-free indicator (blank = leaded)
Package Type: A = Thin Quad Flat Pack; BB = Thin Ball Grid Array
Propagation delay: 2 = 250 ps max; 5 = 500 ps max
Base part number
Company ID: CY = Cypress
7B99XVCY X XX XXT
-
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Document #: 38-07127 Rev. *J Page 17 of 18
Document History Page
Document Title: RoboClock CY7B993V/CY7B994V High speed Multi Phase PLL Clock Buffer
Document Number: 38-07127
Revision ECN Orig. of
Change
Submission
Date Description of Change
** 109957 SZV 12/16/01 Changed from Spec number: 38-00747 to 38-07127
*A 114376 CTK 05/06/02 Added three industrial packages
*B 116570 HWT 09/04/02 Added TTB Features
*C 122794 RBI 12/14/02 Power up requirements to operating conditions information
*D 123694 RGL 03/04/03 Added Min Fout value of 12 MHz for CY7B993V and 24 MHz for CY7B994V to
switching characteristics table
Corrected prop delay limit parameter from (tPDSL,M,H) to tPD in the Lock Detect
Output Description paragraph
*E 128462 RGL 07/29/03 Added clock input frequency (fin) specifications in the switching characteristics
table
*F 391560 RGL See ECN Added Lead-free devices
Added typical values for jitter
*G 2896548 KVM 03/19/10 Changed “Lead-Free” to “Pb-Free” in Ordering Information table.
Removed obsolete part numbers: CY7B993V-2AC, CY7B993V-2ACT,
CY7B993V-2AI, CY7B993V-2AIT, CY7B994V-2AC, CY7B994V-2ACT,
CY7B994V-2BBCT, CY7B994V-2AI, CY7B994V-2AIT, CY7B993V-5AC,
CY7B993V-5ACT, CY7B993V-5AI, CY7B993V-5AIT, CY7B994V-5AC,
CY7B994V-5ACT, CY7B994V-5BBI, CY7B994V-5BBIT, CY7B994V-5AI,
CY7B994V-5AIT and CY7B993V-2AXIT
Added numerical temperature ranges to Ordering Information table
*H 3055192 CXQ 10/11/2010 Removed Part number CY7B994V-5BBXC and CY7B994V-5BBXCT.
Added Ordering Code Definitions.
*I 3076912 CXQ 11/02/2010 Updated Ordering Code Definitions.
*J 3240908 CXQ 04/26/2011 Updated minimum Storage Temperature and 100-pin TQFP package diagram
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Document #: 38-07127 Rev. *J Revised April 26, 2011 Page 18 of 18
TTB™ is a trademark and RoboClock® and PSoC® are the registered trademarks of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the
respective corporations.
RoboClock
CY7B993V, CY7B994V
© Cypress Semiconductor Corporation, 2001-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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