GA05JT01-46
Latest version of this datasheet at: http://www.genesicsemi.com/high-temperature-sic/high-temperature-sic-junction-transistors/
Dec 2014 Pg 1 of 10
Normally – OFF Silicon Carbide
Junction Transistor
Features
Package
• 210°C maximum operating temperature
• Gate Oxide Free SiC Switch
• Exceptional S afe Operati ng Area
• Excellent Gain Linearit y
• Compatible with 5 V TTL Gate Drive
• Temperature Independent S witc hing Performance
• Low Output Capacitance
• Positive Temperature Coef fici ent of RDS,ON
• Suitable for Connecti ng an Anti-parallel Di ode
• RoHS Compliant
TO-46
Advantages
Applications
•
Compatible with Si MOSFET/IGB T Gate Drive ICs
• > 20 µs Short-Circuit Withstand Capability
• Lowest-in-class Conduction Losses
• High Circuit Efficiency
• Minimal Input Signal Distortion
• High Amplifi er Bandwidth
•
Down Hole Oil Drilling
• Geothermal Instrumentation
• Solenoid Actuators
• General Purpose High-T emperature Switchi ng
• Amplifiers
• Solar Inverters
• Switched-Mode Power Supply (SMPS)
• Power Factor Correction (PFC)
Table of Contents
Sectio n I: Absolute Maximum Ratings ...........................................................................................................1
Section II: Static Electrical Characteristics ....................................................................................................2
Section III: Dynamic Electrical Characteristics .............................................................................................2
Sectio n IV : F igures ...........................................................................................................................................3
Sectio n V: Driving the GA05JT01-46...............................................................................................................7
Sectio n VI : Package Dimensions ................................................................................................................. 10
Section VII: SPICE Model Parameters ......................................................................................................... 11
Section I: Absolute Maximum Ratings
Parameter
Symbol
Conditions
Value
Unit
Notes
Drain – Source Voltage
VDS
VGS = 0 V
100
V
Continuous Drain Current
ID
T
J
= 210°C, T
C
= 25°C
5.8
A
Continuous Gate Current
IGM
0.5
A
Turn-Off Safe Operating Area RBSOA TVJ = 210°C, IG = 0.5 A,
Clamped Inductive Lo ad
I
D,max
= 9
@ VDS ≤ VDSmax
A Fig. 18
Short Circuit Safe Operati ng Area SCSOA
T
VJ
= 210°C, I
G
= 0.5 A, V
DS
= 70 V,
Non Repetitive >20 µs
Reverse Gate – Source Voltage
V
SG
30
V
Reverse Drain – Source Voltage
VSD
25
V
Power Dissipation Ptot TJ = 210°C, TC = 25 °C 20 W Fig. 16
Operating and Storage Tem perature Tstg -55 t o 210 °C
D
SG
D
S
G
VDS = 100 V
RDS(ON) = 240 mΩ
ID (Tc = 25°C) = 9 A
hFE (Tc = 25°C) = 110
GA05JT01-46
Latest version of this datasheet at: http://www.genesicsemi.com/high-temperature-sic/high-temperature-sic-junction-transistors/
Dec 2014 Pg 2 of 10
Section II: Static Electrical Characteristics
A: On State
B: Off State
C: Thermal
Section III: Dynamic Electrical Characteristics
A: Capacitance and Gate Charge
B: Switching1
1 – All times are relative to the Drain-Source Voltage VDS
Parameter Symbol Conditions
Value
Unit Notes
Min.
Typical
Max.
Drain – Source On Resistance RDS(ON) ID = 5 A, Tj = 25 °C
ID = 5 A, Tj = 125 °C
ID = 5 A, Tj = 175 °C
ID = 5 A, Tj = 210 °C
240
368
455
580
mΩ Fig. 5
Gate – Source Saturation Voltage VGS,sat ID = 5 A, ID/IG = 40, Tj = 25 °C
ID = 5 A, ID/IG = 30, Tj = 175 °C
3.45
3.22
V Fig. 7
DC Current Gain hFE VDS = 5 V, ID = 5 A, Tj = 25 °C
VDS = 5 V, ID = 5 A, Tj = 125 °C
VDS = 5 V, ID = 5 A, Tj = 175 °C
VDS = 5 V, ID = 5 A, Tj = 210 °C
113
79
72
70
– Fig. 5
Drain Leakage Current IDSS VR = 100 V, VGS = 0 V, Tj = 25 °C
VR = 100 V, VGS = 0 V, Tj = 125 °C
VR = 100 V, VGS = 0 V, Tj = 210 °C
10
50
100
100
500
1000
μA Fig. 6
Gate Leakage Current
ISG
V
SG
= 20 V, T
j
= 25 °C
20
nA
Thermal resistanc e, junct i on - case RthJC
Assumes thermal conduction through
baseplate only actual value may be lower
9.86 °C/W Fig. 19
Parameter Symbol Conditions
Value
Unit Notes
Min.
Typical
Max.
Input Capacitance
Ciss
VGS = 0 V, VD = 100 V, f = 1 MHz
547
pF
Fig. 7
Reverse Transfer/Out put Capac itance
Crss/Coss
V
D
= 100 V,
f
= 1 MHz
45
pF
Fig. 7
Output Capacitance Stored Energy
E
OSS
VGS = 0 V, VD = 100 V, f = 1 MHz
0.2
µJ
Fig. 8
Effective Out put Capacit ance,
time related Coss,tr ID = constant, VGS = 0 V, VDS = 0…70 V 83 pF
Effective Out put Capacit ance,
energy related Coss,er VGS = 0 V, VDS = 0…70 V 67 pF
Gate-Source Charge
QGS
V
GS
= -5…3 V
3.7
nC
Gate-Drain Charge
QGD
VGS = 0 V, VDS = 0…70 V
5.8
nC
Gate Charge - Total
QG
9.5
nC
Internal Gate Resistance – zero bias RG(INT-ZERO)
f = 1 MHz, V
AC
= 50 mV, V
DS
= V
GS
= 0 V ,
T
j
= 210 ºC 14.5 Ω
Internal Gate Resistance – ON
RG(INT-ON)
VGS > 2.5 V, VDS = 0 V, Tj = 210 ºC
0.37
Ω
Turn On Delay Time
td(on)
Tj = 25 ºC, VDS = 70 V,
ID = 5 A, Resistive Load
Refer to Section V: for additional driving
information
8.0
ns
Fall Time, VDS
tf
7.4
ns
Fig. 11, 13
Turn Off Delay Time
td(off)
14.0
ns
Rise Time, V
DS
t
r
4.2
ns
Fig. 12, 14
Turn On Delay Time
t
d(on)
Tj = 210 ºC, VDS = 70 V,
ID = 5 A, Resistive Load
Refer to Section V: for addit io nal driving
information
8.0
ns
Fall Time, V
DS
t
f
7.8
ns
Fig. 11
Turn Off Delay Time
td(off)
28.0
ns
Rise Time, VDS
tr
2.3
ns
Fig. 12
Turn-On Energy Per Pulse
Eon
Tj = 25 ºC, VDS = 70 V,
ID = 5 A, Inducti ve Lo ad
3.6
µJ
Fig. 11, 13
Turn-Off Energy Per Pulse
Eoff
0.4
µJ
Fig. 12, 14
Total Switching Energy
E
tot
4.0
µJ
Turn-On Energy Per Pulse
E
on
Tj = 210 ºC, VDS = 70 V,
ID = 5 A, Inducti ve Lo ad
3.6
µJ
Fig. 11
Turn-Off Energy Per Pulse
Eoff
0.5
µJ
Fig. 12
Total Switching Energy
Etot
4.1
µJ
GA05JT01-46
Latest version of this datasheet at: http://www.genesicsemi.com/high-temperature-sic/high-temperature-sic-junction-transistors/
Dec 2014 Pg 3 of 10
Section IV: Figures
A: Static Characteristics
Figure 1: Typical Ou tpu t Characteristics at 25 °C Figure 2: Typical Output Characteristics at 125 °C
Figure 3: Typical Ou tpu t Characteristics at 210 °C Figure 4: Drain-So u r ce Voltage vs. Gate Curren t
Figure 5: DC Current Gain and Normalized On-Resistance
vs. Temperature
Figure 6: DC Current Gain vs. Drain Current
GA05JT01-46
Latest version of this datasheet at: http://www.genesicsemi.com/high-temperature-sic/high-temperature-sic-junction-transistors/
Dec 2014 Pg 4 of 10
Figure 7: Typical Gate – Source Saturation Voltage Figure 8: Typical Blocking Characteristics
B: Dynamic Characteristics
Figure 9: Input, Output, and Reverse Transfer Capaci tan ce Figure 10: Energy stored in Output Capacitance
Figure 11: Typical Turn On Energy Losses and Switching
Times vs. Temperature
Figure 12: Typical Turn Off Energy Losses and Switching
Times vs. Temperature
GA05JT01-46
Latest version of this datasheet at: http://www.genesicsemi.com/high-temperature-sic/high-temperature-sic-junction-transistors/
Dec 2014 Pg 5 of 10
Figure 13: Typical Turn On Energy Losses and Switching
Times vs. Drain Current
Figure 14: Typical Turn Off Energy Losses and Switching
Times vs. Drain Current
C: Current an d Power Derating
Figure 15: Typical Har d Swi tch ed Device Power Loss vs.
Switching Frequency
2
Figure 16: Power Derating Curve
Figure 17: Forward Bias Safe Operating Area at Tc= 25 oC
Figure 18: Turn-Off Safe Operating Area
2 – Representative values based on device conduction and switching loss. Actual losses will depend on gate drive conditions, device load, and circuit topology.
GA05JT01-46
Latest version of this datasheet at: http://www.genesicsemi.com/high-temperature-sic/high-temperature-sic-junction-transistors/
Dec 2014 Pg 7 of 10
Section V: Driving the GA05JT01-46
The GA05JT01-46 is a c urrent controlled S iC transistor which requi res a posit ive gate c urrent for turn-on and to rem ain in on-state. It may be
driven by different drive topol ogi es depending on the intended appl ication.
Table 1: Estimated Power Consumption and switching frequencies for variou s Gate Drive topologies.
Drive Topology Gate Drive Power
Consumption Switching
Frequency
Simple TTL
High
Low
Constant Current
Medium
Medium
High Speed – Boost Capacitor
Medium
High
High Speed – Boost Inductor Low High
Proportional
Lowest
Medium
Pulsed Power
Medium
N/A
A: Simple TTL Drive
The GA05JT01-46 may be driven by 5 V TTL logic by using a simple current amplification stage. The current amplifier output current must
meet or exceed the steady state gate current, IG,steady, required to operate the GA05JT01-46. An external gate resistor RG, shown in the
Figure 22 topology, sets IG,steady to the required level which is dependent on the SJT drain current ID and DC current gain hFE, RG may be
calculated f rom the equation below. The values of hFE and VGS,sat may be read from Fi gure 6 and Figure 7, respectively. VEC,sat can be taken
from the PNP datasheet, a partial list of high-temperature P NP and NPN transistors options is given below. High-tem perat ure MOSFETs m ay
also be used in the topology.
, =5.0 , () , () (,)
1.5
Figure 21: Simple TTL Gate Drive Topology
Table 2: Partial List of High-Temperature BJTs for TTL Gate D riving
BJT Part Number Type Tj,max (°C)
PHPT60603PY
PNP
175
PHPT60603NY
NPN
175
2N2222
NPN
200
2N6730
PNP
200
2N2905 PNP 200
2N5883
PNP
200
2N5885
NPN
200
SiC SJT
D
S
G
TTL
Gate Signal
0 / 5 V
TTL i/p
inverted
I
G,steady
5 V
PNP
NPN
Inverting
Current
Boost
Stage
0 / 5 V
TTL o/p R
G
GA05JT01-46
Latest version of this datasheet at: http://www.genesicsemi.com/high-temperature-sic/high-temperature-sic-junction-transistors/
Dec 2014 Pg 8 of 10
B: High Speed Driving
For ultra high s peed GA05JT01-46 switchi ng (tr, tf < 20 ns) while mai ntaining low gate drive los ses t he supplied gate current should include a
positive current peak during turn-on, a negative voltage peak duri ng turn-off, and continuous gate current IG to rem ain on.
An SJT is rapidly switched f rom its bl ocking state t o on-state, when the nec essary gate c harge for turn-on, QG, is s upplied by a burst o f high
gate current until the gate-source capacitance, CGS, and gate-drain capacitance, CGD, are fully charged. Ideally, the burst should terminate
when the drain voltage has fal l en to its on-state value in order to avoid unnecessary drive losses. A negative voltage peak is recommended for
the turn-off transition in order t o ensure that t he gate current is not being supplied under high dV/ dt due to the Mill er effect. While s atisfactory
turn off can be achieved with VGS = 0 V, a negative VGS value m ay be used in order to speed up the turn-off transition.
B:1: High Speed, Low Loss Drive with Boost Capacitor
The GA05JT01-46 may be driven using a High Speed, Low Loss Drive with Boost Capacitor topology in which mult iple voltage levels, a gate
resistor, and a gate capacitor are used to provide current peaks at turn-on and turn-of f for fast switching and a continuous gate current while in
on-state. As shown in Figure 23, in thi s topology two gate driver ICs are utili zed. An external gate resistor RG is driven by a low voltage driver
to supply t he continuous gate current t hroughout on-stat e.and a gate capacitor CG is driven at a higher voltage level t o supply a high current
peak at turn-on and turn-off. A 3 kV isolated evaluation gate drive board (GA03IDDJT30-FR4) from GeneSiC Semiconductor utilizing this
topology is commercial l y avail abl e for high and low-side driving, its datas heet provides additi onal details about t his dri ve topology.
Figure 22: High Speed, Low Loss Drive with Boost Capaci tor Topology
B:2: High Speed, Low Loss Drive with Boost Inductor
A High Speed, Low-Loss Driver with B oost Inductor is also capable of driving t he GA05JT01-46 at high-speed. It utilizes a gate drive inductor
instead of a capacitor t o provide the high-current gate current pulses IG,on and IG,off. During operation, inductor L is charged to a specified IG,on
current value then made to discharge IL into the SJT gate pin using logic control of S1, S2, S3, and S4, as shown in Figure 24. After turn on,
while the device rem ai ns on the necess ary steady st ate gate c urrent IG,steady is suppli ed from s ource VCC through RG. Pleas e refer t o the artic le
“A current -sourc e concept for fast and efficient driving of silicon carbide transistors” by Dr. Jacek Rąbkowski for additional information on this
driving topology.3
Figure 23: High Speed, Low-Loss Driver with Boost Inductor Topology
3 – Archives of Electrical Engineering. Volume 62, Issue 2, Pages 333–34 3, IS SN (Print ) 00 04-0746, DOI: 10.2478/aee-2013-0026, June 2013
Gate
RG
CGIG
SiC SJT
D
S
G
VGH
VGL
Gate Signal
SiC SJT D
S
G
L
R
G
V
EE
V
CC
V
CC
V
EE
S
1
S
2
S
3
S
4
GA05JT01-46
Latest version of this datasheet at: http://www.genesicsemi.com/high-temperature-sic/high-temperature-sic-junction-transistors/
Dec 2014 Pg 9 of 10
C: Proportional Gate Current Driving
A proportional gate drive t opology may be beneficial f or applicat ions in which the GA05JT01-46 will operate over a wide range of drain current
conditi ons to lower the gate drive power consumpt ion. A proportional gat e driver relies on instant aneous drain current I D feedback to vary the
steady state gate current IG,steady supplied to the GA05JT01-46.
C:1: Voltage Controlled Proportional Driver
A volt age cont rolled proport ional driver relies on a gat e drive i ntegrat ed c irc uit to det ect the GA05JT01-46 drain-s ource volt age VDS duri ng on-
state to sense I D. The integrated circ uit will then increas e or decrease IG in response to ID. This allows IG and gate drive power consumpt ion to
reduce while ID is low or for IG to increase when ID increases. A high voltage diode connected between the drain and sense protects the
integrated circuit from high-voltage when blocking. A simplified version of this topology is shown in Figure 25. Additional information will be
available in the future at http://www.genesicsemi.com/references/product-notes/.
Figure 24: Simplified Voltage Controlled Proporti onal Driver
C:2: Current Controlled Proportional Driver
The current controlled proportional driver relies on a low-loss transformer in the drain or source path to provide feedback of the
GA05JT01-46 drain c urrent during on-state t o supply IG,steady int o the gate. IG,steady will increase or decreas e in response to ID at a fixed forced
current gain which is set be the turns ratio of the transform er, hforce = ID / IG = N2 / N1. GA05JT01-46 is initially tuned-on using a gate current
pulse supplied into an RC drive circuit to allow ID current to begin flowing. This topology allows IG,steady and the gate drive power consumption to
reduce while ID is relatively low or for IG,steady to increase when ID increases. A simplified version of this topology is shown in Figure 26.
Additional information will be available in the future at http://www.genesicsemi.com/references/product-notes/.
Figure 25: Simplified Current Contr olle d Proportional Driver
SiC SJT
Proportional
Gate Current
Driver D
S
G
Gate Signal
I
G,steady
HV Diode
Sense
Signal Output
SiC SJT D
S
G
N
2
N
2
N
1
N
3
Gate Signal
GA05JT01-46
Latest version of this datasheet at: http://www.genesicsemi.com/high-temperature-sic/high-temperature-sic-junction-transistors/
Dec 2014 Pg 10 of 10
Section VI: Package Dimensions
TO-46 PACKAGE OUTLINE
NOTE
1. CONTROLLED DIMENSION IS INCH. DIMENS ION IN BRACKET IS MILLIMETER.
2. DIMENSIONS DO NOT INCLUDE END FLASH, MOLD FLASH, MATERIAL PROTRUSIONS
Revision History
Date Revision Comments Supersedes
2014/12/12 1 Updated Electrical Charact erist ics
2014/08/25 0 Initi al releas e
Publis hed by
GeneSiC Semiconductor, Inc.
43670 Trade Center Place Suite 155
Dulles, VA 20166
GeneSiC Semiconductor, Inc. reserves right to make changes to the product specific ations and dat a in this document without notice.
GeneSiC disclaims all and any warranty and liabil ity arising out of use or application of any product. No license, express or implied to any
intellect ual propert y rights is granted by this document.
Unless otherwise expressly i ndicated, GeneS i C products are not designed, test ed or authorized f or use in lif e-saving, medical, aircraft
navigation, comm unic ation, air t raffic c ontrol and weapons systems, nor in applications where their failure may result in death, personal
injury and/or property damage.
GA05JT01-46
Dec 2014 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 1 of 1
Section VII: SPICE Model Par amet ers
This is a secure document. Please copy this code from the SPICE model PDF file on our website
(http://www.genesicsemi.com/images/hit_sic/sjt/GA05JT01-46_SPICE.pdf into LTSPICE (version 4)
software for simulation of the GA05JT01-46.
* MODEL OF GeneSiC Semiconductor Inc.
*
* $Revision: 1.0 $
* $Date: 12-DEC-2014 $
*
* GeneSiC Semiconductor Inc.
* 43670 Trade Center Place Ste. 155
* Dulles, VA 20166
*
* COPYRIGHT (C) 2014 GeneSiC Semiconductor Inc.
* ALL RIGHTS RESERVED
*
* These models are provided "AS IS, WHERE IS, AND WITH NO WARRANTY OF ANY KIND
EITHER EXPRESSED OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY
AND FITNESS FOR A
* PARTICULAR PURPOSE."
* Models accurate up to 2 times rated drain current.
*
.model GA05JT01 NPN
+ IS 9.8338E-48
+ ISE 1.0733E-26
+ EG 3.23
+ BF 135
+ BR 0.55
+ IKF 200
+ NF 1
+ NE 2.
+ RB 14.5
+ IRB 0.002
+ RBM 0.37
+ RE 0.01
+ RC 0.23
+ CJC 2.16E-10
+ VJC 3.656
+ MJC 0.4717
+ CJE 5.021E-10
+ VJE 2.95
+ MJE 0.4867
+ XTI 3
+ XTB -1.0
+ TRC1 1.050E-2
+ VCEO 100
+ ICRATING 9
+ MFG GeneSiC_Semiconductor
*
* End of GA05JT01 SPICE Model
