1
©2006 Integrated Device Technology, Inc.
APRIL 2006
DSC 3198/8
I/O
Control
Address
Decoder
64Kx8
MEMORY
ARRAY
7008
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
0L
OE
L
R/W
L
A
15L
A
0L
I/O
0-7L
SEM
L
INT
L
(2)
BUSY
L
(1,2)
R/W
L
CE
0L
OE
L
I/O
Control
Address
Decoder
OE
R
R/W
R
CE
0R
A
15R
A
0R
I/O
0-7R
SEM
R
INT
R
(2)
R
BUSY
(1,2)
M/S
(1)
CE
1L
R/W
R
CE
0R
OE
R
CE
1R
3198 drw 01
1L
CE
1R
CE
16 16
Functional Block Diagram
◆IDT7008 easily expands data bus width to 16 bits or
more using the Master/Slave select when cascading more
than one device
◆M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
◆Interrupt Flag
◆On-chip port arbitration logic
◆Full on-chip hardware support of semaphore signaling
between ports
◆Fully asynchronous operation from either port
◆TTL-compatible, single 5V (±10%) power supply
◆Available in 84-pin PGA, 84-pin PLCC, and a 100-pin TQFP
◆Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Features
◆True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
◆High-speed access
– Commercial: 15/20/25/35/55ns (max.)
– Industrial: 20/55ns (max.)
– Military: 25/35/55ns (max.)
◆Low-power operation
– IDT7008S
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT7008L
Active: 750mW (typ.)
Standby: 1mW (typ.)
◆Dual chip enables allow for depth expansion without
external logic
HIGH-SPEED
64K x 8 DUAL-PORT
STATIC RAM
IDT7008S/L
NOTES:
1. BUSY is an input as a Slave (M/S = VIL) and an output when it is a Master (M/S = VIH).
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
◆Green parts available, see ordering information
2
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
APRIL 03, 2006
Description
The IDT7008 is a high-speed 64K x 8 Dual-Port Static RAM. The
IDT7008 is designed to be used as a stand-alone 512K-bit Dual-Port RAM
or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or-more
word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach
in 16-bit or wider memory system applications results in full-speed, error-
free operation without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by the chip enables (CE0 and CE1) permit the on-chip
circuitry of each port to enter a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 750mW of power.
The IDT7008 is packaged in a 84-pin Ceramic Pin Grid Array (PGA),
a 84-pin Plastic Leadless Chip Carrier (PLCC) and a 100-pin Thin Quad
Flatpack (TQFP).
NOTES:
1. This text does not indicate orientation of the actual part marking.
2. All Vcc pins must be connected to power supply.
3. Package body is approximately 1.15 in x 1.15 in x .17 in.
4. This package code is used to reference the package diagram.
5. All GND pins must be connected to ground supply.
Pin Configurations(1,2,3)
NC
GND
I/O
6R
I/O
5R
I/O
4R
I/O
3R
Vcc
I/O
2R
I/O
0R
I/O
0L
I/O1
L
GND
I/O
2L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
I/O
3L
I/O
1R
I/O
7R
Vcc
OE
L
RIW
L
SEM
L
CE
1L
CE
0L
NC
A
15L
A
14L
A
13L
A
8L
A
7L
A
12L
A
11L
A
10L
A
9L
GND
Vcc
NC
NC
NC
A
14R
NC
GND
NC
GND
NC
SEM
R
CE
1R
CE
0R
OE
R
R/W
R
NC
A
15R
A
12R
A
13R
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
A
4R
A
3R
A
2R
A
1R
A
0R
INT
R
BUSY
R
M/S
BUSY
L
INT
L
NC
A
0L
A
2L
A
3L
A
5L
A
6L
A
1L
A
4L
GND
14
15
16
17
18
19
20
INDEX
21
22
23
24
11109876543218483
33 34 35 36 37 38 39 40 41 42 43 44 45
13
12
25
26
27
28
29
30
31
32 46 47 48 49 50 51 52 53
72
71
70
69
68
67
66
65
64
63
62
73
74
61
60
59
58
57
56
55
54
82 81 80 79 78 77 76 75
IDT7008J
J84-1
(4)
84-Pin PLCC
Top View
(5)
3198 drw 02
GND
GND
,
07/16/04
6.42
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
3 APRIL 03, 2006
NOTES:
1. This text does not indicate orientation of the actual part marking.
2. All Vcc pins must be connected to power supply.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. All GND pins must be connected to ground supply.
Pin Configurations(1,2,3) (con't.)
Index
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
10099 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
IDT7008PF
PN100-1
(4)
100-Pin TQFP
Top View
(5)
NC
GND
GND
OE
R
R/W
R
SEM
R
CE
1R
CE
0R
NC
NC
GND
A
15R
A
12R
A
13R
A
11R
A
10R
A
9R
A
8R
A
7R
NC
NC
A
14R
NC
NC
NC
3198 drw 03
NC
NC
GND
OE
L
R/W
L
SEM
L
CE
1L
CE
0L
NC
NC
NC
Vcc
NC
A
15L
A
14L
A
13L
A
8L
A
7L
NC
NC
NC
A
12L
A
11L
A
10L
A
9L
NC
NC
I/O
6R
I/O
5R
I/O
4R
I/O
3R
Vcc
I/O
2R
I/O
0R
GND
Vcc
I/O
0L
I/O1
L
GND
I/O
2L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
I/O
3L
I/O
1R
I/O
7R
GND
NC
NC
NC
NC
A
6R
A
5R
A
4R
A
3R
A
2R
A
1R
A
0R
INT
R
BUSY
R
M/S
BUSY
L
INT
L
NC
A
0L
GND
A
2L
A
3L
A
5L
A
6L
NC
NC
A
1L
A
4L
,
07/16/04
4
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
APRIL 03, 2006
NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 1.12 in x 1.12 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part marking. Pin Names
Pin Configurations(1,2,3) (con't)
Left P or t Ri ght Por t Nam es
CE
0L
, CE
1L
CE
0R
, CE
1R
Chip Enab le s
R/W
L
R/W
R
Re ad / Wri te E na bl e
OE
L
OE
R
Outp ut Enab le
A
0L
- A
15L
A
0R
- A
15R
Address
I/O
0L
- I/ O
7L
I/O
0R
- I/ O
7R
Data Inp ut/Outp ut
SEM
L
SEM
R
Semaphore Enable
INT
L
INT
R
Inte rrup t Flag
BUSY
L
BUSY
R
Busy Flag
M/SMaster or Slave Select
V
CC
Power
GND Ground
3198 tbl 01
3198 drw 04
63 61 60 58 55 54 51 48 46 45
66
67
69
72
75
76
79
81
82
83
125
7
8
11
10
12
14 17 20
23
26
28 29
32 31
33 35
38
41
43
IDT7008G
G84-3
(4)
84-PIN PGA
TOP VIEW
(5)
ABC DEF GHJK L
42
59 56 49 50 40
25
27
30
36
34
37
39
84346915131618
22 24
19 21
68
71
70
77
80
11
10
09
08
07
06
05
04
03
02
01
64
65
62
57 53 52
47 44
73
74
78
INDEX
NC
GND
OE
L
R/W
L
CE
1L
CE
0L
NC
A
15L
A
14L
A
13L
A
8L
A
7L
A
12L
A
11L
A
10L
A
9L
GND
Vcc
NC
NC
NC
A
14R
GND
NC
GND
NC
CE
1R
CE
0R
OE
R
R/W
R
SEM
R
NC
A
15R
A
12R
A
13R
A
11R
A
10R
A
9R
A
8R
A
7R
I/O
6R
I/O
5R
I/O
4R
I/O
3R
Vcc
I/O
2R
I/O
0R
I/O
0L
I/O1
L
GND
I/O
2L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
I/O
3L
I/O
1R
I/O
7R
A
6R
A
5R
A
4R
A
3R
A
2R
A
1R
A
0R
/S
A
0L
A
2L
A
3L
A
5L
A
6L
A
1L
A
4L
Vcc
GND
NC
INT
R
BUSY
L
L
.
GND
BUSY
R
M
INT NC
GND
SEM
L
07/16/04
6.42
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
5 APRIL 03, 2006
Truth Table I: Chip Enable(1)
Truth Table II: Non-Contention Read/Write Control
NOTES:
1. A0L – A15L ≠ A0R – A15R.
2. Refer to Chip Enable Truth Table.
Truth T able III: Semaphore Read/Write Control(1)
NOTES:
1. There are eight semaphore flags written to via I/O0 and read from all the I/Os (I/O0-I/O7). These eight semaphore flags are addressed by A0-A2.
2. Refer to Chip Enable Truth Table.
NOTES:
1. Chip Enable references are shown above with the actual CE0 and CE1 levels, CE is a reference only.
CE CE
0
CE
1
Mode
LV
IL
V
IH
Port Selected (TTL Active)
< 0. 2V > V
CC
-0.2V Port Se lec te d (CMOS A ctive )
H
V
IH
X Port Deselected (TTL Inactive)
XV
IL
Port Deselected (TTL Inactive)
>V
CC
-0.2V X Port De se lected (CMOS Inactive )
X<
0.2V Port De selected (CMOS Inactive )
3198 tbl 02
Inputs
(1)
Outputs
Mode
CE
(2)
R/WOE SEM I/O0-7
H X X H Hig h-Z Dese le cte d: Powe r-Do wn
LLXHDATA
IN Write to mem ory
LHLHDATA
OUT Re ad memory
X X H X Hig h-Z Outp uts Disab le d
3198 tbl 03
Inputs Outputs
Mode
CE
(2)
R/WOE SEM I/O
0-7
HHLLDATA
OUT
Read Semaphore Flag Data Out
H
↑
XLDATA
IN
Write I/O
0
into Semaphore Flag
LXXL
______
Not Allowed
3198 tbl 04
6
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
APRIL 03, 2006
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. COUT also references CI/O.
Capacitance
(TA = +25°C, f = 1.0mhz) (TQFP Only)
DC Electrical Characteristics Over the Operating
T emperature and Supply Voltage Range(2) (VCC = 5.0V ± 10%)
NOTES:
1. At Vcc < 2.0V, input leakages are undefined.
2. Refer to Chip Enable Truth Table.
Absolute Maximum Ratings(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
Recommended DC Operating
Conditions
NOTES:
1. This is the parameter TA. This is the "instant on" case tempreature.
Maximum Operating Temperature
and Supply Voltage(1)
Symbol Rating Commercial
& Industrial Military Unit
V
TERM
(2)
Te rminal Voltage
with Re sp e ct
to GND
-0.5 to +7.0 -0.5 to +7.0 V
T
BIAS
Temperature
Under Bias -55 to +125 -65 to +135
o
C
T
STG
Storage
Temperature -65 to +150 -65 to +150
o
C
I
OUT
DC Output Curre nt 50 50 mA
3198 tbl 05
Grade Ambient
Temperature GND Vcc
Military -55
O
C to +125
O
C0V 5.0V
+
10%
Commercial 0
O
C to +70
O
C0V 5.0V
+
10%
Industrial -40
O
C to +85
O
C0V 5.0V
+
10%
3198 tbl 06
Symbol Parameter Min. Typ. Max. Unit
V
CC
Sup ply Vo ltag e 4. 5 5.0 5.5 V
GND Ground 0 0 0 V
V
IH
Input High Voltag e 2.2
____
6.0
(2)
V
V
IL
Input Lo w Vo ltag e -0.5
(1)
____
0.8 V
3198 tbl 07
Symbol Parameter Conditions Max. Unit
C
IN
In p ut C apac i ta nce V
IN
= 0V 9 pF
C
OUT
(2)
Outp ut Cap ac itanc e V
OUT
= 0V 10 pF
3198 tb l 08
Symbol Parameter Test Conditions
7008S 7008L
UnitMin. Max. Min. Max.
|I
LI
| Input Leakag e Current
(1)
V
CC
= 5.5V, V
IN
= 0V to V
CC ___
10
___
5µA
|I
LO
|
Output Leakage Curre nt CE = V
IH
, V
OUT
= 0V to V
CC ___
10
___
5µA
V
OL
Output Low Vo ltage I
OL
= 4mA
___
0.4
___
0.4 V
V
OH
Output Hig h Voltag e I
OH
= -4mA 2.4
___
2.4
___
V
3198 tbl 09
6.42
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
7 APRIL 03, 2006
NOTES:
1. 'X' in part numbers indicates power rating (S or L)
2. VCC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ tRC, and using “AC Test Conditions” of input
levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6. Refer to Chip Enable Truth Table.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,6) (VCC = 5.0V ± 10%)
7008X15
Co m 'l On l y 7008X20
Com'l
& I nd
7008X25
Com'l &
Military
Sym bol Parameter Test Conditi on Version Typ.(2) Max. Typ.(2) Max. Typ.(2) Max. Unit
I
CC
Dynami c Op erating
Current
(B o th Ports A ct iv e )
CE = V
IL
, Outputs Disabled
SEM = V
IH
f = f
MAX
(3)
COM'L S
L205
200 365
325 190
180 325
285 180
170 305
265 mA
MIL &
IND S
L
___
___
___
___
___
180
___
335 170
170 345
305
I
SB1
S tandb y Curre nt
(B o th Ports - TTL Le v e l
Inputs)
CE
L
= CE
R
= V
IH
SEM
R
= SEM
L
= V
IH
f = f
MAX
(3)
COM'L S
L65
65 110
90 50
50 90
70 40
40 85
60 mA
MIL &
IND S
L
___
___
___
___
___
50
___
85 40
40 100
80
I
SB2
S tandb y Curre nt
(O ne Po rt - TTL Le ve l
Inputs)
CE
"A"
= V
IL
and CE
"B"
= V
IH
(5)
Active Port Outp uts Disabled,
f=f
MAX
(3)
SEM
R
= SEM
L
= V
IH
COM'L S
L130
130 245
215 115
115 215
185 105
105 200
170 mA
MIL &
IND S
L
___
___
___
___
___
115
___
220 105
105 230
200
I
SB3
Full Stand by Current
(B o th Ports - A ll CMOS
Le vel Inputs )
Bo th Po rts CE
L
and
CE
R
> V
CC
- 0.2V
V
IN
> V
CC
- 0. 2V o r
V
IN
< 0. 2V, f = 0(4)
SEM
R
= SEM
L
> V
CC
- 0.2V
COM'L S
L1.0
0.2 15
51.0
0.2 15
51.0
0.2 15
5mA
MIL &
IND S
L
___
___
___
___
___
0.2
___
10 1.0
0.2 30
10
I
SB4
Full Stand by Current
(O ne Po rt - Al l CM OS
Le vel Inputs )
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V (5)
SEM
R
= SEM
L
> V
CC
- 0.2V
V
IN
> V
CC
- 0. 2V o r V
IN
< 0. 2V
Active Port Outp uts Disabled
f = f
MAX
(3)
COM'L S
L120
120 220
190 110
110 190
160 100
100 170
145 mA
MIL &
IND S
L
___
___
___
___
___
110
___
195 100
100 200
175
3198 tb l 10 a
7008X35
Com 'l &
Military
7008X55
Com'l, Ind
& Mi li tary
Sym bol Parameter Test Condition Version Typ.
(2)
Max. Typ.
(2)
Max. Unit
I
CC
Dynamic Operating Current
(Both Ports Active) CE = V
IL
, Outp uts Disable d
SEM = V
IH
f = f
MAX
(3)
COM'L S
L160
160 295
255 150
150 270
230 mA
MIL &
IND S
L160
160 335
295 150
150 310
270
I
SB1
S tand by Curre nt
(Bo th P orts - TTL Lev e l
Inputs)
CE
L
= CE
R
= V
IH
SEM
R
= SEM
L
= V
IH
COM'L S
L30
30 85
60 20
20 85
60 mA
MIL &
IND S
L20
20 100
80 13
13 100
80
I
SB2
S tand by Curre nt
(One Po rt - TTL Level
Inp uts )
CE
"A"
= V
IL
and CE
"B"
= V
IH
(5)
Active Po rt Outputs Disabled ,
f=f
MAX
(3)
SEM
R
= SEM
L
= V
IH
COM'L S
L95
95 185
155 85
85 165
135 mA
MIL &
IND S
L95
95 215
185 85
85 195
165
I
SB3
Full Standby Current
(B o th P o rts - A ll CM OS
Level Inputs)
Bo th Po rts CE
L
and
CE
R
> V
CC
- 0. 2V
V
IN
> V
CC
- 0. 2V o r
V
IN
< 0.2V, f = 0
(4)
SEM
R
= SEM
L
> V
CC
- 0. 2V
COM'L S
L1.0
0.2 15
51.0
0.2 15
5mA
MIL &
IND S
L1.0
0.2 30
10 1.0
0.2 30
10
I
SB4
Full Standby Current
(One Port - All CMOS
Level Inputs)
CE
"A"
< 0. 2V and
CE
"B"
> V
CC
- 0. 2V
(5)
SEM
R
= SEM
L
> V
CC
- 0. 2V
V
IN
> V
CC
- 0.2V or V
IN
< 0. 2V
Active Po rt Outputs Disabled
f = f
MAX
(3)
COM'L S
L90
90 160
135 80
80 135
110 mA
MIL &
IND S
L90
90 190
165 80
80 175
150
3198 tbl 10 b
8
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
APRIL 03, 2006
Timing of Power-Up Power-Down
Waveform of Read Cycles(5)
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first CE or OE.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
6. Refer to Chip Enable Truth Table.
AC Test Conditions
Figure 2. Output Test Load
(for tLZ, tHZ, tWZ, tOW)
* Including scope and jig.
Figure 1. AC Output Test Load
3198 drw 06
893Ω
30pF
347Ω
5V
DATA
OUT
BUSY
INT
893Ω
5pF*
347Ω
5V
DATA
OUT
3198 drw 05
tRC
R/W
CE
(6)
ADDR
tAA
OE
3198 drw 07
(4)
tACE
(4)
tAOE
(4)
(1)
tLZ tOH
(2)
tHZ
(3,4)
tBDD
DATAOUT
BUSYOUT
VALID DATA
(4)
CE
3198 drw 08
t
PU
I
CC
I
SB
t
PD
(6)
,
Inp ut Puls e Le ve l s
Inp ut Ris e /Fall Ti me s
Inp ut Ti ming Re fe re nc e L ev e ls
Outp ut Re fere nce Le ve ls
Outp ut Lo ad
GND to 3.0V
5ns Max .
1.5V
1.5V
Fi g ure s 1 and 2
3198 tbl 11
6.42
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
9 APRIL 03, 2006
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage(6)
NOTES:
1. Transition is measured 0mV from Low- or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranted by device characterization, but is not production tested.
3. To access RAM, CE= VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE= VIH and SEM = VIL.
5 . The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage
and temperature, the actual tDH will always be smaller than the actual tOW.
6. 'X' in part numbers indicates power rating (s or L).
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(6)
7008X15
Com'l Only 7008X20
Com'l
& I nd
7008X25
Com 'l &
Military
7008X35
Co m' l &
Military
7008X55
Com'l, Ind
& Mi l i tary
UnitSymbol Parameter Min.Max.Min.Max.Min.Max.Min.Max.Min.Max.
RE AD CYCL E
t
RC
Re ad Cycle Ti me 15
____
20
____
25
____
35
____
55
____
ns
t
AA
Addre ss Access Time
____
15
____
20
____
25
____
35
____
55 ns
t
ACE
Chip Enable Acce ss Time
(4)
____
15
____
20
____
25
____
35
____
55 ns
t
AOE
Outp ut E nab le Acc e ss Time
____
10
____
12
____
13
____
20
____
30 ns
t
OH
Output Hold from Address Change 3
____
3
____
3
____
3
____
3
____
ns
t
LZ
Output Low-Z Time
(1,2)
3
____
3
____
3
____
3
____
3
____
ns
t
HZ
Output High-Z Time
(1,2)
____
10
____
12
____
15
____
15
____
25 ns
t
PU
Chip Enable to Po we r Up Time
(2)
0
____
0
____
0
____
0
____
0
____
ns
t
PD
Chip Dis able to Po wer Do wn Tim e
(2)
____
15
____
20
____
25
____
35
____
50 ns
t
SOP
Semaphore Flag Update Pulse (OE or SEM)10
____
10
____
12
____
15
____
15
____
ns
t
SAA
Semaphore Address Access Time
____
15
____
20
____
25
____
35
____
55 ns
3198 tbl 12
Symbol Parameter
7008X15
Co m ' l O nly 7008X20
Com'l
& I nd
7008X25
Com' l &
Military
7008X35
Co m ' l &
Military
7008X55
Com'l, Ind
& Mili tary
UnitMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
WRIT E CYCLE
t
WC
Write Cycle Tim e 15
____
20
____
25
____
35
____
55
____
ns
t
EW
Chip Enab le to End -of-Write
(3)
12
____
15
____
20
____
30
____
45
____
ns
t
AW
Address Valid to End-o f-Write 12
____
15
____
20
____
30
____
45
____
ns
t
AS
Address Set-up Time
(3)
0
____
0
____
0
____
0
____
0
____
ns
t
WP
Write Pulse Width 12
____
15
____
20
____
25
____
40
____
ns
t
WR
Write Rec ove ry Time 0
____
0
____
0
____
0
____
0
____
ns
t
DW
Da ta Val id to E nd - o f-Wr ite 1 0
____
15
____
15
____
15
____
30
____
ns
t
HZ
Outp ut Hig h-Z Time
(1,2)
____
10
____
12
____
15
____
15
____
25 ns
t
DH
Data Ho ld Time
(5)
0
____
0
____
0
____
0
____
0
____
ns
t
WZ
Write Enable to Output in Hig h-Z
(1,2)
____
10
____
12
____
15
____
15
____
25 ns
t
OW
O utput A cti ve from End-o f- W ri te
(1,2,5)
0
____
0
____
0
____
0
____
0
____
ns
t
SWRD
S EM Flag Wri te to R ead Time 5
____
5
____
5
____
5
____
5
____
ns
t
SPS
SEM Flag Contention Wind ow 5
____
5
____
5
____
5
____
5
____
ns
3198 tbl 13
10
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
APRIL 03, 2006
Timing Wa vef orm of Write Cyc le No . 1, R/W Controlled Timing(1,5,8)
Timing Wa v ef orm of Write Cyc le No. 2, CE Controlled Timing(1,5)
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7 . This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure
2).
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be
placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as
the specified tWP.
9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
10. Refer to Chip Enable Truth Table.
R/W
t
WC
t
HZ
t
AW
t
WR
t
AS
t
WP
DATA
OUT
(2)
t
WZ
t
DW
t
DH
t
OW
OE
ADDRESS
DATA
IN
CE or SEM
(6)
(4) (4)
(3)
3198 drw 09
(7)
(7)
(9,10)
3198 drw 10
t
WC
t
AS
t
WR
t
DW
t
DH
ADDRESS
DATA
IN
R/W
t
AW
t
EW
(3)
(2)
(6)
CE or SEM
(9,10)
6.42
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
11 APRIL 03, 2006
Timing Wa veform of Semaphore Read after Write Timing, Either Side(1)
NOTES:
1. DOR = DOL = VIL, CEL = CER = VIH (Refer to Chip Enable Truth Table).
2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A".
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
Timing Waveform of Semaphore Write Contention(1,3,4)
NOTES:
1. CE = VIH for the duration of the above timing (both write and read cycle) (Refer to Chip Enable Truth Table).
2. "DATAOUT VALID" represents all I/O's (I/O0 - I/O15) equal to the semaphore value.
SEM
3198 drw 11
t
AW
t
EW
t
SOP
DATA
0
VALID ADDRESS
t
SAA
R/W
t
WR
t
OH
t
ACE
VALID ADDRESS
DATA
IN
VALID DATA
OUT
VALID
(2)
t
DW
t
WP
t
DH
t
AS
t
SWRD
t
AOE
t
SOP
Read Cycle
Write Cycle
A
0
-A
2
OE
SEM
"A"
3198 drw 12
t
SPS
MATCH
R/W
"A"
MATCH
A
0"A"
-A
2"A"
SIDE "A"
(2)
SEM
"B"
R/W
"B"
A
0"B"
-A
2"B"
SIDE "B"
(2)
12
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
APRIL 03, 2006
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part numbers indicates power rating (S or L).
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(6)
7008X15
Co m'l On ly 7008X20
Com'l
& Ind
7008X25
Com 'l &
Military
7008X35
Co m'l &
Military
7008X55
Co m ' l , In d &
Military
Symbol Parameter Min.Max.Min.Max.Min.Max.Min.Max.Min.Max.Unit
BUSY TIMING (M/S=V
IH
)
t
BAA
BUSY Access Time from Ad dress Match
____
15
____
20
____
20
____
20
____
45 ns
t
BDA
BUSY Disable Time from Address Not Matched
____
15
____
20
____
20
____
20
____
40 ns
t
BAC
BUSY Access Time from Chip Enab le Low
____
15
____
20
____
20
____
20
____
40 ns
t
BDC
BUSY Access Time from Chip Enab le High
____
15
____
17
____
17
____
20
____
35 ns
t
APS
Arb itratio n Priority Se t-up Time
(2)
5
____
5
____
5
____
5
____
5
____
ns
t
BDD
BUSY Dis able to Valid Data
(3)
____
15
____
20
____
25
____
35
____
55 ns
t
WH
Write Ho ld Afte r BUSY
(5)
12
____
15
____
17
____
25
____
25
____
ns
BUSY TIMING (M/S=V
IL
)
t
WB
BUSY I npu t to W r i te
(4)
0
____
0
____
0
____
0
____
0
____
ns
t
WH
Write Ho ld Afte r BUSY
(5)
12
____
15
____
17
____
25
____
25
____
ns
PORT-TO-PORT DELAY TIMING
t
WDD
Write Puls e to Data Delay
(1)
____
30
____
45
____
50
____
60
____
80 ns
t
DDD
Wr ite Da ta Vali d to Re a d Da ta Delay
(1)
____
25
____
30
____
35
____
45
____
65 ns
3198 tbl 14
6.42
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
13 APRIL 03, 2006
3198 drw 13
t
DW
t
APS
ADDR
"A"
t
WC
DATA
OUT "B"
MATCH
t
WP
R/W
"A"
DATA
IN "A"
ADDR
"B"
t
DH
VALID
(1)
MATCH
BUSY
"B"
t
BDA
VALID
t
BDD
t
DDD
(3)
t
WDD
Timing Waveform of Write with Port-to-Port Read and BUSY(2,5) (M/S = VIH)(4)
Timing Waveform of Write with BUSY (M/S = VIL)
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).
2. CEL = CER = VIL, refer to Chip Enable Truth Table.
3. OE = VIL for the reading port.
4. If M/S = VIL (SLAVE), then BUSY is an input (BUSY"A" = VIH and BUSY"B" = "don't care", for this example).
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. tWB is only for the 'Slave' version.
3198 drw 14
R/W
"A"
BUSY
"B"
t
WP
t
WB
(3)
R/W
"B"
t
WH
(1)
(2)
14
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
APRIL 03, 2006
Waveform of BUSY Arbitration Controlled by CE Timing(1,3) (M/S = VIH)
Waveform of BUSY Arbitration Cyc le Controlled by Address Match
Timing(1) (M/S = VIH)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
3. Refer to Chip Enable Truth Table.
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(1)
3198 drw 15
ADDR
"A"
and
"B"
ADDRESSES MATCH
CE
"A"
CE
"B"
BUSY
"B"
t
APS
t
BAC
t
BDC
(2)
3198 drw 16
ADDR
"A"
ADDRESS "N"
ADDR
"B"
BUSY
"B"
t
APS
t
BAA
t
BDA
(2)
MATCHING ADDRESS "N"
7008X15
Com ' l O nly 7008X20
Com'l
& I nd
7008X25
Com ' l &
Military
7008X35
Com'l &
Military
7008X55
Com'l, Ind
& Military
Symbol Parameter Min.Max.Min.Max.Min.Max.Min.Max.Min.Max.Unit
I NTERRUPT TIMI NG
t
AS
Address Se t-up Time 0
____
0
____
0
____
0
____
0
____
ns
t
WR
Write Re c ov e ry Ti me 0
____
0
____
0
____
0
____
0
____
ns
t
INS
Interrup t Se t Ti me
____
15
____
20
____
20
____
25
____
40 ns
t
INR
Interrup t Re s e t Time
____
15
____
20
____
20
____
25
____
40 ns
3198 tb l 15
6.42
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
15 APRIL 03, 2006
Waveform of Interrupt Timing(1,5)
T ruth T able IV — Interrupt Flag(1,4,5)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. See Interrupt Truth Table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
5. Refer to Chip Enable Truth Table.
NOTES:
1. Assumes BUSYL = BUSYR =VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. INTL and INTR must be initialized at power-up.
5. Refer to Chip Enable Truth Table.
3198 drw 17
ADDR
"A"
INTERRUPT SET ADDRESS
CE
"A"
R/W
"A"
t
AS
t
WC
t
WR
(3) (4)
t
INS
(3)
INT
"B"
(2)
3198 drw 18
ADDR
"B"
INTERRUPT CLEAR ADDRESS
CE
"B"
OE
"B"
t
AS
t
RC
(3)
t
INR
(3)
INT
"B"
(2)
Left Port Right Port
FunctionR/W
L
CE OE
L
A
15L
-A
0L
INT
L
R/W
R
CE OE
R
A
15R
-A
0R
INT
R
LLXFFFFXXXX X L
(2)
S e t Ri g h t INT
R
Flag
XXXXXXLLFFFFH
(3
)
Re s et Ri g ht INT
R
Flag
XXX XL
(3)
L L X FF F E X S e t L e ft INT
L
Flag
X L L FFFE H
(2)
X X X X X Res e t L e ft INT
L
Flag
3198 tb l 16
16
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
APRIL 03, 2006
Functional Description
The IDT7008 provides two ports with separate control, address and
I/O pins that permit independent access for reads or writes to any location
in memory. The IDT7008 has an automatic power down feature controlled
by CE. The CE0 and CE1 control the on-chip power down circuitry that
permits the respective port to go into a standby mode when not selected
(CE HIGH). When a port is enabled, access to the entire memory array
is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail box
or message center) is assigned to each port. The left port interrupt flag
(INTL) is asserted when the right port writes to memory location FFFE
(HEX), where a write is defined as CER = R/WR = VIL per the Truth Table.
The left port clears the interrupt through access of address location FFFE
when CEL = OEL = VIL, R/W is a "don't care". Likewise, the right port
interrupt flag (INTR) is asserted when the left port writes to memory location
FFFF (HEX) and to clear the interrupt flag (INTR), the right port must read
the memory location FFFF. The message (8 bits) at FFFE or FFFF is user-
defined since it is an addressable SRAM location. If the interrupt function
is not used, address locations FFFE and FFFF are not used as mail boxes,
but as part of the random access memory. Refer to Table IV for the interrupt
operation.
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT7008 are
push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2 . "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
4. Refer to Chip Enable Truth Table.
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7008.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O7). These eight semaphores are addressed by A0-A2.
3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
Truth Table V —Address BUSY
Arbitration(4)
Truth Table VI — Example of Semaphore Procurement Sequence(1,2,3)
Inputs Outputs
Function
CE
L
CE
R
A
OL
-A
15L
A
OR
-A
15R
BUSY
L
(1) BUSY
R
(1)
X X NO MATCH H H Normal
H X MATCH H H Normal
X H MATCH H H Normal
LL MATCH (2) (2) Write
Inhibit(3)
31 98 tbl 17
Functions D
0
- D
7
Left D
0
- D
7
Right Status
No Action 1 1 Semaphore free
Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token
Rig ht Po rt Writes "0" to Se maphore 0 1 No chang e . Rig ht sid e has no write acce ss to se map hore
Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token
Left Port Writes "0" to Semaphore 1 0 No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token
Left Port Writes "1" to Semaphore 1 1 Semaphore free
Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token
Right Port Writes "1" to Semaphore 1 1 Semaphore free
Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token
Left Port Writes "1" to Semaphore 1 1 Semaphore free
3198 tbl 18
6.42
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
17 APRIL 03, 2006
Busy Logic
Busy Logic provides a hardware indication that both ports of the RAM
have accessed the same location at the same time. It also allows one of the
two accesses to proceed and signals the other side that the RAM is “busy”.
The BUSY pin can then be used to stall the access until the operation on
the other side is completed. If a write operation has been attempted from
the side that receives a BUSY indication, the write signal is gated internally
to prevent the write from proceeding.
The use of BUSY logic is not required or desirable for all applications.
In some cases it may be useful to logically OR the BUSY outputs together
and use any BUSY indication as an interrupt source to flag the event of
an illegal or illogical operation. If the write inhibit function of BUSY logic is
not desirable, the BUSY logic can be disabled by placing the part in slave
mode with the M/S pin. Once in slave mode the BUSY pin operates solely
as a write inhibit input pin. Normal operation can be programmed by tying
the BUSY pins HIGH. If desired, unintended write operations can be
prevented to a port by tying the BUSY pin for that port LOW.
The BUSY outputs on the IDT7008 RAM in master mode, are push-
pull type outputs and do not require pull up resistors to operate. If these
RAMs are being expanded in depth, then the BUSY indication for the
resulting array requires the use of an external AND gate.
result in a glitched internal write inhibit signal and corrupted data in the
slave.
Semaphores
The IDT7008 is an extremely fast Dual-Port 64K x 8 CMOS Static RAM
with an additional 8 address locations dedicated to binary semaphore flags.
These flags allow either processor on the left or right side of the Dual-Port
RAM to claim a privilege over the other processor for functions defined by
the system designer’s software. As an example, the semaphore can be
used by one processor to inhibit the other from accessing a portion of the
Dual-Port RAM or any other shared resource.
The Dual-Port RAM features a fast access time, and both ports are
completely independent of each other. This means that the activity on the
left port in no way slows the access time of the right port. Both ports are
identical in function to standard CMOS Static RAM and can be read from,
or written to, at the same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READ/WRITE of, a non-
semaphore location. Semaphores are protected against such ambiguous
situations and may be used by the system program to avoid any conflicts
in the non-semaphore portion of the Dual-Port RAM. These devices have
an automatic power-down feature controlled by CE, the Dual-Port RAM
enable, and SEM, the semaphore enable. The CE and SEM pins control
on-chip power down circuitry that permits the respective port to go into
standby mode when not selected. This is the condition which is shown in
Truth Table II where CE and SEM are both HIGH.
Systems which can best use the IDT7008 contain multiple processors
or controllers and are typically very high-speed systems which are
software controlled or software intensive. These systems can benefit from
a performance increase offered by the IDT7008s hardware semaphores,
which provide a lockout mechanism without requiring complex program-
ming.
Software handshaking between processors offers the maximum in
system flexibility by permitting shared resources to be allocated in varying
configurations. The IDT7008 does not use its semaphore flags to control
any resources through hardware, thus allowing the system designer total
flexibility in system architecture.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred in
either processor. This can prove to be a major advantage in very high-
speed systems.
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are independent
of the Dual-Port RAM. These latches can be used to pass a flag, or token,
from one port to the other to indicate that a shared resource is in use. The
semaphores provide a hardware assist for a use assignment method
called “Token Passing Allocation.” In this method, the state of a semaphore
latch is used as a token indicating that shared resource is in use. If the left
processor wants to use this resource, it requests the token by setting the
latch. This processor then verifies its success in setting the latch by reading
it. If it was successful, it proceeds to assume control over the shared
resource. If it was not successful in setting the latch, it determines that the
right side processor has set the latch first, has the token and is using the
shared resource. The left processor can then either repeatedly request
that semaphore’s status or remove its request for that semaphore to perform
another task and occasionally attempt again to gain control of the token via
Width Expansion Busy Logic
Master/Slave Arrays
When expanding an IDT7008 RAM array in width while using BUSY
logic, one master part is used to decide which side of the RAMs array will
receive a BUSY indication, and to output that indication. Any number of
slaves to be addressed in the same address range as the master, use
the BUSY signal as a write inhibit signal. Thus on the IDT7008 RAM the
BUSY pin is an output if the part is used as a master (M/S pin = VIH), and
the BUSY pin is an input if the part used as a slave (M/S pin = VIL) as shown
in Figure 3.
If two or more master parts were used when expanding in width, a split
decision could result with one master indicating BUSY on one side of the
array and another master indicating BUSY on one other side of the array.
This would inhibit the write operations from one port for part of a word and
inhibit the write operations from the other port for the other part of the word.
The BUSY arbitration, on a master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write. In
a master/slave array, both address and chip enable must be valid long
enough for a BUSY flag to be output from the master before the actual write
pulse can be initiated with the R/W signal. Failure to observe this timing can
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT7008 RAMs.
3198drw 19
MASTER
Dual Port RAM
BUSY (R)
CE
0
MASTER
Dual Port RAM
BUSY (R)
SLAVE
Dual Port RAM
BUSY (R)
SLAVE
Dual Port RAM
BUSY (R)
CE
1
CE
1
CE
0
A
16
BUSY (L) BUSY (L)
BUSY (L) BUSY (L)
,
18
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
APRIL 03, 2006
the set and test sequence. Once the right side has relinquished the token,
the left side should succeed in gaining control.
The semaphore flags are active LOW. A token is requested by writing
a zero into a semaphore latch and is released when the same side writes
a one to that latch.
The eight semaphore flags reside within the IDT7008 in a separate
memory space from the Dual-Port RAM. This address space is accessed
by placing a LOW input on the SEM pin (which acts as a chip select for the
semaphore flags) and using the other control pins (Address, CE, and
R/W) as they would be used in accessing a standard Static RAM. Each
of the flags has a unique address which can be accessed by either side
through address pins A0 – A2. When accessing the semaphores, none of
the other address pins has any effect.
When writing to a semaphore, only data pin D0 is used. If a LOW level
is written into an unused semaphore location, that flag will be set to a zero
on that side and a one on the other side (see Table VI). That semaphore
can now only be modified by the side showing the zero. When a one is
written into the same location from the same side, the flag will be set to a
one for both sides (unless a semaphore request from the other side is
pending) and then can be written to by both sides. The fact that the side
which is able to write a zero into a semaphore subsequently locks out writes
from the other side is what makes semaphore flags useful in interprocessor
communications. (A thorough discussion on the use of this feature follows
shortly.) A zero written into the same location from the other side will be
stored in the semaphore request latch for that side until the semaphore is
freed by the first side.
When a semaphore flag is read, its value is spread into all data bits so
that a flag that is a one reads as a one in all data bits and a flag containing
a zero reads as all zeros. The read value is latched into one side’s output
register when that side's semaphore select (SEM) and output enable (OE)
signals go active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the other side.
Because of this latch, a repeated read of a semaphore in a test loop must
cause either signal (SEM or OE) to go inactive or the output will never
change.
A sequence WRITE/READ must be used by the semaphore in order
to guarantee that no system level contention will occur. A processor
requests access to shared resources by attempting to write a zero into a
semaphore location. If the semaphore is already in use, the semaphore
request latch will contain a zero, yet the semaphore flag will appear as one,
a fact which the processor will verify by the subsequent read (see Table
VI). As an example, assume a processor writes a zero to the left port at
a free semaphore location. On a subsequent read, the processor will verify
that it has written successfully to that location and will assume control over
the resource in question. Meanwhile, if a processor on the right side
attempts to write a zero to the same semaphore flag it will fail, as will be
verified by the fact that a one will be read from that semaphore on the right
side during subsequent read. Had a sequence of READ/WRITE been
used instead, system contention problems could have occurred during the
gap between the read and write cycles.
It is important to note that a failed semaphore request must be followed
by either repeated reads or by writing a one into the same location. The
reason for this is easily understood by looking at the simple logic diagram
of the semaphore flag in Figure 4. Two semaphore request latches feed
into a semaphore flag. Whichever latch is first to present a zero to the
semaphore flag will force its side of the semaphore flag LOW and the other
side HIGH. This condition will continue until a one is written to the same
semaphore request latch. Should the other side’s semaphore request latch
have been written to a zero in the meantime, the semaphore flag will flip
Figure 4. IDT7008 Semaphore Logic
over to the other side as soon as a one is written into the first side’s request
latch. The second side’s flag will now stay LOW until its semaphore request
latch is written to a one. From this it is easy to understand that, if a semaphore
is requested and the processor which requested it no longer needs the
resource, the entire system can hang up until a one is written into that
semaphore request latch.
The critical case of semaphore timing is when both sides request a
single token by attempting to write a zero into it at the same time. The
semaphore logic is specially designed to resolve this problem. If simulta-
neous requests are made, the logic guarantees that only one side receives
the token. If one side is earlier than the other in making the request, the first
side to make the request will receive the token. If both requests arrive at
the same time, the assignment will be arbitrarily made to one port or the
other.
One caution that should be noted when using semaphores is that
semaphores alone do not guarantee that access to a resource is secure.
As with any powerful programming technique, if semaphores are misused
or misinterpreted, a software error can easily happen.
Initialization of the semaphores is not automatic and must be handled
via the initialization program at power-up. Since any semaphore request
flag which contains a zero must be reset to a one, all semaphores on both
sides should have a one written into them at initialization from both sides
to assure that they will be free when needed.
D
3198 drw 20
0DQ
WRITE D
0
D
Q
WRITE
SEMAPHORE
REQUEST FLIP FLOP SEMAPHORE
REQUEST FLIP FLOP
LPORT RPORT
SEMAPHORE
READ SEMAPHORE
READ
,
6.42
IDT7008S/L
High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
19 APRIL 03, 2006
Ordering Information
NOTES:
1. Industrial temperature range is available on selected TQFP packages in standard power.
For other speeds, packages and powers contact your sales office.
2. Green parts available. For specific speeds, packages and powers contact your local sales office.
A
Power
999
Speed
A
Package
A
Process/
Temperature
Range
Blank
I
(1)
B
Commercial (0°Cto+70°C)
Industrial (-40°Cto+85°C)
Military (-55°Cto+125°C)
Compliant to MIL-PRF-38535 QML
PF
G
J
100-pin TQFP (PN100-1)
108-pin PGA (G108-1)
84-pin PLCC (J84-1)
S
LStandard Power
Low Power
XXXXX
Device
Type
512K (64K x 8) Dual-Port RAM
7008
IDT
3198 drw 21
Commercial Only
Commercial & Industrial
Commercial & Military
Commercial & Military
Commercial, Industrial & Military
Speed in nanoseconds
15
20
25
35
55
A
G
(2)
Green
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-284-2794
San Jose, CA 95138 fax: 408-284-2775 DualPortHelp@idt.com
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Datasheet Document History
01/06/99: Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Pages 2 and 3 Added additional notes to pin configurations
06/03/99: Changed drawing format
11/10/99: Replaced IDT logo
05/08/99: Page 6 Increased storage temperature parameter
Clarified TA parameter
Page 7 DC Electrical paramters–changed wording from "open" to "disabled"
Changed ±200mV to 0mV in notes
07/26/04: Page 2 - 4 Added date revision for pin configurations
Page 6 Updated Capacitance table
Page 7 Added 15ns commercial speed grade to the DC Electrical Characteristics
Added 20ns Industrial temp for low power to DC Electrical Characteristics
Page 9, 12 & 14 Added 15ns commercial speed grade to AC Electrical Characteristics
Added 20ns Industrial temp for low power to AC Electrical Characteristics for Read, Write, Busy and Interrupt
Page 19 Added Commercial for 15ns and Industrial temp to 20ns in ordering information
Page 1 & 19 Replaced old TM logo with new TM logo
04/03/06: Page 1 Added green availability to features
Page 19 Added green indicator to ordering information
