IS61WV20488ALL
IS61/64WV20488BLL
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est version of this device specification before relying on any published information and before placing orders for products.
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Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 1
Rev. C
06/23/2014
2M x 8 HIGH-SPEED CMOS STATIC RAM June 2014
FEATURES
• High-speed access times:
8, 10, 20 ns
• High-performance,low-powerCMOSprocess
• Multiplecenterpowerandgroundpinsfor
greater noise immunity
• EasymemoryexpansionwithCE and OE op-
tions
• CE power-down
• Fullystaticoperation:noclockorrefresh
required
• TTLcompatibleinputsandoutputs
• Singlepowersupply
–
Vdd1.65Vto2.2V(IS61WV20488ALL)
speed = 20ns for Vcc = 1.65V to 2.2V
–
Vdd2.4Vto3.6V(IS61/64WV20488BLL)
speed = 10ns for Vcc = 2.4V to 3.6V
speed = 8ns for Vcc = 3.3V + 5%
• Packagesavailable:
–
48-ball miniBGA (9mm x 11mm)
–44-pinTSOP(TypeII)
• IndustrialandAutomotiveTemperatureSupport
• Lead-freeavailable
DESCRIPTION
TheISSIIS61WV20488ALL/BLLand
IS64WV20488BLLareveryhigh-speed,low
power,2M-wordby8-bitCMOSstaticRAM.The
IS61WV20488ALL/BLLandIS64WV20488BLLarefab-
ricated using ISSI'shigh-performanceCMOStechnol-
ogy.Thishighlyreliableprocesscoupledwithinnovative
circuit design techniques, yields higher performance
and low power consumption devices.
When CE is HIGH (deselected), the device assumes
a standby mode at which the power dissipation can be
reduceddownwithCMOSinputlevels.
TheIS61WV20488ALL/BLLandIS64WV20488BLL
operate from a single power supply and all inputs are
TTL-compatible.
TheIS61WV20488ALL/BLLandIS64WV20488BLLare
availablein48ballminiBGAand44-pinTSOP(TypeII)
packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A20
CE
OE
WE
2M X 8
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VDD
I/O
DATA
CIRCUIT
I/O0-I/O7