1
®
FN6830.0
ISL6174
Dual Low Voltage Circuit Breaker
This IC targets dual voltage hot swap applications across the
+2.5V to +3.3V (nominal) bias supply voltage range with a
second lower voltage rail down to less than 1V where a circuit
breaker response to an over current event is preferred.
It features a charge pump for driving external N-Channel
MOSFETs, accurate programmable circuit breaker current
thresholds and delay output undervoltage monitoring and
reporting and adjustable soft-start.
The circuit breaker current level (ICB) for each rail is set by
two external resistors, and for each rail a delay (tCB) is set by
an external capacitor on the TCB pin. After tCB has expired,
the IC then quickly pulls down the associated GATE(s)
output turning off its external FET(s).
Pinout ISL6174
(28 LD QFN)
TOP VIEW
Features
• Fast Circuit Breaker Quickly Responds to Overcurrent
Fault Conditions
• Less than 1µs Response Time to Dead Short
• Programmable Circuit Breaker Level and De lay
• Two Levels of Overcurrent Detection Provide Fast
Response to Varying Fault Conditions
• Overcurrent Circuit Breaker and Fault Isolation Functions
• Adjustable Circuit Breaker Threshold as Low as 20mV
• Adjustable Voltage Ramp-up for In-Rush Protection
During Turn-On
• Rail Independent Control, Monitoring and Reporting I/O
• Dual Supply Hot Swap Power Distribution Control to <1V
• Charge Pump Allows the Use of N-Channel MOSFETs
• QFN Package:
- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline
- Near Chip Scale Package Footprint, Which Improves
PCB Efficiency and has a Thinner Profile
• Pb-Free (RoHS Compliant)
Applications
• Power Supply Sequencing, Distribution and Control
• Hot Swap / Electronic Circuit Breaker Circuits
Ordering Information
P ART NUMBER
(Note) PART
MARKING
TEMP.
RANGE
(°C) PACKAGE
(Pb-Free) PKG.
DWG. #
ISL6174IRZ* ISL6174 IRZ -40 to +85 28 Ld 5x5 QFN L28.5x5
ISL617XEVAL1Z Evaluation Platform
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on
reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach materials,
and 100% matte tin plate plus anneal (e3 termination finish, which is
RoHS compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free
peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
1
2
3
4
5
6
7
21
20
19
18
17
16
15
28 27 26 25 24 23 22
8 9 10 11 12 13 14
DNC
GND
PGND
CPQ-
BIAS
CPQ+
CPVDD
VS1
UV1
EN1
OCREF
EN2
UV2
VS2
SNS2
VO2
SS2
GT2
FLT2
PG2
TCB2
SNS1
VO1
SS1
GT1
FLT1
PG1
TCB1
V1(IN)
V2(IN)
V1(OUT)
V2(OUT)
RSNS1
RSNS2
RSET1
RSET2
FIGURE 1. TYPICAL APPLICATION
ISL6174
EN1 EN2
BIAS
CPQ+
CPQ-
CPVDD
PGND
GND
TCB1TCB2 VS2 SNS2 GT2 VO2
UV2
PG2
FLT2
FLT1
PG1
SS1
SS2
OCREF
GT1 VO1
UV1
VS1 SNS1
Data Sheet
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
December 19, 2008
2FN6830.0
December 19, 2008
Block Diagram
FIGURE 2. ISL6174 - INTERNAL BLOCK-DIAGRAM OF THE IC - CHANNEL ONE ONLY
QRsns
3K
10K
10K
X2
Charge
Pump
X2
Charge
Pump
Rset
Current
Mirror
POR and
Bandgap
633mV
1.178V
10V(out)
1.178V
4
Iref
Iref
633mV
1.178V
LOAD
FLT1
PG1
CT1
SS1
UV1
OCREF
EN1
RTR/LTCH
CPQ+
CPQ-
CPVDD
BIAS
VS1
SNS1
GT1
VO1
PGND
GND
BIAS
BIAS
10V
CPVDD
CPVDD
OC Timer
&
Logic
Soft Start
Amplifier
Current
Limit
Amplifier 24µA
10µA
10µA
WOC
Comparator
OC
Comparator
-
-
+
+
+
+
-
-
+
+
-
-
Timeout
Comparator
UV
Comparator
Io
Iset
ISL6173
Vin Vo
Rref
Cp
Cv
Css
Rs1
Rs2
Ct
42µA
1k
TCB1
tCB1
ISL6174
3FN6830.0
December 19, 2008
Pinout 28 LEAD QFN
TOP VIEW
1
2
3
4
5
6
7
21
20
19
18
17
16
15
28 27 26 25 24 23 22
8 9 10 11 12 13 14
DNC
GND
PGND
CPQ-
BIAS
CPQ+
CPVDD
VS1
UV1
EN1
OCREF
EN2
UV2
VS2
SNS2
VO2
SS2
GT2
FLT2
PG2
TCB2
SNS1
VO1
SS1
GT1
FLT1
PG1
TCB1
Pin Descriptions
PIN NAME FUNCTION DESCRIPTION
1 SNS1 Current Sense Input This pin is connected to the current sense resistor and control MOSFET Drain node. It provides
current sense signal to the internal comparator in conjunction with VS1 pin.
2 VO1 Output V oltage 1 This pin is connected to the control MOSFET switch source, which connects to a load. Internally , this
voltage is used for SS control.
3 SS1 Soft-Start Duration Set
Input A capacitor from this pin to ground sets the output sof t-start ramp slope. This capacitor is charged by
the internal 10µA current source setting the soft-start ramp. The output voltage ramp tracks the SS
ramp by controlled enhancement of FET gate. Once ramp-up is completed, the capacitor continues
to charge to the CPVDD voltage rail. If common capacitor is used (by tying SS1, SS2 together and
the capacitor to GND from the connection) then both the outputs track each other as they ramp up.
4 GT1 Gate Drive Output Direct connection to the gate of the external N-Channel MOSFET. At turn-on the Gate will charge to
4 X Vbias or 10V(max) from the 24µA source.
5FLT1
Fault Output This is an open drain output. It asserts (pulls low) once the circuit breaker delay (determined by the
TCB timeout cap) has expired. This output is valid for Vbias>1V.
6PG1
Power Good Output This is an active low, open drain output. When asserted (logic zero), it indicates that the voltage on
UV1 pin is more than 643mV (633mV + 10mV hysteresis). This output is valid at VBIAS >1V.
7 TCB1 Circuit Breaker Delay
Timer A capacitor from this pin to ground sets the delay from the onset of an over current event to channel
shutdown (circuit breaker delay). Once the voltage on TCB cap reaches VCT_Vth the GA TE output is
pulled down and the FLT is asserted.
The time for circuit breaker delay (tCB) = (CTCB*1.178)/10µA.
8 DNC Do not connect Do not connect
9 GND Chip Gnd This pin is also internally shorted to the metal tab at the bottom of the IC.
10 PGND Charge pump ground. Both GND and PGND must be tied together externally.
11 CPQ- Charge Pump Capacitor
Low Side Flying cap lowside.
ISL6174
4FN6830.0
December 19, 2008
12 BIAS Chip Bias Voltage Provides IC Bias. Should be 2V to 4V for IC to function normally. This pin can be powered from a
supply voltage that is not being controlled. It is preferable to use 3.3V even if the channels being
controlled are 2.5V or lower because more gate drive voltage will be available to the MOSFETs.
13 CPQ+ Charge Pump Capacitor
High Side Flying cap highside. Use of 0.1µF for 2.5V bias and 0.022µF for 3.3V bias is recommended.
14 CPVDD Charge Pump Output This is the voltage used for some internal pull-ups and bias. Use of 0.47µF (minimum) is
recommended.
15 TCB2 Timer Capacitor Same function as pin 7
16 PG2 Power Good Output Same function as pin 6
17 FLT2 Fault Output Same as pin 5
18 GT2 Gate Drive Output Same as pin 4
19 SS2 Soft-Start Duration Set
Input Same as pin 3
20 VO2 Output Voltage 2 Same as pin 2
21 SNS2 Current Sense Input Same as pin 1
22 VS2 Current Sense
Reference V oltage input for one of the two voltages. Provides a 20µA current source for the ISET series resistor
which sets the voltage to which the sense resistor IR drop is compared.
23 UV2 Undervoltage Monitor
Input This pin is one of the two inputs to the undervoltage comparator. The other input is the 633mV
reference. It is meant to sense the output voltage through a resistor divider. If the output voltage
drops so that the voltage on the UV pin goes below 633mV, PG2 is deasserted.
24 EN2 Enable This is an active low input. When asserted (pulled low), the SS and gate drive are released and the
output voltage gets enabled. When deasserted (pulled high or left floating), the reverse happens.
25 OCREF Ref. Current Adj. Allows adjustment of the reference current through RSET and the internal Circuit Breaker set resistor,
thus setting the thresholds for CR, OC and WOC.
26 EN1 Enable Input Same as pin 24
27 UV1 Undervoltage Monitor
Input Same as pin 23
28 VS1 Current Sense
Reference Same as pin 22
Pin Descriptions (Continued)
PIN NAME FUNCTION DESCRIPTION
ISL6174
5FN6830.0
December 19, 2008
Absolute Maximum Ratings Thermal Information
VBIAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5V
GTx, CPQ+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +12V
ENx, SNSx, PGx, FLTx, VSx, TCBx, UVx,
SSx, CPQ-, CPVDD. . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.5VDC
Output Current . . . . . . . . . . . . . . . . . . . . . . .Short Circuit Protected
Thermal Resistance (Typical, Notes 1 , 4) θJA (°C/W) θJC (°C/W)
5x5 QFN Package . . . . . . . . . . . . . . . . 42 12.5
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
For recommended soldering conditions, see Tech Brief TB389.
(QFN - Leads Only)
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
VBIAS / VIN1 Supply Voltage Range. . . . . . . . . . . +2.25V to +3.63V
Temperature Range (TA) -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. All voltages are relative to GND, unless otherwise specified.
3. 1V (min) on the BIAS pin required for FLT to be valid.
4. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside..
Electrical Specifications VDD = 2.5V to +3.3V, VS = 1V,TA = TJ = -40°C to +85°C, Unless Otherwise Specified. Parameters with MIN
and/or MAX limits are 100% tested at +25°C, unless otherwise specified.
Temperature limits established by characterization and are not production tested.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
CIRCUIT BREAKER CONTROL
ISET Current ISET ROCREF = 14.7kΩ19 20 21 µA
Over Current Comparator Offset Voltage Vio VVS - VSNS with IOUT = 0A -1.25 -0.05 1.25 mV
Circuit Breaker Threshold Voltage VCRVTH VVS - VSNS at FLT assertion,
RISET = 1.0k, ISET = 20µA 19.7 mV
TCB Threshold Voltage VCT_Vth Peak Voltage 1.128 1.178 1.202 V
TCB Charging Current ICT 91011µA
TCB Default Delay TCT TCB = Open 3 µs
GATE DRIVE
GATE Response Time from WOC (Open) pd_woc_open GATE open
100mV of overdrive on the WOC
comparator
3ns
GATE Response Time from WOC
(Loaded) pd_woc_load GATE = 1nF
100mV of overdrive on the WOC
comparator
100 ns
GATE Turn-On Current IGATE_on GATE = 2V, VVS = 2V, VSNS = 2.1V 21 24 27 µA
GATE Turn-Off Current IGATE_off OC or WOC Turn-off Gate Current 100 mA
GATE Voltage VGATE Bias = 2.5V (Figure 5, 6) 8.2 8.8 9.3 V
2.1 < Bias < 2.5 (Figure 5, 6) 7 V
BIAS
Supply Current IBIAS VBIAS = 3.3V 6 9.3 12 mA
POR Rising Threshold VIN_POR_L2H 1.85 2.02 2.12 V
POR Falling Threshold VIN_POR_H2L 1.80 1.98 2.10 V
POR Threshold Hysteresis VIN_POR_HYS 5 33 mV
ISL6174
6FN6830.0
December 19, 2008
I/O
Undervoltage Comparator Falling
Threshold VUV_VTHF 620 635 650 mV
Undervoltage Comparator Hysteresis VUV_HYST 91725mV
EN Rising Threshold PWR_Vth_R VBIAS = 2.5V 1.75 2.04 2.25 V
EN Falling Threshold PWR_Vth_F VBIAS = 2.5V 0.97 1.11 1.20 V
EN Hysteresis PWR_HYST VBIAS = 2.5V 600 905 1175 mV
PG Pull-Down Voltage VOL_PG IPG = 8mA 0.05 0.15 0.3 V
FLT Pull-Down Voltage (Note 3) VOL_FLT IFLT = 8mA 0.05 0.15 0.3 V
Soft-Start Charging Current ISS VSS = 1V 9 10 11 µA
CHARGE PUMP
CPVDD V_CPVDD VBIAS = 3.3V 4.9 5.2 5.5 V
CPVDD V_CPVDD VBIAS = 3.3V
T = +25°C
External User Load = 6mA
5.0 V
Electrical Specifications VDD = 2.5V to +3.3V, VS = 1V,TA = TJ = -40°C to +85°C, Unless Otherwise Specified. Parameters with MIN
and/or MAX limits are 100% tested at +25°C, unless otherwise specified.
Temperature limits established by characterization and are not production tested. (Continued)
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
ISL6174
7FN6830.0
December 19, 2008
Typical Performance Curves (at +25°C unless otherwise specified)
FIGURE 3. I_BIAS vs V_BIAS FIGURE 4. NORMALIZED I BIAS (VBIAS = 3.3V) vs
TEMPERATURE
FIGURE 5. VGATE vs V_BIAS FIGURE 6. VGATE vs V_BIAS
FIGURE 7. GATE VOLTAGE vs TEMPERATURE FIGURE 8. GATE TURN-ON CURRENT vs TEMPERATURE
0
2
4
6
8
10
12
1.0 1.4 1.7 2.0 2.3 2.9 3.2 3.7
V_BIAS(V)
I_BIAS (mA)
CPQ = 22nF, CPVDD = 0.47µF 0.94
0.96
0.98
1.00
1.02
1.04
-40 0 25 70 85 125
TEMPERATURE (°C)
NORMALIZED I BIAS
0.0
2.0
4.0
6.0
8.0
10.0
12.0
2.0 2.4 2.6 3.0 3.2 3.4 3.8
V BIAS (V)
VGATE (V)
CPQ = 22nF, CPVDD = 0.47µF
3.62.2 3.8 4.0
0.0
2.0
4.0
6.0
8.0
10.0
12.0
V BIAS (V)
VGATE (V)
CPQ = 0.1µF, CPVDD = 0.47µF
2.0 2.4 2.6 3.0 3.2 3.4 3.83.62.2 3.8 4.0
8.0
8.2
8.4
8.6
8.8
9.0
9.2
-40 0 25 70 85 125
TEMPERATURE (°C)
VGATE VBIAS = 2.5V (V)
23.0
23.2
23.4
23.6
23.8
24.0
24.2
24.4
24.6
24.8
25.0
-40 0 25 70 85 125
TEMPERATURE (°C)
GATE TURN_ON CURRENT (µA)
ISL6174
8FN6830.0
December 19, 2008
FIGURE 9. CIRCUIT BREAKER GA TE TURN-OFF CURRENT
vs TEMPERATURE FIGURE 10. CIRCUIT BREAKER Vth vs TEMPERATURE
FIGURE 11. UNDERVOLTAGE Vth vs TEMPERATURE FIGURE 12. ISET vs TEMPERATURE
FIGURE 13. WOC RESPONSE vs LOAD CAPACITANCE FIGURE 14. RESPONSE TIME vs IO*RSNS
Typical Performance Curves (at +25°C unless otherwise specified) (Continued)
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
-40 0 25 70 85 125
TEMPERATURE (°C)
NORMALIZED CIRCUTI BREAKER
GATE CURRENT
13
15
17
19
21
23
25
70 85 125
TEMPERATURE (°C)
CIRCUIT BREAKER Vth (mV)
ISET = 20µA, RSET = 1.0k
-40 0 25
620
625
630
635
640
645
650
655
660
-40 0 25 70 85 125
TEMPERATURE (°C)
UNDERVOLTAGE VTH (MV)
RISING VTH
FALLING VTH
19.00
19.20
19.40
19.60
19.80
20.00
20.20
20.40
20.60
20.80
21.00
-40 0 25 70 85 125
TEMPERATURE (°C)
ISET W ROCREF = 14.7k (µA)
1
10
100
1000
10000
CG (nF)
TRESPONSE (ns)
0 0.1 0.47 1.0 4.0 8.7 14 222.0 0
0.5
1.0
1.5
2.0
2.5
3.0
100 150 200 250 300
OC (% OF LIMIT)
RESPONSE TIME (µs)
ISL6174
9FN6830.0
December 19, 2008
Detailed Description of Operation
ISL6174 targets dual voltage hot-swap applications with a
bias of 2.1V to 3.6VDC and the voltages being controlled
down to 0.7VDC. The IC’s main functions are to control start-
up inrush current and provide circuit breaker protection of
the sourcing supplies from OC loads. This is achieved by
enhancing an external MOSFET in a controlled manner. In
order to fully enhance the MOSFET, the IC must provide
adequate gate to source voltage, which is typically 5V or
greater. Hence, the final steady-state voltage on Gate (GT)
pin must be a minimum of 5V above the load voltage. Two
internal charge-pumps allow this to happen.
Controlled Soft-Start
The output voltages are monitored through the Vo pins and
slew up at a rate determined by the capacitors on the
Soft-start (SS) pin, as illustrate d in Figure 15. 24µA of gate
charge current is available. The soft-start amplifier controls
the output voltage by robbing some of the gate charge
current thus slowing down the MOSFET enhancement.
When the load voltage reaches its set level, as sensed by its
respective UV pin through an external resistor divider, the
Power Good (PG) output goes active.
Current Monitoring and Circuit Breaker Protection
The IC monitors the load cu rrent (Io) by sensing the
voltage-drop across the low value current sense resistor
(RSNS), which is connected in series with the MOSFET (as
shown in the “Block Diagram” on page 2), through Sense
(SNS) and voltage set (VS) pins. The latter is through a
resistor, R SET, as shown . Two levels of overcurrent
detection are available to protect against al l possible fault
scenarios. These levels are:
• Timed Circuit Breaker (CB)
• Way Overcurrent Circuit Breaker (WOC)
Each of these modes is described in detail as follows:
TIMED CIR CUIT BREA KER (CB) MOD E
When the load current reaches the Circuit Breaker threshold
(ICB) the ISL6174 enters the timed Circuit Breaker Mode.
When the circuit enters this mode , the OC comp ara tor which
directly looks at the voltage drop across RSNS detects it and
start s the CB delay timer. TCB begins to charge whatever
capacit ance is on tha t pin from an intern al 10µ A current
source. The amount of time it ta kes for this capa cit ance to
charge to ~1.18V (VCT_Vth) set s up the Circuit Breaker delay.
Upon expiration of the CB delay (tCB), the MOSFET gate is
pulled down quickly.
If during and prior to tCB expiring the load current falls below
ICB then in that case, the Circu it Breaker mod e is no longer
active and the IC discharges the CTCB cap.
The Circuit Breaker threshold (ICB) is set by sinking a
reference current, ISET, through RSET by selecting an
appropriate resistor between OCREF and GN D, which set s
IREF. The relationship between IREF an d ISET is IREF =
4*ISET, where IREF = Vocref/Rocref = 1.178/Rocref. IREF
would typically be set at 80µA. This ISET * RSET voltage is
then compared to the voltage across a load current series
sense low ohmic resistor.
Selecting appropriate values for RSET and RSNS such that
when IO = ICR,
WAY OVERCURRENT CIRCUIT BREAKER (WOC) MODE
This mode is designed to handle very fast, very low
impedance shorts on the load side, which can result in very
high di/dt transients on the input current. The WOC circuit
breaker level is typically 200% of the Circuit Breaker limit. In
this mode the comparator, which directly looks at the voltage
drop across RSNS and once the WOC level is exceeded the
IC pulls the gate very quickly to GND, the SSx capacitor is
discharged, FLT is asserted and a new SS sequence is
allowed to begin after ENx recycle.
Q
SS1
GT1
VO1
10V
CPVDD
SOFT-
START
AMPLIFIER
24µA
10µA
+
42µA
VO
0
0
VIN
CPVDD
VIN
+
-
-
FIGURE 15. SOFT-START OPERATION
(EQ. 1)
Io*RSNS = ISET*RSET
ISL6174
10 FN6830.0
December 19, 2008
Bias and Charge Pump Voltages:
The BIAS pin feeds the chip bias voltage directly to the fi rst
of the two internal charge pumps, which are cascaded. The
output of the first charge pump, in addition to feeding the
second charge pump, is accessible on th e CPVDD pin. The
voltage on the CPVDD pin is approximately 5V. It also
provides power to the POR and band-gap circuitry as shown
in the block diagram. A capacitor connected externally
across CPQ+ and CPQ- pins of the IC is the “flying” cap for
the charge-pump.
The second charge-pump is used exclusively to drive the
gates of the MOSFETs during soft start through the 24µA
current sources, one for each channel. The output of this
charge pump is approximately 10V as shown in the “Block
Diagram” on page 2.
Typical Hot-plug Power Up Sequence
1. When power is applied to the IC on the BIAS pin, the first
charge pump immediately powers up.
2. If the BIAS voltage is 2.1V or higher , the IC comes out of
POR. Both SS and TCB caps remain discharged and the
gate (GT) voltage remains low.
3. ENx pin, when pulled below it’s specified threshold,
enables the respective channel.
4. SSx cap begins to charge up through the internal 10µA
current source, the gate (GT) voltage begins to rise and
the corresponding output voltage begins to rise at the
same rate as the SS cap voltage. This is tightly controlled
by the soft-start amplifier shown in the block diagram.
5. SS cap begins to charge but the corresponding TCBx cap
is held discharged.
6. Fault (FLT) remains deasserted (stays high) and the
output voltage continues to rise.
7. If the load current on the output exceeds the set current
limit for grea te r th an the circuit breaker delay, FLT gets
asserted and the channel shutdown occurs.
8. If the voltage on UV pin exceeds 633mV threshold as a
result of rising Vo, the Power Good (PG) output goes
active.
9. At the end of the SS interval, the SS cap voltage reaches
CPVDD and remains charged as long as EN remains
asserted or there is no other fault condition present that
would attempt to pull down the gate.
Applications Information
Selection of External Components
The typical application circuit of Figure 2 has been used for
this section, which provides guidelines to select the external
component values.
MOSFET (Q1)
This component should be selected on the basis of its
rDS(ON) specification at the expected Vgs (gate to source
voltage) and the effective input gate capacitance (Ciss). One
needs to ensure that the combined voltage drop across the
Rsense and rDS(ON) at the desired maximum current
(including transients) will still keep the output voltage above
the minimum required level.
Ciss of the MOSFET influences the overcurrent response
time. It is recommended that a MOSFET with Ciss of less
than 10nF be chosen. Ciss will also have an impact on the
SS cap value selection as seen late r.
Current Sense Resistor (RSNS)
The voltage drop across this resistor, which represents the
load current (Io), is compared against the set threshold of
the Circuit Breaker comparator. The value of this resistor is
determined by how much combined voltage drop is tolerable
between the source and the load. It is recommended that at
least 20mV drop be allowed across this resistor at max load
current. This resistor is expected to carry maximum full load
current indefinitely. Hence, the power rating of this resistor
must be greater than IO(MAX)2*RSNS.
This resistor is typically a low value resistor and hence the
voltage signal appearing across it is also small. In order to
maintain high current sense accuracy, current sense trace
routing is critical. It is recommended that either a four wire
resistor or the routing method as shown in Figure 17 be
used.
Q
Rsns
RSET
VS1
SNS1
GT1
-
+
Io
ISET
VIN VO
+-
+
-
ISL6174
25Ω
WOC
COMPARATOR
GATE
PULLDOWN
CURRENT
FIGURE 16. OC / WOC OPERATION
-
+
3k
OC COMPARATOR
ISL6174
11 FN6830.0
December 19, 2008
Current Set Resistor (RSET)
This resistor sets the threshold for the Circuit Breaker
comparator in conjunction with RSNS. Once RSNS has been
selected, use Equation 1 to calculate RSET. Use 20µA for
ISET in a typical application.
Reference Current Set Resistor (RREF)
This resistor sets up the current i n th e in t ern a l curre nt
source, IREF/4, shown in Figure 2 for the comparators. The
voltage at the OCREF pin is the same as the internal
bandgap reference. The current (IREF) flowing through this
resistor is simply:
IREF = 1.178/RREF
This current, IREF, should be set at 80µA to force 20µA in the
internal current source as shown in Figure 2, becaus e of the
4:1 current mirror. This equates to the resistor value of
14.7k.
Selection of Rs1 and Rs2
These resistors set the UV detect point. The UV comparator
detects the undervoltage condition when it sees the voltage
at UV pin drop below 0.633V. The resistor divider values
should be selected accordingly.
Charge Pump Capacitor Select ion (CP and CV)
CP is the “flying cap” and CV is the smoothing cap of the
charge pump, which operates at 450kHz set internally. The
output resistance of the charge pump, which affects the
regulation, is dependent on the CP value and its ESR,
charge-pump switch resistance, and the frequency and ESR
of the smoothing cap, CV.
It is recommended that CP be kept within 0.022µF
(minimum) to 0.1µF (maximum) range. Only ceramic
capacitors are recommended. Use 0.1µF cap if CPVDD
output is expected to power an external circuit, in which case
the current draw from CPVDD must be kept below 10mA.
CV should at least be 0.47µF (ceramic only). Higher values
may be used if low ripple performance is desired.
Time- out Capacitor Selection (CT)
This capacitor determines the current regulation delay
period. As shown in Figure 2, when the voltage across this
capacitor exceeds 1.178V, the time-out comparator detects it
and the gate voltage is pulled to 0V thus shutting down the
channel. An internal 10µA current source charges this
capacitor . Hence, the value of this capacitor is determined by
Equation 2.
Where,
TOUT = Desired time-out period.
Soft-Start Capacitor Selection (CSS)
The rate of change of voltage (dv/dt) on this capacitor, which
is determined by the internal 10µA current source, is the
same as that on the output load capacitance. Hence, the
value of this capacitor directly controls the inrush current
amplitude during hot swap operation.
Where,
CO = Load Capacitance
IINRUSH = Desired Inrush Current
IINRUSH is the sum of the DC steady-state load current and
the load capacitance charging current. If the DC steady-state
load remains disabled until after the soft-start period expires
(PGx could be used as a load enable signal, for example),
then only the capacitor charging current should be used as
IINRUSH. The Css value should always be more than (1/2.4)
of that of Ciss of the MOSFET to ensure proper soft-start
operation. This is because the Ciss is charged from 24µA
current source, whereas the Css gets charged from a 10µA
current source (Figure 15). In order to make sure both VSS
and VO track during the soft-start, this condition is
necessary.
ISL6174 Evaluation Platform
The ISL617XEVAL1Z is the primary evaluation board for this
IC. For the BOM, schematic and photograph, see the “BOM
for ISL617XEVAL1Z Board and Schematic” on page 15.
The evaluation board has been designed with a typical
application in mind and with accessibility to all the featured
pins to enable a user to understand and verify these features
of the IC. The two circuit breaker levels are programmed to
2.2A for each input rail but they can easily be scaled up or
down by adjusting some component values.
There are two input voltages, one for each channel that are
switched by a dual N-Channel MOSFET (Q1) to the output
connectors.
LOAD CURRENT CARRYING
TRACES
RSNS
CURRENT
SENSE
TRACES
FIGURE 17. RECOMMENDED CURRENT SENSE RESISTOR
PCB LAYOUT
CT10μAT
OUT
•()1.178⁄=(EQ. 2)
CSS CO10μAI
INRUSH
⁄()•=(EQ. 3)
ISL6174
12 FN6830.0
December 19, 2008
Pins SS1 and SS2 of the IC are available as jumper test
points so that they can be tied together to achieve
concurrent tracking between Vo1 and Vo2. Both the EN
inputs must be turned on together to check this function,
jumpers are provide to facilitate this.
Each channel is preloaded with the resistive load that makes
up the UV threshold level. Additional lo ading can be
externally applied as desired.
The internal Circuit Breaker amplifier is fast enough to
respond to very fast di/dt events.
On this board, the timeout capacitor value for side ‘1’ is
0.15µF, which corresponds to a ti meout period of 17.67ms.
The scope shots are taken from the ISL6174EVAL1 to
demonstrate the ISL6174s critical operational waveforms.
Figure 18 illustrates the circuit breaker operation which will
be evident with a slow ramping output current at the
program med 2.2A level, ICB. This mode of operation will be
invoked while the OC event is < ~2X the ICB. as shown in
Figure 19. Characteristic of this operational mode is the TCB
pin ramping to VCB to establish the circuit breaker delay.
The way to confirm WOC mode, is by looking at the TCB pin
waveform. If no ramping is seen prior to GATE turn off, then
WOC is active. The following waveform in Figure 20 shows
WOC operation:
:
Figure 21 is a 200X zoom of a WOC turn-off event and
clearly illustrates the lack of any TCB ramping during this
WOC event.
FIGURE 18. SLOW RAMPING TO 2.2A OC CIRCUIT BREAKER
OPERATION
TCB
Iin
GATE
FIGURE 19. TRANSIENT TO 3.9A OC CIRCUIT BREAKER
OPERATION
GATE
TCB
Iin
FIGURE 20. WOC CIRCUIT BREAKER OPERATION
GATE
TCB
Iin
ISL6174
13 FN6830.0
December 19, 2008
Figure 22 illustrates the GATE response time to an output
short. The time from the input current > 2.2A (ICB) to the
FET gate being pulled down is ~0.6µs.
The previous scope shots illustrate the performance with a
~18ms circuit breaker delay, tCB as determined by the
10.5µF cap on TCB pin. Figure 23 shows the performance
with an open TCB pin for the same amplitude of OC event as
shown in Figure 19. Once again, see the TCB pin ramp
duration and tCB of ~3µs, the intrinsic delay of the IC OC
response.
Dual Voltage Tracking During Turn-on
The ISL6174 Dual Circuit Breaker is also designed to
provide either concurrent or ratiometric tracking of the two
output voltages during turn-on. This capability is critical in
providing power to many high value loads.
The two channels can be forced to track each other by
simply tying their SS pins together and using a common SS
capacitor, CSS. In addition, their EN pins also must be tied
together . T ypical S t art-up waveforms in this mode are shown
in Figure 24, where the common CSS value is 0.066µF.
If one channel experiences a CB event and turns off, the
other one will too.
To achieve ratiometric tracking, the ratio of the two CSS must
match the ratio of the two voltages being handle d. In the
illustrated case in Figure 25, the 1.5V to 3.3V ratio of 1:2.2 is
FIGURE 21. WOC CIRCUIT BREAKER OPERAT ION ZOOM
GATE
TCB
Iin
FIGURE 22. SHORTED OUTPUT GATE RESPONSE
GATE
Iin
FIGURE 23. TRANSIENT TO 3.9A OC CIRCUIT BREAKER
OPERATION with TCB OPEN
GATE
TCB
Iin
FIGURE 24. CONCURRENT TRACKING MODE
VO2
VO1
ISL6174
14
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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For information regarding Intersil Corporation and its products, see www.intersil.com
FN6830.0
December 19, 2008
reflected in the choices of CSS cap values of 0.033µF and
0.072µF. These cap values result in the performance
demonstrated, the variance from a perfect match being the
effect of variance in capacitor values, VSS and ISS.
ISL617XEVAL1Z Photograph
FIGURE 25. RAT I OMETRIC TRACKING MODE
VO1
VO2
ISL6174
15 FN6830.0
December 19, 2008
BOM for ISL617XEVAL1Z Board and Schematic
REFERENCE PART PKG MFG P/N MANUFACTURER
U1 Circuit Breaker IC 28 Ld 5X5
QFN ISL6174DRZ Intersil
Q1 FDS6912A SO8 FDS6912A or equivalent Various
C1 0.033µF 0402 Any
C2 0.15µF 0402 Any
C7 0.47µF Any
C3 2.2µF Any
C5, C9 0.1µF Any
C6, C11 0.022µF 0402 Any
C10 0.22µF 0402 Any
R7, R13 0.01 2512 Any
R1 3.57k 0402 Any
R16 2.55k 0402 Any
R10 14.7k 0402 Any
R3 0 0402 Any
R4, R5, R14, R15 10k 0402 Any
R8, R12 1.1k 0402 Any
R2, R6, R17, R18 1k 0402 Any
J_EN1, EN1-2, J_EN2, JRTR_LTCH, SS1_SS2 Jumper 2 PIN, 0.1” Any
ISL6174
ISL6174
ISL6174
16 FN6830.0
December 19, 2008
ISL6174
Package Outline Drawing
L28.5x5
28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 10/07
located within the zone indicated . Th e pin #1 identifier may be
Unless otherwise specified, tol erance : Decim al ± 0.05
Tiebar shown (if present) is a non-functional feature.
The configuration of the pin #1 identifier is optio nal, but must be
between 0.15mm an d 0.3 0m m from the te rminal tip.
Dimension b applies to the metallized terminal and is measured
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994 .
6.
either a mold or mark feature.
3.
5.
4.
2.
Dimensions are in millimeters.1.
NOTES:
BOTTOM VIEW
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
BOTTOM VIEW
SIDE VIEW
5.00 A
5.00
B
INDEX AREA
PIN 1
6
(4X) 0.15
28X 0.55 ± 0.10 4
A
28X 0.25
M0.10 C B
14 8
4X
0.50
24X
3.0
6
PIN #1 INDEX AREA
3 .10 ± 0 . 15
0 . 90 ± 0.1 BASE PLANE
SEE DETAIL "X"
SEATING PLANE
0.10 C
C
0.08 C
0 . 2 REF
C
0 . 05 MAX.
0 . 00 MIN.
5
( 3. 10)
( 4. 65 TYP )
( 24X 0 . 50)
(28X 0 . 25 )
( 28X 0 . 75)
15
22
21
7
1
28
+ 0.05
- 0.07
