K4M281633F - R(B)E/N/G/C/L/F
December 2003
Mobile-SDRAM
• 3.0V & 3.3V power supply.
• LVCMOS compatible with multiplexed address.
• Four banks operation.
• MRS cycle with address key programs.
-. CAS latency (1, 2 & 3).
-. Burst length (1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
• EMRS cycle with address key programs.
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation.
• Special Function Support.
-. PASR (Partial Array Self Refresh).
-. Internal TCSR (Temperature Compensated Self Refresh)
• DQM for masking.
• Auto refresh.
• 64ms refresh period (4K cycle).
• Commercial Temperature Operation (-25°C ~ 70°C).
• Extended Temperature Operation (-25°C ~ 85°C).
• 54Balls FBGA with 0.8mm ball pitch
( -RXXX : Leaded, -BXXX : Lead Free).
FEATURES The K4M281633F is 134,217,728 bits synchronous high data
rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits,
fabricated with SAMSUNG’s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock and I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst lengths and programmable latencies allow the same
device to be useful for a variety of high band width and high per-
formance memory system applications.
GENERAL DESCRIPTION
ORDERING INFORMATION
- R(B)E/N/G : Normal / Low / Low Power, Extended Temperature(-25°C ~ 85°C)
- R(B)C/L/F : Normal / Low / Low Power, Commercial Temperature(-25°C ~ 70°C)
NOTES :
1. In case of 40MHz Frequency, CL1 can be supported .
2. Samsung are not designed or manufactured for use in a device or system that is used under cir cu mstance in which human life is potentially at stake.
Please contact to the memory mar keting team in samsung electronics when considering the use of a product contained herein for any specific
purpose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use.
Part No. Max Freq. Interface Package
K4M281633F-R(B)E/N/G/C/L/F75 133MHz(CL=3) LVCMOS 54 FBGA
Leaded (Lead Free)
K4M281633F-R(B)E/N/G/C/L/F1H 105MHz(CL=2)
K4M281633F-R(B)E/N/G/C/L/F1L 105MHz(CL=3)*1
2M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA
K4M281633F - R(B)E/N/G/C/L/F
December 2003
Mobile-SDRAM
Bank Select
Data Input Register
2M x 16
2M x 16
Sense AMP
Output BufferI/O Control
Column Decoder
Latency & Burst Length
Programming Register
Address Register
Row Buffer
Refresh Counter
Row Decoder Col. Buffer
LRAS
LCBR
LCKE
LRAS LCBR LWE LDQM
CLK CKE CS RAS CAS WE L(U)DQM
LWE
LDQM
DQi
CLK
ADD
LCAS LWCBR
2M x 16
2M x 16
Timing Register
FUNCTIONAL BLOCK DIAGRAM
K4M281633F - R(B)E/N/G/C/L/F
December 2003
Mobile-SDRAM
54Ball(6x9) FBGA
123789
A VSS DQ15 VSSQ VDDQ DQ0 VDD
B DQ14 DQ13 VDDQ VSSQ DQ2 DQ1
C DQ12 DQ11 VSSQ VDDQ DQ4 DQ3
D DQ10 DQ9 VDDQ VSSQ DQ6 DQ5
E DQ8 NC VSS VDD LDQM DQ7
F UDQM CLK CKE CAS RAS WE
G NC A11 A9 BA0 BA1 CS
HA8A7A6A0A1A10
J VSS A5 A4 A3 A2 VDD
Pin Name Pin Function
CLK System Clock
CS Chip Select
CKE Clock Enable
A0 ~ A11 Address
BA0 ~ BA1Bank Select Address
RAS Row Address Strobe
CAS Column Address Strobe
WE Write Enable
L(U)DQM Data Input/Output Mask
DQ0 ~ 15 Data Input/Output
VDD/VSS Power Supply/Ground
VDDQ/VSSQ Data Output Power/Ground
Symbol Min Typ Max
A 0.90 0.95 1.00
A10.30 0.35 0.40
E - 8.00 -
E1-6.40-
D - 8.00 -
D1-6.40-
e - 0.80 -
b 0.40 0.45 0.50
z--0.10
[Unit:mm]
Package Dimension and Pin Configuration
< Top View*2 >< Bottom View*1 >
< Top View*2 >
*2: Top View
521634897
F
E
D
C
B
J
H
G
A
e
D
D/2
D1
E1
EE/2
A
A1
z
b
Encapsulant
Max. 0.20
*1: Bottom View
#A1 Ball Origin Indicator
K4M281633F
SEC Week
XXXX
K4M281633F - R(B)E/N/G/C/L/F
December 2003
Mobile-SDRAM
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 to 85°C for Extended, -25 to 70°C for Commercial)
NOTES :
1. VIH (max) = 5.3V AC.The overshoot voltage duration is 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns.
3. Any input 0V VIN VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs.
4. Dout is disabled, 0V VOUT VDDQ.
Parameter Symbol Min Typ Max Unit Note
Supply voltage VDD 2.7 3.0 3.6 V
VDDQ 2.7 3.0 3.6 V
Input logic high voltage VIH 2.2 3.0 VDDQ + 0.3 V 1
Input logic low voltage VIL -0.3 00.5 V 2
Output logic high voltage VOH 2.4 - - V IOH = -2mA
Output logic low voltage VOL - - 0.4 V IOL = 2mA
Input leakage current ILI -10 -10 uA 3
CAPACITANCE (VDD = 3.0V & 3.3V, TA = 23°C, f = 1MHz, VREF =0.9V ± 50 mV)
Pin Symbol Min Max Unit Note
Clock CCLK 2.0 4.0 pF
RAS, CAS, WE, CS, CKE, DQM CIN 2.0 4.0 pF
Address CADD 2.0 4.0 pF
DQ0 ~ DQ15 COUT 3.0 6.0 pF
ABSOLUTE MAXIMUM RATINGS
NOTES:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Parameter Symbol Value Unit
Voltage on any pin relative to Vss VIN, VOUT -1.0 ~ 4.6 V
Voltage on VDD supply relative to Vss VDD, VDDQ -1.0 ~ 4.6 V
Storage temperature TSTG -55 ~ +150 °C
Power dissipation PD1.0 W
Short circuit current IOS 50 mA
K4M281633F - R(B)E/N/G/C/L/F
December 2003
Mobile-SDRAM
DC CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 to 85°C for Extended, -25 to 70°C for Commercial)
NOTES:
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Internal TCSR can be supported.
In commercial Temp : Max 40°C/Max 70°C, In extended Temp : Max 40°C/Max 85°C
4. K4M281633F-R(B)E/C**
5. K4M281633F-R(B)N/L**
6. K4M281633F-R(B)G/F**
7. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ).
Parameter Symbol Test Condition Version Unit Note
-75 -1H -1L
Operating Current
(One Bank Active) ICC1 Burst length = 1
tRC tRC(min)
IO = 0 mA 80 75 75 mA 1
Precharge S t andby Current in
power-down mode ICC2PCKE VIL(max), tCC = 10ns 0.5 mA
ICC2PS CKE & CLK VIL(max), tCC = 0.5
Precharge Standby Current
in non power-down mode
ICC2NCKE VIH(min), CS VIH(min), tCC = 10ns
Input signals are changed one time during 20ns 12
mA
ICC2NS CKE VIH(min), CLK VIL(max), tCC =
Input signals are stable 10
Active Standby Current
in power-down mode ICC3PCKE VIL(max), tCC = 10ns 7mA
ICC3PS CKE & CLK VIL(max), tCC = 7
Active Standby Current
in non power-down mode
(One Bank Active)
ICC3NCKE VIH(min), CS VIH(min), tCC = 10ns
Input signals are changed one time during 20ns 23 mA
ICC3NS CKE VIH(min), CLK VIL(max), tCC =
Input signals are stable 20 mA
Operating Current
(Burst Mode) ICC4
IO = 0 mA
Page burst
4Banks Activated
tCCD = 2CLKs
130 130 110 mA 1
Refresh Current ICC5 tRC tRC(min) 170 170 155 mA 2
Self Refresh Current ICC6CKE 0.2V
-E/C 700 uA 4
-N/L 500 5
-G/F
Internal TCSR Max 40 Max 85/70 °C 3
Full Array 350 500
uA 6
1/2 of Full Array 300 400
1/4 of Full Array 280 360
K4M281633F - R(B)E/N/G/C/L/F
December 2003
Mobile-SDRAM
AC OPERATING TEST CONDITIONS(VDD = 2.7V3.6V, TA = -25 to 85°C for Extended, -25 to 70°C for Commercial)
Parameter Value Unit
AC input levels (Vih/Vil) 2.4 / 0.4 V
Input timing measurement reference level 0.5 x VDDQ V
Input rise and fall time tr/tf = 1/1 ns
Output timing measurement reference level 0.5 x VDDQ V
Output load condition See Figure 2
VDDQ
1200
870
Output
30pF
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Vtt=0.5 x VDDQ
50
Output
30pF
Z0=50
Figure 2. AC Output Load Circuit
Figure 1. DC Output Load Circuit
K4M281633F - R(B)E/N/G/C/L/F
December 2003
Mobile-SDRAM
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
NOTES :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to t he next
higher integer.
2. Minimum delay is required to complete write.
3. Minimum tRDL=2CLK and tDAL(= tRDL + tRP) is required to complete both of last data write command(tRDL) and precharge command(tRP).
4. All parts allow every cycle column address change.
5. In case of row precharge interrupt, auto precharge and read burst stop.
Parameter Symbol Version Unit Note
-75 -1H -1L
Row active to row active delay tRRD(min) 15 19 19 ns 1
RAS to CAS delay tRCD(min) 19 19 24 ns 1
Row precharge time tRP(min) 19 19 24 ns 1
Row active time tRAS(min) 45 50 60 ns 1
tRAS(max) 100 us
Row cycle time tRC(min) 64 69 84 ns 1
Last data in to row precharge tRDL(min) 2CLK 2
Last data in to Active delay tDAL(min) tRDL + tRP - 3
Last data in to new col. address delay tCDL(min) 1CLK 2
Last data in to burst stop tBDL(min) 1CLK 2
Col. address to col. address delay tCCD(min) 1CLK 4
Number of valid output data CAS latency=3 2
ea 5
Number of valid output data CAS latency=2 1
Number of valid output data CAS latency=1 0
K4M281633F - R(B)E/N/G/C/L/F
December 2003
Mobile-SDRAM
AC CHARACTERISTICS(AC operating conditions unless otherwise noted)
NOTES :
1. Parameters depend on pr ogrammed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Parameter Symbol -75 -1H -1L Unit Note
Min Max Min Max Min Max
CLK cycle time CAS latency=3 tCC 7.5
1000
9.5
1000
9.5
1000 ns 1
CLK cycle time CAS latency=2 tCC 9.5 9.5 12
CLK cycle time CAS latency=1 tCC - - 25
CLK to valid output delay CAS latency=3 tSAC 5.4 7 7
ns 1,2
CLK to valid output delay CAS latency=2 tSAC 778
CLK to valid output delay CAS latency=1 tSAC - - 20
Output data hold time CAS latency=3 tOH 2.5 2.5 2.5
ns 2
Output data hold time CAS latency=2 tOH 2.5 2.5 2.5
Output data hold time CAS latency=1 tOH - - 2.5
CLK high pulse width tCH 2.5 3.0 3.0 ns 3
CLK low pulse width tCL 2.5 3.0 3.0 ns 3
Input setup time tSS 2.0 2.5 2.5 ns 3
Input hold time tSH 1.0 1.5 1.5 ns 3
CLK to output in Low-Z tSLZ 111ns 2
CLK to output in Hi-Z
CAS latency=3
tSHZ
5.4 7 7
ns
CAS latency=2 778
CAS latency=1 - - 20
K4M281633F - R(B)E/N/G/C/L/F
December 2003
Mobile-SDRAM
SIMPLIFIED TRUTH TABLE
(V=Valid, X=Dont Care, H=Logic High, L=Logic Low)
NOTES :
1. OP Code : Operand Code
A0 ~ A11 & BA0 ~ BA1 : Program keys. (@MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are the same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
Partial self refresh can be issued only after setting partial se lf refresh mode of EMRS.
4. BA0 ~ BA1 : Bank select addresses.
5. During burst read or write with auto pr echarge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at the positive g oing edge of CLK masks t he data-in at that same CLK in writ e operation (W rite DQM late ncy is 0), but in read operation,
it makes the data-out Hi -Z state after 2 CLK cycles. (Read DQM latency is 2).
COMMAND CKEn-1 CKEn CS RAS CAS WE DQM BA0,1 A10/AP A11,
A9 ~ A0 Note
Register Mode Register Set H X L L L L X OP CODE 1, 2
Refresh
Auto Refresh HHL L L H X X 3
Self
Refresh
Entry L 3
Exit L H L H H H X X 3
H X X X 3
Bank Active & Row Addr. H X L L H H X V Row Address
Read &
Column Address Auto Precharge Disable H X L H L H X V LColumn
Address
(A0~A8)
4
Auto Precharge Enable H4, 5
Write &
Column Address Auto Precharge Disable H X L H L L X V LColumn
Address
(A0~A8)
4
Auto Precharge Enable H4, 5
Burst Stop H X L H H L X X 6
Precharge Bank Selection H X L L H L X V L X
All Banks X H
Clock Suspend or
Active Power Down Entry H L H X X X XXL V V V
Exit L H X X X X X
Precharge Power Down
Mode
Entry H L H X X X X
X
L H H H
Exit L H H X X X X
L V V V
DQM H X V X 7
No Operation Command H X H X X X X X
L H H H
K4M281633F - R(B)E/N/G/C/L/F
December 2003
Mobile-SDRAM
Register Programmed with Extended MRS
Address BA1 BA0 A11 ~ A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Function Mode Select RFU*1 DS RFU*1 PASR
Normal MRS Mode
Test Mode CAS Latency Burst Type Burst Length
A8 A7 Type A6 A5 A4 Latency A3 Type A2 A1 A0 BT=0 BT=1
0 0 Mode Register Set 000Reserved 0Sequential 000 1 1
0 1 Reserved 001 11Interleave 001 2 2
1 0 Reserved 010 2Mode Select 010 4 4
1 1 Reserved 011 3BA1 BA0 Mode 011 8 8
Write Burst Length 100Reserved
0 0 Setting
for Nor-
mal MRS
100Reserved Reserved
A9 Length 101Reserved 101Reserved Reserved
0Burst 110Reserved 110Reserved Reserved
1Single Bit 111Reserved 111Full Page Reserved
Full Page Length x16 : 128Mb(512)
Register Programmed with Normal MRS
Address BA0 ~ BA1 A11 ~ A10/AP A9*2 A8 A7 A6 A5 A4 A3 A2 A1 A0
Function "0" Setting for
Normal MRS RFU*1 W.B.L Test Mode CAS Latency BT Burst Length
A. MODE REGISTER FIELD TABLE TO PROGRAM MODES
NOTES:
1.RFU(Reserved for future use) should stay "0" during MRS cycle.
2.If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled.
Mode Select Driver Strength PASR
BA1 BA0 Mode A6 A5 Driver Strength A2 A1 A0 Size of Refreshed Array
0 0 Normal MRS 0 0 Full 000 Full Array
0 1 Reserved 0 1 1/2 001 1/2 of Full Array
1 0 EMRS for Mobile SDRAM 1 0 Reserved 010 1/4 of Full Array
1 1 Reserved 1 1 Reserved 011 Reserved
Reserved Address 100 Reserved
A11~A10/AP A9 A8 A7 A4 A3 101 Reserved
0 0 0 0 0 0 110 Reserved
111 Reserved
EMRS for PASR(Partial Array Self Ref.) & DS(Driver Strength)
K4M281633F - R(B)E/N/G/C/L/F
December 2003
Mobile-SDRAM
1. In order to save power consumption, Mobile SDRAM has PASR option.
2. Mobile SDRAM supports 3 kinds of PASR in self refresh mode :Full Array, 1/2 of Full Array and 1/4 of Full Array.
BA1=0
Partial Self Refresh Area
1. Apply power and attempt to maintain CKE at a high state and all other inputs may be undefined.
- Apply VDD before or at the same time as VDDQ.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
6. Issue a extended mode register set command to define DS or PASR operating type of the device after normal MRS.
EMRS cycle is not mandatory and the EMRS command needs to be issued only when DS or PASR is used.
The default state without EMRS command issued is full driver strength and full array refreshed.
The device is now ready for the o peration selected by EMRS.
For operating with DS or PASR , set DS or PASR mode in EMRS setting stage.
In order to adjust another mode in the state of DS or PASR mode, additional EMRS set is required but power up sequence is not
needed again at this time. In that case, all banks have to be in idle state prior to adjusting EMRS set.
BA0=0 BA1=0
BA0=0 BA1=0
BA0=1
BA1=1
BA0=1
BA1=1
BA0=0
BA1=1
BA0=1
BA1=1
BA0=0
BA1=0
BA0=1
BA1=0
BA0=0 BA1=0
BA0=1
BA1=1
BA0=1
BA1=1
BA0=0
Partial Array Self Refresh
B. POWER UP SEQUENCE
Internal Temperature Compensated Self Refresh (TCSR)
1. In order to save power consumption, Mobile-DRAM includes the internal temperature sensor and control units to control the self
refresh cycle automatically according to the two temperature range : Max 40 °C and Max 85 °C(for Extended), Max 70 °C(for
Commercial).
2. If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored.
Temperature Range
Self Refresh Current (Icc6)
Unit
- E/C - N/L - G/F
Full Array 1/2 of Full Array 1/4 of Full Array
Max 85/70 °C700 500 500 400 360 uA
Max 40 °C350 300 280
- Full Array - 1/2 Array - 1/4 Array
K4M281633F - R(B)E/N/G/C/L/F
December 2003
Mobile-SDRAM
C. BURST SEQUENCE
1. BURST LENGTH = 4
Initial Address Sequential Interleave
A1 A0
0 0 0 1 2 3 0 1 2 3
0 1 1 2 3 0 1 0 3 2
1 0 2 3 0 1 2 3 0 1
1 1 3 0 1 2 3 2 1 0
2. BURST LENGTH = 8
Initial Address Sequential Interleave
A2 A1 A0
0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6
0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5
0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4
1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3
1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2
1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1
1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0