CY7C0430V-100BGC - Cypress Semiconductor Corp.

PRELIMINARY

3.3V 64K x 18

Synchronous QuadPort™ Static RAM

CY7C0430V

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600

S eptember 12, 2000

Features

• True f our- ported memory cells which al low simult a-

neous access of the same m emo ry location

• Synchronous Pipelined device

—64K x 18 organiz ati on

• Pipelined output mode allows fast 133-MHz operation

• High Ba ndwi dth up t o 10 Gbps (133 M Hz x 18 bi t s wide

x 4 ports)

• 0.25-micron CMOS for optimum speed/po wer

• High-speed clock to data access 4.7 ns (max.)

• 3.3V Low operating power

—Active = 750 mA (maximum)

—Standby = 5 mA (maximum)

• C ounter wrap-around control

—Internal mask register controls counter wrap-around

—Counter-Interrupt flags to indicate wrap-around

• C ounter re adback on address lines

• M ask register re adback on address lines

• Interrupt flags for messag e passi ng

• M aster reset f or all po rts

• Wi dth and depth expansi on capabilities

• Dual Chip Enables on all ports for easy depth expansion

• Separate upper-byte and lower- byt e controls on all

ports

• 272- BGA pac ka ge (27 mm x 27 m m 1.27-mm ball pitch )

• C om me rcial and Indust ri al temperat ure ranges

• IEEE 1149.1 JTAG boundar y scan

Notes:

1. Port 1 Control Logic Block is detailed on page 2.

2. Port 2, Port 3, and Port 4 Logic Blocks are similar to Port 1 Logic Blocks.

Port-1

Control

Logic

Port 1

Counter/

Mask Reg/

Address

Decode

Port 1

I/O

Top Level Logic Block Diagra m

RAM

Array

Port 1 Operation-Control Logic Bl ocks[1]

Port 2 Logi c Blocks[2]

Port 4 Logic Blocks[2]

Port 3 Logic Blocks[2]

CNTLDP1

CNTINCP1

CNTRSTP1

MKLDP1

CNTINTP1

MKRDP1

CNTRDP1

INTP1

CE1P1

CE0P1

R/WP1

OEP1

UBP1

LBP1

I/O0P1- I/O17P1

A0P1–A15P1 16

TMS

TCK

TDI TDO

MRST Reset

Logic

JTAG

Controller

CLKP1

Port 1

Port 2 Port 3

Port 4

For the most recent information, visit the Cypress web site at www.cypress.com

CY7C0430V

PRELIMINARY

Addr.

Read

Back

P ort 1 Operation- Control Logic Bloc k Diagram:

R/WP1

CE0P1

CE1P1

LBP1

OEP1

UBP1

I/O9P1–I/O17P1

I/O0P1–I/O8P1

I/O

Control

Counter/

A0P1–A15P1

CLKP1

CNTLDP1

CNTINCP1

CNTRSTP1

MKLDP1

CNTINTP1

MKRDP1

Mask Regi ster

Port-1

Port 1

RAM

Array

Port 1

Port 2

Port 4

Port 3

Address

Readback

Port 1

CNTRDP1

Port 1

Address

Decode

Port 1

Interrupt

Logic

R/WP1

CE0P1

CE1P1

OEP1 INTP1

CLKP1

MRST

Priority

Decision

Logic

MRST

(Address Readback is independent of CEs)

LBP1

UBP1

CY7C0430V

PRELIMINARY

Functional Description

The CY7C0430V is a 1-Mb synchronous true fo ur-por t Static

RAM. This is a high-speed, low-power 3.3V CMOS four-port

static RAM. Four por ts are provided, per mitting independent,

sim ul taneous acces s f or reads f r om an y locat ion i n memory. A

particular port can write to a certain loc ation while ot her ports

are reading that location simultaneously. The result of wri ting

to the same locat ion by more than one port at the same time

is undefined. Registers on control, address and data lines al-

low for mini m al set-up and hold time.

Data is register ed for decreas ed cycle time . Clock to data v alid

tCD2 = 4.7 ns. Each port contains a burst counte r on the input

address register. After exter nally loading the counter with the

initial address the counter will self -increment the address in-

ternal ly (more details to follow). The int ernal write pul se widt h

is independent of the duration of the R/W input signal. The

internal writ e pulse is self -timed to all ow the shortest possible

cycle times .

A HIGH on CE0 or LOW on CE1 f or one clock cycle wil l power

down the internal circuitry to reduce the static power consump-

tion. One cycle is required with chip enabl es asserted to reac-

tivate the outputs.

Count er enable inpu ts are pr ovided to stall the oper ation of the

addr ess input and uti lize the i nternal addres s generate d by the

internal counter for fast interleaved memory applications. A

por t's burst counter is loaded with an exter nal address when

the port's Count er Load pin (CNTLD) is asserted LOW. When

the port's Counter Increment pin (CNTINC) is asserted, the

address counter wil l increment on each subsequent LOW-to-

HIGH transition of that port's clock signal. This will read/ write

one word from/into each successive address location until

CNTINC is deasserted. The counter can address the entire

memory array and will loop back to the star t. Counter Reset

(CNTRST) is used to reset the burst counter . A count er-mask

regist er is used to control the counter wrap. The counter and

mask register operations are described in more details in the

following sections.

The counter or mask register values can be read back on the

bidir ectional address lines by activating MKRD or CNTRD re-

spectively.

The new features added to the QuadPort™ as compared to

standard synchronous dual-ports include: readback of

burst-counter internal address value on address lines,

counter-mask registers to control the counter wrap-around,

readback of mask register value on address lines, interrupt

flags for message passing, JTAG for boundary scan, and asyn-

chronous Master Reset.

CY7C0430V

PRELIMINARY

Pin Configurat ion

272-Ball Gr id Array (BGA)

Top View

1234567891011121314151617181920

ALB

P1 I/O17

P2 I/O15

P2 I/O13

P2 I/O11

P2 I/O9

P2 I/O16

P1 I/O14

P1 I/O12

P1 I/O10

P4 I/O12

P4 I/O14

P4 I/O16

P4 I/O9

P3 I/O11

P3 I/O13

P3 I/O15

P3 I/O17

P3 LB

BVDD1 UB

P1 I/O16

P2 I/O14

P2 I/O12

P2 I/O10

P2 I/O17

P1 I/O13

P1 I/O11

P1 TMS TDI I/O11

P4 I/O13

P4 I/O17

P4 I/O10

P3 I/O12

P3 I/O14

P3 I/O16

P3 UB

P4 VDD1

CA14

P1 A15

P1 CE1

P1 CE0

P1 R/W

P1 I/O15

P1 VSS2 VSS2 I/O9

P1 TCK TDO I/O9

P4 VSS2 VSS2 I/O15

P4 R/W

P4 CE0

P4 CE1

P4 A15

P4 A14

D VSS1 A12

P1 A13

P1 OE

P1 VDD2 VSS2 VSS2 VDD2 VDD VSS VSS VDD VDD2 VSS2 VSS2 VDD2 OE

P4 A13

P4 A12

P4 VSS1

EA10

P1 A11

P1 MKRD

P1 CNTRD

P4 MKRD

P4 A11

P4 A10

FA7

P1 A8

P1 A9

P1 CNTINT

P4 A9

P4 A8

P4 A7

GVSS1 A5

P1 A6

P1 CNTINC

P4 A6

P4 A5

P4 VSS1

HA3

P1 A4

P1 MKLD

P1 CNTLD

P4 MKLD

P4 A4

P4 A3

JVDD1 A1

P1 A2

P1 VDD GND[3] GND[3] GND[3] GND[3] VDD A2

P4 A1

P4 VDD1

KA0

P1 INT

P1 CNTRST

P1 CLK

P1 GND[3] GND[3] GND[3] GND[3] CLK

P4 CNTRST

P4 INT

P4 A0

LA0

P2 INT

P2 CNTRST

P2 VSS GND[3] GND[3] GND[3] GND[3] VSS CNTRST

P3 INT

P3 A0

M VDD1 A1

P2 A2

P2 CLK

P2 GND[3] GND[3] GND[3] GND[3] CLK

P3 A2

P3 A1

P3 VDD1

NA3

P2 A4

P2 MKLD

P2 CNTLD

P3 MKLD

P3 A4

P3 A3

PVSS1 A5

P2 A6

P2 CNTINC

P3 A6

P3 A5

P3 VSS1

RA7

P2 A8

P2 A9

P2 CNTINT

P3 A9

P3 A8

P3 A7

TA10

P2 A11

P2 MKRD

P2 CNTRD

P3 MKRD

P3 A11

P3 A10

U VSS1 A12

P2 A13

P2 OE

P2 VDD2 VSS2 VSS2 VDD2 VDD VSS VSS VDD VDD2 VSS2 VSS2 VDD2 OE

P3 A13

P3 A12

P3 VSS1

VA14

P2 A15

P2 CE1

P2 CE0

P2 R/W

P2 I/O6

P2 VSS2 VSS2 I/O0

P2 NC NC I/O0

P3 VSS2 VSS2 I/O6

P3 R/W

P3 CE0

P3 CE1

P3 A15

P3 A14

W VDD1 UB

P2 I/O7

P1 I/O5

P1 I/O3

P1 I/O1

P1 I/O8

P2 I/O4

P2 I/O2

P2 MRST VSS I/O2

P3 I/O4

P3 I/O8

P3 I/O1

P4 I/O3

P4 I/O5

P4 I/O7

P4 UB

P3 VDD1

YLB

P2 I/O8

P1 I/O6

P1 I/O4

P1 I/O2

P1 I/O0

P1 1/O7

P2 I/O5

P2 I/O3

P2 I/O1

P3 I/O3

P3 I/O5

P3 I/O7

P3 I/O0

P4 I/O2

P4 I/O4

P4 I/O6

P4 I/O8

P4 LB

Note:

3. Central Leads are for thermal dissipation only. They are connected to device VSS.

CY7C0430V

PRELIMINARY

Selection Guide

CY7C0430V

-133 CY7C0430V

-100

fMAX2 (MHz) 133 100

Max Acc ess Time (ns) (Cl ock to Data) 4.7 5.0

Max Oper ating Current ICC (mA) 750 600

Max Standby Current for ISB1 (mA) (All por ts TTL Level ) 200 150

Max Standby Current for ISB3 (mA) (All por t s CMOS Level) 5 5

Pin Definit ions

Port 1 Port 2 Port 3 Po rt 4 Description

A0P1–A15P1 A0P2–A15P2 A0P3–A15P3 A0P4–A15P4 Address Input/Out put.

I/O0P1–I/O17P1 I/O0P2–I/O17P2 I/O0P3–I/O17P3 I/O0P4–I/O17P4 Data Bus Input/Output.

CLKP1 CLKP2 CLKP3 CLKP4 Clo ck Input. This input can be free running or strobed.

Maximum clock input rate is fMAX.

LBP1 LBP2 LBP3 LBP4 Lower Byte Selec t Inp ut. Asserting this signal L OW en-

ables read and write oper atio ns to t he lower byte. For

read operations both the LB and OE signals m ust be as-

serted to drive output data on the lower by te of the data

pins.

UBP1 UBP2 UBP3 UBP4 Upper Byte Selec t Input . Same functio n as LB , but to the

upper byte.

CE0P1,CE1P1 CE0P2,CE1P2 CE0P3,CE1P3 CE0P4,CE1P4 Chip Enable Input. To select any port, both CE0 AND CE1

mus t be asserted to their active state s (CE0 ≤ VIL and

CE1 ≥ VIH).

OEP1 OEP2 OEP3 OEP4 Output Enab le Input. This si gnal mus t be a sserted LO W

to enable the I/O data li nes dur ing read operations. OE

is asynchronous input.

R/WP1 R/WP2 R/WP3 R/WP4 Read/Write Enab le Input. This s ignal is asserted LO W to

write to the dual port memory arr ay. Fo r read oper ations ,

assert this pin HIGH.

MRST Master Reset Input. This is one signal f or All Ports. MRST

is an asynchronous input. Asserting MRST LO W per-

f orms all of the reset func tions as described in t he te xt. A

MRST operation is requir ed at power-up.

CNTRSTP1 CNTRSTP2 CNTRSTP3 CNTRSTP4 Counter Reset Input . Asserti ng thi s signal LOW resets

the burst address counter of its respective port to z ero.

CNTRST is second t o MRST in priority with respect to

counter and mask regis ter oper ations.

MKLDP1 MKLDP2 MKLDP3 MKLDP4 Mask Register Load input. Asser ting this signal LOW

loads the mask register with the external address avail-

able on the address lines. MKLD oper ation has higher

priority o ver CNTLD oper ati on.

CNTLDP1 CNTLDP2 CNTLDP3 CNTLDP4 Count er Load In put. Asserti ng this signal LO W loads t he

burst counter with the external address present on the

address pins.

CNTINCP1 CNTINCP2 CNTINCP3 CNTINCP4 Counter Increment Input. Asserting thi s si gnal LOW in-

crements the burst add ress counter of its re spectiv e port

on each rising edge of CLK.

CY7C0430V

PRELIMINARY

CNTRDP1 CNTRDP2 CNTRDP3 CNTRDP4 Counter Rea dbac k I nput. When as serted LO W, t he int er-

nal ad dres s v al ue of t he coun ter wil l be r ead bac k on the

address lines. During CNTRD operation, both CNTLD

and CNTINC must be HIGH. Counter readback operation

has higher priority over mask register readback opera-

tion. Counter readback operation is ind ependent of port

chip enab les . If address readb ac k oper ati on occurs with

chip enables active (CE0 = LOW, CE1 = HIGH), the data

line s (I/ Os) wil l be t hree-st ated. The readbac k ti ming will

be valid after one no-operation cycle plus tCD2 from the

rising edge of the n ext cycle.

MKRDP1 MKRDP2 MKRDP3 MKRDP4 Mask Register Readback Input. When asserted LOW, the

value of the mask registe r will be readback on address

lines. During mask register readback operation, all

counter and MKL D inputs must be HIGH (see Count er

and Mask Register Operations truth table). Mask register

readback op eration is independent of port chip e nables .

If addr ess readback oper atio n occurs with chip enables

active (CE0 = LOW, CE1 = HIGH ), the data lines (I /Os)

will be three-stated. The readback will be valid after one

no-operation cycl e plus tCD2 from t he rising edge of the

ne xt cycle.

CNTINTP1 CNTINTP2 CNTINTP3 CNTINTP4 Counter Int errup t flag output. Flag is asserted LOW for

one clock cycle when the counter wraps ar ound to loca-

tion z ero.

INTP1 INTP2 INTP3 INTP4 In terrupt fl ag output. Interrupt permits commu nications

betwee n al l f our p orts. The upper four memory loc ations

can be used f or message passing. Example of operation:

INTP4 is asserted LOW when another port writes to the

mailbox location of Port 4. Flag is cleared when Port 4

reads t he con tents of its mai lbo x . The same oper at ion i s

appli cable to Ports 1, 2, and 3.

TMS JTAG Test Mode Selec t I nput. It cont rols the advance of

JTAG TAP state ma chine. State machine transi tion s oc-

cur on the rising edge of TCK.

TCK JTA G Test Cloc k Input. This can be CLK of any port or a n

external clock connected to the JTAG TAP.

TDI JTAG Test Data Input. This is the only data input. TDI

inputs will shift data serially in to the selected register.

TDO JTAG Test Data Output. This is the only data output. TDO

transitions occur on the falling edge of TCK. TDO normal-

ly thr ee-stated except when captured data is s hif ted out

of the JTAG TAP.

GND Thermal ground f or heat d issip ati on.

VSS Ground Input.

VDD Power Inpu t.

VSS1 Address lin es ground Input.

VDD1 Address lin es power Input.

VSS2 Data lines ground Input.

VDD2 Data li nes power Input.

Pin Definit ions (continued)

Port 1 Port 2 Port 3 Port 4 Description

CY7C0430V

PRELIMINARY

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature ... .. .. ........ ......... ........ –65°C to + 150°C

Ambient Tem perature with

Power Applied............................................–55°C to + 125°C

Supply Vo ltage to Ground Potent ial ..............–0.5V to + 4.6V

DC Voltage Appl ied to

Ou t pu t s in Hi gh Z Sta t e... ..... ..... ..... ..... ..... –0.5V to VCC+0.5V

DC Input Voltage .....................................–0.5V to VCC+0.5V

Ou tp u t C urre n t in to O u tp u ts (LOW ).. .. ..... ..... ..... ..... ..... 20 m A

Stati c Discharge Voltage ............. ..... ...................... ...>2001V

Latch-Up Current.....................................................>200 mA

Operating Range

Range Ambient

Temperature VDD

Commercial 0°C to + 70 °C 3.3V ± 150 mV

Industrial –40°C to +8 5 °C 3.3V ± 150 mV

Electrical Characteristics Over the Operating Range

Parameter Description

CY7C0430V

Unit

-133 -100

Min. Typ Max Min. Typ Max

VOH Output HIGH Voltage

(VCC = Min., IOH = –4.0 mA) 2.4 2.4 V

VOL Output LOW Voltage

(VCC = Min., IOH = +4.0 mA) 0.4 0.4 V

VIH Input HIGH Voltage 2.0 2.0 V

VIL Input LOW Voltage 0. 8 0.8 V

IOZ Outpu t Leakage Current –10 10 –10 10 µA

ICC Operating Current (VCC = Ma x.,

IOUT = 0 m A ) Ou tpu t s D i s abled,

CE = VIL, f = fmax

Indust. 413 750 330 600 mA

Com’l. mA

ISB1 Standby Current (4 Ports toggling

at TTL Levels,0 active) CE1-4 ≥

VIH, f = fMAX

Indust. 80 200 60 150 mA

Com’l. mA

ISB2 Standby Current (4 Ports toggling

at TTL Levels, 1 active) CE1 | CE2

| CE3 | CE4 < VIL, f = fMAX

Indust. 170 349 128 263 mA

Com’l. mA

ISB3 Standb y Curr ent (4 P orts CMOS

Level, 0 a cti ve) CE1-4 ≥ VIH, f = 0 Indust. 1.5 5 1.5 5 mA

Com’l. µA

ISB4 Standb y Curr ent (4 P orts CMOS

Lev el, 1 active and to ggling) CE1

| CE2 | CE 3 | CE4 < VIL, f = fMAX

Indust. 110 240 83 180 mA

Com’l. mA

JTAG TAP Electrical Characteristics Ov er the Oper ating Range

Parameter Description Test Condi tions Min. Max. Unit

VOH1 Output HIGH Voltage IOH = −4.0 mA 2.4 V

VOL1 Output LOW Voltage IOL = 4.0 mA 0.4 V

VIH Input HIGH Voltage 2.0 V

VIL Input LOW Voltage 0.8 V

IXInput Leakage Current GND ≤ VI ≤ VDD –100 100 µA

Capacitance

Parameter Description Test Conditi ons Max. Unit

CIN Input Capacitance TA = 25°C, f = 1 MHz,

VCC = 3.3V 8pF

COUT Output Capacit ance 8pF

CY7C0430V

PRELIMINARY

AC Test Load

Note:

4. Test Conditions: C = 10 pF.

=1.5V

OUTPUT

(a) Normal Load

R = 50

Ω

= 50

Ω

[4]

3.0V

GND 90% 90%

10%

tRtF

10%

ALL INPUT PULSES

(b) Three-State Delay

OUTPUT

5 pF

R = 50

Ω

= 50

Ω

TDO

C = 10 pF

Z0=50Ω

GND

1.5V

50Ω

=3.3V

OUTPUT

5 pF

R = 50

Ω

= 50

Ω

=0.0V

CY7C0430V

PRELIMINARY

Swi t ch i n g C h ar acteri stic s Over the Industrial Operating Range

Parameter Description

CY7C0430V

Unit

–133 –100

Min. Max. Min. Max.

fMAX2 Maximum Frequency 133 100 MHz

tCYC2 Cl ock Cycle Time 7.5 10 ns

tCH2 Cl ock HIGH Ti me 3 4 ns

tCL2 Cl ock LOW Time 3 4 ns

tRClock Rise Time 2 3 ns

tFClock Fall Time 2 3 ns

tSA Address Set-up Time 2.3 3 ns

tHA Address Hold Time 0.7 0.7 ns

tSC Ch ip En able Se t - up Tim e 2. 3 3 ns

tHC Ch ip En able H ol d Time 0. 7 0. 7 n s

tSW R/W Set-up Time 2.3 3 ns

tHW R/W Hold Time 0.7 0.7 ns

tSD Input Data Set-up T ime 2. 3 3 n s

tHD Input Data Hold Time 0. 7 0.7 ns

tSB Byte Set-up Time 2.3 3 ns

tHB Byte Hold Time 0.7 0.7 ns

tSCLD CNTLD Set-up Time 2.3 3 ns

tHCLD CNTLD Hold Time 0.7 0.7 ns

tSCINC CNTINC Set -up Time 2.3 3 ns

tHCINC CNTINC Hold T ime 0.7 0.7 ns

tSCRST CNTRST Set-up Ti me 2.3 3 ns

tHCRST CNTRST Hold Time 0.7 0.7 ns

tSCRD CNTRD Set-up Time 2.3 3 ns

tHCRD CNTRD Hold Time 0.7 0.7 ns

tSMLD MKLD Set-up Time 2.3 3 ns

tHMLD MKLD Hold Tim e 0.7 0.7 ns

tSMRD MKRD Set-up Time 2.3 3 ns

tHMRD MKRD Hold Time 0.7 0.7 ns

tOE Output Enable to Data Valid 6.5 8 ns

tOLZ[5] OE to LOW Z 1 1 ns

tOHZ[5] OE to HIGH Z 1 6 1 7 ns

tCD2 Cl ock to Data Valid 4.7 5 ns

tCA2 Clock to Counter Address Readback Valid 4.7 5 ns

tCM2 Clock to M ask Register readback Valid 4.7 5 ns

tDC Data Output Hold After Clock HIGH 1 1 ns

tCKHZ[6] Cloc k HIGH to Outp ut Hi gh Z 1 4.8 1 6.8 ns

tCKLZ[6] Cloc k HIGH to Outp ut LOW Z 1 1 ns

tSINT Clock to INT S e t Ti m e 1 7 .5 1 10 ns

tRINT Clock to I NT Reset Tim e 1 7.5 1 10 ns

tSCINT Clock to CNTINT S e t Ti me 1 7 .5 1 10 ns

tRCINT Clock to CNTINT Reset Time 1 7.5 1 10 ns

CY7C0430V

PRELIMINARY

Notes:

5. This parameter is guaranteed by design, but it is not production tested.

6. Valid for both address and data outputs.

Master Reset Timing

tRS Mast er Reset Pulse Width 7.5 10 ns

tRSR Master Reset Recovery Time 7.5 10 ns

tROF Master Reset to Output Flags Reset Ti m e 6.5 8 ns

Port to Port Delays

tCCS Clock to Clo ck Set-up Time 6.5 9 ns

Swi t ch i n g C h ar acteri stic s Over the Industrial Operating Range (cont inued)

Parameter Description

CY7C0430V

Unit

–133 –100

Min. Max. Min. Max.

CY7C0430V

PRELIMINARY

JTAG Timing and S witching Waveforms

Parameter Description

CY7C0430V

Unit

–133 –100

Min. Max. Min. Max.

fJTAG Maxi mum JTAG TAP Controller Freque ncy 10 10 MHz

tTCYC TCK Clock Cycle Time 100 100 ns

tTH TCK Clock High Tim e 40 40 ns

tTL TCK Clock Low Ti m e 40 40 ns

tTMSS TMS Setup to TCK Clock Rise 10 10 ns

tTMSH TMS Hold After TCK Cloc k Rise 10 10 ns

tTDIS TDI Setup to TCK Clock Rise 10 10 ns

tTDIH TDI Hold after TCK Cloc k Rise 10 10 ns

tTDOV TCK Clock Low to TDO Valid 20 20 ns

tTDOX TCK Clock Low to TDO Invalid 0 0 ns

Test Clock

Test M ode Select

TCK

TMS

Te st D ata-In

TDI

Test Data-Out

TDO

tTCYC

tTMSH

tTL

tTH

tTMSS

tTDIS tTDIH

tTDOX tTDOV

CY7C0430V

PRELIMINARY

Switching Waveform s

Ma ster R ese t[7]

Notes:

7. ts is the set-up time required for all input control signals.

MRST

tRSR

tRS

INACTIVE ACTIVE

TMS

TDO

INT

CNTINT

tRSF

ALL

ADDRESS/

DATA

LINES

ALL

OTHER

INPUTS

tCH2 tCL2

tCYC2

CLK

CY7C0430V

PRELIMINARY

Read Cycle[8, 9, 10 , 11, 12 ]

Notes:

8. OE is asynchronously controlled; all other inputs (excluding MRST) are synchronous to the rising clock edge.

9. CNTLD= VIL, MKLD= VIH, CNTINC = x, and MRST=CNTRST = VIH.

10. The output is disabled (high-impedance state) by CE=VIH following the next rising edge of the clock.

11. Addresses do not have to be accessed sequentially. Note 9 indicates that address is constantly loaded on the rising edge of the CLK. Numbers are f or reference

only.

12. CE is internal signal. CE = VIL if CE0 = VIL and CE1 = VIH.

Swi t ch i n g Wav efor ms (continued)

tCH2 tCL2

tCYC2

tSC tHC

tSW tHW

tSA tHA

AnAn+1

CLK

R/W

ADDRESS

DATAOUT

An+2 An+3

tSC tHC

tOHZ

tOE

tOLZ

tDC

tCD2

tCKLZ

QnQn+1 Qn+2

1 Latency

tSB tHB

CY7C0430V

PRELIMINARY

Bank Select Read[13, 14 ]

Read-to-Write-to-Read (OE = VIL)[15, 16, 17, 18]

Notes:

13. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each Bank consists of one Cypress Quadport device from this data sheet.

ADDRESS(B1) = ADDRESS(B2).

14. LB = UB = OE = CNTLD = VIL; MRST= CNTRST= MKLD = VIH.

15. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals.

16. LB = UB = CNTLD = VIL; MRST= CNTRST= MKLD =VIH.

17. Addresses do not have to be accessed sequentially since CNTLD= V IL constantly loads the address on the rising edge of the CLK; numbers are for reference only.

18. During “No operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.

Swi t ch i n g Wav efor ms (continued)

A0A1A2A3A4A5

tSA tHA

tSC tHC

tSA tHA

tSC tHC

tSC tHC tCKHZ

tDC

tCD2

tCKLZ

tCD2 tCD2 tCKHZ

tCKLZ

tCD2 tCKHZ

tCKLZ

tCD2

tCH2 tCL2

tCYC2

CLK

ADDRESS(B1)

CE(B1)

DATAOUT(B2)

DATAOUT(B1)

ADDRESS(B2)

CE(B2)

tCYC2tCL2

tCH2

tHC

tSC

tHW

tSW

tHA

tSA

tHW

tSW

tCD2 tCKHZ

tSD tHD

tCKLZ

tCD2

NO OPERATION WRITEREAD READ

CLK

R/W

ADDRESS

DATAIN

DATAOUT

AnAn+1 An+2 An+2

Dn+2

An+3 An+4

QnQn+3

CY7C0430V

PRELIMINARY

Read-to-Write-to-Read (OE Controlled)[15, 16, 17, 18]

Read wit h Addr ess Count er Advance[19, 20]

Notes:

19. CE0 = OE = LB = UB = VIL; CE1 = R/W = CNTRST = MRST = MKLD = MKRD = CNTRD = VIH.

20. The “Internal Address” is equal to the “External Address” when CNTLD= VIL.

Swi t ch i n g Wav efor ms (continued)

tCYC2tCL2

tCH2

tHC

tSC

tHW

tSW

tHA

tSA

AnAn+1 An+2 An+3 An+4 An+5

tHW

tSW

tSD tHD

Dn+2

tCD2

tOHZ

READ READWRITE

Dn+3

CLK

R/W

ADDRESS

DATAIN

DATAOUT

tCKLZ

tCD2

Qn+4

COUNTER HOLD

READ WITH COUNTER

tSA tHA

tSCLD tHCLD

tSCINC tHCINC

tCH2 tCL2

tCYC2

Qx–1QxQnQn+1 Qn+2 Qn+3

tDC

tCD2

READ WITH COUNTER

READ

EXTERNAL

ADDRESS

CLK

ADDRESS

CNTLD

DATAOUT

CNTINC

CY7C0430V

PRELIMINARY

Write wit h Address Counter Advance [20, 21]

Note:

21. CE0 = LB = UB = R/W = VIL; CE1 = CNTRST = MRST = MKLD = MKRD = CNTRD = VIH.

Swi t ch i n g Wav efor ms (continued)

tCH2 tCL2

tCYC2

AnAn+1 An+2 An+3 An+4

Dn+1 Dn+1 Dn+2 Dn+3 Dn+4

tSCLD tHCLD

tSCINC tHCINC

tSD tHD

WRITE EXTERNAL WRITE WITH COUNTER

ADDRESS WRITE WITH

COUNTER WRITE COUNTER

HOLD

CLK

ADDRESS

INTERNAL

CNTINC

CNTLD

DATAIN

ADDRESS

tSA tHA

CY7C0430V

PRELIMINARY

Counter Reset [ 17 , 22, 23]

Notes:

22. CE0 = LB = UB = VIL; CE1 = MRST = MKLD = MKRD = CNTRD = VIH.

23. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset.

Swi t ch i n g Wav efor ms (continued)

tCH2 tCL2

tCYC2

CLK

ADDRESS

INTERNAL

CNTINC

CNTLD

DATAIN

ADDRESS

CNTRST

R/W

DATAOUT Q0Q1Qn

AXA0A1AnAn+1

tSCRST tHCRST

tSD tHD

tSW tHW

AnAn+1

tSA tHA

COUNTER

RESET WRITE

ADDRESS 0 READ

AD DRESS 1 READ

ADDRESS n

tSCLD tHCLD

CY7C0430V

PRELIMINARY

Load and Read Address Counter[24]

Notes:

24. CE0 = OE = LB = UB = VIL; CE1 = R/W = CNTRST = MRST = MKLD = MKRD = VIH.

25. Address in output mode. Host must not be driving address bus after time tCKLZ in next cloc k cycle.

26. Address in input mode. Host can drive address bus after tCKHZ.

27. This is the value of the address counter being read out on the address lines.

Swi t ch i n g Wav efor ms (continued)

READ DATA WITH COUNTER

tSA tHA

tSCLD tHCLD

tSCINC tHCINC

tCH2 tCL2

tCYC2

Qx–1QxQnQn+1 Qn+2

READ

INTERNAL

ADDRESS

CLK

-A

CNTLD

DATAOUT

CNTINC

tSCRD tHCRD

CNTRD

AnAn+1 An+2

INTERNAL

ADDRESS

An+2

An+2 An+2

Qn+2

tCD2 tDC

tCKLZ

tCKHZ

CA2

LOAD

EXTERNAL

ADDRESS

Note 25 Note 26

[27]

An+2

CY7C0430V

PRELIMINARY

Load and Read Mask Register [28]

Notes:

28. CE0 = OE = LB = UB = VIL; CE1 = R/W = CNTRST = MRST = CNTLD = CNTRD = CNTINC =VIH.

29. This is the value of the Mask Register read out on the address lines.

Switching Waveforms (continued)

tSA tHA

tSMLD tHMLD

tCH2 tCL2

tCYC2

READ

MASK-REGISTER

VALUE

CLK

-A

MKLD

tSMRD tHMRD

MKRD

AnAnAn

INTERNAL

VALUE

AnAn

tCKLZ tCKHZ

tCA2

LOAD

MASK REGISTER

VALUE

MASK

[29]

Note 25 Note 26

CY7C0430V

PRELIMINARY

P ort 1 Writ e to Port 2 Read[3 0, 31, 32]

Notes:

30. CE0 = OE = LB = UB = CNTLD =VIL; CE1 = CNTRST = MRST = MKLD = MKRD = CNTRD = CNTINC =VIH.

31. This timing is valid when one port is writing, and one or more of the three other ports is reading the same location at the same time. If tCCS is violated, indeterminate

data will be read out.

32. If tCCS< minimum specified value, then P ort 2 will read the most recent data (written by Port 1) only (2*tCYC2 + tCD2) after the rising edge of P ort 2's clock. If tCCS

> minimum specified value, then Port 2 will read the most recent data (written by Port 1) (tCYC2 + tCD2) after the rising edge of Port 2's clock .

Swi t ch i n g Wav efor ms (continued)

tSA tHA

tSW tHW

tCH2 tCL2

tCYC2

CLKP1

R/WP1

tCKHZ tHD

tSA

tHA

tDC

tCCS

tSD tCKLZ

tCH2

tCL2

tCYC2

tCD2

PORT-1

ADDRESS

PORT-1

DATAIN

CLKP2

R/WP2

PORT-2

ADDRESS

PORT-2

DATAOUT

CY7C0430V

PRELIMINARY

Counter Interrupt [33, 34, 35]

Mailbox Interrupt Timing[36, 37, 38, 39, 40]

Notes:

33. CE0 = OE = LB = UB = VIL; CE1 = R/W = CNTRST = MRST = CNTRD = MKRD = VIH.

34. CNTINT is always driven.

35. CNTINC goes LOW as the counter address masked portion is incremented from xx7Fh to xx00h. The “x” is “don’t care.”

36. CE0 = OE = LB = UB = CNTLD =VIL; CE1 = CNTRST = MRST = CNTRD = CNTINC = MKRD = MKLD =VIH.

37. Address “FFFE” is the mailbox location for Port 2.

38. Port 1 is configured for Write operation, and Port 2 is configured for Read operation.

39. Port 1 and Port 2 are used for simplicity. All four ports can write to or read from any mailbox.

40. Interrupt flag is set with respect to the rising edge of the write clock, and is reset with respect to the rising edge of the read clock.

Swi t ch i n g Wav efor ms (continued)

tSMLD tHMLD

tSCLD tHCLD

tCH2 tCL2

tCYC2

CLK

MKLD

CNTLD

Anxx7Eh

INTERNAL

ADDRESS xx7Fh xx00h

xx7Dh

EXTERNAL

ADDRESS

tSCINC tHCINC

CNTINC

COUNTER

007Fh

xx7Dh xx00h

CNTINT tSCINT tRCINT

CH2

CL2

CYC2

CLK

tCH2 tCL2

tCYC2

CLKP2

FFFE

tSA tHA

An+3

AnAn+1 An+2

PORT-1

ADDRESS

AmAm+4

Am+1 FFFE Am+3

PORT-2

ADDRESS

INTP2

tSA tHA

tSINT tRINT

CY7C0430V

PRELIMINARY

Tabl e 1. Read/Write and Enabl e O peration (Any Port)[41, 42, 43]

Inputs Outputs

OE CLK CE0CE1R/W I/O0–I/O17 Operation

X H X X High-Z Deselected

X X L X High-Z Deselected

X L H L DIN Write

L L H H DOUT Read

H X L H X High-Z Outputs Disabled

Tabl e 2. Address Counter and Count er-Mask Regi ster Control Operati on (Any Port)[41, 44, 45]

CLK MRST CNTRST MKLD CNTLD CNTINC CNTRD MKRD Mode Operation

X L X X X X X X Master-

Reset Counter/A ddress Register Reset and Mask

Registe r Set (resets entire chi p as per reset

state table)

H L X X X X X Reset Count er/Address Regist er Reset

H H L X X X X Load Load of Address Lines into Mask Register

H H H L X X X Load Load of Address Lines into Counter/Address

H H H H L X X Incre-

ment Co unter In crement

H H H H H L X Read-

back Readback Counte r on Addr ess Lines

H H H H H H L Read-

back Readback Mask Register on Addre ss Lines

H H H H H H H Hold Counter Hol d

Notes:

41. “X” = “don’t care,” “H” = VIH, “L” = VIL.

42. OE is an asynchronous input signal.

43. When CE changes state, deselection and read happen after one cycle of latency.

44. CE0 = OE = VIL; CE1 = R/W = VIH.

45. Counter operation and mask register operation is independent of Chip Enables.

CY7C0430V

PRELIMINARY

Master Reset

The QuadPort undergoes a complete reset by taking its Master

Reset (MRST) input LO W. The Master Reset in put can switch

asynchronously to the clocks. A Master Reset initializes the

internal b u rst c ount ers t o zer o, and t he counter mask regis ters

to al l ones (c omple tely unmask ed). A Master Reset also f orces

the Mailbox Interrupt (INT) flags and the Counter Interrupt

(CNTINT) flags HIGH, and takes all registered control signals

to a deselected read state[46]. A Master Reset must be per-

formed on the QuadPort a ft er power-up.

Interrupts

The upper four memory locations may be used for message

passing and permit communications between ports. Table 3

shows the interrupt operation for all ports. For the 1-Meg

QuadPort, the highest memory location FFFF is the mailbox

for Port 1, FFFE is the mailbox f or P ort 2, FFFD is the mailb ox

for Por t 3, and FFFC is the mailbox for Por t 4. Table 3 show s

that in order to set Por t 1 INTP1 flag, a write by any other port

to address FFFF will assert INTP1 LO W. A read of FFFF loca-

tio n by Port 1 w i ll r e s et INT P1 HIGH. When one port wr ites to

the othe r port’s ma ilbo x, the I nterrupt fla g (INT) of t he po rt that

the mai lbo x bel ongs to is asserted LO W. The Int errupt is r eset

when t he o wner ( port) of t he mailb o x read s the c onte nts of the

mailbox. The interrupt flag is set in a flow-through mode (i.e.,

it follows the clock edge of the writing port). Also, the flag is

reset i n a flow-through mode (i.e., it follows the clock edge of

the reading port).

Each port can r ead the other por t’s mailbox without resetting

the in terrupt. If an app licat ion d oes not r equire messa ge p ass-

ing, INT pins should be treated as no-connect and should be

lef t floa ting. When t wo ports or more write to the same mailbo x

at the same time INT will be asserted but the contents of the

mailbox are not guaranteed to be val id.

Note:

46. During Master Reset the control signals will be set to a deselected read state: CE0I = LBI = UBI = R/WI = MKLDI = MKRDI = CNTRDI = CNTRSTI = CNTLDI =

CNTINCI = VIH; CE1I = VIL. The “I” suffix on all these signals denotes that these are the internal registered equivalent of the associated pin signals.

Tabl e 3. Interrupt Operat ion Example

Port 1 Port 2 Port 3 Port 4

Function A0P1–15P1 INTP1 A0P2–15P2 INTP2 A0P3–15P3 INTP3 A0P4–15P4 INTP4

Set Port 1 INTP1 Flag X L FFFF XFFFF XFFFF X

Reset Port 1 INTP1 Flag FFFF H X X X X X X

Set Port 2 INTP2 Flag FFFE X X L FFFE XFFFE X

Reset Port 2 IN TP2 Flag X X FFFE H X X X X

Set Port 3 INTP3 Flag FFFD XFFFD X X L FFFD X

Reset Port 3 INTP3 Flag XXXXFFFD H X X

Set Port 4 INTP4 Flag FFFC XFFFC XFFFC X X L

Reset Port 4 IN TP4 Flag XXXXXXFFFC H

CY7C0430V

PRELIMINARY

Address Counter Control Operations

Counter enab le inputs are pro vided to st all t he operation of the

address input and ut ili ze the int ernal addr ess generat ed by the

internal counter for the fast interleaved memory applicati ons.

A por t’s burst counter is loaded with the port ’s Counter Load

pin ( CNTLD). When the port’s Coun ter Incr ement (CNTINC) is

asserted, the address count er wi ll increment on ea ch LOW to

HIGH transition of that por t’s clock signal. This will read/write

one word from/into each successive address location until

CNTINC is deasserted. Depe nding on the mask register state ,

the coun ter can ad dres s the ent ire mem ory arr a y and wi ll l oop

back to start. Counter Reset (CNTRST) is used to reset the

Burst Count er (the Mask Register value is unaffected). When

using the counter in readback mode, the int ernal addres s val-

ue of the count er wi ll be read back on the address lin es when

Counter Readback Signal (CNTRD) is asserted. Fig ure 1 pro-

vides a block diagram of the readback operati on. Table 2 lists

control signals required for counter operations. The signals are

lis ted based on their priority. For example, master reset takes

precedence over counter reset, and counter load has lower

priority th an m ask register load (described below). All counter

operations are independent of Chip Enables (CE0 and CE1).

When the address readback operation is perfor med the data

I/Os are three-stated (if CEs are active) and one-clock cycle

(no-operation cycle) latency is experienced. The address will

be read at time tCA2 from the rising edge of t he cloc k f oll ow ing

the no-operation cycle. The read back address can be either

of the burst counter or the mask register based on the levels

of Counter Read signal (CNTRD) and Mask Register Read

signal (MKRD). Both signals are synchronized to the port's

cl ock as show n i n Table 2. Counter read has a higher pr iority

than mask read.

Addr.

Read

Back

Counter/

Address

CLK

CNTLD = 1

CNTINC = 1

CNTRST = 1

MKLD = 1

MKRD

CNTRD

Memory

Array

Mask

Read back

Bidirectional

Address Lines

Figure 1. Counter and Mask Regist er Read Back on Address Lines

CY7C0430V

PRELIMINARY

Counter-Mask Register

The burst cou nter has a mask register that controls whe n and

where the count er wr aps . A n int errupt fla g (CNTI NT) is assert-

ed for one clock cycle when the unmasked portion of the

counter address wraps around from all ones (CNTINC must be

asserted) to all zeros. The example in Figure 2 shows the

counter mask register loaded with a mask value of 003F un-

masking the first 6 bits with bit “0” as the LSB and bit “15” as

the MSB. Th e maxim um va lue the mask re gister can be loaded

with is FFFF. Setting the mask regist er to this val ue allo ws the

counter to access the entire memory space. The address

counter is then loaded with an initial value of XXX8. The

“blocked” ad dresses ( in thi s case, the 6th add res s through the

15th ad dress) ar e loaded with an address but do not in crement

once loaded. The counter address will start at address XXX8.

With CNTINC asserted LOW, the counter will increment its

internal addr ess v alue till it reaches th e mask regist er v al ue of

3F and wraps around the memory block to location XXX0.

Therefore, the counter uses the mask-register to define

wrap-ar ound point. The mask regist er of ever y port is loaded

when MKLD (mask r egi ster load) for that por t is LOW. When

MKRD is LOW, the value of the mask r egister can be read o ut

on address lines in a manner similar to counter read back op-

erati on (s ee Table 2 for required conditions).

When t he burst count er is loaded with an addres s higher than

the mask register value, the higher addresses will form the

mask ed porti on of the coun ter addr ess and are call ed bl oc ked

addresses. The blocked addresses will not be changed or af-

f ect ed by t he coun ter in crement op er ation. The only exce ption

is mask register bit 0. It can be masked to allow the address

counter to increment by two . If the mask regi ster bit 0 is loaded

with a logic value of “0,” th en address count er bit 0 is masked

and can not be changed during counter increment operation.

If t he loaded v alue for addr ess counter bit 0 is “0,” the counter

will i ncr ement by two and the address values are even. If the

loaded value for address counter bit 0 is “1,” the counter will

increment by two and the address values are odd. This oper-

ations allows the user to achieve a 36-bit interface using any

two ports , where the counter of one port counts ev en addr ess-

es and the counter of the other port counts odd addresses.

This even-odd address scheme stores one half of the 36-bit

word i n eve n memory loca tions, and the other hal f in o dd mem-

ory locations. CNTINT will be asserted when the unmasked

portion of the counter wraps to all zeros. Loading mask regis-

ter bit 0 with “1” al lows the counter to increment the address

value sequentially.

Tab le 2 groups the operations of the mask register with the

oper at ions of the addr ess counter. Address co unter and mask

Master rese t (MRST) i s the on ly as ynchr ono us si gnal l ist ed o n

Table 2. Signals are listed based on their priority going from

left column to right column with MRST being the highest. A

LO W on MRST wi ll reset both count er regi st er to all zeros an d

mask register to all ones. On the other hand, a LOW on

CNTRST will only clear the addr ess counter register to zeros

and the mask register will remain intact.

There are f our opera ti ons for the counter and mask register:

1. Load operation: When CNTLD or MKLD is LO W, the ad-

dress counter or the mask register i s loaded with the ad-

dress value presented at the address lines. This value rang-

es f rom 0 to FFFF ( 64K). Th e mask regist er l oad op erat ion

has a higher priority over the address counter l oad opera-

tion.

2. Increment: O nce the address counter is loaded with an ex-

ternal address , the counter can internally increment t he ad-

215 214 2621

2522

242320

215 214 2621

2522

242320

215 214 2621

2522

242320

215 214 2621

2522

242320

0’s1

0101

X’s1

X0X0

X’s1

X1X1

X’s0

X0X0

Blocked Address Counter Addres s

Mask

bit-0

Address

Counter

bit-0

CNTINT

Example:

Load

Counter-Mask

Regist er = 3F

Load

Address

Counter = 8

Max

Address

Max + 1

Address

Figure 2. Programmable Counter-Mask Regi ster Operat ion[47]

Note:

47. The “X” in this diag ram represents the counter upper-bits.

CY7C0430V

PRELIMINARY

dress value by asserting CNTINC LOW. The counter can

address the ent ir e m emo ry array (depend on the v alue of

the mask regi ster) and loop back to location 0. The inc re-

ment operation is second in priority t o load operation.

3. Readb ack: the int ernal v alue of either the burst counter or

the mask register can be read out on the address lines when

CNTRD or MK R D is LOW. Counter readback has higher

priority ov er mask re gister readback. A no-operation delay

cycle is e xperienced when readback operation is per-

formed. The addr ess will be valid after tCA2 (for counter

readback) or tCM2 (for mask readback ) fr om the f ollowing

por t's cl ock rising edge. Address r eadback operation is i n-

dependent of the port' s chip enab les (CE0 and CE1). If ad-

dress readback occurs while the port is enabled (chip en-

ables active), the data lines (I/Os) will be three-stated.

4. Hold operation: In order to hold the value of the address

counter at ce rtai n addres s , all si gna ls i n Table 2 hav e to be

HIGH. This operation has the least priority. This operation

is useful in many applications where wait states are needed

or when address is available few cycles ahead of data.

The counte r and mask regist er oper ation s are tota lly i ndepen-

dent of port c hip enable s.

IEEE 1149.1 Serial Boundary Scan (JTAG)

The CY7C0430V i ncorporat es a serial bound ary scan te st ac-

cess port (TAP). This port operates in accordance with IEEE

Standard 1149.1-1900. Note that the TAP controller functions

in a manner that does not conflict with the operation of other

devices using 1149.1 fully compli ant TAPs. The TAP operates

using JEDEC sta ndard 3.3V I/O logi c le v els . It is composed of

three input c onnections and one output connecti on requi red by

the t es t lo gic d efined b y the standar d. Disa b ling the JTA G Fe a-

ture

It is possible to operate the QuadPort without using the JTAG

feature. To disable the TAP controller, TCK must be tied LOW

(VSS) to prevent clocking of the devi ce. TDI and TMS ar e in-

ternally pulled up and may be unconnected. They may alter-

nately be connected to VDD through a pull-up resistor. TDO

should be left unconnected. Upon power-up, the device will

come up in a reset state which will not interfere with the oper-

ation of the device.

Test Access P ort (TAP) - Test Clock (TCK)

The test clock is used only with the TAP controller. All inputs

are captured on the rising edge of TCK. Al l outputs are driven

from the falling edge of TCK.

Test Mode Select

The TMS input is used to give command s to the TAP control ler

and is sampled on the rising edge of TCK. It is allowable to

leave this pin unconnected if the TAP is not used. The pin is

pull ed up internally, resulting in a logi c HIGH leve l.

Test Data-In (TDI)

The T DI pi n is used to serially input informati on into the regis-

ters and can be conn ected to the input of any of th e regis ters.

The register between TDI and TDO i s chosen by the instruc-

tion that is loaded into the TAP instruction regi st er. For infor-

mation on loading the instruction register, see the TAP Con-

troller State Diagram. TDI is internally pulled up and can be

unconnected if the TAP is unused in an application. TDI is

connected to the most signi ficant bit (MSB ) on any regi ster.

Test Data Out (TDO)

The TDO output pin is used to seri all y clock data-out fr om the

registers. The output is active depending upon the current

stat e of the TAP state machine (see TAP Controller Sta te Di a-

gram (FSM)). The output changes on the falling edge of TCK.

TDO is connected to the l east signif icant bit (LSB) of any reg-

ister.

Performing a TAP Reset

A Reset is perf ormed by f orcin g TMS HIGH (VDD) f or f iv e risin g

edges of TCK. This RESET does not affect the operation of the

QuadP ort and ma y be pe rf ormed whi le the de vice i s operati ng.

At power-up, the TAP is reset internally to ensure that TDO

com es up in a hi gh-Z stat e.

TAP Regi sters

Registers are connect ed between the TDI and TDO pins and

allow data to be scanned into and out of the QuadPort test

circuitry. Only one register can be sel ected at a time through

the instruction r egisters. Da ta is serially loaded into the TDI pin

on the ri si ng edge of TCK. Data i s output on the TDO pin on

the falling edge of TCK.

Instruction Regi ster

Four-bit instructions can be serially loaded into the i nstruction

TDI and TDO pins as shown in the following JTAG Control ler

diag ram. Upon powe r-up , the i nstruction regi ster is load ed with

the IDCODE instruction. It is also loaded with the IDCODE

instruction if the controller is placed in a reset state as de-

scrib ed in the previous section.

When the TAP c ontroller is in the Cap tureIR st ate, the two least

sign ifi cant bits are load ed with a binary “01” pattern to allow f or

fault isolation of the board level serial te st path.

Bypass Register

To sav e time when serial ly shiftin g data thr ough registers , it is

som etimes adv a ntageous to skip certain de vices . The b ypass

regi ster is a si ngle- bit r egist er that ca n be plac ed betwe en TDI

and TDO pins. This allows data to be shifted through the

Qua dPort with minimal delay. The b ypass regi ster is set LOW

(VSS) when the BYPASS instruction is executed.

Boundary Scan Registe r

The boundar y scan register is connected to all the input and

output pins on the QuadPort. The boundary scan register is

load ed with the c onte nts o f th e QP Input an d Ou tput ring whe n

the TAP controller is in the Capture-DR state and is then

placed between the TDI and TDO pins when the controller is

moved to the Shift-DR state. The EXTEST, and SAM-

PLE/PRELOAD instructions can be used to capture the con-

tents of the Input and Output ring.

Identification (I D) Register

The ID register is loaded with a vendor-specific, 32-bit code

during t he C aptur e-DR state w hen the IDCODE command is

loaded in the instruction register. The IDCODE is hardwired

into the QuadPor t and can be shifted out when the TAP con-

troller is in the Shift-DR state. The ID register has a vendor

code an d other inf ormatio n described i n the Identificat ion Reg-

iste r D e fin i tio n s tabl e.

CY7C0430V

PRELIMINARY

TAP Inst ruction Set

Sixteen different instructions are possible with the 4-bit instruc-

tion r egiste r. All combinations a re l isted in Table 6, Instruction

Codes. Seven of these instructions (codes) ar e l isted as RE-

SERVED and should not b e used. The other nine inst ructions

are described in detail below.

The TAP controller used in this QuadPort is fully com pliant t o

the 11 49. 1 con v enti on. Th e TAP contr olle r can be used to l oad

address, data or control signals into the QuadPort and can

preload the Input or output buffers. Th e Q uadPort implements

all of the 1149.1 instr uctions except INTEST. Table 6 list s all

instructions.

Instructions are loaded into the TAP controller during the

Shift-IR stat e when the instruction register is placed between

TDI and TDO. During this state, instructions are shifted

throu gh the instruction regist er throu gh the TDI and TDO pins.

To e x ecut e the inst ructi on once it is shi fted i n, the TAP contr ol-

ler needs to be moved into the Update-IR s tat e.

EXTEST

EXTE ST is a ma ndator y 1149 .1 instruc tion which i s to b e exe-

cuted whenever the instruction register is loaded with all 0s. EX-

TEST allows circuitr y external to the Quad Por t package to be

teste d. Boun dary -scan reg ister cells a t output pins ar e used to

apply test stimuli, while those at input pins capture test results.

IDCODE

The IDCODE ins truction causes a vend or-spe cific , 32-bit code

to be loaded into the instruction register. It also places the

inst ruction regis ter b etween the TDI and TDO pi ns and al lows

the IDCODE t o be shi fted ou t of t he de vi ce whe n the TAP co n-

troller enters the Shift-DR state. The IDCODE instruction is

loaded into the instruction register upon power-up or whenever

the TAP controller is given a test logic reset sta te.

High-Z

The High-Z instruction causes the boundary scan register to

be connected between the TDI and TDO pins when the TAP

controller is in a Shift-DR state. It also places all QuadPort

outputs into a High-Z state.

SAMPLE / PRELOAD

SAMPLE / PRELOAD is a 1149.1 mandatory instruction.

When the SAMPLE / PRELOAD instructions loaded into the

instr uction regi ster and the TAP controller in the Capture-DR

state, a snapshot of data on the inputs and outp ut pins is cap-

tured in the boundary scan register.

The user must be aware that the TAP controller cl ock can only

oper ate at a f requency up to 10 MHz, while th e QuadP ort cloc k

operates more than an order of magnitude faster. Because

there is a large diff erence in the clock frequencies, it is possible

that during the Capture- DR state, an input or output wi ll under-

go a tr ans ition. The TAP ma y then try to capt ure a signa l whil e

in transition (metastable state). This will not harm the device,

bu t there is no guar antee as to the va lue that will be captured.

Repeatable results may not be possible.

To guarantee that the boundary scan register will capt ure the

correct value of a signal, the QuadPort signal must be stabi-

lized long enough to meet the TAP controller's capture set-up

plus hold times . Once the dat a is capt ured , it is pos sib le to s hift

out the data by putting the TAP into the Shift-DR state. This

places the boundar y scan regist er between the TDI and TDO

pins. If t he TAP controller goes into the Update-DR state, t he

sampled dat a will be updated.

BYPASS

When the BYPASS instructi on is loaded in the ins truc tion reg-

ister and the TAP is placed in a Shift-DR state, the bypass

tage of the BYPASS instruction is that it shortens the boundary

scan path when mul tiple devices are connected together on a

board.

CLAMP

The opt ional CLAMP i nstruct ion al lows t he sta te of t he sign als

driven from QuadPor t pins to be determined from the bound-

ary-scan regis ter whi le t he BYPASS regist er i s se lected as th e

seria l path be tween TDI and TDO. CLAMP cont rol s boundary

cell s to 1 o r 0.

Boundary Scan Cells (BSC)

Table 7 lists all QuadPort I/Os with their associated BSC. No-

tice that the cells have even numbers. Every I/O has two

boundary s can cells . Bidi rection al signal s (addre ss lines , data-

lines) require two cells so that one (the odd cell) is used to

control a thr ee-st ate buffer. Input only and output only si gnals

have an extra dummy cell (odd cells) that are used to ease

device l ayout.

CY7C0430V

PRELIMINARY

TA P C o n troller State D iagr am (F SM)[48]

Note:

48. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.

TEST-LOGIC

RESET

RUN_TEST/

IDLE SELECT

DR-SCAN

CAPTURE-DR

SHIFT-DR

EXIT1-DR

PAUSE-DR

EXIT2-DR

UPDATE-DR

SELECT

IR-SCAN

CAPTURE-IR

SHIFT-IR

EXIT1-IR

PAUSE-IR

EXIT2-IR

UPDATE-IR

CY7C0430V

PRELIMINARY

JTAG TAP Con trol l er B l o ck Diag r am

3 2 1 0

31 30 29 0

0391

Bypass Register ( BYR)

Instructi on Register (IR)

Identific ati on Register (IDR)

Boundary Scan Register (BSR)

TDI

Selection

Circuitry TDO

TCK

TMS TAP

CONTROLLER

MRST

(MUX)

CY7C0430V

PRELIMINARY

JTAG Timi ng Wavef orm

Tabl e 4. Iden tification Register Def initions

Instruc tion Field Value Description

Revision Nu mb er

(31:28) 1h Reser ved for ver sion number

Cypress Device ID

(27:12) C000h Defines Cypress part n um ber

Cypress JEDEC ID

(11:1) 34h Allows uni que ident ification of QuadPort v endor

ID Register Pr esence

(0) 1Indicate the presence of an ID re gister

Test Clock

Test M ode Select

TCK

TMS

Te st D ata-In

TDI

Test Data-Out

TDO

tTCYC

tTMSH

tTL

tTH

tTMSS

tTDIS tTDIH

tTDOX tTDOV

CY7C0430V

PRELIMINARY

Tabl e 5. Scan Registers Sizes

Instruction (IR) 4

Bypass (BYR) 1

Identificati on (I DR) 32

Boundary Scan (BSR) 392

Tabl e 6. Instructi on Identificat ion Codes

Instruction Code Description

EXTEST 0000 Captur es the I nput/Output ring contents . Places the bou ndary scan r egister

(BSR) between the TDI and TDO.

BYPASS 1111 Pl aces the bypass regis ter (BYR) between TDI and TDO .

IDCODE 0111 Lo ads the ID regist er (I DR) with t he v endor ID code a nd pl aces t he r egist er

between TDI and TDO .

HIGHZ 0110 Pl aces t he BYR betwe en TDI and TD O. F orces all Qua dPort output drivers

to a High-Z state.

CLAMP 0101 Controls boundary to 1/0. Uses BYR.

SAMPLE/PRELOAD 0001 Captures the Input/Out put ring content s. Pla ces the bou ndary sc an regist er

(BSR) bet ween TDI and TDO.

RESERVED All other codes Seven combinations are reserved. Do not use other than the above.

CY7C0430V

PRELIMINARY

Tabl e 7. Boundary Scan Order

Ce ll # Signal Name Bu mp (B a ll) ID

2A0_P4 K20

4A1_P4 J19

6A2_P4 J18

8A3_P4 H20

10 A4_P4 H19

12 A5_P4 G19

14 A6_P4 G18

16 A7_P4 F20

18 A8_P4 F19

20 A9_P4 F18

22 A10_P4 E20

24 A11_P4 E19

26 A12_P4 D19

28 A13_P4 D18

30 A14_P4 C20

32 A15_P4 C19

34 CNTINT_P4 F17

36 CNTRST_P4 K18

38 MKLD_P4 H18

40 CNTLD_P4 H17

42 CNTINC_P4 G17

44 CNTRD_P4 E17

46 MKRD_P4 E18

48 LB_P4 A20

50 UB_P4 B19

52 OE_P4 D17

54 R/W_P4 C16

56 CE1_P4 C18

58 CE0_P4 C17

60 INT_P4 K19

62 CLK_P4 K17

64 A0_P3 L20

66 A1_P3 M19

68 A2_P3 M18

70 A3_P3 N20

72 A4_P3 N19

74 A5_P3 P19

76 A6_P3 P18

78 A7_P3 R20

80 A8_P3 R19

82 A9_P3 R18

84 A10_P3 T20

86 A11_P3 T19

88 A12_P3 U19

90 A13_P3 U18

92 A14_P3 V20

94 A15_P3 V19

96 CNTINT_P3 R17

98 CNTRST_P3 L18

100 MKLD_P3 N18

102 CNTLD_P3 N17

104 CNTINC_P3 P17

106 CNTRD_P3 T17

108 MKRD_P3 T18

110 LB_P3 Y20

112 UB_P3 W19

114 OE_P3 U17

116 R/W_P3 V16

118 CE1_P3 V18

120 CE0_P3 V17

122 INT_P3 L19

124 CLK_P3 M17

126 IO0_P4 Y15

128 IO1_P4 W15

130 IO2_P4 Y16

132 IO3_P4 W16

134 IO4_P4 Y17

136 IO5_P4 W17

138 IO6_P4 Y18

140 IO7_P4 W18

142 IO8_P4 Y19

144 IO0_P3 V12

146 IO1_P3 Y11

148 IO2_P3 W12

150 IO3_P3 Y12

152 IO4_P3 W13

154 IO5_P3 Y13

156 IO6_P3 V15

158 IO7_P3 Y14

160 IO8_P3 W14

162 IO0_P1 Y6

164 IO1_P1 W6

Tabl e 7. Boundary Scan Order (continued)

Cell # Sign al Name Bump (Ball) ID

CY7C0430V

PRELIMINARY

166 IO2_P1 Y5

168 IO3_P1 W5

170 IO4_P1 Y4

172 IO5_P1 W4

174 IO6_P1 Y3

176 IO7_P1 W3

178 IO8_P1 Y2

180 IO0_P2 V9

182 IO1_P2 Y10

184 IO2_P2 W9

186 IO3_P2 Y9

188 IO4_P2 W8

190 IO5_P2 Y8

192 IO6_P2 V6

194 IO7_P2 Y7

196 IO8_P2 W7

198 A0_P2 L1

200 A1_P2 M2

202 A2_P2 M3

204 A3_P2 N1

206 A4_P2 N2

208 A5_P2 P2

210 A6_P2 P3

212 A7_P2 R1

214 A8_P2 R2

216 A9_P2 R3

218 A10_P2 T1

220 A11_P2 T2

222 A12_P2 U2

224 A13_P2 U3

226 A14_P2 V1

228 A15_P2 V2

230 CNTINT_P2 R4

232 CNTRST_P2 L3

234 MKLD_P2 N3

236 CNTLD_P2 N4

238 CNTINC_P2 P4

240 CNTRD_P2 T4

242 MKRD_P2 T3

244 LB_P2 Y1

246 UB_P2 W2

Tabl e 7. Boundary Scan Order (continued)

Ce ll # Signal Name Bu mp (B a ll) ID

248 OE_P2 U4

250 R/W_P2 V5

252 CE1_P2 V3

254 CE0_P2 V4

256 INT_P2 L2

258 CLK_P2 M4

260 A0_P1 K1

262 A1_P1 J2

264 A2_P1 J3

266 A3_P1 H1

268 A4_P1 H2

270 A5_P1 G2

272 A6_P1 G3

274 A7_P1 F1

276 A8_P1 F2

278 A9_P1 F3

280 A10_P1 E1

282 A11_P1 E2

284 A12_P1 D2

286 A13_P1 D3

288 A14_P1 C1

290 A15_P1 C2

292 CNTINT_P1 F4

294 CNTRST_P1 K3

296 MKLD_P1 H3

298 CNTLD_P1 H4

300 CNTINC_P1 G4

302 CNTRD_P1 E4

304 MKRD_P1 E3

306 LB_P1 A1

308 UB_P1 B2

310 OE_P1 D4

312 R/W_P1 C5

314 CE1_P1 C3

316 CE0_P1 C4

318 INT_P1 K2

320 CLK_P1 K4

322 IO9_P2 A6

324 IO10_P2 B6

326 IO11_P2 A5

328 IO12_P2 B5

Tabl e 7. Boundary Scan Order (continued)

Cell # Sign al Name Bump (Ball) ID

CY7C0430V

PRELIMINARY

330 IO13_P2 A4

332 IO14_P2 B4

334 IO15_P2 A3

336 IO16_P2 B3

338 IO17_P2 A2

340 IO9_P1 C9

342 IO10_P1 A10

344 IO11_P1 B9

346 IO12_P1 A9

348 IO13_P1 B8

350 IO14_P1 A8

352 IO15_P1 C6

354 IO16_P1 A7

356 IO17_P1 B7

358 IO9_P3 A15

360 IO10_P3 B15

362 IO11_P3 A16

364 IO12_P3 B16

366 IO13_P3 A17

368 IO14_P3 B17

370 IO15_P3 A18

372 IO16_P3 B18

374 IO17_P3 A19

376 IO9_P4 C12

378 IO10_P4 A11

380 IO11_P4 B12

382 IO12_P4 A12

384 IO13_P4 B13

386 IO14_P4 A13

388 IO15_P4 C15

390 IO16_P4 A14

392 IO17_P4 B14

Tabl e 7. Boundary Scan Order (continued)

Ce ll # Signal Name Bu mp (B a ll) ID

CY 7C0430V

PRELIMINARY

of any circui try other than circuitry embodied in a Cypress Semiconductor pr oduct. Nor does it conv ey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or fai lure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Orde ring Inform ation

Document #: 38-00882-*A

64K x 18 3.3V Synchronous QuadPort SRAM

Speed

(MHz) Ordering Code Package

Name P ackage Type Operating

Range

133 CY7C0430V-133BGC BG272 272-Ball Grid Array (BGA) Commerc ial

CY7C0430V- 133BG I BG272 272-Ball Grid Array (BGA) Industrial

100 CY7C0430V-100BGC BG272 272-Ball Grid Array (BGA) Commerc ial

CY7C0430V- 100BG I BG272 272-Ball Grid Array (BGA) Industrial

Package Diagram

272-Lead Ball Grid Array (27 x 27 x 2.33 mm) BG272

51-85130