LM4995, LM4995TMBD
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LM4995 1.3 W Audio Power Amplifier
Check for Samples: LM4995,LM4995TMBD
1FEATURES DESCRIPTION
The LM4995 is an audio power amplifier primarily
2• Available in Space-Saving 0.4mm Pitch designed for demanding applications in mobile
DSBGA Package phones and other portable communication device
• Ultra Low Current Shutdown Mode applications. It is capable of delivering 1.2W of
• BTL Output Can Drive Capacitive Loads continuous average power to an 8ΩBTL load with
less than 1% distortion (THD+N) from a 5VDC power
• Improved Click and Pop Circuitry Eliminates supply.
Noise during Turn-On and Turn-Off Transitions Boomer audio power amplifiers were designed
• 2.4 - 5.5V Operation specifically to provide high quality output power with a
• No Output Coupling Capacitors, Snubber minimal amount of external components. The
Networks or Bootstrap Capacitors Required LM4995 does not require output coupling capacitors
• Unity-Gain Stable or bootstrap capacitors, and therefore is ideally suited
for mobile phone and other low voltage applications
• External Gain Configuration Capability where minimal power consumption is a primary
• WSON Package: 0.5mm Pitch, 3 x 3 mm requirement.
The LM4995 features a low-power consumption
APPLICATIONS shutdown mode, which is achieved by driving the
• Mobile Phones shutdown pin with logic low. Additionally, the LM4995
• PDAs features an internal thermal shutdown protection
mechanism.
• Portable electronic devices The LM4995 contains advanced click and pop
KEY SPECIFICATIONS circuitry which eliminates noise which would
otherwise occur during turn-on and turn-off
• PSRR at 3.6V (217Hz & 1kHz): 75 dB transitions.
• Output Power at 5.0V, 1% THD+N, 8Ω:The LM4995 is unity-gain stable and can be
1.3 W (typ) configured by external gain-setting resistors.
• Output Power at 3.6V, 1% THD+N, 8Ω:
625 mW (typ)
• Shutdown Current: 0.01µA (typ)
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2006–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
A B C
-IN +IN
VO1
VO2
BYP
GND GND VDD
SHDN
3
2
1
1
2
3
4
8
7
6
5
SHUTDOWN
BYPASS
+IN
-IN
VO2
GND
VDD
VO1
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TYPICAL APPLICATION
Figure 1. Typical Audio Amplifier Application Circuit
CONNECTION DIAGRAM xxx
xxx
Figure 3. WSON (Top View)
See NGQ0008A Package
Figure 2. DSBGA (Top View)
See YFQ0009 Package
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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ABSOLUTE MAXIMUM RATINGS(1)(2)
Supply Voltage(3) 6.0V
Storage Temperature −65°C to +150°C
Input Voltage −0.3V to VDD +0.3V
Power Dissipation(4)(5) Internally Limited
ESD Susceptibility(6) 2000V
ESD Susceptibility(7) 200V
Junction Temperature 150°C
Thermal Resistance θJA (DSBGA) 96.5°C/W
θJA (WSON) 56°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensure for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) If the product is in Shutdown mode and VDD exceeds 6V (to a max of 8V VDD), then most of the excess current will flow through the
ESD protection circuits. If the source impedance limits the current to a max of 10mA, then the device will be protected. If the device is
enabled when VDD is greater than 5.5V and less than 6.5V, no damage will occur, although operation life will be reduced. Operation
above 6.5V with no current limit will result in permanent damage.
(4) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX,θJA, and the ambient temperature
TA. The maximum allowable power dissipation is PDMAX = (TJMAX–TA)/θJA or the number given in Absolute Maximum Ratings, whichever
is lower. For the LM4995, see power derating curves for additional information.
(5) Maximum power dissipation in the device (PDMAX) occurs at an output power level significantly below full output power. PDMAX can be
calculated using Equation 1 shown in the APPLICATION INFORMATION section. It may also be obtained from the power dissipation
graphs.
(6) Human body model, 100pF discharged through a 1.5kΩresistor.
(7) Machine Model, 220pF–240pF discharged through all pins.
OPERATING RATINGS
Temperature Range (TMIN ≤TA≤TMAX)−40°C ≤TA≤85°C
Supply Voltage 2.4V ≤VDD ≤5.5V
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ELECTRICAL CHARACTERISTICS VDD = 5V(1)(2)
The following specifications apply for the circuit shown in Figure 1, unless otherwise specified. Limits apply for TA= 25°C.
LM4995 Units
Symbol Parameter Conditions (Limits)
Typical(3) Limit(4)(5)
VIN = 0V, Io= 0A, No Load 1.5 2.5 mA (max)
IDD Quiescent Power Supply Current VIN = 0V, Io= 0A, 8ΩLoad 1.8 mA
ISD Shutdown Current VSD = VGND 0.01 1 µA (max)
VOS Output Offset Voltage No Load 5 26 mV (max)
PoOutput Power THD+N = 1% (max); f = 1 kHz 1.3 (TM) W
1.25 (SD)
TWU Wake-up time 165 ms
THD+N Total Harmonic Distortion + Noise Po= 500mWRMS; f = 1kHz 0.08 %
Vripple = 200mV sine p-p 73 (f = 217Hz)
PSRR Power Supply Rejection Ratio dB
Input terminated to GND 73 (f = 1kHz)
VSDIH Shutdown Voltage Input High 1.5 V
VSDIL Shutdown Voltage Input Low 1.2 V
(1) All voltages are measured with respect to the ground pin, unless otherwise specified.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensure for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(3) Typicals are measured at 25°C and represent the parametric norm.
(4) Limits are specified to AOQL (Average Outgoing Quality Level).
(5) Datasheet min/max specification limits are specified by design, test, or statistical analysis.
ELECTRICAL CHARACTERISTICS VDD = 3.6V(1)(2)
The following specifications apply for the circuit shown in Figure 1, unless otherwise specified. Limits apply for TA= 25°C.
LM4995 Units
Symbol Parameter Conditions (Limits)
Typical(3) Limit(4)(5)
VIN = 0V, Io= 0A, No Load 1.3 2.3 mA (max)
IDD Quiescent Power Supply Current VIN = 0V, Io= 0A, 8ΩLoad 1.6 mA
ISD Shutdown Current VSD = VGND 0.01 1 µA (max)
VOS Output Offset Voltage No Load 5 26 mV (max)
Output Power THD+N = 1% (max); f = 1 kHz 625 (TM) mW
Po610 (SD)
TWU Wake-up time 130 ms
THD+N Total Harmonic Distortion + Noise Po= 300mWRMS; f = 1kHz 0.07 %
Vripple = 200mV sine p-p 75 (f = 217Hz)
PSRR Power Supply Rejection Ratio dB
Input terminated to GND 76 (f = 1kHz)
VSDIH Shutdown Voltage Input High 1.3 V
VSDIL Shutdown Voltage Input Low 1 V
(1) All voltages are measured with respect to the ground pin, unless otherwise specified.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensure for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(3) Typicals are measured at 25°C and represent the parametric norm.
(4) Limits are specified to AOQL (Average Outgoing Quality Level).
(5) Datasheet min/max specification limits are specified by design, test, or statistical analysis.
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ELECTRICAL CHARACTERISTICS VDD = 3.0V(1)(2)
The following specifications apply for the circuit shown in Figure 1, unless otherwise specified. Limits apply for TA= 25°C.
LM4995 Units
Symbol Parameter Conditions (Limits)
Typical(3) Limit(4)(5)
VIN = 0V, Io= 0A, No Load 1.3 mA
IDD Quiescent Power Supply Current VIN = 0V, Io= 0A, 8ΩLoad 1.6 mA
ISD Shutdown Current VSD = VGND 0.01 µA
VOS Output Offset Voltage No Load 5 mV
PoOutput Power THD+N = 1% (max); f = 1 kHz 400 mW
TWU Wake-up time 110 ms
THD+N Total Harmonic Distortion + Noise Po= 250mWRMS; f = 1kHz 0.07 %
Vripple = 200mV sine p-p 74 (f = 217Hz)
PSRR Power Supply Rejection Ratio dB
Input terminated to GND 75 (f = 1kHz)
VSDIH Shutdown Voltage Input High 1.2 V
VSDIL Shutdown Voltage Input Low 1 V
(1) All voltages are measured with respect to the ground pin, unless otherwise specified.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensure for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(3) Typicals are measured at 25°C and represent the parametric norm.
(4) Limits are specified to AOQL (Average Outgoing Quality Level).
(5) Datasheet min/max specification limits are specified by design, test, or statistical analysis.
EXTERNAL COMPONENTS DESCRIPTION
(Figure 1)
Components Functional Description
1. RiInverting input resistance which sets the closed-loop gain in conjunction with Rf. This resistor also forms a high pass
filter with Ciat fC= 1/(2πRiCi).
2. CiInput coupling capacitor which blocks the DC voltage at the amplifiers input terminals. Also creates a highpass filter with
Riat fC= 1/(2πRiCi). Refer to the section, PROPER SELECTION OF EXTERNAL COMPONENTS, for an explanation
of how to determine the value of Ci.
3. RfFeedback resistance which sets the closed-loop gain in conjunction with Ri.
4. CSSupply bypass capacitor which provides power supply filtering. Refer to the POWER SUPPLY BYPASSING section for
information concerning proper placement and selection of the supply bypass capacitor.
5. CBBypass pin capacitor which provides half-supply filtering. Refer to the section, PROPER SELECTION OF EXTERNAL
COMPONENTS, for information concerning proper placement and selection of CB.
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0.01
10
0.02
0.05
0.1
0.2
0.5
1
2
5
THD+N (%)
20 20k50 100 200 500 1k 2k 5k 10k
FREQUENCY (Hz)
0.01
10
0.02
0.05
0.1
0.2
0.5
1
2
5
0.01
10
0.02
0.05
0.1
0.2
0.5
1
2
5
THD+N (%)
20 20k50 100 200 500 1k 2k 5k 10k
FREQUENCY (Hz)
0.01
10
0.02
0.05
0.1
0.2
0.5
1
2
5
0.01
10
0.02
0.05
0.1
0.2
0.5
1
2
5
20 20k50 100 200 500 1k 2k 5k 10k
FREQUENCY (Hz)
0.01
10
0.02
0.05
0.1
0.2
0.5
1
2
5
THD+N (%)
20 200050 100 200 500 1000
0.01
10
0.02
0.05
0.1
0.2
0.5
1
2
5
0.01
10
0.02
0.05
0.1
0.2
0.5
1
2
5
THD+N (%)
OUTPUT POWER (mW)
10 100020 50 100 200 500
0.01
10
0.02
0.05
0.1
0.2
0.5
1
2
5
0.01
10
0.02
0.05
0.1
0.2
0.5
1
2
5
THD+N (%)
OUTPUT POWER (mW)
10 100020 50 100 200 500
0.01
10
0.02
0.05
0.1
0.2
0.5
1
2
5
0.01
10
0.02
0.05
0.1
0.2
0.5
1
2
5
THD+N (%)
OUTPUT POWER (mW)
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TYPICAL PERFORMANCE CHARACTERISTICS
THD+N vs Output Power THD+N vs Output Power
VDD = 3V, RL= 8ΩVDD = 3.6V, RL= 8Ω
Figure 4. Figure 5.
THD+N vs Frequency
THD+N vs Output Power VDD = 3V, RL= 8Ω,
VDD = 5V, RL= 8Ωf = 1kHz, PO= 250mW
Figure 6. Figure 7.
THD+N vs Frequency THD+N vs Frequency
VDD = 3.6V, RL= 8Ω, VDD = 5V, RL= 8Ω,
f = 1kHz, PO= 300mW f = 1kHz, PO= 500mW
Figure 8. Figure 9.
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OUTPUT POWER (mW)
0 200 400 600 800 1000 1200
POWER DISSIPATION (mW)
0
100
400
500
600
700
300
200
OUTPUT POWER (mW)
0 100 200 300 400 500 600
POWER DISSIPATION (mW)
0
50
200
250
300
350
150
100
FREQUENCY (Hz)
-100
0
-90
-80
-70
-60
-50
-40
-30
-20
-10
50 100 200 500 1k 2k 5k 10k
PSRR (dB)
OUTPUT POWER (mW)
0 50 100 150 200 250 300 350
POWER DISSIPATION (mW)
0
50
100
150
200
250
-100
0
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k50 100 200 500 1k 2k 5k 10k
FREQUENCY (Hz)
PSRR (dB)
-100
0
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k50 100 200 500 1k 2k 5k 10k
FREQUENCY (Hz)
PSRR (dB)
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
PSRR vs Frequency PSRR vs Frequency
VDD = 3V, RL= 8ΩVDD = 3.6V, RL= 8Ω
Figure 10. Figure 11.
PSRR vs Frequency Power Dissipation vs Output Power
VDD = 5V, RL= 8ΩVDD = 3V, RL= 8Ω
Figure 12. Figure 13.
Power Dissipation vs Output Power Power Dissipation vs Output Power
VDD = 3.6V, RL= 8ΩVDD = 5V, RL= 8Ω
Figure 14. Figure 15.
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SHUTDOWN VOLTAGE (V)
SUPPLY CURRENT (mA)
0
100
10
20
30
40
50
60
70
80
90
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
SHUTDOWN VOLTAGE (V)
SUPPLY CURRENT (mA)
0
100
10
20
30
40
50
60
70
80
90
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
SHUTDOWN VOLTAGE (V)
SUPPLY CURRENT (mA)
0
100
10
20
30
40
50
60
70
80
90
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
SHUTDOWN VOLTAGE (V)
SUPPLY CURRENT (mA)
0
100
10
20
30
40
50
60
70
80
90
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
SHUTDOWN VOLTAGE (V)
SUPPLY CURRENT (mA)
0
100
10
20
30
40
50
60
70
80
90
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
OUTPUT LEVEL (dB)
20k50 1k 2k 5k 10k
FREQUENCY (Hz)
20 500200100
Ci = 0.33PF (tantulum)
Ci = 1PF (tantulum) Ci = 1PF (ceramic)
-10
+1
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Output Level vs Frequency Response Shutdown Voltage VSDIH
(Three different caps) VDD = 3V
Figure 16. Figure 17.
Shutdown Voltage VSDIH Shutdown Voltage VSDIH
VDD = 3.6V VDD = 5V
Figure 18. Figure 19.
Shutdown Voltage VSDIL Shutdown Voltage VSDIL
VDD = 3V VDD = 3.6V
Figure 20. Figure 21.
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SHUTDOWN VOLTAGE (V)
SUPPLY CURRENT (mA)
0
100
10
20
30
40
50
60
70
80
90
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
VOLTAGE SUPPLY (V)
2.0 3.0 4.0 5.0 6.0
OUTPUT POWER (mW)
0
200
400
600
800
1000
1200
1400
1600
1800
2000
THD+N = 10%
THD+N = 1%
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Shutdown Voltage VSDIL Output Power vs Supply Voltage
VDD = 5V RL= 8Ω
Figure 22. Figure 23.
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APPLICATION INFORMATION
BRIDGE CONFIGURATION EXPLANATION
As shown in Figure 1, the LM4995 has two internal operational amplifiers. The first amplifier's gain is externally
configurable, while the second amplifier is internally fixed in a unity-gain, inverting configuration. The closed-loop
gain of the first amplifier is set by selecting the ratio of Rfto Riwhile the second amplifier's gain is fixed by the
two internal 20kΩresistors. Figure 1 shows that the output of amplifier one serves as the input to amplifier two
which results in both amplifiers producing signals identical in magnitude, but out of phase by 180°. Consequently,
the differential gain for the IC is
AVD= 2 *(Rf/Ri) (1)
By driving the load differentially through outputs Vo1 and Vo2, an amplifier configuration commonly referred to as
“bridged mode” is established. Bridged mode operation is different from the classical single-ended amplifier
configuration where one side of the load is connected to ground.
A bridge amplifier design has a few distinct advantages over the single-ended configuration, as it provides
differential drive to the load, thus doubling output swing for a specified supply voltage. Four times the output
power is possible as compared to a single-ended amplifier under the same conditions. This increase in attainable
output power assumes that the amplifier is not current limited or clipped. In order to choose an amplifier's closed-
loop gain without causing excessive clipping, please refer to the AUDIO POWER AMPLIFIER DESIGN section.
A bridge configuration, such as the one used in LM4995, also creates a second advantage over single-ended
amplifiers. Since the differential outputs, Vo1 and Vo2, are biased at half-supply, no net DC voltage exists across
the load. This eliminates the need for an output coupling capacitor which is required in a single supply, single-
ended amplifier configuration. Without an output coupling capacitor, the half-supply bias across the load would
result in both increased internal IC power dissipation and also possible loudspeaker damage.
POWER DISSIPATION
Power dissipation is a major concern when designing a successful amplifier, whether the amplifier is bridged or
single-ended. A direct consequence of the increased power delivered to the load by a bridge amplifier is an
increase in internal power dissipation. Since the LM4995 has two operational amplifiers in one package, the
maximum internal power dissipation is 4 times that of a single-ended amplifier. The maximum power dissipation
for a given application can be derived from the power dissipation graphs or from Equation (1).
PDMAX = 4*(VDD)2/(2π2RL) (2)
It is critical that the maximum junction temperature TJMAX of 150°C is not exceeded. TJMAX can be determined
from the power derating curves by using PDMAX and the PC board foil area. By adding copper foil, the thermal
resistance of the application can be reduced from the free air value of θJA, resulting in higher PDMAX values
without thermal shutdown protection circuitry being activated. Additional copper foil can be added to any of the
leads connected to the LM4995. It is especially effective when connected to VDD, GND, and the output pins.
Refer to the application information on the LM4995 reference design board for an example of good heat sinking.
If TJMAX still exceeds 150°C, then additional changes must be made. These changes can include reduced supply
voltage, higher load impedance, or reduced ambient temperature. Internal power dissipation is a function of
output power. Refer to the TYPICAL PERFORMANCE CHARACTERISTICS curves for power dissipation
information for different output powers and output loading.
POWER SUPPLY BYPASSING
As with any amplifier, proper supply bypassing is critical for low noise performance and high supply rejection.
The capacitor location on both the bypass and power supply pins should be as close to the device as possible. A
ceramic 0.1μF placed in parallel with the tantalum 2.2μF bypass (CB) capacitor will aid in supply stability. This
does not eliminate the need for bypassing the power supply pins of the LM4995. The selection of a bypass
capacitor, especially CB, is dependent upon PSRR requirements, click and pop performance (as explained in the
section, PROPER SELECTION OF EXTERNAL COMPONENTS), system cost, and size constraints.
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SHUTDOWN FUNCTION
In order to reduce power consumption while not in use, the LM4995 contains shutdown circuitry that is used to
turn off the amplifier's bias circuitry. This shutdown feature turns the amplifier off when logic low is placed on the
shutdown pin. By switching the shutdown pin to GND, the LM4995 supply current draw will be minimized in idle
mode. Idle current is measured with the shutdown pin connected to GND. The trigger point for shutdown is
shown as a typical value in the Shutdown Hysteresis Voltage graphs in the TYPICAL PERFORMANCE
CHARACTERISTICS section. It is best to switch between ground and supply for maximum performance. While
the device may be disabled with shutdown voltages in between ground and supply, the idle current may be
greater than the typical value of 0.01µA. In either case, the shutdown pin should be tied to a definite voltage to
avoid unwanted state changes.
In many applications, a microcontroller or microprocessor output is used to control the shutdown circuitry, which
provides a quick, smooth transition to shutdown. Another solution is to use a single-throw switch in conjunction
with an external pull-up resistor. This scheme ensures that the shutdown pin will not float, thus preventing
unwanted state changes.
PROPER SELECTION OF EXTERNAL COMPONENTS
Proper selection of external components in applications using integrated power amplifiers is critical to optimize
device and system performance. While the LM4995 is tolerant of external component combinations,
consideration to component values must be used to maximize overall system quality.
The LM4995 is unity-gain stable which gives the designer maximum system flexibility. The LM4995 should be
used in low gain configurations to minimize THD+N values, and maximize the signal to noise ratio. Low gain
configurations require large input signals to obtain a given output power. Input signals equal to or greater than 1
Vrms are available from sources such as audio codecs. Please refer to the section, AUDIO POWER AMPLIFIER
DESIGN, for a more complete explanation of proper gain selection.
Besides gain, one of the major considerations is the closed-loop bandwidth of the amplifier. To a large extent, the
bandwidth is dictated by the choice of external components shown in Figure 1. The input coupling capacitor, Ci,
forms a first order high pass filter which limits low frequency response. This value should be chosen based on
needed frequency response for a few distinct reasons.
SELECTION OF INPUT CAPACITOR SIZE
Large input capacitors are both expensive and space hungry for portable designs. Clearly, a certain sized
capacitor is needed to couple in low frequencies without severe attenuation. But in many cases the speakers
used in portable systems, whether internal or external, have little ability to reproduce signals below 100Hz to
150Hz. Thus, using a large input capacitor may not increase actual system performance.
In addition to system cost and size, click and pop performance is effected by the size of the input coupling
capacitor, Ci. A larger input coupling capacitor requires more charge to reach its quiescent DC voltage (nominally
1/2 VDD). This charge comes from the output via the feedback and is apt to create pops upon device enable.
Thus, by minimizing the capacitor size based on necessary low frequency response, turn-on pops can be
minimized.
Besides minimizing the input capacitor size, careful consideration should be paid to the bypass capacitor value.
Bypass capacitor, CB, is the most critical component to minimize turn-on pops since it determines how fast the
LM4995 turns on. The slower the LM4995's outputs ramp to their quiescent DC voltage (nominally 1/2 VDD), the
smaller the turn-on pop. Choosing CBequal to 1.0µF along with a small value of Ci(in the range of 0.1µF to
0.39µF), should produce a virtually clickless and popless shutdown function. While the device will function
properly, (no oscillations or motorboating), with CBequal to 0.1µF, the device will be much more susceptible to
turn-on clicks and pops. Thus, a value of CBequal to 1.0µF is recommended in all but the most cost sensitive
designs.
Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: LM4995 LM4995TMBD
LM4995, LM4995TMBD
SNAS329G –APRIL 2006–REVISED APRIL 2013
www.ti.com
AUDIO POWER AMPLIFIER DESIGN
A 1W/8ΩAUDIO AMPLIFIER
Given:
Power Output 1 Wrms
Load Impedance 8Ω
Input Level 1 Vrms
Input Impedance 20 kΩ
Bandwidth 100 Hz–20 kHz ± 0.25 dB
A designer must first determine the minimum supply rail to obtain the specified output power. By extrapolating
from the Output Power vs Supply Voltage graphs in the TYPICAL PERFORMANCE CHARACTERISTICS
section, the supply rail can be easily found.
5V is a standard voltage in most applications, it is chosen for the supply rail. Extra supply voltage creates
headroom that allows the LM4995 to reproduce peaks in excess of 1W without producing audible distortion. At
this time, the designer must make sure that the power supply choice along with the output impedance does not
violate the conditions explained in the POWER DISSIPATION section.
Once the power dissipation equations have been addressed, the required differential gain can be determined
from Equation (3).
(3)
Rf/Ri= AVD/2 (4)
From Equation (3), the minimum AVD is 2.83; use AVD = 3.
Since the desired input impedance was 20 kΩ, and with a AVD impedance of 2, a ratio of 1.5:1 of Rfto Riresults
in an allocation of Ri= 20 kΩand Rf= 30 kΩ. The final design step is to address the bandwidth requirements
which must be stated as a pair of −3 dB frequency points. Five times away from a −3 dB point is 0.17 dB down
from passband response which is better than the required ±0.25 dB specified.
fL= 100Hz/5 = 20Hz
fH= 20kHz * 5 = 100kHz
As stated in the EXTERNAL COMPONENTS DESCRIPTION section, Riin conjunction with Cicreate a highpass
filter.
Ci≥1/(2π*20 kΩ*20 Hz) = 0.397 µF; use 0.39 µF
The high frequency pole is determined by the product of the desired frequency pole, fH, and the differential gain,
AVD. With a AVD = 3 and fH= 100kHz, the resulting GBWP = 300kHz which is much smaller than the LM4995
GBWP of 2.5MHz. This figure displays that if a designer has a need to design an amplifier with a higher
differential gain, the LM4995 can still be used without running into bandwidth limitations.
The LM4995 is unity-gain stable and requires no external components besides gain-setting resistors, an input
coupling capacitor, and proper supply bypassing in the typical application. However, if a closed-loop differential
gain of greater than 10 is required, a feedback capacitor (C4) may be needed as shown in Figure 24 to
bandwidth limit the amplifier. This feedback capacitor creates a low pass filter that eliminates possible high
frequency oscillations. Care should be taken when calculating the -3dB frequency in that an incorrect
combination of R3and C4will cause rolloff before 20kHz. A typical combination of feedback resistor and
capacitor that will not produce audio band high frequency rolloff is R3= 20kΩand C4= 25pf. These components
result in a -3dB point of approximately 320kHz.
12 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LM4995 LM4995TMBD
LM4995, LM4995TMBD
SNAS329G –APRIL 2006–REVISED APRIL 2013
www.ti.com
Figure 26. REFERENCE DESIGN BOARD SCHEMATIC
PCB LAYOUT GUIDELINES
This section provides practical guidelines for mixed signal PCB layout that involves various digital/analog power
and ground traces. Designers should note that these are only "rule-of-thumb" recommendations and the actual
results will depend heavily on the final layout.
GENERAL MIXED SIGNAL LAYOUT RECOMMENDATION
POWER AND GROUND CIRCUITS
For 2 layer mixed signal design, it is important to isolate the digital power and ground trace paths from the
analog power and ground trace paths. Star trace routing techniques (bringing individual traces back to a central
point rather than daisy chaining traces together in a serial manner) can have a major impact on low level signal
performance. Star trace routing refers to using individual traces to feed power and ground to each circuit or even
device. This technique will require a greater amount of design time but will not increase the final price of the
board. The only extra parts required will be some jumpers.
SINGLE-POINT POWER / GROUND CONNECTIONS
The analog power traces should be connected to the digital traces through a single point (link). A "Pi-filter" can
be helpful in minimizing High Frequency noise coupling between the analog and digital sections. It is further
recommended to put digital and analog power traces over the corresponding digital and analog ground traces to
minimize noise coupling.
PLACEMENT OF DIGITAL AND ANALOG COMPONENTS
All digital components and high-speed digital signal traces should be located as far away as possible from analog
components and circuit traces.
AVOIDING TYPICAL DESIGN / LAYOUT PROBLEMS
Avoid ground loops or running digital and analog traces parallel to each other (side-by-side) on the same PCB
layer. When traces must cross over each other do it at 90 degrees. Running digital and analog traces at 90
degrees to each other from the top to the bottom side as much as possible will minimize capacitive noise
coupling and cross talk.
14 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LM4995 LM4995TMBD
LM4995, LM4995TMBD
www.ti.com
SNAS329G –APRIL 2006–REVISED APRIL 2013
REVISION HISTORY
Rev Date Description
1.0 04/05/06 Initial WEB released of the datasheet.
1.1 05/17/06 Added the SD package.
1.2 08/07/06 Text edits.
1.3 08/22/06 Edited the THD+N Typical values on the 3
EC tables, then re-released the D/S to the
WEB (per Allan S.).
1.4 09/11/07 Updated the SD pkg. diagram.
Changes from Revision F (April 2013) to Revision G Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 14
Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LM4995 LM4995TMBD
PACKAGE OPTION ADDENDUM
www.ti.com 20-Jan-2017
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM4995SD/NOPB ACTIVE WSON NGQ 8 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM L4995
LM4995TM/NOPB ACTIVE DSBGA YFQ 9 250 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 G
G8
LM4995TMX/NOPB ACTIVE DSBGA YFQ 9 3000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 G
G8
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
PACKAGE OPTION ADDENDUM
www.ti.com 20-Jan-2017
Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM4995SD/NOPB WSON NGQ 8 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1
LM4995TM/NOPB DSBGA YFQ 9 250 178.0 8.4 1.35 1.35 0.76 4.0 8.0 Q1
LM4995TMX/NOPB DSBGA YFQ 9 3000 178.0 8.4 1.35 1.35 0.76 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Oct-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM4995SD/NOPB WSON NGQ 8 1000 210.0 185.0 35.0
LM4995TM/NOPB DSBGA YFQ 9 250 210.0 185.0 35.0
LM4995TMX/NOPB DSBGA YFQ 9 3000 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Oct-2013
Pack Materials-Page 2
MECHANICAL DATA
YFQ0009xxx
www.ti.com
TMD09XXX (Rev A)
E
0.600±0.075
D
A
. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
NOTES:
4215077/A 12/12
D: Max =
E: Max =
1.24 mm, Min =
1.24 mm, Min =
1.18 mm
1.18 mm
www.ti.com
PACKAGE OUTLINE
C
8X 0.3
0.2
2 0.1
8X 0.5
0.3
2X
1.5
1.6 0.1
6X 0.5
0.8
0.7
0.05
0.00
B3.1
2.9 A
3.1
2.9
(0.1) TYP
WSON - 0.8 mm max heightNGQ0008A
PLASTIC SMALL OUTLINE - NO LEAD
4214922/A 03/2018
PIN 1 INDEX AREA
SEATING PLANE
0.08 C
1
45
8
PIN 1 ID 0.1 C A B
0.05 C
THERMAL PAD
EXPOSED
9
SYMM
SYMM
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
(1.6)
6X (0.5)
(2.8)
8X (0.25)
8X (0.6)
(2)
(R0.05) TYP ( 0.2) VIA
TYP
(0.75)
WSON - 0.8 mm max heightNGQ0008A
PLASTIC SMALL OUTLINE - NO LEAD
4214922/A 03/2018
SYMM
1
45
8
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
9
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
SOLDER MASK
OPENING
SOLDER MASK
METAL UNDER
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
8X (0.25)
8X (0.6)
6X (0.5)
(1.79)
(1.47)
(2.8)
(R0.05) TYP
WSON - 0.8 mm max heightNGQ0008A
PLASTIC SMALL OUTLINE - NO LEAD
4214922/A 03/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD 9:
82% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
SYMM
1
45
8
SYMM
METAL
TYP
9
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