STA120DJ - STMICROELECTRONICS

1/15

STA120

December 2002

■MONOLITHIC CMOS RECEIVER

■3.3V SU PPL Y VO L TAG E

■LOW-JITTER, ON-CHIP CLOCK RECOVERY

256xFs OU TP UT CLOC K PROV I DED

■SUPP ORT S: AES/EBU, IEC 958, S/PD IF, &

EI AJ CP- 3 4 0/ 1201 PROF ESSIO NAL AND

CONSUMER FORMATS

■EXTENSIVE ER ROR REPORTI N G REPEAT

LA S T S A MP LE ON ERROR OPTION

DESCRIPTION

The STA120 is a monolithic CMOS device that re-

ceives and decodes audio data according to the

AES/EBU, IEC 9 5 8, S/PDIF, & EI AJ C P-340/120 1

interface standards.

The STA120 recovers the clock and synchroniza-

tion signals and de-multipl exes the audi o and dig-

ital data. Differential or single ended inputs can be

decoded.

The STA120 de-multiplexes the channel, user and

validity data directly to serial output pins with ded-

icated output pins for the most important channel

status bits.

SO28

ORDERING NUMBER: STA120D

DIGI TAL AUDIO INTERFACE RECEIVER

BLOCK DIAGRAM

AUDIO

SERIAL PORT

REGISTERS

DE MUX

CLOCK & DATA

RECOVERY

C0/E0

M2 M0AGNDFILT

SDATA

SCK

FSYNC

VREF

ERF CBL

RXP 9

25 15

2318

D97AU613A

VA+ MCK

DGNDVD+

19212022

RS422

Receiver

RXN 10

MUX

CS12/FCK

SEL

MUX

Ca/E1

Cb/E2

Cc/F0

Cd/F1

Ce/F2

STA120

2/15

ABSOLUTE MAXIMUM RATINGS

PIN CONNECTIONS (Top view)

Symbol Parameter Value Unit

D+

, V

A+

Power Supply Voltage 4 V

Input Voltage ( excluding pins 9, 10) -0.3 to V

+ +0.3 V

amb

Ambient Operating Temperature (power applied) -30 to +85 °C

stg

Storage Temperature -40 to 150 °C

PINS DESCRIPTION

N. Name Description

Power Supply

D+

Positive Digital Power.Positive supply for the digital section. Nominally 3.3V.

8 DGND Digital Ground.Ground for the digital section.

21 AGND Analog Ground.Ground for the analog section. AGND should be connected to same ground as

DGND.

22 V

A+

Positive Analog Power.Positive supply for the analog section. Nominally 3.3V.

Audio Output Interface

11 FSYNC Frame Sync.Delineates the serial data and may indicate the particular channel, left or right and

may be an input or output. The format is based on M0, M1, M2 and M3 pins.

12 SCK Serial Clock.Serial clock for SDATA pin which can be configured (via the M0, M1, M2 and M3

pins) as an input or output and can sample data on the rising or falling edge. As an output, SCK

will generate 32 clocks for every audio sample. As an input, 32 SCK periods per audio sample

must be provided in all normal modes.

17, 18,

23, 24 M2, M3,

M1, M0 Serial Port Mode Selects.Selects the format of Fsync and the sample edge of SCK with respect

to SDATA.

26 SDATA Serial Data. Audio data serial output pin.

C0/E0

VD+

DGND

RXP

RXN

SCK

FSYNC

CS12/FCK

CBL

SEL

MCK

FILT

AGND

VA+

M023

D97AU609A

Cd/F1

Cc/F0

Cb/E2

Ca/E1 M1

ERF

SDATA

Ce/F2

VERF

3/15

STA120

Control Pins

1 C Channel S tatus Outpu t. Received chann el status bit serial ou tput por t. FSYN C may b e used to

latch this bit externally. Except in I2S modes when this pin is updated at the active edge off

Fsync.

2 Cd Channel Sta tus Output Bits.Thes e pin are dual Function with the "C" bits selected when SEL is

high. Channel status information is displayed for the channel selected by CS12. C0, which is

channel status bit 0, defines professional (C0 = 0) or consumer (C0 = 1) mode and further

controls the definition of the Ca-Ce pins. These pins are updated with the rising edge of CBL.

F1 Frequency reporting Bits.Encoder sample frequency information that is enabled by bringing SEL

low. A proper clock on FCK must be input for at least two thirds of a channel status block for

these pins to be valid. They are updated three times per block, starting at the block boundary.

3 C c Channel Sta tus Output Bits.Thes e pin are dual Function with the "C" bits selected when SEL is

high. Channel status information is displayed for the channel selected by CS12. C0, which is

channel status bit 0, defines professional (C0 = 0) or consumer (C0 = 1) mode and further

controls the definition of the Ca-Ce pins. These pins are updated with the rising edge of CBL.

F0 Frequency reporting Bits.Encoded sample frequency information that is enabled by bringing SEL

low. A proper clock on FCK must be input for at least two thirds of a channel status block for

these pins to be valid. They are updated three times per block, starting at the block boundary.

4 Cb Channel Sta tus Output Bits.Thes e pin are dual Function with the "C" bits selected when SEL is

high. Channel status information is displayed for the channel selected by CS12. C0, which is

channel status bit 0, defines professional (C0 = 0) or consumer (C0 = 1) mode and further

controls the definition of the Ca-Ce pins. These pins are updated with the rising edge of CBL.

E2 Erro r Co nditio n.En coded err or in for mat ion t hat is en abled by br ing ing SEL low. The erro r cod es

are pr ior itized and latch ed so that th e erro r code disp layed is the h ighes t level of error since the

last clearing of the error pins. Clearing is accomplished by bringing SEL high for more than 8

MCK cycles.

5 Ca Channel Sta tus Output Bits.Thes e pin are dual Function with the "C" bits selected when SEL is

high. Channel status information is displayed for the channel selected by CS12. C0, which is

channel status bit 0, defines professional (C0 = 0) or consumer (C0 = 1) mode and further

controls the definition of the Ca-Ce pins. These pins are updated with the rising edge of CBL.

5 E 2 Erro r Co nditio n.En coded err or in for mat ion t hat is en abled by br ing ing SEL low. The erro r cod es

are pr ior itized and latch ed so that th e erro r code disp layed is the h ighes t level of error since the

last clearing of the error pins. Clearing is accomplished by bringing SEL high for more than 8

MCK cycles.

6C0

Channel Sta tus Output Bits.Thes e pin are dual Function with the "C" bits selected when SEL is

high. Channel status information is displayed for the channel selected by CS12. C0, which is

channel status bit 0, defines professional (C0 = 0) or consumer (C0 = 1) mode and further

controls the definition of the Ca-Ce pins. These pins are updated with the rising edge of CBL.

E0 Erro r Co nditio n.En coded err or in for mat ion t hat is en abled by br ing ing SEL low. The erro r cod es

are pr ior itized and latch ed so that th e erro r code disp layed is the h ighes t level of error since the

last clearing of the error pins. Clearing is accomplished by bringing SEL high for more than 8

MCK cycles.

13 CS12 Channel Select.This pin is also dual function and is selected by bringing SEL high. CS12 selects

sub-frame1 (when low) or sub- frame2 (wh en high ) to be displayed by channe l status pin s C0 an

Ca through Ce.

FCK F requency Clock.F requency Clock input that is enabled by bringing SEL low. FCK is compared to

the received clock frequ ency with the value dis played on F2 through F0. Nominal in put val ue is

6.144MHz.

14 U User Bit.Received user bit serial output port, FSYNC may be used to latch this bit externally.

Except in I2S modes when this pin is updated at the active edge off Fsync.

15 CBL Channel Status Block Start.The channel status block output is high for the first four bytes of

channel status and low for the last 20 bytes.

PINS DESCRIPTION (continued)

N. Name Description

STA120

4/15

DIGITAL CHARACTER ISTICS (T

amb

= 25°C; V

D+

, V

A+

= 3.3V ±1 0%)

Note 1: FS i s defined as the incomi ng audio sample frequency per channel.

SWITCHING CHARACTERISTICS - SERIAL PORTS (T

amb

= 25°C; V

D+

, V

A+

= 3.3V ±10%)

No te 2: The ou tput w ord r ate , O WR, re fers to the f r equenc y at whic h an au dio sam ple is outp ut f ro m the p art. (A ster eo pai r i s tw o aud io

sam pl es). Th erefore, in Mast er m ode, t here are always 3 2 SCK peri ods in one audi o sampl e. I n Slave mode 32 SC K periods must

be provided in most serial port formats.

16 SEL Select.Control pin that selects either channel status information (SEL = 1) or error and frequency

information (SEL = 0) to be displayed on six (C0, Ca Cb, Cc, Cd, Ce) pins.

27 Ce Channel Sta tus Output Bits.Thes e pin are dual Function with the "C" bits selected when SEL is

high. Channel status information is displayed for the channel selected by CS12. C0, which is

channel status bit 0, defines professional (C0 = 0) or consumer (C0 = 1) mode and further

controls the definition of the Ca-Ce pins. These pins are updated with the rising edge of CBL.

F2 Frequency reporting Bits.Encoded sample frequency information that is enabled by bringing SEL

low. A proper clock on FCK must be input for at least two thirds of a channel status block for

these pins to be valid. They are updated three times per block, starting at the block boundary.

28 VERF Validity + Erro r Flag. A logic al OR'ing of the validity bit from the rece ived data and the erro r flag.

May be used by interpolation filters to interpolate through errors.

Receiver Interface

9 RXP Line Receiver. (RS422 compatible)

10 RXN Line Receiver. (RS422 compatible)

Phase Locked Loop

19 MCK Master Clock.Low Jitter clock output of 256 times the received sample frequency.

20 FILT Filter.An external 330 Ohm resistor and 0.47µF capacitor in parallel with a 15nF capacitor is

required from FILT pin to analog ground.

25 E RF Error Flag,Signals that an error has occurred while receiving the audio sample currently being

read from the serial port. Three errors cause ERF to go high: a parity or biphase coding violation

during the current sample, or an out of lock PLL receiver.

Symbol Parameter Test Condition Min. Typ. Max. Unit

D+

A+

Power supply voltage Range 3.0 3.3 3.6 V

High-Level Input Voltage 2.0 V

Low-Level Input Voltage +0.8 V

High-Level Output Voltage I

= 200µA

-1.0

Low-Level Output Voltage I

= 3.2mA 0.4 V

I nput Leaka ge Curren t 1.0 10 µA

Input Sample Frequency (Note 1) 25 96 kHz

MCK Master Clock frequency (Note 1) 6.4

256xFS

25 MHz

MCK Clock Jitter 300

ps RMS

MCK Duty Cycle (high time/cycle time) 50 %

dd_ST

Static I

(MCK = 0) 0.1 1 mA

dd_DYN

Dynamic Idd 6 15 mA

Symbol Parameter Test Condition Min. Typ. Max. Unit

sck

SCK Frequency (Note 2) OWRx32 Hz

PINS DESCRIPTION (continued)

N. Name Description

5/15

STA120

Figure 1. Circuit Diagram

GENERAL DESCRIPTION

The STA 120 is a m onolithic CMO S circuit that receives a nd dec od es audio and digital d ata ac cord ing to

the AES/EBU, IEC 958, S/PDIF, and EIAJ CP-340/1201 interface stand ards.

It contains a RS422 line recei ver and P hase-Locked Loops (P LL) that recov ers t he clock and s ynchroni-

zation signals and de-multiplexes the audio and digital data. The STA120 de-multiplexes the channel sta-

tus, user and validity informa tion direct ly to serial output pins with dedicated pi ns for the m ost important

channel status bits.

Line Receiver

The line receiver can decode di fferential as well as single ende d inputs. The receiver cons its of a differ-

ential input Schmitt trigger with 50mV of hysteresis. The hysteresis prevents noisy signals from corrupting

the pha se detector. A ppendi x A contains m ore informa tion on how t o co nfigure the line rec ei vers for di f-

ferential and single ended signals.

Clocks and Jitter Attenuation

The primary function of this chip is to recover a udio data and l ow jitter clocks from a digital audio trans-

mission line. The clocks that can be generated are MCK (256xFS), SCK (64xFS), and FSYNC (FS or

2xFS). MCK is the out put of the v oltage control led oscillator which is a compo nent of th e PLL. Th e PLL

consists of phase and frequency detectors, a second-order loop filter, and a voltage controlled oscillator.

All components of the PLL are on chip with the exception of a resistor and capacitors used in the loop filter.

This filter is connected between t he FILT pin an d A GND. The c losed-loop transfer func tion, which spec i-

fies the PLL 's jitter attenuation characte ristics, is shown in Figure 2.

The loop will begin to attenuate jitter at ap proximately 25kHz w ith another pole at 80kHz and will have

50dB of attenuation by 1MHz. Since most data jitter introduced by the transmission line is high in frequen-

cy, it will be strongly attenuated.

Multiple frequency detectors are used to minimize th e time it takes the P LL to lock to the inc oming data

stream and to prevent false lock conditions. When the PLL is not locked to the incoming data stream, the

10 AUDIO

DATA

PROCESSOR

µCONTROLLER

LOGIC

RECEIVER

CIRCUIT

(See Appendix A) RXN SCK

FSYNC

VD+

STA120

3.3V

ANALOG

VA+

AGND 21

0.1µF

VERF

SDATA

CBL

D97AU611

3.3V

DIGITAL

0.1µF

FILT

15nF

0.47µF

330Ω8

DGND

MCK

RXP

CHANNEL STATUS

and/or

ERROR/FREQUENCY

REPORTING

CS12/FCK

SEL

ERF

C/E-F bits

STA120

6/15

frequency detectors pull the VCO frequency within

the lock range of the PLL. When no digital audio

data is present, the VCO frequenc y is pulled to its

mini mum val ue.

Figure 2. Jitter Attenuator Characteristics.

As a m as ter, SCK is alw ay s MCK d ivided by fou r,

producing a frequency of 64 x FS. In the STA120,

FSYNC is always generated from the incoming

data stream. When FSY NC is generat ed f rom the

data its edges are extracted at times when in-

tersymbol interference is at a m inimum. Th is pro-

vides a sample frequency clock that is as

spectrally pure as the digital audio source clock for

moderate length transmission lines.

STA120 DESCRIPTION

The STA120 does not need a microprocessor to

handle the non-au dio data (although a micro may

be used with the C and U serial ports). Instead,

dedicated pins are available for the most important

channel status bits. The STA120 is a monolithic

CMOS circuits that receives and decodes digital

audio data which was encoded according to the

digital audio interface standards. It contains a

clock and data recovery utilizing an on-chip phase-

locked loop. The output data is output through a

configurable serial port that supports 14 formats.

The channel status and user data have their own

serial pins and the validity flag is OR'ed with the

ERF flag to prov ide a single p in, VERF, indicat ing

that the audio output may not be valid. This pin

may be used by interpolation filters that provide er-

ror correction.

Audio Ser i a l P ort

The audio serial port is used primarily to output au-

dio data and consi sts of three pins: SCK, FSY NC

and SDATA. These pins are configured via four

control pins: M0, M1,M2,and M3.M3 selects be-

tween eight normal serial formats (M3 = 0), and six

special formats (M3 = 1).

Normal M odes ( M3 = 0)

When M3 is low, the normal serial port formats

shown in Fi gure 3 are s elected us in g M 2, M1 and

M0. These formats are also listed in Table 1

wherein the first word part the format number (Out-

In) indicates whether FSYNC and SCK are outputs

from the STA120 or are inputs.

The next word (L/R-WSYNC) indicates whether

FSYNC indicates the particular channel or just de-

lineates each word. If an error occurs (ERF=1)

while using one of these formats, the previous val-

id audio data for that channel will be output.

If the STA 120 is not locked , the last sample is re-

peated at the outp ut. In some modes FS YN C and

SCK are outputs and i n others they are inputs. In

Table 3, LSB J i s short for LS B ju stified where t he

LSB is justified to the end o f the audio frame and

the MSB varies with word length. As outputs the

STA120 generates 32 SCK periods per audio

sample (64 per stereo sampl e) and, as in puts, 32

SCK periods mus t be provided per audio sample.

When FSYNC and SCK are inputs, one stereo

sample is double buffered. For those modes which

output 24 bits of audio data, the auxiliary bits will

be included. If the auxiliary bits are not used for

audio data, they must be masked off.

1 10 100 1000 (KHz)

100

(dB)

D97AU612

7/15

STA120

Table 1. Normal Audio Port Modes (M3 = 0)

Special Mod es (M3 = 1)

When M3 is high, the special audio modes desc ribed in Table 2 are select ed via M2, M1 , and M0. In for-

mats 8, 9, and 10, SCK, FSYNC, and SDATA are the same as in formats 0, 1, and 2 respectively; however,

the recovered data is output as is even if ERF is high, indicating an error. (In modes 0-2 the previous valid

sample is output).

When out of lock invalid data are sen t to the outpu t and the ERF pin goes high.

Format 11 is similar to format 0 except that SCK is an input and FSYNC is an output.

In this mode FSYNC and SDATA are synchronized to the incoming SCK, This mode may be useful when

writing data to storage.

Table 2. Special Audio Port Mod es (M3 = 1)

Format 12 is similar to format 7 except that SDATA is the entire data word received from the transmission

line including the C, U, V, and P bits, with zeros in place of the pream ble. In format 13 SDATA cont ains

the entire biphase encoded dat a from the transmission line includi ng the preamble , and SCK is twice the

normal frequency.

The normal two frame delay of data from input to output is reduced to only a few bit periods in formats 12

and 13. However, the C, U, V bits and error codes f ollow t heir norma l pathways a nd t heref ore foll ow the

output data by nearly two frames. Figure 4.... illustrates formats 12 and 13. Format 14 is reserved and not

presently used, and format 15 causes the S TA120 to go into a reset state. While in reset all outputs will

be inactive except MCK. The STA120 incorporates a Power-on Reset to avoid a Reset at power-up.

C, U, V ERF, ERF, and CBL Serial Outputs

The C and U bits and C BL are output one S CK period prior to the active edge of FSYNC in all serial port

formats except 2, 3 and 10 (I

S modes). The active edge of FSYNC may be used to latch C, U, and CBL

externally. In formats 2, 3 and 10, the C and U bits and CBL are updated with the active edge of FSYNC.

The validity + error flag (VERF) and the error flag (ERF) are always updated at the active edge of FSYNC.

M2 M1 M0 Format

0 0 0 0 - Out, L/R, 16-24 Bits

0 0 1 1 - In, L/R, 16-24 Bits

010

2 - Out, L/R, I

S Compatible

011

3 - In, L/R, I

S Compatible

1 0 0 4 - Out, WSYNC, 16-24 Bits

1 0 1 5 - Out, L/R, 16 Bits LSBJ

1 1 0 6 - Out, L/R, 18 Bits LSBJ

1 1 1 7 - Out, L/R, MSB Last

M2 M1 M0 Format

0 0 0 8 - Format 0 - No repeat on error

0 0 1 9 - Format 1 - No repeat on error

0 1 0 10 - Format 2 - No repeat on error

0 1 1 11 - Format 0 - Async. SCK input

1 0 0 12 - Received NRZ Data

1 0 1 13 - Received Bi-phase Data

1 1 0 14 - Reserved

1 1 1 15 - STA120 Reset

STA120

8/15

This timing is illustrated in Figure 5.

The C output contains the channel status bits with CBL rising indicating the start of a new channel status

block. CBL is high for the first four bytes of channel status (32 frames or 64 sampl es) and low for the last

20 bytes of channel status (160 frames or 320 samples).

The U output contains the User Channel data. The V bit is OR'ed with the ERF flag and output on the

VERF pin. This indicates that the audio sample may be in error and can be used by interpolation filters to

interpolate through the error.

ERF being hi gh indicates a serious error occurred on the transmission line. T here are three errors that

cause ERF to go high: a parity error or biphase coding violation during that sample, or an out of lock PLL

rece iv e r. Ti min g for the a bove pin s is illustra t ed in Figu r e 5 .

Mult i func t io n Pins

There are seven multifunction pins which contain either error and received frequency information, or chan-

nel status information, selecta ble by SEL.

Figure 3. Audio Serial Port Formats

FSYNC(out)

MSB LSB MSB LSB MSB

LEFT RIGHT

SCK(out)

SDATA(out)

FSYNC(in)

MSB LSB MSB LSB MSB

LEFT RIGHT

SCK(in)

SDATA(out)

FSYNC(out)

MSB LSB MSB LSB MSB

LEFT RIGHT

SCK(out)

SDATA(out)

FORMAT 0:

FORMAT 1:

FORMAT 2:

FSYNC(out)

MSB LSB MSB LSB MSB

LEFT RIGHT

SCK(out)

SDATA(out)

FSYNC(out)

LSB MSB LSB

SCK(out)

SDATA(out)

FORMAT 4:

FORMAT 5: LEFT RIGHT

LSB MSB

16 Bits 16 Bits

FSYNC(out)

LSB MSB LSB

SCK(out)

SDATA(out)

FORMAT 6: LEFT RIGHT

LSB MSB

18 Bits 18 Bits

FSYNC(out)

MSB LSB MSB

SCK(out)

SDATA(out)

FORMAT 7: LEFT RIGHT

MSB LSB

D97AU610

M2 M1 M0

0 0 0

0 0 1

0 1 0

FSYNC(in)

MSB LSB MSB LSB MSB

LEFT RIGHT

SCK(in)

SDATA(out)

FORMAT 3:

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

9/15

STA120

Figure 4. Special Audio P ort Form ats 12 and 13

Error A n d Fre q uenc y R epo rt i ng

When SEL is low, error and received frequency information are selected.

The error information is encoded on pins E 2, E1, and E0, and is decoded as shown in Ta ble 3. When an

error occurs, the corresponding error code is latched.

Clearing is then accomp lished by bringing SEL hig h for more than eight MCK cycles. The errors have a

priority associated with their error code, with validity having the lowest priority that occurred since the last

clearing will be selected.

Table 3. Error Decoding

Figu re 5. CB L Ti m i ng

E2 E1 E0 Error

0 0 0 No Error

0 0 1 Validity Bit High

0 1 0 Confidence flag

0 1 1 Slipped Sample

1 0 0 CRC Error (PRO only)

1 0 1 Parity Error

1 1 0 Bi-Phase Coding Error

1 1 1 No Lock

AUX LSB

LEFT RIGHT

MSB V U C P AUX LSB MSB V U C P

LSB

LEFT RIGHT

MSB LSB MSB

AUX VUCP AUX VUCP

FSYNC(out)

SCK(out)

SDATA(out)

FSYNC(out)

SCK(out)

SDATA(out)

D98AU987

RIGHT 0 RIGHT 191 LEFT 0RIGHT 31RIGHT 191

CBL

D98AU988

LEFT 0 LEFT 1 LEFT 32SDATA

Ca-Ce

FSYNC

ERF,

VERF

C, U

STA120

10/15

The validity flag indicates that the validity bit for a previous sample was high since the last clearing of the

error codes. The slipped s am ple error can on ly occu r when FSY NC and SCK of the audio serial port are

inputs. In this case, if FSYNC is asynchronous to the received data rate, periodically a stereo sample will

be dropped or reread depending on whether the read rate is slower or faster than the received data rate .

When this occurs, the slipped sample error code will appear on the "E" pins.

The CRC error is updated at the beginning of a channel status block, and is only valid when the profes-

sional format of channel status data is received. This error is indicated when the STA120 calculated CRC

value does not match the CRC byte of the channel status block or when a bl ock boundary changes (as in

removing samples while editing).

The parity error occurs when the incoming sub-frame does not have even parity as specified by the stan-

dards. The biphase coding error indicates a biphase coding violation occurred. The no lock error indicates

that the PLL is not locked onto the incoming data stream. Lock is achieved after receiving three frame pre-

ambles then one block preamble, and is lost after not receiving four consecutive frame preambles .

The receive frequen cy inform ation is enc oded on pins F2, F1 and F0, and is dec ode d as shown in Ta ble

6. The on-chip frequency comparator compares the received clock frequency to an externally supplied

6.144MHz clock which is input on the FCK pin. The "F" pins. The clock on FCK must be valid for two thirds

of a block for the "F" pins to be accurate.

Table 4. Sample Frequency Decoding

Channel Sta tus Re port in g

When SEL is high, channel status is displayed on C 0, and Ca -Ce for the channel selected by CS12. If

CS12 is low, channel status for sub-frame1 is displayed, and if CS12 is high, channel status for subframe

2 is displayed. the contents of Ca-Ce depend upon the C0 professional/consumer bit. The information re-

port is shown in Table 5.

Table 5. Channel Status Pins

F2 F1 F0 Error

0 0 0 Out of Range

0 0 1 48KHz ±4%

0 1 0 44.1 KHz ±4%

0 1 1 32KHz ±4%

1 0 0 48KHz ±400ppm

1 0 1 44.1 KHz ±400 ppm

1 1 0 44.056KHz ±400ppm

1 1 1 32KHz ±400ppm

Pin Professional Consumer

C0 0 (low) 1 (high)

Ca C1 C1

Cb EM0 C2

Cc EM1 C3

Cd C9 ORIG

Ce CRCE IGCAT

11/15

STA120

Professional Channel Status (C0 = 0)

When C0 is low, the received channel status block is encoded ac cording to the profes sional / broadc ast

format. The Ca through Ce pins are defined for some of the more important professional bits. As listed in

Table 5, Ca is the inverse of channel status bit1. Therefore, if the incoming channel status bit1. Therefore,

if the incoming channel status bit 1 is 1, Ca, defined as C1, will be 0. C1 indicates whether audio (C1 = 1)

or non-audio (C1 = 0) data is being received. Cb and Cc, defined as EM0 and EM1 respectively, indicate

emphasis and a re encoded vers ion of channel st atus bits 2, 3, and 4. The de cod ing is listed in Table 6.

Cd, defined as C9, is the inverse of channel status bit 9, which gives some indication of channel status bit

9, which gives some indication of channel mode. (Bit 9 is also defined as bit 1 of byte 1). When Ce, defined

as CRCE, is low, the STA120 calculated CRC value does not match the received CRC value. This signal

may be used to qualify Ca through Cd. If Ca through Ce are being displayed, Ce going low can indicate

not to update the display.

Table 6. Emphasis Encoding

Consumer Channel Status (C0 = 1)

When C0 is high, the received channel status block is encoded according to the consumer format. In this

case Ca through Ce are defined differently as shown in Table 5.

Ca is the inverse of channel status bit 1, C1, indicating audio (C1 = 1) or non-audio (C1 = 0). Cb is defined

as the inverse of cha nnel status bit 2, C2, which indicates c opy inhibit/copyright information Cc, d efined

as C3, is t he emphasis bit of channel status, with C3 low i ndicating the data has had pre-emphasis added.

The audio standards, in consumer mode, describe bit 15, L, as the generation status which indicates

whether the audio data is an original work or a copy (1st generation or higher). The definition of the Lbit is

reversed for three c ategory codes: two broadcas t c odes, and laser-opt ical (CD's). Th erefore, to i nterpret

the L bit properly, the category code must be decoded. The STA120 does this decoding i nternally and pro-

vides the ORIG signal that, when low, indicates that the audio data is original over all category codes .

SCMS

The consumer a udio standards a lso ment ion a serial copy m anage men t system, SCMS, for dealing with

copy protection of copyrighted works. SCMS is designed to allow unlimited duplication of the original work,

but no duplication of any copies of the original. This system utilizes the channel status bit 2, Copy, and

channel status bit 15, L or generation status, along with the category codes. If the Copy bit is 0, copyright

protection is asserted over the material is an original or a duplication. (As mentioned in the previous para-

graph, the def inition of the L bit can be reve rsed based on the cat egory codes.) There are two category

codes that get special attention: general and A/D converters w ithout C or L bit information. For these two

categories the SCMS stand ard requires t hat equipment interfacing to these cat egories set the C bit to 0

(copyright protection asserted) and the L bit t o 1 (original). To support this feature, Ce, in the consum er

mode, is defined as IGCAT (ignorant category) which is low for the "general" (0000000) and "A/D convert-

er without copyright information" (01100xx) categories.

EM1 EM0 C2 C3 C4 Emphasis

0 0 1 1 1 CCITT J.17 em pha sis

0 1 1 1 0 50/15ms emphasis

1 0 1 0 0 No emphasis

1 1 0 0 0 Not indicated

STA120

12/15

APPENDIX A: RS422 RECEIVER INFORMATION

The RS422 receivers on the STA120 is designed to receive both the professional and consumer interfac-

es, and meet all specific ations list ed in the digital aud io standar ds. Figure 6 illust rates the inter nal sche-

matic of the receiver portion of both chips. The receiver has a differential input. A Schmitt trigger is

incorporated to add hysteresis which prevents noisy signals from corrupting the phase detector.

Figure 6. RS422 Receiver Internal Circuit

Professional Interface

The digital aud io speci fications for professional use c all for a balanced recei ver, u sing XLR connectors,

with 110Ω ±20% impedance. (The XLR connector on the receiver should have female pins with a male

shell.) Since the receiver has a very high impedance, a 110Ω resistor should be placed across the receiv-

er terminals to match the line i mpedance, as shown in figure 7, and, since the part has internal biasing,

no external biasing network is needed. If some isolation is desired without the use of transformers, a

0.01µF capacitor s houl d b e pl ac ed o n t he input of esch pi n (RX P a nd RX N) as s hown in F igure 8. How-

ever, if transformers are not used, high frequenc y energy could be c oupled between transmitter and re-

ceiver causing degradation in analog performance.

Although transformers are not required by AES the y are str ongly re commended. The EBU requires trans-

formers. Figure 7 and 8 show an optional DC blocking capacitor on the transmission line. A 0.1 to 0.47µF

ceramic capacitor may be used to block any DC voltage that is accidentally connected to the digital audio

receiver. The use of this capacitor is an issue of robustness s the digital audio transmission line does not

have a DC voltage component.

Figu re 7. P rofe ssional Inp ut C ir cui t

Figure 8. Transfo rmerless Pr ofessional Circuit

K-ix

D98AU983

RXP

RXN

110Ω

RXP

RXN

(*)See Text

110Ω

TWISTED

PAIR

D98AU984A

XLR

110Ω

RXP

RXN

(*)See Text

110Ω

TWISTED

PAIR

D98AU985A

XLR

0.01µF

13/15

STA120

Grounding the shield of the cables a tricky issue. In the configuration of systems , it is import ant to avoid

ground loops and DC current flowing down the shield of the cable that could results when boxes with dif-

ferent ground potentials are connecte d.

Genera lly, it is good p ra ctice to groun d th e s hield to the ch assis of the trans m itting unit, and c onn ect the

shield through a capacitor to chass is ground at th e receiver. How ever, in some cases it is advantageous

to have the ground of two boxes help to the same potential, and the cable shield might be depended upon

to make that electrical connection.

Generally, it may be a good idea to provide the option of grounding or capacitively coupling to ground with

a "ground-lift" circuit.

Consumer Interface

In the case of the consum er interface, the standa rds call for an unb alanced circuit having a receive r im-

pedance o f 75Ω ±5% . Th e connect or for the con su mer interface is a n RCA phono plug (f ixed sock et de-

scribed in Table IV of IEC268-11). The receiver circuit for the consumer interface is shown in Figure 9.

Figu re 9. Cons um er Inp ut Circui t

TTL/CMOS Level s

The circuit shown in Figure 10 may be used when external RS422 receivers or TTL/CMOS logic drive the

STA120 receiver section.

Figure 10. TTL/CMOS Interface

75Ω

RXP

RXN

75Ω

coax

D02AU1387

RCA Phono 100nF

100nF STA120

RXP

RXN

100nF

D98AU986C

STA120

14/15

SO28

DIM. mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

A 2.65 0.104

a1 0.1 0.3 0.004 0.012

b 0.35 0.49 0.014 0.019

b1 0.23 0.32 0.009 0.013

C 0.5 0.020

c1 45° (typ.)

D 17.7 18.1 0.697 0.713

E 10 10.65 0.394 0.419

e 1.27 0.050

e3 16.51 0.65

F 7.4 7.6 0.291 0.299

L 0.4 1.27 0.016 0.050

S8° (max.)

OUTLINE AND

MECHANICAL DATA

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15/15

STA120