December 2007 Rev 4 1/108
1
M58LT256JST
M58LT256JSB
256 Mbit (16 Mb × 16, multiple bank, multilevel, burst)
1.8 V supply, secure Flash memories
Features
■Supply voltage
–V
DD = 1.7 V to 2.0 V for program, erase
and read
–V
DDQ = 2.7 V to 3.6 V for I/O buffers
–V
PP = 9 V for fast program
■Synchronous/asynchronous read
– Synchronous burst read mode: 52 MHz
– Random access: 85 ns
– Asynchronous page read mode
■Synchronous burst read suspend
■Programming time
– 5 µs typical word program time using Buffer
Enhanced Factory Program command
■Memory organization
– Multiple bank memory array: 16 Mbit banks
– Parameter blocks (top or bottom location)
■Dual operations
– Program/erase in one bank while read in
others
– No delay between read and write
operations
■Block protection
– All blocks protected at power-up
– Any combination of blocks can be protected
with zero latency
– Absolute write protection with VPP = VSS
■Security
– Software security features
– 64 bit unique device number
– 2112 bit user programmable OTP Cells
■CFI (common Flash interface)
■100 000 program/erase cycles per block
■Electronic signature
– Manufacturer code: 20h
– Top device codes:
M58LT256JST: 885Eh
– Bottom device codes
M58LT256JSB: 885Fh
■TBGA64 package
– ECOPACK® compliant
TBGA64 (ZA)
10 x 13 mm
BGA
www.numonyx.com
Contents M58LT256JST, M58LT256JSB
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Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1 Address inputs (A0-A23) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2 Data input/output (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4 Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.6 Reset (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.7 Latch Enable (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.8 Clock (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.9 Wait (WAIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.10 VDD supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.11 VDDQ supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.12 VPP program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.13 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.14 VSSQ ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1 Bus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2 Bus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3 Address latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4 Output disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.6 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4 Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1 Read Array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2 Read Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.3 Read Electronic Signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.4 Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.5 Clear Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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4.6 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.7 The Blank Check command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.8 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.9 Buffer Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.10 Buffer Enhanced Factory Program command . . . . . . . . . . . . . . . . . . . . . 25
4.10.1 Setup phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.10.2 Program and verify phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.10.3 Exit phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.11 Program/Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.12 Program/Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.13 Protection Register Program command . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.14 Set Configuration Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.15 Block Protect command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.16 Block Unprotect command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.1 Program/Erase Controller status bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . 34
5.2 Erase suspend status bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.3 Erase/blank check status bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.4 Program status bit (SR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.5 VPP status bit (SR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.6 Program suspend status bit (SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.7 Block protection status bit (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.8 Bank write/multiple word program status bit (SR0) . . . . . . . . . . . . . . . . . 36
6 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.1 Read select bit (CR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.2 X latency bits (CR13-CR11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.3 Wait polarity bit (CR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.4 Data output configuration bit (CR9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.5 Wait configuration bit (CR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.6 Burst type bit (CR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.7 Valid clock edge bit (CR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.8 Wrap burst bit (CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
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6.9 Burst length bits (CR2-CR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7 Read modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.1 Asynchronous read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.2 Synchronous burst read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.2.1 Synchronous burst read suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.3 Single synchronous read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8 Dual operations and multiple bank architecture . . . . . . . . . . . . . . . . . 47
9 Block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.1 Reading a block’s protection status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.2 Protected state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.3 Unprotected state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.4 Protection operations during erase suspend . . . . . . . . . . . . . . . . . . . . . . 51
10 Program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 52
11 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
12 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
13 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
14 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Appendix A Block address tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Appendix B Common Flash interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Appendix C Flowcharts and pseudocodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Appendix D Command interface state tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
M58LT256JST, M58LT256JSB List of tables
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List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 2. Bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 3. Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 4. Command codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 5. Standard commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 6. Factory commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 7. Electronic signature codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 8. Protection Register locks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 9. Status Register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 10. X latency settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 11. Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 12. Burst type definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 13. Dual operations allowed in other banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 14. Dual operations allowed in same bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 15. Dual operation limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 16. Program/erase times and endurance cycles, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 17. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 18. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 19. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 20. DC characteristics - currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 21. DC characteristics - voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 22. Asynchronous read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 23. Synchronous read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 24. Write AC characteristics, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 25. Write AC characteristics, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 26. Reset and power-up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 27. TBGA64 10 × 13 mm - 8 x 8 active ball array, 1 mm pitch, package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 28. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 29. M58LT256JST - parameter bank block addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 30. M58LT256JST - main bank base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 31. M58LT256JST - block addresses in main banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 32. M58LT256JSB - parameter bank block addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 33. M58LT256JSB - main bank base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 34. M58LT256JSB - block addresses in main banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 35. Query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 36. CFI query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 37. CFI query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 38. Device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 39. Primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 40. Protection register information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 41. Burst read information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 42. Bank and erase block region information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 43. Bank and erase block region 1 information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 44. Bank and erase block region 2 information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 45. Command interface states - modify table, next state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 46. Command Interface states - modify table, next output state . . . . . . . . . . . . . . . . . . . . . . 101
Table 47. Command interface states - lock table, next state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
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List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 2. TBGA64 package connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 3. Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 4. Protection Register memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 5. X latency and data output configuration example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 6. Wait configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 7. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 8. AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 9. Asynchronous random access read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 10. Asynchronous page read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 11. Synchronous burst read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 12. Single synchronous read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 13. Synchronous burst read suspend AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 14. Clock input AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 15. Write AC waveforms, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 16. Write AC waveforms, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 17. Reset and power-up AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 18. TBGA64 10 × 13 mm - 8 x 8 active ball array, 1 mm pitch, bottom view
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 19. Program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 20. Blank check flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 21. Buffer program flowchart and pseudocode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 22. Program suspend and resume flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 23. Block erase flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 24. Erase suspend and resume flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 25. Protect/unprotect operation flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 26. Protection Register program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 27. Buffer enhanced factory program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . 97
Description M58LT256JST, M58LT256JSB
8/108
1 Description
The M58LT256JST/B are 256 Mbit (16 Mbit x 16) non-volatile secure Flash memories. They
may be erased electrically at block level and programmed in-system on a word-by-word
basis using a 1.7 V to 2.0 V VDD supply for the circuitry and a 2.7 V to 3.6 V VDDQ supply for
the input/output pins. An optional 9 V VPP power supply is provided to speed up factory
programming.
The devices feature an asymmetrical block architecture. The M58LT256JST/B have an array
of 259 blocks, and are divided into 16 Mbit banks. There are 15 banks each containing 16
main blocks of 64 Kwords, and one parameter bank containing 4 parameter blocks of 16
KWords and 15 main blocks of 64 KWords.
The multiple bank architecture allows dual operations. While programming or erasing in one
bank, read operations are possible in other banks. Only one bank at a time is allowed to be
in program or erase mode. It is possible to perform burst reads that cross bank boundaries.
The bank architecture is summarized in Ta b le 2 , and the memory map is shown in Figure 3.
The parameter blocks are located at the top of the memory address space for the
M58LT256JST, and at the bottom for the M58LT256JSB.
Each block can be erased separately. Erase can be suspended to perform a program or
read operation in any other block, and then resumed. Program can be suspended to read
data at any memory location except for the one being programmed, and then resumed.
Each block can be programmed and erased over 100 000 cycles using the supply voltage
VDD. There is a buffer enhanced factory programming command available to speed up
programming.
Program and erase commands are written to the command interface of the memory. An
internal Program/Erase Controller manages the timings necessary for program and erase
operations. The end of a program or erase operation can be detected and any error
conditions identified in the Status Register. The command set required to control the
memory is consistent with JEDEC standards.
The device supports synchronous burst read and asynchronous read from all blocks of the
memory array. At power-up the device is configured for asynchronous read. In synchronous
burst read mode, data is output on each clock cycle at frequencies of up to 52 MHz. The
synchronous burst read operation can be suspended and resumed.
The device features an automatic standby mode. When the bus is inactive during
asynchronous read operations, the device automatically switches to the automatic standby
mode. In this condition the power consumption is reduced to the standby value and the
outputs are still driven.
The M58LT256JST/B features an instant, individual block protection scheme that allows any
block to be protected or unprotected with no latency, enabling instant code and data
protection. They can be protected individually preventing any accidental programming or
erasure. There is an additional hardware protection against program and erase. When
VPP ≤VPPLK all blocks are protected against program or erase. All blocks are protected at
power-up.
M58LT256JST, M58LT256JSB Description
9/108
The device includes 17 Protection Registers and 2 Protection Register locks, one for the first
Protection Register and the other for the 16 OTP (one-time-programmable) Protection
Registers of 128 bits each. The first Protection Register is divided into two segments: a 64
bit segment containing a unique device number written by Numonyx, and a 64 bit segment
OTP by the user. The user programmable segment can be permanently protected. Figure 4,
shows the Protection Register Memory map.
The M58LT256JST/B also has a full set of software security features that are not described
in this datasheet, but are documented in a dedicated application note. For further
information please contact Numonyx.
The M58LT256JST/B are offered in a TBGA64, 10 × 13 mm, 1 mm pitch package, and are
supplied with all the bits erased (set to ’1’).
Figure 1. Logic diagram
AI13299
A0-A23
W
DQ0-DQ15
VDD
M58LT256JST
M58LT256JSB
E
VSS
16
G
RP
VDDQ VPP
L
K
WAIT
VSSQ
Description M58LT256JST, M58LT256JSB
10/108
Table 1. Signal names
Signal name Function Direction
A0-A23 Address inputs Inputs
DQ0-DQ15 Data input/outputs, command inputs I/O
EChip Enable Input
GOutput Enable Input
WWrite Enable Input
RP Reset Input
K Clock Input
LLatch Enable Input
WAIT Wait Output
VDD Supply voltage
VDDQ Supply voltage for input/output buffers
VPP Optional supply voltage for Fast Program & Erase
VSS Ground
VSSQ Ground input/output supply
NC Not connected internally
DU Do not use
M58LT256JST, M58LT256JSB Description
11/108
Figure 2. TBGA64 package connections (top view through package)
AI13414
DQ6
A0
VSSQ
VDD
DQ10
VDD
DQ7
DQ5VDDQ
DQ2
H
DQ14
VSS
DQ13
D A15
A19
EA8
C
A16
A20
A10
A14
K
A7
B A18A1
A12
A13
A
87654321
A6A2
A3 A4
G
F
E
DQ0
A5 VPP A17
A9 A11
RP
DQ15DQ9DQ8 DQ1 DQ4DQ3
GDQ12DQ11
W
VSS NC
NC
NC NC
NC
NC
NC NC
A23
A21
A22
WAIT
NC
NC
L
Description M58LT256JST, M58LT256JSB
12/108
Figure 3. Memory map
Table 2. Bank architecture
Number Bank size Parameter blocks Main blocks
Parameter bank 16 Mbits 4 blocks of 16 KWords 15 blocks of 64 KWords
Bank 1 16 Mbits - 16 blocks of 64 KWords
Bank 2 16 Mbits - 16 blocks of 64 KWords
Bank 3 16 Mbits - 16 blocks of 64 KWords
----
----
----
----
Bank 14 16 Mbits - 16 blocks of 64 KWords
Bank 15 16 Mbits - 16 blocks of 64 KWords
AI13403b
M58LT256JST - Top Boot Block
Address lines A0-A23
16 Main
Blocks
Bank 15
M58LT256JSB - Bottom Boot Block
Address lines A0-A23
64 Kword
000000h
00FFFFh
64 Kword
0F0000h
0FFFFFh
64 Kword
C00000h
C0FFFFh
64 Kword
CF0000h
CFFFFFh
64 Kword
D00000h
D0FFFFh
64 Kword
DF0000h
DFFFFFh
64 Kword
E00000h
E0FFFFh
64 Kword
EF0000h
EFFFFFh
64 Kword
F00000h
F0FFFFh
64 Kword
FE0000h
FEFFFFh
16 Kword
FF0000h
FF3FFFh
16 Kword
FFC000h
FFFFFFh
4 Parameter
Blocks
Parameter
Bank
Parameter
Bank
16 Kword
000000h
003FFFh
16 Kword
00C000h
00FFFFh
64 Kword
010000h
01FFFFh
64 Kword
0F0000h
0FFFFFh
64 Kword
100000h
10FFFFh
64 Kword
1F0000h
1FFFFFh
64 Kword
200000h
20FFFFh
64 Kword
2F0000h
2FFFFFh
64 Kword
300000h
30FFFFh
64 Kword
3F0000h
3FFFFFh
64 Kword
F00000h
F0FFFFh
64 Kword
FF0000h
FFFFFFh
Bank 3
Bank 2
Bank 1
Bank 15
Bank 3
Bank 2
Bank 1
16 Main
Blocks
16 Main
Blocks
16 Main
Blocks
15 Main
Blocks
4 Parameter
Blocks
15 Main
Blocks
16 Main
Blocks
16 Main
Blocks
16 Main
Blocks
16 Main
Blocks
M58LT256JST, M58LT256JSB Signal descriptions
13/108
2 Signal descriptions
See Figure 1: Logic diagram and Table 1: Signal names for a brief overview of the signals
connected to this device.
2.1 Address inputs (A0-A23)
The address inputs select the cells in the memory array to access during bus read
operations. During bus write operations they control the commands sent to the command
interface of the Program/Erase Controller.
2.2 Data input/output (DQ0-DQ15)
The data I/O output the data stored at the selected address during a bus read operation or
input a command or the data to be programmed during a bus write operation.
2.3 Chip Enable (E)
The Chip Enable input activates the memory control logic, input buffers, decoders and
sense amplifiers. When Chip Enable is at VILand Reset is at VIH the device is in active
mode. When Chip Enable is at VIH the memory is deselected, the outputs are high
impedance and the power consumption is reduced to the standby level.
2.4 Output Enable (G)
The Output Enable input controls data outputs during the bus read operation of the memory.
2.5 Write Enable (W)
The Write Enable input controls the bus write operation of the memory’s command interface.
The data and address inputs are latched on the rising edge of Chip Enable or Write Enable,
whichever occurs first.
2.6 Reset (RP)
The Reset input provides a hardware reset of the memory. When Reset is at VIL, the
memory is in reset mode: the outputs are high impedance and the current consumption is
reduced to the Reset supply current IDD2. Refer to Table 20: DC characteristics - currents for
the value of IDD2. After Reset all blocks are in the protected state and the Configuration
Register is reset. When Reset is at VIH, the device is in normal operation. Upon exiting reset
mode the device enters asynchronous read mode, however, a negative transition of Chip
Enable or Latch Enable is required to ensure valid data outputs.
Signal descriptions M58LT256JST, M58LT256JSB
14/108
2.7 Latch Enable (L)
Latch Enable latches the address bits on its rising edge. The address latch is transparent
when Latch Enable is at VIL and it is inhibited when Latch Enable is at VIH.
2.8 Clock (K)
The clock input synchronizes the memory to the microcontroller during synchronous read
operations; the address is latched on a Clock edge (rising or falling, according to the
configuration settings) when Latch Enable is at VIL. Clock is ignored during asynchronous
read and in write operations.
2.9 Wait (WAIT)
Wait is an output signal used during synchronous read to indicate whether the data on the
output bus are valid. This output is high impedance when Chip Enable is at VIH, Output
Enable is at VIH or Reset is at VIL. It can be configured to be active during the wait cycle or
one clock cycle in advance.
2.10 VDD supply voltage
VDD provides the power supply to the internal core of the memory device. It is the main
power supply for all operations (read, program and erase).
2.11 VDDQ supply voltage
VDDQ provides the power supply to the I/O pins and enables all outputs to be powered
independently from VDD.
2.12 VPP program supply voltage
VPP is both a control input and a power supply pin. The two functions are selected by the
voltage range applied to the pin.
If VPP is kept in a low voltage range (0 V to VDDQ) VPP is seen as a control input. In this case
a voltage lower than VPPLK gives absolute protection against program or erase, while VPP in
the VPP1 range enables these functions (see Tables 20 and 21, DC Characteristics for the
relevant values). VPP is only sampled at the beginning of a program or erase; a change in its
value after the operation has started does not have any effect and program or erase
operations continue.
If VPP is in the range of VPPH it acts as a power supply pin. In this condition VPP must be
stable until the program/erase algorithm is completed.
M58LT256JST, M58LT256JSB Signal descriptions
15/108
2.13 VSS ground
VSS ground is the reference for the core supply. It must be connected to the system ground.
2.14 VSSQ ground
VSSQ ground is the reference for the input/output circuitry driven by VDDQ. VSSQ must be
connected to VSS
Note: Each device in a system should have VDD, VDDQ and VPP decoupled with a 0.1 µF ceramic
capacitor close to the pin (high-frequency, inherently-low inductance capacitors should be
as close as possible to the package). See Figure 8: AC measurement load circuit. The PCB
track widths should be sufficient to carry the required VPP program and erase currents.
Bus operations M58LT256JST, M58LT256JSB
16/108
3 Bus operations
There are six standard bus operations that control the device. These are bus read, bus
write, address latch, output disable, standby and reset. See Table 3: Bus operations for a
summary.
Typically glitches of less than 5 ns on Chip Enable or Write Enable are ignored by the
memory and do not affect bus write operations.
3.1 Bus read
Bus read operations output the contents of the memory array, the electronic signature, the
Status Register and the common Flash interface. Both Chip Enable and Output Enable must
be at VIL to perform a read operation. The Chip Enable input should be used to enable the
device. Output Enable should be used to gate data onto the output. The data read depends
on the previous command written to the memory (see Section 4: Command interface). See
Figures 9, 10 and 11 Read AC waveforms, and Tables 22 and 23 Read AC characteristics
for details of when the output becomes valid.
3.2 Bus write
Bus write operations write commands to the memory or latch input data to be programmed.
A bus write operation is initiated when Chip Enable and Write Enable are at VIL with Output
Enable at VIH. Commands, input data and addresses are latched on the rising edge of Write
Enable or Chip Enable, whichever occurs first. The addresses must be latched prior to the
write operation by toggling Latch Enable (when Chip Enable is at VIL). The Latch Enable
must be tied to VIH during the bus write operation.
See Figures 15 and 16, Write AC waveforms, and Tables 24 and 25, Write AC
characteristics for details of the timing requirements.
3.3 Address latch
Address latch operations input valid addresses. Both Chip enable and Latch Enable must be
at VIL during address latch operations. The addresses are latched on the rising edge of
Latch Enable.
3.4 Output disable
The outputs are high impedance when the Output Enable is at VIH.
M58LT256JST, M58LT256JSB Bus operations
17/108
3.5 Standby
Standby disables most of the internal circuitry allowing a substantial reduction of the current
consumption. The memory is in standby when Chip Enable and Reset are at VIH. The power
consumption is reduced to the standby level IDD3 and the outputs are set to high impedance,
independently from the Output Enable or Write Enable inputs. If Chip Enable switches to VIH
during a program or erase operation, the device enters standby mode when finished.
3.6 Reset
During reset mode the memory is deselected and the outputs are high impedance. The
memory is in reset mode when Reset is at VIL. The power consumption is reduced to the
reset level, independently from the Chip Enable, Output Enable or Write Enable inputs. If
Reset is pulled to VSS during a program or erase, this operation is aborted and the memory
content is no longer valid.
Table 3. Bus operations(1)
1. X = ‘don't care’.
Operation E G W L RP WAIT(2)
2. WAIT signal polarity is configured using the Set Configuration Register command.
DQ15-DQ0
Bus read VIL VIL VIH VIL(3)
3. L can be tied to VIH if the valid address has been previously latched.
VIH Data output
Bus write VIL VIH VIL VIL(3) VIH Data input
Address latch VIL XV
IH VIL VIH Data output or Hi-Z(4)
4. Depends on G.
Output disable VIL VIH VIH XV
IH Hi-Z Hi-Z
Standby VIH XXXV
IH Hi-Z Hi-Z
Reset XXXXV
IL Hi-Z Hi-Z
Command interface M58LT256JST, M58LT256JSB
18/108
4 Command interface
All bus write operations to the memory are interpreted by the command interface.
Commands consist of one or more sequential bus write operations. An internal
Program/Erase Controller manages all timings and verifies the correct execution of the
program and erase commands. The Program/Erase Controller provides a Status Register
whose output may be read at any time to monitor the progress or the result of the operation.
The command interface is reset to read mode when power is first applied, when exiting from
reset or whenever VDD is lower than VLKO. Command sequences must be followed exactly.
Any invalid combination of commands are ignored.
Refer to Table 4: Command codes, Table 5: Standard commands, Ta bl e 6: Fa c to r y
commands and Appendix D: Command interface state tables for a summary of the
Command Interface.
Table 4. Command codes
Hex code Command
01h Block Protect Confirm
03h Set Configuration Register Confirm
10h Alternative Program Setup
20h Block Erase Setup
40h Program Setup
50h Clear Status Register
60h Block Protect Setup, Block Unprotect Setup and Set Configuration Register
Setup
70h Read Status Register
80h Buffer Enhanced Factory Program Setup
90h Read Electronic Signature
98h Read CFI Query
B0h Program/Erase Suspend
BCh Blank Check Setup
C0h Protection Register Program
CBh Blank Check Confirm
D0h Program/Erase Resume, Block Erase Confirm, Block Unprotect Confirm, Buffer
Program or Buffer Enhanced Factory Program Confirm
E8h Buffer Program
FFh Read Array
M58LT256JST, M58LT256JSB Command interface
19/108
4.1 Read Array command
The Read Array command returns the addressed bank to read array mode.
One bus write cycle is required to issue the Read Array command. Once a bank is in read
array mode, subsequent read operations output the data from the memory array.
A Read Array command can be issued to any banks while programming or erasing in
another bank.
If the Read Array command is issued to a bank currently executing a program or erase
operation, the bank returns to read array mode. The program or erase operation continues,
however, the data output from the bank is not guaranteed until the program or erase
operation has finished. The read modes of other banks are not affected.
4.2 Read Status Register command
The device contains a Status Register that is used to monitor program or erase operations.
The Read Status Register command is used to read the contents of the Status Register for
the addressed bank.
One bus write cycle is required to issue the Read Status Register command. Once a bank is
in Read Status Register mode, subsequent read operations output the contents of the
Status Register.
The Status Register data is latched on the falling edge of the Chip Enable or Output Enable
signals. Either Chip Enable or Output Enable must be toggled to update the Status Register
data.
The Read Status Register command can be issued at any time, even during program or
erase operations. The Read Status Register command only changes the read mode of the
addressed bank. The read modes of other banks are not affected. Only asynchronous read
and single synchronous read operations should be used to read the Status Register. A Read
Array command is required to return the bank to read array mode.
See Ta b le 9 for the description of the Status Register bits.
Command interface M58LT256JST, M58LT256JSB
20/108
4.3 Read Electronic Signature command
The Read Electronic Signature command reads the manufacturer and device codes, the
Protection Status of the addressed bank, the Protection Register, and the Configuration
Register.
One bus write cycle is required to issue the Read Electronic Signature command. Once a
bank is in read electronic signature mode, subsequent read operations in the same bank
outputs the manufacturer code, the device code, the protection status of the addressed
bank, the Protection Register, or the Configuration Register (see Ta bl e 8 ).
The Read Electronic Signature command can be issued at any time, even during program or
erase operations, except during Protection Register program operations. Dual operations
between the parameter bank and the electronic signature location are not allowed (see
Table 15: Dual operation limitations for details).
If a Read Electronic Signature command is issued to a bank that is executing a program or
erase operation, the bank goes into read electronic signature mode. Subsequent bus read
cycles output the electronic signature data and the Program/Erase Controller continues to
program or erase in the background.
The Read Electronic Signature command only changes the read mode of the addressed
bank. The read modes of other banks are not affected. Only asynchronous read and single
synchronous read operations should be used to read the electronic signature. A Read Array
command is required to return the bank to read array mode.
4.4 Read CFI Query command
The Read CFI Query command reads data from the CFI.
One bus write cycle is required to issue the Read CFI Query command. Once a bank is in
read CFI query mode, subsequent bus read operations in the same bank read from the
common Flash interface.
The Read CFI Query command can be issued at any time, even during program or erase
operations.
If a Read CFI Query command is issued to a bank that is executing a program or erase
operation, the bank goes into read CFI query mode. Subsequent bus read cycles output the
CFI data and the Program/Erase Controller continues to program or erase in the
background.
The Read CFI Query command only changes the read mode of the addressed bank. The
read modes of other banks are not affected. Only asynchronous read and single
synchronous read operations should be used to read from the CFI. A Read Array command
is required to return the bank to read array mode. Dual operations between the parameter
bank and the CFI memory space are not allowed (see Table 15: Dual operation limitations
for details).
See Appendix B: Common Flash interface, Tables 35, 36, 37, 38, 39, 40, 41, 42, 43 and 44
for details on the information contained in the common Flash interface memory area.
M58LT256JST, M58LT256JSB Command interface
21/108
4.5 Clear Status Register command
The Clear Status Register command resets (set to ‘0’) all error bits (SR1, 3, 4 and 5) in the
Status Register.
One bus write cycle is required to issue the Clear Status Register command. The Clear
Status Register command does not affect the read mode of the bank.
The error bits in the Status Register do not automatically return to ‘0’ when a new command
is issued. The error bits in the Status Register should be cleared before attempting a new
program or erase command.
4.6 Block Erase command
The Block Erase command erases a block. It sets all the bits within the selected block to ’1’
and all previous data in the block is lost.
If the block is protected, then the erase operation aborts, the data in the block is not
changed, and the Status Register outputs the error.
Two bus write cycles are required to issue the command.
●The first bus cycle sets up the Block Erase command.
●The second latches the block address and starts the Program/Erase Controller.
If the second bus cycle is not the Block Erase Confirm code, Status Register bits SR4 and
SR5 are set, and the command is aborted.
Once the command is issued, the bank enters read Status Register mode and any read
operation within the addressed bank outputs the contents of the Status Register. A Read
Array command is required to return the bank to read array mode.
During block erase operations the bank containing the block being erased only accepts the
Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the
Program/Erase Suspend commands, and all other commands are ignored.
The block erase operation aborts if Reset, RP
, goes to VIL. As data integrity cannot be
guaranteed when the Block Erase operation is aborted, the block must be erased again.
Refer to Section 8 for detailed information about simultaneous operations allowed in banks
not being erased.
Typical erase times are given in Table 16: Program/erase times and endurance cycles,.
See Appendix C, Figure 23: Block erase flowchart and pseudocode for a suggested
flowchart for using the Block Erase command.
Command interface M58LT256JST, M58LT256JSB
22/108
4.7 The Blank Check command
The Blank Check command checks whether a main array block has been completely
erased. Only one block at a time can be checked. To use the Blank Check command VPP
must be equal to VPPH. If VPP is not equal to VPPH, the device ignores the command and no
error is shown in the Status Register.
Two bus cycles are required to issue the Blank Check command:
●The first bus cycle writes the Blank Check command (BCh) to any address in the block
to be checked.
●The second bus cycle writes the Blank Check Confirm command (CBh) to any address
in the block to be checked and starts the blank check operation.
If the second bus cycle is not Blank Check Confirm, Status Register bits SR4 and SR5 are
set to '1' and the command aborts.
Once the command is issued, the addressed bank automatically enters the Status Register
mode and further reads within the bank output the Status Register contents.
The only operation permitted during blank check is read Status Register. Dual operations
are not supported while a blank check operation is in progress. Blank check operations
cannot be suspended and are not allowed while the device is in program/erase suspend.
The SR7 Status Register bit indicates the status of the blank check operation in progress.
SR7 = '0' means that the blank check operation is still ongoing, and SR7 = '1' means that the
operation is complete.
The SR5 Status Register bit goes High (SR5 = '1') to indicate that the blank check operation
has failed.
At the end of the operation the bank remains in the read Status Register mode until another
command is written to the command interface.
See Appendix C, Figure 20: Blank check flowchart and pseudocode for a suggested
flowchart for using the Blank Check command.
Typical blank check times are given in Table 16: Program/erase times and endurance
cycles,.
M58LT256JST, M58LT256JSB Command interface
23/108
4.8 Program command
The program command is used to program a single word to the memory array.
If the block being programmed is protected, then the program operation aborts, the data in
the block is not changed, and the Status Register outputs the error.
Two bus write cycles are required to issue the Program command.
●The first bus cycle sets up the Program command.
●The second latches the address and data to be programmed and starts the
Program/Erase Controller.
Once the programming has started, read operations in the bank being programmed output
the Status Register content.
During a program operation, the bank containing the word being programmed only accepts
the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the
Program/Erase Suspend commands, and all other commands are ignored. A Read Array
command is required to return the bank to read array mode.
Refer to Section 8 for detailed information about simultaneous operations allowed in banks
not being programmed.
Typical program times are given in Table 16: Program/erase times and endurance cycles,.
The program operation aborts if Reset, RP
, goes to VIL. As data integrity cannot be
guaranteed when the program operation is aborted, the word must be reprogrammed.
See Appendix C, Figure 19: Program flowchart and pseudocode for the flowchart for using
the Program command.
Command interface M58LT256JST, M58LT256JSB
24/108
4.9 Buffer Program command
The Buffer Program command uses the device’s 32-word write buffer to speed up
programming. Up to 32 words can be loaded into the write buffer. The Buffer Program
command dramatically reduces in-system programming time compared to the standard non-
buffered program command.
Four successive steps are required to issue the Buffer Program command.
1. The first bus write cycle sets up the Buffer Program command. The setup code can be
addressed to any location within the targeted block.
After the first bus write cycle, read operations in the bank output the contents of the Status
Register. Status Register bit SR7 should be read to check that the buffer is available
(SR7 = 1). If the buffer is not available (SR7 = 0), re-issue the Buffer Program command to
update the Status Register contents.
2. The second bus write cycle sets up the number of words to be programmed. Value n is
written to the same block address, where n+1 is the number of words to be
programmed.
3. Use n+1 bus write cycles to load the address and data for each word into the write
buffer. Addresses must lie within the range from the start address to the start address
+ n, where the start address is the location of the first data to be programmed.
Optimum performance is obtained when the start address corresponds to a 32-word
boundary.
4. The final bus write cycle confirms the Buffer Program command and starts the program
operation.
All the addresses used in the buffer program operation must lie within the same block.
Invalid address combinations or failing to follow the correct sequence of bus write cycles
sets an error in the Status Register and aborts the operation without affecting the data in the
memory array.
If the Status Register bits SR4 and SR5 are set to '1', the Buffer Program Command is not
accepted. Clear the Status Register before re-issuing the command.
If the block being programmed is protected, an error is set in the Status Register and the
operation aborts without affecting the data in the memory array.
During buffer program operations the bank being programmed only accepts the Read Array,
Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase
Suspend commands, and all other commands are ignored.
Refer to Section 8 for detailed information about simultaneous operations allowed in banks
not being programmed.
See Appendix C, Figure 21: Buffer program flowchart and pseudocode for a suggested
flowchart on using the Buffer Program command.
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4.10 Buffer Enhanced Factory Program command
The Buffer Enhanced Factory Program command has been specially developed to speed up
programming in manufacturing environments where the programming time is critical.
It is used to program one or more write buffer(s) of 32 words to a block. Once the device
enters Buffer Enhanced Factory Program mode, the write buffer can be reloaded any
number of times as long as the address remains within the same block. Only one block can
be programmed at a time.
If the block being programmed is protected, then the program operation aborts, the data in
the block is not changed, and the Status Register outputs the error.
The use of the Buffer Enhanced Factory Program command requires the following operating
conditions:
●VPP must be set to VPPH
●VDD must be within operating range
●Ambient temperature TA must be 30 °C ± 10 °C
●The targeted block must be unprotected
●The start address must be aligned with the start of a 32-word buffer boundary
●The address must remain the start address throughout programming.
Dual operations are not supported during the Buffer Enhanced Factory Program operation
and the command cannot be suspended.
The Buffer Enhanced Factory Program command consists of three phases: the setup
phase, the program and verify phase, and the exit phase. Please refer to Tabl e 6: Fa c t o r y
commands for detailed information.
4.10.1 Setup phase
The Buffer Enhanced Factory Program command requires two bus write cycles to initiate the
command.
●The first bus write cycle sets up the Buffer Enhanced Factory Program command.
●The second bus write cycle confirms the command.
After the confirm command is issued, read operations output the contents of the Status
Register. The read Status Register command must not be issued or it is interpreted as data
to program.
The Status Register P/EC Bit SR7 should be read to check that the P/EC is ready to
proceed to the next phase.
If an error is detected, SR4 goes high (set to ‘1’) and the Buffer Enhanced Factory Program
operation is terminated. See Section 5: Status Register for details on the error.
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4.10.2 Program and verify phase
The program and verify phase requires 32 cycles to program the 32 words to the write
buffer. The data is stored sequentially, starting at the first address of the write buffer, until the
write buffer is full (32 words). To program less than 32 words, the remaining words should be
programmed with FFFFh.
Three successive steps are required to issue and execute the program and verify phase of
the command.
1. Use one bus write operation to latch the start address and the first word to be
programmed. The Status Register Bank Write status bit SR0 should be read to check
that the P/EC is ready for the next word.
2. Each subsequent word to be programmed is latched with a new bus write operation.
The address must remain the start address as the P/EC increments the address
location.If any address is given that is not in the same block as the start address, the
program and verify phase terminates. Status Register bit SR0 should be read between
each bus write cycle to check that the P/EC is ready for the next word.
3. Once the write buffer is full, the data is programmed sequentially to the memory array.
After the program operation the device automatically verifies the data and reprograms if
necessary.
The program and verify phase can be repeated, without re-issuing the command, to
program additional 32 word locations as long as the address remains in the same block.
4. Finally, after all words, or the entire block have been programmed, write one bus write
operation to any address outside the block containing the start address, to terminate
program and verify phase.
Status Register bit SR0 must be checked to determine whether the program operation is
finished. The Status Register may be checked for errors at any time but it must be checked
after the entire block has been programmed.
4.10.3 Exit phase
Status Register P/EC bit SR7 set to ‘1’ indicates that the device has exited the buffer
enhanced factory program operation and returned to read Status Register mode. A full
Status Register check should be done to ensure that the block has been successfully
programmed. See Section 5: Status Register for more details.
For optimum performance the Buffer Enhanced Factory Program command should be
limited to a maximum of 100 program/erase cycles per block. If this limit is exceeded the
internal algorithm continues to work properly but some degradation in performance is
possible. Typical program times are given in Ta bl e 1 6 .
See Appendix C, Figure 27: Buffer enhanced factory program flowchart and pseudocode for
a suggested flowchart on using the Buffer Enhanced Factory Program command.
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4.11 Program/Erase Suspend command
The Program/Erase Suspend command is used to pause a program or block erase
operation. The command can be addressed to any bank. The Program/Erase Resume
command is required to restart the suspended operation.
One bus write cycle is required to issue the Program/Erase Suspend command. Once the
Program/Erase Controller has paused bits SR7, SR6 and/ or SR2 of the Status Register are
set to ‘1’.
The following commands are accepted during program/erase suspend:
– Program/Erase Resume
– Read Array (data from erase-suspended block or program-suspended word is not
valid)
– Read Status Register
– Read Electronic Signature
– Read CFI query
In addition, if the suspended operation is a block erase, then the following commands are
also accepted:
– Clear Status Register
– Program (except in erase-suspended block)
– Buffer Program (except in erase suspended blocks)
– Block Protect
– Block Unprotect
During an erase suspend the block being erased can be protected by issuing the Block
Protect command. When the Program/Erase Resume command is issued, the operation
completes.
It is possible to accumulate multiple suspend operations. For example, it is possible to
suspend an erase operation, start a program operation, suspend the program operation,
and then read the array.
If a Program command is issued during a block erase suspend, the erase operation cannot
be resumed until the program operation completes.
The Program/Erase Suspend command does not change the read mode of the banks. If the
suspended bank was in read Status Register, read electronic signature or read CFI query
mode, the bank remains in that mode and outputs the corresponding data.
Refer to Section 8 for detailed information about simultaneous operations allowed during
program/erase suspend.
During a program/erase suspend, the device can be placed in standby mode by taking Chip
Enable to VIH. Program/erase is aborted if Reset, RP, goes to VIL.
See Appendix C, Figure 22: Program suspend and resume flowchart and pseudocode, and
Figure 24: Erase suspend and resume flowchart and pseudocode for flowcharts for using
the Program/Erase Suspend command.
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4.12 Program/Erase Resume command
The Program/Erase Resume command restarts the program or erase operation suspended
by the Program/Erase Suspend command. One bus write cycle is required to issue the
command, and the command can be issued to any address.
The Program/Erase Resume command does not change the read mode of the banks. If the
suspended bank was in read Status Register, read electronic signature or read CFI query
mode, the bank remains in that mode and outputs the corresponding data.
If a program command is issued during a block erase suspend, then the erase cannot be
resumed until the program operation completes.
See Appendix C, Figure 22: Program suspend and resume flowchart and pseudocode, and
Figure 24: Erase suspend and resume flowchart and pseudocode for flowcharts for using
the Program/Erase Resume command.
4.13 Protection Register Program command
The Protection Register Program command programs the user OTP segments of the
Protection Register and the two Protection Register Locks.
The device features 16 OTP segments of 128 bits and one OTP segment of 64 bits, as
shown in Figure 4: Protection Register memory map.
The segments are programmed one word at a time. When shipped all bits in the segment
are set to ‘1’. The user can only program the bits to ‘0’.
Two bus write cycles are required to issue the Protection Register Program command.
●The first bus cycle sets up the Protection Register Program command.
●The second latches the address and data to be programmed to the Protection Register
and starts the Program/Erase Controller.
Read operations to the bank being programmed output the Status Register content after the
program operation has started. Attempting to program a previously protected Protection
Register results in a Status Register error.
The Protection Register program cannot be suspended. Dual operations between the
parameter bank and the Protection Register memory space are not allowed (see Ta bl e 15 :
Dual operation limitations for details)
The two Protection Register Locks protect the OTP segments from further modification. The
protection of the OTP segments is not reversible. Refer to Figure 4: Protection Register
memory map and Table 8: Protection Register locks for details on the lock bits.
See Appendix C, Figure 26: Protection Register program flowchart and pseudocode for a
flowchart for using the Protection Register Program command.
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4.14 Set Configuration Register command
The Set Configuration Register command writes a new value to the Configuration Register.
Two bus write cycles are required to issue the Set Configuration Register command.
●The first cycle sets up the Set Configuration Register command and the address
corresponding to the Configuration Register content.
●The second cycle writes the Configuration Register data and the confirm command.
The Configuration Register data must be written as an address during the bus write cycles,
that is A0 = CR0, A1 = CR1, …, A15 = CR15. Addresses A16-A23 are ignored.
Read operations output the array content after the Set Configuration Register command is
issued.
The Read Electronic Signature command is required to read the updated contents of the
Configuration Register.
4.15 Block Protect command
The Block Protect command protects a block and prevents program or erase operations
from changing the data in it. All blocks are protected after power-up or reset.
Two bus write cycles are required to issue the Block Protect command.
●The first bus cycle sets up the Block Protect command.
●The second bus write cycle latches the block address and protects the block.
Once the command has been issued, subsequent bus read operations read the Status
Register.
The protection status can be monitored for each block using the Read Electronic Signature
command.
Refer to Section 9: Block protection for a detailed explanation. See Appendix C, Figure 25:
Protect/unprotect operation flowchart and pseudocode for a flowchart for using the Block
Protect command.
4.16 Block Unprotect command
The Block Unprotect command unprotects a block, allowing the block to be programmed or
erased.
Two bus write cycles are required to issue the Block Unprotect command.
●The first bus cycle sets up the Block Unprotect command.
●The second bus write cycle latches the block address and unprotects the block.
Once the command has been issued, subsequent bus read operations read the Status
Register.
The protection status can be monitored for each block using the Read Electronic Signature
command. Refer to Section 9: Block protection for a detailed explanation and Appendix C,
Figure 25: Protect/unprotect operation flowchart and pseudocode for a flowchart for using
the Block Unprotect command.
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Table 5. Standard commands(1)
1. X = ‘don't care’, WA = Word Address in targeted bank, RD = Read Data, SRD = Status Register Data,
ESD = Electronic Signature Data, QD = Query Data, BA = Block Address, BKA = Bank Address, PD =
Program Data, PRA = Protection Register Address, PRD = Protection Register Data, CRD = Configuration
Register Data.
Commands
Cycles
Bus operations
1st cycle 2nd cycle
Op. Add Data Op. Add Data
Read Array 1+ Write BKA FFh Read WA RD
Read Status Register 1+ Write BKA 70h Read BKA(2)
2. Must be same bank as in the first cycle. The signature addresses are listed in Table 7.
SRD
Read Electronic Signature 1+ Write BKA 90h Read BKA(2) ESD
Read CFI query 1+ Write BKA 98h Read BKA(2) QD
Clear Status Register 1 Write X 50h
Block Erase 2 Write BKA or
BA(3)
3. Any address within the bank can be used.
20h Write BA D0h
Program 2 Write BKA or
WA(3)
40h or
10h Write WA PD
Buffer Program(4)
4. n+1 is the number of words to be programmed.
n+4
Write BA E8h Write BA n
Write PA1PD1Write PA2PD2
Write PAn+1 PDn+1 Write X D0h
Program/Erase Suspend 1 Write X B0h
Program/Erase Resume 1 Write X D0h
Protection Register Program 2 Write PRA C0h Write PRA PRD
Set Configuration Register 2 Write CRD 60h Write CRD 03h
Block Protect 2 Write BKA or
BA(3) 60h Write BA 01h
Block Unprotect 2 Write BKA or
BA(3) 60h Write BA D0h
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Table 6. Factory commands
Command Phase
Cycles
Bus write operations(1)
1. WA = Word Address in targeted bank, BKA = Bank Address, PD = Program Data, BA = Block Address, X =
‘don’t care’.
1st 2nd 3rd Final -1 Final
Add Data Add Data Add Data Add Data Add Data
Blank
Check 2 BA BCh BA CBh
Buffer
Enhanced
Factory
Program
Setup 2 BKA or
WA(2)
2. Any address within the bank can be used.
80h WA1D0h
Program/
verify(3)
3. The program/verify phase can be executed any number of times as long as the data is to be programmed
to the same block.
≥32 WA1PD1WA1PD2WA1PD3WA1PD31 WA1PD32
Exit 1 NOT
BA1(4)
4. WA1 is the Start Address, NOT BA1 = Not Block Address of WA1.
X
Table 7. Electronic signature codes
Code Address (h) Data (h)
Manufacturer code Bank address + 000 0020
Device code Top Bank address + 001 885E (M58LT256JST)
Bottom Bank address + 001 885F (M58LT256JSB)
Block protection Protected Block address + 002 0001
Unprotected 0000
Configuration Register Bank address + 005 CR(1)
1. CR = Configuration Register, PRLD = Protection Register Lock Data.
Protection Register
PR0 lock
Numonyx factory default
Bank address + 080
0002
OTP area permanently
protected 0000
Protection Register PR0
Bank address + 081
Bank address + 084 Unique device number
Bank address + 085
Bank address + 088 OTP Area
Protection Register PR1 through PR16 lock Bank address + 089 PRLD(1)
Protection Registers PR1-PR16 Bank address + 08A
Bank address + 109 OTP Area
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Figure 4. Protection Register memory map
AI07563
User Programmable OTP
Unique device number
Protection Register Lock 1 0
88h88h
85h
84h
81h
80h
User Programmable OTP
PROTECTION REGISTERS
User Programmable OTP
Protection Register Lock 1043297513 12 1011 8 6
14
15
PR1
PR16
PR0
89h
8Ah
91h
102h
109h
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Table 8. Protection Register locks
Lock
Description
Number Address Bits
Lock 1 80h
Bit 0 Pre-programmed to protect Unique Device Number, address
81h to 84h in PR0
Bit 1 Protects 64 bits of OTP segment, address 85h to 88h in PR0
Bits 2 to 15 Reserved
Lock 2 89h
Bit 0 Protects 128 bits of OTP segment PR1
Bit 1 Protects 128 bits of OTP segment PR2
Bit 2 Protects 128 bits of OTP segment PR3
----
----
Bit 13 Protects 128 bits of OTP segment PR14
Bit 14 Protects 128 bits of OTP segment PR15
Bit 15 Protects 128 bits of OTP segment PR16
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5 Status Register
The Status Register provides information on the current or previous program or erase
operations. Issue a Read Status Register command to read the contents of the Status
Register (refer to Section 4.2 for more details). To output the contents, the Status Register is
latched and updated on the falling edge of the Chip Enable or Output Enable signals, and
can be read until Chip Enable or Output Enable returns to VIH. The Status Register can only
be read using single asynchronous or single synchronous reads. Bus read operations from
any address within the bank always read the Status Register during program and erase
operations if no Read Array command has been issued.
The various bits convey information about the status and any errors of the operation. Bits
SR7, SR6, SR2 and SR0 give information on the status of the device and are set and reset
by the device. Bits SR5, SR4, SR3 and SR1 give information on errors, they are set by the
device but must be reset by issuing a Clear Status Register command or a hardware reset.
If an error bit is set to ‘1’ the Status Register should be reset before issuing another
command.
The bits in the Status Register are summarized in Table 9: Status Register bits. Refer to
Ta bl e 9 in conjunction with the following sections.
5.1 Program/Erase Controller status bit (SR7)
The Program/Erase Controller status bit indicates whether the Program/Erase Controller is
active or inactive in any bank.
When the Program/Erase Controller status bit is Low (set to ‘0’), the Program/Erase
Controller is active. When the bit is High (set to ‘1’), the Program/Erase Controller is inactive,
and the device is ready to process a new command.
The Program/Erase Controller status bit is Low immediately after a Program/Erase Suspend
command is issued until the Program/Erase Controller pauses. After the Program/Erase
Controller pauses, the bit is High.
5.2 Erase suspend status bit (SR6)
The erase suspend status bit indicates that an erase operation has been suspended in the
addressed block. When the erase suspend status bit is High (set to ‘1’), a Program/Erase
Suspend command has been issued and the memory is waiting for a Program/Erase
Resume command.
The erase suspend status bit should only be considered valid when the Program/Erase
Controller status bit is High (Program/Erase Controller inactive). SR6 is set within the erase
suspend latency time of the Program/Erase Suspend command being issued, therefore, the
memory may still complete the operation rather than entering the suspend mode.
When a Program/Erase Resume command is issued the erase suspend status bit returns
Low.
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5.3 Erase/blank check status bit (SR5)
The erase/blank check status bit identifies if there was an error during a block erase
operation. When the erase/blank check status bit is High (set to ‘1’), the Program/Erase
Controller has applied the maximum number of pulses to the block and still failed to verify
that it has erased correctly.
The erase/blank check status bit should be read once the Program/Erase Controller status
bit is High (Program/Erase Controller inactive).
The erase/blank check status bit also indicates whether an error occurred during the Blank
Check operation. If the data at one or more locations in the block where the Blank Check
command has been issued is different from FFFFh, SR5 is set to '1'.
Once set High, the erase/blank check status bit must be set Low by a Clear Status Register
command or a hardware reset before a new erase command is issued, otherwise, the new
command appears to fail.
5.4 Program status bit (SR4)
The program status bit is used to identify if there was an error during a program operation.
The program status bit should be read once the Program/Erase Controller status bit is High
(Program/Erase Controller inactive).
When the program status bit is High (set to ‘1’), the Program/Erase Controller has applied
the maximum number of pulses to the word and still failed to verify that it has programmed
correctly.
Once set High, the program status bit must be set Low by a Clear Status Register command
or a hardware reset before a new program command is issued; otherwise, the new
command appears to fail.
5.5 VPP status bit (SR3)
The VPP status bit identifies an invalid voltage on the VPP pin during program and erase
operations. The VPP pin is only sampled at the beginning of a program or erase operation.
Program and erase operations are not guaranteed if VPP becomes invalid during an
operation.
When the VPP status bit is Low (set to ‘0’), the voltage on the VPP pin was sampled at a valid
voltage.
When the VPP status bit is High (set to ‘1’), the VPP pin has a voltage that is below the VPP
lockout voltage, VPPLK, the memory is protected and program and erase operations cannot
be performed.
Once set High, the VPP status bit must be set Low by a Clear Status Register command or a
hardware reset before a new program or erase command is issued; otherwise, the new
command appears to fail.
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5.6 Program suspend status bit (SR2)
The program suspend status bit indicates that a program operation has been suspended in
the addressed block. The program suspend status bit should only be considered valid when
the Program/Erase Controller status bit is High (Program/Erase Controller inactive).
When the program suspend status bit is High (set to ‘1’), a Program/Erase Suspend
command has been issued and the memory is waiting for a Program/Erase Resume
command.
SR2 is set within the program suspend latency time of the Program/Erase Suspend
command being issued, therefore, the memory may still complete the operation rather than
entering the suspend mode.
When a Program/Erase Resume command is issued, the Program Suspend status bit
returns Low.
5.7 Block protection status bit (SR1)
The block protection status bit i identifies if a program or block erase operation has tried to
modify the contents of a protected block.
When the block protection status bit is High (set to ‘1’), a program or erase operation has
been attempted on a protected block.
Once set High, the block protection status bit must be set Low by a Clear Status Register
command or a hardware reset before a new program or erase command is issued;
otherwise, the new command appears to fail.
5.8 Bank write/multiple word program status bit (SR0)
The bank write status bit indicates whether the addressed bank is programming or erasing.
In buffer enhanced factory program mode the multiple word program bit shows if the device
is ready to accept a new word to be programmed to the memory array.
The bank write status bit should only be considered valid when the Program/Erase
Controller status bit SR7 is Low (set to ‘0’).
When both the Program/Erase Controller status bit and the bank write status bit are Low (set
to ‘0’), the addressed bank is executing a program or erase operation. When the
Program/Erase Controller status bit is Low (set to ‘0’) and the bank write status bit is High
(set to ‘1’), a program or erase operation is being executed in a bank other than the one
being addressed.
In buffer enhanced factory program mode if the multiple word program status bit is Low (set
to ‘0’), the device is ready for the next word. If the multiple word program status bit is High
(set to ‘1’), the device is not ready for the next word.
For further details on how to use the Status Register, see the flowcharts and pseudocodes
provided in Appendix C.
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Table 9. Status Register bits
Bit Name Type Logic
level(1)
1. Logic level '1' is High, '0' is Low.
Definition
SR7 P/EC status Status '1' Ready
'0' Busy
SR6 Erase suspend status Status '1' Erase suspended
'0' Erase In progress or completed
SR5 Erase/blank check
status Error '1' Erase/blank check error
'0' Erase/blank check success
SR4 Program status Error '1' Program error
'0' Program success
SR3 VPP status Error '1' VPP invalid, abort
'0' VPP OK
SR2 Program suspend
status Status '1' Program suspended
'0' Program in progress or completed
SR1 Block protection
status Error '1' Program/erase on protected block, abort
'0' No operation to protected blocks
SR0
Bank write status Status
'1'
SR7 = ‘1’ Not allowed
SR7 = ‘0’ Program or erase operation in a bank
other than the addressed bank
'0'
SR7 = ‘1’ No program or erase operation in the
device
SR7 = ‘0’ Program or erase operation in
addressed bank
Multiple word
program status (buffer
enhanced factory
program mode)
Status
'1'
SR7 = ‘1’ Not allowed
SR7 = ‘0’
The device is NOT ready for the next
buffer loading or is going to exit the
BEFP mode
'0'
SR7 = ‘1’ The device has exited the BEFP
mode
SR7 = ‘0’ The device is ready for the next buffer
loading
Configuration Register M58LT256JST, M58LT256JSB
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6 Configuration Register
The Configuration Register configures the type of bus access that the memory performs.
Refer to Section 7 for details on read operations.
The Configuration Register is set through the command interface using the Set
Configuration Register command. After a reset or power-up the device is configured for
asynchronous read (CR15 = 1). The Configuration Register bits are described in Ta bl e 1 1
The bits specify the selection of the burst length, burst type, burst X latency and the read
operation. Refer to Figures 5 and 6 for examples of synchronous burst configurations.
6.1 Read select bit (CR15)
The read select bit, CR15, switches between asynchronous and synchronous read
operations.
When the read select bit is set to ’1’, read operations are asynchronous. When the read
select bit is set to ’0’, read operations are synchronous.
Synchronous burst read is supported in both parameter and main blocks and can be
performed across banks.
On reset or power-up the read select bit is set to ’1’ for asynchronous access.
6.2 X latency bits (CR13-CR11)
The X latency bits are used during synchronous read operations to set the number of clock
cycles between the address being latched and the first data becoming available. Refer to
Figure 5: X latency and data output configuration example.
For correct operation the X latency bits can only assume the values in Table 11:
Configuration Register.
Ta bl e 1 0 shows how to set the X latency parameter, taking into account the speed class of
the device and the frequency used to read the Flash memory in synchronous mode.
Table 10. X latency settings
fmax tKmin X latency min
30 MHz 33 ns 3
40 MHz 25 ns 4
52 MHz 19 ns 5
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6.3 Wait polarity bit (CR10)
The wait polarity bit sets the polarity of the Wait signal used in synchronous burst read
mode. During synchronous burst read mode the Wait signal indicates whether the data
output are valid or a WAIT state must be inserted.
When the Wait polarity bit is set to ‘0’, the Wait signal is active Low. When the wait polarity
bit is set to ‘1’ the Wait signal is active High.
6.4 Data output configuration bit (CR9)
The data output configuration bit configures the output to remain valid for either one or two
clock cycles during synchronous mode.
When the data output configuration bit is ’0’ the output data is valid for one clock cycle, and
when it is ’1’, the output data is valid for two clock cycles.
The data output configuration bit must be configured using the following condition:
●tK > tKQV + tQVK_CPU
where
●tK is the clock period
●tQVK_CPU is the data setup time required by the system CPU
●tKQV is the clock to data valid time.
If this condition is not satisfied, the data output configuration bit should be set to ‘1’ (two
clock cycles). Refer to Figure 5: X latency and data output configuration example.
6.5 Wait configuration bit (CR8)
The wait configuration bit controls the timing of the Wait output pin, WAIT, in synchronous
burst read mode.
When WAIT is asserted, data is not valid, and when WAIT is de-asserted, data is valid.
When the wait configuration bit is Low (set to ’0’), the wait output pin is asserted during the
WAIT state. When the wait configuration bit is High (set to ’1’), the wait output pin is
asserted one data cycle before the WAIT state.
6.6 Burst type bit (CR7)
The burst type bit determines the sequence of addresses read during synchronous burst
reads.
The burst type bit is High (set to ’1’), as the memory outputs from sequential addresses only.
See Table 12: Burst type definition for the sequence of addresses output from a given
starting address in sequential mode.
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6.7 Valid clock edge bit (CR6)
The valid clock edge bit, CR6, configures the active edge of the Clock, K, during
synchronous read operations. When the valid clock edge bit is Low (set to ’0’) the falling
edge of the Clock is the active edge. When the valid clock edge bit is High (set to ’1’) the
rising edge of the Clock is the active edge.
6.8 Wrap burst bit (CR3)
The wrap burst bit, CR3, selects between wrap and no wrap. Synchronous burst reads can
be confined inside the 4 or 8-word boundary (wrap) or overcome the boundary (no wrap).
When the wrap burst bit is Low (set to ‘0’), the burst read wraps. When it is High (set to ‘1’)
the burst read does not wrap.
6.9 Burst length bits (CR2-CR0)
The burst length bits sets the number of words to be output during a synchronous burst read
operation as result of a single address latch cycle.
They can be set for 4 words, 8 words, 16 words or continuous burst, where all the words are
read sequentially. In continuous burst mode the burst sequence can cross bank boundaries.
In continuous burst mode, in 4, 8 or 16-word no-wrap, depending on the starting address,
the device asserts the WAIT signal to indicate that a delay is necessary before the data is
output.
If the starting address is aligned to an 8-word boundary, no WAIT state is needed and the
WAIT output is not asserted. If the starting address is not aligned to an 8-word boundary,
WAIT becomes asserted when the burst sequence crosses the first 8-word boundary to
indicate that the device needs an internal delay to read the successive words in the array.
WAIT is asserted only once during a continuous burst access. See also Table 12: Burst type
definition.
CR14, CR5 and CR4 are reserved for future use.
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Table 11. Configuration Register
Bit Description Value Description
CR15 Read select 0 Synchronous read
1 Asynchronous read (default at power-on)
CR14 Reserved
CR13-CR11 X latency
010 2 clock latency(1)
1. The combination X latency=2, Data held for two clock cycles and Wait active one data cycle before the
WAIT state is not supported.
011 3 clock latency
100 4 clock latency
101 5 clock latency
110 6 clock latency
111 7 clock latency (default)
Other configurations reserved
CR10 Wait polarity 0 WAIT is active Low
1 WAIT is active High (default)
CR9 Data output configuration 0 Data held for one clock cycle
1 Data held for two clock cycles (default)(1)
CR8 Wait configuration
0 WAIT is active during WAIT state
1WAIT is active one data cycle before WAIT
state(1) (default)
CR7 Burst type 0Reserved
1 Sequential (default)
CR6 Valid clock edge 0 Falling Clock edge
1 Rising Clock edge (default)
CR5-CR4 Reserved
CR3 Wrap burst 0Wrap
1 No wrap (default)
CR2-CR0 Burst length
001 4 words
010 8 words
111 Continuous (default)
Configuration Register M58LT256JST, M58LT256JSB
42/108
Table 12. Burst type definition
Mode
Start
add.
Sequential
Continuous burst
4 words 8 words 16 words
Wrap
0 0-1-2-3 0-1-2-3-4-5-6-7
N/A
0-1-2-3-4-5-6...
1 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-5-6-7...
2 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5-6-7-8...
3 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5-6-7-8-9...
...
7 7-4-5-6 7-0-1-2-3-4-5-6 7-8-9-10-11-12-
13...
...
12 12-13-14-15 12-13-14-15-8-9-
10-11
12-13-14-15-16-
17...
13 13-14-15-12 13-14-15-8-9-10-
11-12
13-14-15-16-17-
18...
14 14-15-12-13 14-15-8-9-10-11-
12-13
14-15-16-17-18-
19...
15 15-12-13-14 15-8-9-10-11-12-
13-14
15-16-17-18-19-
20...
No-wrap
0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15
Same as for wrap
(wrap /no wrap
has no effect on
continuous burst)
1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3-4-5-6-7-8--9-10-11-12-13-14-15-16
2 2-3-4-5 2-3-4-5-6-7-8-9... 2-3-4-5--6-7-8-9-10-11-12-13-14-15-16-17
3 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5-6-7-8-9-10-11-12-13-14-15-16-17-18
...
7 7-8-9-10 7-8-9-10-11-12-13-
14
7-8-9-10-11-12-13-14-15-16-17-18-19-20-
21-22
...
12 12-13-14-15 12-13-14-15-16-17-
18-19
12-13-14-15-16-17-18-19-20-21-22-23-24-
25-26-27
13 13-14-15-16 13-14-15-16-17-18-
19-20
13-14-15-16-17-18-19-20-21-22-23-24-25-
26-27-28
14 14-15-16-17 14-15-16-17-18-19-
20-21
14-15-16-17-18-19-20-21-22-23-24-25-26-
27-28-29
15 15-16-17-18 15-16-17-18-19-20-
21-22
15-16-17-18-19-20-21-22-23-24-25-26-27-
28-29-30
M58LT256JST, M58LT256JSB Configuration Register
43/108
Figure 5. X latency and data output configuration example
1. The settings shown are X latency = 4, data output held for one clock cycle.
Figure 6. Wait configuration example
AI08904
A23-A0 VALID ADDRESS
K
L
DQ15-DQ0
VALID DATA
X-latency
VALID DATA
tACC
tAVK_CPU tKtQVK_CPU
tQVK_CPU
tKQV
1st cycle 2nd cycle 3rd cycle 4th cycle
E
tDELAY
AI08905
A23-A0 VALID ADDRESS
K
L
DQ15-DQ0 VALID DATA
WAIT
CR8 = '0'
CR10 = '0'
WAIT
CR8 = '1'
CR10 = '0'
VALID DATA NOT VALID VALID DATA
E
WAIT
CR8 = '0'
CR10 = '1'
WAIT
CR8 = '1'
CR10 = '1'
Read modes M58LT256JST, M58LT256JSB
44/108
7 Read modes
Read operations can be performed in two different ways depending on the settings in the
Configuration Register. If the clock signal is ‘don’t care’ for the data output, the read
operation is asynchronous. If the data output is synchronized with clock, the read operation
is synchronous.
The read mode and format of the data output are determined by the Configuration Register.
(See Section 6: Configuration Register for details). All banks support both asynchronous
and synchronous read operations.
7.1 Asynchronous read mode
In asynchronous read operations the clock signal is ‘don’t care’. The device outputs the data
corresponding to the address latched, that is the memory array, Status Register, common
Flash interface or the electronic signature, depending on the command issued. CR15 in the
Configuration Register must be set to ‘1’ for asynchronous operations.
Asynchronous read operations can be performed in two different ways, asynchronous
random access read and asynchronous page read. Only asynchronous page read takes full
advantage of the internal page storage so different timings are applied.
In asynchronous read mode a page of data is internally read and stored in a page buffer.
The page has a size of 8 words and is addressed by address inputs A0, A1 and A2. The first
read operation within the page has a longer access time (tAVQV, random access time),
subsequent reads within the same page have much shorter access times (tAVQV1, page
access time). If the page changes then the normal, longer timings apply again.
The device features an automatic standby mode. During asynchronous read operations,
after a bus inactivity of 150 ns, the device automatically switches to the automatic standby
mode. In this condition the power consumption is reduced to the standby value and the
outputs are still driven.
In asynchronous read mode, the WAIT signal is always de-asserted.
See Table 22: Asynchronous read AC characteristics, Figure 9: Asynchronous random
access read AC waveforms for details.
M58LT256JST, M58LT256JSB Read modes
45/108
7.2 Synchronous burst read mode
In synchronous burst read mode the data is output in bursts synchronized with the clock. It is
possible to perform burst reads across bank boundaries.
Synchronous burst read mode can only be used to read the memory array. For other read
operations, such as read Status Register, read CFI and read electronic signature, single
synchronous read or asynchronous random access read must be used.
In synchronous burst read mode the flow of the data output depends on parameters that are
configured in the Configuration Register.
A burst sequence starts at the first clock edge (rising or falling depending on valid clock
edge bit CR6 in the Configuration Register) after the falling edge of Latch Enable or Chip
Enable, whichever occurs last. Addresses are internally incremented and data is output on
each data cycle after a delay which depends on the X latency bits CR13-CR11 of the
Configuration Register.
The number of words to be output during a synchronous burst read operation can be
configured as 4 words, 8 words, 16 words or continuous (burst length bits CR2-CR0). The
data can be configured to remain valid for one or two clock cycles (data output configuration
bit CR9).
The order of the data output can be modified through the wrap burst bit in the Configuration
Register. The burst sequence is sequential and can be confined inside the 4 or 8-word
boundary (wrap) or overcome the boundary (no wrap).
The WAIT signal may be asserted to indicate to the system that an output delay is occurring.
This delay depends on the starting address of the burst sequence and on the burst
configuration.
WAIT is asserted during the X latency, the WAIT state and at the end of a 4, 8 and 16-word
burst. It is only de-asserted when output data is valid. In continuous burst read mode a
WAIT state occurs when crossing the first 16-word boundary. If the starting address is
aligned to the burst length (4, 8 or 16 words), the wrapped configuration has no impact on
the output sequence.
The WAIT signal can be configured to be active Low or active High by setting CR10 in the
Configuration Register.
See Table 23: Synchronous read AC characteristics and Figure 11: Synchronous burst read
AC waveforms for details.
7.2.1 Synchronous burst read suspend
A synchronous burst read operation can be suspended, freeing the data bus for other higher
priority devices. It can be suspended during the initial access latency time (before data is
output) or after the device has output data. When the synchronous burst read operation is
suspended, internal array sensing continues and any previously latched internal data is
retained. A burst sequence can be suspended and resumed as often as required as long as
the operating conditions of the device are met.
A synchronous burst read operation is suspended when Chip Enable, E, is Low and the
current address has been latched (on a Latch Enable rising edge or on a valid clock edge).
The Clock signal is then halted at VIH or at VIL, and Output Enable, G, goes High.
When Output Enable, G, becomes Low again and the Clock signal restarts, the
synchronous burst read operation is resumed exactly where it stopped.
Read modes M58LT256JST, M58LT256JSB
46/108
WAIT being gated by E, it remains active and does not revert to high impedance when G
goes High. So if two or more devices are connected to the system’s READY signal, to
prevent bus contention the WAIT signal of the M58LT256JST/B should not be directly
connected to the system’s READY signal.
WAIT reverts to high-impedance when Chip Enable, E, goes High.
See Table 23: Synchronous read AC characteristics and Figure 13: Synchronous burst read
suspend AC waveforms for details.
7.3 Single synchronous read mode
Single synchronous read operations are similar to synchronous burst read operations,
except that the memory outputs the same data to the end of the operation.
Synchronous single reads are used to read the electronic signature, Status Register, CFI,
block protection status, Configuration Register status or Protection Register. When the
addressed bank is in read CFI, read Status Register or read electronic signature mode, the
WAIT signal is asserted during the X latency and at the end of a 4, 8 and 16-word burst. It is
only de-asserted when output data are valid.
See Table 23: Synchronous read AC characteristics and Figure 11: Synchronous burst read
AC waveforms for details.
M58LT256JST, M58LT256JSB Dual operations and multiple bank architecture
47/108
8 Dual operations and multiple bank architecture
The multiple bank architecture of the M58LT256JST/B gives greater flexibility for software
developers to split the code and data spaces within the memory array. The dual operations
feature simplifies the software management of the device by allowing code to be executed
from one bank while another bank is being programmed or erased.
The dual operations feature means that while programming or erasing in one bank, read
operations are possible in another bank with zero latency (only one bank at a time is allowed
to be in program or erase mode).
If a read operation is required in a bank, which is programming or erasing, the program or
erase operation can be suspended. Also if the suspended operation is erase, then a
program command can be issued to another block. This means the device can have one
block in erase suspend mode, one programming, and other banks in read mode.
Bus read operations are allowed in another bank between setup and confirm cycles of
program or erase operations.
By using a combination of these features, read operations are possible at any moment in the
M58LT256JST/B device.
Dual operations between the parameter bank and either of the CFI, the OTP or the
electronic signature memory space are not allowed. Ta bl e 1 5 shows which dual operations
are allowed or not between the CFI, the OTP, the electronic signature locations and the
memory array.
Tabl e s 13 and 14 show the dual operations possible in other banks and in the same bank.
Dual operations and multiple bank architecture M58LT256JST, M58LT256JSB
48/108
Table 13. Dual operations allowed in other banks
Status of bank
Commands allowed in another bank
Read
Array
Read
Status
Register
Read
CFI
query
Read
Electronic
Signature
Program,
Buffer
Program
Block
Erase
Program
/Erase
Suspend
Program
/Erase
Resume
I d l e Ye s Ye s Ye s Ye s Ye s Ye s Ye s Ye s
Programming Yes Yes Yes Yes – – Yes –
Erasing Yes Yes Yes Yes – – Yes –
Program
suspended Ye s Ye s Ye s Ye s – – – Ye s
Erase
suspended Ye s Ye s Ye s Ye s Ye s – – Ye s
Table 14. Dual operations allowed in same bank
Status of bank
Commands allowed in same bank
Read
Array
Read
Status
Register
Read
CFI
query
Read
Electronic
Signature
Program,
Buffer
Program
Block
Erase
Program
/Erase
Suspend
Program
/Erase
Resume
I d l e Ye s Ye s Ye s Ye s Ye s Ye s Ye s Ye s
Programming –(1)
1. The Read Array command is accepted but the data output is not guaranteed until the Program or Erase
has completed.
Ye s Ye s Ye s – – Ye s –
Erasing –(1) Ye s Ye s Ye s – – Ye s –
Program
suspended Ye s (2)
2. Not allowed in the Block that is being erased or in the word that is being programmed.
Ye s Ye s Ye s – – – Ye s
Erase
suspended Ye s (2) Ye s Ye s Ye s Ye s (1) –– Yes
M58LT256JST, M58LT256JSB Dual operations and multiple bank architecture
49/108
Table 15. Dual operation limitations
Current status
Commands allowed
Read CFI/OTP /
electronic
signature
Read
parameter
blocks
Read main blocks
Located in
parameter
bank
Not located in
parameter
bank
Programming/erasing
parameter blocks No No No Yes
Programming/
erasing main
blocks
Located in
parameter
bank
Ye s N o N o Ye s
Not located in
parameter
bank
Ye s Ye s Ye s In different
bank only
Programming OTP No No No No
Block protection M58LT256JST, M58LT256JSB
50/108
9 Block protection
The M58LT256JST/B features an instant, individual block protection scheme that allows any
block to be protected or unprotected with no latency. This protection scheme has two levels
of protection.
●Protect/unprotect - this first level allows software only control of block protection.
●VPP ≤ VPPLK - this second level offers a complete hardware protection against program
and erase on all blocks.
The protection status of each block can be set to protected and unprotected. Appendix C,
Figure 25 shows a flowchart for the protection operations.
9.1 Reading a block’s protection status
The protection status of every block can be read in the read electronic signature mode of the
device. To enter this mode issue the Read Electronic Signature command. Subsequent
reads at the address specified in Ta b l e 7 output the protection status of that block.
The protection status is represented by DQ0. DQ0 indicates the block protect/unprotect
status, is set by the Protect command, and cleared by the Unprotect command.
The following sections explain the operation of the protection system.
9.2 Protected state
The default status of all blocks on power-up or after a hardware reset is protected (state =
1). Protected blocks are fully protected from program or erase operations. Any program or
erase operations attempted on a protected block return an error in the Status Register. The
status of a protected block can be changed to unprotected using the appropriate software
commands. An unprotected block can be protected by issuing the Protect command.
9.3 Unprotected state
Unprotected blocks (state = 0) can be programmed or erased. All unprotected blocks return
to the protected state after a hardware reset or when the device is powered-down. The
status of an unprotected block can be changed to protected using the appropriate software
commands. A protected block can be unprotected by issuing the Unprotect command.
M58LT256JST, M58LT256JSB Block protection
51/108
9.4 Protection operations during erase suspend
Changes to block protection status can be performed during an erase suspend by using the
standard protection command sequences to unprotect or protect a block. This is useful in
the case when another block needs to be updated while an erase operation is in progress.
To change block protection during an erase operation, first write the Erase Suspend
command, then check the Status Register until it indicates that the erase operation has
been suspended. Next, write the desired protect command sequence to a block and the
protection status is changed. After completing any desired protect, read, or program
operations, resume the erase operation with the Erase Resume command.
If a block is protected during an erase suspend of the same block, the erase operation
completse when the erase is resumed. Protection operations cannot be performed during a
program suspend.
Program and erase times and endurance cycles M58LT256JST, M58LT256JSB
52/108
10 Program and erase times and endurance cycles
The program and erase times and the number of program/erase cycles per block are shown
in Ta b l e 1 6 . Exact erase times may change depending on the memory array condition. The
best case is when all the bits in the block are at ‘0’ (pre-programmed). The worst case is
when all the bits in the block are at ‘1’ (not pre-programmed). Usually, the system overhead
is negligible with respect to the erase time. In the M58LT256JST/B the maximum number of
program/erase cycles depends on the VPP voltage supply used.
Table 16. Program/erase times and endurance cycles(1), (2)
Parameter Condition Min Typ
Typical after
100 kW/E
cycles
Max Unit
VPP = VDD
Erase
Parameter block (16 KWord) 0.4 1 2.5 s
Main Block
(64 KWord)
Pre-programmed 1 3 4 s
Not pre-programmed 1.2 4 s
Program(3)
Single word Word Program 80 400 µs
Buffer Program 80 400 µs
Buffer (32 words) (buffer program) 300 1200 µs
Main block (64 KWord) 600 ms
Suspend latency Program 20 25 µs
Erase 20 25 µs
Program/erase
cycles (per block)
Main blocks 100 000 cycles
Parameter blocks 100 000 cycles
VPP = VPPH
Erase Parameter block (16 KWord) 0.4 2.5 s
Main block (64 KWord) 1 4 s
Program(3)
Single word
Word program 80 400 µs
Buffer enhanced factory
program(4) 5400µs
Buffer (32
words)
Buffer program 180 1200 µs
Buffer enhanced factory program 150 1000 µs
Main Block
(64 KWords)
Buffer program 360 ms
Buffer enhanced factory program 300 ms
Bank (16
Mbits)
Buffer program 5.8 s
Buffer enhanced factory program 4.8 s
Program/erase
cycles (per block)
Main blocks 1000 cycles
Parameter blocks 2500 cycles
Blank check Main blocks 2 ms
Parameter blocks 0.5 ms
1. TA = –25 to 85 °C; VDD = 1.7 V to 2 V; VDDQ = 1.7 V to 3.6 V.
2. Values are liable to change with the external system-level overhead (command sequence and Status Register polling
execution).
3. Excludes the time needed to execute the command sequence.
4. This is an average value on the entire device.
M58LT256JST, M58LT256JSB Maximum ratings
53/108
11 Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the Numonyx SURE Program
and other relevant quality documents.
Table 17. Absolute maximum ratings
Symbol Parameter
Value
Unit
Min Max
TAAmbient operating temperature –40 85 °C
TBIAS Temperature under bias –40 85 °C
TSTG Storage temperature –65 125 °C
VIO Input or output voltage –0.5 4.2 V
VDD Supply voltage –0.2 2.5 V
VDDQ Input/output supply voltage –0.2 3.8 V
VPP Program voltage –0.2 10 V
IOOutput short circuit current 100 mA
tVPPH Time for VPP at VPPH 100 hours
DC and AC parameters M58LT256JST, M58LT256JSB
54/108
12 DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics tables that
follow are derived from tests performed under the measurement conditions summarized in
Table 18: Operating and AC measurement conditions. Designers should check that the
operating conditions in their circuit match the operating conditions when relying on the
quoted parameters.
Figure 7. AC measurement I/O waveform
Table 18. Operating and AC measurement conditions
Parameter
M58LT256JST/B
Units85
Min Max
VDD supply voltage 1.7 2.0 V
VDDQ supply voltage 2.7 3.6 V
VPP supply voltage (factory environment) 8.5 9.5 V
VPP supply voltage (application environment) –0.4 VDDQ + 0.4 V
Ambient operating temperature –25 85 °C
Load capacitance (CL)30pF
Input rise and fall times 5 ns
Input pulse voltages 0 to VDDQ V
Input and output timing ref. voltages VDDQ/2 V
AI06161
VDDQ
0V
VDDQ/2
M58LT256JST, M58LT256JSB DC and AC parameters
55/108
Figure 8. AC measurement load circuit
Table 19. Capacitance(1)
1. Sampled only, not 100% tested.
Symbol Parameter Test condition Min Max Unit
CIN Input capacitance VIN = 0 V 6 8 pF
COUT Output capacitance VOUT = 0 V 8 12 pF
AI12842
VDDQ
CL
CL includes JIG capacitance
22kΩ
DEVICE
UNDER
TEST
0.1µF
VDD
0.1µF
VDDQ
22kΩ
DC and AC parameters M58LT256JST, M58LT256JSB
56/108
Table 20. DC characteristics - currents
Symbol Parameter Test condition Typ Max Unit
ILI Input leakage current 0 V ≤ VIN ≤ VDDQ ±1 µA
ILO Output leakage current 0 V ≤ VOUT ≤ VDDQ ±1 µA
IDD1
Supply current
asynchronous Read (f=5 MHz) E = VIL, G = VIH 13 15 mA
Supply current
synchronous read (f=52 MHz)
4 word 16 19 mA
8 word 18 20 mA
16 word 22 25 mA
Continuous 23 27 mA
IDD2 Supply current (reset) RP = VSS ± 0.2 V 50 110 µA
IDD3 Supply current (standby) E = VDD ± 0.2 V
K = VSS
50 110 µA
IDD4
Supply current (automatic
standby) E = VIL, G = VIH 50 110 µA
IDD5 (1)
1. Sampled only, not 100% tested.
Supply current (program) VPP = VPPH 35 50 mA
VPP = VDD 35 50 mA
Supply current (erase) VPP = VPPH 35 50 mA
VPP = VDD 35 50 mA
IDD6 (1),
(2)
2. VDD dual operation current is the sum of read and program or erase currents.
Supply current
(dual operations)
Program/erase in one bank,
asynchronous read in another
bank
48 65 mA
Program/erase in one bank,
synchronous read (continuous
f=52 MHz) in another bank
58 77 mA
IDD7(1) Supply current program/ erase
suspended (standby)
E = VDD ± 0.2 V
K = VSS
50 110 µA
IPP1(1)
VPP supply current (program) VPP = VPPH 822mA
VPP = VDD 0.2 5 µA
VPP supply current (erase) VPP = VPPH 822mA
VPP = VDD 0.2 5 µA
IPP2 VPP supply current (read) VPP ≤ VDD 0.2 5 µA
IPP3(1) VPP supply current (standby) VPP ≤ VDD 0.2 5 µA
M58LT256JST, M58LT256JSB DC and AC parameters
57/108
Table 21. DC characteristics - voltages
Symbol Parameter Test condition Min Typ Max Unit
VIL Input Low voltage 0 0.4 V
VIH Input High voltage VDDQ –0.4 VDDQ + 0.4 V
VOL Output Low voltage IOL = 100 µA 0.1 V
VOH Output High voltage IOH = –100 µA VDDQ –0.1 V
VPP1 VPP program voltage-logic Program, erase 2.7 3.3 3.6 V
VPPH VPP program voltage factory Program, erase 8.5 9.0 9.5 V
VPPLK Program or erase lockout 0.4 V
VLKO VDD lock voltage 1 V
DC and AC parameters M58LT256JST, M58LT256JSB
58/108
Figure 9. Asynchronous random access read AC waveforms
AI08906b
tAVAV
tELQX
tEHQX
tGLQV
tGLQX
tGHQX
DQ0-DQ15
E
G
tELQV
tEHQZ
tGHQZ
VALID
A0-A23 VALID VALID
L(2)
tELLH
tLLQV
tLLLH
tAVLH tLHAX tAXQX
WAIT(1)
tELTV
tEHTZ
Hi-Z
Hi-Z
tAVQV
tGLTV
tGHTZ
Notes: 1. Write Enable, W, is High, WAIT is active Low.
2. Latch Enable, L, can be kept Low (also at board level) when the Latch Enable function is not required or supported.
M58LT256JST, M58LT256JSB DC and AC parameters
59/108
Figure 10. Asynchronous page read AC waveforms
AI08907b
A3-A23
E
G
A0-A2 VALID ADD.
L
DQ0-DQ15
VALID ADD.VALID ADD.VALID ADDRESS
VALID ADDRESS
VALID
DATA
tLHAX
tAVLH
tLLQV
tAVQV1tGLQX
tLLLH
tELLH
WAIT
tAVAV
tELQV
tELQX
tELTV
tGLQV
(1)
Note 1. WAIT is active Low.
Valid Address Latch
Outputs
Enabled Valid Data Standby
Hi-Z
tGLTV
VALID ADD. VALID ADD.VALID ADD.
VALID ADD.
VALID
DATA
VALID
DATA
VALID
DATA
VALID
DATA
VALID
DATA
VALID
DATA
VALID
DATA
DC and AC parameters M58LT256JST, M58LT256JSB
60/108
Table 22. Asynchronous read AC characteristics
Symbol Alt Parameter
M58LT256JST/B
Unit
85
Read timings
tAVAV tRC Address Valid to Next Address Valid Min 85 ns
tAVQV tACC Address Valid to Output Valid (Random) Max 85 ns
tAVQV1 tPAGE Address Valid to Output Valid (Page) Max 25 ns
tAXQX(1)
1. Sampled only, not 100% tested.
tOH Address Transition to Output Transition Min 0 ns
tELTV Chip Enable Low to Wait Valid Max 25 ns
tELQV(2)
2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV.
tCE Chip Enable Low to Output Valid Max 85 ns
tELQX(1) tLZ Chip Enable Low to Output Transition Min 0 ns
tEHTZ Chip Enable High to Wait Hi-Z Max 17 ns
tEHQX(1) tOH Chip Enable High to Output Transition Min 0 ns
tEHQZ(1) tHZ Chip Enable High to Output Hi-Z Max 17 ns
tGLQV(2) tOE Output Enable Low to Output Valid Max 25 ns
tGLQX(1) tOLZ Output Enable Low to Output Transition Min 0 ns
tGLTV Output Enable Low to Wait Valid Max 17 ns
tGHQX(1) tOH Output Enable High to Output Transition Min 0 ns
tGHQZ(1) tDF Output Enable High to Output Hi-Z Max 17 ns
tGHTZ Output Enable High to Wait Hi-Z Max 17 ns
Latch timings
tAVLH tAVADVH Address Valid to Latch Enable High Min 10 ns
tELLH tELADVH Chip Enable Low to Latch Enable High Min 10 ns
tLHAX tADVHAX Latch Enable High to Address Transition Min 9 ns
tLLLH tADVLADVH Latch Enable Pulse Width Min 10 ns
tLLQV tADVLQV
Latch Enable Low to Output Valid
(Random) Max 85 ns
M58LT256JST, M58LT256JSB DC and AC parameters
61/108
Figure 11. Synchronous burst read AC waveforms
AI13723
DQ0-DQ15
E
G
A0-A23
L
WAIT
K
(4)
VALID VALID
VALID ADDRESS
tLLLH
tAVLH
tGLQX
tAVKH
tLLKH
tELKH tKHAX
tKHQXtKHQV
NOT VALID VALID
Note 1
Note 2 Note 2
tKHTX tKHTV
tEHQX
tEHQZ
tGHQX
tGHQZ
tKHTX
Hi-Z
VALID
Note 2
tKHTV tEHTZ
Address
Latch X Latency Valid Data Flow Boundary
Crossing
Valid
Data Standby
Note 1. The number of clock cycles to be inserted depends on the X latency set in the Burst Configuration Register.
2. The WAIT signal can be configured to be active during wait state or one cycle before. WAIT signal is active Low.
3. Address latched and data output on the rising clock edge.
4. Either the rising or the falling edge of the clock signal, K, can be configured as the active edge. Here, the active edge of K is the rising one.
tEHEL
tKHQV tKHQX
tKHQV
tKHQX
Hi-Z
tGLTV
DC and AC parameters M58LT256JST, M58LT256JSB
62/108
Figure 12. Single synchronous read AC waveforms
1. The WAIT signal is configured to be active during wait state. WAIT signal is active Low.
2. Address latched and data output on the rising clock edge. Either the rising or the falling edge of the clock
signal, K, can be configured as the active edge. Here, the active edge is the rising one.
Ai13400
E
G
A0-A23
L
WAIT(1,2)
K(2)
VALID ADDRESS
tGLQV
tAVKH
tLLKH
tELKH
Hi-Z
tELQX
tKHQV
tGLQX
tKHTV
DQ0-DQ15 VALID
Hi-Z
tELQV
tGLTV
tGHTZ
M58LT256JST, M58LT256JSB DC and AC parameters
63/108
Figure 13. Synchronous burst read suspend AC waveforms
AI13724
DQ0-DQ15
E
G
A0-A23
L
WAIT
(2)
K
(4)
VALID VALID
VALID ADDRESS
tLLLH
tAVLH
tGLQV
tAVKH
tLLKH
tELKH tKHAX
VALID VALID
Note 1
tEHQX
tEHQZ
tGHQX
tGHQZ
Hi-Z
tKHQV
tEHTZ
Note 1. The number of clock cycles to be inserted depends on the X latency set in the Configuration Register.
2. The WAIT signal is configured to be active during wait state. WAIT signal is active Low.
3. The CLOCK signal can be held high or low
4. Address latched and data output on the rising clock edge. Either the rising or the falling edge of the clock signal, K, can be configured as the active edge.
Here, the active edge is the rising one.
tGLQX
tEHEL
tGHQZ tGLQV
Note 3
Hi-Z
tGLTV tGHTZ tGLTV
DC and AC parameters M58LT256JST, M58LT256JSB
64/108
Figure 14. Clock input AC waveform
Table 23. Synchronous read AC characteristics(1) (2)
1. Sampled only, not 100% tested.
2. For other timings please refer to Table 22: Asynchronous read AC characteristics.
Symbol Alt Parameter
M58LT256JST/B
Unit
85
Synchronous Read timings
tAVKH tAVCLKH Address Valid to Clock High Min 9 ns
tELKH tELCLKH Chip Enable Low to Clock High Min 9 ns
tEHEL
Chip Enable Pulse Width
(subsequent synchronous reads) Min 20 ns
tEHTZ Chip Enable High to Wait Hi-Z Max 17 ns
tKHAX tCLKHAX Clock High to Address Transition Min 10 ns
tKHQV
tKHTV
tCLKHQV
Clock High to Output Valid
Clock High to WAIT Valid Max 17 ns
tKHQX
tKHTX
tCLKHQX
Clock High to Output Transition
Clock High to WAIT Transition Min 3 ns
tLLKH tADVLCLKH Latch Enable Low to Clock High Min 9 ns
Clock specifications
tKHKH tCLK Clock Period (f=52 MHz) Min 19 ns
tKHKL
tKLKH
Clock High to Clock Low
Clock Low to Clock High Min 6 ns
tf
tr
Clock Fall or Rise Time Max 2 ns
AI06981
tKHKH
tf tr
tKHKL
tKLKH
M58LT256JST, M58LT256JSB DC and AC parameters
65/108
Figure 15. Write AC waveforms, Write Enable controlled
E
G
W
DQ0-DQ15 COMMAND CMD or DATA STATUS REGISTER
VPP
VALID ADDRESSA0-A23
tAVAV
tQVVPL
tAVWH tWHAX
PROGRAM OR ERASE
tELWL tWHEH
tWHDX
tDVWH
tWLWH
tWHWL
tVPHWH
SET-UP COMMAND CONFIRM COMMAND
OR DATA INPUT
STATUS REGISTER
READ
1st POLLING
tELQV
Ai13401
tWHGL
tWHEL
BANK ADDRESS VALID ADDRESS
L
tAVLH
tLLLH
tELLH
tLHAX
tGHWL
tWHVPL
tELKV
K
tWHLL
tWHAV
DC and AC parameters M58LT256JST, M58LT256JSB
66/108
Table 24. Write AC characteristics, Write Enable controlled(1)
1. Sampled only, not 100% tested.
Symbol Alt Parameter
M58LT256JST/B Unit
85
Write Enable Controlled timings
tAVAV tWC Address Valid to Next Address Valid Min 85 ns
tAVLH Address Valid to Latch Enable High Min 10 ns
tAVWH(3) Address Valid to Write Enable High Min 50 ns
tDVWH tDS Data Valid to Write Enable High Min 50 ns
tELLH Chip Enable Low to Latch Enable High Min 10 ns
tELWL tCS Chip Enable Low to Write Enable Low Min 0 ns
tELQV Chip Enable Low to Output Valid Min 85 ns
tELKV Chip Enable Low to Clock Valid Min 9 ns
tGHWL Output Enable High to Write Enable Low Min 17 ns
tLHAX Latch Enable High to Address Transition Min 9 ns
tLLLH Latch Enable Pulse Width Min 10 ns
tWHAV(2)
2. Meaningful only if L is always kept Low.
Write Enable High to Address Valid Min 0 ns
tWHAX(2) tAH Write Enable High to Address Transition Min 0 ns
tWHDX tDH Write Enable High to Input Transition Min 0 ns
tWHEH tCH Write Enable High to Chip Enable High Min 0 ns
tWHEL(3)
3. tWHEL and tWHLL have this value when reading in the targeted bank or when reading following a Set
Configuration Register command. System designers should take this into account and may insert a
software No-Op instruction to delay the first read in the same bank after issuing any command and to
delay the first read to any address after issuing a Set Configuration Register command. If the first read
after the command is a Read Array operation in a different bank and no changes to the Configuration
Register have been issued, tWHEL and tWHLL are 0 ns.
Write Enable High to Chip Enable Low Min 25 ns
tWHGL Write Enable High to Output Enable Low Min 0 ns
tWHLL(3) Write Enable High to Latch Enable Low Min 25 ns
tWHWL tWPH Write Enable High to Write Enable Low Min 25 ns
tWLWH tWP Write Enable Low to Write Enable High Min 50 ns
Protection timings
tQVVPL Output (Status Register) Valid to VPP Low Min 0 ns
tVPHWH tVPS VPP High to Write Enable High Min 200 ns
tWHVPL Write Enable High to VPP Low Min 200 ns
M58LT256JST, M58LT256JSB DC and AC parameters
67/108
Figure 16. Write AC waveforms, Chip Enable controlled
W
G
E
DQ0-DQ15 COMMAND CMD or DATA STATUS REGISTER
VPP
VALID ADDRESSA0-A23
tAVAV
tQVVPL
tAVEH tEHAX
PROGRAM OR ERASE
tWLEL
tEHWH
tEHDX
tDVEH
tELEH
tEHEL
tVPHEH
SET-UP COMMAND CONFIRM COMMAND
OR DATA INPUT
STATUS REGISTER
READ
1st POLLING
tELQV
Ai13402
tEHGL
tWHEL
BANK ADDRESS VALID ADDRESS
L
tAVLH
tLLLH
tLHAX
tGHEL
tEHVPL
tELKV
K
tELLH
DC and AC parameters M58LT256JST, M58LT256JSB
68/108
Table 25. Write AC characteristics, Chip Enable controlled(1)
1. Sampled only, not 100% tested.
Symbol Alt Parameter
M58LT256JST/B
Unit
85
Chip Enable Controlled timings
tAVAV tWC Address Valid to Next Address Valid Min 85 ns
tAVEH Address Valid to Chip Enable High Min 50 ns
tAVLH Address Valid to Latch Enable High Min 10 ns
tDVEH tDS Data Valid to Chip Enable High Min 50 ns
tEHAX tAH Chip Enable High to Address Transition Min 0 ns
tEHDX tDH Chip Enable High to Input Transition Min 0 ns
tEHEL tCPH Chip Enable High to Chip Enable Low Min 25 ns
tEHGL Chip Enable High to Output Enable Low Min 0 ns
tEHWH tCH Chip Enable High to Write Enable High Min 0 ns
tELKV Chip Enable Low to Clock Valid Min 9 ns
tELEH tCP Chip Enable Low to Chip Enable High Min 50 ns
tELLH Chip Enable Low to Latch Enable High Min 10 ns
tELQV Chip Enable Low to Output Valid Min 85 ns
tGHEL Output Enable High to Chip Enable Low Min 17 ns
tLHAX Latch Enable High to Address Transition Min 9 ns
tLLLH Latch Enable Pulse Width Min 10 ns
tWHEL(2)
2. tWHEL has this value when reading in the targeted bank or when reading following a Set Configuration
Register command. System designers should take this into account and may insert a software No-Op
instruction to delay the first read in the same bank after issuing any command and to delay the first read to
any address after issuing a Set Configuration Register command. If the first read after the command is a
Read Array operation in a different bank and no changes to the Configuration Register have been issued,
tWHEL is 0 ns.
Write Enable High to Chip Enable Low Min 25 ns
tWLEL tCS Write Enable Low to Chip Enable Low Min 0 ns
Protection timings
tEHVPL Chip Enable High to VPP Low Min 200 ns
tQVVPL Output (Status Register) Valid to VPP Low Min 0 ns
tVPHEH tVPS VPP High to Chip Enable High Min 200 ns
M58LT256JST, M58LT256JSB DC and AC parameters
69/108
Figure 17. Reset and power-up AC waveforms
AI06976
W,
RP
E, G,
VDD, VDDQ
tVDHPH tPLPH
Power-up Reset
tPLWL
tPLEL
tPLGL
tPLLL
L
tPHWL
tPHEL
tPHGL
tPHLL
Table 26. Reset and power-up AC characteristics
Symbol Parameter Test condition 85 Unit
tPLWL
tPLEL
tPLGL
tPLLL
Reset Low to
Write Enable Low,
Chip Enable Low,
Output Enable Low,
Latch Enable Low
During program Min 25 µs
During erase Min 25 µs
Read Min 80 ns
Other conditions Min 200 µs
tPHWL
tPHEL
tPHGL
tPHLL
Reset High to
Write Enable Low,
Chip Enable Low,
Output Enable Low,
Latch Enable Low
Min 30 ns
tPLPH(1),(2) RP Pulse Width Min 50 ns
tVDHPH(3) Supply voltages High to Reset
High Min 150 µs
1. The device Reset is possible but not guaranteed if tPLPH < 50 ns.
2. Sampled only, not 100% tested.
3. It is important to assert RPr to allow proper CPU initialization during power-up or reset.
Package mechanical M58LT256JST, M58LT256JSB
70/108
13 Package mechanical
To meet environmental requirements, Numonyx offers these devices in ECOPACK®
packages, which have a lead-free second-level interconnect. The category of second-level
interconnect is marked on the package and on the inner box label, in compliance with
JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
Figure 18. TBGA64 10 × 13 mm - 8 x 8 active ball array, 1 mm pitch, bottom view
package outline
1. Drawing is not to scale.
E1E
D1
D
eb
SD
SE
A2
A1
A
BGA-Z23
ddd
FD
FE
BALL "A1"
M58LT256JST, M58LT256JSB Package mechanical
71/108
Table 27. TBGA64 10 × 13 mm - 8 x 8 active ball array, 1 mm pitch, package
mechanical data
Symbol
Millimeters Inches
Typ Min Max Typ Min Max
A 1.200 0.0472
A1 0.300 0.200 0.350 0.0118 0.0079 0.0138
A2 0.800 0.0315
b 0.350 0.500 0.0138 0.0197
D 10.000 9.900 10.100 0.3937 0.3898 0.3976
D1 7.000 – – 0.2756 – –
ddd 0.100 0.0039
e 1.000 – – 0.0394 – –
E 13.000 12.900 13.100 0.5118 0.5079 0.5157
E1 7.000 – – 0.2756 – –
FD 1.500 – – 0.0591 – –
FE 3.000 – – 0.1181 – –
SD 0.500 – – 0.0197 – –
SE 0.500 – – 0.0197 – –
Part numbering M58LT256JST, M58LT256JSB
72/108
14 Part numbering
Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact the Numonyx sales office nearest to you.
Table 28. Ordering information scheme
Example: M58LT256JST 8 ZA 6 E
Device type
M58
Architecture
L = multilevel, multiple bank, burst mode
Operating voltage
T = VDD = 1.7 V to 2.0 V, VDDQ = 2.7 V to 3.6 V
Density
256 = 256 Mbit (× 16)
Technology
J = 90 nm technology, multilevel design
Security
S = Secure
Parameter location
T = top boot
B = bottom boot
Speed
8 = 85 ns
Package
ZA = TBGA64, 10 × 13 mm, 1 mm pitch
Temperature range
6 = –40 to 85 °C
Packing option
E = ECOPACK® package, standard packing
F = ECOPACK® package, tape and reel packing
T = tape and reel packing
Blank = standard packing
M58LT256JST, M58LT256JSB Block address tables
73/108
Appendix A Block address tables
The following set of equations can be used to calculate a complete set of block addresses
using the information contained in Tables 29 to 34.
To calculate the block base address from the block number:
First it is necessary to calculate the bank number and the block number offset. This can be
achieved using the following formulas:
Bank_Number = (Block_Number − 3) / 16
Block_Number_Offset = Block_Number − 3 − (Bank_Number x 16)
If Bank_Number = 0, the block base address can be directly read from Tables 29 and 32
(parameter bank block addresses) in the block number offset row. Otherwise:
Block_Base_Address = Bank_Base_Address + Block_Base_Address_Offset
To calculate the bank number and the block number from the block base address:
If the address is in the range of the parameter bank, the bank number is 0 and the block
number can be directly read from tables 29 and 32 (parameter bank block addresses), in the
row that corresponds to the address given. Otherwise, the block number can be calculated
using the formulas below:
For the top configuration (M58LT256JST):
Block_Number = ((NOT address) / 216) + 3
For the bottom configuration (M58LT256JSB):
Block_Number = (address / 216) + 3
For both configurations the bank number and the block number offset can be calculated
using the following formulas:
Bank_Number = (Block_Number − 3) / 16
Block_Number_Offset = Block_Number − 3 − (Bank_Number x 16)
Block address tables M58LT256JST, M58LT256JSB
74/108
Table 29. M58LT256JST - parameter bank block addresses
Block number Size (KWords) Address range
0 16 FFC000-FFFFFF
1 16 FF8000-FFBFFF
2 16 FF4000-FF7FFF
3 16 FF0000-FF3FFF
4 64 FE0000-FEFFFF
5 64 FD0000-FDFFFF
6 64 FC0000-FCFFFF
7 64 FB0000-FBFFFF
8 64 FA0000-FAFFFF
9 64 F90000-F9FFFF
10 64 F80000-F8FFFF
11 64 F70000-F7FFFF
12 64 F60000-F6FFFF
13 64 F50000-F5FFFF
14 64 F40000-F4FFFF
15 64 F30000-F3FFFF
16 64 F20000-F2FFFF
17 64 F10000-F1FFFF
18 64 F00000-F0FFFF
M58LT256JST, M58LT256JSB Block address tables
75/108
1. There are two bank regions: bank region 1 contains all the banks that are made up of main blocks only;
bank region 2 contains the banks that are made up of the parameter and main blocks (Parameter Bank).
Table 30. M58LT256JST - main bank base addresses
Bank number Block numbers Bank base address
1 19-34 E00000
2 35-50 D00000
3 51-66 C00000
4 67-82 B00000
5 83-98 A00000
6 99-114 900000
7 115-130 800000
8 131-146 700000
9 147-162 600000
10 163-178 500000
11 179-194 400000
12 195-210 300000
13 211-226 200000
14 227-242 100000
15 243-258 000000
Table 31. M58LT256JST - block addresses in main banks
Block number offset Block base address offset
0 0F0000
1 0E0000
2 0D0000
3 0C0000
4 0B0000
5 0A0000
6 090000
7 080000
8 070000
9 060000
10 050000
11 040000
12 030000
13 020000
14 010000
15 000000
Block address tables M58LT256JST, M58LT256JSB
76/108
Table 32. M58LT256JSB - parameter bank block addresses
Block number Size (KWords) Address range
18 64 0F0000-0FFFFF
17 64 0E0000-0EFFFF
16 64 0D0000-0DFFFF
15 64 0C0000-0CFFFF
14 64 0B0000-0BFFFF
13 64 0A0000-0AFFFF
12 64 090000-09FFFF
11 64 080000-08FFFF
10 64 070000-07FFFF
9 64 060000-06FFFF
8 64 050000-05FFFF
7 64 040000-04FFFF
6 64 030000-03FFFF
5 64 020000-02FFFF
4 64 010000-01FFFF
3 16 00C000-00FFFF
2 16 008000-00BFFF
1 16 004000-007FFF
0 16 000000-003FFF
M58LT256JST, M58LT256JSB Block address tables
77/108
1. There are two bank regions: bank region 2 contains all the banks that are made up of main blocks only;
bank region 1 contains the banks that are made up of the parameter and main blocks (parameter bank).
Table 33. M58LT256JSB - main bank base addresses
Bank number Block numbers Bank base address
15 243-258 F00000
14 227-242 E00000
13 211-226 D00000
12 195-210 C00000
11 179-194 B00000
10 163-178 A00000
9 147-162 900000
8 131-146 800000
7 115-130 700000
6 99-114 600000
5 83-98 500000
4 67-82 400000
3 51-66 300000
2 35-50 200000
1 19-34 100000
Table 34. M58LT256JSB - block addresses in main banks
Block number offset Block base address offset
15 0F0000
14 0E0000
13 0D0000
12 0C0000
11 0B0000
10 0A0000
9 090000
8 080000
7 070000
6 060000
5 050000
4 040000
3 030000
2 020000
1 010000
0 000000
Common Flash interface M58LT256JST, M58LT256JSB
78/108
Appendix B Common Flash interface
The CFI (common Flash interface) is a JEDEC approved, standardized data structure that
can be read from the Flash memory device. It allows a system software to query the device
to determine various electrical and timing parameters, density information, and functions
supported by the memory. The system can interface easily with the device, enabling the
software to upgrade itself when necessary.
When the Read CFI Query command is issued the device enters CFI query mode and the
data structure is read from the memory. Tables 35, 36, 37, 38, 39, 40, 41, 42, 43 and 44
show the addresses used to retrieve the data. The query data is always presented on the
lowest order data outputs (DQ0-DQ7), the other outputs (DQ8-DQ15) are set to 0.
The CFI data structure also contains a security area where a 64-bit unique security number
is written (see Figure 4: Protection Register memory map). This area can only be accessed
in read mode by the final user. It is impossible to change the security number after it has
been written by Numonyx. Issue a Read Array command to return to read mode.
1. The Flash memory display the CFI data structure when CFI Query command is issued. In this table are
listed the main sub-sections detailed in Tables 36, 37, 38 and 39. Query data is always presented on the
lowest order data outputs.
Table 35. Query structure overview
Offset Sub-section name Description
000h Reserved Reserved for algorithm-specific information
010h CFI query identification string Command set ID and algorithm data offset
01Bh System interface information Device timing and voltage information
027h Device geometry definition Flash device layout
PPrimary algorithm-specific extended
query table
Additional information specific to the primary
algorithm (optional)
AAlternate algorithm-specific extended
query table
Additional information specific to the alternate
algorithm (optional)
080h Security code area
Lock Protection Register
Unique device number and
User programmable OTP
M58LT256JST, M58LT256JSB Common Flash interface
79/108
Table 36. CFI query identification string
Offset Sub-section name Description Value
000h 0020h Manufacturer code Numonyx
001h 885Eh
885Fh Device code M58LT256JST
M58LT256JSB
Top
Bottom
002h-
00Fh reserved Reserved
010h 0051h
Query unique ASCII String "QRY"
"Q"
011h 0052h "R"
012h 0059h "Y"
013h 0001h Primary algorithm command set and control interface
ID code 16-bit ID code defining a specific algorithm
014h 0000h
015h offset = P = 000Ah Address for primary algorithm extended query table
(see Ta bl e 3 9 )p = 10Ah
016h 0001h
017h 0000h Alternate vendor command set and control interface ID
code second vendor - specified algorithm supported NA
018h 0000h
019h value = A = 0000h Address for alternate algorithm extended query table NA
01Ah 0000h
Common Flash interface M58LT256JST, M58LT256JSB
80/108
Table 37. CFI query system interface information
Offset Data Description Value
01Bh 0017h
VDD logic supply minimum program/erase or write voltage
bit 7 to 4 BCD value in volts
bit 3 to 0 BCD value in 100 millivolts
1.7 V
01Ch 0020h
VDD logic supply maximum program/erase or write voltage
bit 7 to 4 BCD value in volts
bit 3 to 0 BCD value in 100 millivolts
2 V
01Dh 0085h
VPP [programming] supply minimum program/erase voltage
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 millivolts
8.5 V
01Eh 0095h
VPP [programming] supply maximum program/erase voltage
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 millivolts
9.5 V
01Fh 0008h Typical time-out per single byte/word program = 2n µs 256 µs
020h 0009h Typical time-out for Buffer Program = 2n µs 512 µs
021h 000Ah Typical time-out per individual block erase = 2n ms 1 s
022h 0000h Typical time-out for full chip erase = 2n ms NA
023h 0001h Maximum time-out for word program = 2n times typical 512 µs
024h 0001h Maximum time-out for Buffer Program = 2n times typical 1024 µs
025h 0002h Maximum time-out per individual block erase = 2n times typical 4 s
026h 0000h Maximum time-out for chip erase = 2n times typical NA
M58LT256JST, M58LT256JSB Common Flash interface
81/108
Table 38. Device geometry definition
Offset Data Description Value
027h 0019h Device size = 2n in number of bytes 32 Mbytes
028h
029h
0001h
0000h Flash device Interface code description x 16
Async.
02Ah
02Bh
0006h
0000h Maximum number of bytes in multi-byte program or page = 2n 64 Bytes
02Ch 0002h
Number of identical sized erase block regions within the
device
bit 7 to 0 = x = number of erase block regions
2
M58LT256JST
02Dh
02Eh
00FEh
0000h
Erase block region 1 information
Number of identical-size erase blocks = 00FEh+1 255
02Fh
030h
0000h
0002h
Erase block region 1 information
Block size in region 1 = 0200h * 256 Byte 128 Kbytes
031h
032h
0003h
0000h
Erase block region 2 information
Number of identical-size erase blocks = 0003h+1 4
033h
034h
0080h
0000h
Erase block region 2 information
Block size in region 2 = 0080h * 256 byte 32 Kbytes
035h
038h Reserved Reserved for future erase block region information NA
M58LT256JSB
02Dh
02Eh
0003h
0000h
Erase block region 1 Information
Number of identical-size erase block = 0003h+1 4
02Fh
030h
0080h
0000h
Erase block region 1 information
Block size in region 1 = 0080h * 256 bytes 32 Kbytes
031h
032h
00FEh
0000h
Erase block region 2 information
Number of identical-size erase block = 00FEh+1 255
033h
034h
0000h
0002h
Erase block region 2 information
Block size in region 2 = 0200h * 256 bytes 128 Kbytes
035h
038h Reserved Reserved for future erase block region information NA
Common Flash interface M58LT256JST, M58LT256JSB
82/108
Table 39. Primary algorithm-specific extended query table
Offset Data Description Value
(P)h = 10Ah 0050h
Primary algorithm extended query table unique ASCII string “PRI”
"P"
0052h "R"
0049h "I"
(P+3)h =10Dh 0031h Major version number, ASCII "1"
(P+4)h = 10Eh 0033h Minor version number, ASCII "3"
(P+5)h = 10Fh 00E6h Extended query table contents for primary algorithm. Address
(P+5)h contains less significant byte.
bit 0 Chip Erase supported(1 = Yes, 0 = No)
bit 1 Erase Suspend supported(1 = Yes, 0 = No)
bit 2 Program Suspend supported(1 = Yes, 0 = No)
bit 3 Legacy Protect/Unprotect supported(1 = Yes, 0 = No)
bit 4 Queued Erase supported(1 = Yes, 0 = No)
bit 5 Instant individual block locking supported(1 = Yes, 0 = No)
bit 6 Protection bits supported(1 = Yes, 0 = No)
bit 7 Page mode read supported(1 = Yes, 0 = No)
bit 8 Synchronous read supported(1 = Yes, 0 = No)
bit 9 Simultaneous operation supported(1 = Yes, 0 = No)
bit 10 to 31 Reserved; undefined bits are ‘0’. If bit 31 is ’1’ then
another 31 bit field of optional features follows at the end of the
bit-30 field.
No
Ye s
Ye s
No
No
Ye s
Ye s
Ye s
Ye s
Ye s
0003h
(P+7)h = 111h 0000h
(P+8)h = 112h 0000h
(P+9)h = 113h 0001h
Supported Functions after Suspend
Read Array, Read Status Register and CFI Query
bit 0 Program supported after Erase Suspend (1 = Yes, 0 = No)
bit 7 to 1 Reserved; undefined bits are ‘0’
Ye s
(P+A)h = 114h 0001h Block Protect Status
Defines which bits in the Block Status Register section of the
Query are implemented.
bit 0 Block protect Status Register Protect/Unprotect
bit active (1 = Yes, 0 = No)
bit 1 Block Protect Status Register Lock-Down bit active (1 =
Ye s , 0 = N o )
bit 15 to 2 Reserved for future use; undefined bits are ‘0’
Ye s
No
(P+B)h = 115h 0000h
(P+C)h = 116h 0018h
VDD Logic Supply Optimum Program/Erase voltage (highest
performance)
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV
1.8 V
(P+D)h = 117h 0090h
VPP Supply Optimum Program/Erase voltage
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV
9 V
M58LT256JST, M58LT256JSB Common Flash interface
83/108
Table 40. Protection register information
Offset Data Description Value
(P+E)h = 118h 0002h Number of protection register fields in JEDEC ID space.
0000h indicates that 256 fields are available. 2
(P+F)h = 119h 0080h Protection Field 1: Protection Description
Bits 0-7 Lower byte of protection register address
Bits 8-15 Upper byte of protection register address
Bits 16-23 2n bytes in factory pre-programmed region
Bits 24-31 2n bytes in user programmable region
80h
(P+10)h = 11Ah 0000h 00h
(P+ 11)h = 11Bh 0003h 8 Bytes
(P+12)h = 11Ch 0003h 8 Bytes
(P+13)h = 11Dh 0089h
Protection Register 2: Protection Description
Bits 0-31 protection register address
Bits 32-39 n number of factory programmed regions (lower
byte)
Bits 40-47 n number of factory programmed regions (upper
byte)
Bits 48-55 2n bytes in factory programmable region
Bits 56-63 n number of user programmable regions (lower
byte)
Bits 64-71 n number of user programmable regions (upper
byte)
Bits 72-79 2n bytes in user programmable region
89h
(P+14)h = 11Eh 0000h 00h
(P+15)h = 11Fh 0000h 00h
(P+16)h = 120h 0000h 00h
(P+17)h = 121h 0000h 0
(P+18)h = 122h 0000h 0
(P+19)h = 123h 0000h 0
(P+1A)h = 124h 0010h 16
(P+1B)h = 125h 0000h 0
(P+1C)h = 126h 0004h 16
Common Flash interface M58LT256JST, M58LT256JSB
84/108
Table 41. Burst read information
Offset Data Description Value
(P+1D)h = 127h 0004h
Page-mode read capability
bits 0-7 n’ such that 2n HEX value represents the number of
read-page bytes. See offset 0028h for device word width to
determine page-mode data output width.
16 bytes
(P+1E)h = 128h 0004h Number of synchronous mode read configuration fields that
follow. 4
(P+1F)h = 129h 0001h
Synchronous mode read capability configuration 1
bit 3-7 Reserved
bit 0-2 n’ such that 2n+1 HEX value represents the
maximum number of continuous synchronous reads when
the device is configured for its maximum word width. A
value of 07h indicates that the device is capable of
continuous linear bursts that will output data until the
internal burst counter reaches the end of the device’s
burstable address space. This field’s 3-bit value can be
written directly to the read configuration register bit 0-2 if
the device is configured for its maximum word width. See
offset 0028h for word width to determine the burst data
output width.
4
(P+20)h = 12Ah 0002h Synchronous mode read capability configuration 2 8
(P-21)h = 12Bh
(P+22)h = 12Ch
0003h
0007h
Synchronous mode read capability configuration 3 16
Synchronous mode read capability configuration 4 Cont.
M58LT256JST, M58LT256JSB Common Flash interface
85/108
1. The variable P is a pointer which is defined at CFI offset 015h.
2. Bank regions. There are two bank regions, see Tables 29 to 34.
Table 42. Bank and erase block region information
M58LT256JST M58LT256JSB
Description
Offset Data Offset Data
(P+23)h = 12Dh 02h (P+23)h = 12Dh 02h Number of bank regions within the device
Table 43. Bank and erase block region 1 information
M58LT256JST M58LT256JSB
Description
Offset Data Offset Data
(P+24)h = 12Eh 0Fh (P+24)h = 12Eh 01h Number of identical banks within bank region 1
(P+25)h = 12Fh 00h (P+25)h = 12Fh 00h
(P+26)h = 130h 11h (P+26)h = 130h 11h
Number of program or erase operations allowed in
bank region 1:
Bits 0-3: number of simultaneous program
operations
Bits 4-7: number of simultaneous erase
operations
(P+27)h = 131h 00h (P+27)h = 131h 00h
Number of program or erase operations allowed in
other banks while a bank in same region is
programming
Bits 0-3: number of simultaneous program
operations
Bits 4-7: number of simultaneous erase
operations
(P+28)h = 132h 00h (P+28)h = 132h 00h
Number of program or erase operations allowed in
other banks while a bank in this region is erasing
Bits 0-3: number of simultaneous program
operations
Bits 4-7: number of simultaneous erase
operations
(P+29)h = 133h 01h (P+29)h = 133h 02h
Types of erase block regions in bank region 1
n = number of erase block regions with contiguous
same-size erase blocks.
Symmetrically blocked banks have one blocking
region(2).
(P+2A)h = 134h 0Fh (P+2A)h = 134h 03h Bank Region 1 Erase Block Type 1 Information
Bits 0-15: n+1 = number of identical-sized erase
blocks
Bits 16-31: n×256 = number of bytes in erase
block region
(P+2B)h = 135h 00h (P+2B)h = 135h 00h
(P+2C)h = 136h 00h (P+2C)h = 136h 80h
(P+2D)h = 137h 02h (P+2D)h = 137h 00h
(P+2E)h = 138h 64h (P+2E)h = 138h 64h Bank region 1 (Erase Block Type 1)
Minimum block erase cycles × 1000
(P+2F)h = 139h 00h (P+2F)h = 139h 00h
Common Flash interface M58LT256JST, M58LT256JSB
86/108
1. The variable P is a pointer which is defined at CFI offset 015h.
2. Bank regions. There are two bank regions, see Tables 29 to 34.
3. Although the device supports Page Read mode, this is not described in the datasheet as its use is not
advantageous in a multiplexed device.
(P+30)h = 13Ah 02h (P+30)h = 13Ah 02h
Bank region 1 (Erase Block type 1): bits per cell,
internal ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
Bits 5-7: reserved
(P+31)h = 13Bh 03h (P+31)h = 13Bh 03h
Bank region 1 (Erase Block type 1): page mode
and synchronous mode capabilities
Bit 0: page-mode reads permitted
Bit 1: synchronous reads permitted
Bit 2: synchronous writes permitted
Bits 3-7: reserved
(P+32)h = 13Ch 0Eh Bank region 1 Erase Block type 2 information
Bits 0-15: n+1 = number of identical-sized
erase blocks
Bits 16-31: n × 256 = number of bytes in erase
block region
(P+33)h = 13Dh 00h
(P+34)h = 13Eh 00h
(P+35)h = 13Fh 02h
(P+36)h = 140h 64h Bank region 1 (Erase Block type 2)
Minimum block erase cycles × 1000
(P+37)h = 141h 00h
(P+38)h = 142h 02h
Bank regions 1 (Erase Block Type 2): bits per cell,
internal ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
Bits 5-7: reserved
(P+39)h = 143h 03h
Bank region 1 (Erase Block Type 2): page mode
and synchronous mode capabilities
Bit 0: page-mode reads permitted
Bit 1: synchronous reads permitted
Bit 2: synchronous writes permitted
Bits 3-7: reserved
Table 43. Bank and erase block region 1 information (continued)
M58LT256JST M58LT256JSB
Description
Offset Data Offset Data
M58LT256JST, M58LT256JSB Common Flash interface
87/108
Table 44. Bank and erase block region 2 information
M58LT256JST M58LT256JSB
Description
Offset Data Offset Data
(P+32)h = 13Ch 01h (P+3A)h = 144h 0Fh Number of identical banks within bank region 2
(P+33)h = 13Dh 00h (P+3B)h = 145h 00h
(P+34)h = 13Eh 11h (P+3C)h = 146h 11h
Number of program or erase operations allowed in
bank region 2:
Bits 0-3: number of simultaneous program
operations
Bits 4-7: number of simultaneous erase operations
(P+35)h = 13Fh 00h (P+3D)h = 147h 00h
Number of program or erase operations allowed in
other banks while a bank in this region is
programming
Bits 0-3: number of simultaneous program
operations
Bits 4-7: number of simultaneous erase operations
(P+36)h = 140h 00h (P+3E)h = 148h 00h
Number of program or erase operations allowed in
other banks while a bank in this region is erasing
Bits 0-3: number of simultaneous program
operations
Bits 4-7: number of simultaneous erase operations
(P+37)h = 141h 02h (P+3F)h = 149h 01h
Types of erase block regions in bank region 2
n = number of erase block regions with contiguous
same-size erase blocks.
Symmetrically blocked banks have one blocking
region.(2)
(P+38)h = 142h 0Eh (P+40)h = 14Ah 0Fh Bank region 2 Erase Block type 1 information
Bits 0-15: n+1 = number of identical-sized erase
blocks
Bits 16-31: n × 256 = number of bytes in erase
block region
(P+39)h = 143h 00h (P+41)h = 14Bh 00h
(P+3A)h = 144h 00h (P+42)h = 14Ch 00h
(P+3B)h = 145h 02h (P+43)h = 14Dh 02h
(P+3C)h = 146h 64h (P+44)h = 14Eh 64h Bank region 2 (Erase Block type 1)
Minimum block erase cycles × 1000
(P+3D)h = 147h 00h (P+45)h = 14Fh 00h
(P+3E)h = 148h 02h (P+46)h = 150h 02h
Bank region 2 (Erase Block type 1): bits per cell,
internal ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
Bits 5-7: reserved
(P+3F)h = 149h 03h (P+47)h = 151h 03h
Bank region 2 (Erase Block type 1): page mode
and synchronous mode capabilities (defined in
Ta b l e 4 1 )
Bit 0: page-mode reads permitted
Bit 1: synchronous reads permitted
Bit 2: synchronous writes permitted
Bits 3-7: reserved
Common Flash interface M58LT256JST, M58LT256JSB
88/108
1. The variable P is a pointer which is defined at CFI offset 015h.
2. Bank regions. There are two bank regions, see Tables 29 to 34.
3. Although the device supports Page Read mode, this is not described in the datasheet as its use is not
advantageous in a multiplexed device.
(P+40)h = 14Ah 03h Bank region 2 Erase Block type 2 information
Bits 0-15: n+1 = number of identical-sized erase
blocks
Bits 16-31: n × 256 = number of bytes in erase
block region
(P+41)h = 14Bh 00h
(P+42)h = 14Ch 80h
(P+43)h = 14Dh 00h
(P+44)h = 14Eh 64h Bank region 2 (Erase Block type 2)
Minimum block erase cycles × 1000
(P+45)h = 14Fh 00h
(P+46)h = 150h 02h
Bank region 2 (Erase Block Type 2): bits per cell,
internal ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
Bits 5-7: reserved
(P+47)h = 151h 03h
Bank region 2 (Erase Block type 2): page mode
and synchronous mode capabilities (defined in
Ta b l e 4 1 )
Bit 0: page-mode reads permitted
Bit 1: synchronous reads permitted
Bit 2: synchronous writes permitted
Bits 3-7: reserved
(P+48)h = 152h (P+48)h = 152h Feature space definitions
(P+49)h = 153h (P+43)h = 153h Reserved
Table 44. Bank and erase block region 2 information (continued)
M58LT256JST M58LT256JSB
Description
Offset Data Offset Data
M58LT256JST, M58LT256JSB Flowcharts and pseudocodes
89/108
Appendix C Flowcharts and pseudocodes
Figure 19. Program flowchart and pseudocode
1. Status check of SR1 (Protected Block), SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program
operation or after a sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
3. Any address within the bank can equally be used.
Write 40h or 10h (3)
AI06170b
Start
Write Address
& Data
Read Status
Register (3)
YES
NO
SR7 = 1
YES
NO
SR3 = 0
NO
SR4 = 0
VPP Invalid
Error (1, 2)
Program
Error (1, 2)
program_command (addressToProgram, dataToProgram) {:
writeToFlash (addressToProgram, 0x40);
/*writeToFlash (addressToProgram, 0x10);*/
/*see note (3)*/
do {
status_register=readFlash (addressToProgram);
"see note (3)";
/* E or G must be toggled*/
} while (status_register.SR7== 0) ;
if (status_register.SR3==1) /*VPP invalid error */
error_handler ( ) ;
YES
End
YES
NO
SR1 = 0 Program to Protected
Block Error (1, 2)
writeToFlash (addressToProgram, dataToProgram) ;
/*Memory enters read status state after
the Program Command*/
if (status_register.SR4==1) /*program error */
error_handler ( ) ;
if (status_register.SR1==1) /*program to protect block error */
error_handler ( ) ;
}
Flowcharts and pseudocodes M58LT256JST, M58LT256JSB
90/108
Figure 20. Blank check flowchart and pseudocode
1. Any address within the bank can equally be used.
2. If an error is found, the Status Register must be cleared before further Program/Erase operations.
Write Block
Address & BCh
Start
SR7 = 1
Write Block
Address & CBh
Read
Status Register (1)
SR4 = 1
SR5 = 1
SR5 = 0
NO
YES
Command Sequence
Error (2)
YES
Blank Check Error (2)
NO
End
blank_check_command (blockToCheck) {
writeToFlash (blockToCheck, 0xBC);
writeToFlash (blockToCheck, 0xCB);
/* Memory enters read status state after
the Blank Check Command */
do {
status_register = readFlash (blockToCheck);
/* see note (1) */
/* E or G must be toggled */
} while (status_register.SR7==0);
if (status_register.SR4==1) && (status_register.SR5==1)
/* command sequence error */
error_handler () ;
if (status_register.SR5==1)
/* Blank Check error */
error_handler () ;
}
ai10520c
M58LT256JST, M58LT256JSB Flowcharts and pseudocodes
91/108
Figure 21. Buffer program flowchart and pseudocode
1. n + 1 is the number of data being programmed.
2. Next Program data is an element belonging to buffer_Program[].data; Next Program address is an element belonging to
buffer_Program[].address
3. Routine for Error Check by reading SR3, SR4 and SR1.
Buffer Program E8h
Command,
Start Address
AI08913b
Start
Write Buffer Data,
Start Address
YES
X = n
End
NO
Write n
(1)
,
Start Address
X = 0
Write Next Buffer Data,
Next Program Address
X = X + 1
Program
Buffer to Flash
Confirm D0h
Read Status
Register
NO
SR7 = 1
YES
Full Status
Register Check
(3)
(2)
Read Status
Register
NO
SR7 = 1
YES
Buffer_Program_command (Start_Address, n, buffer_Program[] )
/* buffer_Program [] is an array structure used to store the address and
data to be programmed to the Flash memory (the address must be within
the segment Start Address and Start Address+n) */
{
do {writeToFlash (Start_Address, 0xE8) ;
status_register=readFlash (Start_Address);
} while (status_register.SR7==0);
writeToFlash (Start_Address, n);
writeToFlash (buffer_Program[0].address, buffer_Program[0].data);
/*buffer_Program[0].address is the start address*/
x = 0;
while (x<n)
{ writeToFlash (buffer_Program[x+1].address, buffer_Program[x+1].data);
x++;
}
writeToFlash (Start_Address, 0xD0);
do {status_register=readFlash (Start_Address);
} while (status_register.SR7==0);
full_status_register_check();
}
Flowcharts and pseudocodes M58LT256JST, M58LT256JSB
92/108
Figure 22. Program suspend and resume flowchart and pseudocode
1. The Read Status Register command (Write 70h) can be issued just before or just after the Program Resume command.
Write 70h
AI10117b
Read Status
Register
YES
NO
SR7 = 1
YES
NO
SR2 = 1
Write D0h
Read data from
another address
Start
Write B0h
Program Complete
Write FFh
program_suspend_command ( ) {
writeToFlash (any_address, 0xB0) ;
writeToFlash (bank_address, 0x70) ;
/* read status register to check if
program has already completed */
do {
status_register=readFlash (bank_address) ;
/* E or G must be toggled*/
} while (status_register.SR7== 0) ;
if (status_register.SR2==0) /*program completed */
{ writeToFlash (bank_address, 0xFF) ;
read_data ( ) ;
/*The device returns to Read Array
(as if program/erase suspend was not issued).*/
}
else
{ writeToFlash (bank_address, 0xFF) ;
read_data ( ); /*read data from another address*/
writeToFlash (any_address, 0xD0) ;
/*write 0xD0 to resume program*/
writeToFlash (bank_address, 0x70) ;
/*read status register to check if program has completed */
}
}
Write FFh
Program Continues with
Bank in Read Status
Register Mode
Read Data
Write 70h(1)
M58LT256JST, M58LT256JSB Flowcharts and pseudocodes
93/108
Figure 23. Block erase flowchart and pseudocode
1. If an error is found, the Status Register must be cleared before further Program/Erase operations.
2. Any address within the bank can equally be used.
Write 20h (2)
AI10976
Start
Write Block
Address & D0h
Read Status
Register (2)
YES
NO
SR7 = 1
YES
NO
SR3 = 0
YES
SR4, SR5 = 1
VPP Invalid
Error (1)
Command
Sequence Error (1)
NO
NO
SR5 = 0 Erase Error (1)
End
YES
NO
SR1 = 0 Erase to Protected
Block Error (1)
YES
erase_command ( blockToErase ) {
writeToFlash (blockToErase, 0x20) ;
/*see note (2) */
writeToFlash (blockToErase, 0xD0) ;
/* Memory enters read status state after
the Erase Command */
} while (status_register.SR7== 0) ;
do {
status_register=readFlash (blockToErase) ;
/* see note (2) */
/* E or G must be toggled*/
if (status_register.SR3==1) /*VPP invalid error */
error_handler ( ) ;
if ( (status_register.SR4==1) && (status_register.SR5==1) )
/* command sequence error */
error_handler ( ) ;
if (status_register.SR1==1) /*program to protect block error */
error_handler ( ) ;
if ( (status_register.SR5==1) )
/* erase error */
error_handler ( ) ;
}
Flowcharts and pseudocodes M58LT256JST, M58LT256JSB
94/108
Figure 24. Erase suspend and resume flowchart and pseudocode
1. The Read Status Register command (Write 70h) can be issued just before or just after the Erase Resume command.
Write 70h
AI12897b
Read Status
Register
YES
NO
SR7 = 1
YES
NO
SR6 = 1
Erase Continues with
Bank in Read Status
Register Mode
Write D0h
Read data from another block
or
Program
or
Block Protect/Unprotect
Start
Write B0h
Erase Complete
Write FFh
Read Data
Write FFh
erase_suspend_command ( ) {
writeToFlash (bank_address, 0xB0) ;
writeToFlash (bank_address, 0x70) ;
/* read status register to check if
erase has already completed */
do {
status_register=readFlash (bank_address) ;
/* E or G must be toggled*/
} while (status_register.SR7== 0) ;
if (status_register.SR6==0) /*erase completed */
{ writeToFlash (bank_address, 0xFF) ;
read_data ( ) ;
/*The device returns to Read Array
(as if program/erase suspend was not issued).*/
}
else
{ writeToFlash (bank_address, 0xFF) ;
read_program_data ( );
/*read or program data from another block*/
writeToFlash (bank_address, 0xD0) ;
/*write 0xD0 to resume erase*/
writeToFlash (bank_address, 0x70) ;
/*read status register to check if erase has completed */
}
}
Write 70h(1)
M58LT256JST, M58LT256JSB Flowcharts and pseudocodes
95/108
Figure 25. Protect/unprotect operation flowchart and pseudocode
1. Any address within the bank can equally be used.
Write
01h, D0h
AI12895
Read Block
Protect State
YES
NO
Protection
change
confirmed?
Start
Write 60h (1) protect_operation_command (address, protect_operation) {
writeToFlash (address, 0x60) ; /*configuration setup*/
/* see note (1) */
if (readFlash (address) ! = protection_state_expected)
error_handler () ;
/*Check the protection state (see Read Block Signature table )*
/
writeToFlash (address, 0xFF) ; /*Reset to Read Array mode*/
/*see note (1) */
}
Write FFh (1)
Write 90h (1)
End
if (protect_operation==PROTECT) /*to protect the block*/
writeToFlash (address, 0x01) ;
else if (protect_operation==UNPROTECT) /*to unprotect the block*/
writeToFlash (address, 0xD0) ;
writeToFlash (address, 0x90) ;
/*see note (1) */
Flowcharts and pseudocodes M58LT256JST, M58LT256JSB
96/108
Figure 26. Protection Register program flowchart and pseudocode
1. Status check of SR1 (Protected Block), SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program
operation or after a sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
3. Any address within the bank can equally be used.
Write C0h (3)
AI06177b
Start
Write Address
& Data
Read Status
Register (3)
YES
NO
SR7 = 1
YES
NO
SR3 = 0
NO
SR4 = 0
VPP Invalid
Error (1, 2)
Program
Error (1, 2)
protection_register_program_command (addressToProgram, dataToProgram) {:
writeToFlash (addressToProgram, 0xC0) ;
/*see note (3) */
do {
status_register=readFlash (addressToProgram) ;
/* see note (3) */
/* E or G must be toggled*/
} while (status_register.SR7== 0) ;
if (status_register.SR3==1) /*VPP invalid error */
error_handler ( ) ;
YES
End
YES
NO
SR1 = 0 Program to Protected
Block Error (1, 2)
writeToFlash (addressToProgram, dataToProgram) ;
/*Memory enters read status state after
the Program Command*/
if (status_register.SR4==1) /*program error */
error_handler ( ) ;
if (status_register.SR1==1) /*program to protect block error */
error_handler ( ) ;
}
M58LT256JST, M58LT256JSB Flowcharts and pseudocodes
97/108
Figure 27. Buffer enhanced factory program flowchart and pseudocode
Write 80h to
Address WA1
AI12898
Start
Write D0h to
Address WA1
Write FFFFh to
Address = NOT WA1
Read Status
Register
SR7 = 0
NO
NO
SR0 = 0
YES
Read Status Register
SR3 and SR1for errors
Exit
Write PDX
Address WA1
Increment Count
X = X + 1
Initialize count
X = 0
X = 32
YES
Read Status
Register
Last data?
YES
Read Status
Register
SR7 = 1
YES
Full Status Register
Check
End
YES
SR4 = 1
NO
NO
NO
NO
SETUP PHASE
PROGRAM AND
VERIFY PHASE
EXIT PHASE
Buffer_Enhanced_Factory_Program_Command
(start_address, DataFlow[]) {
writeToFlash (start_address, 0x80) ;
writeToFlash (start_address, 0xD0) ;
do {
do {
status_register = readFlash (start_address);
if (status_register.SR4==1) { /*error*/
if (status_register.SR3==1) error_handler ( ) ;/*VPP error */
if (status_register.SR1==1) error_handler ( ) ;/* Protected Block */
}
while (status_register.SR7==1)
x=0; /* initialize count */
do {
writeToFlash (start_address, DataFlow[x]);
x++;
}while (x<32)
do {
status_register = readFlash (start_address);
}while (status_register.SR0==1)
} while (not last data)
writeToFlash (another_block_address, FFFFh)
do {
status_register = readFlash (start_address)
}while (status_register.SR7==0)
full_status_register_check();
}
Command interface state tables M58LT256JST, M58LT256JSB
98/108
Appendix D Command interface state tables
Table 45. Command interface states - modify table, next state(1)
Current CI State
Command Input
Read
Array(2)
(FFh)
Program
Setup(3)(4)
(10/40h)
Buffer
Program
(3)(4)
(E8h)
Block
Erase,
Setup(3)(4)
(20h)
BEFP
Setup
(80h)
Blank
Check
setup
(BCh)
Erase
Confirm
P/E Resume,
Block
Unprotect
confirm,
BEFP
Confirm(3)(4)
(D0h)
Blank
Check
confirm
(CBh)
Buffer
Program,
Program/
Erase
Suspend
(B0h)
Read
Status
Register
(70h)
Clear
Status
Register
(5)
(50h)
Read
Electronic
Signature
, Read
CFI Query
(90h, 98h)
Ready Ready Program
Setup
BP
Setup
Erase
Setup
BEFP
Setup
Blank
Check
setup
Ready
Protect/CR Setup Ready (Protect Error)
Ready
(unprotect
block)
Ready (Protect Error)
OTP
Setup OTP Busy
Busy OTP
Busy
IS in OTP
Busy
OTP
busy IS in OTP Busy OTP Busy
IS in
OTP
busy
OTP Busy
Program
Setup Program Busy
Busy Program
Busy
IS in
Program
Busy
Program
Busy
IS in Program
Busy Program Busy Program
Suspend Program Busy
IS in
Program
Busy
Program Busy
Suspend PS IS in PS PS IS in Program
Suspend PS Program Busy Program Suspend
IS in PS Program Suspend
Buffer
Program
Setup Buffer Program Load 1 (give word count load (N-1));
Buffer
Load 1 if N=0 go to Buffer Program Confirm. Else (N ≠ 0) go to Buffer Program Load 2 (data load)
Buffer
Load 2
Buffer Program Confirm when count =0; Else Buffer Program Load 2
(note: Buffer Program will fail at this point if any block address is different from the first address)
Confirm Ready (error) BP Busy Ready (error)
Busy BP Busy IS in BP
Busy BP Busy IS in BP Busy BP Busy BP
Suspend Buffer Program Busy
IS in BP
Busy Buffer Program Busy
Suspend BP
Suspend
IS in BP
Suspend
BP
Suspend IS in BP Suspend BP
Suspend BP busy Buffer Program Suspend
IS in BP
Suspend Buffer Program Suspend
M58LT256JST, M58LT256JSB Command interface state tables
99/108
Erase
Setup Ready (error) Erase Busy Ready (error)
Busy Erase
Busy
IS in
Erase
Busy
Erase
Busy IS in Erase Busy Erase Busy Erase
Suspend Erase Busy
IS in
Erase
Busy
Erase Busy
Suspend Erase
Suspend
Program
in
ES
BP in ES IS in Erase
Suspend ES Erase Busy Erase Suspend
IS in ES Erase Suspend
Program
in Erase
Suspend
Setup Program Busy in Erase Suspend
Busy
Program
Busy in
ES
IS in
Program
Busy in
ES
Program
Busy in
ES
IS in Program
Busy in ES Program Busy in ES PS in ES Program Busy in Erase
Suspend
IS in
Program
busy in
ES
Program busy in Erase Suspend
Suspend PS in ES IS in PS in
ES PS in ES IS in Program
Suspend in ES PS in ES Program Busy
in ES Program Suspend in Erase Suspend
IS in PS
in ES Program Suspend in Erase Suspend
Buffer
Program
in Erase
Suspend
Setup Buffer Program Load 1 in Erase Suspend (give word count load (N-1)); if N=0 go to Buffer Program confirm. Else (N ≠ 0) go to
Buffer Program Load 2
Buffer
Load 1 Buffer Program Load 2 in Erase Suspend (data load)
Buffer
Load 2
Buffer Program Confirm in Erase Suspend when count =0; Else Buffer Program Load 2 in Erase Suspend (note: Buffer Program
will fail at this point if any block address is different from the first address)
Confirm Erase Suspend (sequence error) BP Busy in ES Erase Suspend (sequence error)
Busy BP Busy
in ES
IS in BP
Busy in
ES
BP busy
in ES
IS in BP busy in
ES BP Busy in ES
BP
Suspend
in ES
Buffer Program Busy in ES
IS in BP
busy in
ES
Buffer Program Busy in Erase Suspend
Suspend
BP
Suspend
in ES
IS in BP
Suspend
in ES
BP
Suspend
in ES
IS in BP Suspend
in Erase Suspend
BP
Suspend
in ES
BP Busy in
Erase
Suspend
Buffer Program Suspend in Erase Suspend
IS in BP
Suspend
in ES
BP Suspend in Erase Suspend
Table 45. Command interface states - modify table, next state(1) (continued)
Current CI State
Command Input
Read
Array(2)
(FFh)
Program
Setup(3)(4)
(10/40h)
Buffer
Program
(3)(4)
(E8h)
Block
Erase,
Setup(3)(4)
(20h)
BEFP
Setup
(80h)
Blank
Check
setup
(BCh)
Erase
Confirm
P/E Resume,
Block
Unprotect
confirm,
BEFP
Confirm(3)(4)
(D0h)
Blank
Check
confirm
(CBh)
Buffer
Program,
Program/
Erase
Suspend
(B0h)
Read
Status
Register
(70h)
Clear
Status
Register
(5)
(50h)
Read
Electronic
Signature
, Read
CFI Query
(90h, 98h)
Command interface state tables M58LT256JST, M58LT256JSB
100/108
Blank
Check
Setup Ready (error)
Blank
Check
busy
Ready (error)
Busy Blank Check busy
Protect/CR Setup
in Erase Suspend Erase Suspend (Protect Error) Erase
Suspend Erase Suspend (Protect Error)
Buffer
EFP
Setup Ready (error) BEFP Busy Ready (error)
Busy BEFP Busy(6)
1. CI = Command Interface, CR = Configuration register, BEFP = Buffer Enhanced Factory program, P/E C = Program/Erase
controller, IS = Illegal State, BP = Buffer Program, ES = Erase Suspend.
2. At Power-up, all banks are in. Issuing a Read Array command to a busy bank, results in undetermined data output.
3. The two cycle command should be issued to the same bank address.
4. If the P/E C is active, both cycles are ignored.
5. The Clear Status Register command clears the SR error bits except when the P/E C. is busy or suspended.
6. BEFP is allowed only when Status Register bit SR0 is reset to '0'. BEFP is busy if Block Address is first BEFP Address. Any
other commands are treated as data.
Table 45. Command interface states - modify table, next state(1) (continued)
Current CI State
Command Input
Read
Array(2)
(FFh)
Program
Setup(3)(4)
(10/40h)
Buffer
Program
(3)(4)
(E8h)
Block
Erase,
Setup(3)(4)
(20h)
BEFP
Setup
(80h)
Blank
Check
setup
(BCh)
Erase
Confirm
P/E Resume,
Block
Unprotect
confirm,
BEFP
Confirm(3)(4)
(D0h)
Blank
Check
confirm
(CBh)
Buffer
Program,
Program/
Erase
Suspend
(B0h)
Read
Status
Register
(70h)
Clear
Status
Register
(5)
(50h)
Read
Electronic
Signature
, Read
CFI Query
(90h, 98h)
M58LT256JST, M58LT256JSB Command interface state tables
101/108
Table 46. Command Interface states - modify table, next output state(1) (2)
Current CI State
Command Input
Read
Array
(3)
(FFh)
Program
Setup(4)
(5)
(10/40h)
Buffer
Program
(E8h)
Block
Erase,
Setup(4)
(5)
(20h)
BEFP
Setup
(80h)
Blank
Check
setup
(BCh)
Erase Confirm
P/E Resume,
Block
Unprotect
confirm, BEFP
Confirm(4)(5)
(D0h)
Blank
Check
confirm
(CBh)
Program/
Erase
Suspend
(B0h)
Read
Status
Register
(70h)
Clear
Status
Register
(50h)
Read
Electronic
signature,
Read CFI
Query
(90h, 98h)
Program Setup
Status Register
Erase Setup
OTP Setup
Program Setup in
Erase Suspend
BEFP Setup
BEFP Busy
Buffer Program
Setup
Buffer Program
Load 1
Buffer Program
Load 2
Buffer Program
Confirm
Buffer Program
Setup in Erase
Suspend
Buffer Program
Load 1 in Erase
Suspend
Buffer Program
Load 2 in Erase
Suspend
Buffer Program
Confirm in Erase
Suspend
Blank Check setup
Protect/CR Setup
Protect/CR Setup in
Erase Suspend
Command interface state tables M58LT256JST, M58LT256JSB
102/108
OTP Busy
Array Status Register Output Unchanged Status
Register
Output
Unchang
ed
Status
Register
Ready
Electronic
Signature/
CFI
Program Busy
Erase Busy
Buffer Program
Busy
Program/Erase
Suspend
Buffer Program
Suspend
Program Busy in
Erase Suspend
Buffer Program
Busy in Erase
Suspend
Program Suspend
in Erase Suspend
Buffer Program
Suspend in Erase
Suspend
Blank Check busy
Illegal State Output Unchanged
1. The output state shows the type of data that appears at the outputs if the bank address is the same as the command
address. A bank can be placed in Read Array, Read Status Register, Read Electronic Signature or Read CFI mode,
depending on the command issued. Each bank remains in its last output state until a new command is issued to that bank.
The next state does not depend on the bank output state.
2. CI = Command Interface, CR = Configuration Register, BEFP = Buffer Enhanced Factory Program, P/E. C. =
Program/Erase Controller.
3. At Power-up, all banks are in read array mode. Issuing a Read Array command to a busy bank, results in undetermined
data output.
4. The two cycle command should be issued to the same bank address.
5. If the P/EC is active, both cycles are ignored.
Table 46. Command Interface states - modify table, next output state(1) (2) (continued)
Current CI State
Command Input
Read
Array
(3)
(FFh)
Program
Setup(4)
(5)
(10/40h)
Buffer
Program
(E8h)
Block
Erase,
Setup(4)
(5)
(20h)
BEFP
Setup
(80h)
Blank
Check
setup
(BCh)
Erase Confirm
P/E Resume,
Block
Unprotect
confirm, BEFP
Confirm(4)(5)
(D0h)
Blank
Check
confirm
(CBh)
Program/
Erase
Suspend
(B0h)
Read
Status
Register
(70h)
Clear
Status
Register
(50h)
Read
Electronic
signature,
Read CFI
Query
(90h, 98h)
M58LT256JST, M58LT256JSB Command interface state tables
103/108
Table 47. Command interface states - lock table, next state(1)
Current CI State
Command Input
Protect/CR
Setup(2)
(60h)
OTP
Setup(2)
(C0h)
Block
Protect
Confirm
(01h)
Set CR
Confirm
(03h)
Block Address
(WA0)(3)
(XXXXh)
Illegal
Command(4)
P/E C
operation
completed(5)
Ready Protect/CR Setup OTP Setup Ready N/A
Protect/CR Setup Ready (Protect error) Ready Ready (Protect error) N/A
OTP
Setup OTP Busy N/A
Busy IS in OTP Busy OTP Busy Ready
IS in OTP busy OTP Busy IS Ready
Program
Setup Program Busy N/A
Busy IS in Program Busy Program Busy Ready
IS in Program
busy Program busy IS Ready
Suspend IS in PS Program Suspend
N/A
IS in PS Program Suspend
Buffer
Program
Setup Buffer Program Load 1 (give word count load (N-1)); N/A
Buffer Load 1 Buffer Program Load 2(6) Exit see note (6) N/A
Buffer Load 2 Buffer Program Confirm when count =0; Else Buffer Program Load 2 (note: Buffer Program will fail
at this point if any block address is different from the first address) N/A
Confirm Ready (error) N/A
Busy IS in BP Busy Buffer Program Busy Ready
IS in Buffer
Program busy Buffer Program Busy IS Ready
Suspend IS in BP Suspend Buffer Program Suspend
N/A
IS in BP
Suspend Buffer Program Suspend
Erase
Setup Ready (error) N/A
Busy IS in Erase Busy Erase Busy Ready
IS in Erase busy Erase Busy IS ready
Suspend Protect/CR Setup
in ES IS in ES Erase Suspend
N/A
IS in ES Erase Suspend
Command interface state tables M58LT256JST, M58LT256JSB
104/108
Program
in Erase
Suspend
Setup Program Busy in Erase Suspend N/A
Busy IS in Program busy in ES Program Busy in Erase Suspend ES
IS in Program
busy in ES Program Busy in Erase Suspend IS in ES
Suspend IS in PS in ES Program Suspend in Erase Suspend
N/A
IS in PS in ES Program Suspend in Erase Suspend
Buffer
Program
in Erase
Suspend
Setup Buffer Program Load 1 in Erase Suspend (give word count load (N-1))
N/A
Buffer Load 1 Buffer Program Load 2 in Erase Suspend(7) Exit see note (7)
Buffer Load 2
Buffer Program Confirm in Erase Suspend when count =0; Else Buffer Program Load 2 in Erase
Suspend (note: Buffer Program will fail at this point if any block address is different from the first
address)
Confirm Erase Suspend (sequence error)
Busy IS in BP busy in ES Buffer Program Busy in Erase Suspend ES
IS in BP busy in
ES BP busy in ES IS in ES
Suspend IS in BP suspend in ES Buffer Program Suspend in Erase Suspend
N/A
IS in BP
Suspend in ES Buffer Program Suspend in Erase Suspend
Blank
Check
Setup Ready (error) N/A
Blank Check
busy Blank Check busy Ready
Protect/CR Setup in ES Erase Suspend (Protect error) Erase Suspend Erase Suspend (Protect error) N/A
BEFP
Setup Ready (error) N/A
Busy BEFP Busy(8) Exit BEFP Busy(8) N/A
1. CI = Command Interface, CR = Configuration register, BEFP = Buffer Enhanced Factory program, P/E C = Program/Erase
controller, IS = Illegal State, BP = Buffer program, ES = Erase suspend, WA0 = Address in a block different from first BEFP
address.
2. If the P/E C is active, both cycle are ignored.
3. BEFP Exit when Block Address is different from first Block Address and data are FFFFh.
4. Illegal commands are those not defined in the command set.
5. N/A: not available. In this case the state remains unchanged.
6. If N=0 go to Buffer Program Confirm. Else (not =0) go to Buffer Program Load 2 (data load)
7. If N=0 go to Buffer Program Confirm in Erase suspend. Else (not =0) go to Buffer Program Load 2 in Erase suspend.
8. BEFP is allowed only when Status Register bit SR0 is set to '0'. BEFP is busy if Block Address is first BEFP Address. Any
other commands are treated as data.
Table 47. Command interface states - lock table, next state(1) (continued)
Current CI State
Command Input
Protect/CR
Setup(2)
(60h)
OTP
Setup(2)
(C0h)
Block
Protect
Confirm
(01h)
Set CR
Confirm
(03h)
Block Address
(WA0)(3)
(XXXXh)
Illegal
Command(4)
P/E C
operation
completed(5)
M58LT256JST, M58LT256JSB Command interface state tables
105/108
Table 48. Command interface states - lock table, next output state (1) (2)
Current CI State
Command Input
Protect/CR
Setup(3)(6
0h)
Blank
Check setup
(BCh)
OTP
Setup(3)
(C0h)
Blank Check
confirm
(CBh)
Block
Protect
Confirm
(01h)
Set CR
Confirm
(03h)
BEFP
Exit(4)
(FFFFh)
Illegal
Command
(5)
P. E./C.
Operation
Completed
Program Setup
Status Register
Output
Unchanged
Erase Setup
OTP Setup
Program in Erase Suspend
BEFP Setup
BEFP Busy
Buffer Program Setup
Buffer Program Load 1
Buffer Program Load 2
Buffer Program Confirm
Buffer Program Setup in Erase
Suspend
Buffer Program Load 1 in Erase
Suspend
Buffer Program Load 2 in Erase
Suspend
Buffer Program Confirm in Erase
Suspend
Blank Check setup
Protect/CR Setup
Status Register Array Status Register
Protect/CR Setup in Erase Suspend
Command interface state tables M58LT256JST, M58LT256JSB
106/108
OTP Busy
Status Register Output Unchanged Array Output Unchanged
Ready
Program Busy
Erase Busy
Buffer Program Busy
Program/Erase Suspend
Buffer Program Suspend
Program Busy in Erase Suspend
Buffer Program Busy in Erase
Suspend
Program Suspend in Erase Suspend
Buffer Program Suspend in Erase
Suspend
Blank Check busy
Illegal State Output Unchanged
1. The output state shows the type of data that appears at the outputs if the bank address is the same as the command
address. A bank can be placed in Read Array, Read Status Register, Read Electronic Signature or Read CFI mode,
depending on the command issued. Each bank remains in its last output state until a new command is issued to that bank.
The next state does not depend on the bank's output state.
2. CI = Command Interface, CR = Configuration Register, BEFP = Buffer Enhanced Factory Program, P/E. C. =
Program/Erase Controller.
3. If the P/EC is active, both cycles are ignored.
4. BEFP Exit when Block Address is different from first Block Address and data are FFFFh.
5. Illegal commands are those not defined in the command set.
Table 48. Command interface states - lock table, next output state (continued)(1) (2)
Current CI State
Command Input
Protect/CR
Setup(3)(6
0h)
Blank
Check setup
(BCh)
OTP
Setup(3)
(C0h)
Blank Check
confirm
(CBh)
Block
Protect
Confirm
(01h)
Set CR
Confirm
(03h)
BEFP
Exit(4)
(FFFFh)
Illegal
Command
(5)
P. E./C.
Operation
Completed
M58LT256JST, M58LT256JSB Revision history
107/108
15 Revision history
Table 49. Document revision history
Date Revision Changes
18-Jul-2006 0.1 Initial release.
31-Oct-2006 0.2
Description of CR2-CR0 011 value modified in Ta ble 1 1:
Configuration Register and Note 2 added.
Table 12: Burst type definition modified.
Timings modified in Table 16: Program/erase times and endurance
cycles,.
VIO max and VDDQ max modified in Table 17: Absolute maximum
ratings.
Values changed in Table 20: DC characteristics - currents.
VPP1 modified in Table 21: DC characteristics - voltages.
Figure 24: Erase suspend and resume flowchart and pseudocode
modified.
Appendix D: Command interface state tables modified.
18-Dec-2006 0.3
Document status promoted from Target Specification to Preliminary
Data. Small text changes. Wait (WAIT) signal behavior in relation to
Output Enable modified. Section 5.4: Program status bit (SR4) and
Section 6.9: Burst length bits (CR2-CR0) modified.
Device architecture corrected (see Table 2: Bank architecture,
Figure 3: Memory map and Appendix A: Block address tables).
IDD1 and IDD6 parameter values updated in Tabl e 2 0 : D C
characteristics - currents. Figure 13: Synchronous burst read
suspend AC waveforms modified. tPLWL, tPLEL, tPLGL and tPLLL
values modified under Other conditions (see Table 26: Reset and
power-up AC characteristics). tELTV timing removed from Figure 11:
Synchronous burst read AC waveforms, Figure 13: Synchronous
burst read suspend AC waveforms and Table 23: Synchronous read
AC characteristics. tELTV timing modified in Table 22: Asynchronous
read AC characteristics.
Appendix B: Common Flash interface modified.
23-Feb-2007 1
Block Lock Down confirm (2Fh) removed from Table 47: Command
interface states - lock table, next state and Table 48: Command
interface states - lock table, next output state. Small text changes.
27-Jun-2007 2
Document status promoted from Preliminary Data to full Datasheet.
Section 7.2: Synchronous burst read mode modified.
16 word boundary (wrap) feature removed from the document.
Two packing options added in Table 28: Ordering information
scheme.
Small text changes.
01-Oct-2007 3
Changed deassertion condition in Section 7.2: Synchronous burst
read mode to state that WAIT is only de-asserted when output data
is valid. Changed TA and TBIAS minimum values in Ta ble 1 7:
Absolute maximum ratings from -25 to -40.
10-Dec-2007 4 Applied Numonyx branding.
M58LT256JST, M58LT256JSB
108/108
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