High Temperature, High Voltage,
Latch-Up Proof, 8-Channel Multiplexer
Data Sheet ADG5298
Rev. 0 Document Feedback
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FEATURES
Extreme high temperature operation up to 210°C
Latch-up proof
JESD78D Class II rating
Low leakage
Ultralow capacitance and charge injection
Source capacitance, off: 2.9 pF at ±15 V dual supply
Drain capacitance, off: 34 pF at ±15 V dual supply
Charge injection: 0.2 pC at ±15 V dual supply and
+12 V single supply
Low on resistance: 290 Ω typical for dual supply at 210°C
±9 V to ±22 V dual-supply operation
9 V to 40 V single-supply operation
48 V supply maximum rating
Fully specified at ±15 V, ±20 V, +12 V, and +36 V
VSS to VDD analog signal range
APPLICATIONS
Downhole drilling and instrumentation
Avionics
Heavy industrial
High temperature environments
GENERAL DESCRIPTION
The ADG5298 is a latch-up proof, monolithic, complementary
metal-oxide semiconductor (CMOS) analog multiplexer designed
for operation up to 210°C. The ADG5298 switches one of eight
inputs to a common output, as determined by the 3-bit binary
address lines, A0, A1, and A2.
An EN input enables or disables the device. When EN is disabled,
all channels switch off. The ultralow capacitance and charge
injection of this switch makes it an ideal solution for data
acquisition and sample-and-hold applications, where low glitch
and fast settling are required.
The switch conducts equally well in both directions when on,
and it has an input signal range that extends to the power supplies.
In the off condition, signal levels up to the supplies are blocked.
This multiplexer is available in a 16-lead ceramic flat package
(FLATPACK) and a 16-lead ceramic flat package with reverse
formed gullwing leads (FLATPACK_RF). Both packages are
designed for robustness at extreme temperatures and are
qualified for up to 1000 hours of operation at the maximum
temperature rating.
The ADG5298 is a member of a growing series of high temperature
qualified products offered by Analog Devices, Inc. For a complete
selection table of available high temperature products, see the
high temperature product list and qualification data available at
www.analog.com/hightemp.
FUNCTIONAL BLOCK DIAGRAM
ADG5298
S1
S8
D
1-OF-8
DECODER
A0 A1 A2 EN
14872-001
Figure 1.
PRODUCT HIGHLIGHTS
1. Trench Isolation Guards Against Latch-Up and Minimizes
Parasitic Leakage.
A dielectric trench separates the P channel and N channel
transistors to prevent latch-up even under severe overvoltage
conditions.
2. Achieved JESD78D Class II rating.
The ADG5298 was stressed to ±500 mA with a 10 ms pulse
at the maximum temperature of the device (210°C).
3. 0.2 pC Charge Injection.
4. Dual-Supply Operation.
For applications where the analog signal is bipolar, the
ADG5298 can operate from dual supplies of up to ±22 V.
5. Single-Supply Operation.
For applications where the analog signal is unipolar, the
ADG5298 can operate from a single rail power supply of
up to 40 V.
6. 3 V Logic-Compatible Digital Inputs.
VINH = 2.0 V, VINL = 0.8 V.
7. No Logic Power Supply (VL) Required.
ADG5298 Data Sheet
Rev. 0 | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
±15 V Dual-Supply ....................................................................... 3
±20 V Dual Supply ....................................................................... 4
12 V Single Supply ........................................................................ 5
36 V Single Supply ........................................................................ 6
Continuous Current per Channel (Sx or D) ............................. 6
Absolute Maximum Ratings ............................................................ 7
Thermal Resistance .......................................................................7
ESD Caution...................................................................................7
Pin Configurations and Function Descriptions ............................8
Typical Performance Characteristics ..............................................9
Test Circuits ..................................................................................... 14
Terminology .................................................................................... 16
Theory of Operation ...................................................................... 17
Trench Isolation .......................................................................... 17
Applications Information .............................................................. 18
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 20
REVISION HISTORY
9/2016—Revision 0: Initial Version
Data Sheet ADG5298
Rev. 0 | Page 3 of 20
SPECIFICATIONS
±15 V DUAL-SUPPLY
VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, and −55°C ≤ TA ≤ +210°C, unless otherwise noted.
Table 1.
Parameter Symbol1 Test Conditions/Comments1 Min Typ 2 Max Unit
ANALOG SWITCH
Analog Signal Range VSS VDD V
On Resistance RON Supply voltage (VS) = ±10 V, drain source
current (IDS) = −1 mA, see Figure 31; for
maximum RON, VDD = +13.5 V, VSS = −13.5 V
290 400 Ω
On-Resistance Match Between Channels ΔRON VS = ±10 V, IDS = −1 mA 2.0 10 Ω
On-Resistance Flatness RFLAT (ON) VS = ±10 V, IDS = −1 mA 60 130 Ω
LEAKAGE CURRENTS VDD = +16.5 V, VSS = −16.5 V
Source Off Leakage IS (off) VS = ±10 V, VD =
10 V, see Figure 32 −8 ±0.005 +8 nA
Drain Off Leakage ID (off) VS = ±10 V, VD =
10 V, see Figure 32 −60 ±0.005 +60 nA
Channel On Leakage ID (on), IS (on) VS = VD = ±10 V, see Figure 30 −70 ±0.01 +70 nA
DIGITAL INPUTS
Input High Voltage VINH 2.0 V
Input Low Voltage VINL 0.8 V
Input Current IINL or IINH Input voltage (VIN) = ground voltage (VGND) or VDD −0.1 +0.002 +0.1 µA
Digital Input Capacitance CIN 3 pF
DYNAMIC CHARACTERISTICS3
Transition Time tTRANSITION Load resistance (RL) = 300 Ω, load capacitance
(CL) = 35 pF, VS = 10 V, see Figure 36
150 335 ns
On Time tON (EN) RL = 300 Ω, CL = 35 pF, VS = 10 V, see Figure 38 125 275 ns
Off Time tOFF (EN) RL = 300 Ω, CL = 35 pF, VS = 10 V, see Figure 38 160 275 ns
Break-Before-Make Time Delay tD RL = 300 Ω, CL = 35 pF, S1 voltage (VS1) =
S2 voltage (VS2) = 10 V, see Figure 37
25 55 ns
Charge Injection QINJ VS = 0 V, RS = 0 Ω, CL = 1 nF, see Figure 39 0.2 pC
Off Isolation RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 34 86 dB
Channel to Channel Crosstalk RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 33 −80 dB
−3 dB Bandwidth RL = 50 Ω, CL = 5 pF, see Figure 35 110 MHz
Source Capacitance, Off CS (off) VS = 0 V, frequency (f) = 1 MHz 2.9 pF
Drain Capacitance, Off CD (off) VS = 0 V, f = 1 MHz 34 pF
Source/Drain Capacitance, On CD (on), CS
(on)
VS = 0 V, f = 1 MHz 37 pF
POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V
Supply Current
Positive IDD Digital inputs = 0 V or 5 V, see Figure 28 60 80 µA
Negative
I
SS
Digital inputs = 0 V or 5 V, see Figure 29
10
20
µA
Ground Current IGND Digital inputs = 0 V or 5 V 60 80 µA
Supply Range VDD/VSS GND = 0 V ±9 ±22 V
1 See the Terminology section.
2 TA = 25°C, except for the analog switch and power requirements values, where TA = 210°C.
3 Guaranteed by design, not subject to production test.
ADG5298 Data Sheet
Rev. 0 | Page 4 of 20
±20 V DUAL SUPPLY
VDD = +20 V ± 10%, VSS = −20 V ± 10%, GND = 0 V, and −55°C ≤ TA ≤ +210°C, unless otherwise noted.
Table 2.
Parameter Symbol1 Test Conditions/Comments1 Min Typ 2 Max Unit
ANALOG SWITCH
Analog Signal Range VSS VDD V
On Resistance RON VS = ±15 V, IDS = −1 mA, see Figure 31;
for maximum RON, VDD = +18 V, VSS = −18 V
240 350 Ω
On-Resistance Match Between Channels ΔRON VS = ±15 V, IDS = −1 mA 1.5 10 Ω
R
FL AT (O N)
V
S
= ±15 V, I
DS
= −1 mA
55
110
Ω
LEAKAGE CURRENTS VDD = +22 V, VSS = −22 V
Source Off Leakage IS (off ) VS = ±15 V, VD =
15 V, see Figure 32 −8 ±0.005 +8 nA
Drain Off Leakage ID (off ) VS = ±15 V, VD =
15 V, see Figure 32 −60 ±0.005 +60 nA
Channel On Leakage ID (on), IS (on) VS = VD = ±15 V, see Figure 30 −70 ±0.01 +70 nA
DIGITAL INPUTS
Input High Voltage VINH 2.0 V
V
INL
0.8
V
Input Current IINL or IINH VIN = VGND or VDD −0.1 +0.002 +0.1 µA
Digital Input Capacitance CIN 3 pF
DYNAMIC CHARACTERISTICS3
Transition Time tTRANSITION RL = 300 Ω, CL = 35 pF, VS = 10 V, see Figure 36 140 305 ns
On Time tON (EN) RL = 300 Ω, CL = 35 pF, VS = 10 V, see Figure 38 120 245 ns
Off Time tOFF (EN) RL = 300 Ω, CL = 35 pF, VS = 10 V, see Figure 38 160 260 ns
Break-Before-Make Time Delay tD RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 10 V,
see Figure 37
20 45 ns
Charge Injection QINJ VS = 0 V, RS = 0 Ω, CL = 1 nF, see Figure 39 0.4 pC
Off Isolation RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 34 86 dB
Channel to Channel Crosstalk RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 33 −80 dB
−3 dB Bandwidth RL = 50 Ω, CL = 5 pF, see Figure 35 121 MHz
Source Capacitance, Off CS (off ) VS = 0 V, f = 1 MHz 2.8 pF
C
D
(off)
V
S
= 0 V, f = 1 MHz
33
pF
Source/Drain Capacitance, On CD (on), CS (on) VS = 0 V, f = 1 MHz 36 pF
POWER REQUIREMENTS VDD = +22 V, VSS = −22 V
Supply Current
Positive IDD Digital inputs = 0 V or 5 V, see Figure 28 60 120 µA
Negative ISS Digital inputs = 0 V or 5 V, see Figure 29 10 20 µA
Ground Current IGND Digital inputs = 0 V or 5 V 60 120 µA
Supply Range VDD/VSS GND = 0 V ±9 ±22 V
1 See the Terminology section.
2 TA = 25°C, except for the analog switch and power requirements values, where TA = 210°C.
3 Guaranteed by design, not subject to production test.
Data Sheet ADG5298
Rev. 0 | Page 5 of 20
12 V SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, and −55°C ≤ TA ≤ +210°C, unless otherwise noted.
Table 3.
Parameter Symbol1 Test Conditions/Comments1 Min Typ 2 Max Unit
ANALOG SWITCH
Analog Signal Range VSS VDD V
On Resistance RON VS = 0 V to 10 V, IDS = −1 mA, see Figure 31;
for maximum RON, VDD = 10.8 V, VSS = 0 V
650 800 Ω
On-Resistance Match Between Channels ΔRON VS = 0 V to 10 V, IDS = −1 mA 3 24 Ω
On-Resistance Flatness
R
FL AT (O N)
V
S
= 0 V to 10 V, I
DS
= −1 mA
240
380
Ω
LEAKAGE CURRENTS VDD = 13.2 V, VSS = 0 V
Source Off Leakage IS (off) VS = 1 V/10 V, VD = 10 V/1 V, see Figure 32 −8 ±0.005 +8 nA
Drain Off Leakage ID (off) VS = 1 V/10 V, VD = 10 V/1 V, see Figure 32 −60 ±0.005 +60 nA
Channel On Leakage ID (on), IS (on) VS = VD = 1 V/10 V, see Figure 30 −70 ±0.01 +70 nA
DIGITAL INPUTS
Input High Voltage VINH 2.0 V
Input Low Voltage VINL 0.8 V
Input Current IINL or IINH VIN = VGND or VDD −0.1 +0.002 +0.1 µA
Digital Input Capacitance CIN 3 pF
DYNAMIC CHARACTERISTICS3
Transition Time tTRANSITION RL = 300 Ω, CL = 35 pF, VS = 8 V, see Figure 36 200 490 ns
On Time tON (EN) RL = 300 Ω, CL = 35 pF, VS = 8 V, see Figure 38 180 435 ns
Off Time
t
OFF
(EN)
R
L
= 300 Ω, C
L
= 35 pF, V
S
= 8 V, see Figure 38
165
305
ns
Break-Before-Make Time Delay tD RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 8 V,
see Figure 37
40 95 ns
Charge Injection QINJ VS = 6 V, RS = 0 Ω, CL = 1 nF, see Figure 39 0.2 pC
Off Isolation RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 34 −86 dB
Channel to Channel Crosstalk RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 33 −80 dB
−3 dB Bandwidth RL = 50 Ω, CL = 5 pF, see Figure 35 95 MHz
Source Capacitance, Off CS (off) VS = 6 V, f = 1 MHz 3.3 pF
Drain Capacitance, Off CD (off ) VS = 6 V, f = 1 MHz 38 pF
Source/Drain Capacitance, On CD (on), CS (on) VS = 6 V, f = 1 MHz 41 pF
POWER REQUIREMENTS VDD = 13.2 V
Supply Current
Positive IDD Digital inputs = 0 V or 5 V, see Figure 28 50 75 µA
Negative ISS Digital inputs = 0 V or 5 V, see Figure 29 7.5 15 µA
Ground Current IGND Digital inputs = 0 V or 5 V 50 75 µA
Supply Range VDD/VSS GND = 0 V, VSS = 0 V 9 40 V
1 See the Terminology section.
2 TA = 25°C, except for the analog switch and power requirements values, where TA = 210°C.
3 Guaranteed by design, not subject to production test.
ADG5298 Data Sheet
Rev. 0 | Page 6 of 20
36 V SINGLE SUPPLY
VDD = 36 V ± 10%, VSS = 0 V, GND = 0 V, and −55°C ≤ TA ≤ +210°C, unless otherwise noted.
Table 4.
Parameter Symbol1 Test Conditions/ Comments1 Min Typ 2 Max Unit
ANALOG SWITCH
Analog Signal Range VSS VDD V
On Resistance RON VS = 0 V to 30 V, IDS = −1 mA, see Figure 31;
for maximum RON, VDD = 32.4 V, VSS = 0 V
260 350 Ω
On-Resistance Match Between Channels ΔRON VS = 0 V to 30 V, IDS = −1 mA 1.5 10 Ω
On-Resistance Flatness
R
FL AT (O N)
V
S
= 0 V to 30 V, I
DS
= −1 mA
55
110
Ω
LEAKAGE CURRENTS VDD = 13.2 V, VSS = 0 V
Source Off Leakage IS (off) VS = 1 V/10 V, VD = 10 V/1 V, see Figure 32 −8 ±0.005 +8 nA
Drain Off Leakage ID (off) VS = 1 V/10 V, VD = 10 V/1 V, see Figure 32 −60 ±0.005 +60 nA
Channel On Leakage ID (on), IS (on) VS = VD = 1 V/10 V, see Figure 30 −70 ±0.01 +70 nA
DIGITAL INPUTS
Input High Voltage VINH 2.0 V
Input Low Voltage VINL 0.8 V
Input Current IINL or IINH VIN = VGND or VDD −0.1 +0.002 +0.1 µA
Digital Input Capacitance CIN 3 pF
DYNAMIC CHARACTERISTICS3
Transition Time tTRANSITION RL = 300 Ω, CL = 35 pF, VS = 18 V, see Figure 36 170 320 ns
On Time tON (EN) RL = 300 Ω, CL = 35 pF, VS = 18 V, see Figure 38 150 265 ns
Off Time
t
OFF
(EN)
R
L
= 300 Ω, C
L
= 35 pF, V
S
= 18 V, see Figure 38
180
265
ns
Break-Before-Make Time Delay tD RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 18 V,
see Figure 37
20 55 ns
Charge Injection QINJ VS = 6 V, RS = 0 Ω, CL = 1 nF, see Figure 39 0.3 pC
Off Isolation RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 34 −86 dB
Channel to Channel Crosstalk RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 33 −80 dB
−3 dB Bandwidth RL = 50 Ω, CL = 5 pF, see Figure 35 105 MHz
Source Capacitance, Off CS (off ) VS = 6 V, f = 1 MHz 2.7 pF
Drain Capacitance, Off CD (off ) VS = 6 V, f = 1 MHz 32 pF
Source/Drain Capacitance, On CD (on), CS (on) VS = 6 V, f = 1 MHz 35 pF
POWER REQUIREMENTS VDD = 13.2 V
Supply Current
Positive IDD Digital inputs = 0 V or 5 V, see Figure 28 80 155 µA
Negative ISS Digital inputs = 0 V or 5 V, see Figure 29 10 20 µA
Ground Current IGND Digital inputs = 0 V or 5 V 80 155 µA
Supply Range VDD/VSS GND = 0 V, VSS = 0 V 9 40 V
1 See the Terminology section.
2 TA = 25°C, except for the analog switch and power requirements values, where TA = 210°C.
3 Guaranteed by design, not subject to production test.
CONTINUOUS CURRENT PER CHANNEL (Sx OR D)
Table 5.
Parameter Test Conditions/Comments 175°C 210°C Unit
CONTINUOUS CURRENT (Sx OR D) θJA = 70 °C/W
V
DD
= +15 V, V
SS
= −15 V
10
10
mA maximum
VDD = +20 V, VSS = −20 V 10 10 mA maximum
VDD = 12 V, VSS = 0 V 6 6 mA maximum
V
DD
= 36 V, V
SS
= 0 V
10
10
mA maximum
Data Sheet ADG5298
Rev. 0 | Page 7 of 20
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 6.
Parameter Rating
VDD to VSS 48 V
VDD to GND −0.3 V to +48 V
VSS to GND +0.3 V to −48 V
Analog Inputs1 VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
Digital Inputs1 VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
Peak Current, Sx or D Pins 31 mA (pulsed at 1 ms, 10%
duty cycle maximum)
Continuous Current, Sx or D Pins2 Data + 5%
Temperature Range −55°C to +210°C
Junction Temperature 212°C
Reflow Soldering Peak Temperature,
Pb Free
260°C (+ 0°C/− 5°C)
1 Overvoltages at the Ax, EN, Sx, or D pins are clamped by internal diodes.
Limit the current to the maximum ratings given.
2 See Table 5.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Only one absolute maximum rating can be applied at any one
time.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Table 7. Thermal Resistance
Package Type
θ
JA
θ
JC
Unit
F-16-11 70 22 °C/W
FR-16-11 70 10 °C/W
1 Thermal impedance simulated values are based on JEDEC 2s2p thermal test
board. See JEDEC JESD51.
ESD CAUTION
ADG5298 Data Sheet
Rev. 0 | Page 8 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
A0
1
EN
2
V
SS 3
S1
4
A1
16
A2
15
GND
14
V
DD
13
S2
5
S5
12
S3
6
S6
11
S4
7
S7
10
D
8
S8
9
ADG5298
TOP VIEW
(Not to Scale)
14872-002
Figure 2. FLATPACK Pin Configuration
A1
A2
S5
S6
S7
GND
VDD
S8
A0
EN
S2
S3
S4
VSS
S1
D
ADG5298
TOP VIEW
(Not to Scale)
1
2
3
4
5
16
15
14
13
12
6
11
710
89
14872-003
Figure 3. Reversed Formed FLATPACK Pin Configuration
Table 8. Pin Function Descriptions
Pin No. Mnemonic Description
1 A0 Logic Control Input 0.
2 EN Active High Digital Input. When low, the device is disabled and all switches are off. When high, the Ax logic inputs
determine the on switches.
3 VSS Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to ground.
4 S1 Source Terminal 1. This pin can be an input or an output.
5 S2 Source Terminal 2. This pin can be an input or an output.
6 S3 Source Terminal 3. This pin can be an input or an output.
7 S4 Source Terminal 4. This pin can be an input or an output.
8 D Drain Terminal. This pin can be an input or an output.
9 S8 Source Terminal 8. This pin can be an input or an output.
10 S7 Source Terminal 7. This pin can be an input or an output.
11 S6 Source Terminal 6. This pin can be an input or an output.
12 S5 Source Terminal 5. This pin can be an input or an output.
13 VDD Most Positive Power Supply Potential.
14 GND Ground (0 V) Reference.
15 A2 Logic Control Input 2.
16 A1 Logic Control Input 1.
Table 9. Truth Table
A2 A1 A0 EN On Switch
X1 X1 X1 0 None
0 0 0 1 S1
0 0 1 1 S2
0 1 0 1 S3
0 1 1 1 S4
1 0 0 1 S5
1 0 1 1 S6
1 1 0 1 S7
1 1 1 1 S8
1 X is don’t care.
Data Sheet ADG5298
Rev. 0 | Page 9 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
160
0
20
40
60
80
100
120
140
–25 –20 –15 –10 –5 0 5 10 15 20 25
ON RESISTANCE (Ω)
VS, VD (V)
TA = 25°C
VDD = +18V
VSS = –18V
VDD = +22V
VSS = –22V
VDD = +20V
VSS = –20V
14872-106
Figure 4. On Resistance (RON) as a Function of VS, VD (±20 V Dual Supply)
250
200
150
100
50
0
–20 –15 –10 –5 0 5 10 15 20
ON RESISTANCE (Ω)
V
S
, V
D
(V)
T
A
= 25°C
V
DD
= +9V
V
SS
= –9V
V
DD
= +13.5V
V
SS
= –13.5V
V
DD
= +15V
V
SS
= –15V
V
DD
= +16.5V
V
SS
= –16.5V
14872-107
Figure 5. On Resistance (RON) as a Function of VS, VD (±15 V Dual Supply)
450
0
ON RESISTANCE (Ω)
V
S
, V
D
(V)
0
0.6
1.2
1.8
2.4
3.0
3.6
4.8
5.4
6.0
6.6
7.8
8.4
9.0
9.6
10.2
10.8
11. 4
12.0
12.6
13.2
350
250
50
200
4.2
7.2
400
300
150
100
T
A
= 25°C V
DD
= 9V
V
SS
= 0V
V
DD
= 12V
V
SS
= 0V
V
DD
= 10.8V
V
SS
= 0V
V
DD
= 13.2V
V
SS
= 0V
14872-108
Figure 6. On Resistance (RON) as a Function of VS, VD (12 V Single Supply)
160
0
ON RESISTANCE (Ω)
V
S
, V
D
(V)
0
1.6
3.2
4.8
6.4
8.0
9.6
12.8
14.4
16.0
17.6
19.2
22.4
24.0
25.6
27.2
28.8
30.4
32.0
33.6
35.2
36.8
120
100
60
40
20
140
80
11. 2
38.4
20.8
T
A
= 25°C
V
DD
= 39.6V
V
SS
= 0V
V
DD
= 36V
V
SS
= 0V
V
DD
= 32.4V
V
SS
= 0V
40.0
14872-109
Figure 7. On Resistance (RON) as a Function of VS, VD (36 V Single Supply)
0
50
100
150
200
250
300
350
–15–12–9–6–303691215
ON RESISTANCE (Ω)
V
S
, V
D
(V)
+210°C
+175°C
+125°C
+85°C
+25°C
–40°C
–55°C
V
DD
= +15V
V
SS
= –15V
14872-008
Figure 8. On Resistance (RON) as a Function of VS, VD for Various
Temperatures, ±15 V Dual Supply
0
50
100
150
200
250
300
–20 –15 –10 –5 0 5 10 15 20
V
S
, V
D
(V)
V
DD
= +20V
V
SS
= –20V
ON RESISTANCE (Ω)
+210°C
+175°C
+125°C
+85°C
+25°C
–40°C
–55°C
14872-009
Figure 9. On Resistance (RON) as a Function of VS, VD for Various
Temperatures, ±20 V Dual Supply
ADG5298 Data Sheet
Rev. 0 | Page 10 of 20
V
S
, V
D
(V)
0
100
200
300
400
500
600
700
024681012
ON RESISTANCE (Ω)
V
DD
= 12V
V
SS
= 0V
+210°C
+175°C
+125°C
+85°C
+25°C
–40°C
–55°C
14872-010
Figure 10. On Resistance (RON) as a Function of VS, VD for Various
Temperatures, 12 V Single Supply
0
50
100
150
200
250
300
048121620
V
S
, V
D
(V)
24 28 32 36
ON RESISTANCE (Ω)
+210°C
+175°C
+125°C
+85°C
+25°C
–40°C
–55°C
V
DD
= 36V
V
SS
= 0V
14872-011
Figure 11. On Resistance (RON) as a Function of VS, VD for Various
Temperatures, 36 V Single Supply
–25
–20
–15
–10
–5
0
5
–55 –25 5 35 65 95 125 155 185 215
LEAKAGE CURRENT (nA)
TEMPERATURE (°C)
V
DD
= +15V
V
SS
= –15V
V
BIAS
= +10V, –10V
I
S
(OFF) + –
I
D
(OFF) + –
I
S
(OFF) – +
I
D
(OFF) – +
I
S
, I
D
(ON) + +
I
S
, I
D
(ON) – –
14872-013
Figure 12. Leakage Currents vs. Temperature, ±15 V Dual Supply
–55 –25 5 35 65 95 125 155 185 215
LEAKAGE CURRENT (nA)
TEMPERATURE (°C)
–50
–40
–30
–20
–10
0
10
I
S
(OFF) + –
I
D
(OFF) + –
I
S
(OFF) – +
I
D
(OFF) – +
I
S
, I
D
(ON) + +
I
S
, I
D
(ON) – –
V
DD
= +20V
V
SS
= –20V
V
BIAS
= +15V, –15V
14872-014
Figure 13. Leakage Current vs. Temperature, ±20 V Dual Supply
–55 –25 5 35 65 95 125 155 185 215
LEAKAGE CURRENT (nA)
TEMPERATURE (°C)
–35
–30
–25
–20
–15
–10
–5
0
5
I
S
(OFF) + –
I
D
(OFF) + –
I
S
(OFF) – +
I
D
(OFF) – +
I
S
, ID (ON) + +
I
S
, ID (ON) – –
V
DD
= 12V
V
SS
= 0V
V
BIAS
= 1V, 10V
14872-015
Figure 14. Leakage Current vs. Temperature, 12 V Single Supply
–55 –25 5 35 65 95 125 155 185 215
TEMPERATURE (°C)
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
5
LEAKAGE CURRENT (nA)
V
DD
= 36V
V
SS
= 0V
V
BIAS
= 1V, 30V
I
S
(OFF) + –
I
D
(OFF) + –
I
S
(OFF) – +
I
D
(OFF) – +
I
S
, I
D
(ON) + +
I
S
, I
D
(ON) – –
14872-022
Figure 15. Leakage Current vs. Temperature, 36 V Single Supply
Data Sheet ADG5298
Rev. 0 | Page 11 of 20
0
–80
–100
–120
–140
10k 100k 1M 10M 1G
OFF ISOLATION (dB)
FREQUENCY (Hz)
100M
–60
–40
–20
T
A
= 25°C
V
DD
= +15V
V
SS
= –15V
14872-118
Figure 16. Off Isolation vs. Frequency, ±15 V Dual Supply
0
–80
–100
–120
–140
10k 100k 1M 10M 1G
CROSSTALK (dB)
FREQUENCY (Hz)
100M
–60
–40
–20
BETWEEN S1 AND S2
BETWEEN S1 AND S8
T
A
= 25°C
V
DD
= +15V
V
SS
= –15V
14872-119
Figure 17. Crosstalk vs. Frequency, ±15 V Dual Supply
40
20
15
5
CHARGE INJECTION (pC)
25
30
35
10
0
–20 –10 0 10 20 30
VS(V)
TA = 25°C
DEMUX (DRAIN TO SOURCE)
VDD = +15V
VSS = –15V
VDD = +20V
VSS = –20V
VDD = +36V
VSS = 0V
VDD = +12V
VSS = 0V
14872-120
Figure 18. Charge Injection (QINJ) vs. Source Voltage (VS), Drain to Source
–
5
100k 1M 10M 100M
ATTENUATION (dB)
FREQUENCY (Hz)
1G
–7
–6
–8
–9
–10
–11
–12
T
A
= 25°C
V
DD
= +15V
V
SS
= –15V
14872-122
Figure 19. Attenuation vs. Frequency, ±15 V Dual Supply
0
–80
–100
–1201k 10k 100k 1M
ACPSRR (dB)
FREQUENCY (Hz)
10M
–60
–40
–20
NO DECOUPLING
CAPACITORS
T
A
= 25°C
V
DD
= +15V
V
SS
= –15V
DECOUPLING
CAPACITORS
14872-121
Figure 20. ACPSRR vs. Frequency, ±15 V Dual Supply
5
1
0
–2
CHARGE INJECTION (pC)
2
3
4
–1
–20 –10 0 10 20 30
V
S
(V)
V
DD
= +20V
V
SS
= –20V
V
DD
= +15V
V
SS
= –15V
V
DD
= +36V
V
SS
= 0V
V
DD
= +12V
V
SS
= 0V
T
A
= 25°C
MUX (SOURCE TO DRAIN)
14872-123
Figure 21. Charge Injection (QINJ) vs. Source Voltage (VS), Source to Drain
ADG5298 Data Sheet
Rev. 0 | Page 12 of 20
0
50
100
150
200
250
300
350
400
–4010 60110160210
t
TRANSITION
TIME (ns)
TEMPERATURE (°C)
V
DD
= 12V, V
SS
= 0V
V
DD
= 36V, V
SS
= 0V
V
DD
= +15V, V
SS
= –15V
V
DD
= +20V, V
SS
= –20V
14872-012
Figure 22. tTRANSITION Time vs. Temperature
80
70
60
50
40
30
20
10
0
–15 –10 151050–5
CAPACITANCE (pF)
VS (V)
TA = 25°C
VDD = +15V
VSS = –15V
SOURCE/DRAIN ON
DRAIN OFF
SOURCE OFF
14872-126
Figure 23. Capacitance vs. Source Voltage(VS), ±15 V Dual Supply
–1.0
–0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
–15 –10 –5 0 5 10 15
V
S
(V)
+25°C
+175°C
+210°C
CHARGE INJECTION (pC)
14872-024
V
DD
= +15V
V
SS
= −15V
Figure 24. Charge Injection as a Function of VS for Various Temperatures, ±15
V Dual Supply
–1
0
1
2
3
4
5
–20 –15 –10 –5 0 5 10 15 20
CHARGE INJECTION (pC)
V
S
(V)
+25°C
+175°C
+210°C
V
DD
= +20V
V
SS
= −20V
14872-025
Figure 25. Charge Injection as a Function of VS for Various Temperatures, ±20
V Dual Supply
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
024681012
CHARGE INJECTION (pC)
VS (V)
+25°C
+175°C
+210°C
14872-026
VDD = 12V
VSS = 0V
Figure 26. Charge Injection as a Function of VS for Various Temperatures,
12 V Single Supply
–1.0
–0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0 5 10 15 20 25 30 35
CHARGE INJECTION (pC)
V
S
(V)
+25°C
+175°C
+210°C
14872-127
V
DD
= 36V
V
SS
= 0V
Figure 27. Charge Injection as a Function of VS for Various Temperatures,
36 V Single Supply
Data Sheet ADG5298
Rev. 0 | Page 13 of 20
0
20
40
60
80
100
120
TEMPERATURE (°C)
I
DD
(µA)
V
DD
= 12V, V
SS
= 0V
V
DD
= 36V, V
SS
= 0V
V
DD
= +15V, V
SS
= –15V
V
DD
= +20V, V
SS
= –20V
14872-128
–55 –25 5 35 65 95 125 155 185 215
Figure 28. IDD vs Temperature
–1
0
1
2
3
4
5
6
7
I
SS
(µA)
TEMPERATURE (°C)
V
DD
= 12V, V
SS
= 0V
V
DD
= 36V, V
SS
= 0V
V
DD
= +15V, V
SS
= –15V
V
DD
= +20V, V
SS
= –20V
14872-129
–55 –25 5 35 65 95 125 155 185 215
Figure 29. ISS vs Temperature
ADG5298 Data Sheet
Rev. 0 | Page 14 of 20
TEST CIRCUITS
S2
V
D
V
S
S8
S1 A
D
NC
NC = NO CONNECT
I
D
(ON)
14872-027
Figure 30. On Leakage
S
I
DS
Sx D
V
R
ON
=V÷I
DS
14872-028
Figure 31. On Resistance
S1 D
V
S
A A
V
D
I
S
(OFF) I
D
(OFF)
S8
A
14872-031
Figure 32. Off Leakage
CHANNEL-TO-CHANNEL CROSSTALK = 20 log V
OUT
GND
S1
D
S2
V
OUT
NETWORK
ANALYZER
R
L
50Ω
R
L
50Ω
V
S
V
S
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
14872-029
Figure 33. Channel-to-Channel Crosstalk
V
OUT
50Ω
NETWORK
ANALYZER
R
L
50Ω
Sx
V
S
V
DD
V
SS
0.1µF
DD
V
SS
GND
50Ω
OFF ISOLATION = 20 logV
OUT
V
S
14872-030
Figure 34. Off Isolation
V
OUT
50Ω
NETWORK
ANALYZER
R
L
50Ω
Sx
D
INSERTION LOSS = 20 log
V
OUT
WITH SWITCH
V
OUT
WITHOUT SWITCH
V
S
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
GND
14872-033
Figure 35. −3 dB Bandwidth
Data Sheet ADG5298
Rev. 0 | Page 15 of 20
3V
0V
OUTPUT
t
R < 20ns
t
F < 20ns
A
DDR ESS
D
RIVE (VIN)
t
TRANSITION
t
TRANSITION
50% 50%
90%
10%
OUTPUT
ADG5298
A0
A1
A2
50Ω
300Ω
GND
S1
S2 TO S7
S8
D
35pF
VIN
2.0V EN
V
DD
V
SS
VDD VSS
VS1
VS8
14872-034
Figure 36. Address to Output Switching Times, tTRANSITION
OUTPUT
ADG5298
A0
A1
A2
50Ω
300Ω
GND
S1
S2 TO S7
S8
D
35pF
V
IN
2.0V EN
V
DD
V
SS
V
DD
V
SS
V
S
3V
0V
OUTPUT
80% 80%
A
DDRESS
DRIVE (V
IN
)
t
D
14872-035
Figure 37. Break-Before-Make Time Delay, tD
OUTPUT
ADG5298
A0
A1
A2
50Ω300ΩGND
S1
S2 TO S8
D
35pF
V
IN
EN
V
DD
V
SS
V
DD
V
SS
V
S
3V
0V
OUTPUT
50% 50%
t
OFF
(EN)
t
ON
(EN)
0.9V
OUT
0.1V
OUT
ENABLE
DRIVE (V
IN
)
14872-036
Figure 38. Enable Delay, tON (EN), tOFF (EN)
3V
V
IN
V
OUT
Q
INJ
= C
L
× ∆V
OUT
∆V
OUT
DSx
EN
GND C
L
1nF
V
OUT
V
IN
R
S
V
S
V
DD
V
SS
V
DD
V
SS
A0
A1
A2
ADG5298
14872-037
Figure 39. Charge Injection, QINJ
ADG5298 Data Sheet
Rev. 0 | Page 16 of 20
TERMINOLOGY
IDD
IDD represents the positive supply current.
ISS
ISS represents the negative supply current.
VD, VS
VD and VS represent the analog voltage on Terminal D and
Terminal Sx, respectively.
RON
RON is the ohmic resistance between Terminal D and
Terminal Sx.
∆RON
∆RON represents the difference between the RON of any two
channels.
RFLAT (ON)
Flatness that is defined as the difference between the maximum
and minimum value of on resistance measured over the
specified analog signal range is represented by RFLAT (ON).
IS (Off)
IS (off) is the source leakage current with the switch off.
ID (Off)
ID (off) is the drain leakage current with the switch off.
ID (On), IS (On)
ID (on) and IS (on) represent the channel leakage currents with
the switch on.
VINL
VINL is the maximum input voltage for Logic 0.
VINH
VINH is the minimum input voltage for Logic 1.
IINL, IINH
IINL and IINH represent the low and high input currents of the
digital inputs.
CD (Off)
CD (off) represents the off switch drain capacitance, which is
measured with reference to ground.
CS (Off)
CS (off) represents the off switch source capacitance, which is
measured with reference to ground.
CD (On), CS (On)
CD (on) and CS (on) represent on switch capacitances, which are
measured with reference to ground.
CIN
CIN represents the digital input capacitance.
tON (EN)
tON (EN) represents the delay time between the 50% and 90%
points of the digital input and switch on condition.
tOFF (EN)
tOFF (EN) represents the delay time between the 50% and 90%
points of the digital input and switch off condition.
tTRANSITION
tTRANSITION represents the delay time between the 50% and 90%
points of the digital inputs and the switch on condition when
switching from one address state to another.
Break-Before-Make Time Delay (tD)
tD represents the off time measured between the 80% point of
both switches when switching from one address state to
another.
Off Isolation
Off isolation is a measure of unwanted signal coupling through
an off channel.
Charge Injection
Charge injection is a measure of the glitch impulse transferred
from the digital input to the analog output during switching.
Crosstalk
Crosstalk is a measure of unwanted signal that is coupled
through from one channel to another as a result of parasitic
capacitance.
Bandwidth
Bandwidth is the frequency at which the output is attenuated
by −3 dB.
On Response
On response is the frequency response of the on switch.
AC Power Supply Rejection Ratio (ACPSRR)
ACPSRR is a measure of the ability of a device to avoid coupling
noise and spurious signals that appear on the supply voltage pin
to the output of the switch. The dc voltage on the device is
modulated by a sine wave of 0.62 V p-p. The ratio of the amplitude
of signal on the output to the amplitude of the modulation is the
ACPSRR.
Data Sheet ADG5298
Rev. 0 | Page 17 of 20
THEORY OF OPERATION
The ADG5298 is a latch-up proof, bidirectional, 8:1 CMOS
multiplexer that is designed to operate at very high temperatures.
The device is controlled by four parallel digital inputs (EN, A0,
A1, and A2). The EN input allows for the ADG5298 to be enabled
or disabled. When the ADG5298 is disabled, the source pins (S1
to S8) disconnect from the drain pin (D). When the ADG5298
is enabled, the address lines (A0, A1, and A2) can determine
which source pin (S1 to S8) is connected to the drain pin (D).
TRENCH ISOLATION
In the ADG5298, an insulating oxide layer (trench) is placed
between the negative channel metal-oxide semiconductor
(NMOS) and the positive channel metal-oxide semiconductor
(PMOS) transistors of each CMOS switch. Parasitic junctions,
which occur between the transistors in junction isolated switches,
are eliminated, and the result is a completely latch-up proof
switch that has minimal leakage over temperature.
In junction isolation, the N well and P well of the PMOS and
NMOS transistors form a diode that is reverse biased under
normal operation. However, during overvoltage conditions, this
diode can become forward-biased. A silicon controlled rectifier
(SCR) type circuit is formed by the two transistors, causing a
significant amplification of the current that, in turn, leads to
latch-up. With trench isolation, this diode is removed, and the
result is a latch-up proof switch.
NMOS PMOS
P WELL N WELL
BURIED OXIDE LAYER
HANDLE WAFER
TRENCH
14872-038
Figure 40. Trench Isolation
ADG5298 Data Sheet
Rev. 0 | Page 18 of 20
APPLICATIONS INFORMATION
The ultralow capacitance and charge injection of this switch
makes it an ideal solution for data acquisition and sample-and-
hold applications, where low glitch and fast settling are required.
The ADG5298 can operate in a wide ambient temperature
range from −55°C to +210°C. Its wide range coupled with its
latch-up immune and low leakage features makes the ADG5298
perfect for use in harsh environments, such as downhole drilling
and avionics. The ADG5298 has achieved a JESD78D Class II
rating, handling stresses to ±500 mA with a 10 ms pulse at the
maximum operating temperature of the device (210°C).
Data Sheet ADG5298
Rev. 0 | Page 19 of 20
OUTLINE DIMENSIONS
04-27-2016-A
TOP VIEW BOTTOM VIEW
END VIEW
SIDE VIEW
0.66 MIN
0.20 MIN
0.70 REF
8.89 MIN
1.02
MIN
7.01
6.86
6.71 5.23
5.08
4.93
10.36
10.16
9.96
7.40
7.24
7.09
25.65
25.40
25.15
0.152
0.127
0.102
2.32
2.11
1.90
0.48
0.43
0.38
1.34
1.27
1.20
1
8
16
9
0.89
BSC
PKG-004164/4875
R 0.32
BSC
Figure 41. 16-Lead Ceramic Flat Package [FLATPACK]
(F-16-1)
Dimensions shown in millimeters
0
6-24-2015-A
BOTTOM VIEW
16 9
18
12.446
REF
0.66 MIN
P
KG-004875
3.02
2.74
2.46
0.432
0.381
0.330
SIDE VIEW
SEATING
PLANE
4.978
4.826
4.673 1.524
1.397
1.270
1.524
1.397
1.270
0.254
0.203
0.152
0.254
0.203
0.152
END VIEW
7.01
6.86
6.71
10.36
10.16
9.96 7.40
7.24
7.09
5.23
5.08
4.93
2.32
2.11
1.90
0.48
0.43
0.38
1.34
1.27
1.20
0.152
0.127
0.102
Figure 42. 16-Lead Ceramic Flat Package with Reverse Formed Gullwing Leads [FLATPACK_RF]
Cavity Down
(FR-16-1)
Dimensions shown in millimeters
ADG5298 Data Sheet
Rev. 0 | Page 20 of 20
ORDERING GUIDE
Model1 Temperature Range Package Description
Package
Option
ADG5298HFZ −55°C to +210°C 16-Lead Ceramic Flat Package [FLATPACK] F-16-1
ADG5298HFRZ −55°C to +210°C 16-Lead Ceramic Flat Package with Reverse Formed Gullwing Leads [FLATPACK_RF] FR-16-1
EVAL-ADG5298EB1Z Evaluation Board
1 Z = RoHS Compliant Part.
©2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14872-0-9/16(0)