MC10E336, MC100E336 5VECL 3Bit Registered Bus Transceiver The MC10E/MC100E336 contains three bus transceivers with both transmit and receive registers. The bus outputs (BUS0-BUS2) are specified for driving a 25 bus; the receive outputs (Q0 - Q2) are specified for 50 . The bus outputs feature a normal HIGH level (VOH) and a cutoff LOW level -- when LOW, the outputs go to -2.0 V and the output emitter-follower is "off", presenting a high impedance to the bus. The bus outputs also feature edge slow-down capacitors. The Transmit Enable pins (TEN) control whether current data is held in the transmit register, or new data is loaded from the A/B inputs. A LOW on both of the Bus Enable inputs (BUSEN), when clocked through the register, disables the bus outputs to -2.0 V. The receiver section clocks bus data into the receive registers, after gating with the Receive Enable (RXEN) input. All registers are clocked by a positive transition of CLK1 or CLK2 (or both). Additional leadframe grounding is provided through the Ground pins (GND) which should be connected to 0 V. The GND pins are not electrically connected to the chip. The 100 Series contains temperature compensation. * * * * * * * * * 25 Cutoff Bus Outputs http://onsemi.com MARKING DIAGRAMS MC10E336FN AWLYYWW PLCC-28 FN SUFFIX CASE 776 A WL YY WW 28 1 = Assembly Location = Wafer Lot = Year = Work Week 50 Receiver Outputs MC100E336FN AWLYYWW 28 1 Transmit and Receive Registers 1500 ps Max. Clock to Bus ORDERING INFORMATION 1000 ps Max. Clock to Q Bus Outputs Feature Internal Edge Slow-Down Capacitors Device Package Shipping Additional Package Ground Pins MC10E336FN PLCC-28 37 Units/Rail PECL Mode Operating Range: VCC= 4.2 V to 5.7 V with VEE= 0 V NECL Mode Operating Range: VCC= 0 V with VEE= -4.2 V to -5.7 V Internal Input Pulldown Resistors MC10E336FNR2 PLCC-28 500 Units/Reel MC100E336FN PLCC-28 37 Units/Rail MC100E336FNR2 PLCC-28 500 Units/Reel * * ESD Protection: > 1 KV HBM, > 75 V MM * Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test * Moisture Sensitivity Level 1 * * For Additional Information, see Application Note AND8003/D Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34 Transistor Count = 430 devices Semiconductor Components Industries, LLC, 2000 October, 2000 - Rev. 3 1 Publication Order Number: MC10E336/D MC10E336, MC100E336 LOGIC DIAGRAM AND PINOUT ASSIGNMENT TEN2 TEN1 B2 A2 NC VCCO Q2 23 22 21 PIN DESCRIPTION BUSEN1 BUSEN2 RXEN 26 25 24 20 19 18 PIN GND FUNCTION TEN1, TEN2 ECL Transit Enable A0-A2 ECL Data Inputs A B0-B2 ECL Data Inputs B Q0-Q1 ECL Output 27 17 BUS2 28 16 VCC 15 Q1 BUSEN1, BUSEN2 ECL Bus Enables 14 VCCO BUS0-BUS2 ECL Bus Outputs RXEN ECL Receive Enable CLK1, CLK2 ECL Clock Input VCC, VCCO Positive Supply VEE Negative Supply GND Ground NC No Connect VEE 1 CLK1 2 CLK2 3 13 BUS1 A0 4 12 GND Pinout: 28-Lead PLCC (Top View) 5 6 7 B0 A1 B1 8 9 10 11 VCCO BUS0 GND Q0 * All VCC and VCCO pins are tied together on the die. Warning: All VCC, VCCO, and VEE pins must be externally connected to Power Supply to guarantee proper operation. LOGIC DIAGRAM A0 B0 0 1 DQ 25 W CUTOFF D Q 0 A1 B1 DQ 25 W CUTOFF 1 D Q 0 A2 B2 DQ 50 W 25 W CUTOFF 1 D Q TEN1 TEN2 RXEN BUSEN1 BUSEN2 50 W DQ CLK1 CLK2 http://onsemi.com 2 50 W BUS0 Q0 BUS1 Q1 BUS2 Q2 MC10E336, MC100E336 MAXIMUM RATINGS (Note 1.) Symbol Parameter Condition 1 Condition 2 Rating Units VCC PECL Mode Power Supply VEE = 0 V 8 V VEE NECL Mode Power Supply VCC = 0 V -8 V VI PECL C Mode ode Input u Voltage o age NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 -6 V V Iout Output Current Continuous Surge 50 100 mA mA TA Operating Temperature Range Tstg Storage Temperature Range JA Thermal Resistance (Junction to Ambient) 0 LFPM 500 LFPM 28 PLCC 28 PLCC JC Thermal Resistance (Junction to Case) std bd 28 PLCC VEE PECL Operating Range NECL Operating Range Tsol Wave Solder VI VCC VI VEE 0 to +85 C -65 to +150 C 63.5 43.5 C/W C/W 22 to 26 C/W 4.2 to 5.7 -5.7 to -4.2 V V 265 C <2 to 3 sec @ 248C 1. Maximum Ratings are those values beyond which device damage may occur. 10E SERIES PECL DC CHARACTERISTICS VCCx= 5.0 V; VEE= 0.0 V (Note 1.) 0C Symbol Characteristic Min Typ 25C Max Min Typ 85C Max Min Typ Max Unit IEE Power Supply Current 125 150 125 150 125 150 mA VOH Output HIGH Voltage (Note 2.) 3980 4070 4160 4020 4105 4190 4090 4185 4280 mV VOL Output LOW Voltage (Note 2.) 3050 3210 3370 3050 3210 3370 3050 3227 3405 mV VIH Input HIGH Voltage 3830 3995 4160 3870 4030 4190 3940 4110 4280 mV VIL Input LOW Voltage 3050 3285 3520 3050 3285 3520 3050 3302 3555 mV VCUT Cut-off Output Voltage (Note 2.) 2.97 2.9 2.97 2.9 IIH Input HIGH Current 2.9 V A RXEN All Other Inputs IIL 2.97 Input LOW Current 225 150 0.5 0.3 225 150 0.5 0.25 225 150 0.3 A 0.2 NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.46 V / -0.06 V. 2. Outputs are terminated through a 50 ohm resistor to VCC -2.10 volts. 10E SERIES NECL DC CHARACTERISTICS VCCx= 0.0 V; VEE= -5.0 V (Note 1.) 0C Symbol Characteristic Min 25C Typ Max 125 150 Min 85C Typ Max 125 150 Min IEE Power Supply Current VOH Output HIGH Voltage (Note 2.) -1020 -930 -840 -980 -895 -810 -910 VOL Output LOW Voltage (Note 2.) -1950 -1790 -1630 -1950 -1790 -1630 -1950 VIH Input HIGH Voltage -1170 -1005 -840 -1130 -970 -810 -1060 VIL Input LOW Voltage -1950 -1715 -1480 -1950 -1715 -1480 -1950 VCUT Cut-off Output Voltage (Note 2.) 2.97 2.9 2.97 2.9 IIH Input HIGH Current 2.9 Input LOW Current Max Unit 125 150 mA -815 -720 mV -1773 -1595 mV -890 -720 mV -1698 -1445 mV 2.97 V A RXEN All Other Inputs IIL Typ 225 150 0.5 0.3 225 150 0.5 0.065 225 150 0.3 0.2 A NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.46 V / -0.06 V. 2. Outputs are terminated through a 50 ohm resistor to VCC -2.10 volts. http://onsemi.com 3 MC10E336, MC100E336 100E SERIES PECL DC CHARACTERISTICS VCCx= 5.0 V; VEE= 0.0 V (Note 1.) 0C Symbol Characteristic Min 25C Typ Max 125 150 Min 85C Typ Max 125 150 Min Typ Max Unit 144 173 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 2.) 3975 4050 4120 3975 4050 4120 3975 4050 4120 mV VOL Output LOW Voltage (Note 2.) 3190 3295 3380 3190 3255 3380 3190 3260 3380 mV VIH Input HIGH Voltage 3835 4050 4120 3835 4120 4120 3835 4120 4120 mV VIL Input LOW Voltage 3190 3300 3525 3190 3525 3525 3190 3525 3525 mV VCUT Cut-off Output Voltage (Note 2.) 2.97 2.9 2.97 2.9 2.97 V IIH Input HIGH Current IIL Input LOW Current 2.9 A RXEN All Other Inputs 225 150 0.5 0.3 225 150 0.5 0.25 225 150 0.5 A 0.2 NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.46 V / -0.8 V. 2. Outputs are terminated through a 50 ohm resistor to VCC -2.10 volts. 100E SERIES NECL DC CHARACTERISTICS VCCx= 0.0 V; VEE= -5.0 V (Note 1.) 0C Symbol Characteristic Min 25C Typ Max 125 150 Min 85C Typ Max 125 150 Min Typ Max Unit 144 173 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 2.) -1025 -950 -880 -1025 -950 -880 -1025 -950 -880 mV VOL Output LOW Voltage (Note 2.) -1810 -1705 -1620 -1810 -1745 -1620 -1810 -1740 -1620 mV VIH Input HIGH Voltage -1165 -950 -880 -1165 -880 -880 -1165 -880 -880 mV VIL Input LOW Voltage -1810 -1700 -1475 -1810 -1475 -1475 -1810 -1475 -1475 mV VCUT Cut-off Output Voltage (Note 2.) 2.97 2.9 2.97 2.9 2.97 V IIH Input HIGH Current IIL Input LOW Current 2.9 A RXEN All Other Inputs 225 150 0.5 0.3 225 1502 0.5 0.25 225 150 0.5 0.2 A NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.46 V / -0.8 V. 2. Outputs are terminated through a 50 ohm resistor to VCC -2.10 volts. http://onsemi.com 4 MC10E336, MC100E336 AC CHARACTERISTICS VCCx= 5.0 V; VEE= 0.0 V or VCCx= 0.0 V; VEE= -5.0 V (Note 1.) 0C Symbol Characteristic Min fMAX Maximum Toggle Frequency tPLH Propagation Delay to Output th tPW Min 85C Typ Max Min TBD Typ Max TBD Unit GHz ps Clk to Q 500 700 100 500 700 1000 500 700 1000 Clk to BUS 825 1250 1800 825 1250 1800 825 1250 1800 BUS, RXEN 150 -150 150 -150 150 -150 BUSEN 100 - 200 100 - 200 100 - 200 A, B Data 300 - 50 300 - 50 300 - 50 TEN 450 150 450 150 450 150 Setup Time ps Hold Time ps BUS, RXEN 450 150 450 150 450 150 BUSEN 500 200 500 200 500 200 A, B Data 350 50 350 50 350 50 TEN 200 -150 200 -150 200 -150 Clk 400 Minimum Pulse Width tJITTER Cycle-to-Cycle Jitter tr Rise/Fall Times tf 25C Max TBD tPHL ts Typ ps 400 TBD 400 TBD TBD ps ps 20 - 80% (Qn) 300 450 700 300 450 700 300 450 700 20 - 80% (BUSn Rise) 500 800 1000 500 800 1000 500 800 1000 20 - 80% (BUSn Fall) 300 500 800 300 500 800 300 500 800 1. 10 Series: VEE can vary +0.46 V / -0.06 V. 100 Series: VEE can vary +0.46 V / -0.8 V. Q D Receiver Device Driver Device Qb Db 50 50 V TT VTT = VCC -2.10 V Figure 1. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020 - Termination of ECL Logic Devices.) http://onsemi.com 5 MC10E336, MC100E336 Resource Reference of Application Notes AN1404 - ECLinPS Circuit Performance at Non-Standard VIH Levels AN1405 - ECL Clock Distribution Techniques AN1406 - Designing with PECL (ECL at +5.0 V) AN1503 - ECLinPS I/O SPICE Modeling Kit AN1504 - Metastability and the ECLinPS Family AN1568 - Interfacing Between LVDS and ECL AN1596 - ECLinPS Lite Translator ELT Family SPICE I/O Model Kit AN1650 - Using Wire-OR Ties in ECLinPS Designs AN1672 - The ECL Translator Guide AND8001 - Odd Number Counters Design AND8002 - Marking and Date Codes AND8020 - Termination of ECL Logic Devices http://onsemi.com 6 MC10E336, MC100E336 PACKAGE DIMENSIONS PLCC-28 FN SUFFIX PLASTIC PLCC PACKAGE CASE 776-02 ISSUE E 0.007 (0.180) B Y BRK -N- T L -M M M 0.007 (0.180) U S N T L -M S S N S D Z -L- -M- D W X V 28 1 G1 0.010 (0.250) S T L -M S N S VIEW D-D Z C A 0.007 (0.180) R 0.007 (0.180) M M T L -M S T L -M S N S N S H M 0.007 (0.180) T L -M N S K1 E 0.004 (0.100) G J S K SEATING PLANE F VIEW S G1 0.010 (0.250) -T- T L -M S N 0.007 (0.180) VIEW S S NOTES: 1. DATUMS L, M, AND N DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM T, SEATING PLANE. 3. DIM R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). DIM A B C E F G H J K R U V W X Y Z G1 K1 http://onsemi.com 7 INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 0.025 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 0.020 10 2 0.410 0.430 0.040 MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.57 4.20 2.79 2.29 0.48 0.33 1.27 BSC 0.81 0.66 0.51 0.64 11.58 11.43 11.58 11.43 1.21 1.07 1.21 1.07 1.42 1.07 0.50 10 2 10.42 10.92 1.02 M T L -M S N S S MC10E336, MC100E336 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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