DATASHEET AX5051 Version 1.6 2 Document Type Document Status Document Version Product Version 1.6 Datasheet Version 1.6 AX5051 Datasheet AX5051 Table of Contents Table of Contents 1. Overview .................................................................................................................................... 6 1.1. Features ........................................................................................................................................... 6 1.2. Applications .................................................................................................................................... 6 2. Block Diagram ........................................................................................................................... 7 3. Pin Function Descriptions .......................................................................................................... 8 3.1. Pinout Drawing ............................................................................................................................... 9 4. Specifications .......................................................................................................................... 10 4.1. Absolute Maximum Ratings ........................................................................................................ 10 4.2. DC Characteristics ....................................................................................................................... 11 Supplies .......................................................................................................................................... 11 Logic ............................................................................................................................................... 12 4.3. AC Characteristics ....................................................................................................................... 13 Crystal Oscillator ........................................................................................................................... 13 RF Frequency Generation Subsystem (Synthesizer) ................................................................ 14 Transmitter...................................................................................................................................... 15 Receiver ......................................................................................................................................... 16 SPI Timing........................................................................................................................................ 18 5. Circuit Description ................................................................................................................... 19 5.1. Voltage Regulator ....................................................................................................................... 20 5.2. Crystal Oscillator........................................................................................................................... 20 5.3. SYSCLK Output.............................................................................................................................. 21 5.4. Power-on-reset (POR) and RESET_N Input ................................................................................ 21 5.5. RF Frequency Generation Subsystem....................................................................................... 21 VCO ................................................................................................................................................ 22 VCO Auto-Ranging ...................................................................................................................... 22 Loop Filter and Charge Pump .................................................................................................... 22 Version 1.6 Datasheet AX5051 3 4 Table of Contents Registers ......................................................................................................................................... 22 5.6. RF Input and Output Stage (ANTP/ANTN) ................................................................................ 23 LNA.................................................................................................................................................. 23 I/Q Mixer......................................................................................................................................... 23 PA .................................................................................................................................................... 23 5.7. Analog IF Filter .............................................................................................................................. 23 5.8. Digital IF Channel Filter and Demodulator............................................................................... 23 Registers ......................................................................................................................................... 24 5.9. Encoder ......................................................................................................................................... 24 5.10. Framing and FIFO ................................................................................................................... 25 HDLC Mode ................................................................................................................................... 26 RAW Mode..................................................................................................................................... 26 RAW Mode with Preamble Match............................................................................................. 26 802.15.4 (ZigBee)........................................................................................................................... 27 5.11. RX AGC and RSSI .................................................................................................................... 27 5.12. Modulator ................................................................................................................................ 28 5.13. Automatic Frequency Control (AFC) .................................................................................. 28 5.14. PWRMODE Register ................................................................................................................ 29 5.15. Serial Peripheral Interface (SPI) ............................................................................................ 31 SPI Timing........................................................................................................................................ 31 6. Register Bank Description ....................................................................................................... 32 6.1. Control Register Map................................................................................................................... 33 7. Application Information.......................................................................................................... 37 7.1. Typical Application Diagram ..................................................................................................... 37 7.2. Antenna Interface Circuitry........................................................................................................ 38 Single-Ended Antenna Interface ............................................................................................... 38 Dipole Antenna Interface ........................................................................................................... 39 7.3. Voltage Regulator ....................................................................................................................... 39 Version 1.6 Datasheet AX5051 Table of Contents 8. QFN28 Package Information .................................................................................................. 40 8.1. Package Outline QFN28 ............................................................................................................. 40 8.2. QFN28 Soldering Profile ............................................................................................................... 41 8.3. QFN28 Recommended Pad Layout ......................................................................................... 42 8.4. Assembly Process ......................................................................................................................... 42 Stencil Design & Solder Paste Application ............................................................................... 42 9. Life Support Applications ........................................................................................................ 44 10. Contact Information ................................................................................................................ 45 Version 1.6 Datasheet AX5051 5 6 Overview 1. Overview 1.1. * QFN28 package * Low power receiver: 20 - 21 mA in high sensitivity mode and 17-18 mA in low power mode * Low power transmitter 11 - 40 mA during transmit Features * Advanced multi-channel single chip UHF transceiver * * Configurable for usage in 400-470 MHz and 800-930 MHz SRD bands Extended supply voltage range 2.3V - 3.6V * Internal power-on-reset * 32 bit RX/TX data FIFO * Programmable Cyclic Redundancy Check (CRC-CCITT, CRC-16, CRC32) * Optional spectral shaping using a self synchronizing shift register * Brown-out detection * Integrated RX/TX switching * Differential antenna pins * * * Wide variety of shaped modulations supported in RX and TX (ASK, PSK, MSK, FSK) Data rates from 38.4 to 200 kbps (FSK, MSK) and to 600 kbps (ASK, PSK) Ultra fast settling RF frequency synthesizer for low-power consumption * Variable channel filtering from 40 kHz to 600 kHz * 802.15.4 compatible * RF carrier frequency and FSK deviation programmable in 1 Hz steps * Fully integrated RF frequency synthesizer with VCO auto-ranging and band-width boost modes for fast locking * Few external components * 1.2. Applications 400-470 MHz and 800-930 MHz data transmission and reception in the Short Range Devices (SRD) band. * Telemetric applications, sensor readout On chip communication controller and flexible digital modem * Toys * Channel hopping up to 2000 hops/s * Wireless audio * Wireless networks * Sensitivity down to -104 dBm * Wireless USB * Up to +12 dBm programmable transmitter power amplifier for long range operation * Access control * Remote keyless entry * ARIB compatible * Pointing devices and keyboards * Active RFID * RFID base station transmitter * 433/868/915 MHz SRD band systems * Crystal oscillator with programmable transconductance and programmable internal tuning capacitors for low cost crystals * Automatic frequency control (AFC) * SPI micro-controller interface * Fully integrated current/voltage references Version 1.6 Datasheet AX5051 Block Diagram Block Diagram AX5051 Modulator PA FOUT Divider Voltage Regulator 13 24 VREG SYSCLK 28 CLK16N CLK16P 27 Communication Controller & Serial Interface Chip configuration POR 14 15 20 16 17 12 19 RESET_N RF Frequency Generation Subsystem FXTAL IRQ Crystal Oscillator typ. 16 MHz AGC FIFO RSSI MOSI 5 MISO ANTN Demodulator CLK 4 VDD_IO ANTP Digital IF channel filter ADC Framing IF Filter & AGC PGAs LNA Encoder Mixer SEL 2. Figure 1 Functional block diagram of the AX5051 Version 1.6 Datasheet AX5051 7 8 Pin Function Descriptions 3. Pin Function Descriptions Symbol Pin(s) Type Description NC 1 N Not to be connected VDD 2 P Power supply, must be supplied with regulated voltage VREG GND 3 P Ground ANTP 4 A Antenna input/output ANTN 5 A Antenna input/output GND 6 P Ground VDD 7 P Power supply, must be supplied with regulated voltage VREG NC 8 N Not to be connected TST1 9 I Must be connected to GND TST2 10 I Must be connected to GND GND 11 P Ground RESET_N 12 I Optional reset pin If this pin is not used it must be connected to VDD_IO SYSCLK 13 I/O SEL 14 I Default functionality: Crystal oscillator (or divided) clock output Can be programmed to be used as a general purpose I/O pin Serial peripheral interface select CLK 15 I MISO 16 O MOSI 17 I Serial peripheral interface data input TST3 18 I Must be connected to GND IRQ 19 I/O VDD_IO 20 P Unregulated power supply NC 21 N Not connected GND 22 P Ground NC 23 N Not to be connected VREG 24 P Regulated output voltage VDD pins must be connected to this supply voltage A 1F low ESR capacitor to GND must be connected to this pin NC 25 N Not to be connected VDD 26 P Power supply, must be supplied with regulated voltage VREG CLK16P 27 A Crystal oscillator input/output CLK16N 28 A Crystal oscillator input/output A = I = O = analog signal digital input signal digital output signal Serial peripheral interface clock Serial peripheral interface data output Default functionality: Transmit and receive interrupt Can be programmed to be used as a general purpose I/O pin I/O N P = = = digital input/output signal not to be connected power or ground All digital inputs are Schmitt trigger inputs, digital input and output levels are LVCMOS/LVTTL compatible and 5V tolerant. The centre pad of the QFN28 package should be connected to GND. Version 1.6 Datasheet AX5051 Pin Function Descriptions CLK16P NC VREG NC GND 28 VDD Pinout Drawing CLK16N 3.1. 27 26 25 24 23 22 21 NC NC 1 VDD 2 20 VDD_IO GND 3 19 IRQ AX5051 ANTP 4 18 TST3 10 11 12 13 14 SEL 9 SYSCLK 8 GND 15 CLK RESET_N VDD 7 TST2 16 MISO TST1 17 MOSI GND 6 NC ANTN 5 Figure 2: Pinout drawing (Top view) Version 1.6 Datasheet AX5051 9 10 Specifications 4. Specifications 4.1. Absolute Maximum Ratings Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. SYMBOL DESCRIPTION VDD_IO Supply voltage IDD CONDITION MIN MAX UNIT -0.5 5.5 V Supply current 100 mA Ptot Total power consumption 800 mW Pi Absolute maximum input power at receiver input 15 dBm II1 DC current into any pin except ANTP, ANTN -10 10 mA II2 DC current into pins ANTP, ANTN -100 100 mA IO Output Current 40 mA Via Input voltage ANTP, ANTN pins -0.5 5.5 V Input voltage digital pins -0.5 5.5 V -2000 2000 V Ves Electrostatic handling Tamb Operating temperature -40 85 C Tstg Storage temperature -65 150 C Tj Junction Temperature 150 C Version 1.6 HBM Datasheet AX5051 Specifications 4.2. DC Characteristics Supplies SYMBOL DESCRIPTION TAMB Operational ambient temperature VDD_IO I/O and voltage regulator supply voltage VREG Internally regulated supply voltage CONDITION MIN. TYP. MAX. UNIT -40 27 85 C RX operation or TX operation up to 4 dBm output power 2.3 3.0 3.6 V TX operation up to 12 dBm output power 2.4 3.0 3.6 V Power-down mode PWRMODE=0x00 All other power modes 1.7 2.1 2.5 V 2.8 V VREGdroptyp Regulator voltage drop RX operation or TX operation up to 4 dBm output power 50 mV VREGdropmax Regulator voltage drop at maximum internal current consumption TX mode with 12 dBm output power 300 mV IPDOWN Power-down current PWRMODE=0x00 0.5 868 MHz, bit rate 10 kbit/s 20 868 MHz, bit rate 600 kbit/s 21 433 MHz, bit rate 10 kbit/s 20 433 MHz, bit rate 600 kbit/s 21 868 MHz, bit rate 10 kbit/s 17 868 MHz, bit rate 600 kbit/s 18 433 MHz, bit rate 10 kbit/s 17 433 MHz, bit rate 600 kbit/s 18 868 MHz, 10 dBm 36 868 MHz, 4 dBm 23 868 MHz, 0 dBm 18 Current consumption TX 868 MHz, -12 dBm 11 VCO_I=001; REF_I=011; LOCURST=1 433 MHz, 12 dBm 36 433 MHz, 6dBm 23 433 MHz, 2 dBm 19 433 MHz, -8 dBm 12 Current consumption RX IRX-HS High sensitivity mode: VCO_I=001; REF_I=011 Current consumption RX IRX-LP ITX Version 1.6 Low power mode: VCO_I=001; REF_I=101 A mA mA mA Datasheet AX5051 11 12 Specifications Logic SYMBOL DESCRIPTION CONDITION MIN. TYP. MAX. UNIT DIGITAL INPUTS VT+ Schmitt trigger low to high threshold point 1.9 V VT- Schmitt trigger high to low threshold point 1.2 V VIL Input voltage, low VIH Input voltage, high 2.0 IL Input leakage current -10 0.8 V 10 A V DIGITAL OUTPUTS IOH Output Current, high VOH= 2.4V 4 mA IOL Output Current, low VOL= 0.4V 4 mA IOZ Tri-state output leakage current Version 1.6 -10 10 A Datasheet AX5051 Specifications 4.3. AC Characteristics Crystal Oscillator SYMBOL DESCRIPTION CONDITION fXTAL Crystal frequency Note 1 16 XTALOSCGM=0000 1 XTALOSCGM=0001 2 XTALOSCGM =0010 default 3 XTALOSCGM =0011 4 XTALOSCGM =0100 5 XTALOSCGM =0101 6 XTALOSCGM =0110 6.5 XTALOSCGM =0111 7 XTALOSCGM =1000 7.5 gmosc Transconductance oscillator Programmable tuning capacitors at pins CLK16N and CLK16P Cosc Cosc-lsb Programmable tuning capacitors, increment per LSB of XTALCAP fext External clock input RINosc Input DC impedance MIN. TYP. XTALOSCGM =1001 8 XTALOSCGM =1010 8.5 XTALOSCGM =1011 9 XTALOSCGM =1100 9.5 XTALOSCGM =1101 10 XTALOSCGM =1110 10.5 XTALOSCGM =1111 11 XTALCAP = 000000 default XTALCAP = 111111 Note 2 10 MAX. UNIT MHz mS 2 pF 33 pF 0.5 pF 16 MHz k Notes 1. 2. Tolerances and start-up times depend on the crystal used. Depending on the RF frequency and channel spacing the IC must be calibrated to the exact crystal frequency using the readings of the register TRKFREQ If an external clock is used, it should be input via an AC coupling at pin CLK16P with the oscillator powered up and XTALCAP=000000 Version 1.6 Datasheet AX5051 13 14 Specifications RF Frequency Generation Subsystem (Synthesizer) SYMBOL DESCRIPTION fREF Reference frequency frange_hi frange_low fRESO Frequency range CONDITION MIN. BANDSEL=0 800 BW2 Synthesizer loop bandwidth BW3 VCO current: VCOI=001 930 BANDSEL=1 400 470 1 100 Loop filter configuration: FLT=01 Charge pump current: PLLCPI=001 50 Charge pump current: PLLCPI=010 kHz 200 Loop filter configuration: FLT=10 Charge pump current: PLLCPI=010 500 Tset1 Loop filter configuration: FLT=01 Charge pump current: PLLCPI=010 15 Loop filter configuration: FLT=01 Charge pump current: PLLCPI=001 30 Loop filter configuration: FLT=11 Charge pump current: PLLCPI=010 7 Tset4 Loop filter configuration: FLT=10 Charge pump current: PLLCPI=010 3 Tstart1 Loop filter configuration: FLT=01 Charge pump current: PLLCPI=010 25 Loop filter configuration: FLT=01 Charge pump current: PLLCPI=001 50 Loop filter configuration: FLT=11 Charge pump current: PLLCPI=010 12 Loop filter configuration: FLT=10 Charge pump current: PLLCPI=010 5 Synthesizer settling time for 1MHz step as typically required for RX/TX switching Tset3 VCO current: VCO_I=001 Tstart2 Synthesizer start-up time if crystal oscillator and reference are running Tstart3 VCO current: VCO_I=001 Tstart4 PN8681 PN4331 PN8682 PN4332 Version 1.6 Synthesizer phase noise Loop filter configuration: FLT=01 Charge pump current: PLLCPI=010 VCO current: VCO_I=001 Synthesizer phase noise Loop filter configuration: FLT=01 Charge pump current: PLLCPI=001 VCO current: VCO_I=001 MHz Hz Loop filter configuration: FLT=01 Charge pump current: PLLCPI=010 Loop filter configuration: FLT=11 UNIT MHz BW4 Tset2 MAX. 16 Frequency resolution BW1 TYP. s s 868 MHz, 50 kHz from carrier -85 868 MHz, 100 kHz from carrier -90 868 MHz, 300 kHz from carrier -100 868 MHz, 2 MHz from carrier -110 433 MHz, 50 kHz from carrier -90 433 MHz, 100 kHz from carrier -95 433 MHz, 300 kHz from carrier -105 433 MHz, 2 MHz from carrier -115 868 MHz, 50 kHz from carrier -80 868 MHz, 100 kHz from carrier -90 868 MHz, 300 kHz from carrier -105 868 MHz, 2 MHz from carrier -115 433 MHz, 50 kHz from carrier -90 433 MHz, 100 kHz from carrier -95 433 MHz, 300 kHz from carrier -110 433 MHz, 2 MHz from carrier -122 dBc/Hz dBc/Hz Datasheet AX5051 Specifications Transmitter SYMBOL DESCRIPTION SBR Signal bit rate CONDITION MIN. TYP. ASK & PSK 38.4 600 FSK 38.4 200 TXRNG=0000 Transmitter power @ 868 MHz PTX868 LOCURST=1 PTX433 Transmitter power @ 433 MHz PTX868-harm2 Emission @ 2nd harmonic PTX868-harm3 Emission @ 3rd harmonic UNIT kbps -40 TXRNG=0001 -7.5 TXRNG=0010 -2 TXRNG=0011 1.5 TXRNG=0100 3.5 TXRNG=0101 5.5 TXRNG=0110 6.5 TXRNG=0111 7.5 TXRNG=1000 8.5 TXRNG=1001 9.5 TXRNG=1010 10 TXRNG=1011 10.5 TXRNG=1100 11 TXRNG=1101 11.5 TXRNG=1110 12 TXRNG=1111 12.5 TXRNG=1111 13 Note 1 MAX. -50 -55 dBm dBm dBc Notes 1. Additional low-pass filtering was applied to the antenna interface, see section 7: Application Information. Version 1.6 Datasheet AX5051 15 16 Specifications Receiver SYMBOL DESCRIPTION SBR Signal bit rate Input sensitivity at BER = 10-3 for 868 MHz operation IS868_HS High sensitivity mode: VCO_I=001; REF_I=011; RXIMIX=01 note 6 Input sensitivity at BER = 10-3 for 868 MHz operation IS868_LS Low power mode: VCO_I=001; REF_I=101; RXIMIX=01 note 6 IL Maximum input level CP1dB Input referred compression point IIP3 Input referred IP3 RSSIR RSSI control range RSSIS1 RSSI step size RSSIS2 RSSI step size Version 1.6 CONDITION MIN. TYP. MAX. ASK & PSK 38.4 600 FSK 38.4 200 ASK 38.4 kbps -103 ASK 50 kbps -102 ASK 100kbps -100 ASK 200 kbps -97 FSK 38.4 kbps -104 FSK 50 kbps -103 FSK 100kbps -101 FSK 200kbps -98 PSK 200 kbps -100 PSK 400 kbps -97 PSK 600 kbps -95 802.15.4 (ZigBee) -102 ASK 38.4 kbps -101 ASK 50 kbps -100 ASK 100kbps -98 ASK 200 kbps -95 FSK 38.4 kbps -102 FSK 50 kbps -101 FSK 100kbps -99 FSK 200kbps -95 PSK 200 kbps -98 PSK 400 kbps -95 PSK 600 kbps -93 802.15.4 (ZigBee) -100 kbps dBm dBm -20 2 tones separated by 100 kHz UNIT -35 dBm dBm -25 85 dB Before digital channel filter; calculated from register AGCCOUNTER 0.625 dB Behind digital channel filter; calculated from registers AGCCOUNTER, TRKAMPL 0.1 dB Datasheet AX5051 Specifications SYMBOL SEL868 DESCRIPTION CONDITION Adjacent channel suppression FSK 50 kbps, 18 Alternate channel suppression notes 1 & 2 19 Adjacent channel suppression FSK 100 kbps, 16 Alternate channel suppression notes 1 & 3 30 Adjacent channel suppression PSK 200 kbps, 17 Alternate channel suppression notes 1 & 4 28 Blocking at +/- 1MHz offset Blocking at - 2MHz offset BLK868 Blocking at +/- 10MHz offset Blocking at +/- 100MHz offset IMRR868 Image rejection MIN. TYP. MAX. UNIT dB dB dB 38 FSK 100 kbps, note 5 40 60 dB 82 30 Notes 1. 2. 3. 4. 5. 6. Interferer/Channel @ BER = 10-3, channel level is +10dB above the typical sensitivity, the interfering signal is a random data signal (except PSK200); both channel and interferer are modulated without shaping FSK 50 kbps: 868 MHz, 200 kHz channel spacing, 25 kHz deviation, programming as recommended in Programming Manual FSK 100 kbps: 868 MHz, 400kHz channel spacing, 50 kHz deviation , programming as recommended in Programming Manual PSK 200 kbps: 868 MHz, 400kHz channel spacing, programming as recommended in Programming Manual, interfering signal is a constant wave Channel/Blocker @ BER = 10-3, channel level is +10dB above the typical sensitivity, the blocker signal is a constant wave; channel signal is modulated without shaping, the image frequency lies 2 MHz above the wanted signal Sensitivities for the 433 MHz band are 1-2 dB better than those for the 868 MHz band Version 1.6 Datasheet AX5051 17 18 Specifications SPI Timing SYMBOL DESCRIPTION CONDITION MIN. TYP. MAX. Tss SEL falling edge to CLK rising edge 10 ns Tsh CLK falling edge to SEL rising edge 10 ns Tssd SEL falling edge to MISO driving 0 10 ns Tssz SEL rising edge to MISO high-Z 0 10 ns Ts MOSI setup time 10 ns Th MOSI hold time 10 ns Tco CLK falling edge to MISO output Tck CLK period Tcl Tch 10 Note 1 UNIT ns 50 ns CLK low duration 40 ns CLK high duration 40 ns Notes 1. For SPI access during power-down mode the period should be relaxed to 100ns. For a figure showing the SPI timing parameters see section 5.15: Serial Peripheral Interface (SPI). Version 1.6 Datasheet AX5051 Circuit Description 5. Circuit Description The AX5051 is a true single chip low-power CMOS transceiver primarily for use in SRD bands. The on-chip transceiver consists of a fully integrated RF front-end with modulator, and demodulator. Base band data processing is implemented in an advanced and flexible communication controller that enables user friendly communication via the SPI interface. AX5051 can be operated from a 2.3 V to 3.6 V power supply over a temperature range of -40oC to 85oC, it consumes 11 - 40 mA for transmitting, depending on the output power, 20 21 mA for receiving in high sensitivity mode and 17 - 18 mA for receiving in low power mode. The AX5051 features make it an ideal interface for integration into various battery powered SRD solutions such as ticketing or as transceiver for telemetric applications e.g. in sensors. As primary application, the transceiver is intended for UHF radio equipment in accordance with the European Telecommunication Standard Institute (ETSI) specification EN 300 220-1 and the US Federal Communications Commission (FCC) standard CFR47, part 15. The use of AX5051 in accordance to FCC Par 15.247, allows for improved range in the 915 MHz band. Additionally AX5051 is compatible with the low frequency standards of 802.15.4 (ZigBee). The AX5051 sends and receives data via the SPI port in frames. This standard operation mode is called Frame Mode. Pre and post ambles as well as checksums can be generated automatically. Interrupts control the data flow between a controller and the AX5051. The AX5051 behaves as a SPI slave interface. Configuration of the AX5051 is also done via the SPI interface. AX5051 supports any data rate from 38.4 kbps to 200 kbps for FSK and MSK and from 38.4 kbps for 600 kbps for ASK and PSK. To achieve optimum performance for specific data rates and modulation schemes several register settings to configure the AX5051 are necessary, they are outlined in the following, for details see the AX5051 Programming Manual. Spreading and despreading is possible on all data rates and modulation schemes. The net transfer rate is reduced by a factor of 15 in this case. For ZigBee either 600 or 300 kbps modes have to be chosen. The receiver supports multi-channel operation for all data rates and modulation schemes. Version 1.6 Datasheet AX5051 19 20 Circuit Description 5.1. Voltage Regulator The AX5051 uses an on-chip voltage regulator to create a stable supply voltage for the internal circuitry at pin VREG from the primary supply VDD_IO. All VDD pins of the device must be connected to VREG. The antenna pins ANTP and ANTN must be DC biased to VREG. The I/O level of the digital pins is VDD_IO. The voltage regulator requires a 1F low ESR capacitor at pin VREG. In power-down mode the voltage regulator typically outputs 1.7 V at VREG, if it is poweredup its output rises to typically 2.5 V. At device power-up the regulator is in power-down mode. The voltage regulator must be powered-up before receive or transmit operations can be initiated. This is handled automatically when programming the device modes via the PWRMODE register. Register VREG contains status bits that can be read to check if the regulated voltage is above 1.3 V or 2.3 V, sticky versions of the bits are provided that can be used to detect low power events (brown-out detection). 5.2. Crystal Oscillator The on-chip crystal oscillator allows the use of an inexpensive quartz crystal as the RF generation subsystem's timing reference. Although a wider range of crystal frequencies can be handled by the crystal oscillator circuit, it is recommended to use 16 MHz as reference frequency since this choice allows all the typical SRD band RF frequencies to be generated. The oscillator circuit is enabled by programming the PWRMODE register. At power-up it is not enabled. To adjust the circuit's characteristics to the quartz crystal being used without using additional external components, both the transconductance and the tuning capacitance of the crystal oscillator can be programmed. The transconductance is programmed via register bits XTALOSCGM[3:0] in register XTALOSC. The integrated programmable tuning capacitor bank makes it possible to connect the oscillator directly to pins CLK16N and CLK16P without the need for external capacitors. It is programmed using bits XTALCAP[5:0] in register XTALCAP. To synchronize the receiver frequency to a carrier signal, the oscillator frequency could be tuned using the capacitor bank however, the recommended method to implement frequency synchronization is to make use of the high resolution RF frequency generation subsystem together with the Automatic Frequency Control, both are described further down. Alternatively a single ended reference (TXCO, CXO) may be used. The CMOS levels should be applied to CLK16P via an AC coupling with the crystal oscillator enabled. Version 1.6 Datasheet AX5051 Circuit Description 5.3. SYSCLK Output The SYSCLK pin outputs the reference clock signal divided by a programmable integer. Divisions from 1 to 2048 are possible. For divider ratios > 1 the duty cycle is 50%. Bits SYSCLK[3:0] in the PINCFG1 register set the divider ratio. The SYSCLK output can be disabled. Outputting a frequency that is identical to the IF frequency (default 1 MHz) on the SYSCLK pin is not recommended during receive operation, since it requires extensive decoupling on the PCB to avoid interference. 5.4. Power-on-reset (POR) and RESET_N Input AX5051 has an integrated power-on-reset block. No external POR circuit or signal at the RESET_N pin is required, prior to POR the RESET_N pin is disabled. After POR the AX5051 can be reset in two ways: 1. By SPI accesses: the bit RST in the PWRMODE register is toggled. 2. Via the RESET_N pin: A low pulse is applied at the RESET_N pin. With the rising edge of RESET_N the device goes into its operational state. After POR or reset all registers are set to their default values. If the RESET_N pin is not used it must be tied to VDD_IO. 5.5. RF Frequency Generation Subsystem The RF frequency generation subsystem consists of a fully integrated synthesizer, which multiplies the reference frequency from the crystal oscillator to get the desired RF frequency. The advanced architecture of the synthesizer enables frequency resolutions of 1 Hz, as well as fast settling times of 5 - 50 s depending on the settings (see section 4.3: AC Characteristics). Fast settling times mean fast start-up and fast RX/TX switching, which enables low-power system design. For receive operation the RF frequency is fed to the mixer, for transmit operation to the power-amplifier. The frequency must be programmed to the desired carrier frequency. The RF frequency shift by the IF frequency that is required for RX operation, is automatically set when the receiver is activated and does not need to be programmed by the user. The default IF frequency is 1 MHz. It can be programmed to other values. Changing the IF frequency and thus the centre frequency of the digital channel filter can be used to adapt the blocking performance of the device to specific system requirements. The synthesizer loop bandwidth can be programmed, this serves three purposes: 1. Start-up time optimisation, start-up is faster for higher synthesizer loop bandwidths 2. TX spectrum optimisation, phase-noise at 300 kHz to 1 MHz distance from the carrier improves with lower synthesizer loop bandwidths Version 1.6 Datasheet AX5051 21 22 Circuit Description 3. Adaptation of the bandwidth to the data-rate. For transmission of FSK and MSK it is required that the synthesizer bandwidth must be in the order of the data-rate. VCO An on-chip VCO converts the control voltage generated by the charge pump and loop filter into an output frequency. This frequency is used for transmit as well as for receive operation. The frequency can be programmed in 1 Hz steps in the FREQ registers. For operation in the 433 MHz band, the BANDSEL bit in the PLLLOOP register must be programmed. VCO Auto-Ranging The AX5051 has an integrated auto-ranging function, which allows to set the correct VCO range for specific frequency generation subsystem settings automatically. Typically it has to be executed after power-up. The function is initiated by setting the RNG_START bit in the PLLRANGING register. The bit is readable and a 0 indicates the end of the ranging process. The RNGERR bit indicates the correct execution of the auto-ranging. Loop Filter and Charge Pump The AX5051 internal loop filter configuration together with the charge pump current sets the synthesizer loop band width. The loop-filter has three configurations that can be programmed via the register bits FLT[1:0] in register PLLLOOP, the charge pump current can be programmed using register bits PLLCPI[1:0] also in register PLLLOOP. Synthesizer bandwidths are typically 50 - 500 kHz depending on the PLLLOOP settings, for details see the section 4.3: AC Characteristics. Registers Register PLLLOOP Bits Purpose FLT[1:0] Synthesizer loop filter bandwidth, recommended usage is to increase the bandwidth for faster settling time, bandwidth increases of factor 2 and 5 are possible. PLLCPI[2:0] Synthesizer charge pump current, recommended usage is to decrease the bandwidth (and improve the phase-noise) for low data-rate transmissions. BANDSEL Switches between 868 MHz/915 MHz and 433 MHz bands FREQ Programming of the carrier frequency IFFREQHI, IFFREQLO Programming of the IF frequency PLLRANGING Initiate VCO auto-ranging and check results Version 1.6 Datasheet AX5051 Circuit Description 5.6. RF Input and Output Stage (ANTP/ANTN) The AX5051 uses fully differential antenna pins. RX/TX switching is handled internally, an external RX/TX switch is not required. LNA The LNA amplifies the differential RF signal from the antenna and buffers it to drive the I/Q mixer. An external matching network is used to adapt the antenna impedance to the IC impedance. A DC feed to the regulated supply voltage VREG must be provided at the antenna pins. For recommendations, see section 7: Application Information. I/Q Mixer The RF signal from the LNA is mixed down to an IF of typically 1 MHz. I- and Q-IF signals are buffered for the analog IF filter. PA In TX mode the PA drives the signal generated by the frequency generation subsystem out to the differential antenna terminals. The output power of the PA is programmed via bits TXRNG[3:0] in the register TXPWR. Output power as well as harmonic content will depend on the external impedance seen by the PA, recommendations are given in the section 7: Application Information. 5.7. Analog IF Filter The mixer is followed by a complex band-pass IF filter, which suppresses the down-mixed image while the wanted signal is amplified. The centre frequency of the filter is 1 MHz, with a passband width of 1 MHz. The RF frequency generation subsystem must be programmed in such a way that for all possible modulation schemes the IF frequency spectrum fits into the passband of the analog filter. 5.8. Digital IF Channel Filter and Demodulator The digital IF channel filter and the demodulator extract the data bit-stream from the incoming IF signal. They must be programmed to match the modulation scheme as well as the data-rate. Inaccurate programming will lead to loss of sensitivity. The channel filter offers bandwidths of 40 kHz up to 600 kHz. For detailed instructions how to program the digital channel filter and the demodulator see the AX5051 Programming Manual, an overview of the registers involved is given in the following table. The register setups typically must be done once at power-up of the device. Version 1.6 Datasheet AX5051 23 24 Circuit Description Registers Register Remarks CICDEC This register programs the bandwidth of the digital channel filter. DATARATEHI, DATARATELO These registers specify the receiver bit rate, relative to the channel filter bandwidth. TMGGAINHI, TMGGAINLO These registers specify the aggressiveness of the receiver bit timing recovery. More aggressive settings allow the receiver to synchronize with shorter preambles, at the expense of more timing jitter and thus a higher bit error rate at a given signal-to-noise ratio. MODULATION This register selects the modulation to be used by the transmitter and the receiver, i.e. whether ASK, PSK , FSK, MSK or OQPSK should be used. PHASEGAIN, FREQGAIN, FREQGAIN2, AMPLGAIN These registers control the bandwidth of the phase, frequency offset and amplitude tracking loops. Recommended settings are provided in the Programming Manual. AGCATTACK, AGCDECAY These registers control the AGC (automatic gain control) loop slopes, and thus the speed of gain adjustments. The faster the bit-rate, the faster the AGC loop should be. Recommended settings are provided in the Programming Manual. TXRATE These registers control the bit rate of the transmitter. FSKDEV These registers control the frequency deviation of the transmitter in FSK mode. The receiver does not explicitly need to know the frequency deviation, only the channel filter bandwidth has to be set wide enough for the complete modulation to pass. 5.9. Encoder The encoder is located between the Framing Unit, the Demodulator and the Modulator. It can optionally transform the bit-stream in the following ways: * It can invert the bit stream. * It can perform differential encoding. This means that a zero is transmitted as no change in the level, and a one is transmitted as a change in the level. Differential encoding is useful for PSK, because PSK transmissions can be received either as transmitted or inverted, due to the uncertainty of the initial phase. Differential encoding / decoding removes this uncertainty. * It can perform Manchester encoding. Manchester encoding ensures that the modulation has no DC content and enough transitions (changes from 0 to 1 and from 1 to 0) for the demodulator bit timing recovery to function correctly, but does so at a doubling of the data rate. * It can perform Spectral Shaping. Spectral Shaping removes DC content of the bit stream, ensures transitions for the demodulator bit timing recovery, and makes sure that the transmitted spectrum does not have discrete lines even if the transmitted data is cyclic. It does so without adding additional bits, i.e. without changing the data rate. Spectral Shaping uses a self synchronizing feedback shift register. The encoder is programmed using the register ENCODING, details and recommendations on usage are given in the AX5051 Programming Manual. Version 1.6 Datasheet AX5051 Circuit Description 5.10. Framing and FIFO Most radio systems today group data into packets. The framing unit is responsible for converting these packets into a bit-stream suitable for the modulator, and to extract packets from the continuous bit-stream arriving from the demodulator. The Framing unit supports four different modes: * HDLC * Raw * Raw with Preamble Match * 802.15.4 compliant The micro-controller communicates with the framing unit through a 4 level x 10 bit FIFO. The FIFO decouples micro-controller timing from the radio (modulator and demodulator) timing. The bottom 8 bits of the FIFO contain transmit or receive data. The top 2 bit are used to convey meta information in HDLC and 802.15.4 modes. They are unused in Raw and Raw with Preamble Match modes. The meta information consists of packet begin / end information and the result of CRC checks. The AX5051 contains one FIFO. Its direction is switched depending on whether transmit or receive mode is selected. The FIFO can be operated in polled or interrupt driven modes. In polled mode, the microcontroller must periodically read the FIFO status register or the FIFO count register to determine whether the FIFO needs servicing. In interrupt mode EMPTY, NOT EMPTY, FULL, NOT FULL and programmable level interrupts are provided. The AX5051 signals interrupts by asserting (driving high) its IRQ line. The interrupt line is level triggered, active high. Interrupts are acknowledged by removing the cause for the interrupt, i.e. by emptying or filling the FIFO. Basic FIFO status (EMPTY, FULL, Overrun, Underrun, and the top two bits of the top FIFO word) are also provided during each SPI access on MISO while the micro-controller shifts out the register address on MOSI. See the SPI interface section for details. This feature significantly reduces the number of SPI accesses necessary during transmit and receive. Version 1.6 Datasheet AX5051 25 26 Circuit Description HDLC Mode Note: HDLC mode follows High-Level Data Link Control (HDLC, ISO 13239) protocol. HDLC Mode is the main framing mode of the AX5051. In this mode, the AX5051 performs automatic packet delimiting, and optional packet correctness check by inserting and checking a cyclic redundancy check (CRC) field. The packet structure is given in the following table. Flag Address Control Information FCS (Optional Flag) 8 bit 8 bit 8 or 16 bit Variable length, 0 or more bits in multiples of 8 16 / 32 bit 8 bit HDLC packets are delimited with flag sequences of content 0x7E. In AX5051 the meaning of address and control is user defined. The Frame Check Sequence (FCS) can be programmed to be CRC-CCITT, CRC-16 or CRC-32. The receiver checks the CRC, the result can be retrieved from the FIFO, the CRC is appended to the received data. For details on implementing a HDLC communication see the AX5051 Programming Manual. RAW Mode In Raw mode, the AX5051 does not perform any packet delimiting or byte synchronization. It simply serialises transmit bytes and de-serializes the received bit-stream and groups it into bytes. This mode is ideal for implementing legacy protocols in software. RAW Mode with Preamble Match Raw mode with preamble match is similar to raw mode. In this mode, however, the receiver does not receive anything until it detects a user programmable bit pattern (called the preamble) in the receive bit-stream. When it detects the preamble, it aligns the deserialization to it. The preamble can be between 4 and 32 bits long. Version 1.6 Datasheet AX5051 Circuit Description 802.15.4 (ZigBee) 802.15.4 uses binary phase shift keying (PSK) with 300 kbit/s (868 MHz band) or 600 kbit/s (915 MHz band) on the radio. The usable bit rate is only a 15th of the radio bit rate, however. A spreading function in the transmitter expands the user bit rate by a factor of 15, to make the transmission more robust. The despreader function of the receiver undoes that. In 802.15.4 mode, the AX5051 framing unit performs the spreading and despreading function according to the 802.15.4 specification. In receive mode, the framing unit will also automatically search for the 802.15.4 preamble, meaning that no interrupts will have to be serviced by the micro-controller until a packet start is detected. 5.11. RX AGC and RSSI AX5051 features two receiver signal strength indicators (RSSI): 1. RSSI before the digital IF channel filter. The gain of the receiver is adjusted in order to keep the analog IF filter output level inside the working range of the ADC and demodulator. The register AGCCOUNTER contains the current value of the AGC and can be used as an RSSI. The step size of this RSSI is 0.625 dB. The value can be used as soon as the RF frequency generation sub-system has been programmed. 2. RSSI behind the digital IF channel filter. The demodulator also provides amplitude information in the TRK_AMPLITUDE register. By combining both the AGCCOUNTER and the TRK_AMPLITUDE registers, a high resolution (better than 0.1dB) RSSI value can be computed at the expense of a few arithmetic operations on the micro-controller. Formulas for this computation can be found in the AX5051 Programming Manual. Version 1.6 Datasheet AX5051 27 28 Circuit Description 5.12. Modulator Depending on the transmitter settings the modulator generates various inputs for the PA: Modulation Bit = 0 Bit = 1 Main Lobe Bandwidth Max. Bitrate ASK PA off PA on BW=BITRATE 600kBit/s FSK / MSK f=-fdeviation f=+fdeviation BW=(1+h) BITRATE 200kBit/s PSK =0 =180 BW=BITRATE 600kBit/s 0 0 h = modulation index. It is the ratio of the deviation compared to the bit-rate; fdeviation = 0.5hBITRATE, AX5051 can demodulate signals with h < 32. ASK = amplitude shift keying FSK = frequency shift keying MSK = minimum shift keying; MSK is a special case of FSK, where h = 0.5, and therefore fdeviation = 0.25BITRATE; the advantage of MSK over FSK is that it can be demodulated more robustly. PSK = phase shift keying OQPSK = offset quadrature shift keying. The AX5051 supports OQPSK. However, unless compatibility to an existing system is required, MSK should be preferred. All modulation schemes are binary. 5.13. Automatic Frequency Control (AFC) The AX5051 has a frequency tracking register TRKFREQ to synchronize the receiver frequency to a carrier signal. For AFC adjustment, the frequency offset can be computed with the following formula: f = TRKFREQ BITRATEx FSKMUL . 216 FSKMUL is the FSK oversampling factor, it depends on the FSK bit rate and deviation used. To determine it for a specific case, see the AX5051 Programming Manual. For modulations other than FSK, FSKMUL=1. Version 1.6 Datasheet AX5051 Circuit Description 5.14. PWRMODE Register The PWRMODE register controls, which parts of the chip are operating. PWRMODE register Name POWERDOWN All digital and analog functions, except the register file, are disabled. The core supply voltage is reduced to conserve leakage power. SPI registers are still accessible, but at a slower speed. 0.5 A 0000 200 A 0100 VREGON All digital and analog functions, except the register file, are disabled. The core voltage, however is at its nominal value for operation, and all SPI registers are accessible at the maximum speed. 0101 STANDBY The crystal oscillator is powered on; receiver and transmitter are off. 650 A SYNTHRX The synthesizer is running on the receive frequency. Transmitter and receiver are still off. This mode is used to let the synthesizer settle on the correct frequency for receive. 11 mA 1000 1001 FULLRX Synthesizer and receiver are running. 1100 SYNTHTX The synthesizer is running on the transmit frequency. Transmitter and receiver are still off. This mode is used to let the synthesizer settle on the correct frequency for transmit. FULLTX Synthesizer and transmitter are running. Do not switch into this mode before the synthesizer has completely settled on the transmit frequency (in SYNTHTX mode), otherwise spurious spectral transmissions will occur. 1101 Version 1.6 Description Typical Idd 17 - 20 mA 10 mA 11 - 40 mA Datasheet AX5051 29 30 Circuit Description A typical PWRMODE sequence for a transmit session : Step PWRMODE Remarks 1 POWERDOWN 2 STANDBY The settling time is dominated by the crystal used, typical value 3ms. 3 SYNTHTX The synthesizer settling time is 5 - 50 s depending on settings, see section AC Characteristics 4 FULLTX Data transmission 5 SYNTHTX This step must be programmed after FULLTX mode, or the device will not enter POWERDOWN or STANDBY mode. 6 POWERDOWN A typical PWRMODE sequence for a receive session : Step PWRMODE[3:0] Remarks 1 POWERDOWN 2 STANDBY The settling time is dominated by the crystal used, typical value 3ms 3 SYNTHRX The synthesizer settling time is 5 - 50 s depending on settings, see section AC Characteristics 4 FULLRX Data reception 5 POWERDOWN Version 1.6 Datasheet AX5051 Circuit Description 5.15. Serial Peripheral Interface (SPI) The AX5051 can be programmed via a four wire serial interface according SPI using the pins CLK, MOSI, MISO and SEL. Registers for setting up the AX5051 are programmed via the serial peripheral interface in all device modes. When the interface signal SEL is pulled low, a 16 bit configuration data stream is expected on the input signal pin MOSI, which is interpreted as D0...D7, A0...A6, R_N/W. Data read from the interface appears on MISO. Figure 3 shows a write/read access to the interface. The data stream is built of an address byte including read/write information and a data byte. Depending on the R_N/W bit and address bits A[6..0], data D[7..0] can be written via MOSI or read at the pin MISO. R_N/W = 0 means read mode, R_N/W = 1 means write mode. The read sequence starts with 7 bits of status information S[6..0] followed by 8 data bits. The status bits contain the following information: S6 S5 S4 S3 S2 S1 S0 PLL LOCK FIFO OVER FIFO UNDER FIFO FULL FIFO EMPTY FIFOSTAT(1) FIFOSTAT(0) SPI Timing Tss Tck TchTcl Ts Th A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 S6 S5 S4 S3 S2 S1 S0 D7 D6 D5 D4 D3 D2 D1 D0 Tsh SS SCK MOSI R/W MISO Tssd Tco Tssz Figure 3 Serial peripheral interface timing Version 1.6 Datasheet AX5051 31 32 Register Bank Description 6. Register Bank Description This section describes the bits of the register bank in detail. The registers are grouped by functional block to facilitate programming. No checks are made whether the programmed combination of bits makes sense! Bit 0 is always the LSB. Note Whole registers or register bits marked as reserved should be kept at their default values. Note All addresses not documented here must not be accessed, neither in reading nor in writing. Version 1.6 Datasheet AX5051 Register Bank Description 6.1. Control Register Map Addr Name Dir Reset Bit 7 6 5 Description 4 3 2 1 0 Revision & Interface Probing 0 REVISION 1 SCRATCH R SILICONREV(7:0) 00010100 RW 11000101 Silicon Revision SCRATCH(7:0) Scratch Register Operating Mode 2 PWRMODE RW 0---0000 RST - - - PWRMODE(3:0) Power Mode RW ----0010 - - - - XTALOSCGM(3:0) GM of Crystal Oscillator FIFOSTAT(1:0) FIFO OVER FIFO UNDER FIFO EMPTY FIFO Control Crystal Oscillator, Part 1 3 XTALOSC FIFO, Part 1 4 FIFOCTRL RW ------11 5 FIFODATA RW -------- FIFO FULL FIFOCMD(1:0) FIFODATA(7:0) FIFO Data Interrupt Control 6 IRQMASK 7 IRQREQUEST RW --000000 R - - IRQMASK(5:0) IRQ Mask -------- - - IRQREQUEST(5:0) - - IRQ Request Interface & Pin Control 8 IFMODE RW ----0011 0C PINCFG1 RW 11111000 0D PINCFG2 RW 00000000 Version 1.6 - - IFMODE(3:0) Interface Mode Must be set to 0000 reserved IRQZ reserved SYSCLK(3:0) Pin Configuration 1 TST_PINS IRQE reserved reserved IRQI reserved Pin Configuration 2 TST_PINS(1:0) must be set to 11 Datasheet AX5051 33 34 Register Bank Description 0E PINCFG3 0F IRQINVERSION R -------- - - RW --000000 - - - SYSCLKR reserved IRQR reserved IRQINVERSION(5:0) Pin Configuration 3 IRQ Inversion Modulation & Framing 10 MODULATION RW -0000010 - 11 ENCODING RW ----0010 - - 12 FRAMING RW -0000000 FRMRX HSUPP 14 CRCINIT3 RW 11111111 CRCINIT(31:24) CRC Initialization Data or Preamble 15 CRCINIT2 RW 11111111 CRCINIT(23:16) CRC Initialization Data or Preamble 16 CRCINIT1 RW 11111111 CRCINIT(15:8) CRC Initialization Data or Preamble 17 CRCINIT0 RW 11111111 CRCINIT(7:0) CRC Initialization Data or Preamble MODULATION(6:0) - - ENC MANCH CRCMODE(1:0) Modulation ENC SCRAM ENC DIFF FRMMODE(2:0) ENC INV Encoder/Decoder Settings FABORT Framing settings Voltage Regulator 1B VREG R -------- - - - - SSDS SSREG SDS SREG Voltage Regulator Status Synthesizer 20 FREQ3 RW 00111001 FREQ(31:24) Synthesizer Frequency 21 FREQ2 RW 00110100 FREQ(23:16) Synthesizer Frequency 22 FREQ1 RW 11001100 FREQ(15:8) Synthesizer Frequency 23 FREQ0 RW 11001101 FREQ(7:0) Synthesizer Frequency 25 FSKDEV2 RW 00000010 FSKDEV(23:16) FSK Frequency Deviation 26 FSKDEV1 RW 01100110 FSKDEV(15:8) FSK Frequency Deviation 27 FSKDEV0 RW 01100110 FSKDEV(7:0) FSK Frequency Deviation 28 IFFREQHI RW 00100000 IFFREQ(15:8) 2nd LO / IF Frequency 29 IFFREQLO RW 00000000 IFFREQ(7:0) 2nd LO / IF Frequency 2C PLLLOOP RW -0011101 reserved BANDSEL 2D PLLRANGING RW 00001000 STICKY LOCK PLL LOCK RNGERR Version 1.6 - PLLCPI(2:0) RNG START FLT(1:0) VCOR(3:0) Synthesizer Loop Filter Settings Synthesizer VCO Auto-Ranging Datasheet AX5051 Register Bank Description Transmitter 30 TXPWR RW ----1000 31 TXRATEHI RW 00001001 TXRATE(23:16) Transmitter Bitrate 32 TXRATEMID RW 10011001 TXRATE(15:8) Transmitter Bitrate 33 TXRATELO RW 10011010 TXRATE(7:0) Transmitter Bitrate 34 MODMISC RW ------11 - - - - TXRNG(3:0) - Transmit Power reserved PTTCLK GATE - - - - - Misc RF Flags -------- - - - - - FIFOCOUNT(2:0) FIFO Fill state FIFOTHRESH(2:0) FIFO Threshold FIFO, Part 2 35 FIFOCOUNT 36 FIFOTHRESH RW -----000 - - - - - 37 FIFOCONTROL2 RW 0-----00 CLEAR - - - - 3A AGCATTACK RW 00010110 - - - AGCATTACK(4:0) AGC Attack 3B AGCDECAY RW 0-010011 reserved - reserved AGCDECAY(4:0) AGC Decay 3C AGCCOUNTER R -------- 3D CICSHIFT R --000100 - - 3F CICDEC RW 00000100 - - 40 DATARATEHI RW 00011010 DATARATE(15:8) Datarate 41 DATARATELO RW 10101011 DATARATE(7:0) Datarate 42 TMGGAINHI RW 00000000 TIMINGGAIN(15:8) Timing Gain 43 TMGGAINLO RW 11010101 TIMINGGAIN(7:0) Timing Gain 44 PHASEGAIN RW 00--0011 45 FREQGAIN RW 00001010 46 FREQGAIN2 RW ----1010 - - - 47 AMPLGAIN RW ---00110 - - - 48 TRKAMPLHI R -------- TRKAMPL(15:8) Amplitude Tracking 49 TRKAMPLLO R -------- TRKAMPL(7:0) Amplitude Tracking 4A TRKPHASEHI R -------- R - STOPONERR(1:0) Additional FIFO control Receiver Version 1.6 AGCCOUNTER(7:0) reseved CICSHIFT(4:0) CICDEC(5:0) reserved - - - - CIC Shift Factor CIC Decimation Factor PHASEGAIN(3:0) Phase Gain FREQGAIN(3:0) Frequency Gain - FREQGAIN2(3:0) Frequency Gain 2 reserved AMPLGAIN(3:0) Amplitude Gain reserved - AGC Current Value - TRKPHASE(11:8) Phase Tracking Datasheet AX5051 35 36 Register Bank Description 4B TRKPHASELO R -------- TRKPHASE(7:0) Phase Tracking 4C TRKFREQHI R -------- TRKFREQ(15:8) Frequency Tracking 4D TRKFREQLO R -------- TRKFREQ(7:0) Frequency Tracking Crystal Oscillator, Part 2 XTALCAP RW --000000 - - 72 PLLVCOI RW --000100 - - 7A LOCURST RW 00110000 LOCURST 7C REF RW --100011 - - 7D RXMISC RW --110110 - - 4F Crystal oscillator tuning capacitance XTALCAP(5:0) Misc Version 1.6 reserved VCO_I[2:0] LOCURST Must be set to 1 reserved reserved reserved Synthesizer VCO current Must be set to 001 REF_I[2:0] RXIMIX(1:0) Reference adjust Misc RF settings RXIMIX(1:0) must be set to 01 Datasheet AX5051 Application Information Application Information Typical Application Diagram From Power Supply 7.1. 1F NC GND NC VREG VDD CLK16P CLK16N ANTENNA NC NC VDD GND ANTP TST3 MISO VDD CLK SEL MOSI GND SYSCLK ANTN NC TST1 GND IRQ AX5051 TST2 GND RESET_N VREG VDD_IO TO/FROM MICRO-CONTROLLER 7. GND Figure 4 Typical application diagram It is mandatory to add 1F (low ESR) between VREG and GND. Decoupling capacitors are not all drawn. It is recommended to add 100nF decoupling capacitor for every VDD and VDD_IO pin. In order to reduce noise on the antenna inputs it is recommended to add 27 pF on the VDD pins close to the antenna interface. Version 1.6 Datasheet AX5051 37 38 Application Information 7.2. Antenna Interface Circuitry The ANTP and ANTN pins provide RF input to the LNA when AX5051 is in receive mode, and RF output from the PA when AX5051 is in transmit mode. A small antenna can be connected with an optional translation network. The network must provide DC power to the PA and LNA. A biasing to VREG is necessary. Beside biasing and impedance matching, the proposed networks also provide low pass filtering to limit spurious emission. Single-Ended Antenna Interface VDD L1 L3 C3 IC Antenna C1 Pins L6 50 singleended equipment or antenna CB CA C2 L4 C6 LB C5 L2 L5 VDD C4 Figure 5 Structure of the antenna interface to 50 single-ended equipment or antenna Frequency Band L1=L2 [nH] C1 [pF] L3=L4 [nH] C2 [pF] C3=C5 [pF] L5=L6 [nH] LB [nH] CA=CB [pF] C4=C6 [pF] 868 / 915 MHz 18 2.2 12 2.2 1.8 18 6.2 8.2 220 433 MHz 33 3 33 3.3 3.3 39 12 18 220 Version 1.6 Datasheet AX5051 Application Information Dipole Antenna Interface VDD L1 L3 IC Antenna Pins dipole antenna C2 C1 L4 L2 VDD Figure 6 Structure of the antenna interface to a dipole antenna Frequency Band 7.3. L1=L2 [nH] C1 [pF] L3=L4 [nH] C2 [pF] 868 / 915 MHz 18 3.9 6.8 3.3 433 MHz 33 8 15 6.8 Voltage Regulator The AX5051 has an integrated voltage regulator which generates a stable supply voltage VREG from the voltage applied at VDD_IO. Use VREG to supply all the VDD supply pins. Version 1.6 Datasheet AX5051 39 40 QFN28 Package Information 8. 8.1. QFN28 Package Information Package Outline QFN28 AXSEM AX5051-1 YYWWXX Notes 1. 2. 3. 4. JEDEC ref MO-220 All dimensions are in millimeters Pin 1 is identified by chamfer on corner of exposed die pad. Datum C and the seating plane are defined by the flat surface of the metallised terminal 5. Dimension `e' represent the terminal pitch 6. Dimension b applies to metallised terminal and is measured 0.25 to 0.30mm from terminal tip. 7. Dimension L1 represents terminal pull back from package edge. There terminal pull back esists, only upper half of lead is visible on package edge du to half etching of leadframe. 8. Package surface shall be matte finish, Ra 1.6-2.2 9. Package warp shall be 0.050 maximum 10. Leadframe material is copper A194 11. Coplanarity applies to the exposed pad as well as the terminal 12. YYWWXX is the packaging lot code Version 1.6 Datasheet AX5051 QFN28 Package Information 8.2. QFN28 Soldering Profile Preheat Reflow Cooling tp Tp Temperature TL tL TsMAX TsMIN ts 25C t25 to Peak Time Profile Feature Pb-Free Process Average Ramp-Up Rate 3 C/sec max. Preheat Preheat Temperature Min TsMIN 150C Temperature Max TsMAX 200C Time (TsMIN to TsMAX) ts 60 - 180 sec Time 25C to Peak Temperature T25 to Peak 8 min max. TL 217C Time over Liquidus Temperature tL 60 - 150 sec Peak Temperature tp 260C Time within 5C of actual Peak Temperature Tp 20 - 40 sec Reflow Phase Liquidus Temperature Cooling Phase Ramp-down rate 6C/sec max. Notes: All temperatures refer to the top side of the package, measured on the package body surface. Version 1.6 Datasheet AX5051 41 42 QFN28 Package Information 8.3. 1. QFN28 Recommended Pad Layout PCB land and solder masking recommendations are shown in Figure 7. A= Clearance from PCB thermal pad to solder mask opening, 0.0635 mm minimum B = Clearance from edge of PCB thermal pad to PCB land, 0.2 mm minimum C = Clearance from PCB land edge to solder mask opening to be as tight as possible to ensure that some solder mask remains between PCB pads D = PCB land length = QFN solder pad length + 0.1mm E = PCB land width = QFN solder pad width + 0.1 mm Figure 7: PCB land and solder mask recommendations 2. Thermal vias should be used on the PCB thermal pad (middle ground pad) to improve thermal conductivity from the device to a copper ground plane area on the reverse side of the printed circuit board. The number of vias depends on the package thermal requirements, as determined by thermal simulation or actual testing. 3. Increasing the number of vias through the printed circuit board will improve the thermal conductivity to the reverse side ground plane and external heat sink. In general, adding more metal through the PC board under the IC will improve operational heat transfer, but will require careful attention to uniform heating of the board during assembly. 8.4. Assembly Process Stencil Design & Solder Paste Application 1. Stainless steel stencils are recommended for solder paste application. 2. A stencil thickness of 0.125 - 0.150 mm (5 - 6 mils) is recommended for screening. 3. For the PCB thermal pad, solder paste should be printed on the PCB by designing a stencil with an array of smaller openings that sum to 50% of the QFN exposed pad area. Solder paste should be applied through an array of squares (or circles) as shown in Figure 8. 4. The aperture opening for the signal pads should be between 50-80% of the QFN pad area as shown in Figure 9. 5. Optionally, for better solder paste release, the aperture walls should be trapezoidal and the corners rounded. Version 1.6 Datasheet AX5051 QFN28 Package Information 6. The fine pitch of the IC leads requires accurate alignment of the stencil and the printed circuit board. The stencil and printed circuit assembly should be aligned to within + 1 mil prior to application of the solder paste. 7. No-clean flux is recommended since flux from underneath the thermal pad will be difficult to clean if water-soluble flux is used. Figure 8: Solder paste application on exposed pad Minimum 50% coverage 62% coverage Maximum 80% coverage Figure 9: Solder paste application on pins Version 1.6 Datasheet AX5051 43 44 Life Support Applications 9. Life Support Applications This product is not designed for use in life support appliances, devices, or in systems where malfunction of this product can reasonably be expected to result in personal injury. AXSEM customers using or selling this product for use in such applications do so at their own risk and agree to fully indemnify AXSEM for any damages resulting from such improper use or sale. Version 1.6 Datasheet AX5051 Contact Information 10. Contact Information AXSEM AG Oskar-Bider-Strasse 1 CH-8600 Dubendorf SWITZERLAND Phone +41 44 882 17 07 Fax +41 44 882 17 09 Email sales@axsem.com www.axsem.com For further product related or sales information please visit our website or contact your local representative. The specifications in this document are subject to change at AXSEM's discretion. AXSEM assumes no responsibility for any claims or damages arising out of the use of this document, or from the use of products based on this document, including but not limited to claims or damages based on infringement of patents, copyrights or other intellectual property rights. AXSEM makes no warranties, either expressed or implied with respect to the information and specifications contained in this document. AXSEM does not support any applications in connection with life support and commercial aircraft. Performance characteristics listed in this document are estimates only and do not constitute a warranty or guarantee of product performance. The copying, distribution and utilization of this document as well as the communication of its contents to others without expressed authorization is prohibited. Offenders will be held liable for the payment of damages. All rights reserved. Copyright (c) 2007 AXSEM AG Version 1.6 Datasheet AX5051 45