© 2000–2011 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. PowerPC is
a trademark of IBM Corp. and is used under license. All other trademarks are the property of their respective owners.
DS083 (v5.0) June 21, 2011 www.xilinx.com 1
Product Specification
Product Not Recommended For New Designs
Module 1:
Introduction and Overview
10 pages
• Summary of Features
• General Description
• Architecture
• IP Core and Reference Support
• Device/Package Combinations and Maximum I/O
• Ordering Information
Module 2:
Functional Description
60 pages
• Functional Description: RocketIO™ X Multi-Gigabit
Transceiver
• Functional Description: RocketIO Multi-Gigabit
Transceiver
• Functional Description: Processor Block
• Functional Description: PowerPC™ 405 Core
• Functional Description: FPGA
- Input/Output Blocks (IOBs)
- Digitally Controlled Impedance (DCI)
- On-Chip Differential Termination
- Configurable Logic Blocks (CLBs)
- 3-State Buffers
- CLB/Slice Configurations
- 18-Kb Block SelectRAM™ Resources
- 18-Bit x 18-Bit Multipliers
- Global Clock Multiplexer Buffers
- Digital Clock Manager (DCM)
•Routing
• Configuration
Module 3:
DC and Switching Characteristics
59 pages
• Electrical Characteristics
• Performance Characteristics
• Switching Characteristics
• Pin-to-Pin Output Parameter Guidelines
• Pin-to-Pin Input Parameter Guidelines
• DCM Timing Parameters
• Source-Synchronous Switching Characteristics
Module 4:
Pinout Information
302 pages
• Pin Definitions
•Pinout Tables
- FG256/FGG256 Wire-Bond Fine-Pitch BGA Package
- FG456/FGG456 Wire-Bond Fine-Pitch BGA Package
- FG676/FGG676 Wire-Bond Fine-Pitch BGA Package
- FF672 Flip-Chip Fine-Pitch BGA Package
- FF896 Flip-Chip Fine-Pitch BGA Package
- FF1148 Flip-Chip Fine-Pitch BGA Package
- FF1152 Flip-Chip Fine-Pitch BGA Package
- FF1517 Flip-Chip Fine-Pitch BGA Package
- FF1696 Flip-Chip Fine-Pitch BGA Package
- FF1704 Flip-Chip Fine-Pitch BGA Package
IMPORTANT NOTE: Page, figure, and table numbers begin at 1 for each module, and each module has its own Revision
History at the end. Use the PDF "Bookmarks" pane for easy navigation in this volume.
1Virtex-II Pro and Virtex-II Pro X Platform FPGAs:
Complete Data Sheet
DS083 (v5.0) June 21, 2011 0Product Specification
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© 2000–2011 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. PowerPC is
a trademark of IBM Corp. and is used under license. All other trademarks are the property of their respective owners.
DS083 (v5.0) June 21, 2011 www.xilinx.com Module 1 of 4
Product Specification 1
Product Not Recommended For New Designs
Summary of Virtex-II Pro™ / Virtex-II Pro X Features
• High-Performance Platform FPGA Solution, Including
- Up to twenty RocketIO™ or RocketIO X embedded
Multi-Gigabit Transceivers (MGTs)
- Up to two IBM PowerPC™ RISC processor blocks
• Based on Virtex-II™ Platform FPGA Technology
- Flexible logic resources
- SRAM-based in-system configuration
- Active Interconnect technology
- SelectRAM™+ memory hierarchy
- Dedicated 18-bit x 18-bit multiplier blocks
- High-performance clock management circuitry
- SelectI/O™-Ultra technology
- XCITE Digitally Controlled Impedance (DCI) I/O
Virtex-II Pro / Virtex-II Pro X family members and resources
are shown in Table 1.
RocketIO X Transceiver Features (XC2VPX20 and XC2VPX70 Only)
• Variable-Speed Full-Duplex Transceiver (XC2VPX20)
Allowing 2.488 Gb/s to 6.25 Gb/s Baud Transfer Rates.
- Includes specific baud rates used by various
standards, as listed in Table 4, Module 2.
• Fixed-Speed Full-Duplex Tranceiver (XC2VPX70)
Operating at 4.25 Gb/s Baud Transfer Rate.
• Eight or Twenty Transceiver Modules on an FPGA,
Depending upon Device
• Monolithic Clock Synthesis and Clock Recovery
- Eliminates the need for external components
• Automatic Lock-to-Reference Function
• Programmable Serial Output Differential Swing
- 200 mV to 1600 mV, peak-peak
- Allows compatibility with other serial system
voltage levels
• Programmable Pre-emphasis Levels 0 to 500%
• Telecom/Datacom Support Modes
- "x8" and "x10" clocking/data paths
- 64B/66B clocking support
1
0Virtex-II Pro and Virtex-II Pro X Platform FPGAs:
Introduction and Overview
DS083 (v5.0) June 21, 2011 Product Specification
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Tab le 1 : Virtex-II Pro / Virtex-II Pro X FPGA Family Members
Device(1)
RocketIO
Transceiver
Blocks
PowerPC
Processor
Blocks
Logic
Cells(2)
CLB (1 = 4 slices =
max 128 bits) 18 X 18 Bit
Multiplier
Blocks
Block SelectRAM+
DCMs
Maximum
User
I/O PadsSlices
Max Distr
RAM (Kb)
18 Kb
Blocks
Max Block
RAM (Kb)
XC2VP2 4 0 3,168 1,408 44 12 12 216 4 204
XC2VP4 4 1 6,768 3,008 94 28 28 504 4 348
XC2VP7 8 1 11,088 4,928 154 44 44 792 4 396
XC2VP20 8 2 20,880 9,280 290 88 88 1,584 8 564
XC2VPX20 8(4) 1 22,032 9,792 306 88 88 1,584 8 552
XC2VP30 8 2 30,816 13,696 428 136 136 2,448 8 644
XC2VP40 0(3), 8, or 12 2 43,632 19,392 606 192 192 3,456 8 804
XC2VP50 0(3) or 16 2 53,136 23,616 738 232 232 4,176 8 852
XC2VP70 16 or 20 2 74,448 33,088 1,034 328 328 5,904 8 996
XC2VPX70 20(4) 2 74,448 33,088 1,034 308 308 5,544 8 992
XC2VP100 0(3) or 20 2 99,216 44,096 1,378 444 444 7,992 12 1,164
Notes:
1. -7 speed grade devices are not available in Industrial grade.
2. Logic Cell (1) 4-input LUT + (1)FF + Carry Logic
3. These devices can be ordered in a configuration without RocketIO transceivers. See Ta bl e 3 for package configurations.
4. Virtex-II Pro X devices equipped with RocketIO X transceiver cores.
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Introduction and Overview
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DS083 (v5.0) June 21, 2011 www.xilinx.com Module 1 of 4
Product Specification 2
Product Not Recommended For New Designs
• Programmable Receiver Equalization
• Internal AC Coupling
• On-Chip 50Termination
- Eliminates the need for external termination
resistors
• Pre- and Post-Driver Serial and Parallel TX-to-RX
Internal Loopback Modes for Testing Operability
• Programmable Comma Detection
- Allows for any protocol
- Allows for detection of any 10-bit character
• 8B/10B and 64B/66B Encoding Blocks
RocketIO Transceiver Features (All Except XC2VPX20 and XC2VPX70)
• Full-Duplex Serial Transceiver (SERDES) Capable of
Baud Rates from 600 Mb/s to 3.125 Gb/s
• 100 Gb/s Duplex Data Rate (20 Channels)
• Monolithic Clock Synthesis and Clock Recovery (CDR)
• Fibre Channel, 10G Fibre Channel, Gigabit Ethernet,
10 Gb Attachment Unit Interface (XAUI), and
Infiniband-Compliant Transceivers
• 8-, 16-, or 32-bit Selectable Internal FPGA Interface
• 8B /10B Encoder and Decoder (optional)
•50/75 on-chip Selectable Transmit and Receive
Terminations
• Programmable Comma Detection
• Channel Bonding Support (from 2 to 20 Channels)
• Rate Matching via Insertion/Deletion Characters
• Four Levels of Selectable Pre-Emphasis
• Five Levels of Output Differential Voltage
• Per-Channel Internal Loopback Modes
• 2.5V Transceiver Supply Voltage
PowerPC RISC Processor Block Features (All Except XC2VP2)
• Embedded 300+ MHz Harvard Architecture Block
• Low Power Consumption: 0.9 mW/MHz
• Five-Stage Data Path Pipeline
• Hardware Multiply/Divide Unit
• Thirty-Two 32-bit General Purpose Registers
• 16 KB Two-Way Set-Associative Instruction Cache
• 16 KB Two-Way Set-Associative Data Cache
• Memory Management Unit (MMU)
- 64-entry unified Translation Look-aside Buffers (TLB)
- Variable page sizes (1 KB to 16 MB)
• Dedicated On-Chip Memory (OCM) Interface
• Supports IBM CoreConnect™ Bus Architecture
• Debug and Trace Support
• Timer Facilities
Virtex-II Pro Platform FPGA Technology (All Devices)
• SelectRAM+ Memory Hierarchy
- Up to 8 Mb of True Dual-Port RAM in 18 Kb block
SelectRAM+ resources
- Up to 1,378 Kb of distributed SelectRAM+
resources
- High-performance interfaces to external memory
• Arithmetic Functions
- Dedicated 18-bit x 18-bit multiplier blocks
- Fast look-ahead carry logic chains
• Flexible Logic Resources
- Up to 88,192 internal registers/latches with Clock
Enable
- Up to 88,192 look-up tables (LUTs) or cascadable
variable (1 to 16 bits) shift registers
- Wide multiplexers and wide-input function support
- Horizontal cascade chain and Sum-of-Products
support
- Internal 3-state busing
• High-Performance Clock Management Circuitry
- Up to twelve Digital Clock Manager (DCM) modules
· Precise clock de-skew
· Flexible frequency synthesis
· High-resolution phase shifting
- 16 global clock multiplexer buffers in all parts
• Active Interconnect Technology
- Fourth-generation segmented routing structure
- Fast, predictable routing delay, independent of
fanout
- Deep sub-micron noise immunity benefits
• SelectIO™-Ultra Technology
- Up to 1,164 user I/Os
- Twenty-two single-ended standards and
ten differential standards
- Programmable LVCMOS sink/source current (2 mA
to 24 mA) per I/O
- XCITE Digitally Controlled Impedance (DCI) I/O
- PCI/ PCI-X support (1)
- Differential signaling
· 840 Mb/s Low-Voltage Differential Signaling I/O
(LVDS) with current mode drivers
· On-chip differential termination
· Bus LVDS I/O
1. Refer to XAPP653 for more information.
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DS083 (v5.0) June 21, 2011 www.xilinx.com Module 1 of 4
Product Specification 3
Product Not Recommended For New Designs
· HyperTransport (LDT) I/O with current driver
buffers
· Built-in DDR input and output registers
- Proprietary high-performance SelectLink
technology for communications between Xilinx
devices
· High-bandwidth data path
· Double Data Rate (DDR) link
· Web-based HDL generation methodology
• SRAM-Based In-System Configuration
- Fast SelectMAP™ configuration
- Triple Data Encryption Standard (DES) security
option (bitstream encryption)
- IEEE 1532 support
- Partial reconfiguration
- Unlimited reprogrammability
- Readback capability
• Supported by Xilinx Foundation™ and Alliance
Series™ Development Systems
- Integrated VHDL and Verilog design flows
- ChipScope™ Integrated Logic Analyzer
• 0.13 µm Nine-Layer Copper Process with 90 nm
High-Speed Transistors
•1.5V (V
CCINT) core power supply, dedicated 2.5V
VCCAUX auxiliary and VCCO I/O power supplies
• IEEE 1149.1 Compatible Boundary-Scan Logic Support
• Flip-Chip and Wire-Bond Ball Grid Array (BGA)
Packages in Standard 1.00 mm Pitch.
• Wire-Bond BGA Devices Available in Pb-Free
Packaging (www.xilinx.com/pbfree)
• Each Device 100% Factory Tested
General Description
The Virtex-II Pro and Virtex-II Pro X families contain plat-
form FPGAs for designs that are based on IP cores and
customized modules. The family incorporates multi-gigabit
transceivers and PowerPC CPU blocks in Virtex-II Pro
Series FPGA architecture. It empowers complete solutions
for telecommunication, wireless, networking, video, and
DSP applications.
The leading-edge 0.13 µm CMOS nine-layer copper pro-
cess and Virtex-II Pro architecture are optimized for high
performance designs in a wide range of densities. Combin-
ing a wide variety of flexible features and IP cores, the
Virtex-II Pro family enhances programmable logic design
capabilities and is a powerful alternative to mask-pro-
grammed gate arrays.
Architecture
Array Overview
Virtex-II Pro and Virtex-II Pro X devices are user-program-
mable gate arrays with various configurable elements and
embedded blocks optimized for high-density and high-per-
formance system designs. Virtex-II Pro devices implement
the following functionality:
• Embedded high-speed serial transceivers enable data
bit rate up to 3.125 Gb/s per channel (RocketIO) or
6.25 Gb/s (RocketIO X).
• Embedded IBM PowerPC 405 RISC processor blocks
provide performance up to 400 MHz.
• SelectIO-Ultra blocks provide the interface between
package pins and the internal configurable logic. Most
popular and leading-edge I/O standards are supported
by the programmable IOBs.
• Configurable Logic Blocks (CLBs) provide functional
elements for combinatorial and synchronous logic,
including basic storage elements. BUFTs (3-state
buffers) associated with each CLB element drive
dedicated segmentable horizontal routing resources.
• Block SelectRAM+ memory modules provide large
18 Kb storage elements of True Dual-Port RAM.
• Embedded multiplier blocks are 18-bit x 18-bit
dedicated multipliers.
• Digital Clock Manager (DCM) blocks provide
self-calibrating, fully digital solutions for clock
distribution delay compensation, clock multiplication
and division, and coarse- and fine-grained clock phase
shifting.
A new generation of programmable routing resources called
Active Interconnect Technology interconnects all these ele-
ments. The general routing matrix (GRM) is an array of rout-
ing switches. Each programmable element is tied to a
switch matrix, allowing multiple connections to the general
routing matrix. The overall programmable interconnection is
hierarchical and supports high-speed designs.
All programmable elements, including the routing
resources, are controlled by values stored in static memory
cells. These values are loaded in the memory cells during
configuration and can be reloaded to change the functions
of the programmable elements.
Features
This section briefly describes Virtex-II Pro / Virtex-II Pro X
features. For more details, refer to Virtex-II Pro and
Virtex-II Pro X Platform FPGAs: Functional Description.
RocketIO / RocketIO X MGT Cores
The RocketIO and RocketIO X Multi-Gigabit Transceivers
are flexible parallel-to-serial and serial-to-parallel embed-
ded transceiver cores used for high-bandwidth interconnec-
tion between buses, backplanes, or other subsystems.
Multiple user instantiations in an FPGA are possible,
providing up to 100 Gb/s (RocketIO) or 170 Gb/s
(RocketIO X) of full-duplex raw data transfer. Each channel
can be operated at a maximum data transfer rate of
3.125 Gb/s (RocketIO) or 6.25 Gb/s (RocketIO X).
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Product Specification 4
Product Not Recommended For New Designs
Each RocketIO or RocketIO X core implements the following
technology:
• Serializer and deserializer (SERDES)
• Monolithic clock synthesis and clock recovery (CDR)
• 10 Gigabit Attachment Unit Interface (XAUI) Fibre
Channel (3.1875 Gb/s XAUI), Infiniband, PCI Express,
Aurora, SXI-5 (SFI-5,/SPI-5), and OC-48
compatibility(1)
• 8/16/32-bit (RocketIO) or 8/16/32/64-bit (RocketIO X)
selectable FPGA interface
• 8B/10B (RocketIO) or 8B/10B and 64B/66B
(RocketIO X) encoder and decoder with bypassing
option on each channel
• Channel bonding support (two to twenty channels)
- Elastic buffers for inter-chip deskewing and
channel-to-channel alignment
• Receiver clock recovery tolerance of up to
75 non-transitioning bits
•50 (RocketIO X) or 50/75 selectable (RocketIO)
on-chip transmit and receive terminations
• Programmable comma detection and word alignment
• Rate matching via insertion/deletion characters
• Automatic lock-to-reference function
• Programmable pre-emphasis support
• Per-channel serial and parallel transmitter-to-receiver
internal loopback modes
• Optional transmit and receive data inversion
• Cyclic Redundancy Check support (RocketIO only)
PowerPC 405 Processor Block
The PPC405 RISC CPU can execute instructions at a sus-
tained rate of one instruction per cycle. On-chip instruction
and data cache reduce design complexity and improve sys-
tem throughput.
The PPC405 features include:
• PowerPC RISC CPU
- Implements the PowerPC User Instruction Set
Architecture (UISA) and extensions for embedded
applications
- Thirty-two 32-bit general purpose registers (GPRs)
- Static branch prediction
- Five-stage pipeline with single-cycle execution of
most instructions, including loads/stores
- Unaligned and aligned load/store support to cache,
main memory, and on-chip memory
- Hardware multiply/divide for faster integer
arithmetic (4-cycle multiply, 35-cycle divide)
- Enhanced string and multiple-word handling
- Big/little endian operation support
•Storage Control
- Separate instruction and data cache units, both
two-way set-associative and non-blocking
- Eight words (32 bytes) per cache line
- 16 KB array Instruction Cache Unit (ICU), 16 KB
array Data Cache Unit (DCU)
- Operand forwarding during instruction cache line fill
- Copy-back or write-through DCU strategy
- Doubleword instruction fetch from cache improves
branch latency
• Virtual mode memory management unit (MMU)
- Translation of the 4 GB logical address space into
physical addresses
- Software control of page replacement strategy
- Supports multiple simultaneous page sizes ranging
from 1 KB to 16 MB
• OCM controllers provide dedicated interfaces between
Block SelectRAM+ memory and processor block
instruction and data paths for high-speed access
• PowerPC timer facilities
- 64-bit time base
- Programmable interval timer (PIT)
- Fixed interval timer (FIT)
- Watchdog timer (WDT)
• Debug Support
- Internal debug mode
- External debug mode
- Debug Wait mode
- Real Time Trace debug mode
- Enhanced debug support with logical operators
- Instruction trace and trace-back support
- Forward or backward trace
• Two hardware interrupt levels support
• Advanced power management support
Input/Output Blocks (IOBs)
IOBs are programmable and can be categorized as follows:
• Input block with an optional single data rate (SDR) or
double data rate (DDR) register
• Output block with an optional SDR or DDR register and
an optional 3-state buffer to be driven directly or
through an SDR or DDR register
• Bidirectional block (any combination of input and output
configurations)
These registers are either edge-triggered D-type flip-flops
or level-sensitive latches.
IOBs support the following single-ended I/O standards:
• LVTTL, LVCMOS (3.3V,(2) 2.5V, 1.8V, and 1.5V)
• PCI-X compatible (133 MHz and 66 MHz) at 3.3V(3)
• PCI compliant (66 MHz and 33 MHz) at 3.3V(3)
• GTL and GTLP
1. Refer to Table 4, Module 2 for detailed information about RocketIO and RocketIO X transceiver compatible protocols.
2. Refer to XAPP659 for more information.
3. Refer to XAPP653 for more information.
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DS083 (v5.0) June 21, 2011 www.xilinx.com Module 1 of 4
Product Specification 5
Product Not Recommended For New Designs
• HSTL (1.5V and 1.8V, Class I, II, III, and IV)
• SSTL (1.8V and 2.5V, Class I and II)
The DCI I/O feature automatically provides on-chip termina-
tion for each single-ended I/O standard.
The IOB elements also support the following differential sig-
naling I/O standards:
• LVDS and Extended LVDS (2.5V)
• BLV D S (B u s LVD S )
•ULVDS
•LDT
• LVPECL (2.5V)
Two adjacent pads are used for each differential pair. Two or
four IOBs connect to one switch matrix to access the routing
resources. On-chip differential termination is available for
LVD S, LV DS Extended, ULVDS, and LDT standards.
Configurable Logic Blocks (CLBs)
CLB resources include four slices and two 3-state buffers.
Each slice is equivalent and contains:
• Two function generators (F & G)
• Two storage elements
• Arithmetic logic gates
• Large multiplexers
• Wide function capability
• Fast carry look-ahead chain
• Horizontal cascade chain (OR gate)
The function generators F & G are configurable as 4-input
look-up tables (LUTs), as 16-bit shift registers, or as 16-bit
distributed SelectRAM+ memory.
In addition, the two storage elements are either
edge-triggered D-type flip-flops or level-sensitive latches.
Each CLB has internal fast interconnect and connects to a
switch matrix to access general routing resources.
Block SelectRAM+ Memory
The block SelectRAM+ memory resources are 18 Kb of
True Dual-Port RAM, programmable from 16K x 1 bit to
512 x 36 bit, in various depth and width configurations.
Each port is totally synchronous and independent, offering
three "read-during-write" modes. Block SelectRAM+ mem-
ory is cascadable to implement large embedded storage
blocks. Supported memory configurations for dual-port and
single-port modes are shown in Ta bl e 2 .
18 X 18 Bit Multipliers
A multiplier block is associated with each SelectRAM+
memory block. The multiplier block is a dedicated
18 x 18-bit 2s complement signed multiplier, and is opti-
mized for operations based on the block SelectRAM+ con-
tent on one port. The 18 x 18 multiplier can be used
independently of the block SelectRAM+ resource.
Read/multiply/accumulate operations and DSP filter struc-
tures are extremely efficient.
Both the SelectRAM+ memory and the multiplier resource
are connected to four switch matrices to access the general
routing resources.
Global Clocking
The DCM and global clock multiplexer buffers provide a
complete solution for designing high-speed clock schemes.
Up to twelve DCM blocks are available. To generate
deskewed internal or external clocks, each DCM can be
used to eliminate clock distribution delay. The DCM also
provides 90-, 180-, and 270-degree phase-shifted versions
of its output clocks. Fine-grained phase shifting offers
high-resolution phase adjustments in increments of 1/256 of
the clock period. Very flexible frequency synthesis provides
a clock output frequency equal to a fractional or integer mul-
tiple of the input clock frequency. For exact timing parame-
ters, see Virtex-II Pro and Virtex-II Pro X Platform FPGAs:
DC and Switching Characteristics.
Virtex-II Pro devices have 16 global clock MUX buffers, with
up to eight clock nets per quadrant. Each clock MUX buffer
can select one of the two clock inputs and switch glitch-free
from one clock to the other. Each DCM can send up to four
of its clock outputs to global clock buffers on the same edge.
Any global clock pin can drive any DCM on the same edge.
Routing Resources
The IOB, CLB, block SelectRAM+, multiplier, and DCM ele-
ments all use the same interconnect scheme and the same
access to the global routing matrix. Timing models are
shared, greatly improving the predictability of the perfor-
mance of high-speed designs.
There are a total of 16 global clock lines, with eight available
per quadrant. In addition, 24 vertical and horizontal long
lines per row or column, as well as massive secondary and
local routing resources, provide fast interconnect.
Virtex-II Pro buffered interconnects are relatively unaffected
by net fanout, and the interconnect layout is designed to
minimize crosstalk.
Horizontal and vertical routing resources for each row or
column include:
• 24 long lines
• 120 hex lines
• 40 double lines
• 16 direct connect lines (total in all four directions)
Boundary Scan
Boundary-scan instructions and associated data registers
support a standard methodology for accessing and config-
uring Virtex-II Pro devices, complying with IEEE standards
1149.1 and 1532. A system mode and a test mode are
Tab le 2 : Dual-Port and Single-Port Configurations
16K x 1 bit 4K x 4 bits 1K x 18 bits
8K x 2 bits 2K x 9 bits 512 x 36 bits
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Product Specification 6
Product Not Recommended For New Designs
implemented. In system mode, a Virtex-II Pro device will
continue to function while executing non-test Bound-
ary-Scan instructions. In test mode, Boundary-Scan test
instructions control the I/O pins for testing purposes. The
Virtex-II Pro Test Access Port (TAP) supports BYPASS,
PRELOAD, SAMPLE, IDCODE, and USERCODE non-test
instructions. The EXTEST, INTEST, and HIGHZ test instruc-
tions are also supported.
Configuration
Virtex-II Pro / Virtex-II Pro devices are configured by load-
ing the bitstream into internal configuration memory using
one of the following modes:
• Slave-serial mode
• Master-serial mode
• Slave SelectMAP mode
• Master SelectMAP mode
• Boundary-Scan mode (IEEE 1532)
A Data Encryption Standard (DES) decryptor is available
on-chip to secure the bitstreams. One or two triple-DES key
sets can be used to optionally encrypt the configuration data.
The Xilinx System Advanced Configuration Enviornment
(System ACE) family offers high-capacity and flexible solu-
tion for FPGA configuration as well as program/data storage
for the processor. See DS080, System ACE CompactFlash
Solution for more information.
Readback and Integrated Logic Analyzer
Configuration data stored in Virtex-II Pro / Virtex-II Pro con-
figuration memory can be read back for verification. Along
with the configuration data, the contents of all flip-flops and
latches, distributed SelectRAM+, and block SelectRAM+
memory resources can be read back. This capability is use-
ful for real-time debugging.
The Xilinx ChipScope Integrated Logic Analyzer (ILA) cores
and Integrated Bus Analyzer (IBA) cores, along with the
ChipScope Pro Analyzer software, provide a complete solu-
tion for accessing and verifying user designs within
Virtex-II Pro devices.
IP Core and Reference Support
Intellectual Property is part of the Platform FPGA solution.
In addition to the existing FPGA fabric cores, the list below
shows some of the currently available hardware and soft-
ware intellectual properties specially developed for
Virtex-II Pro / Virtex-II Pro X by Xilinx. Each IP core is mod-
ular, portable, Real-Time Operating System (RTOS) inde-
pendent, and CoreConnect compatible for ease of design
migration. Refer to www.xilinx.com/ipcenter for the latest
and most complete list of cores.
Hardware Cores
• Bus Infrastructure cores (arbiters, bridges, and more)
• Memory cores (DDR, Flash, and more)
• Peripheral cores (UART, IIC, and more)
• Networking cores (ATM, Ethernet, and more)
Software Cores
• Boot code
•Test code
• Device drivers
• Protocol stacks
• RTOS integration
• Customized board support package
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Product Specification 7
Product Not Recommended For New Designs
Virtex-II Pro / Virtex-II Pro X Device/Package Combinations and Maximum I/Os
Offerings include ball grid array (BGA) packages with
1.0 mm pitch. In addition to traditional wire-bond intercon-
nect (FG/FGG packages), flip-chip interconnect (FF pack-
ages) is used in some of the BGA offerings. Flip-chip
interconnect construction supports more I/Os than are pos-
sible in wire-bond versions of similar packages, providing a
high pin count and excellent power dissipation.
The device/package combination table (Ta bl e 3 ) details the
maximum number of user I/Os and RocketIO / RocketIO X
MGTs for each device and package using wire-bond or
flip-chip technology.
The FF1148 and FF1696 packages have no RocketIO
transceivers bonded out. Extra SelectIO-Ultra resources
occupy available pins in these packages, resulting in a
higher user I/O count. These packages are available for the
XC2VP40, XC2VP50, and XC2VP100 devices only.
The I/Os per package count includes all user I/Os except
the 15 control pins (CCLK, DONE, M0, M1, M2, PROG_B,
PWRDWN_B, TCK, TDI, TDO, TMS, HSWAP_EN, DXN,
DXP, and RSVD), VBATT, and the RocketIO / RocketIO X
transceiver pins.
Maximum Performance
Maximum performance of the RocketIO / RocketIO X transceiver and the PowerPC processor block varies, depending on
package style and speed grade. See Tabl e 4 for details. Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching
Characteristics contains the rest of the FPGA fabric performance parameters.
Tab le 3 : Virtex-II Pro Device/Package Combinations and Maximum Number of Available I/Os
Package(1) FG256/
FGG256
FG456/
FGG456 FG676 FF672 FF896 FF1152 FF1148 FF1517 FF1704 FF1696
Pitch (mm) 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00
Size (mm) 17 x 17 23 x 23 26 x 26 27 x 27 31 x 31 35 x 35 35 x 35 40 x 40 42.5 x 42.5 42.5 x 42.5
XC2VP2 140 / 4 156 / 4 204 / 4
XC2VP4 140 / 4 248 / 4 348 / 4
XC2VP7 248 / 8 396 / 8 396 / 8
XC2VP20 404 / 8 556 / 8 564 / 8
XC2VPX20 552 / 8(2)
XC2VP30 416 / 8 556 / 8 644 / 8
XC2VP40 416 / 8 692 / 12 804 / 0(3)
XC2VP50 692 / 16 812 / 0(3) 852 / 16
XC2VP70 964/16 996/20
XC2VPX70 992 / 20(2)
XC2VP100 1,040 / 20 1,164 / 0(3)
Notes:
1. Wirebond packages FG256, FG456, and FG676 are also available in Pb-free versions FGG256, FGG456, and FGG676. See Virtex-II Pro Ordering
Examples for details on how to order.
2. Virtex-II Pro X device is equipped with RocketIO X transceiver cores.
3. The RocketIO transceivers in devices in the FF1148 and FF1696 packages are not bonded out to the package pins.
Tab le 4 : Maximum RocketIO / RocketIO X Transceiver and Processor Block Performance
Device
Speed Grade
Units-7(1) -6 -5
RocketIO X Transceiver FlipChip (FF) N/A 6.25(3) 4.25(3) Gb/s
RocketIO Transceiver FlipChip (FF) 3.125 3.125 2.0 Gb/s
RocketIO Transceiver Wirebond (FG) 2.5 2.5 2.0 Gb/s
PowerPC Processor Block 400(2) 350(2) 300 MHz
Notes:
1. -7 speed grade devices are not available in Industrial grade.
2. IMPORTANT! When CPMC405CLOCK runs at speeds greater than 350 MHz in -7 Commercial grade dual-processor devices, or greater than
300 MHz in -6 Industrial grade dual-processor devices, users must implement the technology presented in XAPP755, “PowerPC 405 Clock Macro for
-7(C) and -6(I) Speed Grade Dual-Processor Devices.” Refer to Ta b l e 1 to identify dual-processor devices.
3. XC2VPX70 is only available at fixed 4.25 Gb/s baud rate.
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Product Specification 8
Product Not Recommended For New Designs
Virtex-II Pro Ordering Examples
Virtex-II Pro ordering examples are shown in Figure 1 (flip-chip package) and Figure 2 (Pb-free wire-bond package).
Virtex-II Pro X Ordering Example
A Virtex-II Pro X ordering example is shown in Figure 3.
Figure 1: Virtex-II Pro Ordering Example, Flip-Chip Package
Figure 2: Virtex-II Pro Ordering Example, Pb-Free Wire-Bond Package
Figure 3: Virtex-II Pro X Ordering Example, Flip-Chip Package
Example: XC2VP40 -7 FF 1152
C
Device Type Temperature Range:
C = Commercial (Tj = 0˚C to +85˚C)
I = Industrial* (Tj = –40˚C to +100˚C)
Number of Pins
Package Type
Speed Grade
(-5, -6, -7*)
DS083_02_062104
*NOTE: -7 devices not available in Industrial grade.
Example: XC2VP40 -6 FG G 676 I
Device Type Temperature Range:
C = Commercial (Tj = 0˚C to +85˚C)
I = Industrial* (Tj = –40˚C to +100˚C)
Number of Pins
Package Type
Pb-Free
Speed Grade
(-5, -6, -7*)
DS083-1_02b_062104
*NOTE: -7 devices not available in Industrial grade.
Example: XC2VPX20 -6 FF 896 C
Device Type Temperature Range:
C = Commercial (Tj = 0°C to +85°C)
I = Industrial* (Tj = –40°C to +100°C)
Number of Pins
Package Type
Speed Grade
(-5, -6)
DS083_02a_092705
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DS083 (v5.0) June 21, 2011 www.xilinx.com Module 1 of 4
Product Specification 9
Product Not Recommended For New Designs
Revision History
This section records the change history for this module of the data sheet.
Date Version Revision
01/31/02 1.0 Initial Xilinx release.
06/13/02 2.0 New Virtex-II Pro family members. New timing parameters per speedsfile v1.62.
09/03/02 2.1 Updates to Tabl e 1 and Ta b l e 3 . Processor Block information added to Table 4 .
09/27/02 2.2 In Ta bl e 1 , correct max number of XC2VP30 I/Os to 644.
11/20/02 2.3 Add bullet items for 3.3V I/O features.
01/20/03 2.4 •In Ta b l e 3 , add FG676 package option for XC2VP20, XC2VP30, and XC2VP40.
• Remove FF1517 package option for XC2VP40.
03/24/03 2.4.1 • Correct number of single-ended I/O standards from 19 to 22.
• Correct minimum RocketIO serial speed from 622 Mbps to 600 Mbps.
08/25/03 2.4.2 • Add footnote referring to XAPP659 to callout for 3.3V I/O standards on page 4.
12/10/03 3.0 • XC2VP2 through XC2VP70 speed grades -5, -6, and -7, and XC2VP100 speed grades
-5 and -6, are released to Production status.
02/19/04 3.1 • Ta bl e 1 : Corrected number of RocketIO transceiver blocks for XC2VP40.
• Section Virtex-II Pro Platform FPGA Technology (All Devices): Updated number of
differential standards supported from six to ten.
• Section Input/Output Blocks (IOBs): Added text stating that differential termination is
available for LVDS, LVD S Extended, ULVDS, and LDT standards.
•Figure 1: Added note stating that -7 devices are not available in Industrial grade.
03/09/04 3.1.1 • Recompiled for backward compatibility with Acrobat 4 and above. No content changes.
06/30/04 4.0 Merged in DS110-1 (Module 1 of Virtex-II Pro X data sheet). Added information on available
Pb-free packages.
11/17/04 4.1 No changes in Module 1 for this revision.
03/01/05 4.2 Tab l e 3: Corrected number of RocketIO transceivers for XC2VP7-FG456.
06/20/05 4.3 No changes in Module 1 for this revision.
09/15/05 4.4 • Changed all instances of 10.3125 Gb/s (RocketIO transceiver maximum bit rate) to
6.25 Gb/s.
• Changed all instances of 412.5 Gb/s (RocketIO X transceiver maximum multi-channel
raw data transfer rate) to 250 Gb/s.
10/10/05 4.5 • Changed XC2VPX70 variable baud rate specification to fixed-rate operation at
4.25 Gb/s.
• Changed maximum performance for -7 Virtex-II Pro X MGT (Tabl e 4 ) to N/A.
03/05/07 4.6 No changes in Module 1 for this revision.
11/05/07 4.7 Updated copyright notice and legal disclaimer.
06/21/11 5.0 Added Product Not Recommended for New Designs banner.
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DS083 (v5.0) June 21, 2011 www.xilinx.com Module 1 of 4
Product Specification 10
Product Not Recommended For New Designs
Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND
CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED
WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE
SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE
PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES
THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
Virtex-II Pro Data Sheet
The Virtex-II Pro Data Sheet contains the following modules:
•Virtex-II Pro and Virtex-II Pro X Platform FPGAs:
Introduction and Overview (Module 1)
•Virtex-II Pro and Virtex-II Pro X Platform FPGAs:
Functional Description (Module 2)
•Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC
and Switching Characteristics (Module 3)
•Virtex-II Pro and Virtex-II Pro X Platform FPGAs:
Pinout Information (Module 4)