ADS7817UB/2K5G4 - Texas Instruments High-Performance Analog

DESCRIPTION

The ADS7817 is a 12-bit, 200kHz sampling Analog-to-

Digital (A/D) converter that features a high impedance fully

differential analog input. The reference voltage can be var-

ied from 100mV to 2.5V, with a corresponding input-

referred resolution between 49µV and 1.22mV.

The differential input, low power, automatic power down,

and small size make the ADS7817 ideal for direct connec-

tion to transducers in battery operated systems, remote data

acquisition, or multi-channel applications. The ADS7817 is

available in a plastic mini-DIP-8, an SO-8, or an MSOP-8

package.

12-Bit Differential Input Micro Power Sampling

ANALOG-TO-DIGITAL CONVERTER

FEATURES

●BIPOLAR INPUT RANGE

●TRUE DIFFERENTIAL INPUT

●200kHz SAMPLING RATE

●MICRO POWER: 2.3mW at 200kHz

●POWER DOWN: 3µA Max

●AVAILABLE IN MSOP-8 PACKAGE

●SERIAL INTERFACE

●AC COMMON-MODE REJECTION

SAR Control

Serial

Interface

OUT

Comparator

S/H Amp CS/SHDN

DCLOCK

+In

REF

–In CDAC

OPA658

ADS7817

APPLICATIONS

●TRANSDUCER INTERFACE

●BATTERY OPERATED SYSTEMS

●REMOTE DATA ACQUISITION

●ISOLATED DATA ACQUISITION

●AC MOTOR CONTROL

ADS7817

SBAS066A – MAY 2001

www.ti.com

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

ADS7817

2SBAS066A

ABSOLUTE MAXIMUM RATINGS(1)

+VCC ..................................................................................................... +6V

Analog Input........................................................... –0.3V to (+VCC + 0.3V)

Logic Input .............................................................–0.3V to (+VCC + 0.3V)

Case Temperature ......................................................................... +100°C

Junction Temperature .................................................................... +150°C

Storage Temperature..................................................................... +125°C

External Reference Voltage .............................................................. +5.5V

NOTE: (1) Stresses above these ratings may permanently damage the device.

PIN CONFIGURATION

PIN DESCRIPTIONS

PIN NAME DESCRIPTION

REF Reference Input.

2 +In Non Inverting Input.

3–In Inverting Input.

4 GND Ground.

5 CS/SHDN Chip Select when LOW, Shutdown Mode when HIGH.

OUT The serial output data word is comprised of 12 bits of data. In operation the data is valid on the falling edge of DCLOCK. The

second clock pulse after the falling edge of CS enables the serial output. After one null bit the data is valid for the next 12 edges.

7 DCLOCK Data Clock synchronizes the serial data transfer and determines conversion speed.

8+V

CC Power Supply.

+VCC

DCLOCK

DOUT

CS/SHDN

VREF

+In

–In

GND

ADS7817

PDIP-8,

SOIC-8,

MSOP-8

PACKAGE/ORDERING INFORMATION

MAXIMUM MAXIMUM

INTEGRAL DIFFERENTIAL

LINEARITY LINEARITY PACKAGE SPECIFICATION

ERROR ERROR DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT

PRODUCT (LSB) (LSB) PACKAGE NUMBER(1) RANGE MARKING(2) NUMBER(3) MEDIA

ADS7817P ±2±2 DIP-8 006 –40°C to +85°C ADS7817P ADS7817P Rails

ADS7817U ±2±2 SO-8 182 –40°C to +85°C ADS7817U ADS7817U "

ADS7817U """"""ADS7817U/2K5 Tape and Reel

ADS7817E ±2±2 MSOP-8 337 –40°C to +85°C A17 ADS7817E Rails

ADS7817E """"""ADS7817E/250 Tape and Reel

ADS7817E """"""ADS7817E/2K5 "

ADS7817PB ±2±1 Plastic DIP-8 006 –40°C to +85°C ADS7817PB ADS7817PB Rails

ADS7817UB ±2±1 SO-8 182 –40°C to +85°C ADS7817UB ADS7817UB "

ADS7817UB """"""ADS7817UB/2K5 Tape and Reel

ADS7817EB ±2±1 MSOP 337 –40°C to +85°C A17 ADS7817EB Rails

ADS7817EB """"""ADS7817EB/250 Tape and Reel

ADS7817EB """"""ADS7817EB/2K5 "

ADS7817PC ±1±0.75 DIP-8 006 –40°C to +85°C ADS7817PC ADS7817PC Rails

ADS7817UC ±1±0.75 SO-8 182 –40°C to +85°C ADS7817UC ADS7817UC "

ADS7817UC """"""ADS7817UC/2K5 Tape and Reel

ADS7817EC ±1±0.75 MSOP-8 337 –40°C to +85°C A17 ADS7817EC Rails

ADS7817EC """"""ADS7817EC/250 Tape and Reel

ADS7817EC """"""ADS7817EC/2K5 "

NOTE: (1) For detail drawing and dimension table, please see end of data sheet or Package Drawing File on Web. (2) Performance Grade information is marked

on the reel. (3) Models with a slash(/) are available only in Tape and reel in quantities indicated (e.g. /250 indicates 250 units per reel, /2K5 indicates 2500 devices

per reel). Ordering 2500 pieces of ”ADS7817E/2K5“ will get a single 2500-piece Tape and Reel.

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instru-

ments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling

and installation procedures can cause damage.

ESD damage can range from subtle performance degradation

to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric

changes could cause the device not to meet its published

specifications.

ADS7817 3

SBAS066A

ELECTRICAL CHARACTERISTICS

At –40°C to +85°C, +VCC = +5V, VREF = +2.5V, fSAMPLE = 200kHz, fCLK = 16 • fSAMPLE, –In = +2.5V, unless otherwise specified.

ADS7817 ADS7817B ADS7817C

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS

ANALOG INPUT

Full-Scale Input Span +In – (–In) –VREF +VREF ✻✻✻✻V

Absolute Input Voltage +In –0.3 VCC +0.3 ✻✻✻✻V

–In –0.3 4 ✻✻✻✻V

Capacitance 15 ✻✻pF

Leakage Current ±1✻✻µA

SYSTEM PERFORMANCE

Resolution 12 ✻✻Bits

No Missing Codes 11 12 ✻Bits

Integral Linearity Error ±1±2±0.8 ±2±0.5 ±1 LSB(1)

Differential Linearity Error ±1±2±0.7 ±1±0.4 ±1 LSB

Offset Error ±1±6✻✻ ✻✻LSB

Gain Error ±0.5 ±4✻✻ ✻✻LSB

Noise 63 ✻✻µVrms

Common-Mode Rejection 80 ✻✻dB

Power Supply Rejection 82 ✻✻dB

SAMPLING DYNAMICS

Conversion Time 12 ✻✻

Clk Cycles

Acquisition Time 1.5 ✻✻

Clk Cycles

Throughput Rate 200 ✻✻kHz

DYNAMIC CHARACTERISTICS

Total Harmonic Distortion VIN = 5.0Vp-p at 1kHz –83 ✻✻dB

VIN = 5.0Vp-p at 5kHz –81 ✻✻dB

SINAD VIN = 5.0Vp-p at 1kHz 71 ✻✻dB

Spurious Free Dynamic Range VIN = 5.0Vp-p at 1kHz 86 ✻✻dB

REFERENCE INPUT

Voltage Range 0.1 2.5 ✻✻✻✻V

Resistance CS = VCC 5✻✻GΩ

CS = GND, fSAMPLE = 0Hz

5✻✻GΩ

Current Drain At Code FF8h 20 100 ✻✻ ✻✻µA

SAMPLE

= 12.5kHz

1.3 20 ✻✻ ✻✻µA

CS = VCC 0.001 3 ✻✻ ✻✻µA

DIGITAL INPUT/OUTPUT

Logic Family CMOS ✻✻

Logic Levels:

VIH IIH = +5µA3

+VCC +0.

3✻✻✻✻V

VIL IIL = +5µA–0.3 0.8 ✻✻✻✻V

VOH IOH = –250µA 3.5 ✻✻V

VOL IOL = 250µA 0.4 ✻✻V

Data Format Binary Two’s Complement ✻✻

POWER SUPPLY REQUIREMENTS

VCC Specified Performance 4.75 5.25 ✻✻✻✻V

Quiescent Current 460 800 ✻✻ ✻✻µA

fSAMPLE = 12.5kHz(2, 3) 40 ✻✻µA

fSAMPLE = 12.5kHz(3) 330 ✻✻µA

Power Down CS =VCC, fSAMPLE = 0Hz 3 ✻✻µA

TEMPERATURE RANGE

Specified Performance –40 +85 ✻✻✻✻°C

✻ Specifications same as ADS7817.

NOTE: (1) LSB means Least Significant Bit, with VREF equal to +2.5V, one LSB is 1.22mV. (2) fCLK = 3.2MHz, CS = VCC for 241 clock cycles out of every 256.

(3) See the Power Dissipation section for more information regarding lower sample rates.

ADS7817

4SBAS066A

TIMING CHARACTERISTICS

At TA = +25°C, VCC = +5V, VREF = +2.5V, fSAMPLE = 200kHz, and fCLK = 16 • fSAMPLE, –In = +2.5V, unless otherwise specified.

CHANGE IN OFFSET vs REFERENCE VOLTAGE

4.5

3.5

2.5

1.5

0.5

Change in Offset (LSB)

1.0 1.25 1.5 1.75 2.252.0 2.5

Reference Voltage (V)

CHANGE IN GAIN vs REFERENCE VOLTAGE

3.5

2.5

1.5

0.5

Change in Gain (LSB)

Reference Voltage (V)

1.0 1.25 1.5 1.75 2.252.0 2.5

CHANGE IN OFFSET vs TEMPERATURE

1.2

0.8

0.4

0.0

–0.4

–0.8

–1.2

Delta from 25°C (LSB)

–50 –25 0 25 50 75 100

Temperature (°C)

CHANGE IN GAIN vs TEMPERATURE

0.15

0.1

0.05

–0.05

–0.1

–0.15

Delta from 25°C (LSB)

–50 –25 0 25 50 75 100

Temperature (°C)

12.0

11.5

11.0

10.5

10.0

9.5

9.0

EFFECTIVE NUMBER OF BITS

vs REFERENCE VOLTAGE

Reference Voltage

0.1 1 10

Effective Number of Bits

PEAK-TO-PEAK NOISE vs REFERENCE VOLTAGE

Reference Voltage

0.1 1 10

Peak-to-Peak Noise (LSB)

ADS7817 5

SBAS066A

TIMING CHARACTERISTICS (Cont.)

At TA = +25°C, VCC = +5V, VREF = +2.5V, fSAMPLE = 200kHz, and fCLK = 16 • fSAMPLE, –In = +2.5V, unless otherwise specified.

SIGNAL-TO-NOISE RATIO AND

SIGNAL-TO-(NOISE+DISTORTION)

vs INPUT FREQUENCY

Input Frequency (kHz)

1 10 100

SNR and SINAD (dB)

SNR

SINAD

SIGNAL-TO-(NOISE+DISTORTION)

vs INPUT LEVEL

Input Level (dB)

–60 –50 –40 –30 –10–20 0

SINAD (dB)

POWER SUPPLY REJECTION vs RIPPLE FREQUENCY

–10

–20

–30

–40

–50

–60

–70

–80

–90

Power Supply Rejection (dB)

1 10 100 1000 10000

Ripple Frequency (kHz)

FREQUENCY SPECTRUM

(4096 Point FFT; fIN = 9.9kHz, –0.5dB)

–20

–40

–60

–80

–100

–120

Amplitude (dB)

0 255075100

Frequency (kHz)

SPURIOUS FREE DYNAMIC RANGE AND

TOTAL HARMONIC DISTORTION

vs INPUT FREQUENCY

Input Frequency (kHz)

110100

SFDR (dB)

–95

–90

–85

–80

–75

–70

–65

THD (dB)

SFDR

THD

CHANGE IN INTEGRAL LINEARITY and DIFFERENTIAL

LINEARITY vs SAMPLE RATE

1.5

1.0

0.5

–0.5

Delta from f

SAMPLE

= 200kHz (LSB)

0 80 160 240 320 400

Sample Rate (kHz)

Change in Integral

Linearity (LSB)

Change in Differential

Linearity (LSB)

ADS7817

6SBAS066A

TIMING CHARACTERISTICS (Cont.)

At TA = +25°C, VCC = +5V, VREF = +2.5V, fSAMPLE = 200kHz, and fCLK = 16 • fSAMPLE, –In = +2.5V, unless otherwise specified.

1.00

0.75

0.50

0.25

0.00

–0.25

–0.50

–0.75

–1.00

INTEGRAL LINEARITY ERROR vs CODE

Hex BTC Code

800 000 7FF

ILE (LSB)

1.00

0.75

0.50

0.25

0.00

–0.25

–0.50

–0.75

–1.00

DIFFERENTIAL LINEARITY ERROR vs CODE

Hex BTC Code

800 000 7FF

DLE (LSB)

CHANGE IN INTEGRAL LINEARITY AND DIFFERENTIAL

LINEARITY vs REFERENCE VOLTAGE

0.10

0.05

0.00

–0.05

–0.10

–0.15

–0.20

Delta from +2.5V Reference (LSB)

1 1.25 1.751.5 2.0 2.25 2.5

Reference Voltage (V)

Change in Differential

Linearity (LSB)

Change in Integral

Linearity (LSB)

INPUT LEAKAGE CURRENT vs TEMPERATURE

0.1

0.01

Leakage Current (nA)

–50 –25 0 25 50 75 100

Temperature (°C)

SUPPLY CURRENT vs TEMPERATURE

600

550

500

450

400

350

300

Supply Current (µA)

–50 –25 0 25 50 75 100

Temperature (°C)

POWER DOWN SUPPLY CURRENT

vs TEMPERATURE

2.5

1.5

0.5

Supply Current (µA)

–50 –25 0 25 50 75 100

Temperature (°C)

ADS7817 7

SBAS066A

TIMING CHARACTERISTICS (Cont.)

At TA = +25°C, VCC = +5V, VREF = +2.5V, fSAMPLE = 200kHz, and fCLK = 16 • fSAMPLE, –In = +2.5V, unless otherwise specified.

REFERENCE CURRENT vs SAMPLE RATE

(Code = FF8h)

Reference Current (µA)

0 40 80 120 160 200

Sample Rate (kHz)

REFERENCE CURRENT vs TEMPERATURE

(Code = FF8h)

Reference Current (µA)

–50 –25 0 25 50 75 100

Temperature (°C)

ADS7817

8SBAS066A

THEORY OF OPERATION

The ADS7817 is a classic successive approximation register

(SAR) analog-to-digital (A/D) converter. The architecture is

based on capacitive redistribution which inherently includes

a sample/hold function. The converter is fabricated on a 0.6µ

CMOS process. The architecture and process allow the

ADS7817 to acquire and convert an analog signal at up to

200,000 conversions per second while consuming very little

power.

The ADS7817 requires an external reference, an external

clock, and a single +5V power source. The external refer-

ence can be any voltage between 100mV and 2.5V. The

value of the reference voltage directly sets the range of the

analog input. The reference input current depends on the

conversion rate of the ADS7817.

The external clock can vary between 10kHz (625Hz through-

put) and 3.2MHz (200kHz throughput). The duty cycle of

the clock is essentially unimportant as long as the minimum

high and low times are at least 150ns. The minimum clock

frequency is set by the leakage on the capacitors internal to

the ADS7817.

The analog input is provided to two input pins: +In and –In.

When a conversion is initiated, the differential input on these

pins is sampled on the internal capacitor array. While a

conversion is in progress, both inputs are disconnected from

any internal function.

The digital result of the conversion is clocked out by the

DCLOCK input and is provided serially, most significant bit

first, on the DOUT pin. The digital data that is provided on the

DOUT pin is for the conversion currently in progress—there

is no pipeline delay. It is possible to continue to clock the

ADS7817 after the conversion is complete and to obtain the

serial data least significant bit first. See the Digital Interface

section for more information.

ANALOG INPUT

The analog input is bipolar and fully differential. There are

two general methods of driving the analog input of the

ADS7817: single-ended or differential (see Figure 1). When

the input is single-ended, the –In input is held at a fixed

voltage. The +In input swings around the same voltage and

the peak-to-peak amplitude is 2 • VREF. The value of VREF

determines the range over which the common voltage may

vary (see Figure 2).

When the input is differential, the amplitude of the input is the

difference between the +In and –In input, or: +In – (–In). A

voltage or signal is common to both of these inputs. The peak-

to-peak amplitude of each input is VREF about this common

voltage. However, since the inputs are 180° out of phase, the

peak-to-peak amplitude of the difference voltage is 2 • VREF.

The value of VREF also determines the range of the voltage

that may be common to both inputs (see Figure 3).

FIGURE 1. Methods of Driving the ADS7817: Single-

Ended or Differential.

FIGURE 2. Single-Ended Input: Common Voltage Range vs

VREF.

FIGURE 3. Differential Input: Common Voltage Range vs

VREF.

ADS7817

Single-Ended Input

Common

Voltage

2 • V

REF

peak-to-peak

Differential Input

Common

Voltage

REF

peak-to-peak

REF

peak-to-peak

0.0 0.5 1.0 1.5 2.0 2.5

VREF (V)

Common Voltage Range (V)

–1

2.8

2.2

–0.3

4.0 VCC = 5V

Single-Ended Input

0.0 0.5 1.0 1.5 2.0 2.5

REF

(V)

2.75

= 5V

1.95

4.0

–0.3

Common Voltage Range (V)

–1

Differential Input

ADS7817 9

SBAS066A

In each case, care should be taken to ensure that the output

impedance of the sources driving the +In and –In inputs are

matched. If this is not observed, the two inputs could have

different settling times. This may result in offset error, gain

error, and linearity error which change with both temperature

and input voltage. If the impedance cannot be matched, the

errors can be lessened by giving the ADS7817 more acquisi-

tion time.

The input current on the analog inputs depends on a number

of factors: sample rate, input voltage, and source impedance.

Essentially, the current into the ADS7817 charges the inter-

nal capacitor array during the sample period. After this

capacitance has been fully charged, there is no further input

current. The source of the analog input voltage must be able

to charge the input capacitance (15pF) to a 12-bit settling

level within 1.5 clock cycles. When the converter goes into

the hold mode or while it is in the power down mode, the

input impedance is greater than 1GΩ.

Care must be taken regarding the absolute analog input

voltage. The +In input should always remain within the

range of GND –300mV to VCC +300mV. The –In input

should always remain within the range of GND –300mV to

4V. Outside of these ranges, the converter’s linearity may

not meet specifications.

REFERENCE INPUT

The external reference sets the analog input range. The

ADS7817 will operate with a reference in the range of 100mV

to 2.5V. There are several important implications of this.

As the reference voltage is reduced, the analog voltage

weight of each digital output code is reduced. This is often

referred to as the LSB (least significant bit) size and is equal

to two times the reference voltage divided by 4096. This

means that any offset or gain error inherent in the A/D

converter will appear to increase, in terms of LSB size, as

the reference voltage is reduced. The typical performance

curves of “Change in Offset vs Reference Voltage” and

“Change in Gain vs Reference Voltage” provide more infor-

mation.

The noise inherent in the converter will also appear to

increase with lower LSB size. With a 2.5V reference, the

internal noise of the converter typically contributes only

0.52 LSB peak-to-peak of potential error to the output code.

When the external reference is 100mV, the potential error

contribution from the internal noise will be 25 times larger—

13 LSBs. The errors due to the internal noise are gaussian in

nature and can be reduced by averaging consecutive conver-

sion results.

For more information regarding noise, consult the typical

performance curves “Effective Number of Bits vs Reference

Voltage” and “Peak-to-Peak Noise vs Reference Voltage.”

Note that the effective number of bits (ENOB) figure is

calculated based on the converter’s signal-to-(noise + distor-

tion) with a 1kHz, 0dB input signal. SINAD is related to

ENOB as follows: SINAD = 6.02 • ENOB + 1.76.

With lower reference voltages, extra care should be taken to

provide a clean layout including adequate bypassing, a clean

power supply, a low-noise reference, and a low-noise input

signal. Because the LSB size is lower, the converter will also

be more sensitive to external sources of error such as nearby

digital signals and electromagnetic interference.

The current that must be provided by the external reference

will depend on the conversion result. The current is lowest

at negative full-scale (800h) and is typically 15µA at a

200kHz conversion rate (25°C). For the same conditions, the

current will increase as the analog input approaches positive

full scale, reaching 25µA at an output result of 7FFh. The

current does not increase linearly, but depends, to some

degree, on the bit pattern of the digital output.

The reference current diminishes directly with both conver-

sion rate and reference voltage. As the current from the

reference is drawn on each bit decision, clocking the con-

verter more quickly during a given conversion period will

not reduce the overall current drain from the reference. The

reference current changes only slightly with temperature.

See the curves, “Reference Current vs Sample Rate” and

“Reference Current vs Temperature” in the Typical Perfor-

mance Curves section for more information.

DIGITAL INTERFACE

SERIAL INTERFACE

The ADS7817 communicates with microprocessors and other

digital systems via a synchronous 3-wire serial interface as

shown in Figure 4 and Table I. The DCLOCK signal

synchronizes the data transfer with each bit being transmit-

ted on the falling edge of DCLOCK. Most receiving systems

will capture the bitstream on the rising edge of DCLOCK.

However, if the minimum hold time for DOUT is acceptable,

the system can use the falling edge of DCLOCK to capture

each bit.

TABLE I. Timing Specifications –40°C to +85°C.

SYMBOL

DESCRIPTION MIN TYP MAX UNITS

tSMPL Analog Input Sample TIme 1.5 2.0

Clk Cycles

tCONV Conversion Time 12

Clk Cycles

tCYC Throughput Rate 200 kHz

tCSD CS Falling to 0 ns

DCLOCK LOW

tSUCS CS Falling to 30 ns

DCLOCK Rising

thDO DCLOCK Falling to 15 ns

Current DOUT Not Valid

tdDO DCLOCK Falling to Next 85 150 ns

DOUT Valid

tdis CS Rising to DOUT Tri-State 25 50 ns

ten DCLOCK Falling to DOUT 50 100 ns

Enabled

tfDOUT Fall Time 70 100 ns

trDOUT Rise Time 60 100 ns

ADS7817

10 SBAS066A

CS/SHDN

OUT

DCLOCK

DATA

SUCS

CYC

CONV

POWER

DOWN

SMPL

Note: (1) After completing the data transfer, if further clocks are applied with CS

LOW, the A/D will output LSB-First data then followed with zeroes indefinitely.

B11

(MSB)B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

(1)

NULL

BIT

HI-ZHI-Z B11 B10 B9 B8

NULL

BIT

CS/SHDN

OUT

DCLOCK

CONV

DATA

SUCS

CSD

CYC

POWER DOWN

SMPL

Note: (2) After completing the data transfer, if further clocks are applied with CS

LOW, the A/D will output zeroes indefinitely.

DATA

: During this time, the bias current and the comparator power down and the reference input

becomes a high impedance node, leaving the CLK running to clock out LSB-First data or zeroes.

B11

(MSB)B10 B9 B8 B7 B6 B5 B4 B4B3 B3B2 B2B1 B1B0

NULL

BIT

HI-Z HI-Z

B5 B6 B7 B8 B9 B10 B11

(2)

A falling CS signal initiates the conversion and data transfer.

The first 1.5 to 2.0 clock periods of the conversion cycle are

used to sample the input signal. After the second falling

DCLOCK edge, DOUT is enabled and will output a LOW

value for one clock period. For the next 12 DCLOCK

periods, DOUT will output the conversion result, most sig-

nificant bit first. After the least significant bit (B0) has been

output, subsequent clocks will repeat the output data but in

a least significant bit first format.

After the most significant bit (B11) has been repeated, DOUT

will tri-state. Subsequent clocks will have no effect on the

converter. A new conversion is initiated only when CS has

been taken HIGH and returned LOW.

DATA FORMAT

The output data from the ADS7817 is in Binary Two’s

Complement format as shown in Table II. This table repre-

sents the ideal output code for the given input voltage and

does not include the effects of offset, gain error, or noise.

POWER DISSIPATION

The architecture of the converter, the semiconductor fabrica-

tion process, and a careful design allow the ADS7817 to

convert at up to a 200kHz rate while requiring very little

power. Still, for the absolute lowest power dissipation, there

are several things to keep in mind.

The power dissipation of the ADS7817 scales directly with

conversion rate. The first step to achieving the lowest power

dissipation is to find the lowest conversion rate that will

satisfy the requirements of the system.

In addition, the ADS7817 is in power down mode under two

conditions: when the conversion is complete and whenever

CS is HIGH (see Figure 1). Ideally, each conversion should

occur as quickly as possible, preferably, at a 3.2MHz clock

rate. This way, the converter spends the longest possible

time in the power down mode. This is very important as the

converter not only uses power on each DCLOCK transition

(as is typical for digital CMOS components) but also uses

some current for the analog circuitry, such as the compara-

tor. The analog section dissipates power continuously, until

the power down mode is entered.

Figure 6 shows the current consumption of the ADS7817

versus sample rate. For this graph, the converter is clocked

at 3.2MHz regardless of the sample rate—CS is HIGH for

the remaining sample period. Figure 7 also shows current

consumption versus sample rate. However, in this case, the

DCLOCK period is 1/16th of the sample period—CS is

HIGH for one DCLOCK cycle out of every 16.

FIGURE 4. ADS7817 Basic Timing Diagrams.

DESCRIPTION

ANALOG VALUE

Full Scale Input Span

2 • VREF

Least Significant 2 • VREF/4096

Bit (LSB)

+Full Scale VREF –1 LSB 0111 1111 1111 7FF

Midscale 0V 0000 0000 0000 000

Midscale – 1 LSB 0V – 1 LSB 1111 1111 1111 FFF

–Full Scale –VREF 1000 0000 0000 800

TABLE II. Ideal Input Voltages and Output Codes.

DIGITAL OUTPUT:

BINARY TWO’S COMPLEMENT

BINARY CODE HEX CODE

ADS7817 11

SBAS066A

DOUT

1.4V

Test Point

3kΩ

100pF

CLOAD

DOUT VOH

VOL

tdDO

thDO

DOUT

DCLOCK

VOH

VOL

VIL

DOUT

Test Point

tdis Waveform 2, ten

tdis Waveform 1

100pF

CLOAD

3kΩ

tdis

CS/SHDN

DOUT

Waveform 1(1)

DOUT

Waveform 2(2)

90%

10%

VIH

B11

ten

CS/SHDN

DCLOCK

VOL

DOUT

VCC

Load Circuit for tdDO, tr, and tfVoltage Waveforms for DOUT Rise and Fall Times tr, and tf

Voltage Waveforms for DOUT Delay Times, tdDO Load Circuit for tdis and tden

Voltage Waveforms for ten

FIGURE 5. Timing Diagrams and Test Circuits for the Parameters in Table I.

Voltage Waveforms for tdis

NOTES: (1) Waveform 1 is for an output with internal conditions such that

the output is HIGH unless disabled by the output control. (2) Waveform 2

is for an output with internal conditions such that the output is LOW unless

disabled by the output control.

1000

100

Supply Current (µA)

1 10 100 1000

Sample Rate (kHz)

= 25°C

= +5V

REF

= +2.5V

CLK

= 3.2MHz

FIGURE 6. Maintaining fCLK at the Highest Possible Rate

Allows Supply Current to Drop Directly with

Sample Rate.

FIGURE 7. Scaling fCLK Reduces Supply Current Only

Slightly with Sample Rate.

1000

100

Supply Current (µA)

1 10 100 1000

Sample Rate (kHz)

= 25°C

= +5V

REF

= +2.5V

CLK

= 16 • f

SAMPLE

ADS7817

12 SBAS066A

There is an important distinction between the power down

mode that is entered after a conversion is complete and the

full power down mode which is enabled when CS is HIGH.

While both power down the analog section, the digital section

is powered down only when CS is HIGH. Thus, if CS is left

LOW at the end of a conversion and the converter is continu-

ally clocked, the power consumption will not be as low as

when CS is HIGH. See Figure 8 for more information.

By lowering the reference voltage, the ADS7817 requires

less current to completely charge its internal capacitors on

both the analog input and the reference input. This reduction

in power dissipation should be weighed carefully against the

resulting increase in noise, offset, and gain error as outlined

in the Reference section.

FIGURE 8. Shutdown Current is Considerably Lower with

CS HIGH than when CS is LOW.

Supply Current (µA)

1 10 100 1000

Sample Rate (kHz)

= 25°C

= +5V

REF

= +2.5V

CLK

= 16 • f

SAMPLE

CS LOW

(GND)

CS = HIGH (V

)

SHORT CYCLING

Another way of saving power is to utilize the CS signal to

short cycle the conversion. Because the ADS7817 places the

latest data bit on the DOUT line as it is generated, the

converter can easily be short cycled. This term means that

the conversion can be terminated at any time. For example,

if only 8-bits of the conversion result are needed, then the

conversion can be terminated (by pulling CS HIGH) after

the 8th bit has been clocked out.

This technique can be used to lower the power dissipation in

those applications where an analog signal is being monitored

until some condition becomes true. For example, if the

signal is outside a predetermined range, the full 12-bit

conversion result may not be needed. If so, the conversion

can be terminated after the first n-bits, where n might be as

low as 3 or 4. This results in lower power dissipation in both

the converter and the rest of the system, as they spend more

time in the power down mode.

LAYOUT

For optimum performance, care should be taken with the

physical layout of the ADS7817 circuitry. This is particularly

true if the reference voltage is low and/or the conversion rate

is high. At 200kHz conversion rate, the ADS7817 makes a bit

decision every 312ns. That is, for each subsequent bit deci-

sion, the digital output must be updated with the results of the

last bit decision, the capacitor array appropriately switched

and charged, and the input to the comparator settled to a

12-bit level all within one clock cycle.

The basic SAR architecture is sensitive to spikes on the

power supply, reference, and ground connections that occur

just prior to latching the comparator output. Thus, during

any single conversion for an n-bit SAR converter, there are

n “windows” in which large external transient voltages can

easily affect the conversion result. Such spikes might origi-

nate from switching power supplies, digital logic, and high

power devices, to name a few. This particular source of error

can be very difficult to track down if the glitch is almost

synchronous to the converter’s DCLOCK signal—as the

phase difference between the two changes with time and

temperature, causing sporadic misoperation.

With this in mind, power to the ADS7817 should be clean

and well bypassed. A 0.1µF ceramic bypass capacitor should

be placed as close to the ADS7817 package as possible. In

addition, a 1 to 10µF capacitor and a 10Ω series resistor may

be used to lowpass filter a noisy supply.

The reference should be similarly bypassed with a 0.1µF

capacitor. Again, a series resistor and large capacitor can be

used to lowpass filter the reference voltage. If the reference

voltage originates from an op amp, be careful that the op-

amp can drive the bypass capacitor without oscillation (the

series resistor can help in this case). Keep in mind that while

the ADS7817 draws very little current from the reference on

average, there are higher instantaneous current demands

placed on the external reference circuitry.

Also, keep in mind that the ADS7817 offers no inherent

rejection of noise or voltage variation in regards to the

reference input. This is of particular concern when the

reference voltage is derived from the power supply. Any

noise and ripple from the supply that is not rejected by the

external reference circuitry will appear directly in the digital

results. While high frequency noise can be filtered out as

described in the previous paragraph, voltage variation due to

line frequency (50Hz or 60Hz) can be difficult to remove.

The GND pin on the ADS7817 should be placed on a clean

ground point. In many cases, this will be the “analog”

ground. Avoid connecting the GND pin too close to the

grounding point for a microprocessor, microcontroller, or

digital signal processor. If needed, run a ground trace di-

rectly from the converter to the power supply connection

point. The ideal layout will include an analog ground plane

for the converter and associated analog circuitry.

ADS7817 13

SBAS066A

APPLICATION CIRCUITS

Figures 9, 10 and 11 show some typical applications circuits

for the ADS7817. Figure 9 shows a low cost, low power

circuit for basic data acquisition. Total power dissipation in

the ADS7817 and reference circuitry is under 5mW over

temperature, power supply variations, and at a 200kHz sample

rate.

Figure 10 is a motor control application using three ISO130s

to isolate the motor from the sensing system (three ADS7817s

and a DSP56004). The ISO130 provides 10kV/µs (minimum)

isolation-mode rejection, 85kHz large signal bandwidth, and

a fixed gain of 8. The ADS7817’s reference voltage is 1.2V

and is derived from a REF1004-1.2. This gives the converter

a full-scale input range of ±1.2V. Because of the gain of 8 in

the ISO130, the current sense resistor should give a worst-

case output voltage of less than ±150mV.

Figure 11 is a similar application that isolates the digital

outputs of the three ADS7817s instead of the analog signal

from the motor. Here, the reference voltage for the ADS7817

is 150mV, and the analog input of each ADS7817 is con-

nected directly to the current sense resistor. By removing the

ISO130 from the signal path, a greater signal-to-noise ratio is

achieved in the sensing system. However, nine optical isola-

tors are needed to isolate the A/D converters.

FIGURE 9. Low Cost, Low Power Data Acquisition System.

ADS7817

OUT

DCLOCK

REF

+In

–In

GND

5Ω to 10Ω

22Ω

24.9kΩ

REF1004-2.5 1µF to

10µF

1µF to

10µF

0.1µF

4.7µF

Microcontroller

+5V

ADS7817

14 SBAS066A

FIGURE 10. Motor Control Using the ISO130, ADS7817, and DSPS6004.

78L05

SENSE

from

PWM

from

PWM

First Motor

Leg Driver

AC Motor

–

(Several

Hundred

Volts)

0.1µF

ISO1

+5V

GND1

System

GND System

GND

CLK

CS/SHDN

OUT

SCKT

SDO 0

SDI 1

SDI 0

MOSI/HA 0

ISO130

• • •

+–

+5V

System

GND

200Ω

200ΩSD02

SS/HA2

HV+

(Several

Hundred

Volts)

0.01µF

ADS7817

0.01µF

78L05

0.1µF

ISO2

GND2

System

GND System

GND

OUT

CLK

CS/SHDN

ISO130

to 2nd Motor

Leg Driver

+5V

200Ω

ADS7817

0.01µF

78L05

0.1µF

ISO3

GND3

System

GND System

GND

OUT

CLK

CS/SHDN

ISO130

to 3rd Motor

Leg Driver

+5V

200Ω

ADS7817

0.01µF

REF1004-1.2

0.1µF

5µF

1kΩ

+5V

REF1004-1.2

0.1µF

5µF

1kΩ

+5V

REF1004-1.2

0.1µF

5µF

1kΩ

WST

Motorola

DSPS6004

WSR

SCKR

SCK/SCL

ADS7817 15

SBAS066A

FIGURE 11. Motor Control Using an Isolated ADS7817.

SENSE

from

PWM

from

PWM

AC Motor

1st Motor Leg

To 3rd Motor

Leg

To 2nd Motor

Leg

OUT

CLK

200Ω

ADS7817

ISO1

REF

Opto-Couplers

(1)

NOTE: (1) Suggested Opto-couplers are HCPL-2611 or

HCPL-7611. Inverters or buffers will be needed to drive

these devices. See the appropriate Hewlett-Packard data

sheet for more information.

REF1004-1.2

+5V

768Ω

301Ω+150mV

43.2Ω

4.7µF

0.01µF

4.7µF

0.1µF

WST

Motorola

DSP56004

SDO0

SDO1

SDO2

SCKT

SCKR

SDI0

SDI1

WSR

SCK/SCL

MISO/SDA

MOSI/HA0

HREQ

SS/HA2

PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

ADS7817E/250 ACTIVE MSOP DGK 8 250 Green (RoHS &