To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.com April 1st, 2010 Renesas Electronics Corporation Issued by: Renesas Electronics Corporation (http://www.renesas.com) Send any inquiries to http://www.renesas.com/inquiry. Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. 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Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. SH-2E SH7059 F-ZTATTM, SH7058S F-ZTATTM Hardware Manual Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7000 Series Rev.5.00 2010.02 Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. 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Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. Rev. 5.00 Feb. 24, 2010 Page ii of xciv REJ09B0177-0500 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions may occur due to the false recognition of the pin state as an input signal. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different type number, confirm that the change will not lead to problems. The characteristics of MPU/MCU in the same group but having different type numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different type numbers, implement a system-evaluation test for each of the products. Rev. 5.00 Feb. 24, 2010 Page iii of xciv REJ09B0177-0500 Rev. 5.00 Feb. 24, 2010 Page iv of xciv REJ09B0177-0500 Preface The SH7059/SH7058S is a single-chip RISC (reduced instruction set computer) microcomputer that has the 32-bit internal architecture CPU, SH-2E, as its core, and also includes peripheral functions necessary for system configuration. This LSI is equipped with on-chip peripheral functions necessary for system configuration, including a floating-point unit (FPU), large-capacity ROM and RAM, a direct memory access controller (DMAC), timers, a serial communication interface (SCI), controller area network (HCAN), A/D converter, and I/O ports, therefore, it can be used as a microprocessor built in a high-level control system. This LSI is an F-ZTAT* (Flexible Zero Turn-Around Time) version with flash memory as its on-chip ROM, and it can rapidly and flexibly deal with each situation on an application system with fluid specifications from an early stage of mass production to full-scale production. Note: * F-ZTAT is a trademark of Renesas Technology, Corp. Target users: This manual was written for users who will be using the SH7059 F-ZTAT and SH7058S F-ZTAT in the design of application systems. Users of this manual are expected to understand the fundamentals of electrical curcuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of the SH7059 F-ZTAT and SH7058S F-ZTAT to the above users. Refer to the SH-2E Software Manual for a detailed description of the instruction set. Notes on reading this manual: * In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics. * In order to understand the details of the CPU's functions Read the SH-2E Software Manual. Rule: Bit order: The MSB (most significant bit) is on the left and the LSB (least significant bit) is on the right. Releated Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/ SH7059 F-ZTAT and SH7058S F-ZTAT Manuals: Document Title Document No. SH-2E SH7059 F-ZTATTM, SH7058S F-ZTATTM Hardware Manual This manual SH-2E Software Manual REJ09B0316-0200 Rev. 5.00 Feb. 24, 2010 Page v of xciv REJ09B0177-0500 User's Manuals for Development Tools: Document Title Document No. SuperHTM RISC engine C/C++ Compiler, Assembler, Optimizing Linkage Editor User's Manual REJ10B0047-0100H SuperHTM RISC engine Simulator/Debugger User's Manual REJ10B0210-0400 SuperHTM RISC engine Simulator/Debugger (for SPARC solaris, HP9000 Series 700) User's Manual ADE-702-203 High-performance Embedded Workshop V.4.03 User's Manual REJ10J1586-0100 High-performance Embedded Workshop V.4.04 User's Manual REJ10J1737-0100 Application note: Document Title Document No. C/C++ Compiler REJ05B0463-0400 All trademarks and registered trademarks are the property of their respective owners. Rev. 5.00 Feb. 24, 2010 Page vi of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) All SH7058S/SH7059 All Synchronous serial communication unit (SSU) added 1.1 Features 1.1 Features Table 1.1 SH7058 Features Table 1.1 SH7059 Features 3,4 CPG/PLL, INTC, DMAC, and AUD amended Clock pulse generator (CPG/PLL) Clock pulse generator (CPG/PLL) * On-chip clock-multiplication PLL circuit (x 4, x 8) Interrupt controller (INTC) * On-chip clock-multiplication PLL circuit ( x 8) Interrupt controller (INTC) * 117 internal interrupt sources (ATU-II x 75, SCI x 20, DMAC x 4, A/D x 5, WDT x 1, UBC x 1, CMT x 2, HCAN-II x 8, H-UDI x 1) * 123 internal interrupt sources (ATU-II x 75, SCI x 20, DMAC x 4, A/D x 5, WDT x 1, UBC x 1, CMT x 2, HCAN-II x 8, H-UDI x 1, SSU x 6) Direct memory access controller (DMAC) (4 channels) Direct memory access controller (DMAC) (4 channels) * * DMA transfer requests by on-chip modules SCI, A/D converter, ATU-II, HCAN-II DMA transfer requests by on-chip modules SCI, A/D converter, ATU-II, HCAN-II, SSU Synchronous serial communication unit (SSU) (2 channels) * * * * * * * * Advanced user debugger (AUD) * RAM monitor mode Data input/output frequency: 10 MHz or less Support for master mode Synchronous serial communications with devices having a different clock phase or polarity Choice of 8/16/32-bit width of transmit/receive data Full-duplex communication capability Continuous serial communications Choice of LSB-first or MSB-first transfer Choice of clock source from among seven internal clocks Five interrupt sources Advanced user debugger (AUD) * RAM monitor mode Data input/output frequency: 1/8 or less of the internal operating frequency () Rev. 5.00 Feb. 24, 2010 Page vii of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 1.1 Features 1.1 Features Table 1.1 SH7058 Features Table 1.1 SH7059 Features 6,7 ROM, and RAM amended ROM ROM * 1-MB flash memory * * 1-MB divided into 16 blocks Small blocks: 4 kB x 8 Medium block: 96 kB x 1 Large blocks: 128 kB x 7 * Flash memory: Divided into 16 blocks SH7058S * 1-MB flash memory 1-MB divided into 16 blocks 1-MB divided into 16 blocks 4KB x 8 blocks 96KB x 1 block 128KB x 7 blocks SH7059 Small blocks: 4 kB x 8 Medium block: 96 kB x 1 Large blocks: 128 kB x 7 * RAM emulation function (using 4 kB small block) 1MB Flash memory (SH7058S), 1.5MB Flash memory (SH7059) * RAM emulation function (using 4 KB RAM RAM * * 48 kB SRAM 4KB x 8 blocks 96KB x 1 block 128KB x 3 blocks 256KB x 4 blocks 48KB (SH7058S), 80KB (SH7059) SRAM 1.2 Block Diagram 1.2 Block Diagram Figure 1.1 Block Diagram Figure 1.1 Block Diagram 7 Figure amended Port/control signals Port/control signals PF15/BREQ PF15/BREQ/SCS0 PF14/BACK PF14/BACK/SCS1 ROM (Flash) ROM (Flash) 1MB 1.5MB (SH7059) 1.0MB (SH7058S) RAM 48 kB RAM 80KB (SH7059) 48KB (SH7058S) SCI (5 channels) SCI (5 channels) SSU (2 channels) HCAN-II (2 channels) Rev. 5.00 Feb. 24, 2010 Page viii of xciv REJ09B0177-0500 block) HCAN-II (2 channels) Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 1.2 Block Diagram 1.2 Block Diagram Figure 1.1 Block Diagram Figure 1.1 Block Diagram 7 Figure amended Port Port PL7/SCK2 SSCK1/PL7/SCK2 PL12/IRQ4 SCS0/PL12/IRQ4 PL13/IRQOUT SCS1/PL13/IRQOUT PA14/TxD0 PA14/TxD0/SSO0 PA15/RxD0 PA15/RxD0/SSI0 PB13/SCK0 PB13/SCK0/SSCK0 PB15/PULS5/SCK2 PB15/PULS5/SCK2/SSCK1 PC2/TxD2 PC2/TxD2/SSO1 PC3/RxD2 PC3/RxD2/SSI1 XTAL Clock pulse generator XTAL Clock pulse generator Peripheral address bus (9 bits) Peripheral address bus (19 bits) 1.3.1 Pin Arrangement 1.3.1 Pin Arrangement Figure 1.2 Pin Arrangement (FP-256H) Figure 1.2 Pin Arrangement 8 Pin name added 45 PF14/BACK 45 SCS0/PF14/BACK 46 PF15/BREQ 46 SCS1/PF15/BREQ 143 PA14/TxD0 143 PA14/TxD0/SSO0 144 PA15/RxD0 144 PA15/RxD0/SSI0 160 PB13/SCK0 160 PB13/SCK0/SSCK0 164 PB15/PULS5/SCK2 164 PB15/PULS5/SCK2/SSCK1 167 PC2/TxD2 167 PC2/TxD2/SSO1 168 PC3/RxD2 168 PC3/RxD2/SSI1 223 PL7/SCK2 223 SSCK1/PL7/SCK2 230 PL12/IRQ4 230 SCS0/PL12/IRQ4 231 PL13/IRQOUT 231 SCS1/PL13/IRQOUT Figure 1.3 Pin Assignments Figure 1.3 Pin Arrangement (BP-272) 9 Pin name added C13 PF15/BREQ C13 PF15/BREQ/SCS1 D12 PF14/BACK D12 PF14/BACK/SCS0 K1 PL13/IRQOUT K1 PL13/IRQOUT/SCS1 K2 PL12/IRQ4 K2 PL12/IRQ4/SCS0 M3 PL7/SCK2 M3 PL7/SCK2/SSCK1 U10 PC3/RxD2 U10 PC3/RxD2/SSI1 U12 PB15/PULS5/SCK2 U12 PB15/PULS5/SCK2/SSCK1 W10 PC2/TxD2 W10 PC2/TxD2/SSO1 Y12 PB13/SCK0 Y12 PB13/SCK0/SSCK0 Rev. 5.00 Feb. 24, 2010 Page ix of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 1.3.2 Pin Functions 1.3.2 Pin Functions Table 1.2 Pin Functions Table 1.2 Pin Functions 11 Table amended Pin No. Pin No. Type Symbol Clock XTAL FP-256H 53 BP-272 A15 I/O Type Symbol FP-256H BP-272 I/O Clock XTAL 53 A15 Input/ output Input Synchronous Serial Communication Unit (SSU) added SSO0, SSO1, SSI0, SSI1, SSCK0, SSCK1, SCS0, SCS1 1.3.3 Pin Assignments 1.3.3 Pin Assignments Table 1.3 Pin Assignments Table 1.3 Pin Assignments 20, 23, 24, 26 Table amended Pin No. Pin No. FP-256H BP-272 MCU Mode 33 C9 PF4/A20 A20 NC 34 C10 PF5/A21/POD A21 PF5/A21/POD NC 45 D12 PF14/BACK/SCS0 NC PF14/BACK NC 46 C13 PF15/BREQ/SCS1 Vcc C13 PF15/BREQ Vcc Y17 PA14/TxD0 FP-256H BP-272 MCU Mode Programmer Mode 33 C9 PF4/A20 34 C10 45 D12 46 143 Programmer Mode 143 Y17 PA14/TxD0/SSO0 144 Y16 PA15/RxD0/SSI0 NC NC 160 Y12 PB13/SCK0/SSCK0 NC NC 144 Y16 PA15/RxD0 NC 164 U12 PB15/PULS5/SCK2/SSCK1 NC 160 Y12 PB13/SCK0 NC 167 W10 PC2/TxD2/SSO1 NC 164 U12 PB15/PULS5/SCK2 NC 168 U10 PC3/RxD2/SSI1 NC 223 M3 PL7/SCK2/SSCK1 167 W10 PC2/TxD2 NC 230 K2 PL12/IRQ4/SCS0 OE 231 K1 PL13/IRQOUT/SCS1 NC 168 U10 PC3/RxD2 NC NC 223 M3 PL7/SCK2 230 K2 PL12/IRQ4 OE 231 K1 PL13/IRQOUT NC NC 2.3.1 RISC-type Instruction Set 2.3.1 RISC-type Instruction Set One Instruction per Cycle: One Instruction per Cycle 35 Description amended The microprocessor can execute basic instructions in one cycle using the pipeline system. Instructions are executed in 25 ns at 40 MHz. The microprocessor can execute basic instructions in one cycle using the pipeline system. Instructions are executed in 12.5 ns at 80 MHz. Rev. 5.00 Feb. 24, 2010 Page x of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 2.5.1 State Transitions 2.5.1 State Transitions Figure 2.8 Transitions between Processing States Figure 2.8 Transitions between Processing States 59 Figure amended From any state when RES = 0 and HSTBY = 1 From any state when RES = 0 and HSTBY = 1 RES = 0 HSTBY = 1 Power-on reset state Power-on reset state RES = 1 When an interrupt source or DMA address error occurs Exception processing state Bus request cleared Exception processing source occurs Bus request generated Exception processing state Bus request cleared NMI interrupt source occurs Bus request generated Bus request generated NMI pin 0 1 RES = 1 When an interrupt source or DMA address error occurs Bus release state RES = 0 HSTBY = 1 Bus request generated Exception processing ends Bus request cleared Bus request cleared Bus request generated Bus request generated Program execution state SBY bit cleared for SLEEP instruction Exception processing ends Bus request cleared Bus request cleared Program execution state SBY bit cleared for SLEEP instruction SBY bit set for SLEEP instruction Sleep mode Exception processing source occurs Bus release state Software standby mode SBY bit set for SLEEP instruction Sleep mode Hardware standby mode Software standby mode Hardware standby mode Power-down state From any state when RES = 0 and HSTBY = 0 Power-down state From any state when RES = 0 and HSTBY = 0 Note: An internal reset due to the WDT causes a transition from the program execution state or sleep mode to the exception processing state. Note: An internal reset due to the WDT causes a transition from the program execution state or sleep mode to the exception processing state. 5.1 Overview 5.1 Overview 73 Description amended The internal clock signal (), with frequency either four or eight times the frequency of the clock signal input from the EXTAL pin, is mainly supplied to the bus master modules. The internal clock signal (), with frequency eight times the frequency of the clock signal input from the EXTAL pin, is mainly supplied to the bus master modules. 5.1.1 Block Diagram 5.1.1 Block Diagram Figure 5.1 Block Diagram of Clock Pulse Generator Figure 5.1 Block Diagram of Clock Pulse Generator 73 Figure amended SYSCR1, Oscillation stop detection circuit, and On-chip oscillator circuit deleted XTAL Oscillator circuit XTAL Oscillator circuit PLL multiplier circuit Internal clock () PLL multiplier circuit Internal clock () X8 X 4 or X 8 5.1.2 Pin Configuration 5.1.2 Pin Configuration Table 5.1 CPG Pins Table 5.1 CPG Pins 74 Table amended Pin Name Abbreviation I/O Pin Name Abbreviation I/O Crystal XTAL Input Crystal XTAL Input/output Rev. 5.00 Feb. 24, 2010 Page xi of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 5.1.3 Related Register 5.1.3 Related Register Table 5.2 CPG Register Table 5.2 CPG Register 74 Deleted 5.2.1 Frequency Ranges 5.2.1 Frequency Ranges Table 5.3 Input Frequency and Operating Frequency Table 5.2 Input Frequency and Operating Frequency 75 Table amended Description of x 4 version (PLL Multiplication Factor) deleted Description amended The internal clock signal (), with frequency either four or eight times the frequency of the clock signal input from the EXTAL pin, is mainly supplied to the bus master modules such as CPU, FPU, and DMAC. The internal clock signal (), with frequency eight times the frequency of the clock signal input from the EXTAL pin, is mainly supplied to the bus master modules such as CPU, FPU, and DMAC. Figure 5.2 Frequencies and Phases of Clock Signals Figure 5.2 Frequencies and Phases of Clock Signals Figure amended Description of internal clock () = input clock x 4 deleted 5.2.2 Clock Selection 5.2.2 Clock Selection 75,76 Deleted 5.2.3 Notes on Register Access 5.2.3 Notes on Register Access Figure 5.3 Writing to SYSCR2 Figure 5.3 Writing to SYSCR2 76, 77 Deleted 5.4 Oscillation Stop Detection Function Deleted 79 - 81 6.1.1Types of Exception Processing and Priority 6.1.1Types of Exception Processing and Priority Table 6.1 Types of Exception Processing and Priority Order Table 6.1 Types of Exception Processing and Priority Order 85 On-chip peripheral modules: Synchronous serial communication unit (SSU) added Exception Source Interrupt On-chip peripheral modules: Exception Source Interrupt On-chip peripheral modules: Serial communication interface (SCI) Serial communication interface (SCI) Synchronous serial communication unit (SSU) Controller area network 0 (HCAN0) Controller area network 0 (HCAN0) 6.2.2 Power-On Reset 6.2.2 Power-On Reset 90 Description amended Power-On Reset by Means of RES Pin: When the RES pin is driven low, the chip enters the power-on reset state. To reliably reset the chip, the RES pin should be kept at the low level for at least the duration of the oscillation settling time at power-on or when in standby mode (when the clock is halted), or at least 20 tcyc when the clock is running. In the power-on reset state, the CPU's internal state and all the on-chip peripheral module registers are initialized. Power-On Reset by Means of RES Pin: When the RES pin is driven low, the chip enters the power-on reset state. To reliably reset the chip, the RES pin should be kept at the low level for at least the duration of the oscillation settling time at power-on or when in standby mode (when the clock is halted), or at least 10 tcyc when the clock is running. In the power-on reset state, the CPU's internal state and all the on-chip peripheral module registers are initialized. 6.4.1 Interrupt Sources 6.4.1 Interrupt Sources Table 6.7 Interrupt Sources Table 6.7 Interrupt Sources 93 Synchronous serial communication unit (SSU) added Rev. 5.00 Feb. 24, 2010 Page xii of xciv REJ09B0177-0500 Type Request Source Number of Sources On-chip peripheral module Synchronous communication unit (SSU) 6 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 6.8.2 Value of Vector Base Register (VBR) 6.8.2 Value of Vector Base Register (VBR) 99 Description amended The value of the vector base register must always be a multiple of four. If it is not, an address error will occur when the stack is accessed during exception processing. The value of the vector base register must always be a multiple of four. If it is not, an address error will occur when the vector table is accessed during exception processing. 7.1.2 Block Diagram 7.1.2 Block Diagram Figure 7.1 INTC Block Diagram Figure 7.1 INTC Block Diagram 102 SSU interrupt request added to CPU/DMAC request judgment 7.2.5 On-Chip Peripheral Module Interrupts 7.2.5 On-Chip Peripheral Module Interrupts 105 Synchronous communication unit (SSU) added 7.2.6 Interrupt Exception Vectors and Priority Rankings 7.2.6 Interrupt Exception Vectors and Priority Rankings Table 7.3 Interrupt Exception Processing Vectors and Priorities Table 7.3 Interrupt Exception Processing Vectors and Priorities 113, 114 Interrupt Source: SSU added Interrupt Source Interrupt Source Interrupt Source SCI0 ERI0 SCI0/ SSU0* RXI0 ERI0/ SSERI0 RXI0/ SSRXI0 TXI0 SCI2 ERI2 TXI0/ SSTSI0 RXI2 TXI2 SCI2/ SSU1* ERI2/ SSERI1 RXI2/ SSRXI1 TXI2/ SSTSI1 7.3.1 Interrupt Priority Registers A-L (IPRA-IPRL) 7.3.1 Interrupt Priority Registers A-L (IPRA-IPRL) Table 7.4 Interrupt Request Sources and IPRA-IPRL Table 7.4 Interrupt Request Sources and IPRA-IPRL 116 Table amended Bits Bits Register Interrupt priority register K 15-12 SCI0 7-4 SCI2 Register 15-12 7-4 Interrupt priority register K SCI0/SSU0* SCI2/SSU1* 7.3.1 Interrupt Priority Registers A-L (IPRA-IPRL) 7.3.1 Interrupt Priority Registers A-L (IPRA-IPRL) 116 Description amended If multiple on-chip peripheral modules are assigned to the same bit (DMAC0 and DMAC1, DMAC2 and DMAC3, CMT0, A/D0, and MTAD0, and CMT1, A/D1, and MTAD1), those multiple modules are set to the same priority rank. If multiple on-chip peripheral modules are assigned to the same bit (DMAC0 and DMAC1, DMAC2 and DMAC3, CMT0, A/D0, and MTAD0, CMT1, A/D1, and MTAD1, SCI0 and SSU0*, and SCI2 and SSU1*), those multiple modules are set to the same priority rank. IPRA-IPRL are initialized to H'0000 by a reset and in hardware standby mode. They are not initialized in software standby mode. IPRA-IPRL are initialized to H'0000 by a reset, in hardware standby mode and in software standby mode. 7.3.3 IRQ Status Register (ISR) 7.3.3 IRQ Status Register (ISR) 118 Description amended A reset and hardware standby mode initialize ISR but software standby mode does not. A reset, hardware standby mode and software standby mode initialize ISR . Rev. 5.00 Feb. 24, 2010 Page xiii of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 7.5 Interrupt Response Time 7.5 Interrupt Response Time Table 7.5 Interrupt Response Time (Multiplication Ratio of 8) Table 7.5 Interrupt Response Time 122 Table amended Number of States Peripheral Module Item Synchronizing input signal 0 or 6 (synchronized with peripheral [0 or 3] clock P) with internal clock and DMAC activation judgment Number of States NMI IRQ Notes 1 to 4 [1 or 2] 6 to 9 [3 to 5] For the number of states required for each interrupt, see the note (*) below. The values enclosed in [ ] are values for when the multiplication ratio is 4. Item Peripheral Module NMI IRQ Notes Synchronizing input signal (synchronized with peripheral clock P ) with internal clock and DMAC activation judgment 0 or 6 1 to 4 6 to 9 For the number of states required for each interrupt, see the note below. 8.2.1 User Break Address Register (UBAR) 8.2.1 User Break Address Register (UBAR) 128 Description amended UBARH and UBARL are initialized to H'0000 by a power-on reset and in module standby mode. They are not initialized in software standby mode. UBARH and UBARL are initialized to H'0000 by a power-on reset, in module standby mode, and in software standby mode. 8.2.2 User Break Address Mask Register (UBAMR) 8.2.2 User Break Address Mask Register (UBAMR) 129 Description amended UBAMRH and UBAMRL are initialized to H'0000 by a power-on reset and in module standby mode. They are not initialized in software standby mode. UBAMRH and UBAMRL are initialized to H'0000 by a power-on reset, in module standby mode, and in software standby mode. 8.2.3 User Break Bus Cycle Register (UBBR) 8.2.3 User Break Bus Cycle Register (UBBR) 130 Description amended UBBR is initialized to H'0000 by a power on reset and in module standby mode. It is not initialized in software standby mode. UBBR is initialized to H'0000 by a power on reset, in module standby mode, and in software standby mode. 8.2.4 User Break Control Register (UBCR) 8.2.4 User Break Control Register (UBCR) 132 Description amended UBCR is initialized to H'0000 by a power-on reset and in module standby mode. It is not initialized in software standby mode. UBCR is initialized to H'0000 by a power-on reset, in module standby mode, and in software standby mode. Bits 2 and 1--Clock Select 1 and 0 (CKS1, CKS0) Bits 2 and 1--Clock Select 1 and 0 (CKS1, CKS0) Bits 2 and 1--Clock Select 1 and 0 (CKS1, CKS0): These bits specify the pulse width of the UBCTRG signal output in the event of a condition match. Bit 2: CKS1 Bit 1: CKS0 Description 0 0 When the internal clock is four times an input clock, UBCTRG pulse width is /2 When the internal clock is eight times an input clock, UBCTRG pulse width is /4 (Initial value) Notes: : Internal clock Bit 2: CKS1 Bit 1: CKS0 Description 0 0 UBCTRG pulse width is /4 (Initial value) Notes: : Internal clock See section 8.5.7, Internal Clock () Multiplication Ratio and UBCTRG Pulse Width. 8.5.7 Internal Clock () Multiplication Ratio and UBCTRG Pulse Width 8.5.7 Internal Clock () Multiplication Ratio and UBCTRG Pulse Width 140 Deleted 9.1.2 Block Diagram 9.1.2 Block Diagram Figure 9.1 BSC Block Diagram Figure 9.1 BSC Block Diagram 142 Bus arbitration control unit added BREQ BACK Rev. 5.00 Feb. 24, 2010 Page xiv of xciv REJ09B0177-0500 Bus arbitration control unit Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 9.1.4 Register configuration 9.1.4 Register configuration 143 Description amended All registers are 16 bits. All BSC registers are all initialized by a power-on reset and in hardware standby mode. Values are retained in a manual reset and in software standby mode. All registers are 16 bits. All BSC registers are all initialized by a power-on reset and in hardware standby mode. Values are retained in a manual reset . 9.1.5 Address Map 9.1.5 Address Map Table 9.3 Address Map Table 9.3 Address Map (SH7058S) 145 Table deleted * Number of Access Cycles for On-Chip Peripheral Module Registers Table 9.4 Address Map (SH7059) Newly added Table 9.5 Number of Access Cycles for Peripheral Module registers Newly added 9.2.1 Bus Control Register 1 (BCR1) 9.2.1 Bus Control Register 1 (BCR1) 146 Description amended BCR1 is initialized to H'000F by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. BCR1 is initialized to H'000F by a power-on reset and in hardware standby mode, and in software standby mode. It is not initialized by a manual reset . 9.2.2 Bus Control Register 2 (BCR2) 9.2.2 Bus Control Register 2 (BCR2) 148 Description amended BCR2 is initialized to H'FFFF by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. BCR2 is initialized to H'FFFF by a power-on reset and in hardware standby mode, and in software standby mode. It is not initialized by a manual reset . 9.2.3 Wait Control Register (WCR) 9.2.3 Wait Control Register (WCR) 151 Description amended WCR is initialized to H'7777 by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. WCR is initialized to H'7777 by a power-on reset and in hardware standby mode, and in software standby mode. It is not initialized by a manual reset . 9.2.4 RAM Emulation Register (RAMER) 9.2.4 RAM Emulation Register (RAMER) 152 Description amended RAMER is initialized to H'0000 by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. RAMER is initialized to H'0000 by a power-on reset and in hardware standby mode, in software standby mode. It is not initialized by a manual reset . * SH7059 Newly added 10.1.2 Block Diagram 10.1.2 Block Diagram Figure 10.1 DMAC Block Diagram Figure 10.1 DMAC Block Diagram 165 Figure amended SSU0*, SSU1* Request priority control 10.2.4 DMA Channel Control Registers 0-3 (CHCR0-CHCR3) 10.2.4 DMA Channel Control Registers 0-3 (CHCR0-CHCR3) 172 Table amended Bit 20: RS4 Bit 19: RS3 Bit 18: RS2 Bit 17: RS1 Bit 16: RS0 Description 0 1 1 1 0 No request* 1 0 0 0 0 No request* 1 1 1 0 1 No request* 1 1 1 1 0 No request* Bit 20: RS4 Bit 19: RS3 Bit 18: RS2 Bit 17: RS1 Bit 16: RS0 Description 0 1 1 1 0 SSU0 transmission* 1 0 0 0 0 SSU0 reception* 1 1 1 0 1 SSU1 transmission* 1 1 1 1 0 SSU1 reception* Rev. 5.00 Feb. 24, 2010 Page xv of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 10.3.2 DMA Transfer Requests 10.3.2 DMA Transfer Requests 179 - 182 Description amended On-Chip Peripheral Module Request Mode: In this mode a transfer is performed at the transfer request signal (interrupt request signal) of an on-chip peripheral module. As indicated in table 10.2, there are 26 transfer request signals: 12 from the advanced timer unit (ATU-II), which are compare match or input capture interrupts; the receive data full interrupts (RXI) and transmit data empty interrupts (TXI) of the five serial communication interfaces (SCI); the receive interrupt of HCAN0; and the A/D conversion end interrupts (ADI) of the three A/D converters. When DMA transfers are enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0), a transfer is performed upon the input of a transfer request signal. On-Chip Peripheral Module Request Mode: In this mode a transfer is performed at the transfer request signal (interrupt request signal) of an on-chip peripheral module. As indicated in table 10.2, there are 26 transfer request signals: 12 from the advanced timer unit (ATU-II), which are compare match or input capture interrupts; the receive data full interrupts (RXI) and transmit data empty interrupts (TXI) of the five serial communication interfaces (SCI); the receive interrupt of HCAN0; and the A/D conversion end interrupts (ADI) of the three A/D converters; the receiver data full interrupts (SSRXI), transmit data empty or transmit end interrupts (SSTSI) from two synchronous serial communication unit (SSU). When DMA transfers are enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0), a transfer is performed upon the input of a transfer request signal. When the transfer request is set to RXI (transfer request because the SCI's receive data register is full), the transfer source must be the SCI's receive data register (RDR). When the transfer request is set to TXI (transfer request because the SCI's transmit data register is empty), the transfer destination must be the SCI's transmit data register (TDR). If the transfer request is set to the A/D converter, the data transfer source must be the A/D converter register; if set to HCAN0, the transfer source must be HCAN0 message data. When the transfer request is set to RXI (transfer request because the SCI's receive data register is full), the transfer source must be the SCI's receive data register (RDR). When the transfer request is set to TXI (transfer request because the SCI's transmit data register is empty), the transfer destination must be the SCI's transmit data register (TDR). If the transfer request is set to the A/D converter, the data transfer source must be the A/D converter register; if set to HCAN0, the transfer source must be HCAN0 message data. If the transfer request by the receive data full of the SSU (SSRXI) is selected, the transfer destination must be the SS receive data register (SSRDR) of the SSU. If the transmit data empty or transmit end of the SSU (SSTSI) is selected, the transfer destination must be the SS transmit data register (SSTDR) of the SSU. Rev. 5.00 Feb. 24, 2010 Page xvi of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 10.3.2 DMA Transfer Requests 10.3.2 DMA Transfer Requests Table 10.2 Selecting On-Chip Peripheral Module Request Modes with the RS Bits Table 10.2 Selecting On-Chip Peripheral Module Request Modes with the RS Bits 180, 181 Table and legend amended SSU0 transmit block, SSU0 receive block, SSU1 transmit block, and SSU1 receive block added. Legend: Description of SSU0,SSU1 added DMAC Transfer Request Source DMAC Transfer Request Signal Transfer Source Transfer Destination DMAC Transfer Request Source DMAC Transfer Request Signal RS4 RS3 RS2 RS1 RS0 Bus Mode RS4 RS3 RS2 RS1 RS0 0 0 0 0 1 SCI0 transmit block TXI0 (SCI0 transmitdata-empty transfer request) Don't care* TDR0 Burst/cyclesteal 0 0 0 0 1 1 0 SCI0 receive block 1 0 SCI0 receive block RXI0 (SCI0 receivedata-full transfer request) RDR0 Don't care* Burst/cyclesteal 1 SCI1 transmit block TXI1 (SCI1 transmitdata-empty transfer request) SCI1 transmit block TXI1 (SCI1 transmitdata-empty transfer request) Don't care* 0 SCI1 receive block RXI1 (SCI1 receivedata-full transfer request) RDR1 Don't care* Burst/cyclesteal 1 SCI2 transmit block TXI2 (SCI2 transmitdata-empty transfer request) Don't care* TDR2 Burst/cyclesteal 0 SCI2 receive block RXI2 (SCI2 receivedata-full transfer request) RDR2 Don't care* Burst/cyclesteal SCI3 transmit block TXI3 (SCI3 transmitdata-empty transfer request) Don't care* 1 1 0 1 1 1 0 0 0 1 0 Burst/cyclesteal TDR3 RDR3 SCI4 transmit block TXI4 (SCI4 transmitdata-empty transfer request) Don't care* 0 SCI4 receive block RXI4 (SCI4 receivedata-full transfer request) RDR4 Don't care* Burst/cyclesteal 1 A/D0 ADI0 (A/D0 conversion end interrupt) ADDR0- ADDR11 Don't care* Burst/cyclesteal ADI1 (A/D1 conversion end interrupt) ADDR12- ADDR23 Don't care* ADI2 (A/D2 conversion end interrupt) ADDR24- ADDR31 1 A/D1 A/D2 Don't care* TDR4 1 0 Burst/cyclesteal RXI3 (SCI3 receivedata-full transfer request) 0 1 1 HCAN0 Burst/cyclesteal 1 1 1 0 0 1 Don't care* Burst/cyclesteal RM0 (HCAN0 receive interrupt) MB0-MB15 Don't care* DMAC Transfer Request Signal Transfer Source Transfer Destination RS2 RS1 RS0 1 0 0 0 1 ATU-II ICI0A (ICR0A input capture generation) Don't care* Don't care* Burst/cyclesteal 1 0 ATU-II ICI0B (ICR0B input capture generation) Don't care* Don't care* Burst/cyclesteal 1 ATU-II ICI0C (ICR0C input capture generation) Don't care* Don't care* Burst/cyclesteal 0 ATU-II ICI0D (ICR0D input capture generation) Don't care* Don't care* Burst/cyclesteal 1 1 0 0 1 1 0 ATU-II CMI6A (CYLR6A compare-match generation) Don't care* Don't care* 0 Burst/cyclesteal RS3 1 0 Burst/cyclesteal RS4 0 0 Burst/cyclesteal DMAC Transfer Request Source 1 0 1 1 1 0 1 SCI3 receive block 1 1 TDR1 Bus Mode ATU-II CMI6B (CYLR6B compare-match generation) Don't care* Don't care* Burst/cyclesteal 1 ATU-II CMI6C (CYLR6C compare-match generation) Don't care* Don't care* Burst/cyclesteal 0 ATU-II CMI6D (CYLR6D compare-match generation) Don't care* Don't care* Burst/cyclesteal 1 ATU-II CMI7A (CYLR7A compare-match generation) Don't care* Don't care* Burst/cyclesteal 0 ATU-II CMI7B (CYLR7B compare-match generation) Don't care* Don't care* Burst/cyclesteal 1 ATU-II CMI7C (CYLR7C compare-match generation) Don't care* Don't care* Burst/cyclesteal 0 ATU-II CMI7D (CYLR7D compare-match generation) Don't care* Don't care* Burst/cyclesteal Transfer Source Transfer Destination Bus Mode Don't care* TDR0 Cycle-steal RXI0 (SCI0 receive-data- RDR0 full transfer request) 0 SCI1 receive block 1 SCI2 transmit block TXI2 (SCI2 transmitdata-empty transfer request) Don't care* RXI1 (SCI1 receive-data- RDR1 full transfer request) 0 SCI2 receive block 1 SCI3 transmit block TXI3 (SCI3 transmitdata-empty transfer request) Don't care* RXI2 (SCI2 receive-data- RDR2 full transfer request) 0 SCI3 receive block 1 SCI4 transmit block TXI4 (SCI4 transmitdata-empty transfer request) 0 SCI4 receive block 1 A/D0 0 Don't care* Don't care* Cycle-steal TDR1 Cycle-steal Don't care* Cycle-steal TDR2 Cycle-steal Don't care* Cycle-steal TDR3 Cycle-steal Don't care* Cycle-steal TDR4 Cycle-steal RXI4 (SCI4 receive-data- RDR4 full transfer request) Don't care* Cycle-steal ADI0 (A/D0 ADDR0- conversion end interrupt) ADDR11 Don't care* Burst/cyclesteal A/D1 ADI1 (A/D1 ADDR12- conversion end interrupt) ADDR23 Don't care* Burst/cyclesteal 1 A/D2 ADI2 (A/D2 ADDR24- conversion end interrupt) ADDR31 Don't care* Burst/cyclesteal 0 SSU0 transmit block SSTSI0 (transmitdata-empty or transmit-end transfer request of SSU0) Don't care* SSTDR0_0 to SSTDR3_0 Cycle-steal 1 HCAN0 MB0-MB31 Don't care* Burst/cyclesteal 0 SSU0 receive block SSRXI0 (receive-datafull transfer request of SSU0) SSRDR0_0 to SSRDR3_0 Don't care* Cycle-steal 1 ATU-II ICI0A (ICR0A input capture generation) Don't care* Don't care* Burst/cyclesteal 0 ATU-II ICI0B (ICR0B input capture generation) Don't care* Don't care* Burst/cyclesteal 1 ATU-II ICI0C (ICR0C input capture generation) Don't care* Don't care* Burst/cyclesteal 0 ATU-II ICI0D (ICR0D input capture generation) Don't care* Don't care* Burst/cyclesteal 1 ATU-II CMI6A (CYLR6A compare-match generation) Don't care* Don't care* Burst/cyclesteal RXI3 (SCI3 receive-data- RDR3 full transfer request) RM0 (HCAN0 receive interrupt) Don't care* RS4 RS3 RS2 RS1 RS0 DMAC Transfer Request Source DMAC Transfer Request Signal Transfer Source Transfer Destination 1 0 1 1 0 ATU-II CMI6B (CYLR6B compare-match generation) Don't care* Don't care* Burst/cyclesteal 1 ATU-II CMI6C (CYLR6C compare-match generation) Don't care* Don't care* Burst/cyclesteal 0 ATU-II CMI6D (CYLR6D compare-match generation) Don't care* Don't care* Burst/cyclesteal 1 ATU-II CMI7A (CYLR7A compare-match generation) Don't care* Don't care* Burst/cyclesteal 0 ATU-II CMI7B (CYLR7B compare-match generation) Don't care* Don't care* Burst/cyclesteal 1 ATU-II CMI7C (CYLR7C compare-match generation) Don't care* Don't care* Burst/cyclesteal 0 ATU-II CMI7D (CYLR7D compare-match generation) Don't care* Don't care* Burst/cyclesteal 1 SSU1 transmit block SSTSI1 (transmitdata-empty or transmit-end transfer request of SSU1) Don't care* SSTDR0_1 to SSTDR3_1 Cycle-steal 0 SSU1 receive block SSRXI1 (receive-datafull transfer request of SSU1) SSRDR0_1 to SSRDR3_1 Don't care* Cycle-steal 1 0 0 1 Burst/cyclesteal 0 SCI0 transmit block TXI0 (SCI0 transmitdata-empty transfer request) 1 0 1 Bus Mode Rev. 5.00 Feb. 24, 2010 Page xvii of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 10.3.7 Relationship between Request Modes and Bus Modes by DMA Transfer Category 10.3.7 Relationship between Request Modes and Bus Modes by DMA Transfer Category 190 Note amended 1. Auto-request or on-chip peripheral module request enabled. However, in the case of an on-chip peripheral module request, it is not possible to specify the SCI, HCAN0, or A/D converter for the transfer request source. 1. Auto-request or on-chip peripheral module request enabled. However, in the case of an on-chip peripheral module request, it is not possible to specify the SCI, HCAN0, SSU*5, or A/D converter for the transfer request source. 2. Auto-request or on-chip peripheral module request possible. However, if the transfer request source is also the SCI, HCAN0, or A/D converter, the transfer source or transfer destination must be same as the transfer source. 2. Auto-request or on-chip peripheral module request possible. However, if the transfer request source is also the SCI, HCAN0, SSU*5, or A/D converter, the transfer source or transfer destination must be same as the transfer source. 3. When the transfer request source is the SCI, only cycle-steal mode is possible. 3. When the transfer request source is the SCI, or SSU*5, only cycle-steal mode is possible. 11.1.1 Features 11.1.1 Features Table 11.1 ATU-II Functions Table 11.1 ATU-II Functions 202, 203 Table amended Item Counter configuration Clock sources Item Item (-/32) x (1/2n) (-/32) x (1/2n) (n = 0-5) (n = 0-5) (n = 0-5) Counter configuration TCLKA, TCLKB, AGCK, TCLKA, TCLKB, AGCK, TCLKA, TCLKB, AGCK, AGCKM AGCKM AGCKM Channel 1 -/32 (-/32) x (1/2n) Channels 6, 7 Counter configuration Channels 3-5 Channel 0 Clock sources (-/32) x (1/2n) (n = 0-5) Channel 2 Channel 8 Channel 9 Channel 10 Channels 11 Item (-/32) x (1/2n) (-/32) (-/32) x (1/2n) Counter configuration (n = 0-5) (n = 0-5) Clock sources Channel 0 Channel 1 P-P/32 (P-P/32) x (1/2n) (P-P/32) x (1/2n) (P-P/32) x (1/2n) (n = 0-5) (n = 0-5) (n = 0-5) TCLKA, TCLKB, AGCK, TCLKA, TCLKB, AGCK, TCLKA, TCLKB, AGCK, AGCKM AGCKM AGCKM Channels 6, 7 Clock sources (P-P/32) x (1/2n) (n = 0-5) Channel 2 Channels 3-5 Channel 8 Channel 9 Channel 10 Channels 11 (P-P/32) x (1/2n) (P-P/32) (P-P/32) x (1/2n) (n = 0-5) (n = 0-5) TCLKA, TCLKB TCLKA, TCLKB 11.1.6 Prescaler Diagram 11.1.6 Prescaler Diagram Figure 11.12 Prescaler Diagram Figure 11.12 Prescaler Diagram 229 Figure amended Input clock /2 Input clock P 11.2.5 Timer Status Registers (TSR) 11.2.5 Timer Status Registers (TSR) 273 Description amended * * Bit 3--Input Capture/Compare-Match Flag 3D (IMF3D): Status flag that indicates GR5D input capture or compare-match. Bit 3--Input Capture/Compare-Match Flag 3D (IMF3D): Status flag that indicates GR3D input capture or compare-match. 11.3.9 PWM Timer Function 11.3.9 PWM Timer Function Figure 11.21 PWM Timer Operation Figure 11.21 PWM Timer Operation 375 Figure amended P P STR STR6A TCNT6A Clock TCNT6A Clock TCNT6A 0001 0002 0003 0004 0003 0002 0001 0000 0001 0002 0003 0004 0003 0002 0001 0000 0001 0002 0004 CYLR6A Data = 0000 Data = 0004 0002 0003 0004 0001 0002 0003 0004 0001 0002 0003 0004 0001 0002 0003 0004 0001 0002 0004 Data = 0001 Data = 0000 0002 0002 * PWM output does not change for one cycle after activation 0004 0000 0000 0001 0004 BFR6A 0001 Cleared by software 0002 Data = 0004 Data = 0001 Cleared by software * PWM output does not change for one cycle after activation 0004 0000 0002 DTR6A TO6A Cleared by software TSR6 CMF6A 0001 Write to BFR6A DTR6A TO6A TCNT6A CYLR6A Write to BFR6A BFR6A 0003 Cleared by software 0000 Cleared by software 0001 0004 0001 Cleared by software TSR6 CMF6A Cycle Cycle Cycle Duty = 0% Note: * Since the retained value is output, the PWM output is not guaranteed for one cycle after activation. Rev. 5.00 Feb. 24, 2010 Page xviii of xciv REJ09B0177-0500 Cycle Duty = 100% Cycle Cycle Cycle Cycle Duty = 0% Note: * Since the retained value is output, the PWM output is not guaranteed for one cycle after activation. Cycle Duty = 100% Cycle 0003 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 11.3.11 Event Count Function and Event Cycle Measurement 11.3.11 Event Count Function and Event Cycle Measurement Figure 11.25 Event Cycle Measurement Operation Figure 11.25 Event Cycle Measurement Operation Figure amended P P TCNT3 Clock TCNT3 Clock TCNT3 0000 0001 0002 0003 0004 0005 5678 5679 567A 567B 567C 567D 567E Compare-match trigger (from channel 9) GR3A TCNT3 0000 0001 0002 0003 0004 0005 5678 5679 567A 567B 567C 567D 567E Compare-match trigger (from channel 9) 0003 TSR3 IMF3A 567A Cleared by software 0004 GR3A 567A Cleared by software TSR3 IMF3A 11.6 Sample Setup Procedures 11.6 Sample Setup Procedures Figure 11.60 Sample Setup Procedure for PWM Timer Operation (Channels 6 and 7) Figure 11.60 Sample Setup Procedure for PWM Timer Operation (Channels 6 and 7) 408 Description amended 2. Set the port B control register L (PBCRL) corresponding to the waveform output port to ATU PWM output. Also set the corresponding bit to 1 in the port B IO register (PBIOR) to specify the output attribute. 2. Set the port B control register L (PBCRL) corresponding to the waveform output port to ATU PWM output. . 11.7 Usage Notes 11.7 Usage Notes 423 Title and description amended External Output Value in Software Standby Mode: In software standby mode, the ATU register and external output values are cleared to 0. However, while the channel 1, 2, and 11 TIO1A to TIO1H, TIO2A to TIO2H, TIO11A, and TIO11B external output values are cleared to 0 immediately after software standby mode is exited, other external output values and all registers are cleared to 0 immediately after a transition to software standby mode. External Output Values in Software Standby Mode and Pin State after Software Standby Mode Release: In software standby mode, the ATU register and external output values are initialized. The pin state is high impedance. Also, when pin output is inverted by the pin function controller's port B invert register (PBIR) or port K invert register (PKIR), the corresponding pins are set to 1. Figure 11.74 External Output Value Transition Points in Relation to Software Standby Mode 423 Since the settings of the pin function controller (PFC) are initialized, the PFC must be set again to use the function of the ATU-II external pins after software standby release. Figure 11.74 External Output Value Transition Points in Relation to Software Standby Mode Figure deleted 12.1.4 Register Configuration 12.1.4 Register Configuration Table 12.2 Advanced Pulse Controller Register Table 12.2 Advanced Pulse Controller Register 429 Note deleted Note: Register access with an internal clock multiplication ratio of 4 requires four or five internal clock () cycles. 12.2.1 Pulse Output Port Control Register (POPCR) 12.2.1 Pulse Output Port Control Register (POPCR) 430 Description amended POPCR is initialized to H'0000 by a power-on reset and in hardware standby mode. It is not initialized in software standby mode. POPCR is initialized to H'0000 by a power-on reset, in hardware standby mode and in software standby mode. Rev. 5.00 Feb. 24, 2010 Page xix of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 13.2.2 Timer Control/Status Register (TCSR) 13.2.2 Timer Control/Status Register (TCSR) 441 Table amended Bits 2 to 0--Clock Select 2 to 0 (CKS2 to CKS0) Bits 2 to 0--Clock Select 2 to 0 (CKS2 to CKS0) Description Description Overflow Interval* ( = 40 MHz) Overflow Interval* ( = 80 MHz) 6.4 s 12.8 s 204.8 s 409.6 s 409.6 s 0.8 ms 0.8 ms 1.6 ms 1.6 ms 3.3 ms 3.3 ms 6.6 ms 13.1 ms 26.2 ms 26.2 ms 52.4 ms Note amended Note: * The overflow interval listed is the time from when the TCNT begins counting at H'00 until an overflow occurs. Refer to section 13.4.7, Multiplication Factor for Internal Clock Signal () and Overflow Time. Note: * The overflow interval listed is the time from when the TCNT begins counting at H'00 until an overflow occurs. . 13.4.7 Multiplication Factor for Internal Clock Signal () and Overflow Time 13.4.7 Multiplication Factor for Internal Clock Signal () and Overflow Time 449 Deleted 14.1.3 Register Configuration 14.1.3 Register Configuration Table 14.1 Register Configuration Table 14.1 Register Configuration 453 Note amended Notes: Register access with an internal clock multiplication ratio of 4 requires four or five internal clock () cycles for byte access and word access, and eight or nine internal clock () cycles for longword access. Notes: * Only 0 can be written to the CMCSR0 and CMCSR1 CMF bits to clear the flags. * Only 0 can be written to the CMCSR0 and CMCSR1 CMF bits to clear the flags. 15.1.4 Register Configuration 15.1.4 Register Configuration Table 15.2 Register Table 15.2 Register 467 Note amended Notes: Register access with an internal clock multiplication ratio of 4 requires four or five internal clock () cycles for byte access and word access, and eight or nine internal clock () cycles for longword access. Notes: *1 Only 0 can be written to clear the flags. *2 Do not access empty addresses. 1. Only 0 can be written to clear the flags. 2. Do not access empty addresses. 15.2.5 Serial Mode Register (SMR) 15.2.5 Serial Mode Register (SMR) 469 Description amended The CPU can always read and write to SMR. SMR is initialized to H'00 by a power-on reset and in hardware standby mode. It is not initialized by a manual reset and in software standby mode. The CPU can always read to SMR. The CPU should only perform write operations when making initial settings. Do not use the CPU to perform writes during transmit, receive, or transmit/receive operation. SMR is initialized to H'00 by a power-on reset, in hardware standby mode. The value is not retrained in software standby mode and it is initialized after release. It is not initialized by a manual reset. Rev. 5.00 Feb. 24, 2010 Page xx of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 15.2.6 Serial Control Register (SCR) 15.2.6 Serial Control Register (SCR) 472 Description amended The CPU can always read and write to SCR. SCR is initialized to H'00 by a power-on reset and in hardware standby mode. It is not initialized by a manual reset and in software standby mode. The CPU can always read/write to SCR. SCR is initialized to H'00 by a power-on reset and in hardware standby mode. The value is not retrained in software standby mode and it is initialized after release. It is not initialized by a manual reset. 15.2.7 Serial Status Register (SSR) 15.2.7 Serial Status Register (SSR) 476-478 Description and table amended Note: * Only 0 can be written to clear the flag. Note: * This bit can be written to when its value is read as 1, and it cannot be written to when its value is read as 0. The CPU can always read and write to SSR, but cannot write 1 in the status flags (TDRE, RDRF, ORER, PER, and FER). These flags can be cleared to 0 only if they have first been read (after being set to 1). Bits 2 (TEND) and 1 (MPB) are read-only bits that cannot be written. SSR is initialized to H'84 by a power-on reset, and in hardware standby mode and software standby mode. It is not initialized by a manual reset. Bit 7--Transmit Data Register Empty (TDRE): Bit 7: TDRE Description 1 TDR does not contain valid transmit data The CPU can always read and write to SSR, but when the TDRE, RDRF, ORER, PER, or PEF bit is read as 1 it becomes writable, and when it is read as 0 it is not writable. As examples of ways to prevent a flag from being set inadvertently by a write operation, either prohibit writing 1 to the bit during the period from when it is read as 1 and the next time it is read as 0, or write 0 immediately after the bit is cleared to 0, so that it is always in a not writable state except when performing a flag clearing operation. Bits 2 (TEND) and 1 (MPB) are read-only bits that cannot be written. SSR is initialized to H'84 by a power-on reset, and in hardware standby mode and software standby mode. It is not initialized by a manual reset. Bit 7--Transmit Data Register Empty (TDRE): (Initial value) Bit 7: TDRE Description 1 TDR does not contain valid transmit data [Setting conditions] * Power-on reset, hardware standby mode, or software standby mode * Power-on reset, hardware standby mode, or software standby mode * When the TE bit in SCR is 0 * When the TE bit in SCR is 0 * When data is transferred from TDR to TSR, enabling new data to be written in TDR * When data is transferred from TDR to TSR, enabling new data to be written in TDR * When 1 is written after the first clearing condition is met Bit 6--Receive Data Register Full (RDRF): Bit 6--Receive Data Register Full (RDRF): Bit 6: RDRF Description Bit 6: RDRF Description 1 RDR contains valid received data 1 RDR contains valid received data [Setting condition] [Setting condition] RDRF is set to 1 when serial data is received normally and transferred from RSR to RDR * RDRF is set to 1 when serial data is received normally and transferred from RSR to RDR * When 1 is written after the second clearing condition is met Bit 5--Overrun Error (ORER): Bit 5--Overrun Error (ORER): Bit 5: ORER Description Bit 5: ORER Description 1 A receive overrun error occurred 1 A receive overrun error occurred RDR continues to hold the data received before the overrun error, so subsequent receive data is lost. Serial receiving cannot continue while ORER is set to 1. In synchronous mode, serial transmitting is disabled. RDR continues to hold the data received before the overrun error, so subsequent receive data is lost. Serial receiving cannot continue while ORER is set to 1. In synchronous mode, serial transmitting is disabled. [Setting condition] [Setting condition] ORER is set to 1 if reception of the next serial data ends when RDRF is set to 1 * ORER is set to 1 if reception of the next serial data ends when RDRF is set to 1 * When 1 is written after the second clearing condition is met Bit 4--Framing Error (FER): Bit 4--Framing Error (FER): Bit 4: FER 1 Bit 4: FER 1 Description A receive framing error occurred Description A receive framing error occurred When the stop bit length is two bits, only the first bit is checked to see if it is a 1. The second stop bit is not checked. When a framing error occurs, the SCI transfers the receive data into RDR but does not set RDRF. Serial receiving cannot continue while FER is set to 1. In synchronous mode, serial transmitting is also disabled. When the stop bit length is two bits, only the first bit is checked to see if it is a 1. The second stop bit is not checked. When a framing error occurs, the SCI transfers the receive data into RDR but does not set RDRF. Serial receiving cannot continue while FER is set to 1. In synchronous mode, serial transmitting is also disabled. [Setting condition] [Setting condition] FER is set to 1 if the stop bit at the end of receive data is checked and found to be 0 * FER is set to 1 if the stop bit at the end of receive data is checked and found to be 0 * When 1 is written after the second clearing condition is met Bit 3--Parity Error (PER): Bit 3: PER 1 (Initial value) [Setting conditions] Description A receive parity error occurred Bit 3--Parity Error (PER): Bit 3: PER 1 Description A receive parity error occurred When a parity error occurs, the SCI transfers the receive data into RDR but does not set RDRF. Serial receiving cannot continue while PER is set to 1. When a parity error occurs, the SCI transfers the receive data into RDR but does not set RDRF. Serial receiving cannot continue while PER is set to 1. [Setting condition] [Setting condition] PER is set to 1 if the number of 1s in receive data, including the parity bit, does not match the even or odd parity setting of the parity mode bit (O/E) in the serial mode register (SMR) * PER is set to 1 if the number of 1s in receive data, including the parity bit, does not match the even or odd parity setting of the parity mode bit (O/E) in the serial mode register (SMR) * When 1 is written after the second clearing condition is met Rev. 5.00 Feb. 24, 2010 Page xxi of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 15.2.8 Bit Rate Register (BRR) 15.2.8 Bit Rate Register (BRR) 480 Description amended The CPU can always read and write to BRR. BRR is initialized to H'FF by a power-on reset and in hardware standby mode. It is not initialized by a manual reset and in software standby mode. Each channel has independent baud rate generator control, so different values can be set for each channel. The CPU can always read to BRR. The CPU should only perform write operations when making initial settings. Do not use the CPU to perform writes during transmit, receive, or transmit/receive operation. BRR is initialized to H'FF by a power-on reset and in hardware standby mode. The value is not retained in software standby mode and it is initialized after release. It is not initialized by a manual reset . Each channel has independent baud rate generator control, so different values can be set for each channel. 15.2.9 Serial Direction Control Register (SDCR) 15.2.9 Serial Direction Control Register (SDCR) 487 Description amended The description in this section assumes LSB-first transfer. The description in this section assumes LSB-first transfer. SDCR is initialized to H'F2 by a power-on reset and in the hardware standby mode. It is not initialized by a manual reset and in software standby mode. The CPU can always read from SDCR. The CPU should only write to SDCR when making initial settings. Do not use the CPU to write to SDCR during transmit, receive, or transmit/receive operation. SDCR is initialized to H'F2 by a power-on reset and in the hardware standby mode. The value is not retained in software standby mode and it is initialized after release. It is not initialized by a manual reset . 15.3.2 Operation in Asynchronous Mode 15.3.2 Operation in Asynchronous Mode SCI Initialization (Asynchronous Mode): SCI Initialization (Asynchronous Mode): Figure 15.5 Sample Flowchart for Transmitting Serial Data Figure 15.5 Sample Flowchart for Transmitting Serial Data 494 Figure amended and note added Clear TE bit in SCR to 0; select theTxD pin as an output port with the PFC Clear TE bit in SCR to 0; select theTxD pin as an output port with the PFC 5 Note: Do not write to SMR, SCR, BRR, or SDCR between the start and the end of a transmit operation. However, this does not apply to operation 5. Rev. 5.00 Feb. 24, 2010 Page xxii of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 15.3.2 Operation in Asynchronous Mode 15.3.2 Operation in Asynchronous Mode Figure 15.6 SCI Transmit Operation in Asynchronous Mode Figure 15.6 SCI Transmit Operation in Asynchronous Mode (Example: 8-Bit Data with Parity and One Stop Bit) (Example: 8-Bit Data with Parity and One Stop Bit) 496 Figure amended Start bit 1 Serial data 0 Parity Stop bit bit Data D0 D1 D7 0/1 1 Serial data TDRE TDRE TEND TEND TXI TXI interrupt interrupt handler writes request data in TDR and clears TDRE to 0 TXI interrupt request Start bit 1 0 Parity Stop bit bit Data D0 D1 D7 TXI TXI interrupt interrupt handler writes request data in TDR and clears TDRE to 0 1 frame 0/1 1 TXI interrupt request 1 frame Receiving Serial Data (Asynchronous Mode): Receiving Serial Data (Asynchronous Mode): Figure 15.7 Sample Flowchart for Receiving Serial Data (1) Figure 15.7 Sample Flowchart for Receiving Serial Data (1) 497 Figure amended and note added Clear RE bit in SCR to 0 Clear RE bit in SCR to 0 5 Note: Do not write to SMR, SCR, BRR, or SDCR between the start and the end of a receive operation. However, this does not apply to operation 5. Figure 15.8 Sample Flowchart for Receiving Serial Data (2) Figure 15.8 Sample Flowchart for Receiving Serial Data (2) 498 Figure amended and note added Break? Yes No No Framing error handling Yes Break? Clear RE bit in SCR to 0 Framing error handling Clear RE bit in SCR to 0 5 Note: Do not write to SMR, SCR, BRR, or SDCR between the start and the end of a receive operation. However, this does not apply to operation 5. Rev. 5.00 Feb. 24, 2010 Page xxiii of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 15.3.2 Operation in Asynchronous Mode 15.3.2 Operation in Asynchronous Mode Figure 15.9 SCI Receive Operation Figure 15.9 SCI Receive Operation Example: 8-Bit Data with Parity and One Stop Bit) (Example: 8-Bit Data with Parity and One Stop Bit) 500 Figure amended 1 Serial data Start bit 0 Parity Stop Start bit bit bit Data D0 D1 D7 0/1 1 Data D0 0 Parity Stop bit bit D1 D7 0/1 1 1 1 Idling (marking) Serial data Start bit 0 Parity Stop Start bit bit bit Data D0 D1 D7 0/1 1 D0 0 Parity Stop bit bit Data D1 D7 0/1 1 1 Idling (marking) RDRF TDRF RXI interrupt request FER 1 frame RXI interrupt request FER RXI interrupt handler reads data in RDR and clears RDRF to 0. 1 frame Framing error generates ERI interrupt request. RXI interrupt handler reads data in RDR and clears RDRF to 0. Framing error generates ERI interrupt request. 15.3.3 Multiprocessor Communication 15.3.3 Multiprocessor Communication Transmitting Multiprocessor Serial Data: Transmitting Multiprocessor Serial Data: Figure 15.11 Sample Flowchart for Transmitting Multiprocessor Serial Data Figure 15.11 Sample Flowchart for Transmitting Multiprocessor Serial Data 502 Figure amended and note added Clear TE bit in SCR to 0; select theTxD pin function as an output port with the PFC Clear TE bit in SCR to 0; select theTxD pin function as an output port with the PFC 5 Note: Do not write to SMR, SCR, BRR, or SDCR between the start and the end of a transmit operation. However, this does not apply to operation 5. Figure 15.12 SCI Multiprocessor Transmit Operation Figure 15.12 SCI Multiprocessor Transmit Operation (Example: 8-Bit Data with Multiprocessor Bit and One Stop Bit) (Example: 8-Bit Data with Multiprocessor Bit and One Stop Bit) 503 Figure amended 1 Multiprocessor bit Stop Data bit Start bit Serial data 0 D0 D1 D7 0/1 1 1 TDRE TEND TEND TXI interrupt request TXI interrupt handler writes data in TDR and clears TDRE to 0 1 frame Rev. 5.00 Feb. 24, 2010 Page xxiv of xciv REJ09B0177-0500 TXI interrupt request Start bit Serial data TDRE Multiprocessor bit Stop Data bit TXI interrupt request 0 D0 D1 D7 TXI interrupt handler writes data in TDR and clears TDRE to 0 1 frame 0/1 1 TXI interrupt request Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 15.3.3 Multiprocessor Communication 15.3.3 Multiprocessor Communication Receiving Multiprocessor Serial Data: Receiving Multiprocessor Serial Data: Figure 15.13 Sample Flowchart for Receiving Multiprocessor Serial Data (1) Figure 15.13 Sample Flowchart for Receiving Multiprocessor Serial Data (1) 504 Figure amended and note added Clear RE bit in SCR to 0 6 Clear RE bit in SCR to 0 Note: Do not write to SMR, SCR, BRR, or SDCR between the start and the end of a receive operation. However, this does not apply to operation 6. Figure 15.14 Sample Flowchart for Receiving Multiprocessor Serial Data (2) Figure 15.14 Sample Flowchart for Receiving Multiprocessor Serial Data (2) 505 Figure amended and note added No No Framing error handling Framing error handling Clear RE bit in SCR to 0 Clear RE bit in SCR to 0 6 Note: Do not write to SMR, SCR, BRR, or SDCR between the start and the end of a receive operation. However, this does not apply to operation 6. Figure 15.15 SCI Receive Operation Figure 15.15 SCI Receive Operation (Example: 8-Bit Data with Multiprocessor Bit and One Stop Bit) (Example: 8-Bit Data with Multiprocessor Bit and One Stop Bit) 506 Figure amended 1 Serial data Start bit 0 Data (ID1) D0 D1 Stop Start Data MPB bit bit (data 1) D7 1 1 0 D0 D1 Stop MPB bit D7 0 1 1 Idling (marking) 1 Serial data MPB MPB MPIE MPIE RDRF RDRF RDR value RXI interrupt handler reads data in RDR and clears RDRF to 0 Not station's ID, so MPIE is set to 1 again Data (ID1) 0 D0 D1 Serial data Start bit 0 Data (ID2) D0 D1 1 1 0 D0 No RXI interrupt, RDR maintains state RXI interrupt request (multiprocessor interrupt), MPIE = 0 D1 Stop MPB bit D7 0 1 1 Idling (marking) 1 Serial data MPB MPB MPIE MPIE RDRF RDRF RDR value ID1 RXI interrupt request (multiprocessor interrupt), MPIE = 0 ID2 RXI interrupt handler reads data in RDR and clears RDRF to 0 (B) ID Matches 1 1 0 D0 D1 D7 0 1 1 Idling (marking) RXI interrupt handler reads data in RDR and clears RDRF to 0 Not station's ID, so MPIE is set to 1 again No RXI interrupt, RDR maintains state (A) ID Does Not Match Stop Start Data MPB bit bit (data 2) D7 D7 Stop MPB bit ID1 (A) ID Does Not Match 1 Stop Start Data MPB bit bit (data 1) RDR value ID1 RXI interrupt request (multiprocessor interrupt), MPIE = 0 Start bit Data 2 Station's ID, so receiving MPIE continues, with data bit is again received by the RXI set to 1 interrupt processing routine RDR value Start bit 0 Data (ID2) D0 D1 Stop Start Data MPB bit bit (data 2) D7 1 1 0 ID1 RXI interrupt request (multiprocessor interrupt), MPIE = 0 D0 ID2 RXI interrupt handler reads data in RDR and clears RDRF to 0 D1 Stop MPB bit D7 0 1 1 Idling (marking) Data 2 Station's ID, so receiving MPIE continues, with data bit is again received by the RXI set to 1 interrupt processing routine (B) ID Matches Rev. 5.00 Feb. 24, 2010 Page xxv of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 15.3.4 Synchronous Operation 15.3.4 Synchronous Operation Transmitting Serial Data (Synchronous Mode): Transmitting Serial Data (Synchronous Mode): Figure 15.18 Sample Flowchart for Serial Transmitting Figure 15.18 Sample Flowchart for Serial Transmitting 509 Figure amended and note added Clear TE bit to 0 in SCR Clear TE bit to 0 in SCR 4 Note: Do not write to SMR, SCR, BRR, or SDCR between the start and the end of a transmit operation. However, this does not apply to operation 4. Figure 15.19 Example of SCI Transmit Operation Figure 15.19 Example of SCI Transmit Operation 510 Figure amended Transfer direction Transfer direction Serial clock Serial clock LSB Serial data Bit 0 MSB Bit 1 Bit 7 LSB Bit 0 Bit 1 Bit 6 Bit 7 TDRE Bit 0 MSB Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt request Serial data TEND TXI interrupt TXI interrupt handler writes request data in TDR and clears TDRE to 0 TEI interrupt request 1 frame TXI interrupt request TEI interrupt request TXI interrupt TXI interrupt handler writes request data in TDR and clears TDRE to 0 1 frame Receiving Serial Data (Synchronous Mode): Receiving Serial Data (Synchronous Mode): Figure 15.20 Sample Flowchart for Serial Receiving (1) Figure 15.20 Sample Flowchart for Serial Receiving (1) 511 Figure amended and note added Clear RE bit in SCR to 0 Clear RE bit in SCR to 0 5 Note: Do not write to SMR, SCR, BRR, or SDCR between the start and the end of a receive operation. However, this does not apply to operation 5. Rev. 5.00 Feb. 24, 2010 Page xxvi of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 15.3.4 Synchronous Operation 15.3.4 Synchronous Operation Figure 15.22 Example of SCI Receive Operation Figure 15.22 Example of SCI Receive Operation 512 Figure amended Transfer direction Transfer direction Serial clock Serial data Serial clock Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 Serial data RDRF RDRF ORER ORER RXI interrupt request Read data with RXI interrupt processing routine and clear RDRF bit to 0 RXI interrupt request ERI interrupt request generated by overrun error Bit 7 RXI interrupt request 1 frame Bit 0 Bit 7 Read data with RXI interrupt processing routine and clear RDRF bit to 0 Bit 0 Bit 1 RXI interrupt request Bit 6 Bit 7 ERI interrupt request generated by overrun error 1 frame Transmitting and Receiving Serial Data Simultaneously (Synchronous Mode): Transmitting and Receiving Serial Data Simultaneously (Synchronous Mode): Figure 15.23 Sample Flowchart for Serial Transmission and Reception Figure 15.23 Sample Flowchart for Serial Transmission and Reception 514 Figure amended and notes added Clear TE and RE bits in SCR to 0 Clear TE and RE bits in SCR to 0 6 Note: Do not write to SMR, SCR, BRR, or SDCR between the start and the end of a transmit/receive operation. However, this does not apply to operation 6. 15.5.10 Note on Writing to Registers During Transmit, Receive, and Transmit/Receive Operations Newly added Section 16 Synchronous Serial Communication Unit (SSU) Newly added 16.4.2 Master Control Register_n (MCR_n) (n = 0, 1) 17.4.2 Master Control Register_n (MCR_n) (n = 0, 1) 545 Description amended Bit 5: MCR5 Bit 5: MCR5 Important: Usage of sleep mode is limited. Be sure to carefully read section 16.8, Usage Notes. Note: Do not access to MB during sleep mode. 16.4.3 General Status Register_n (GSR_n) (n = 0, 1) 17.4.3 General Status Register_n (GSR_n) (n = 0, 1) 550 Description amended Transmit/Receive Warning Flag Transmit/Receive Warning Flag Certain restrictions apply when using sleep mode, Be sure to read section 17.8, Usage Notes. Indicates an error warning. Indicates an error warning. 0: Reset condition: When TEC < 96, REC < 96, or TEC 256 0: Reset condition: When TEC < 96, or REC < 96, or TEC 256 1: When 96 TEC < 256 or 96 REC 1: When 96 TEC < 256 or 96 REC Rev. 5.00 Feb. 24, 2010 Page xxvii of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 16.4.4 HCAN-II_Bit timing Configuration Register n (HCAN-II_BCR0_n, HCAN-II_BCR1_n) (n = 0, 1) 17.4.4 HCAN II_ Bit Configuration Register n(HCAN II_BCR0_n,HCAN II_BCR1_n) (n = 0, 1) About Bit Configuration Register: About Bit Configuration Register: 553 Description amended 1-bit time (8-25 quanta) 1-bit time (9-25 quanta) Table 16.5 TSEG1 and TSEG2 Settings Table 17.5 TSEG1 and TSEG2 Settings 554 Table and note amended Note: *When BRP[7:0] = 0, TSEG2[2:0] 2 Note: *When BPR [7:0] = H'00000000, TSEG [2:0] H'001 When BRP[7:0] 1, TSEG2[2:0] 1 16.5.8 Unread Message Status Register n (UMSR1n, UMSR0n) (n = 0, 1) 17.5.8 Unread Message Status Register n (UMSR1n, UMSR0n) (n = 0, 1) * UMSR0n (n = 0, 1) * UMSR0n (n = 0, 1) 580 Table amended Indicate that an unread message has been Indicate that an unread message has been overwritten for mailboxes 15 to 0. overwritten or overrun for mailboxes 15 to 0. 16.6.2 Timer Control Register_n (TCR_n) (n = 0, 1) 17.6.2 Timer Control Register_n (TCR_n) (n = 0, 1) 583 Bit table amended Bit: 15 14 13 12 11 10 9 8 TCR TCR TCR TCR TCR TCR TCR9 15 14 13 12 11 10 Initial Value: 0 0 0 0 0 0 0 7 6 TCR7 0 0 5 4 3 2 1 0 Bit: 15 TPSC TPSC TPSC TPSC TPSC TPSC 0 5 4 3 2 1 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 TCR 15 Initial Value: 0 R/W: R/W 14 13 12 11 10 9 TCR 14 TCR 13 TCR 12 TCR 11 TCR 10 TCR9 8 7 6 TCR7 5 4 TCR5 TCR4 3 2 1 0 TCR3 TCR2 TCR1 TCR0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Table amended 586 Bit Bit Name Initial Value R/W 5 TCR5 0 R/W HCAN-II Timer Prescaler HCAN-II Timer Prescaler 4 TCR4 0 R/W Divide the source clock (2 HCAN peripheral clock) before it is used for the timer. The following relationship exists between source clocks and the timer 3 TCR3 0 R/W Divide the source clock (2 x P) before it is used for the timer. The following relationship exists between source clocks and the timer 2 TCR2 0 R/W 1 TCR1 0 R/W 0 TCR0 0 R/W Bit Bit Name Initial Value R/W Description 5 TCR5 0 R/W 4 TCR4 0 R/W 3 TCR3 0 -- 2 TCR2 0 -- 1 TCR1 0 -- 0 TCR0 0 -- 000000: 1 source clock 000001: 2 source clock 000010: 4 source clock 000011: 6 source clock 000100: 8 source clock : 111111: 126 source clock Description 000000: 1 x source clock 000001: 2 x source clock 000010: 4 x source clock 000011: 6 x source clock 000100: 8 x source clock : 111111: 126 x source clock 16.7.2 HCAN Settings 17.7.2 HCAN Settings Figure 16.7 Reset Sequence Figure 17.7 Reset Sequence 598 Figure amended Clear all mailboxes*2 Clear all mailboxes*2 (MSG-control, data, timestamp, LAFM) (MSG-control, data, timestamp, LAFM, Txtrigger) 16.7.4 Message Transmission Cancellation Sequence 17.7.4 Message Transmission Cancellation Sequence Figure 16.10 Transmission Cancellation Sequence Figure 17.10 Transmission Cancellation Sequence 602 Figure amended Set ABACK[N] *2 Set TXACK[N] Rev. 5.00 Feb. 24, 2010 Page xxviii of xciv REJ09B0177-0500 Set ABACK[N] Set TXACK[N]*2 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 16.7.9 DMAC Interface 17.7.9 DMAC Interface Figure 16.13 DMAC Transfer Flowchart Figure 17.13 DMAC Transfer Flowchart 608 Figure amended Initial setting of DMAC Set activation source Set source and destination addresses Set number of transmissions and interrupts : Processing by hardware : Setting by user : Processing by hardware Initial setting of DMAC Set activation source Set source and destination addresses Set number of transmissions and interrupts Receive a message at mailbox 0 in channel 0 Receive a message at mailbox 0 in channel 0 Activate DMAC Activate DMAC DMAC transfer ended? DMAC transfer ended? Set DMAC transfer end bit Clear RXPR and RFPR Set DMAC transfer end bit Clear RXPR and RFPR Enable DMAC interrupt Enable DMAC interrupt Interrupt to CPU Interrupt to CPU Clear DMAC interrupt flag Clear DMAC interrupt flag End End : Setting by user No Yes No Yes 16.7.11 CAN Bus Interface 17.7.11 CAN Bus Interface Figure 16.16 High-Speed Interface Using HA13721 Figure 17.16 Using the PCA82C250 in a High-Speed Interface 610 Replaced due to the transceiver IC changed. 17.1.1 Features 18.1.1 Features 617 Description amended * High-speed conversion * High-speed conversion Conversion time: minimum 13.3 s per channel (when peripheral clock (Pf) = 20 MHz) Conversion time: minimum 13.3 s per channel (when fop = 20 MHz) 17.1.4 Register Configuration 18.1.4 Register Configuration Table 17.2 A/D Converter Registers Table 18.2 A/D Converter Registers 624 Notes amended Notes: Register access with an internal clock multiplication ratio of 4 requires four or five internal clock () cycles. Notes: 1. A 16-bit access must be made on a word boundary. 1. A 16-bit access must be made on a word boundary. 2. Only 0 can be written to bit 7 to clear the flag. 2. Only 0 can be written to bit 7 to clear the flag. 17.4.3 Analog Input Sampling and A/D Conversion Time 18.4.3 Analog Input Sampling and A/D Conversion Time Table 17.4 A/D Conversion Time (Single Mode) Table 18.4 A/D Conversion Time (Single Mode) 644 Table amended CKS0 : Peripheral Clock (P) = 10 to 20MHz CKS0 : fop = 10 to 20MHz CKS1 : Peripheral Clock (P) = 10MHz CKS1 : fop = 10MHz States (peripheral clock (P)) States (CK base) Rev. 5.00 Feb. 24, 2010 Page xxix of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 17.6 Usage Notes 18.6 Usage Notes 648 Description amended 2. Relation between, AVSS, AVCC and VSS, VCC 2. Relation between, AVSS, AVCC and VSS, VCC When using the A/D converter, set AVCC = 5.0 V 0.5 V, and AVSS = VSS. When the A/D converter is not used, set AVSS = VSS, and do not leave the AVCC pin open. When using the A/D converter, set AVCC = 5.0 V 0.5 V, and AVSS = VSS. When the A/D converter is not used, set AVSS = VSS, and the setting range is AVSS AVCC 5.5 V. 3. AVref input range 3. AVref input range Set AVref = 4.5 V to AVCC when the A/D converter is used, and AVref AVCC when not used. Set AVref = 4.5 V to AVCC when the A/D converter is used, and AVCC - 1.0 V AVref AVCC and AVSS AVref when not used. If conditions above are not met, the reliability of the device may be adversely affected. If conditions above are not met, the reliability of the device may be adversely affected. 18.2.1 A/D Trigger Control Registers 0 and 1 (ADTCR0 and ADTCR1) 19.2.1 A/D Trigger Control Registers 0 and 1 (ADTCR0 and ADTCR1) 655 Description and table amended * Bits 7 and 6--Clock Select 1 and 0 (CKSEL1x and CKSEL0x): Halt the counter or select internal clock " from among /2, /5, and /10, which are obtained by dividing clock . * Bits 7 and 6--Clock Select 1 and 0 (CKSEL1x and CKSEL0x): Halt the counter or select internal clock " from among P/2, P/5, and P/10, which are obtained by dividing clock P. Bit 7: CKSEL1x 0 1 Bit 6: CKSEL0x Description Bit 7: CKSEL1x 0 Counter is halted 0 1 Counter is incremented with internal clock = /2 0 Counter is incremented with internal clock = /5 1 Counter is incremented with internal clock = /10 1 Bit 6: CKSEL0x Description 0 Counter is halted 1 Counter is incremented with internal clock " = P/2 0 Counter is incremented with internal clock " = P/5 1 Counter is incremented with internal clock " = P/10 18.3 Interrupt Interface Deleted 18.4 PFC and I/O Port Interfaces Deleted 18.5.1 Overview 19.3.1 Overview (2) Prescalers (2) Prescalers 683 Description amended The channels incorporate dedicated prescalers, which can halt the clock signal that is input from the first stage or divide the frequency of the clock signal by 2, 5, or 10 according to the setting of the A/D trigger control register in the corresponding channels. Each channel has a dedicated prescaler that can halt the clock signal or divide its frequency by 2, 5, or 10, according to the setting of the A/D trigger control registers (ADTCR0 and ADTCR1) for the corresponding channel. 18.6 Appendices Deleted 19.1.4 Register Configuration 20.1.4 Register Configuration Table 19.2 Register Configuration Table 20.2 Register Configuration 697 Table and note amended Register Abbreviation Initial Value* Status register SDSR H'0B01 ID code register SDIDR H'001D200F 2 Register Abbreviation Status register SDSR Initial Value* 2 H'5001 (SH7058SF) H'0F01 (SH7059F) ID code register SDIDR H'08016447 (SH7058SF) H'0800B447 (SH7059F) Notes: Notes: 2. Initial value when the TRST signal is input. Registers are not initialized by a reset (power-on or manual) or in standby mode. 2. Initial value when the TRST signal is input. Registers are not initialized by a reset (power-on or manual) . 19.3.1 Instruction Register (SDIR) 20.3.1 Instruction Register (SDIR) 699 Description amended SDIR can be initialized by the TRST signal, but is not initialized by a reset or in software standby mode. SDIR can be initialized by the TRST signal or in software standby mode, but is not initialized by a reset . Rev. 5.00 Feb. 24, 2010 Page xxx of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 20.3.2 Status Register (SDSR) 19.3.2 Status Register (SDSR) Description amended 701 Bit: 15 14 13 12 11 10 9 8 -- -- -- -- -- -- -- -- Initial value: 0 0 0 0 1 0 1 1 R/W: R R R R R R R R (SH7058SF) Bit: 15 14 13 12 11 10 9 8 -- -- -- -- -- -- -- -- Initial value: 0 1 0 1 0 0 0 0 R/W: R R R R R R R R 15 14 13 12 11 10 9 8 -- -- -- -- -- -- -- -- (SH7059F) Bit: SDSR is initialized by TRST signal input, but is not initialized by a reset or in software standby mode. Initial value: 0 0 0 0 1 1 1 1 R/W: R R R R R R R R SDSR is initialized by TRST signal input or in software standby mode, but is not initialized by a reset . (SH7058SF) Bits 15 to 1--Reserved: Bits 15 to 12 and 7 to 1 are always read as 0, and the write value should always be 0. Bit 11, 9, and 8 are always read as 1, and the write value should always be 1. Bits 15, 13, and 11 to 1 are always read as 0, and the write value should always be 0. Bits 14 and 12 are always read as 1, and the write value should always be 1. (SH7059F) Bits 15 to 1--Reserved: Bits 15 to 12 and 7 to 1 are always read as 0, and the write value should always be 0. Bits 11 to 8 are always read as 1, and the write value should always be 1 Bit 0--Serial Data Transfer Control Flag (SDTRF): Indicates whether H-UDI registers can be accessed by the CPU. The SDTRF bit is reset by the TRST signal, but is not initialized by a reset or in software standby mode. Bit 0--Serial Data Transfer Control Flag (SDTRF): Indicates whether H-UDI registers can be accessed by the CPU. The SDTRF bit is reaset by the TRST signal, but is not initialized by a reset . 19.3.3 Data Register (SDDR) 20.3.3 Data Register (SDDR) 702 Description amended This register is not initialized by a reset, in hardware or software standby mode, or by the TRST signal. This register is not initialized by a reset, signal. or by the TRST Rev. 5.00 Feb. 24, 2010 Page xxxi of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 19.3.5 Boundary scan register (SDBSR) 20.3.5 Boundary scan register (SDBSR) Table 19.5 Correspondence between Pins and Boundary Scan Register Bits Table 20.5 Correspondence between Pins and Boundary Scan Register Bits 708, 710, 711, 713, 718 Table amended Pin No. Pin Name Pin No. Pin Name 45 PF14/BACK 45 PF14/BACK/SCS0 46 PF15/BREQ 46 PF15/BREQ/SCS1 135 PA8/TIIO4A 135 PA8/TIIO4A 136 PA9/TIO4B 137 PA10/TIO4C 138 PA11/TIO4D 143 PA14/TxD0 144 PA15/RxD0 160 PB13/SCK0 164 PB15/PULS5/ /ADTO0A 136 /ADTO0B 137 PA10/TIO4C /ADTO1A 138 PA11/TIO4D /ADTO1B SCK2 167 PA9/TIO4B 143 PA14/TxD0 144 PA15/RxD0 /SSO0 PC2/TxD2 168 PC3/RxD2 223 PL7/SCK2 230 PL12/IRQ4 231 PL13/IRQOUT /SSI0 160 PB13/SCK0 /SSCK0 164 PB15/PULS5/ SCK2/SSCK1 167 PC2/TxD2/SSO1 168 PC3/RxD2/SSI1 223 PL7/SCK2/SSCK1 230 PL12/IRQ4/SCS0 231 PL13/IRQOUT/SCS1 19.3.6 ID code register (SDIDR) 20.3.6 ID code register (SDIDR) 719 Description and table amended The ID code register (SDIDR) is a 32-bit register. In the IDCODE mode, SDIDR can output H'001D200F, which is a fixed code, from TDO. However, no serial data can be written to SDIDR via TDI. For SDIDR, read/write by the CPU cannot be performed. The ID code register (SDIDR) is a 32-bit register. In the IDCODE mode, SDIDR outputs a fixed code via TDO. The codes are H'0802558 for the SH7058SF and H'0800B447 for the SH7059F. Serial data can not be written to SDIDR via TDI. For SDIDR, read/write by the CPU cannot be performed. Table (SH7058SF) 27 0001 12 11 0001 1101 0010 0000 1 0000 111 27 1000 12 0000 0001 0110 0000 1011 11 0100 1 0100 011 0100 011 (SH7059F) 27 1000 Rev. 5.00 Feb. 24, 2010 Page xxxii of xciv REJ09B0177-0500 12 0000 11 0100 1 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 19.4.3 H-UDI Reset 20.4.3 H-UDI Reset 724 Desciption added * In software standby mode 19.5.2 Notes on Use 20.5.2 Notes on Use 725 5 to 10 added 20.2.1 Pin Descriptions 21.2.1 Pin Descriptions Pin Functions in RAM Monitor Mode Pin Functions in RAM Monitor Mode 733 Description amended Description of AUDCK pin Description of AUDCK pin The external clock input pin. Input the clock to be used for debugging to this pin. The input frequency must not exceed 10 MHz. When no connection is made, this pin is pulled up internally. The external clock input pin. Input the clock to be used for debugging to this pin. The input frequency must not exceed 1/8 of the internal operating frequency(). When no connection is made, this pin is pulled up internally. 20.3.2 Operation 21.3.2 Operation Figure 20.2 Example of Data Output (32-Bit Output) Figure 21.2 Example of Data Output (32-Bit Output)* 734 Title amended and note added Note: * For details on the AUD reset timing and the timing in branch trace mode, refer to section 29.3.13, AUD timing. 20.4.3 Operation 21.4.3 Operation Figure 20.5 Example of Read Operation (Byte Read) Figure 21.5 Example of Read Operation (Byte Read)* Figure 20.6 Example of Write Operation (Longword Write) Figure 21.6 Example of Write Operation (Longword Write)* Figure 20.7 Example of Error Occurrence (Longword Read) Figure 21.7 Example of Error Occurrence (Longword Read)* 736,737 Title amended and note added Note: * For details on the AUD reset timing and the timing in branch trace mode, refer to section 29.3.13, AUD timing. 20.5.1 Initialization 21.5.1 Initialization 737 Description added and amended 3. When AUDRST is driven low 3. In software standby mode 4. When the AUDSRST bit is set to 1 in the SYSCR1 register (see section 25.2.2) 4. When AUDRST is driven low 5. When the MSTOP3 bit is set to 1 in the SYSCR2 register (see section 25.2.3) 5. When the AUDSRST bit is set to 1 in the SYSCR1 register (see section 27.2.2) 6. When the MSTOP3 bit is set to 1 in the SYSCR2 register (see section 27.2.3) 20.5.2 Operation in Software Standby Mode 21.5.2 Operation in Software Standby Mode 737 Deleted Rev. 5.00 Feb. 24, 2010 Page xxxiii of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 21.1 Overview 22.1 Overview Table 21.1 SH7058 Multiplex Pins Table 22.1 SH7059 Multiplex Pins 739 - 741, 743 Function 1 (Related Module) Table amended Function 2 (Related Module) PA14 input/output (port) TxD0 output (SCI) PA15 input/output (port) RxD0 input (SCI) PB13 input/output (port) SCK0 input/output (SCI) PB15 input/output (port) PULS5 output (APC) PC2 input/output (port) TxD2 output (SCI) PC3 input/output (port) RxD2 input (SCI) PF14 input/output (port) BACK output (BSC) PF15 input/output (port) BREQ input (BSC) PL7 input/output (port) SCK2 input/output (SCI) PL12 input/output (port) IRQ4 input (INTC) PL13 input/output (port) IRQOUT output (INTC) Function 3 (Related Module) Function 4 (Related Module) SCK2 input/output (SCI) Function 1 (Related Module) Function 2 (Related Module) Function 3 (Related Module) PA14 input/output (port) TxD0 output (SCI) SSO0 output (SSU) PA15 input/output (port) RxD0 input (SCI) SSI0 input (SSU) PB13 input/output (port) SCK0 input/output (SCI) SSCK0 output (SSU) PB15 input/output (port) PULS5 output (APC) SCK2 input/output (SCI) PC2 input/output (port) TxD2 output (SCI) SSO1 output (SSU) PC3 input/output (port) RxD2 input (SCI) SSI1 input (SSU) PF14 input/output (port) BACK output (BSC) SCS0 input/output (SSU) PF15 input/output (port) BREQ input (BSC) SCS1 input/output (SSU) PL7 input/output (port) SCK2 input/output (SCI) SSCK1 output (SSU) PL12 input/output (port) IRQ4 input (INTC) SCS0 input/output (SSU) PL13 input/output (port) IRQOUT output (INTC) IRQOUT output (INTC) Function 4 (Related Module) SSCK1 output (SSU) SCS1 input/output (SSU) IRQOUT output (INTC) 21.3.1 Port A IO Register (PAIOR) 22.3.1 Port A IO Register (PAIOR) 745 Description amended Bits PA15IOR to PA0IOR correspond to pins PA15/RxD0 to PA0/TI0A. PAIOR is enabled when port A pins function as general input/output pins (PA15 to PA0) or ATU-II input/output pins, and disabled otherwise. Bits PA15IOR to PA0IOR correspond to pins PA15/RxD0/SSI0 to PA0/TI0A. PAIOR is enabled when port A pins function as general input/output pins (PA15 to PA0), ATU-II input/output pins or transmit/receive input/output for the SSU (SSI0 and SSO0), and disabled otherwise. ...When port A pins function as PA15 to PA0 or ATU-II input/output pins, a pin becomes an output when the corresponding bit in PAIOR is set to 1, and an input when the bit is cleared to 0. ...When port A pins function as PA15 to PA0, ATU-II input/output pins or transmit/receive input/output for the SSU (SSI0 and SSO0), a pin becomes an output when the corresponding bit in PAIOR is set to 1, and an input when the bit is cleared to 0. PAIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. PAIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. 21.3.2 Port A Control Registers H and L (PACRH, PACRL) 22.3.2 Port A Control Registers H and L (PACRH, PACRL) 746 Description amended PACRH and PACRL are initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. They are not initialized in software standby mode or sleep mode. PACRH and PACRL are initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. They are not initialized in sleep mode. Rev. 5.00 Feb. 24, 2010 Page xxxiv of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 21.3.2 Port A Control Registers H and L (PACRH, PACRL) 22.3.2 Port A Control Registers H and L (PACRH, PACRL) Port A Control Register H (PACRH) Port A Control Register H (PACRH) 746 Description amended Bit: 15 14 13 12 8 -- PA15MD -- PA14MD PA12MD Initial value: 0 0 0 0 0 R/W: R R/W R R/W R/W * Bit 15--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 14--PA15 Mode Bit (PA15MD): Selects the function of pin PA15/RxD0. Bit 14: PA15MD Description 0 General input/output (PA15) 1 Receive data input (RxD0) * Bit 12--PA14 Mode Bit (PA14MD): Selects the function of pin PA14/TxD0. Description 0 General input/output (PA14) 1 Transmit data output (TxD0) Initial value: R/W: * (Initial value) 14 13 12 0 0 0 0 0 R/W R/W R/W R/W R/W Bit 15: PA15MD1 Bit 14: PA15MD0 Description 0 0 General input/output (PA15) 1 Receive data input (RxD0) 0 Receive data input (SSI0) 1 Received (Do not set) * (Initial value) Bits 13 and 12--PA14 Mode Bit 1,0 (PA14MD1, PA14MD0): Selects the function of pin PA14/TxD0/SSO0. Bit 13: PA14MD1 Bit 12: PA14MD0 Description 0 0 General input/output (PA14) 1 Transmit data output (TxD0) 0 Transmit data output (SSO0) 1 Received (Do not set) 1 8 PA12MD Bits 15 and 14--PA15 Mode Bit 1,0 (PA15MD1, PA15MD0): Selects the function of pin PA15/RxD0/SSI0. 1 Bit 13--Reserved: This bit is always read as 0. The write value should always be 0. 15 PA15MD1 PA15MD0 PA14MD1 PA14MD0 (Initial value) * Bit 12: PA14MD Bit: (Initial value) 21.3.3 Port B IO Register (PBIOR) 22.3.3 Port B IO Register (PBIOR) 750 Description amended Bits PB15IOR to PB0IOR correspond to pins PB15/PULS5/SCK2 to PB0/TO6A. PBIOR is enabled when port B pins function as general input/output pins (PB15 to PB0) or serial clock pins (SCK0, SCK1, SCK2), and disabled otherwise. Bits PB15IOR to PB0IOR correspond to pins PB15/PULS5/SCK2/SSCK1 to PB0/TO6A. PBIOR is enabled when port B pins function as general input/output pins (PB15 to PB0) or serial clock pins (SCK0, SCK1, SCK2, SSCK0, SSCK1), and disabled otherwise. When port B pins function as PB15 to PB0 or SCK0, SCK1, and SCK2, a pin becomes an output when the corresponding bit in PBIOR is set to 1, and an input when the bit is cleared to 0. When port B pins function as PB15 to PB0 or SCK0, SCK1, SCK2, SSCK0, and SSCK1, a pin becomes an output when the corresponding bit in PBIOR is set to 1, and an input when the bit is cleared to 0. PBIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. PBIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. Rev. 5.00 Feb. 24, 2010 Page xxxv of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 21.3.4 Port B Control Registers H and L (PBCRH, PBCRL) 22.3.4 Port B Control Registers H and L (PBCRH, PBCRL) 751, 752 Description amended PBCRH and PBCRL are initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. They are not initialized in software standby mode or sleep mode. PBCRH and PBCRL are initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode and in software standby mode. They are not initialized in sleep mode. Port B Control Register H (PBCRH) Port B Control Register H (PBCRH) Bit: Initial value: R/W: * 15 11 10 PB15 MD1 -- PB13 MD 0 0 0 R/W R R/W Bits 15 and 14--PB15 Mode Bits 1 and 0 (PB15MD1, PB15MD0): These bits select the function of pin PB15/PULS5/SCK2. Bit: 15 11 10 PB15 MD1 PB13 MD1 PB13 MD0 0 0 0 R/W R/W R/W Initial value: R/W: * Bits 15 and 14--PB15 Mode Bits 1 and 0 (PB15MD1, PB15MD0): These bits select the function of pin PB15/PULS5/SCK2/SSCK1. Bit 15: PB15MD1 Bit 14: PB15MD0 Description Bit 15: PB15MD1 Bit 14: PB15MD0 Description 1 1 Reserved (Do not set) 1 1 Serial clock output (SSCK1) * Bit 11--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 10--PB13 Mode Bit (PB13MD): Selects the function of pin PB13/SCK0. Bit 10: PB13MD Description 0 General input/output (PB13) 1 Serial clock input/output (SCK0) * Bits 11 and 10--PB13 Mode Bit 1,0 (PB13MD1, PB13MD0): Selects the function of pin PB13/SCK0/SSCK0. Bit 11: PB13MD1 Bit 10: PB13MD0 Description 0 0 General input/output (PB13) 1 Serial clock input/output (SCK0) 0 Serial clock output (SSCK0) 1 Reserved (Do not set) (Initial value) 1 (Initial value) 21.3.5 Port B Invert Register (PBIR) 22.3.5 Port B Invert Register (PBIR) 756 Description amended Bits PB15IR to PB13IR and PB11IR to PB0IR correspond to pins PB15/PULS5/SCK2 to PB13/SCK0 and PB11/RxD4/HRxD0/TO8H to PB0/TO6A. PBIR is enabled when port B pins function as ATU-II outputs or serial clock pins, and disabled otherwise. Bits PB15IR to PB13IR and PB11IR to PB0IR correspond to pins PB15/PULS5/SCK2/SSCK1 to PB13/SCK0/SSCK0 and PB11/RxD4/HRxD0/TO8H to PB0/TO6A. PBIR is enabled when port B pins function as ATU-II outputs or serial clock pins, and disabled otherwise. ...PBIR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. ...PBIR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. Rev. 5.00 Feb. 24, 2010 Page xxxvi of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 21.3.6 Port C IO Register (PCIOR) 22.3.6 Port C IO Register (PCIOR) 757 Description amended PCIOR is enabled when port C pins function as general input/output pins (PC4 to PC0), and disabled otherwise. PCIOR is enabled when port C pins function as general input/output pins (PC4 to PC0 or transmit/receive input/output for the SSU (SSI1 and SSO1)), and disabled otherwise. When port C pins function as PC4 to PC0, a pin becomes an output when the corresponding bit in PCIOR is set to 1, and an input when the bit is cleared to 0. PCIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. When port C pins function as PC4 to PC0 or transmit/receive input/output for the SSU (SSI1 and SSO1), a pin becomes an output when the corresponding bit in PCIOR is set to 1, and an input when the bit is cleared to 0. PCIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. 21.3.7 Port C Control Register (PCCR) 22.3.7 Port C Control Register (PCCR) 758 Bit table amended Bit: 7 6 5 4 0 -- PC3MD -- PC2MD PC0MD Initial value: 0 0 0 0 0 R/W: R R/W R R/W R/W Bit: 7 6 5 4 PC3MD1 PC3MD0 PC2MD1 PC2MD0 Initial value: R/W: 0 PC0MD 0 0 0 0 0 R/W R/W R/W R/W R/W Description amended PCCR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. PCCR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and software standby mode. It is not initialized in . sleep mode. * Bit 7--Reserved: This bit is always read as 0. The write value should always be 0. * * Bit 6--PC3 Mode Bit (PC3MD): Selects the function of pin PC3/RxD2. Bits 7 and 6--PC3 Mode Bit 1, 0 (PC3MD1, PC3MD0): Selects the function of pin PC3/RxD2/SSI1. Bit 7: PC3MD1 Bit 6: PC3MD0 Description 0 0 General input/output (PC3) 1 Receive data input (RxD2) 0 Receive data input (SSI1) 1 Reserved (Do not set) 1 Bit 6: PC3MD Description 0 General input/output (PC3) 1 Receive data input (RxD2) (Initial value) * Bit 5--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 4--PC2 Mode Bit (PC2MD): Selects the function of pin PC2/TxD2. Bit 4: PC2MD Description 0 General input/output (PC2) 1 Transmit data output (TxD2) (Initial value) * Bits 5 and 4--PC2 Mode Bit 1, 0 (PC2MD1, PC2MD0): Selects the function of pin PC2/TxD2/SSO1. Bit 5: PC2MD1 Bit 4: PC2MD0 Description 0 0 General input/output (PC2) 1 Transmit data output (TxD2) 0 Transmit data output (SSO1) 1 Reserved (Do not set) 1 (Initial value) (Initial value) 21.3.8 Port D IO Register (PDIOR) 22.3.8 Port D IO Register (PDIOR) 759 Description amended PDIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. PDIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized sleep mode. Rev. 5.00 Feb. 24, 2010 Page xxxvii of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 21.3.9 Port D Control Registers H and L (PDCRH, PDCRL) 22.3.9 Port D Control Registers H and L (PDCRH, PDCRL) 760 Description amended PDCRH and PDCRL are initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. They are not initialized in software standby mode or sleep mode. PDCRH and PDCRL are initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. They are not initialized in sleep mode. 21.3.10 Port E IO Register (PEIOR) 22.3.10 Port E IO Register (PEIOR) 764 Description amended PEIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. PEIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. 21.3.11 Port E Control Register (PECR) 22.3.11 Port E Control Register (PECR) 765 Description amended PECR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. PECR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. 21.3.12 Port F IO Register (PFIOR) 22.3.12 Port F IO Register (PFIOR) 770 Description amended Bits PF15IOR to PF0IOR correspond to pins PF15/BREQ to PF0/A16. Bits PF15IOR to PF0IOR correspond to pins PF15/BREQ/SCS1 to PF0/A16. ... PFIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. ... PFIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. It is not initialized by a WDT power-on reset. Rev. 5.00 Feb. 24, 2010 Page xxxviii of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 21.3.13 Port F Control Registers H and L (PFCRH, PFCRL) 22.3.13 Port F Control Registers H and L (PFCRH, PFCRL) 771, 772 Description amended PFCRH and PFCRL are initialized to H'0015 and H'5000, respectively, by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. They are not initialized in software standby mode or sleep mode. PFCRH and PFCRL are initialized to H'0015 and H'5000, respectively, by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. They are not initialized in sleep mode. Bit: 15 14 CKHIZ PF15MD Initial value: R/W: 13 12 11 8 -- PF14MD -- PF12MD 0 0 0 0 0 0 R/W R/W R R/W R R/W Bit: Initial value: R/W: * Bit 14--PF15 Mode Bit (PF15MD): Selects the function of pin PF15/BREQ. * Description Bit 14: PF15MD Expanded Mode Single-Chip Mode 0 General input/output (PF15) (Initial value) General input/output (PF15) (Initial value) Bus request input (BREQ ) General input/output (PF15) 1 * Bit 13--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 12--PF14 Mode Bit (PF14MD): Selects the function of pin PF14/BACK. Expanded Mode Single-Chip Mode 0 General input/output (PF14) (Initial value) General input/output (PF14) (Initial value) Bus acknowledge output (BACK) General input/output (PF14) 1 13 12 11 8 PF12MD 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Bits 14 and 13--PF15 Mode Bit 0, 1 (PF15MD0, PF15MD1): Selects the function of pin PF15/BREQ/SCS1. Description Bit 13: PF15MD1 Expanded Mode Single-Chip Mode 0 0 General input/output (PF15) (Initial value) General input/output (PF15) (Initial value) 1 Reserved (Do not set) Chip select input/output (SCS1) 1 0 Bus request input (BREQ) General input/output (PF15) 1 Reserved (Do not set) * Bits 12 and 11--PF14 Mode Bit 0,1(PF14MD0, PF14MD1): Selects the function of pin PF14/BACK/SCS0. Description Bit 12: PF14MD0 Bit 11: PF14MD1 Expanded Mode Single-Chip Mode 0 0 General input/output (PF14) (Initial value) General input/output (PF14) (Initial value) 1 Reserved (Do not set) Chip select input/output (SCS0) 0 Bus acknowledge output (BACK) General input/output (PF14) 1 Reserved (Do not set) 1 * 14 Bit 14: PF15MD0 Description Bit 12: PF14MD 15 CKHIZ PF15MD PF15MD PF14MD PF14MD 0 1 0 1 Bit 11--Reserved: This bit is always read as 0. The write value should always be 0. 21.3.14 Port G IO Register (PGIOR) 22.3.14 Port G IO Register (PGIOR) 776 Description amended PGIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. PGIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, in software standby mode. It is not initialized in . sleep mode. 21.3.15 Port G Control Register (PGCR) 22.3.15 Port G Control Register (PGCR) 777 Description amended PGCR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. PGCR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. Rev. 5.00 Feb. 24, 2010 Page xxxix of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 21.3.16 Port H IO Register (PHIOR) 22.3.16 Port H IO Register (PHIOR) 778 Description amended PHIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. PHIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. 21.3.17 Port H Control Register (PHCR) 22.3.17 Port H Control Register (PHCR) 779 Description amended PHCR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. PHCR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. 21.3.18 Port J IO Register (PJIOR) 22.3.18 Port J IO Register (PJIOR) 785 Description amended PJIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. PJIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. 21.3.19 Port J Control Registers H and L (PJCRH, PJCRL) 22.3.19 Port J Control Registers H and L (PJCRH, PJCRL) 786 Description amended PJCRH and PJCRL are initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. They are not initialized in software standby mode or sleep mode. PJCRH and PJCRL are initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. They are not initialized in sleep mode. 21.3.20 Port K IO Register (PKIOR) 22.3.20 Port K IO Register (PKIOR) 790 Description amended PKIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. PKIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. 21.3.21 Port K Control Registers H and L (PKCRH, PKCRL) 22.3.21 Port K Control Registers H and L (PKCRH, PKCRL) 790 Description amended PKCRH and PKCRL are initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. They are not initialized in software standby mode or sleep mode. PKCRH and PKCRL are initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. They are not initialized in sleep mode. 21.3.22 Port K Invert Register (PKIR) 22.3.22 Port K Invert Register (PKIR) 795 Description amended PKIR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. PKIR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. Rev. 5.00 Feb. 24, 2010 Page xl of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 21.3.23 Port L IO Register (PLIOR) 22.3.23 Port L IO Register (PLIOR) 796 Description amended Bits PL13IOR to PL0IOR correspond to pins PL13/IRQOUT to PL0/TI10. PLIOR is enabled when port L pins function as general input/output pins (PL13 to PL0), timer input/output pins (TIO11A, TIO11B), or serial clock pins (SCK2, SCK3, SCK4), and disabled otherwise. Bits PL13IOR to PL0IOR correspond to pins PL13/IRQOUT/SCS1 to PL0/TI10. PLIOR is enabled when port L pins function as general input/output pins (PL13 to PL0), timer input/output pins (TIO11A, TIO11B), or serial clock pins (SCK2, SCK3, SCK4, SSCK1), and disabled otherwise. When port L pins function as PL13 to PL0, TIO11A and TIO11B, or SCK2, SCK3, and SCK4, a pin becomes an output when the corresponding bit in PLIOR is set to 1, and an input when the bit is cleared to 0. PLIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. When port L pins function as PL13 to PL0, TIO11A and TIO11B, or SCK2, SCK3, SCK4, and SSCK1 a pin becomes an output when the corresponding bit in PLIOR is set to 1, and an input when the bit is cleared to 0. PLIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. 21.3.24 Port L Control Registers H and L (PLCRH, PLCRL) 22.3.24 Port L Control Registers H and L (PLCRH, PLCRL) Port L Control Register H (PLCRH) Port L Control Register H (PLCRH) 797, 798 Description amended PLCRH and PLCRL are initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. They are not initialized in software standby mode or sleep mode. PLCRH and PLCRL are initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. They are not initialized in sleep mode. Bit: * 15 9 8 -- -- PL12 MD Initial value: 0 0 0 R/W: R R R/W Bits 11 and 10--PL13 Mode Bits 1 and 0 (PL13MD1, PL13MD0): These bits select the function of pin PL13/IRQOUT. Bit 11: PL13MD1 Bit 10: PL13MD0 Description 0 0 General input/output (PL13) 1 IRQOUT is fixed high (IRQOUT) 0 IRQOUT is output by INTC interrupt request (IRQOUT) 1 Reserved (Do not set) 1 (Initial value) Bit: * Bit 9--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 8--PL12 Mode Bit (PL12MD): Selects the function of pin PL12/IRQ4. Description 0 General input/output (PL12) 1 Interrupt request input (IRQ4) 8 -- PL12 MD1 PL12 MD0 0 0 0 R/W: R R/W R/W Bits 11 and 10--PL13 Mode Bits 1 and 0 (PL13MD1, PL13MD0): These bits select the function of pin PL13/IRQOUT/SCS1. Bit 11: PL13MD1 Bit 10: PL13MD0 Description 0 0 General input/output (PL13) 1 IRQOUT is fixed high (IRQOUT) * 0 IRQOUT is output by INTC interrupt request (IRQOUT) 1 Chip select input/output (SCS1) (Initial value) Bit 9, 8--PL12 Mode Bit 1,0 (PL12MD0,PL12MD0): Selects the function of pin PL12/IRQ4/SCS0. Bit 9: PL12MD1 Bit 8: PL12MD0 0 0 General input/output (PL12) 1 Interrupt request input (IRQ4) 1 Bit 8: PL12MD 9 Initial value: 1 * 15 Description 0 Chip select input/output (SCS0) 1 Reserved (Do not set) (Initial value) (Initial value) Rev. 5.00 Feb. 24, 2010 Page xli of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 21.3.24 Port L Control Registers H and L (PLCRH, PLCRL) 22.3.24 Port L Control Registers H and L (PLCRH, PLCRL) Port L Control Register L (PLCRL) Port L Control Register L (PLCRL) 799 Description amended Bit: 15 14 8 -- PL7MD PL4MD Initial value: 0 0 0 R/W: R R/W R/W * Bit 15--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 14--PL7 Mode Bit (PL7MD): Selects the function of pin PL7/SCK2. Bit 14: PL7MD Description 0 General input/output (PL7) 1 Serial clock input/output (SCK2) Bit: 15 14 PL7MD1 PL7MD0 Initial value: R/W: * 0 0 R/W R/W R/W Bits 15 and 14--PL7 Mode Bit 1, 0 (PL7MD1, PL7MD0): Selects the function of pin PL7/SCK2/SSCK1. Bit 14: PL7MD0 0 0 General input/output (PL7) 1 Serial clock input/output (SCK2) 0 Serial clock output (SSCK1) 1 Reserved (Do not set) 1 PL4MD 0 Bit 15: PL7MD1 (Initial value) 8 Description (Initial value) 21.3.25 Port L Invert Register (PLIR) 22.3.25 Port L Invert Register (PLIR) 801 Description amended Bits PL9IR to PL7IR correspond to pins PL9/SCK4/IRQ5 to PL7/SCK2. PLIR is enabled when port L pins function as serial clock pins, and disabled otherwise. Bits PL9IR to PL7IR correspond to pins PL9/SCK4/IRQ5 to PL7/SCK2/SCK1. PLIR is enabled when port L pins function as serial clock pins, and disabled otherwise. ...PLIR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode ...PLIR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. 22.2 Port A 23.2 Port A Figure 22.1 Port A Figure 23.1 Port A 803 Figure amended PA15 (I/O) / RxD0 (input) PA15 (I/O) / RxD0 (input) / SSI0 (input) PA14 (I/O) / TxD0 (output) PA14 (I/O) / TxD0 (output) / SSO0 (output) 22.2.1 Register Configuration 23.2.1 Register Configuration Table 22.1 Register Configuration Table 23.1 Register Configuration 804 Note deleted Note: Register access with an internal clock multiplication ratio of 4 requires four or five internal clock () cycles. 22.2.2 Port A Data Register (PADR) 23.2.2 Port A Data Register (PADR) 804 Description amended Bits PA15DR to PA0DR correspond to pins PA15/RxD0 to PA0/TI0A. Bits PA15DR to PA0DR correspond to pins PA15/RxD0/SSI0 to PA0/TI0A. ...PADR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. ...PADR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. 22.2.3 Port A Port Register (PAPR) 23.2.3 Port A Port Register (PAPR) 805 Description amended Bits PA15PR to PA0PR correspond to pins PA15/RxD0 to PA0/TI0A. Bits PA15PR to PA0PR correspond to pins PA15/RxD0/SSI0 to PA0/TI0A. Rev. 5.00 Feb. 24, 2010 Page xlii of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 22.3 Port B 23.3 Port B Figure 22.2 Port B Figure 23.2 Port B 806 Figure amended PB15 (I/O) / PULS5 (output) / SCK2 (I/O) PB15 (I/O) / PULS5 (output) / SCK2 (I/O) / SSCK1 (output) PB13 (I/O) / SCK0 (I/O) PB13 (I/O) / SCK0 (I/O) / SSCK0 (output) 22.3.1 Register Configuration 23.3.1 Register Configuration Table 22.3 Register Configuration Table 23.3 Register Configuration 806 Note deleted Note: Register access with an internal clock multiplication ratio of 4 requires four or five internal clock () cycles. 22.3.2 Port B Data Register (PBDR) 23.3.2 Port B Data Register (PBDR) 807 Description amended Bits PB15DR to PB0DR correspond to pins PB15/PULS5/SCK2 to PB0/TO6A. Bits PB15DR to PB0DR correspond to pins PB15/PULS5/SCK2/SSCK1 to PB0/TO6A. ...PBDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. ...PBDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. 22.3.3 Port B Port Register (PBPR) 23.3.3 Port B Port Register (PBPR) 808 Description amended Bits PB15PR to PB0PR correspond to pins PB15/PULS5/SCK2 to PB0/TO6A. Bits PB15PR to PB0PR correspond to pins PB15/PULS5/SCK2/SSCK1 to PB0/TO6A. 22.4 Port C 23.4 Port C Figure 22.3 Port C Figure 23.3 Port C 808 Figure amended PC3 (I/O) / RxD2 (input) PC3 (I/O) / RxD2 (input) / SSI1 (input) PC2 (I/O) / TxD2 (output) PC2 (I/O) / TxD2 (output) / SSO1 (output) 22.4.1 Register Configuration 23.4.1 Register Configuration Table 22.5 Register Configuration Table 23.5 Register Configuration 808 Note deleted Note: Register access with an internal clock multiplication ratio of 4 requires four or five internal clock () cycles. 22.4.2 Port C Data Register (PCDR) 23.4.2 Port C Data Register (PCDR) 809 Description amended PCDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. PCDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. 22.5.1 Register Configuration 23.5.1 Register Configuration Table 22.7 Register Configuration Table 23.7 Register Configuration 810 Note deleted Note: Register access with an internal clock multiplication ratio of 4 requires four or five internal clock () cycles. Rev. 5.00 Feb. 24, 2010 Page xliii of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 22.5.2 Port D Data Register (PDDR) 23.5.2 Port D Data Register (PDDR) 811 Description amended PDDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. PDDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. 22.6.1 Register Configuration 23.6.1 Register Configuration Table 22.9 Register Configuration Table 23.9 Register Configuration 813 Note deleted Note: Register access with an internal clock multiplication ratio of 4 requires four or five internal clock () cycles. 22.6.2 Port E Data Register (PEDR) 23.6.2 Port E Data Register (PEDR) 814 Description amended PEDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. PEDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. 22.7 Port F 23.7 Port F Figure 22.6 Port F Figure 23.6 Port F 816 Figure amended Single-chip mode Single-chip mode PF15 (I/O) PF15 (I/O) / SCS1 (I/O) PF14 (I/O) PF14 (I/O) / SCS0 (I/O) 22.7.1 Register Configuration 23.7.1 Register Configuration Table 22.11 Register Configuration Table 23.11 Register Configuration 816 Note deleted Note: Register access with an internal clock multiplication ratio of 4 requires four or five internal clock () cycles. 22.7.2 Port F Data Register (PFDR) 23.7.2 Port F Data Register (PFDR) 817 Description amended Bits PF15DR to PF0DR correspond to pins PF15/BREQ to PF0/A16. Bits PF15DR to PF0DR correspond to pins PF15/BREQ/SCS1 to PF0/A16. ... PFDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. ... PFDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. 22.8.1 Register Configuration 23.8.1 Register Configuration Table 22.13 Register Configuration Table 23.13 Register Configuration 819 Note deleted Note: Register access with an internal clock multiplication ratio of 4 requires four or five internal clock () cycles. 22.8.2 Port G Data Register (PGDR) 23.8.2 Port G Data Register (PGDR) 819 Description amended PGDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. PGDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. Rev. 5.00 Feb. 24, 2010 Page xliv of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 22.9.1 Register Configuration 23.9.1 Register Configuration Table 22.15 Register Configuration Table 23.15 Register Configuration 822 Note deleted Note: Register access with an internal clock multiplication ratio of 4 requires four or five internal clock () cycles. 22.9.2 Port H Data Register (PHDR) 23.9.2 Port H Data Register (PHDR) 822 Description amended PHDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. PHDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. 22.10.1 Register Configuration 23.10.1 Register Configuration Table 22.17 Register Configuration Table 23.17 Register Configuration 824 Note deleted Note: Register access with an internal clock multiplication ratio of 4 requires four or five internal clock () cycles. 22.10.2 Port J Data Register (PJDR) 23.10.2 Port J Data Register (PJDR) 824 Description amended PJDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. PJDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. 22.11.1 Register Configuration 23.11.1 Register Configuration Table 22.19 Register Configuration Table 23.19 Register Configuration 826 Note deleted Note: Register access with an internal clock multiplication ratio of 4 requires four or five internal clock () cycles. 22.11.2 Port K Data Register (PKDR) 23.11.2 Port K Data Register (PKDR) 827 Description amended PKDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. PKDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. 22.12 Port L 23.12 Port L Figure 22.11 Port L Figure 23.11 Port L 828 Pin name added PL13 (I/O) / IRQOUT (output) PL13 (I/O) / IRQOUT (output) / SCS1 (I/O) PL12 (I/O) / IRQ4 (input) PL12 (I/O) / IRQ4 (input) / SCS0 (I/O) PL7 (I/O) / SCK2 (I/O) PL7 (I/O) / SCK2 (I/O) / SSCK1 (output) 22.12.1 Register Configuration 23.12.1 Register Configuration Table 22.21 Register Configuration Table 23.21 Register Configuration 828 Note deleted Note: Register access with an internal clock multiplication ratio of 4 requires four or five internal clock () cycles. Rev. 5.00 Feb. 24, 2010 Page xlv of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 22.12.2 Port L Data Register (PLDR) 23.12.2 Port L Data Register (PLDR) 829 Description amended Bits PL13DR to PL0DR correspond to pins PL13/IRQOUT to PL0/TI10. Bits PL13DR to PL0DR correspond to pins PL13/IRQOUT/SCS1 to PL0/TI10. ... PLDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. ... PLDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. 23.1 Features 24.1 Features 833, 834 Description amended * * Two flash-memory MATs according to LSI initiation mode The user boot MAT is initiated at a power-on reset in user boot mode: 8 kbytes Two flash-memory MATs according to LSI initiation mode The user boot MAT is initiated at a power-on reset in user boot mode: 12 Kbytes * Operating frequency at programming/erasing The operating frequency at programming/erasing is a maximum of 40 MHz. * Operating frequency at programming/erasing The operating frequency at programming/erasing is a maximum of 80 MHz. 23.2.1 Block Diagram 24.2.1 Block Diagram Figure 23.1 Block Diagram of Flash Memory Figure 24.1 Block Diagram of Flash Memory 835 Figure amended Memory MAT unit Memory MAT unit User boot MAT : 8 kbytes User boot MAT : 12 Kbytes 23.2.4 Flash Memory Configuration 24.2.4 Flash Memory Configuration Figure 23.3 Flash Memory Configuration Figure 24.3 Flash Memory Configuration 839 Description amended This LSI's flash memory is configured by the 1-Mbyte user MAT and 8-kbyte user boot MAT. This LSI's flash memory is configured by the 1-Mbyte user MAT and 12-Kbyte user boot MAT. Figure amended <User Boot MAT> <User Boot MAT> Address H'00,0000 to H'00,1FFF 8 kbytes Address H'00,0000 to H'00,2FFF 12 Kbytes Description amended The user MAT and user boot MAT have different memory sizes. Do not access a user boot MAT that is 8 kbytes or more. When a user boot MAT exceeding 8 kbytes is read from, an undefined value is read. Rev. 5.00 Feb. 24, 2010 Page xlvi of xciv REJ09B0177-0500 The user MAT and user boot MAT have different memory sizes. Do not access a user boot MAT that is 12 Kbytes or more. When a user boot MAT exceeding 12 Kbytes is read from, an undefined value is read. Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 23.4.2 Programming/Erasing Interface Registers 24.4.2 Programming/Erasing Interface Registers 847 Descritpion amended The programming/erasing interface registers are as described below. They are all 8-bit registers that can be accessed in bytes. Except for the FLER bit in FCCS and FMATS, these registers are initialized at a power-on reset, in hardware standby mode, or in software standby mode. The FLER bit or FMATS is not initialized in software standby mode. The programming/erasing interface registers are as described below. They are all 8-bit registers that can be accessed in bytes. These regiseters are initialized at a power-on reset, in hardware standby mode, or in software standby mode. * Bit 0--Source Program Copy Operation (SCO): ... Four NOP instructions must be executed immediately after setting this bit to 1. * Bit 0--Source Program Copy Operation (SCO): ... Eight NOP instructions must be executed immediately after setting this bit to 1. 23.4.3 Programming/Erasing Interface Parameters 24.4.3 Programming/Erasing Interface Parameters 851 Description amended ... This parameter uses the general registers of the CPU (R4, R5, and R0) or the on-chip RAM area. The initial value is undefined at a power-on reset or in hardware standby mode. ... This parameter uses the general registers of the CPU (R4, R5, and R0) or the on-chip RAM area. The initial value is undefined at a power-on reset, in hardware standby mode, or in software standby mode. (1) Download Control (1) Download Control 852 Description amended ... The on-chip RAM area to be downloaded is the area as much as 2 kbytes starting from the start address specified by FTDAR. For the address map of the on-chip RAM, see figure 23.10. ...The on-chip RAM area to be downloaded is the area as much as 3 Kbytes starting from the start address specified by FTDAR. For the address map of the on-chip RAM, see figure 24.10. 23.4.4 RAM Emulation Register (RAMER) 24.4.4 RAM Emulation Register (RAMER) 862 Description amended ... RAMER is initialized to H'0000 at a power-on reset or in hardware standby mode and is not initialized in software standby mode. The RAMER setting must be executed in user mode or in user program mode. ... RAMER is initialized to H'0000 at a power-on reset or in hardware standby mode, or in software standby mode. The RAMER setting must be executed in user mode or in user program mode. 23.5.1 Boot Mode 24.5.1 Boot Mode 864 Description added ...After the SCI bit rate is automatically adjusted, the communication with the host is executed by means of the control command method. ... After the SCI bit rate is automatically adjusted, the communication with the host is executed by means of the control command method. The RAM areas used by boot mode are 3 Kbytes starting at address H'FFFF0000, 4 Kbytes starting at address H'FFFFB000, and 128 bytes from H'FFFFBF80 to H'FFFFBFFF, which are used as the stack. (1) SCI Interface Setting by Host (1) SCI Interface Setting by Host Table 23.8 System Clock Frequency that Can Automatically Adjust Bit Rate of This LSI Table 24.8 System Clock Frequency that Can Automatically Adjust Bit Rate of This LSI 865 Table amended Host Bit Rate System Clock Frequency Which Can Automatically Adjust LSI's Bit Rate Host Bit Rate System Clock Frequency Which Can Automatically Adjust LSI's Bit Rate 9,600 bps 20 to 40 MHz (input frequency of 5 to 10 MHz) 9,600 bps 40 to 80 MHz (input frequency of 5 to 10 MHz) 19,200 bps 20 to 40 MHz (input frequency of 5 to 10 MHz) 19,200 bps 40 to 80 MHz (input frequency of 5 to 10 MHz) Rev. 5.00 Feb. 24, 2010 Page xlvii of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 23.5.2 User Program Mode 24.5.2 User Program Mode (1) On-Chip RAM Address Map when Programming/Erasing is Executed (1) On-Chip RAM Address Map when Programming/Erasing is Executed Figure 23.10 RAM Map after Download Figure 24.10 RAM Map after Download 869 Figure amended Area to be downloaded (Size: 2 kbytes) Area to be downloaded (Size: 3 Kbytes) Address Address FTDAR setting+2048 FTDAR setting+3072 (2.3) VBR is cleared to 0 and 1 is written to the SCO bit of FCCS, and then download is executed. (2.3) VBR is cleared to 0 and 1 is written to the SCO bit of FCCS, and then download is executed. 871 Description amended When download is executed, particular interrupt processing, which is accompanied by the bank switch as described below, is performed as an internal microcomputer processing, so VBR need to be cleared to 0. Four NOP instructions are executed immediately after the instructions that set the SCO bit to 1. When download is executed, particular interrupt processing, which is accompanied by the bank switch as described below, is performed as an internal microcomputer processing, so VBR need to be cleared to 0. Eight NOP instructions are executed immediately after the instructions that set the SCO bit to 1. (4) Erasing and Programming Procedure in User Program Mode (4) Erasing and Programming Procedure in User Program Mode Figure 23.13 Sample Procedure of Repeating RAM Emulation, Erasing, and Programming (Overview) Figure 24.13 Sample Procedure of Repeating RAM Emulation, Erasing, and Programming (Overview) 877 Figure amended Set FTDAR to H'03 Set FTDAR to H'04 (Specify H'FFFF1800 as download destination) (Specify H'FFFF2000 as download destination) Description amended * Be sure to initialize both the erasing program and programming program. Initialization by setting the FPEFEQ and FUBRA parameters must be performed for both the erasing program and the programming program. Initialization must be executed for both entry addresses: (download start address for erasing program) + 32 bytes (H'FFFF1020 in this example) and (download start address for programming program) + 32 bytes (H'FFFF1820 in this example). * 23.5.3 User Boot Mode 24.5.3 User Boot Mode (1) User Boot Mode Initiation (1) User Boot Mode Initiation 878 Description amended ... When the reset start is executed in user boot mode, the check routine for flash-memory related registers runs. The RAM area about 1.2 kbytes from H'FFFF0800 and 4 bytes from H'FFFFBFFC (a stack area) is used by the routine. While the check routine is running, NMI and all other interrupts cannot be accepted. Neither can the AUD be used in this period. This period is 100 s while operating at an internal frequency of 40 MHz. ... When the reset start is executed in user boot mode, the check routine for flash-memory related registers runs. The RAM area about 3 Kbytes from H'FFFFB000 and 128 bytes from H'FFFFBF80 to H'FFFFBFFF (a stack area) is used by the routine. While the check routine is running, NMI and all other interrupts cannot be accepted. Neither can the AUD be used in this period. This period is 100 s while operating at an internal frequency of 80 MHz. Rev. 5.00 Feb. 24, 2010 Page xlviii of xciv REJ09B0177-0500 Be sure to initialize both the erasing program and programming program. Initialization by setting the FPEFEQ and FUBRA parameters must be performed for both the erasing program and the programming program. Initialization must be executed for both entry addresses: (download start address for erasing program) + 32 bytes (H'FFFF1020 in this example) and (download start address for programming program) + 32 bytes (H'FFFF2020 in this example). Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 23.6.1 Hardware Protection 24.6.1 Hardware Protection 881 Description amended Programming and erasing of flash memory is forcibly disabled or suspended by hardware protection. In this state, the downloading of an on-chip program and initialization of the flash memory are possible. Programming and erasing of flash memory is forcibly disabled or suspended by hardware protection. In this state by the FWE pin, the downloading of an on-chip program and initialization of the flash memory are possible. 23.6.3 Error Protection 24.6.3 Error Protection Figure 23.16 Transitions to and from Error Protection State Figure 24.16 Transitions to and from Error Protection State 883, 884 Description amended * When the relevant bank area of flash memory is read during programming/erasing (including a vector read or an instruction fetch) * Flash memory is read during programming/erasing (including a vector read or an instruction fetch) * * When a SLEEP instruction (including software standby mode) is executed during programming/erasing When a SLEEP instruction programming/erasing ...Note that the reset signal should only be released after providing a reset input over a period longer than the normal 100 s. is executed during ...Note that the reset signal should only be released after providing a reset input over a period longer than the normal 100 s. Figure amended Program mode Erase mode Read disabled Programming/erasing enabled FLER=0 Reset or standby (Hardware protection) Program mode Erase mode Read enabled Programming/erasing disabled Read disabled Programming/erasing enabled FLER=0 RES = 0 or HSTBY = 0 Er Error occurred Error protection mode Read enabled Programming/erasing disabled FLER=1 ror FLER=0 or =0 =0 (S curr ES Programming/erasing interface BY oft ed R T register is in its initial state. wa HS RES=0 or re sta HSTBY=0 nd by ) oc Software standby mode ror FLER=0 or =0 =0 (S curr ES Programming/erasing interface BY oft ed R T register is in its initial state. wa HS RES=0 , re sta HSTBY=0 nd by or software standby mode cancellation ) oc Software standby mode Error protection mode Read enabled Programming/erasing disabled FLER=1 Read disabled Cancel Programming/erasing disabled software standby mode FLER=1 Read enabled Programming/erasing disabled Er Error occurred Error protection mode (Software standby) Reset or standby (Hardware protection) RES = 0 or HSTBY = 0 (Software standby) Read disabled Programming/erasing disabled FLER=undefined The power is not supplied in this LSI. Programming/erasing interface register is in its initial state. 23.7 Flash Memory Emulation in RAM 24.7 Flash Memory Emulation in RAM Figure 23.18 Example of Overlapped RAM Operation Figure 24.18 Example of Overlapped RAM Operation 886 Address amended EB0 to EB15 EB0 to EB15 H'00000 H'000000 H'01000 H'001000 H'02000 H'002000 H'03000 H'003000 H'04000 H'004000 H'05000 H'005000 H'06000 H'006000 H'07000 H'007000 H'08000 H'008000 ... ... H'FFFFF H'0FFFFF Rev. 5.00 Feb. 24, 2010 Page xlix of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 23.7 Flash Memory Emulation in RAM 24.7 Flash Memory Emulation in RAM Figure 23.19 Programming of Tuned Data Figure 24.19 Programming of Tuned Data 887 Address amended EB0 to EB15 EB0 to EB15 H'00000 H'000000 H'01000 H'001000 H'02000 H'002000 H'03000 H'003000 H'04000 H'004000 H'05000 H'005000 H'06000 H'006000 H'07000 H'007000 H'08000 H'008000 ... ... H'FFFFF H'0FFFFF 23.8.1 Switching between User MAT and User Boot MAT 24.8.1 Switching between User MAT and User Boot MAT 888 Description amended (2) To ensure that the MAT that has been switched to is accessible, execute four NOP instructions in on-chip RAM immediately after writing to FMATS of on-chip RAM (this prevents access to the flash memory during MAT switching). (2) To ensure that the MAT that has been switched to is accessible, execute eight NOP instructions in on-chip RAM immediately after writing to FMATS of on-chip RAM (this prevents access to the flash memory during MAT switching). (5) Memory sizes of the user MAT and user boot MAT are different. When accessing the user boot MAT, do not access addresses exceeding the 8-kbyte memory space. If access goes beyond the 8-kbyte space, the values read are undefined. (5) Memory sizes of the user MAT and user boot MAT are different. When accessing the user boot MAT, do not access addresses exceeding the 12-Kbyte memory space. If access goes beyond the 12-Kbyte space, the values read are undefined. Figure 23.20 Switching between User MAT and User Boot MAT Figure 24.20 Switching between User MAT and User Boot MAT 889 Figure amended Procedure for switching to the user boot MAT Procedure for switching to the user boot MAT (3) Execute four NOP instructions before accessing the user boot MAT. (3) Execute eight NOP instructions before accessing the user boot MAT. Procedure for switching to the user MAT Procedure for switching to the user MAT (3) Execute four NOP instructions before accessing the user MAT. (3) Execute eight NOP instructions before accessing the user MAT. Rev. 5.00 Feb. 24, 2010 Page l of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 23.8.2 Interrupts during Programming/Erasing 24.8.2 Interrupts during Programming/Erasing (2) Interrupts during programming/erasing (2) Interrupts during programming/erasing 892, 893 Description amended 1. When flash memory is being programmed or erased, both the user MAT and user boot MAT cannot be accessed. Prepare the interrupt vector table and interrupt processing routine in on-chip RAM or external memory. Make sure the flash memory being programmed or erased is not accessed by the interrupt processing routine. If flash memory is read, the read values are not guaranteed. If the relevant bank in flash memory that is being programmed or erased is accessed, the error protection state is entered, and programming or erasing is aborted. If a bank other than the relevant bank is accessed, the error protection state is not entered but the read values are not guaranteed. 1. When flash memory is being programmed or erased, both the user MAT and user boot MAT cannot be accessed. Prepare the interrupt vector table and interrupt processing routine in on-chip RAM or external memory. Make sure the flash memory being programmed or erased is not accessed by the interrupt processing routine. If flash memory is read, the read values are not guaranteed. If . flash memory that is being programmed or erased is accessed, the error protect state is entered, and programming or erasing is aborted. . 5. When a transition is made to sleep mode or software standby mode in the interrupt processing routine, the error protection state is entered and programming/erasing is aborted. 5. When a transition is made to sleep mode in the interrupt processing routine, the error protection state is entered and programming/erasing is aborted. 23.8.3 Other Notes 24.8.3 Other Notes 893, 894 Description amended 1. Download time of on-chip program 1. Download time of on-chip program The programming program that includes the initialization routine and the erasing program that includes the initialization routine are each 2 kbytes or less. Accordingly, when the CPU clock frequency is 40 MHz, the download for each program takes approximately 75 s at maximum. The programming program that includes the initialization routine and the erasing program that includes the initialization routine are each 3 Kbytes or less. Accordingly, when the CPU clock frequency is 80 MHz, the download for each program takes approximately 305 s at maximum. 2. User branch processing intervals 2. User branch processing intervals The intervals for executing the user branch processing differs in programming and erasing. The processing phase also differs. Table 23.11 lists the maximum and minimum intervals for initiating the user branch processing when the CPU clock frequency is 40 MHz. The intervals for executing the user branch processing differs in programming and erasing. The processing phase also differs. Table 24.11 lists the minimum and maximum user branch processing intervals when the CPU clock frequency is 80 MHz. Table 23.11 Initiation Intervals of User Branch Processing Table 24.11 User Branch Processing Intervals Table and title amended Processing Name Maximum Interval Minimum Interval Processing Name Maximum Interval Programming Approximately 1 ms Approximately 17 s Programming Approximately 1 ms Approximately 19 s Erasing Approximately 5 ms Approximately 17 s Erasing Approximately 5 ms Approximately 19 s Minimum Interval However, when operation is done with CPU clock of 40 MHz, maximum and minimum values of the time until initial user branch processing are as shown in table 23.12. However, when operation is done with CPU clock of 80 MHz, maximum and minimum values of the time until initial user branch processing are as shown in table 24.12. Table 23.12 Initial User Branch Processing Time Table 24.12 Intervals Until Start of User Branch Processing . Table and title amended Processing Name Max. Min. Processing Name Max. Min. Programming Approximately 113 s Approximately 113 s Programming Approximately 500 s Approximately 500 s Erasing Approximately 85 s Approximately 45 s Erasing Approximately 2300 s Approximately 1000 s Rev. 5.00 Feb. 24, 2010 Page li of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 23.8.3 Other Notes 24.8.3 Other Notes 894 Description amended 4. State in which AUD operation is disabled and interrupts are ignored 4. State in which AUD operation is disabled and interrupts are ignored Checking the flash-memory related registers immediately after user boot mode is initiated (Approximately 100 s if operation is done at an internal frequency of 40 MHz after the reset signal is released) Checking the flash-memory related registers immediately after user boot mode is initiated (Approximately 100 s if operation is done at an internal frequency of 80 MHz after the reset signal is released) 7. FWE pin state Newly added 23.9 Programmer Mode 24.9 Programmer Mode 894 Description amended In programmer mode, set the mode pins as shown in table 23.13, and provide a 6-MHz input-clock signal. In programmer mode, set the mode pins as shown in table 24.13, and provide a 6-MHz input-clock signal. This enables this LSI to operate at 48 MHz. 23.9.1 Pin Arrangement of Socket Adapter 24.9.1 Pin Arrangement of Socket Adapter Figure 23.24 Mapping of On-Chip Flash Memory Figure 24.24 Mapping of On-Chip Flash Memory 895 Figure amended On-chip ROM space (user MAT) On-chip ROM space (user MAT) On-chip ROM space (user MAT) 1 Mbyte On-chip ROM space (user MAT) 1 Mbyte Address in PROM mode Address in PROM mode H'0,0000 to H'F,FFFF H'00,0000 to H'0F,FFFF On-chip ROM space (user boot MAT) On-chip ROM space (user boot MAT) On-chip ROM space (user boot MAT) 8 kbytes On-chip ROM space (user boot MAT) 12 Kbytes Address in MCU mode Address in MCU mode H'0000,0000 to H'0000,1FFF H'0000,0000 to H'0000,2FFF Address in PROM mode Address in PROM mode H'0,0000 to H'0,1FFF H'0,0000 to H'0,2FFF Rev. 5.00 Feb. 24, 2010 Page lii of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 23.9.1 Pin Arrangement of Socket Adapter 24.9.1 Pin Arrangement of Socket Adapter Figure 23.25 Pin Arrangement of Socket Adapter Figure 24.25 Pin Arrangement of Socket Adapter 896 Figure amended SH7058F Socket Adapter (40-Pin Conversion) HN27C4096HG (40 pins) Pin Name Pin No. BP-272 and Note * added Pin No. Pin Name 7 A0 21 A0 8 A1 22 A1 BP-272 FP-256H Pin No. Pin Name 9 A2 23 A2 B3 7 A0 21 A0 10 A3 24 A3 D4 8 A1 22 A1 C4 9 A2 23 A2 A3 10 A3 24 A3 SH7058SF Pin No. Pin Name Socket Adapter (40-Pin Conversion) HN27C4096HG (40 pins) 12 A4 25 A4 14 A5 26 A5 B4 12 A4 25 A4 15 A6 27 A6 A4 14 A5 26 A5 16 A7 28 A7 C5 15 A6 27 A6 17 A8 29 A8 B5 16 A7 28 A7 A5 17 A8 29 18 A9 31 A9 D6 18 A9 31 A9 19 A10 32 A10 B6 19 A10 32 A10 A6 21 A11 33 A11 A8 21 A11 33 A11 C7 23 A12 34 A12 23 A12 34 A12 B7 24 A13 35 A13 24 A13 35 A13 A7 25 A14 36 A14 25 A14 36 A14 D8 26 A15 37 A15 C8 27 A16 38 B8 28 A17 39 A17 A16 26 A15 37 A15 27 A16 38 A16 A8 29 A18 10 A18*1 28 A17 39 A17 D9 31 A19 9 A19*1 29 A18 10 A18 31 A19 9 A19 63 D0 19 I/00 64 D1 18 I/01 C9 33 A20 8 A20*1 D15 63 D0 19 I/00 B18 64 D1 18 I/01 A19 65 D2 17 I/02 C18 66 D3 16 I/03 B19 67 D4 15 I/04 B20 68 D5 14 I/05 65 D2 17 I/02 66 D3 16 I/03 C17 69 D6 13 I/06 67 D4 15 I/04 C19 71 D7 12 I/07 I/05 P1 218 CE 2 CE K2 230 OE 20 OE 68 14 D5 D6 13 I/06 71 D7 12 I/07 D14 218 CE 2 CE 230 OE 20 OE 226 WE 3 WE 56 FWE 4 FWE 1,40 Vcc Vcc 11,30 Vss D5,C6,A10,C11,A12,C12,C13, D13,B14,C15,A16,C16,D16,F17, F18,K19,K20,T20,T19,U19,U16, V15,V9,U6,V5,U4,P3,J3,H4 A9,B13,B15,D7,B12,D11,C14,F19, G3,G17,E20,J4,J20,U20,J9 to 12, K9 to 12,L9 to 12,M1,M9 to 12,P4, T18,U5,U9,V6,V16,W11 C10 B16 58 5,6,7 NC A15 53 8 A20 A14 51 EXTAL 9 A19 A17 60 PLLVcc 61 PLLCAP 62 PLLVss 69 11,20,39,42,43,46,49,52,55,57, 59,70,75,83,100,101,119,120, 128,139,148,172,187,194,203, 212,237,247 13,22,32,41,44,47,50,54,72,77, 84,85,99,121,126,141,150,163, 174,185,196,205,214,227,239, 249 58 RES Power-on reset circuit 53 XTAL Oscillator circuit Vss 51 EXTAL 60 PLLVcc 61 PLLCAP 62 PLLVss PLL circuit 30,161,225 VCL Other NC (OPEN) Capacitor L3 B17 A18 <Legend> FWE I/07 to 0 A19 to 0 CE OE WE 226 WE 56 FWE 11,20,37,39,42,43,46,49,52,55, 57,59,70,75,83,100,101,119, 120,128,139,148,172,187,194, 203,212,237,247 13,22,32,41,44,47,50,54,72,77, 84,85,99,121,126,141,150,163, 174,185,196,205,214,227,239, 249 34 Vcc Vss A21 RES XTAL B9,Y11,M2 30,161,225 VCL Other Other NC (OPEN) Power-on reset circuit Oscillator circuit PLL circuit Capacitor 3 WE 4 FWE 1,40 Vcc 11,30 Vss 5,6,7 NC Legend: FWE : Flash-write enable I/07 to 0 : Data I/O A21 to 0 : Address input CE : Chip enable OE : Output enable WE : Write enable Note: *With using the HN27C4096HG as the base, unused I/O pins are adopted to make up for the shortage of address pins. : Flash-write enable : Data I/O : Address input : Chip enable : Output enable : Write enable 23.9.2 Programmer Mode Operation 24.9.2 Programmer Mode Operation Table 23.14 Settings for Each Operating Mode of Programmer Mode Table 23.14 Settings for Each Operating Mode of Programmer Mode 897 Table amended Pin Name Mode A19 to A0 Pin Name Mode A20 to A0 Rev. 5.00 Feb. 24, 2010 Page liii of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 23.10.1 Serial Communication Interface Specification for Boot Mode 24.10.1 Serial Communication Interface Specification for Boot Mode Programming Programming 917, 918 Description and figure amended (1) User boot MAT programming selection (1) User boot MAT programming selection (2) User MAT programming selection (2) User MAT programming selection (3) Two-user-MAT simultaneous programming selection . Figure 23.30 Programming Sequence Figure 24.30 Programming Sequence Programming selection (H'42, H'43, H'44) Programming selection (H'42, H'43 ) (3) Selection of Two-User-Boot MAT Simultaneous Programming (3) Selection of Two-User-Boot MAT Simultaneous Programming 919 Description deleted User Boot MAT Sum Check: User Boot MAT Checksum: 923, 924 Description amended User Boot MAT Sum Check: The boot program will add the amount of data in user boot MATs and return the result. User Boot MAT Checksum: The boot program will add the amount of data in user boot MATs and return the result. The user boot MAT checksum value is calculated as a 16-Kbyte area. The checksum value is the sum of 12 Kbytes of user boot MAT data and 4 Kbytes of H'FF data. Command H'4A Command: H'4A (one byte): Sum check of user boot MATs Response H'5A Size Command SUM MAT checksum H'4A Command: H'4A (one byte): Checksum of user boot MATs Response: H'5A (one byte): Response to sum check of user boot MATs Response Size (one byte): Number of characters in checksum data (fixed at 4) H'5A Size MAT checksum SUM Response: H'5A (one byte): Response to checksum of user boot MATs MAT checksum (four bytes): Checksum of user boot MATs Size (one byte): Number of characters in checksum data (fixed at 4) The total amount of data is obtained in byte units. MAT checksum (4 bytes): The user boot MAT checksum value calculated by adding byte units, with a further 4 SUM (one byte): Checksum (for transmit data) Kbytes of H'FF data added SUM (one byte): Checksum (for transmit data) 23.10.2 AC Characteristics and Timing in Programmer Mode 24.10.2 AC Characteristics and Timing in Programmer Mode Figure 23.32 Memory Read Timing after Command Write Figure 24.32 Memory Read Timing after Command Write Figure 23.33 Timing at Transition from Memory Read Mode to Other Modes Figure 24.33 Timing at Transition from Memory Read Mode to Other Modes Figure 23.34 CE/OE Enable State Read Figure 24.34 CE/OE Enable State Read Figure 23.35 CE/OE Clock Read Figure 24.35 CE/OE Clock Read Figure 23.36 Timing in Auto-Program Mode Figure 24.36 Timing in Auto-Program Mode Figure 23.37 Timing in Auto-Erase Mode Figure 24.37 Timing in Auto-Erase Mode Figure 23.38 Timing in Status Read Mode Figure 24.38 Timing in Status Read Mode 927 to 932 Figure amended A19-0 A21-0 Table 23.25 AC Characteristics in Auto-Program Mode Table 24.25 AC Characteristics in Auto-Program Mode 930 Table amended Code Symbol Min Max Unit Memory programming time twrite 1 3000 ms Note Code Symbol Min Max Unit Note Memory programming time twrite -- tP ms tP: Refer to section 29.5, Flash Memory Characteristics Table 23.26 AC Characteristics in Auto-Erase Mode Table 24.26 AC Characteristics in Auto-Erase Mode 931 Table amended Code Symbol Min Max Unit Memory erase time terase 100 40000 ms Rev. 5.00 Feb. 24, 2010 Page liv of xciv REJ09B0177-0500 Note Code Symbol Min Max Unit Note Memory erase time terase -- 8 x tE s tE: Refer to section 29.5, Flash Memory Characteristics Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 23.1 Features 25.1 Features 833, 834 Description amended This LSI has 1-Mbyte on-chip flash memory. The flash memory has the following features. This LSI has 1.5-Mbyte on-chip flash memory. The flash memory has the following features. * * * Two flash-memory MATs according to LSI initiation mode Two flash-memory MATs according to LSI initiation mode The user MAT is initiated at a power-on reset in user mode: 1 Mbyte The user MAT is initiated at a power-on reset in user mode: 1.5 Mbyte The user boot MAT is initiated at a power-on reset in user boot mode: 8 kbytes The user boot MAT is initiated at a power-on reset in user boot mode: 12 Kbytes Operating frequency at programming/erasing The operating frequency at programming/erasing is a maximum of 40 MHz. * Operating frequency at programming/erasing The operating frequency at programming/erasing is a maximum of 80 MHz. 23.2.1 Block Diagram 25.2.1 Block Diagram Figure 23.1 Block Diagram of Flash Memory Figure 25.1 Block Diagram of Flash Memory 835 Figure amended Memory MAT unit Memory MAT unit User MAT : 1 MBbyte User MAT : 1.5 MBbyte User boot MAT : 8 kbytes User boot MAT : 12 Kbytes 23.2.4 Flash Memory Configuration 25.2.4 Flash Memory Configuration Figure 23.3 Flash Memory Configuration Figure 25.3 Flash Memory Configuration 839 Description amended This LSI's flash memory is configured by the 1-Mbyte user MAT and 8-kbyte user boot MAT This LSI's flash memory is configured by the 1.5-Mbyte user MAT and 12-Kbyte user boot MAT The user MAT is divided into two 512-kbyte banks (bank 0 and bank 1). The user MAT is divided into three 512-Kbyte banks (bank 0, bank 1 and bank 2). Figure amended <User MAT> <User MAT> Bank 2 (512-Kbytes) added <User boot MAT> <User boot MAT> Address H'00,0000-H'00,1FFF 8 kbytes Address H'00,0000-H'00,2FFF 12 Kbytes The user MAT and user boot MAT have different memory sizes. Do not access a user boot MAT that is 8 kbytes or more. When a user boot MAT exceeding 8 kbytes is read from, an undefined value is read. Description amended 23.2.5 Block Division 25.2.5 Block Division Figure 23.4 Block Division of User MAT Figure 25.4 Block Division of User MAT 840 Description amended The user MAT is divided into 128 kbytes (seven blocks), 96 kbytes (one block), and 4 kbytes (eight blocks) as shown in figure 23.4. The user MAT is divided into 256 Kbytes (4 blocks), 128 Kbytes (three blocks), 96 Kbytes (one block), and 4 Kbytes (eight blocks) as shown in figure 25.4. The user MAT and user boot MAT have different memory sizes. Do not access a user boot MAT that is 12 Kbytes or more. When a user boot MAT exceeding 12 Kbytes is read from, an undefined value is read. Figure amended User MAT : Bank 1 amended User MAT : Bank 1 amended 128 kB x 4 (EB12, EB13, EB14, EB15) 256 Kbytes x 2 (EB12, EB13 ) User MAT : Bank 2 addded Rev. 5.00 Feb. 24, 2010 Page lv of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 23.4.1 Registers 25.4.1 Registers Table 23.4 (1) Register Configuration Table 25.4 (1) Register Configuration 844 Note amended 4. The registers except RAMER can be accessed only in bytes, and the access requires four cycles. Since RAMER is in the BSC, when it is accessed in bytes or words, the access requires four cycles, and when it is accessed in longwords, the access requires eight cycles. 4. The registers except RAMER can be accessed only in bytes, and the access requires four cycles. Since the RAMER register is in the BSC, when it is accessed in bytes , the access requires four cycles, and when it is accessed in longwords, the access requires eight cycles. 23.4.2 Programming/Erasing Interface Registers 25.4.2 Programming/Erasing Interface Registers 846, 847 Description amended The programming/erasing interface registers are as described below. They are all 8-bit registers that can be accessed in bytes. Except for the FLER bit in FCCS and FMATS, these registers are initialized at a power-on reset, in hardware standby mode, or in software standby mode. The FLER bit or FMATS is not initialized in software standby mode. The programming/erasing interface registers are as described below. They are all 8-bit registers that can be accessed in bytes. These registers are initialized at a power-on reset, in hardware standby mode, or in software standby mode. (1) Flash Code Control and Status Register (FCCS) (1) Flash Code Control and Status Register (FCCS) * * Bit 0--Source Program Copy Operation (SCO): Requests the on-chip programming/erasing program to be downloaded to the on-chip RAM. Bit 0--Source Program Copy Operation (SCO): Requests the on-chip programming/erasing program to be downloaded to the on-chip RAM. ... ... Four NOP instructions must be executed immediately after setting this bit to 1. Eight NOP instructions must be executed immediately after setting this bit to 1. (6) Flash Transfer Destination Address Register (FTDAR) (6) Flash Transfer Destination Address Register (FTDAR) 850, 851 Description amended FTDAR specifies the on-chip RAM address to which the on-chip program is downloaded. Make settings for FTDAR before writing 1 to the SCO bit in FCCS. The initial value is H'00 which points to the start address (H'FFFF0000) in on-chip RAM. FTDAR specifies the on-chip RAM address to which the on-chip program is downloaded. Make settings for FTDAR before writing 1 to the SCO bit in FCCS. The initial value is H'00 which points to the start address (H'FFFE8000) in on-chip RAM. Table amended * Bits 6 to 0--Transfer Destination Address (TDA6 to TDA0): These bits specify the download start address. * Bits 6 to 0--Transfer Destination Address (TDA6 to TDA0): These bits specify the download start address. Bits 6 to 0 Bits 6 to 0 TDA6 to TDA0 TDA6 to TDA0 Description H'00 Download start address is set to H'FFFF0000 H'01 Description H'00 Download start address is set to H'FFFE8000 H'01 Download start address is set to H'FFFE8800 Download start address is set to H'FFFF0800 H'02 Download start address is set to H'FFFE9000 H'02 Download start address is set to H'FFFF1000 H'03 Download start address is set to H'FFFE9800 H'03 Download start address is set to H'FFFF1800 H'04 Download start address is set to H'FFFEA000 H'05 Download start address is set to H'FFFEA800 H'04 Download start address is set to H'FFFF2000 H'05 Download start address is set to H'FFFF2800 (Initial value) (Initial value) 23.4.3 Programming/Erasing Interface Parameters 25.4.3 Programming/Erasing Interface Parameters 851 Description amended ... The initial value is undefined at a power-on reset or in hardware standby mode. ... The initial value is undefined at a power-on reset, in hardware standby mode, or in software standby mode. (1) Download Control (1) Download Control 852 Description amended ... The on-chip RAM area to be downloaded is the area as much as 2 kbytes starting from the start address specified by FTDAR. For the address map of the on-chip RAM, see figure 23.10. ... The on-chip RAM area to be downloaded is the area as much as 3 Kbytes starting from the start address specified by FTDAR. For the address map of the on-chip RAM, see figure 25.10. Rev. 5.00 Feb. 24, 2010 Page lvi of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 23.4.4 RAM Emulation Register (RAMER) 25.4.4 RAM Emulation Register (RAMER) Table 23.7 Overlapping of RAM Area and User MAT Area Table 25.7 Overlapping of RAM Area and User MAT Area 862, 863 Bit table amended ... RAMER is initialized to H'0000 at a power-on reset or in hardware standby mode and is not initialized in software standby mode. ... RAMER is initialized to H'0000 at a power-on reset or in hardware standby mode, or in software standby mode. Bit : Bit : Initial value : R/W : 7 2 1 0 RAM2 RAM1 RAM0 0 0 0 0 R R/W R/W R/W 7 2 1 0 RAM0 Initial value : R/W : 0 0 0 0 R R R R/W Table replaced 23.5.1 Boot Mode 25.5.1 Boot Mode 864 Description added ...After the SCI bit rate is automatically adjusted, the communication with the host is executed by means of the control command method. ...After the SCI bit rate is automatically adjusted, the communication with the host is executed by means of the control command method. The RAM areas used by boot mode are 3 Kbytes starting at address H'FFFE8000, 4 Kbytes starting at address H'FFFFB000, and 128 bytes from H'FFFFBF80 to H'FFFFBFFF, which are used as the stack. (1) SCI Interface Setting by Host (1) SCI Interface Setting by Host Table 23.8 System Clock Frequency that Can Automatically Adjust Bit Rate of This LSI Table 25.8 System Clock Frequency that Can Automatically Adjust Bit Rate of This LSI 865 Table amended Host Bit Rate System Clock Frequency Which Can Automatically Adjust LSI's Bit Rate Host Bit Rate System Clock Frequency Which Can Automatically Adjust LSI's Bit Rate 9,600 bps 20 to 40 MHz (input frequency of 5 to 10 MHz) 9,600 bps 40 to 80 MHz (input frequency of 5 to 10 MHz) 19,200 bps 20 to 40 MHz (input frequency of 5 to 10 MHz) 19,200 bps 40 to 80 MHz (input frequency of 5 to 10 MHz) 23.5.2 User Program Mode 25.5.2 User Program Mode (1) On-Chip RAM Address Map when Programming/Erasing is Executed (1) On-Chip RAM Address Map when Programming/Erasing is Executed Figure 23.10 RAM Map after Download Figure 25.10 RAM Map after Download 869 Figure amended Area to be downloaded (Size: 2 kbytes) Area to be downloaded (Size: 3 kbytes) Address Address RAMTOP (H'FFFF0000) RAMTOP (H'FFFE8000) FTDAR setting+2048 FTDAR setting+3072 (2.3) VBR is cleared to 0 and 1 is written to the SCO bit of FCCS, and then download is executed. (2.3) VBR is cleared to 0 and 1 is written to the SCO bit of FCCS, and then download is executed. 871 Description amended ... Four NOP instructions are executed immediately after the instructions that set the SCO bit to 1. ... Eight NOP instructions are executed immediately after the instructions that set the SCO bit to 1. Rev. 5.00 Feb. 24, 2010 Page lvii of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 23.5.2 User Program Mode 25.5.2 User Program Mode (4) Erasing and Programming Procedure in User Program Mode (4) Erasing and Programming Procedure in User Program Mode Figure 23.13 Sample Procedure of Repeating RAM Emulation, Erasing, and Programming (Overview) Figure 25.13 Sample Procedure of Repeating RAM Emulation, Erasing, and Programming (Overview) 877 Figure amended Set FTDAR to H'02 Set FTDAR to H'02 (Specify H'FFFF1000 as download destination) (Specify H'FFFE9000 as download destination) Set FTDAR to H'03 Set FTDAR to H'04 (Specify H'FFFF1800 as download destination) (Specify H'FFFEA000 as download destination) Set FMPDR to H'FFFF0000 to program relevant block (execute programming program) Set FMPDR to H'FFFE8000 to program relevant block (execute programming program) In the above example, the erasing program and programming program are downloaded to areas excluding the 4 kbytes (H'FFFF0000 to H'FFFF0FFF) from the start of on-chip ROM. In the above example, the erasing program and programming program are downloaded to areas excluding the 4 Kbytes (H'FFFE8000 to H'FFFE8FFF) from the start of on-chip ROM. Description amended * Be sure to initialize both the erasing program and programming program. Initialization by setting the FPEFEQ and FUBRA parameters must be performed for both the erasing program and the programming program. Initialization must be executed for both entry addresses: (download start address for erasing program) + 32 bytes (H'FFFF1020 in this example) and (download start address for programming program) + 32 bytes (H'FFFF1820 in this example). * 23.5.3 User Boot Mode 25.5.3 User Boot Mode (1) User Boot Mode Initiation (1) User Boot Mode Initiation 878 Description amended The RAM area about 1.2 kbytes from H'FFFF0800 and 4 bytes from H'FFFFBFFC (a stack area) is used by the routine. ... Neither can the AUD be used in this period. This period is 100 s while operating at an internal frequency of 40 MHz. The RAM area about 3 Kbytes from H'FFFFB000 and 128 bytes from H'FFFFBF80 to H'FFFFBFFF (a stack area) is used by the routine. ... Neither can the AUD be used in this period. This period is approximately 100 s while operating at an internal frequency of 80 MHz. 23.6.1 Hardware Protection 25.6.1 Hardware Protection 881 Description amended Programming and erasing of flash memory is forcibly disabled or suspended by hardware protection. In this state, the downloading of an on-chip program and initialization of the flash memory are possible. Programming and erasing of flash memory is forcibly disabled or suspended by hardware protection. In this state by the FWE pin, the downloading of an on-chip program and initialization of the flash memory are possible. Rev. 5.00 Feb. 24, 2010 Page lviii of xciv REJ09B0177-0500 Be sure to initialize both the erasing program and programming program. Initialization by setting the FPEFEQ and FUBRA parameters must be performed for both the erasing program and the programming program. Initialization must be executed for both entry addresses: (download start address for erasing program) + 32 bytes (H'FFFE9020 in this example) and (download start address for programming program) + 32 bytes (H'FFFEA020 in this example). Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 23.6.3 Error Protection 25.6.3 Error Protection Figure 23.16 Transitions to and from Error Protection State Figure 25.16 Transitions to and from Error Protection State 883, 884 Description amended * * Flash memory is read during programming/erasing (including a vector read or an instruction fetch) * When a SLEEP instruction programming/erasing When the relevant bank area of flash memory is read during programming/erasing (including a vector read or an instruction fetch) * When a SLEEP instruction (including software standby mode) is executed during programming/erasing Error protection is cancelled (FLER bit is cleared) only by a power-on reset or in hardware standby mode. Note that the reset signal should only be released after providing a reset input over a period longer than the normal 100 s. is executed during Error protection is cancelled (FLER bit is cleared) by a power-on reset, in software standby mode, or in hardware standby mode. Note that the reset signal should only be released after providing a reset input over a period longer than the normal 100 s. Figure amended Program mode Erase mode Read disabled Programming/erasing enabled FLER=0 Reset or standby (Hardware protection) Program mode Erase mode Read enabled Programming/erasing disabled FLER=0 Read disabled Programming/erasing enabled FLER=0 RES = 0 or HSTBY = 0 Er Error occurred Error protection mode Read enabled Programming/erasing disabled FLER=1 ror r 0o oc = 0 cu ES Y= oft rred R TB wa HS RES=0 or re sta HSTBY=0 nd by ) (S Software standby mode Programming/erasing interface register is in its initial state. Er Error occurred Error protection mode (Software standby) Error protection mode Read enabled Programming/erasing disabled FLER=1 Read disabled Cancel Programming/erasing disabled software standby mode FLER=1 Reset or standby (Hardware protection) RES = 0 or HSTBY = 0 Programming/erasing interface register is in its initial state. ror r 0o Read enabled Programming/erasing disabled FLER=0 oc = 0 cu ES Y= Programming/erasing interface oft rred R TB register is in its initial state. wa HS RES=0 , re sta HSTBY=0 nd by or software standby mode cancellation ) (S Software standby mode (Software standby) Read disabled Programming/erasing disabled FLER=undefined The power is not supplied in this LSI. 23.7 Flash Memory Emulation in RAM 25.7 Flash Memory Emulation in RAM Figure 23.18 Example of Overlapped RAM Operation Figure 25.18 Example of Overlapped RAM Operation 886 Address amended EB0 to EB15 EB0 to EB15 H'00000 H'000000 H'01000 H'001000 H'02000 H'002000 H'03000 H'003000 H'04000 H'004000 H'05000 H'005000 H'06000 H'006000 H'07000 H'007000 H'08000 H'008000 ... ... H'FFFFF H'17FFFF On-chip RAM On-chip RAM H'FFFF0000 H'FFFE8000 H'FFFF0FFF H'FFFEBFFF ... ... H'FFFFBFFF H'FFFFBFFF Rev. 5.00 Feb. 24, 2010 Page lix of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 23.7 Flash Memory Emulation in RAM 25.7 Flash Memory Emulation in RAM 886 Description amended Figure 23.18 shows an example of an overlap on block area EB0 of the flash memory. Figure 25.18 shows an example of an overlap on block area EB0 to EB3 of the flash memory. Emulation is possible for a single area selected from among the eight areas, from EB0 to EB7, of the user MAT. The area is selected by the setting of the RAM2 to RAM0 bits in RAMER. Emulation is possible for four areas selected from among the eight areas, from EB0 to EB7, of the user MAT. The area is selected by the setting of the RAM0 bit in RAMER. (1) To overlap a part of the RAM on area EB0, to allow realtime programming of the data for this area, set the RAMS bit in RAMER to 1, and each of the RAM2 to RAM0 bits to 0. (2) Realtime programming is carried out using the overlaid area of RAM. In programming or erasing the user MAT, it is necessary to run a program that implements a series of procedural steps, including the downloading of an on-chip program. In this process, set the download area with FTDAR so that the overlaid RAM area and the area where the on-chip program is to be downloaded do not overlap. The initial setting (H'00) of FTDAR causes the tuned data area to overlap with the download area. When using the initial setting of FTDAR, the data that is to be programmed must be saved beforehand in an area that is not used by the system. Figure 23.19 shows an example of programming data that has been emulated to the EB0 area in the user MAT. (1) To overlap a part of the RAM on area EB0 to EB3, to allow realtime programming of the data for this area, set the RAMS bit in RAMER to 1, and each of the RAM0 bit to 0. (2) Realtime programming is carried out using the overlaid area of RAM. In programming or erasing the user MAT, it is necessary to run a program that implements a series of procedural steps, including the downloading of an on-chip program. In this state, note that the RAM area overlaps with the area where the on-chip program is downloaded. Prevent destruction of the data once it has been safely written to RAM by following either of the procedures below. (1) Once the tuning data has been safely written to the four areas used to emulate flash memory, secure the data in an unused area. (2) Write the tuning data to one of the four areas used to emulate flash memory. In this case, use the FTDAR register to select an area for downloading that does not overlap with the area to be tuned. Figure 25.19 shows an example in which the EB0 area is selected for tuning from among the four areas used for emulation, and the data, once safely written to RAM, is then written to the EB0 area in the user MAT. Rev. 5.00 Feb. 24, 2010 Page lx of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 23.7 Flash Memory Emulation in RAM 25.7 Flash Memory Emulation in RAM Figure 23.19 Programming of Tuned Data Figure 25.19 Programming of Tuned Data 887 Address amended EB0 to EB15 EB0 to EB15 H'00000 H'000000 H'01000 H'001000 H'02000 H'002000 H'03000 H'003000 H'04000 H'004000 H'05000 H'005000 H'06000 H'006000 H'07000 H'007000 H'08000 H'008000 ... ... H'FFFFF H'17FFFF <On-chip RAM> <On-chip RAM> H'FFFF0000 H'FFFE8000 H'FFFF0FFF H'FFFE8FFF FTDAR setting FTDAR setting ... ... H'FFFEBFFF ... H'FFFFBFFF H'FFFFBFFF <On-chip RAM> H'FFFEBFFFEB4 887 Note amended Note: Setting the RAMS bit to 1 puts all the blocks in flash memory in the programming/erasing-protected state regardless of the values of the RAM2 to RAM0 bits (emulation protection). Clear the RAMS bit to 0 before actual programming or erasure. Note: Setting the RAMS bit to 1 puts all the blocks in flash memory in the programming/erasing-protected state regardless of the values of the RAM0 bit (emulation protection). Clear the RAMS bit to 0 before actual programming or erasure. 23.8.1 Switching between User MAT and User Boot MAT 25.8.1 Switching between User MAT and User Boot MAT 888 Description amended (2) To ensure that the MAT that has been switched to is accessible, execute four NOP instructions in on-chip RAM immediately after writing to FMATS of on-chip RAM (this prevents access to the flash memory during MAT switching). (2) To ensure that the MAT that has been switched to is accessible, execute eight NOP instructions in on-chip RAM immediately after writing to FMATS of on-chip RAM (this prevents access to the flash memory during MAT switching). (5) Memory sizes of the user MAT and user boot MAT are different. When accessing the user boot MAT, do not access addresses exceeding the 8-kbyte memory space. If access goes beyond the 8-kbyte space, the values read are undefined. (5) Memory sizes of the user MAT and user boot MAT are different. When accessing the user boot MAT, do not access addresses exceeding the 12-Kbyte memory space. If access goes beyond the 12-Kbyte space, the values read are undefined. Rev. 5.00 Feb. 24, 2010 Page lxi of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 23.8.1 Switching between User MAT and User Boot MAT 25.8.1 Switching between User MAT and User Boot MAT Figure 23.20 Switching between User MAT and User Boot MAT Figure 25.20 Switching between User MAT and User Boot MAT 889 Figure amended Procedure for switching to the user boot MAT Procedure for switching to the user boot MAT (3) Execute four NOP instructions before accessing the user boot MAT. (3) Execute eight NOP instructions before accessing the user boot MAT. Procedure for switching to the user MAT Procedure for switching to the user MAT (3) Execute four NOP instructions before accessing the user MAT. (3) Execute eight NOP instructions before accessing the user MAT. 23.8.2 Interrupts during Programming/Erasing 25.8.2 Interrupts during Programming/Erasing (2) Interrupts during programming/erasing (2) Interrupts during programming/erasing 892, 893 Description amended 1. When flash memory is being programmed or erased, both the user MAT and user boot MAT cannot be accessed. Prepare the interrupt vector table and interrupt processing routine in on-chip RAM or external memory. Make sure the flash memory being programmed or erased is not accessed by the interrupt processing routine. If flash memory is read, the read values are not guaranteed. If the relevant bank in flash memory that is being programmed or erased is accessed, the error protection state is entered, and programming or erasing is aborted. If a bank other than the relevant bank is accessed, the error protection state is not entered but the read values are not guaranteed. 1. When flash memory is being programmed or erased, both the user MAT and user boot MAT cannot be accessed. Prepare the interrupt vector table and interrupt processing routine in on-chip RAM or external memory. Make sure the flash memory being programmed or erased is not accessed by the interrupt processing routine. If flash memory is read, the read values are not guaranteed. If . flash memory that is being programmed or erased is accessed, the error protect state is entered, and programming or erasing is aborted. . 5. When a transition is made to sleep mode or software standby mode in the interrupt processing routine, the error protection state is entered and programming/erasing is aborted. If a transition is made to the reset state, the reset signal should only be released after providing a reset input over a period longer than the normal 100 s to reduce the damage to flash memory. Rev. 5.00 Feb. 24, 2010 Page lxii of xciv REJ09B0177-0500 5. When a transition is made to sleep mode in the interrupt processing routine, the error protection state is entered and programming/erasing is aborted. If a transition is made to the reset state, the reset signal should only be released after providing a reset input over a period longer than the normal 100 s to reduce the damage to flash memory. Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 23.8.3 Other Notes 25.8.3 Other Notes 893, 894 Description amended 1. Download time of on-chip program 1. Download time of on-chip program The programming program that includes the initialization routine and the erasing program that includes the initialization routine are each 2 kbytes or less. Accordingly, when the CPU clock frequency is 40 MHz, the download for each program takes approximately 75 s at maximum. The programming program that includes the initialization routine and the erasing program that includes the initialization routine are each 3 Kbytes or less. Accordingly, when the CPU clock frequency is 80 MHz, the download for each program takes approximately 300 s at maximum. 2. User branch processing intervals 2. User branch processing intervals The intervals for executing the user branch processing differs in programming and erasing. The processing phase also differs. Table 23.11 lists the maximum and minimum intervals for initiating the user branch processing when the CPU clock frequency is 40 MHz. The intervals for executing the user branch processing differs in programming and erasing. The processing phase also differs. Table 25.11 lists the minimum and maximum user branch processing intervals when the CPU clock frequency is 80 MHz. Table 23.11 Initiation Intervals of User Branch Processing Table 25.11 User Branch Processing Intervals Table and title amended Processing Name Maximum Interval Minimum Interval Programming Approximately 1 ms Approximately 17 s Erasing Approximately 5 ms Approximately 17 s Processing Name Maximum Interval Minimum Interval Programming Approximately 1 ms Approximately 19 s Erasing Approximately 5 ms Approximately 19 s However, when operation is done with CPU clock of 40 MHz, maximum and minimum values of the time until initial user branch processing are as shown in table 23.12. However, when operation is done with CPU clock of 80 MHz, maximum and minimum values of the time until initial user branch processing are as shown in table 25.12. Table 23.12 Initial User Branch Processing Time Table 25.12 Intervals Until Start of User Branch Processing . Table and title amended Processing Name Max. Min. Processing Name Max. Min. Programming Approximately 113 s Approximately 113 s Programming Approximately 500 s Approximately 500 s Erasing Approximately 85 s Approximately 45 s Erasing Approximately 2300 s Approximately 1000 s 4. State in which AUD operation is disabled and interrupts are ignored Checking the flash-memory related registers immediately after user boot mode is initiated (Approximately 100 s if operation is done at an internal frequency of 40 MHz after the reset signal is released) 4. State in which AUD operation is disabled and interrupts are ignored Description amended Checking the flash-memory related registers immediately after user boot mode is initiated (Approximately 100 s if operation is done at an internal frequency of 80 MHz after the reset signal is released) 7. FWE pin state added 23.9 Programmer Mode 25.9 Programmer Mode 894 Description amended In programmer mode, set the mode pins as shown in table 23.13, and provide a 6-MHz input-clock signal. In programmer mode, set the mode pins as shown in table 25.13, and provide a 6-MHz input-clock signal. This enables this LSI to operate at 48 MHz. Rev. 5.00 Feb. 24, 2010 Page lxiii of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 23.9.1 Pin Arrangement of Socket Adapter 25.9.1 Pin Arrangement of Socket Adapter Figure 23.24 Mapping of On-Chip Flash Memory Figure 25.24 Mapping of On-Chip Flash Memory 895 Figure amended On-chip ROM space(user MAT) 1 Mbyte On-chip ROM space(user MAT) 1.5 Mbyte Address in MCU mode Address in MCU mode H'0000,0000 to H'000F,FFFF H'0000,0000 to H'0017,FFFF Address in PROM mode Address in PROM mode H'0,0000 to H'F,FFFF H'00,0000 to H'17,FFFF On-chip ROM space (user boot MAT) 8 kbytes On-chip ROM space (user boot MAT) 12 Kbytes Address in MCU mode Address in MCU mode H'0000,0000 to H'0000,1FFF H'0000,0000 to H'0000,2FFF Address in PROM mode Address in PROM mode H'0,0000 to H'0,1FFF H'0,0000 to H'0,2FFF Figure 23.25 Pin Arrangement of Socket Adapter Figure 25.25 Pin Arrangement of Socket Adapter 896 Figure amended SH7058F Socket Adapter (40-Pin Conversion) HN27C4096HG (40 pins) Pin Name Pin No. Pin No. Pin Name 7 A0 21 A0 8 A1 22 A1 9 A2 23 10 A3 24 BP-272 and Note* added SH7058SF Pin No. Pin Name Socket Adapter (40-Pin Conversion) HN27C4096HG (40 pins) BP-272 FP-256H Pin No. Pin Name A2 B3 7 A0 21 A0 A3 D4 8 A1 22 A1 C4 9 A2 23 A2 A3 10 A3 24 A3 12 A4 25 A4 14 A5 26 A5 B4 12 A4 25 A4 15 A6 27 A6 A4 14 A5 26 A5 C5 15 A6 27 A6 B5 16 A7 28 A7 16 A7 28 A7 17 A8 29 A8 A5 17 A8 29 18 A9 31 A9 D6 18 A9 31 A9 19 A10 32 A10 B6 19 A10 32 A10 A6 21 A11 33 A11 A8 21 A11 33 A11 C7 23 A12 34 A12 23 A12 34 A12 B7 24 A13 35 A13 24 A13 35 A13 A7 25 A14 36 A14 D8 26 A15 37 A15 C8 27 A16 38 25 A14 36 A14 26 A15 37 A15 B8 28 A17 39 A17 27 A16 38 A16 A8 29 A18 10 A18* 28 A17 39 A17 D9 31 A19 9 A19* 29 A18 10 A18 31 A19 9 A19 63 D0 19 64 D1 18 A16 C9 33 A20 8 A20* D15 63 D0 19 I/00 B18 64 D1 18 I/01 I/00 A19 65 D2 17 I/02 I/01 C18 66 D3 16 I/03 B19 67 D4 15 I/04 65 D2 17 I/02 B20 68 D5 14 I/05 66 D3 16 I/03 C17 69 D6 13 I/06 67 D4 15 I/04 C19 71 D7 12 I/07 P1 218 CE 2 K2 230 OE 20 OE L3 226 WE 3 WE 56 FWE 4 FWE 1,40 Vcc Vcc 11,30 Vss 68 D5 14 I/05 69 D6 13 I/06 71 D7 12 I/07 D14 218 CE 2 CE D5,C6,A10,C11,A12,C12,C13, D13,B14,C15,A16,C16,D16,F17, F18,K19,K20,T20,T19,U19,U16, V15,V9,U6,V5,U4,P3,J3,H4 A9,B13,B15,D7,B12,D11,C14,F19, G3,G17,E20,J4,J20,U20,J9 to 12, K9 to 12,L9 to 12,M1,M9 to 12,P4, T18,U5,U9,V6,V16,W11 C10 230 OE 20 OE 226 WE 3 WE 56 FWE 4 FWE 1,40 Vcc 11,20,39,42,43,46,49,52,55,57, 59,70,75,83,100,101,119,120, 128,139,148,172,187,194,203, 212,237,247 13,22,32,41,44,47,50,54,72,77, 84,85,99,121,126,141,150,163, 174,185,196,205,214,227,239, 249 58 RES Power-on reset circuit 53 XTAL Oscillator circuit Vcc Vss 51 EXTAL 60 PLLVcc 61 PLLCAP 62 PLLVss 30,161,225 VCL Other NC (OPEN) PLL circuit Capacitor Rev. 5.00 Feb. 24, 2010 Page lxiv of xciv REJ09B0177-0500 11,20,37,39,42,43,46,49,52,55, 57,59,70,75,83,100,101,119, 120,128,139,148,172,187,194, 203,212,237,247 13,22,32,41,44,47,50,54,72,77, 84,85,99,121,126,141,150,163, 174,185,196,205,214,227,239, 249 34 Vss A21 11,30 Vss B16 58 5,6,7 NC A15 53 RES XTAL 8 A20 A14 51 EXTAL 9 A19 A17 60 PLLVcc 61 PLLCAP 62 PLLVss B17 A18 <Legend> FWE I/07 to 0 A19 to 0 CE OE WE : Flash-write enable : Data I/O : Address input : Chip enable : Output enable : Write enable B9,Y11,M2 30,161,225 VCL Other Other NC (OPEN) Power-on reset circuit Oscillator circuit PLL circuit Capacitor CE 5,6,7 NC Legend: : Flash-write enable FWE I/07 to 0 : Data I/O A21 to 0 : Address input : Chip enable CE : Output enable OE : Write enable WE Note: *With using the HN27C4096HG as the base, unused I/O pins are adopted to make up for the shortage of address pins. Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 23.9.2 Programmer Mode Operation 25.9.2 Programmer Mode Operation Table 23.14 Settings for Each Operating Mode of Programmer Mode Table 25.14 Settings for Each Operating Mode of Programmer Mode 897 Table amended Pin Name Mode Pin Name Mode A19 to A0 A20 to A0 23.10.1 Serial Communication Interface Specification for Boot Mode 25.10.1 Serial Communication Interface Specification for Boot Mode Programming Programming 917, 918 Description and figure amended (1) User boot MAT programming selection (1) User boot MAT programming selection (2) User MAT programming selection (2) User MAT programming selection (3) Two-user-MAT simultaneous programming selection . Figure 23.30 Programming Sequence Figure 25.30 Programming Sequence Programming selection (H'42, H'43, H'44) Programming selection (H'42, H'43 ) (3) Selection of Two-User-Boot MAT Simultaneous Programming (3) Selection of Two-User-Boot MAT Simultaneous Programming 919 Description deleted User Boot MAT Sum Check: User Boot MAT Checksum: 923, 924 Description amended User Boot MAT Sum Check: The boot program will add the amount of data in user boot MATs and return the result. User Boot MAT Checksum: The boot program will add the amount of data in user boot MATs and return the result. The user boot MAT checksum value is calculated as a 16-Kbyte area. The checksum value is the sum of 12 Kbytes of user boot MAT data and 4 Kbytes of H'FF data. Command H'4A Command: H'4A (one byte): Sum check of user boot MATs Response H'5A Size MAT checksum Command SUM Response: H'5A (one byte): Response to sum check of user boot MATs Size (one byte): Number of characters in checksum data (fixed at 4) MAT checksum (four bytes): Checksum of user boot MATs H'4A Command: H'4A (one byte): Checksum of user boot MATs Response H'5A Size MAT checksum SUM Response: H'5A (one byte): Response to checksum of user boot MATs Size (one byte): Number of characters in checksum data (fixed at 4) The total amount of data is obtained in byte units. MAT checksum (4 bytes): The user boot MAT checksum value calculated by adding byte units, with a further 4 SUM (one byte): Checksum (for transmit data) Kbytes of H'FF data added SUM (one byte): Checksum (for transmit data) User MAT Sum Check: User MAT Checksum: 924 Description amended User MAT Sum Check: The boot program will add the amount of data in user MATs and return the result. Command H'4B Command: H'4B (one byte): Sum check of user MATs Response H'5B Size MAT checksum User MAT Checksum: The boot program will add the amount of data in user MATs and return the result. The user MAT checksum value is calculated as a 2-Mbyte area. The checksum value is the sum of 1.5 Mbytes of user MAT data and 512 Kbytes of H'FF data. Command SUM Response: H'5B (one byte): Response to sum check of user MATs Size (one byte): Number of characters in checksum data (fixed at 4) MAT checksum (four bytes): Checksum of user MATs The total amount of data is obtained in byte units. SUM (one byte): Checksum (for transmit data) H'4B Command: H'4B (one byte): Checksum of user MATs Response H'5B Size MAT checksum SUM Response: H'5B (one byte): Response to checksum of user MATs Size (one byte): Number of characters in checksum data (fixed at 4) MAT checksum (4 bytes): The user MAT checksum value calculated by adding byte units, with a further 512 Kbytes of H'FF data added SUM (one byte): Checksum (for transmit data) 23.10.2 AC Characteristics and Timing in Programmer Mode 25.10.2 AC Characteristics and Timing in Programmer Mode Figure 23.32 Memory Read Timing after Command Write Figure 25.32 Memory Read Timing after Command Write Figure 23.33 Timing at Transition from Memory Read Mode to Other Modes Figure 25.33 Timing at Transition from Memory Read Mode to Other Modes Figure 23.34 CE/OE Enable State Read Figure 25.34 CE/OE Enable State Read Figure 23.35 CE/OE Clock Read Figure 25.35 CE/OE Clock Read Figure 23.36 Timing in Auto-Program Mode Figure 25.36 Timing in Auto-Program Mode Figure 23.37 Timing in Auto-Erase Mode Figure 25.37 Timing in Auto-Erase Mode Figure 23.38 Timing in Status Read Mode Figure 25.38 Timing in Status Read Mode 927 to 932 Figure amended A19-0 A21-0 Rev. 5.00 Feb. 24, 2010 Page lxv of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 23.10.2 AC Characteristics and Timing in Programmer Mode 25.10.2 AC Characteristics and Timing in Programmer Mode Table 23.25 AC Characteristics in Auto-Program Mode Table 25.25 AC Characteristics in Auto-Program Mode 930 Table amended Code Symbol Min Max Unit Memory programming time twrite 1 3000 ms Note Code Symbol Min Max Unit Note Memory programming time twrite -- tP ms tP: Refer to section 29.5, Flash Memory Characteristics Table 23.26 AC Characteristics in Auto-Erase Mode Table 25.26 AC Characteristics in Auto-Erase Mode 931 Table amended Code Symbol Min Max Unit Memory erase time terase 100 40000 ms Note Code Symbol Min Max Unit Note Memory erase time terase -- 6 x tE s tE: Refer to section 29.5, Flash Memory Characteristics 24.1 Overview 26.1 Overview 941 Description amended The SH7058 has 48 kbytes of on-chip RAM. The on-chip RAM is linked to the CPU, direct memory access controller (DMAC), and advanced user debugger (AUD) with a 32-bit data bus (figure 24.1). The SH7058S and SH7059 have 48 and 80 Kbytes of on-chip RAM, respectively. The on-chip RAM is linked to the CPU, direct memory access controller (DMAC), and advanced user debugger (AUD) with a 32-bit data bus (figure 26.1). The on-chip RAM is allocated to addresses H'FFFF0000 to H'FFFFBFFF. The on-chip RAM is allocated to addresses H'FFFF0000 to H'FFFFBFFF in the SH7058S and H'FFFE8000 to H'FFFF BFFF in the SH7059 Figure 24.1 Block Diagram of RAM Figure 26.1 Block Diagram of RAM SH7059 added H'FFFF0000 H'FFFF0001 H'FFFF0002 H'FFFF0003 H'FFFE8000 H'FFFE8001 H'FFFE8002 H'FFFE8003 H'FFFF0004 H'FFFF0005 H'FFFF0006 H'FFFF0007 H'FFFE8004 H'FFFE8005 H'FFFE8006 H'FFFE8007 H'FFFFBFFC H'FFFFBFFD H'FFFFBFFE H'FFFFBFFF H'FFFFBFFC H'FFFFBFFD H'FFFFBFFE H'FFFFBFFF 24.2 Operation 26.2 Operation 942 Description amended When the RAME bit in SYSCR is set to 1, the on-chip RAM is enabled. Accesses to addresses H'FFFF0000-H'FFFFBFFF are then directed to the on-chip RAM. When the RAME bit in SYSCR is set to 1, the on-chip RAM is enabled. Accesses H'FFFF0000-H'FFFFBFFF in the SH7058S or H'FFFE8000 to H'FFFFBFFF in the SH7059 then provide access to the on-chip RAM. 25.1.1 Power-Down States 27.1.1 Power-Down States 943 Description amended 1. Hardware standby mode 1. Hardware standby mode A transition to hardware standby mode is made according to the input level of the RES and HSTBY pins. A transition to hardware standby mode is made according to the input level of the RES and HSTBY pins. In hardware standby mode, all SH7058 functions are halted. In hardware standby mode, all this LSI functions are halted and the power supply to most circuits of this LSI is stopped. This state is exited by means of a power-on reset. This state is exited by means of a power-on reset. 2. Software standby mode 2. Software standby mode A transition to software standby mode is made by means of software (a CPU instruction). A transition to software standby mode is made by means of software (a CPU instruction). In software standby mode, all SH7058 functions are halted. In software standby mode, all this LSI functions are halted and the power supply to most circuits of this LSI is stopped. This state is exited by means of a power-on reset or an NMI interrupt. This state is canceld by a power-on reset or a rising edge of the NMI signal. Rev. 5.00 Feb. 24, 2010 Page lxvi of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 25.1.1 Power-Down States 27.1.1 Power-Down States Table 25.1 Power-Down State Conditions Table 27.1 Power-Down State Conditions 944 Description of CPU Registers deleded and table amended State State Mode Entering Procedure Hardware Low-level standby input at HSTBY pin Software standby Sleep Clock CPU On-Chip Peripheral CPU Registers Modules RAM Halted Halted Undefined Halted Execute Halted Halted Held SLEEP instruction with SSBY bit set to 1 in SBYCR Halted*1 Execute Runs SLEEP instruction with SSBY bit cleared to 0 in SBYCR Runs Halted Held Pins Canceling Procedure Held*2 Initialized High-level input at HSTBY pin, executing power-on reset Held Held Held or high impedance*3 Held Mode Entering Procedure CPU On-Chip Peripheral Modules Hardware standby Low-level input at HSTBY Halted pin (Power supply stopped) Halted Halted (Power supply stopped) (Power supply stopped) Software standby Execute SLEEP instruction Halted with SSBY (Power bit set to 1 in SBYCR supply Halted Halted*1 (Power supply stopped) (Power supply stopped) NMI interrupt Power-on reset Clock stopped) Sleep Execute SLEEP instruction Runs with SSBY bit cleared to 0 in SBYCR Halted and Runs held in registers Interrupt RAM Pins Held*1 Initialized Held High impedance*2 Canceling Procedure High-level input at HSTBY pin, executing power-on reset Rising edge of NMI Power-on reset Runs Runs Interrupt DMA address error Power-on reset DMA address error Manual reset Power-on reset Manual reset Note *1 deleted and notes amended Notes: Notes: 1. Some bits within on-chip peripheral module registers are initialized in software standby mode, and some are not. Refer to the register descriptions for each peripheral module. 1. Clear the RAME bit in SYSCR1 to 0 in advance when changing the state from the program execution state in hardware standby mode. 2. Clear the RAME bit in SYSCR1 to 0 in advance when changing the state from the program execution state in hardware standby mode. 2. When leaving software standby mode, the inside of this LSI is initiated in the reset state. The pin function controller and I/O port-related registers are initialized. For details on the pin state, see Appendix B, Pin States. 3. The state of the I/O ports in standby mode is set by the port high impedance bit (HIZ) in SBYCR. See section 25.2.1, Standby Control Register (SBYCR). 25.1.2 Pin Configuration 27.1.2 Pin Configuration Table 25.2 Pin Configuration Table 27.2 Pin Configuration 945 Table amended Description of NMI input pin added 25.1.3 Related Registers 27.1.3 Related Registers Table 25.3 Related Registers Table 27.3 Related Registers 945 Table amended Abbreviation*1 Abbreviation . Notes: 1. Register access with an internal clock multiplication ratio of 4 requires four internal clock () cycles for SBYCR, and four or five internal clock () cycles for SYSCR1 and SYSCR2. Note*1 deleted Rev. 5.00 Feb. 24, 2010 Page lxvii of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 25.2.1 Standby Control Register (SBYCR) 27.2.1 Standby Control Register (SBYCR) 945, 946 Description amended The standby control register (SBYCR) is an 8-bit readable/writable register that sets the transition to standby mode, and the port state in standby mode. SBYCR is initialized to H'1F by a power-on reset. The standby control register (SBYCR) is an 8-bit readable/writable register that sets the transition to standby mode . SBYCR is initialized to H'1F by a power-on reset, and set to H'3F in software standby mode. Bit: 7 6 5 0 SSBY HIZ -- -- 0 0 0 1 Initial value: R/W R/W R R R/W: Initial value: R/W: Bit: 7 6 5 0 SSBY -- SSBYF -- 0 0 0 1 R/W R R R Bit 6: Port High Impedance (HIZ) Bits 6 and 5: Description amended Bit 5: Reserved Bit 6: Reserved Bit 5: Software Standby Flag (SSBYF) 25.2.2 System Control Register 1 (SYSCR1) 27.2.2 System Control Register 1 (SYSCR1) 946, 947 Bit table amended Bit: 7 6 Bit: 0 OSCSTOP INOSCE RAME Initial value: -- 0 1 R/W: R R/W R/W * Bits 7 and 6: Refer to section 5.4, Precautions for Performing Crystal Resonator Stoppage Detection Function. * Bits 5 to 2--Reserved: These bits are always read as 0. The write value should always be 0. * 7 6 0 -- -- RAME Initial value: 0 0 1 R/W: R R R/W Bits 7 to 2--Reserved: These bits are always read as 0. The write value should always be 0. 25.2.3 System Control Register 2 (SYSCR2) 27.2.3 System Control Register 2 (SYSCR2) 947 Bit 7: Description amended Bit: Initial value: R/W: * 7 Bit: 0 CKSEL MSTOP0 0 1 R/W R/W Bit 7--Internal Clock () Select (CKSEL): See section 5, Clock Pulse Generator (CPG). * 7 0 -- MSTOP0 Initial value: 0 1 R/W: R R/W Bit 7--Reserved: This bit is always read as 0 and cannot be modified. 25.3.1 Transition to Hardware Standby Mode 27.3.1 Transition to Hardware Standby Mode 949 Description amended Hardware standby mode reduces power consumption drastically by halting all SH7058 functions. As the transition to hardware standby mode is made by means of external pin input, the transition is made asynchronously, regardless of the current state of the SH7058, and therefore the chip state prior to the transition is not preserved. In hardware standby mode, power consumption is drastically reduced by halting all the functions in this LSI and stopping the internal power supply except the on-chip RAM. Since the the transition to hardware standby mode is made by external pin input, the transition is made asynchronously, regardless of the current state of this LSI, and internal power supply is stopped except the on-chip RAM. Therefore the chip state prior to the transition is not preserved. Rev. 5.00 Feb. 24, 2010 Page lxviii of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 25.4.1 Transition to Software Standby Mode 27.4.1 Transition to Software Standby Mode 950 Description amended ... The SH7058 switches from the program execution state to software standby mode. In software standby mode, power consumption is greatly reduced by halting not only the CPU, but the clock and on-chip peripheral modules as well. CPU register contents and on-chip RAM data are held as long as the prescribed voltages are applied (when the RAME bit in SYSCR1 is 0). The register contents of some on-chip peripheral modules are initialized, but some are not. The I/O port state can be selected as held or high impedance by the port high impedance bit (HIZ) in SBYCR. ... This LSI switches from the program execution state to software standby mode. In software standby mode, power consumption is drastically reduced by halting all the functions in this LSI and stopping the internal power supply except the on-chip RAM. The contents of the on-chip RAM are held as long as the given voltages are suppled. For details on the regiseter states of on-chip peripheral modules, see Appendix A.2, Register States in Reset and Power-Down States. For details on the pin states, see Appendix B, Pin States. 25.4.2 Canceling Software Standby Mode 27.4.2 Canceling Software Standby Mode 950 Description amended Software standby mode is canceled by an NMI interrupt or a power-on reset. Software standby mode is canceled by a rising edge of the NMI pin or a power-on reset. Cancellation by NMI: Cancellation by a rising edge of the NMI pin: Replaced Cancellation by Power-On Reset: Cancellation by Power-On Reset: 951 Description added A power-on reset of the SH7058 caused by driving the RES pin low cancels software standby mode. When the RES pin is driven low, this LSI enters the power-on reset state and software standby mode is canceled. At this time, the software standby flag (SSBYF) is cleared to 0. 25.4.3 Software Standby Mode Application Example 27.4.3 Software Standby Mode Application Example 952 Description amended This example describes a transition to software standby mode on the falling edge of the NMI signal, and cancellation on the rising edge of the NMI signal. The timing is shown in figure 25.3. In this example, the NMI exception processing is started by the falling edge of the NMI signal: a transition to software standby mode is made; the mode is canceled by the rising edge of the NMI signal. The timing is shown in figure 27.3 When the NMI pin is changed from high to low level while the NMI edge select bit (NMIE) in ICR is set to 0 (falling edge detection), the NMI interrupt is accepted. When the NMIE bit is set to 1 (rising edge detection) by the NMI exception service routine, the software standby bit (SSBY) in SBYCR is set to 1, and a SLEEP instruction is executed, software standby mode is entered. When the NMI signal is driven from high to low while the NMI edge select bit (NMIE) in ICR is set to 0 (falling edge detection), the NMI interrupt is accepted. When the NMIE bit is set to 1 (rising edge detection) by the NMI exception service routine and the SLEEP instruction is executed with the software standby bit (SSBY) in SBYCR set to 1, software standby mode is entered and the internal power supply is stopped. Thereafter, software standby mode is canceled when the NMI pin is changed from low to high level. Thereafter, software standby mode is canceled when the NMI signal is driven from low to high. After the internal power supply is provided, the clock starts oscillation, and the oscillation settling counter overflows, the power-on reset exception processing begins. Figure 25.3 Software Standby Mode NMI Timing (Application Example) Figure 27.3 Software Standby Mode NMI Timing (Application Example) Figure replaced Rev. 5.00 Feb. 24, 2010 Page lxix of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 25.5.2 Canceling Sleep Mode 27.5.2 Canceling Sleep 953 Note added Note: When performing cancellation by power-on reset, do not place RAM write instructions immediately (within eight instructions) after the sleep instruction. This will ensure that no instructions are executed before the transition to the reset. 27.1 Absolute Maximum Ratings 29.1 Absolute Maximum Ratings Table 27.1 Absolute Maximum Ratings Table 29.1 Absolute Maximum Ratings 957 Table amended Item Power supply voltage* Symbol Rating Unit Remarks Item VCC and PLLVCC pins VCC -0.3 to +4.3 V The PLLCAP, EXTAL, XTAL, CK, and H-UDI pins are concerned. (VCC and PLLVCC are the same voltage) Power supply voltage* PVCC1 and PVCC2 pins PVCC -0.3 to + 6.5 V Except for the PLLCAP, EXTAL, XTAL, CK, and H-UDI pins and the analog input pin Vin -0.3 to VCC + 0.3 V Vin -0.3 to PVCC + 0.3 V Input voltage EXTAL and H-UDI pins All pins other than analog input, EXTAL, and H-UDI pins Refer to table 27.2, Correspondence between Power Supply Names and Pins Symbol Rating Unit Remarks VCC and PLLVCC pins VCC -0.3 to +4.3 V The EXTAL, XTAL, CK, and H-UDI pins are concerned. (VCC and PLLVCC are the same voltage) PVCC1 and PVCC2 pins PVCC -0.3 to + 6.5 V Except for the PLLCAP, EXTAL, XTAL, CK, and H-UDI pins and the analog input pin Vin Refer to table 29.2, Correspondence between Power Supply Names and Pins -0.3 to VCC + 0.3 V All pins other than Vin analog input, EXTAL, PLLCAP, and H-UDI pins -0.3 to PVCC + 0.3 V PLLCAP pin -0.3 to + 2.1 V Input voltage EXTAL and H-UDI pins Vin 27.2 DC Characteristics 29.2 DC Characteristics Table 27.2 Correspondence between Power Supply Names and Pins Table 29.2 Correspondence between Power Supply Names and Pins 960, 964, 965, 967 Description of functions 3 and 4 amended Pin No. (FP-2 Function Function 56H) 3 4 Pin No. Function 3 Function 4 45 SCS0 46 SCS1 45 135 ADTO0A 46 136 ADTO0B 135 137 ADTO1A 136 138 137 143 SSO0 138 144 SSI0 143 160 SSCK0 144 164 SCK2 160 167 SSO1 164 168 SSI1 SCK2 ADTO1B 167 223 SSCK1 168 230 SCS0 223 231 IRQOUT 230 231 IRQOUT Rev. 5.00 Feb. 24, 2010 Page lxx of xciv REJ09B0177-0500 SSCK1 SCS1 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 27.2 DC Characteristics 29.2 DC Characteristics Table 27.4 DC Characteristics Table 29.4 DC Characteristics Table amended 973, 974 Item Symbol Current Normal operation consumption Sleep ICC Min Typ Max Unit - 100 150 mA -- 80 130 mA Measurement Conditions Item f = 80 MHz Current consumption -- -- 300 A Ta 50C (2.7 V Vcc 3.6 V) -- -- 750 A 50C < Ta 105C -- 1000 A 105C < Ta 125C RAM standby -- -- 600 A Ta 50C (2.4 V Vcc 2.7 V) -- -- 1000 A 50C < Ta 105C -- -- 1000 A 105C < Ta 125C -- 80 130 mA VCC = 3.3 V Write operation Symbol Min Typ Max Unit Measurement Conditions ICC -- 100 150 mA f = 80 MHz (SH7058SF) mA f = 80 MHz (SH7058SF) Sleep Standby -- Normal operation -- 130 180 -- 80 130 f = 80 MHz (SH7059F) -- 90 160 Standby -- -- 300 A Ta 50C (2.4 V Vcc 3.6 V) -- -- 750 A 50C < Ta 105C -- -- 1000 A 105C < Ta 125C -- 110 170 mA VCC = 3.3 V -- 140 200 Write operation f = 80 MHz (SH7059F) f = 80 MHz (SH7058SF) VCC = 3.3 V f = 80 MHz (SH7059F) f = 40 MHz Item Symbol Analog supply During A/D conversion current AlCC Awaiting A/D conversion, standby Min Typ Max Unit -- 1.2 5 mA -- 1.0 30 A Measurement Conditions Item Analog supply current During A/D conversion Symbol Min Typ Max Unit AlCC -- 4.5 12 mA -- 1.0 30 A Awaiting A/D conversion, standby Measurement Conditions 27.3.5 Advanced Timer Unit Timing and Advance Pulse Controller Timing 29.3.5 Advanced Timer Unit Timing and Advance Pulse Controller Timing Figure 27.13 ATU Clock Input Timing Figure 29.13 ATU Clock Input Timing 987 Figure replaced CK VOL VOL tTCKS CK VOL VOL tTCKS tTCKS tTCKS TCLKA, TCLKB TCLKA, TCLKB tTCKWL tTCKWH tTCKWL 27.3.9 HCAN Timing 29.3.9 HCAN Timing 991 Usage note added. tTCKWH Rev. 5.00 Feb. 24, 2010 Page lxxi of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 27.3.10 A/D Converter Timing 29.3.10 A/D Converter Timing Table 27.15 A/D Converter Timing Table 29.15 A/D Converter Timing 992 Description amended CKS=0:fop=T.B.D CKS=0:fop=10 to 20 MHz CKS=1:fop=T.B.D CKS=1:fop=10 MHz 29.3.11MTAD Timing Newly added 29.3.15 SSU Timing Newly added 27.5 Flash Memory Characteristics 29.5.1 SH7058S Table 27.20 Flash Memory Characteristics Table 29.22 Flash Memory Characteristics 1001 Table and notes amended Item Item Symbol Min Typ Max Unit Programming time*1*2*4 tP -- 3 200 ms/128 bytes Erase time*1*3*5 tE -- 2 20 s/block Reprogramming count NWEC 100 -- -- Times 1 2 4 Programming time* * * 1 3 5 Symbol Min Typ Max Unit tP -- 1 20 ms/128 bytes tE -- 1.3 3.5 s/block 100 -- -- Times Erase time* * * Reprogramming count NWEC Notes: 1. 2. 3. 4. Use the on-chip programming/erasing routine for programming/erasure. When all 0 are programmed. 128 Kbytes of block The total reprogramming time (programming time + erasing time) is as follows. 20 s (typ), 35 s (reference value), 50 s (max) However, 90% of the values are within the reference value. 5. tE distributes focusing on near the typ. value. Notes: 1. 2. 3. 4. Use the on-chip programming/erasing routine for programming/erasure. When all 0 are programmed. 128 kbytes of block The total reprogramming time (programming time + erasing time) is as follows. 40 s (typ.), reference value: 60 s, 80 s (max.) However, 90% of the values are within the reference value. 5. tP, tE distributes focusing on near the typ. value. 29.5.2 SH7059 Newly added A.1 Address A.1 Address Table A.1 Address Table A.1 Address Table and notes amended 1007, 1008, 1029, 1030 Register Name AbbreviBit 7 ation Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit Names Bit 2 Bit 1 Bit 0 H'FFFFD082 TCR TCR15 TCR14 TCR13 TCR12 TCR11 TCR10 TCR9 -- H'FFFFD083 TCR7 -- TPSC5 TPSC4 TPSC3 TPSC2 TPSC1 TPSC0 Bit 6 Bit 5 Bit 4 Bit 2 Bit 1 Bit 0 Register Name AbbreviBit 7 ation Register Name [12] Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TCR13 TCR12 TCR11 TCR10 TCR9 -- H'FFFFD883 TCR7 -- TPSC5 TPSC4 TPSC3 TPSC2 TPSC1 TPSC0 Bit 6 Bit 5 Bit 4 Bit 2 Bit 1 Bit 0 Bit 3 Bit 2 Bit 1 Bit 0 TCR12 TCR11 TCR10 TCR9 -- TCR7 -- TCR5 TCR4 TCR3 TCR2 TCR1 TCR0 Bit 6 Bit 5 Bit 4 Bit 2 Bit 1 Bit 0 H'FFFFD083 Register Name Abbreviation Bit 7 H'FFFFD10C MB0[11], [12] MSG_DATA_4 Bit 3 MSG_DATA_5 Rev. 5.00 Feb. 24, 2010 Page lxxii of xciv REJ09B0177-0500 Bit 3 MSG_DATA_5 Register Name Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'FFFFD882 TCR TCR15 TCR14 TCR13 TCR12 TCR11 TCR10 TCR9 -- TCR7 -- TCR5 TCR4 TCR3 TCR2 TCR1 TCR0 Bit 6 Bit 5 Bit 4 Bit 2 Bit 1 Bit 0 H'FFFFD883 Bit Names H'FFFFD90C MBx[11], MSG_DATA_4 [12] Bit 4 TCR13 Bit Names Bit 5 TCR14 H'FFFFD90D Bit 5 TCR14 Bit Names Bit 6 TCR15 AbbreviBit 7 ation Bit 6 TCR15 H'FFFFD10D H'FFFFD882 TCR Register Name Bit 7 TCR Bit Names Bit 3 MSG_DATA_5 AbbreviBit 7 ation Abbreviation H'FFFFD082 Bit Names H'FFFFD10C MBx[11], MSG_DATA_4 H'FFFFD10D Register Name Bit Names Register Name Abbreviation Bit 7 H'FFFFD90C MB0[11], [12] MSG_DATA_4 H'FFFFD90D MSG_DATA_5 Bit 3 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 A.1 Address A.1 Address Table A.1 Address Table A.1 Address Table and notes amended 1051, 1065, 1067- 1069, 1072 Register Name AbbreviBit 7 ation Bit Names Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'FFFFEC14 SBYCR SSBY HIZ -- -- -- -- -- -- H'FFFFEC26 RAMER -- -- -- -- -- -- -- -- Register Name Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'FFFFEC14 SBYCR SSBY -- SSBYF -- -- -- -- -- H'FFFFEC26 RAMER* -- -- -- -- -- -- -- -- -- -- -- -- RAMS RAM2 RAM1 RAM0 -- -- -- -- -- -- -- -- -- -- -- -- RAMS -- -- RAM0 2 H'FFFFEC27 H'FFFFEC27 -- -- -- RAMS -- RAM2 RAM1 RAM0 H'FFFFEC26 3 RAMER* H'FFFFEC27 Notes: 1. This is the read address. The Write Address is H'FFFEC10 for TCSR and TCNT, and H'FFFEC12 for RSTCSR. For details, see section 13.2.4, Register Access. 2. Version with 1-Mbyte ROM and 48-Kbyte RAM 3. Version with 1.5-Mbyte ROM and 80-Kbyte RAM Register Abbrevi-a Name tion Bit Names Bit Names Bit 7 H'FFFFF708 SYSCR1 H'FFFFF70A SYCSR2* -- Bit 6 OSCSTOP INOSCE 1 2 H'FFFFF70B SYCSR2* CKSEL Register Abbrevi-ati -- -- Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Name Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 -- -- -- -- -- -- AUDSRST RAME 1 -- -- -- -- -- -- -- -- 2 -- -- -- -- MSTOP3 MSTOP2 MSTOP1 MSTOP0 -- -- -- -- AUDSRST RAME H'FFFFF708 SYSCR1 -- -- -- -- -- H'FFFFF70A SYCSR2* H'FFFFF70B SYCSR2* Register Name Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'FFFFF722 PACRH PA15MD1 PA15MD0 PA14MD1 PA14MD0 -- PA13MD -- PA12MD PA11MD1 PA11MD0 PA10MD1 PA10MD0 PA9MD1 PA9MD0 PA8MD1 PA8MD0 PB15MD1 PB15MD0 PB14MD1 PB14MD0 PB13MD1 PB13MD0 PB12MD1 PB12MD0 PB11MD1 PB11MD0 PB10MD1 PB10MD0 PB9MD1 PB9MD0 PB8MD1 PB8MD0 -- -- -- -- -- -- -- PC4MD PC3MD1 PC3MD0 PC2MD1 PC2MD0 -- PC1MD -- PC0MD PFCRH CKHIZ PF15MD0 PF15MD1 PF14MD0 PF14MD1 PF13MD -- PF12MD -- PF11MD -- PF10MD -- PF9MD -- PF8MD PLCRH -- -- -- -- PL13MD1 PL13MD0 PL12MD1 PL12MD0 PL11MD1 PL11MD0 PL10MD1 PL10MD0 PL9MD1 PL9MD0 -- PL8MD PLCRL PL7MD1 PL7MD0 -- PL6MD -- PL5MD -- PL4MD -- PL3MD PL2MD1 PL2MD0 PL1MD1 PL1MD0 -- PL0MD0 H'FFFFF76E ADTRGR0 EXTRG -- -- -- -- -- -- -- H'FFFFF784 PDPR -- -- PD13PR PD12PR PD11PR PD10PR PD9PR PD8PR PD7PR PD6PR PD5PR PD4PR PD3PR PD2PR PD1PR PD0PR PLPR -- -- PL13PR PL12PR PL11PR PL10PR PL9PR PL8PR PL7PR PL6PR PL5PR PL4PR PL3PR PL2PR PL1PR PL0PR H'FFFFF86C ADTCR0 CKSEL10 CKSEL00 -- -- DTSEL0B DTSEL0A ADSEL0B ADSEL0A H'FFFFF86D ADTSR0 -- TADF0B TADF0A ADDF0B ADDF0A ADCYLF0 ADCMF0B ADCMF0A H'FFFFF86E ADTIER0 ADTRG0 TADE0B TADE0A ADDE0B ADDE0A ADCYLE0 ADCME0B ADCNE0A H'FFFFF87C ADTCR1 CKSEL11 CKSEL01 -- -- DTSEL1B DTSEL1A ADSEL1B ADSEL1A H'FFFFF87D ADTSR1 -- TADF1B TADF1A ADDF1B ADDF1A ADCYLF1 ADCMF1B ADCMF1A H'FFFFF87E ADTIER1 ADTRG1 TADE1B TADE1A ADDE1B ADDE1A ADCYLE1 ADCME1B ADCNE1A -- MSTOP3 -- MSTOP2 MSTOP1 -- MSTOP0 Bit Names Name on Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'FFFFF722 PACRH -- -- PA12MD H'FFFFF723 PA11MD1 PA11MD0 PA10MD1 PA10MD0 PA10MD1 PA9MD0 PA8MD1 PA8MD0 H'FFFFF732 PBCRH PB15MD1 PB15MD0 PB14MD1 PB14MD0 -- PB12MD1 PB12MD0 PA15MD -- PA14MD -- PA13MD PB13MD H'FFFFF723 H'FFFFF732 H'FFFFF73C H'FFFFF733 PB11MD1 PB11MD0 PB10MD1 PB10MD0 PB9MD1 PB9MD0 PB8MD1 PBCRH H'FFFFF733 PCCR PB8MD0 H'FFFFF73D H'FFFFF73C PCCR -- -- -- -- -- -- -- PC4MD H'FFFFF74A H'FFFFF73D -- PC3MD -- PC2MD -- PC1MD -- PC0MD H'FFFFF74A PFCRH CKHIZ PF15MD -- PF14MD -- PF13MD -- PF12MD H'FFFFF74B -- PF11MD -- PF10MD -- PF9MD -- PF8MD H'FFFFF74B H'FFFFF758 PLCRH -- -- -- -- PL13MD1 PL13MD0 -- PL12MD H'FFFFF759 PL11MD1 PL11MD0 PL10MD1 PL10MD0 PL9MD1 PL9MD0 -- PL8MD H'FFFFF758 H'FFFFF759 H'FFFFF75A H'FFFFF75B H'FFFFF75A PLCRL -- PL7MD -- PL6MD -- PL5MD -- PL4MD H'FFFFF75B -- PL3MD PL2MD1 PL2MD0 PL1MD1 PL1MD0 -- PL0MD0 H'FFFFF76E ADTRG0 EXTRG -- -- -- -- -- -- -- H'FFFFF784 PDPR PD15PR PD14PR PD13PR PD12PR PD11PR PD10PR PD9PR PD8PR H'FFFFF785 H'FFFFF788 PLPR PD7PR PL15PR PD6PR PL14PR PD5PR PL13PR PD4PR PL12PR PD3PR PL11PR PD2PR PL10PR PD1PR PL9PR H'FFFFF785 H'FFFFF788 H'FFFFF789 PD0PR PL8PR H'FFFFF789 PL7PR PL6PR PL5PR PL4PR PL3PR PL2PR PL1PR PL0PR H'FFFFF86C ADTCR0 CKSEL1x CKSEL0x -- -- DTSELxB DTSELxA ADSELxB ADSELxA H'FFFFF86D ADTSR0 -- TADFxB TADFxA ADDFxB ADDFxA ADCYLFx H'FFFFF86E ADTIER0 ADTRGx TADExB TADExA ADDExB ADDExA ADCYLEx ADCMExB ADCNExA ADCMFxB ADCMFxA H'FFFFF87C ADTCR1 CKSEL1x CKSEL0x -- -- DTSELxB DTSELxA ADSELxB ADCMFxB ADCMFxA SSU newly added ADSELxA H'FFFFF87D ADTSR1 -- TADFxB TADFxA ADDFxB ADDFxA ADCYLFx H'FFFFF87E ADTIER1 ADTRGx TADExB TADExA ADDExB ADDExA ADCYLEx ADCMExB ADCNExA Rev. 5.00 Feb. 24, 2010 Page lxxiii of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 A.2 Register States in Reset and Power-Down States A.2 Register States in Reset and Power-Down States Table A.2 Register States in Reset and Power-Down States Table A.2 Register States After Reset and Power-Down States 1073, 1075, 1076 Title and figure amended Synchronous Serial Communication Unit (SSU), Multi-trigger A/D (MTAD) added, note deleted. Table A.2 Register States in Reset and Power-Down States Power-Down State Type Name Hardware Standby Software Standby CPU R0 to R15 Initialized Held Table amended Power-Down State Type Name Hardware Standby Software Standby CPU R0 to R15 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized SR GBR VBR SR MACH, MACL GBR PR VBR PC MACH, MACL FPU FPSCR PC FPU FR0 to FR15 Initialized Held Interrupt controller (INTC) IPRA to IPRL User break controller (UBC) UBARH, UBARL FPUL IPRA to IPRL Initialized Held UBARH, UBARL UBCR Initialized Held UBAMRH, UBAMRL UBBR UBCR Bus state controller (BSC) BCR1, BCR2 Advanced pulse controller (APC) POPCR Serial communication interface (SCI) SMR0 to SMR4 Initialized Bus state controller (BSC) BCR1, BCR2 Advanced pulse controller (APC) POPCR Initialized Initialized Serial communication interface (SCI) SMR0 to SMR4 Initialized Initialized Initialized Initialized WCR BRR0 to BRR4 SCR0 to SCR4 Held TDR0 to TDR4 WCR Initialized SSR0 to SSR4 Held RDR0 to RDR4 SDCR0 to SDCR4 Initialized Held BRR0 to BRR4 Intialized TDR0 to TDR4 SSR0 to SSR4 ADDR0 (H/L) to ADDR31 (H/L) ADCR0, ADCR1, ADCR2 ADTRGR0, ADTRGR1 ADTRGR2 RDR0 to RDR4 SDCR0 to SDCR4 ADDR0 (H/L) to ADDR31 (H/L) A/D converter ADSCR0, ADCSR1, ADCSR2 SCR0 to SCR4 A/D converter UBAMRH, UBAMRL UBBR ICR ISR User break controller (UBC) ICR ISR FPSCR Interrupt controller (INTC) FR0 to FR15 FPUL PR Held Initialized Initialized ADSCR0, ADCSR1 ADCSR2 ADCR0, ADCR1 ADCR2 ADTRGR0, ADTRGR1 ADTRGR2 Rev. 5.00 Feb. 24, 2010 Page lxxiv of xciv REJ09B0177-0500 Held Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 A.2 Register States in Reset and Power-Down States A.2 Register States in Reset and Power-Down States Table A.2 Register States in Reset and Power-Down States Table A.2 Register States After Reset and Power-Down States 1076-1077 Type Power-Down State Type Name Pin function controller (PFC) PAIOR, PBIOR PCIOR, PDIOR PEIOR, PFIOR PGIOR, PHIOR PJIOR, PKIOR, PLIOR Hardware Standby Software Standby Initialized Held Flash ROM Software Standby Initialized Initialized PADR, PBDR, PCDR, PDDR, Initialized PEDR, PFDR, PGDE, PHDR, PJDR, PKDR, PLDR Initialized PAPR, PBPR, PDPR, PJPR, Pin state PLPR Pin state Initialized Initialized Initialized Initialized Pin function controller PAIOR, PBIOR, (PFC) PCIOR, PDIOR, PEIOR, PFIOR, PGIOR, PHIOR, PJIOR, PKIOR, PLIOR PACRH, PACRL, PBCRH, PBCRL, PBIR, PCCR, PDCRH, PDCRL, PECR, PFCRH, PFCRL, PGCR, PHCR, PJCRH, PJCRL, PKCRH, PKCRL, PKIR, PLCRH, PLCRL, PLIR PACRH, PACRL PBCRH, PBCRL PBIR, PCCR, PDCRH PDCRL, PECR PFCRH, PFCRL PGCR, PHCR, PJCRH PJCRL, PKCRH PKCRL, PKIR, PLCRH PLCRL,PLIR I/O ports Hardware Standby Name I/O ports Flash ROM RAMER FCCS PADR, PBDR, PCDR PDDR, PEDR, PFDR PGDE, PHDR, PJDR PKDR, PLDR Initialized RAMER Initialized FPCS Held FECS FKEY FMATS FCCS Held Initialized/ Held* FTDAR Power-down SBYCR state related SYSCR1, SYSCR2 Initialized FPCS FECS FKEY FMATS Held FTDAR Initialized Initialized Power-down SBYCR state related SYSCR1, SYSCR2 Held MSTCR Type Name Power-On Hardware Standby Software Standby Controller area network MB Undefined Undefined Undefined Held SDIR Held Undefined Undefined Held High-performance user debug interface (H-UDI) Type Name Power-On Hardware Standby Software Standby Controller area network (HCAN) MB Undefined Held High-performance SDIR user debug SDSR interface (H-UDI) SDDRH, SDDRL (HCAN) Held Held SDSR SDDRH, SDDRL Note deleted. Note: * Bit 7 (FLER) is held, and bit 0 (SCO) is initialized. Rev. 5.00 Feb. 24, 2010 Page lxxv of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 Appendix B Pin States Appendix B Pin States Table B.1 Pin States Table B.1 Pin States 1079, 1080 Table amended Pin State Pin State Reset State Reset State Power-Down State Power-Down State Power-On Power-On ROMless Expanded Mode ROMless Expanded Mode Expanded SingleH-UDI Mode with Chip Hardware Software Module ROM Mode Standby Standby Standby AUD Module Standby Bus-Relea sed State O O Clock Type Pin Name 8 Bits Clock CK*2 O Z H*1 O XTAL O L L O O O EXTAL I Z I I I I PLLCAP I I I I I I I Z I I I I I I I I I HSTBY I I I I MD0 I I I I System RES control FWE I I I I I I I I MD0 I I I I I I I MD1 I I I I I I I I MD2 I I I I I I I I WDTOVF O Z Z O O O BREQ -- Z Z I I BACK -- Z Z O O L NMI I Z I I I I O Z O* O O O -- Z Z I I I -- Z Z O O L I Z I I I I IRQ0 to IRQ7 -- Z Z I I I IRQOUT -- Z O* O O O Z Z O O Z -- Z Z I/O I/O Z Z Z I/O I/O Z Z Z I I I WRH, WRL H RD H -- Z Z O CS0 H -- Z Z O -- Z Z O O O O System control Interrupt IRQ0 to IRQ7 Data bus Bus control Z I I I I Z I I Z Z O O O -- Z Z O O Z D0 to D7 Z -- Z Z I/O I/O D8 to D15 -- -- Z Z I/O I/O Z WAIT I -- Z Z I I I WRH, WRL H -- Z Z O O Z RD -- I O IRQOUT Address bus A0 to A21 -- Z Z Z O O I Z H -- CS0 H -- Z Z O O Z CS1 to CS3 -- Z Z O O Z Port POD -- Z Z I I I ATU-II TI0A to TI0D -- Z Z I I I TIO1A to TIO1H -- Z Z I/O I/O I/O TIO2A to TIO2H -- Z Z I/O I/O I/O TIO3A to TIO3D -- Z Z I/O I/O I/O Z Z Z Z CS1 to CS3 -- Z Z O O Z Port POD -- Z Z I I I ATU-II TI0A to TI0D -- Z Z I I I TIO1A to TIO1H -- Z K* 1 I/O I/O I/O TIO2A to TIO2H -- Z K*1 I/O I/O I/O TIO3A to TIO3D -- Z K*1 I/O I/O I/O Pin State Pin State Reset State I HSTBY WDTOVF -- I/O I FWE BREQ Z I/O I I I I I/O Z I I -- O L Z I I WAIT O L I I D8 to D15 O Z I/O I I I -- Z O XTAL EXTAL I I Z AUD Module Bus-Release Standby d State I MD2 Data bus D0 to D7 H-UDI Module Standby I I -- Software Standby Z I O Single-Chi p Mode Hardware Standby I I Address A0 to A21 bus Expanded Mode with ROM I I 1 CK* 1 16 Bits I I Interrupt NMI 8 Bits PLLCAP I 1 Pin Name RES MD1 BACK Bus control 16 Bits Type Reset State Power-Down State Power-Down State Power-On Power-On ROMless Expanded Mode Type Pin Name 8 Bits ATU-II TIO4A to TIO4D -- Expanded SingleH-UDI Mode with Chip Hardware Software Module ROM Mode Standby Standby Standby Z 1 K* TIO5A to TIO5D -- Z K*1 TO6A to TO6D -- Z O* TO7A to TO7D SCI 16 Bits ROMless Expanded Mode -- Z 1 1 O* 8 Bits Software Standby H-UDI Module Standby TIO4A to TIO4D -- Z Z I/O TIO5A to TIO5D -- Z Z I/O I/O I/O TO6A to TO6D -- Z Z O O O AUD Module Bus-Release Standby d State I/O I/O I/O I/O I/O I/O TO7A to TO7D O O O TO8A to TO8P -- Z Z O O O TI9A to TI9F -- Z Z I I I TI10 -- Z Z I I I O O O -- Z O*1 O O O TI9A to TI9F -- Z Z I I I TI10 -- Z Z I I I TIO11A, TIO11B -- Z K*1 I/O I/O I/O TCLKA, TCLKB -- Z Z I I I SCK0 to SCK4 -- Z K*1 I/O I/O I/O TxD0 to TxD4 -- Z O*1 O O O RxD0 to RxD4 Single-Chi p Mode Hardware Standby Pin Name ATU-II Bus-Relea sed State TO8A to TO8P -- Z Z I I I Z Z Z I I I -- Z Z I I I ADEND -- Z O*1 O O O AVref I I I I I I O A/D AN0 to AN31 converter ADTRG0, ADTRG1 Expanded Mode with ROM Type AUD Module Standby SCI A/D converter MTAD 16 Bits -- Z Z O I/O O I/O O TIO11A, TIO11B -- Z Z I/O I/O I/O TCLKA, TCLKB -- Z Z I I I SCK0 to SCK4 -- Z Z I/O I/O I/O TxD0 to TxD4 -- Z Z O O O RxD0 to RxD4 -- Z Z I I I AN0 to AN31 Z Z Z I I I ADTRG0, ADTRG1 -- Z Z I I I ADEND -- Z Z O O O AVref I I I I I I ADTO0A -- Z Z O O O ADTO0B -- Z Z O O O ADTO1A -- Z Z O O O ADTO1B -- Z Z O O O APC PULS0 to PULS7 -- Z Z O O O HCAN HTxD0, HTxD1 -- Z Z O O O APC PULS0 to PULS7 -- Z O*1 O O HRxD0, HRxD1 -- Z Z I O I HCAN HTxD0, HTxD1 -- Z O* 1 O O O UBC UBCTRG -- Z Z O O O HRxD0, HRxD1 -- Z Z I I I I/O port PA0 to PA15 Z Z Z I/O I/O PB0 to PB15 Z Z Z I/O I/O I/O PC0 to PC4 Z Z Z I/O I/O I/O Z Z Z I/O I/O I/O UBC I/O port UBCTRG PA0 to PA15 -- Z Z Z 1 O* 1 K* O O O I/O I/O I/O PD0 to PD13 I/O PB0 to PB15 Z Z K* 1 I/O I/O I/O PE0 to PE15 -- Z PC0 to PC4 Z Z K* 1 I/O I/O I/O PF0 to PF5 -- Z PD0 to PD13 Z Z K*1 I/O I/O I/O PF6 to PF10 -- PE0 to PE15 -- Z Z K* 1 I/O I/O I/O PF0 to PF5 -- Z Z K*1 I/O I/O I/O PH8 to PH15 Z Z Z I/O I/O I/O PJ0 to PJ15 Z Z Z I/O I/O I/O PK0 to PK15 Z Z Z I/O I/O PF6 to PF10 -- PH11 to PF15 Z PG0 to PG3 Z PH0 to PH7 -- PH8 to PH15 Z PJ0 to PJ15 Z Z -- Z K* 1 I/O I/O I/O Z K*1 I/O I/O I/O 1 Z K* I/O I/O I/O Z Z K*1 I/O I/O I/O Z Z K*1 I/O I/O I/O Z K* 1 I/O I/O I/O PK0 to PK15 Z Z K*1 I/O I/O I/O PL0 to PL13 Z Z K* 1 I/O I/O I/O Rev. 5.00 Feb. 24, 2010 Page lxxvi of xciv REJ09B0177-0500 SSU* 2 PH11 to PF15 Z PG0 to PG3 Z PH0 to PH7 -- Z Z -- Z I/O I/O I/O Z I/O I/O I/O Z I/O I/O I/O Z Z Z Z Z I/O I/O Z Z I/O I/O I/O Z Z Z I/O I/O I/O I/O I/O PL0 to PL13 Z Z Z I/O I/O I/O SSCK0, SSCK1 -- Z Z O O O SSI0, SSI1 -- I I I SSO0, SSO1 -- Z Z O O O SCS0, SCS1 -- Z Z Z Z I/O I/O I/O Differences between SH7058 and SH7058S/SH7059 SH7058 (Rev.3, REJ09B0046-0300H) SH7058S/SH7059 Appendix B Pin States Appendix B Pin States Table B.2 Pin States Table B.2 Pin States 1081 Table amended Type Pin Name H-UDI TMS Software Standby Type Software Pin Name Standby I H-UDI TMS TRST I TRST Z TDI I TDI Z TDO O/Z TDO Z TCK I TCK Z Table B.3 Pin States Table B.3 Pin States 1081 Type AUD Z Table amended Software Standby AUDSRST = 1/ Normal Operation Hardware Standby AUD Module Standby AUD Reset (AUDRST = L) AUDRST Z L input H input AUDMD Z I I AUDATA0 to AUDATA3 Z When AUDMD = H: I When AUDMD = L: H (pulled up internally) When AUDMD = H: I/O When AUDMD = L: O AUDCK Z When AUDMD = H: I When AUDMD = L: H (pulled up internally) When AUDMD = H: I When AUDMD = L: O AUDSYNC Z When AUDMD = H: I When AUDMD = L: H (pulled up internally) When AUDMD = H: I When AUDMD = L: O Pin Name Type Pin Name Hardware Standby Software Standby AUD Module Standby AUD Reset (AUDRST = L) AUD AUDRST Z L input H input AUDMD Z I I AUDATA0 to AUDATA3 Z When AUDMD = H: I When AUDMD = L: H (pulled up internally) When AUDMD = H: I/O When AUDMD = L: O AUDCK Z When AUDMD = H: I When AUDMD = L: H (pulled up internally) When AUDMD = H: I When AUDMD = L: O AUDSYNC Z When AUDMD = H: I When AUDMD = L: H (pulled up internally) When AUDMD = H: I When AUDMD = L: O AUDSRST = 1/ Normal Operation Note 1. deleted Notes: 1. When the port impedance bit (HIZ) in the standby control register (SBYCR) is set to 1, output pins become high-impedance. Appendix C. Product Lineup Table C.1 SH7059 F-ZTAT Product Lineup Newly added Table C.2 SH7058 F-ZTAT Product Lineup Table C.2 SH7058S F-ZTAT Product Lineup 1083 Table amended Product Type SH7058 F-ZTAT Operating Temperature (Except for W/E of Flash Memory) Model Name Mark Model Name Package HD64F7058BF80L 64F7058F80 256-pin (FP-256H) -40 C to 105 C HD64F7058BF80K 64F7058F80 256-pin (FP-256H) -40 C to 125 C HD64F7058BP80L 64F7058BP80 272-pin (BP-272) -40 C to 105 C HD64F7058BP80K 64F7058BP80 272-pin (BP-272) -40 C to 125 C Product Type SH7058S F-ZTAT Model Name Mark Model Name Package Operating Temperature (Except for W/E of Flash Memory) R4F70580SCL80FP R4F70580SC 256-pin (FP-256H) - 40C to 105C R4F70580SCK80FP R4F70580SC 256-pin (FP-256H) - 40C to 125C R4F70580SCL80BG R4F70580SC 272-pin (BP-272) - 40C to 105C R4F70580SCK80BG R4F70580SC 272-pin (BP-272) - 40C to 125C Rev. 5.00 Feb. 24, 2010 Page lxxvii of xciv REJ09B0177-0500 Differences between SH7058 and SH7058S/SH7059 Rev. 5.00 Feb. 24, 2010 Page lxxviii of xciv REJ09B0177-0500 Contents Section 1 Overview .................................................................................................................................................. 1.1 1.2 1.3 1 Features .................................................................................................................................................................. 1 Block Diagram ....................................................................................................................................................... 7 Pin Description....................................................................................................................................................... 8 1.3.1 Pin Arrangement ....................................................................................................................................... 8 1.3.2 Pin Functions ............................................................................................................................................ 10 1.3.3 Pin Assignments........................................................................................................................................ 17 Section 2 CPU ........................................................................................................................................................... 25 2.1 2.2 2.3 2.4 2.5 Register Configuration ........................................................................................................................................... 2.1.1 General Registers (Rn).............................................................................................................................. 2.1.2 Control Registers ...................................................................................................................................... 2.1.3 System Registers....................................................................................................................................... 2.1.4 Floating-Point Registers............................................................................................................................ 2.1.5 Floating-Point System Registers ............................................................................................................... 2.1.6 Initial Values of Registers......................................................................................................................... Data Formats .......................................................................................................................................................... 2.2.1 Data Format in Registers........................................................................................................................... 2.2.2 Data Formats in Memory .......................................................................................................................... 2.2.3 Immediate Data Format ............................................................................................................................ Instruction Features................................................................................................................................................ 2.3.1 RISC-Type Instruction Set........................................................................................................................ 2.3.2 Addressing Modes .................................................................................................................................... 2.3.3 Instruction Format..................................................................................................................................... Instruction Set by Classification ............................................................................................................................ 2.4.1 Instruction Set by Classification ............................................................................................................... Processing States.................................................................................................................................................... 2.5.1 State Transitions........................................................................................................................................ 25 25 26 27 27 28 28 28 28 29 29 29 29 32 35 37 37 48 48 Section 3 Floating-Point Unit (FPU) .................................................................................................................. 51 3.1 3.2 3.3 3.4 3.5 3.6 Overview................................................................................................................................................................ Floating-Point Registers and Floating-Point System Registers.............................................................................. 3.2.1 Floating-Point Register File ...................................................................................................................... 3.2.2 Floating-Point Communication Register (FPUL) ..................................................................................... 3.2.3 Floating-Point Status/Control Register (FPSCR)...................................................................................... Floating-Point Format ............................................................................................................................................ 3.3.1 Floating-Point Format............................................................................................................................... 3.3.2 Non-Numbers (NaN) ................................................................................................................................ 3.3.3 Denormalized Number Values.................................................................................................................. 3.3.4 Other Special Values................................................................................................................................. Floating-Point Exception Model ............................................................................................................................ 3.4.1 Enable State Exceptions............................................................................................................................ 3.4.2 Disable State Exceptions........................................................................................................................... 3.4.3 FPU Exception Event and Code................................................................................................................ 3.4.4 Floating-Point Data Arrangement in Memory .......................................................................................... 3.4.5 Arithmetic Operations Involving Special Operands ................................................................................. Synchronization with CPU..................................................................................................................................... Usage Notes ........................................................................................................................................................... 51 51 51 51 52 54 54 54 55 55 55 55 55 56 56 56 56 56 Rev. 5.00 Feb. 24, 2010 Page lxxix of xciv REJ09B0177-0500 Section 4 Operating Modes ................................................................................................................................... 57 4.1 Operating Mode Selection ..................................................................................................................................... 57 Section 5 Clock Pulse Generator (CPG) ............................................................................................................ 59 5.1 5.2 5.3 5.4 Overview................................................................................................................................................................ 5.1.1 Block Diagram.......................................................................................................................................... 5.1.2 Pin Configuration...................................................................................................................................... Frequency Ranges.................................................................................................................................................. 5.2.1 Frequency Ranges..................................................................................................................................... Clock Source.......................................................................................................................................................... 5.3.1 Connecting a Crystal Oscillator ................................................................................................................ 5.3.2 External Clock Input Method.................................................................................................................... Usage Notes ........................................................................................................................................................... 59 59 60 60 60 61 61 62 63 Section 6 Exception Processing ........................................................................................................................... 65 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 Overview................................................................................................................................................................ 6.1.1 Types of Exception Processing and Priority ............................................................................................. 6.1.2 Exception Processing Operations.............................................................................................................. 6.1.3 Exception Processing Vector Table .......................................................................................................... Resets ..................................................................................................................................................................... 6.2.1 Types of Reset .......................................................................................................................................... 6.2.2 Power-On Reset ........................................................................................................................................ 6.2.3 Manual Reset ............................................................................................................................................ Address Errors ....................................................................................................................................................... 6.3.1 Address Error Sources .............................................................................................................................. 6.3.2 Address Error Exception Processing......................................................................................................... Interrupts................................................................................................................................................................ 6.4.1 Interrupt Sources....................................................................................................................................... 6.4.2 Interrupt Priority Level ............................................................................................................................. 6.4.3 Interrupt Exception Processing ................................................................................................................. Exceptions Triggered by Instructions .................................................................................................................... 6.5.1 Types of Exceptions Triggered by Instructions ........................................................................................ 6.5.2 Trap Instructions ....................................................................................................................................... 6.5.3 Illegal Slot Instructions ............................................................................................................................. 6.5.4 General Illegal Instructions....................................................................................................................... 6.5.5 Floating-Point Instructions........................................................................................................................ When Exception Sources Are Not Accepted ......................................................................................................... Stack Status after Exception Processing Ends ....................................................................................................... Usage Notes ........................................................................................................................................................... 6.8.1 Value of Stack Pointer (SP) ...................................................................................................................... 6.8.2 Value of Vector Base Register (VBR) ...................................................................................................... 6.8.3 Address Errors Caused by Stacking of Address Error Exception Processing........................................... 65 65 66 66 68 68 68 69 70 70 70 71 71 71 72 72 72 72 73 73 73 74 75 75 75 75 76 Section 7 Interrupt Controller (INTC) ................................................................................................................ 77 7.1 7.2 Overview................................................................................................................................................................ 7.1.1 Features..................................................................................................................................................... 7.1.2 Block Diagram.......................................................................................................................................... 7.1.3 Pin Configuration...................................................................................................................................... 7.1.4 Register Configuration.............................................................................................................................. Interrupt Sources.................................................................................................................................................... 7.2.1 NMI Interrupts .......................................................................................................................................... 7.2.2 User Break Interrupt ................................................................................................................................. Rev. 5.00 Feb. 24, 2010 Page lxxx of xciv REJ09B0177-0500 77 77 78 79 79 80 80 80 7.3 7.4 7.5 7.6 7.2.3 H-UDI Interrupt ........................................................................................................................................ 7.2.4 IRQ Interrupts ........................................................................................................................................... 7.2.5 On-Chip Peripheral Module Interrupts ..................................................................................................... 7.2.6 Interrupt Exception Vectors and Priority Rankings .................................................................................. Description of Registers......................................................................................................................................... 7.3.1 Interrupt Priority Registers A-L (IPRA-IPRL) ........................................................................................ 7.3.2 Interrupt Control Register (ICR)............................................................................................................... 7.3.3 IRQ Status Register (ISR)......................................................................................................................... Interrupt Operation................................................................................................................................................. 7.4.1 Interrupt Sequence .................................................................................................................................... 7.4.2 Stack after Interrupt Exception Processing ............................................................................................... Interrupt Response Time ........................................................................................................................................ Data Transfer with Interrupt Request Signals ........................................................................................................ 7.6.1 Handling CPU Interrupt Sources, but Not DMAC Activating Sources .................................................... 7.6.2 Handling DMAC Activating Sources but Not CPU Interrupt Sources ..................................................... 80 80 81 81 88 88 89 90 91 91 93 94 96 96 96 Section 8 User Break Controller (UBC) ............................................................................................................ 97 8.1 8.2 8.3 8.4 8.5 Overview................................................................................................................................................................ 8.1.1 Features..................................................................................................................................................... 8.1.2 Block Diagram .......................................................................................................................................... 8.1.3 Register Configuration.............................................................................................................................. Register Descriptions ............................................................................................................................................. 8.2.1 User Break Address Register (UBAR) ..................................................................................................... 8.2.2 User Break Address Mask Register (UBAMR) ........................................................................................ 8.2.3 User Break Bus Cycle Register (UBBR) .................................................................................................. 8.2.4 User Break Control Register (UBCR)....................................................................................................... Operation................................................................................................................................................................ 8.3.1 Flow of the User Break Operation ............................................................................................................ 8.3.2 Break on On-Chip Memory Instruction Fetch Cycle ................................................................................ 8.3.3 Program Counter (PC) Values Saved........................................................................................................ Examples of Use .................................................................................................................................................... 8.4.1 Break on CPU Instruction Fetch Cycle ..................................................................................................... 8.4.2 Break on CPU Data Access Cycle ............................................................................................................ 8.4.3 Break on DMA Cycle ............................................................................................................................... Usage Notes ........................................................................................................................................................... 8.5.1 Simultaneous Fetching of Two Instructions.............................................................................................. 8.5.2 Instruction Fetches at Branches ................................................................................................................ 8.5.3 Contention between User Break and Exception Processing...................................................................... 8.5.4 Break at Non-Delay Branch Instruction Jump Destination....................................................................... 8.5.5 User Break Trigger Output ....................................................................................................................... 8.5.6 Module Standby ........................................................................................................................................ 97 97 98 98 99 99 100 101 102 103 103 104 105 105 105 106 106 107 107 107 108 108 108 108 Section 9 Bus State Controller (BSC) ................................................................................................................ 109 9.1 9.2 Overview................................................................................................................................................................ 9.1.1 Features..................................................................................................................................................... 9.1.2 Block Diagram .......................................................................................................................................... 9.1.3 Pin Configuration...................................................................................................................................... 9.1.4 Register Configuration.............................................................................................................................. 9.1.5 Address Map ............................................................................................................................................. Description of Registers......................................................................................................................................... 9.2.1 Bus Control Register 1 (BCR1) ................................................................................................................ 9.2.2 Bus Control Register 2 (BCR2) ................................................................................................................ 109 109 110 111 111 112 114 114 115 Rev. 5.00 Feb. 24, 2010 Page lxxxi of xciv REJ09B0177-0500 9.3 9.4 9.5 9.6 9.2.3 Wait Control Register (WCR) .................................................................................................................. 9.2.4 RAM Emulation Register (RAMER)........................................................................................................ Accessing External Space ...................................................................................................................................... 9.3.1 Basic Timing............................................................................................................................................. 9.3.2 Wait State Control .................................................................................................................................... 9.3.3 CS Assert Period Extension ...................................................................................................................... Waits between Access Cycles................................................................................................................................ 9.4.1 Prevention of Data Bus Conflicts.............................................................................................................. 9.4.2 Simplification of Bus Cycle Start Detection............................................................................................. Bus Arbitration....................................................................................................................................................... Memory Connection Examples.............................................................................................................................. 117 119 121 121 122 123 123 123 124 125 126 Section 10 Direct Memory Access Controller (DMAC) ............................................................................... 129 10.1 Overview................................................................................................................................................................ 10.1.1 Features..................................................................................................................................................... 10.1.2 Block Diagram.......................................................................................................................................... 10.1.3 Register Configuration.............................................................................................................................. 10.2 Register Descriptions ............................................................................................................................................. 10.2.1 DMA Source Address Registers 0-3 (SAR0-SAR3) ............................................................................... 10.2.2 DMA Destination Address Registers 0-3 (DAR0-DAR3)....................................................................... 10.2.3 DMA Transfer Count Registers 0-3 (DMATCR0-DMATCR3).............................................................. 10.2.4 DMA Channel Control Registers 0-3 (CHCR0-CHCR3)........................................................................ 10.2.5 DMAC Operation Register (DMAOR)..................................................................................................... 10.3 Operation ............................................................................................................................................................... 10.3.1 DMA Transfer Flow ................................................................................................................................. 10.3.2 DMA Transfer Requests ........................................................................................................................... 10.3.3 Channel Priority........................................................................................................................................ 10.3.4 DMA Transfer Types................................................................................................................................ 10.3.5 Dual Address Mode .................................................................................................................................. 10.3.6 Bus Modes ................................................................................................................................................ 10.3.7 Relationship between Request Modes and Bus Modes by DMA Transfer Category................................ 10.3.8 Bus Mode and Channel Priorities ............................................................................................................. 10.3.9 Source Address Reload Function.............................................................................................................. 10.3.10 DMA Transfer Ending Conditions............................................................................................................ 10.3.11 DMAC Access from CPU......................................................................................................................... 10.4 Examples of Use .................................................................................................................................................... 10.4.1 Example of DMA Transfer between On-Chip SCI and External Memory ............................................... 10.4.2 Example of DMA Transfer between A/D Converter and On-Chip Memory (Address Reload On) ......... 10.4.3 Example of DMA Transfer between External Memory and SCI1 Transmitting Side (Indirect Address on) ................................................................................................................................ 10.5 Usage Notes ........................................................................................................................................................... 129 129 130 130 132 132 132 133 134 137 138 138 140 143 143 144 148 149 149 150 151 151 152 152 152 Section 11 Advanced Timer Unit-II (ATU-II) ................................................................................................. 11.1 Overview................................................................................................................................................................ 11.1.1 Features..................................................................................................................................................... 11.1.2 Pin Configuration...................................................................................................................................... 11.1.3 Register Configuration.............................................................................................................................. 11.1.4 Block Diagrams ........................................................................................................................................ 11.1.5 Inter-Channel and Inter-Module Signal Communication Diagram........................................................... 11.1.6 Prescaler Diagram..................................................................................................................................... 11.2 Register Descriptions ............................................................................................................................................. 11.2.1 Timer Start Registers (TSTR) ................................................................................................................... 157 157 157 161 164 170 180 181 182 182 Rev. 5.00 Feb. 24, 2010 Page lxxxii of xciv REJ09B0177-0500 154 155 11.3 11.4 11.5 11.6 11.7 11.8 11.2.2 Prescaler Registers (PSCR)....................................................................................................................... 11.2.3 Timer Control Registers (TCR) ................................................................................................................ 11.2.4 Timer I/O Control Registers (TIOR)......................................................................................................... 11.2.5 Timer Status Registers (TSR) ................................................................................................................... 11.2.6 Timer Interrupt Enable Registers (TIER).................................................................................................. 11.2.7 Interval Interrupt Request Registers (ITVRR) .......................................................................................... 11.2.8 Trigger Mode Register (TRGMDR) ......................................................................................................... 11.2.9 Timer Mode Register (TMDR) ................................................................................................................. 11.2.10 PWM Mode Register (PMDR).................................................................................................................. 11.2.11 Down-Count Start Register (DSTR) ......................................................................................................... 11.2.12 Timer Connection Register (TCNR)......................................................................................................... 11.2.13 One-Shot Pulse Terminate Register (OTR) .............................................................................................. 11.2.14 Reload Enable Register (RLDENR) ......................................................................................................... 11.2.15 Free-Running Counters (TCNT) ............................................................................................................... 11.2.16 Down-Counters (DCNT)........................................................................................................................... 11.2.17 Event Counters (ECNT)............................................................................................................................ 11.2.18 Output Compare Registers (OCR) ............................................................................................................ 11.2.19 Input Capture Registers (ICR) .................................................................................................................. 11.2.20 General Registers (GR)............................................................................................................................. 11.2.21 Offset Base Registers (OSBR) .................................................................................................................. 11.2.22 Cycle Registers (CYLR) ........................................................................................................................... 11.2.23 Buffer Registers (BFR) ............................................................................................................................. 11.2.24 Duty Registers (DTR) ............................................................................................................................... 11.2.25 Reload Register (RLDR)........................................................................................................................... 11.2.26 Channel 10 Registers ................................................................................................................................ Operation................................................................................................................................................................ 11.3.1 Overview................................................................................................................................................... 11.3.2 Free-Running Counter Operation and Cyclic Counter Operation ............................................................. 11.3.3 Compare-Match Function ......................................................................................................................... 11.3.4 Input Capture Function ............................................................................................................................. 11.3.5 One-Shot Pulse Function .......................................................................................................................... 11.3.6 Offset One-Shot Pulse Function and Output Cutoff Function .................................................................. 11.3.7 Interval Timer Operation .......................................................................................................................... 11.3.8 Twin-Capture Function ............................................................................................................................. 11.3.9 PWM Timer Function ............................................................................................................................... 11.3.10 Channel 3 to 5 PWM Function.................................................................................................................. 11.3.11 Event Count Function and Event Cycle Measurement ............................................................................. 11.3.12 Channel 10 Functions................................................................................................................................ Interrupts ................................................................................................................................................................ 11.4.1 Status Flag Setting Timing........................................................................................................................ 11.4.2 Status Flag Clearing.................................................................................................................................. CPU Interface......................................................................................................................................................... 11.5.1 Registers Requiring 32-Bit Access ........................................................................................................... 11.5.2 Registers Permitting 8-Bit, 16-Bit, or 32-Bit Access................................................................................ 11.5.3 Registers Requiring 16-Bit Access ........................................................................................................... 11.5.4 8-Bit or 16-Bit Accessible Registers......................................................................................................... 11.5.5 Registers Requiring 8-Bit Access ............................................................................................................. Sample Setup Procedures....................................................................................................................................... Usage Notes ........................................................................................................................................................... ATU-II Registers and Pins ..................................................................................................................................... 185 186 193 202 224 241 245 245 246 248 253 256 259 260 262 263 263 264 264 266 267 267 268 268 269 280 280 284 285 286 287 288 288 289 290 291 292 293 300 300 303 304 304 305 306 306 307 307 315 324 Rev. 5.00 Feb. 24, 2010 Page lxxxiii of xciv REJ09B0177-0500 Section 12 Advanced Pulse Controller (APC) ................................................................................................. 327 12.1 Overview................................................................................................................................................................ 12.1.1 Features..................................................................................................................................................... 12.1.2 Block Diagram.......................................................................................................................................... 12.1.3 Pin Configuration...................................................................................................................................... 12.1.4 Register Configuration.............................................................................................................................. 12.2 Register Descriptions ............................................................................................................................................. 12.2.1 Pulse Output Port Control Register (POPCR) .......................................................................................... 12.3 Operation ............................................................................................................................................................... 12.3.1 Overview................................................................................................................................................... 12.3.2 Advanced Pulse Controller Output Operation .......................................................................................... 12.4 Usage Notes ........................................................................................................................................................... 327 327 328 329 329 329 329 330 330 331 334 Section 13 Watchdog Timer (WDT)................................................................................................................... 335 13.1 Overview................................................................................................................................................................ 13.1.1 Features..................................................................................................................................................... 13.1.2 Block Diagram.......................................................................................................................................... 13.1.3 Pin Configuration...................................................................................................................................... 13.1.4 Register Configuration.............................................................................................................................. 13.2 Register Descriptions ............................................................................................................................................. 13.2.1 Timer Counter (TCNT)............................................................................................................................. 13.2.2 Timer Control/Status Register (TCSR)..................................................................................................... 13.2.3 Reset Control/Status Register (RSTCSR)................................................................................................. 13.2.4 Register Access......................................................................................................................................... 13.3 Operation ............................................................................................................................................................... 13.3.1 Watchdog Timer Mode ............................................................................................................................. 13.3.2 Interval Timer Mode ................................................................................................................................. 13.3.3 Timing of Setting the Overflow Flag (OVF) ............................................................................................ 13.3.4 Timing of Setting the Watchdog Timer Overflow Flag (WOVF)............................................................. 13.4 Usage Notes ........................................................................................................................................................... 13.4.1 TCNT Write and Increment Contention ................................................................................................... 13.4.2 Changing CKS2 to CKS0 Bit Values ....................................................................................................... 13.4.3 Changing between Watchdog Timer/Interval Timer Modes..................................................................... 13.4.4 System Reset by WDTOVF Signal........................................................................................................... 13.4.5 Internal Reset in Watchdog Timer Mode.................................................................................................. 13.4.6 Manual Reset in Watchdog Timer ............................................................................................................ 335 335 336 336 337 337 337 337 339 339 340 340 342 342 342 343 343 343 343 344 344 344 Section 14 Compare Match Timer (CMT) ........................................................................................................ 345 14.1 Overview................................................................................................................................................................ 14.1.1 Features..................................................................................................................................................... 14.1.2 Block Diagram.......................................................................................................................................... 14.1.3 Register Configuration.............................................................................................................................. 14.2 Register Descriptions ............................................................................................................................................. 14.2.1 Compare Match Timer Start Register (CMSTR) ...................................................................................... 14.2.2 Compare Match Timer Control/Status Register (CMCSR) ...................................................................... 14.2.3 Compare Match Timer Counter (CMCNT) .............................................................................................. 14.2.4 Compare Match Timer Constant Register (CMCOR)............................................................................... 14.3 Operation ............................................................................................................................................................... 14.3.1 Cyclic Count Operation ............................................................................................................................ 14.3.2 CMCNT Count Timing............................................................................................................................. 14.4 Interrupts................................................................................................................................................................ 14.4.1 Interrupt Sources and DTC Activation ..................................................................................................... Rev. 5.00 Feb. 24, 2010 Page lxxxiv of xciv REJ09B0177-0500 345 345 345 346 346 346 347 348 348 349 349 349 349 349 14.4.2 Compare Match Flag Set Timing.............................................................................................................. 14.4.3 Compare Match Flag Clear Timing .......................................................................................................... 14.5 Usage Notes ........................................................................................................................................................... 14.5.1 Contention between CMCNT Write and Compare Match ........................................................................ 14.5.2 Contention between CMCNT Word Write and Incrementation................................................................ 14.5.3 Contention between CMCNT Byte Write and Incrementation ................................................................. 350 350 351 351 351 352 Section 15 Serial Communication Interface (SCI) ......................................................................................... 353 15.1 Overview................................................................................................................................................................ 15.1.1 Features..................................................................................................................................................... 15.1.2 Block Diagram .......................................................................................................................................... 15.1.3 Pin Configuration...................................................................................................................................... 15.1.4 Register Configuration.............................................................................................................................. 15.2 Register Descriptions ............................................................................................................................................. 15.2.1 Receive Shift Register (RSR) ................................................................................................................... 15.2.2 Receive Data Register (RDR) ................................................................................................................... 15.2.3 Transmit Shift Register (TSR) .................................................................................................................. 15.2.4 Transmit Data Register (TDR).................................................................................................................. 15.2.5 Serial Mode Register (SMR)..................................................................................................................... 15.2.6 Serial Control Register (SCR)................................................................................................................... 15.2.7 Serial Status Register (SSR) ..................................................................................................................... 15.2.8 Bit Rate Register (BRR) ........................................................................................................................... 15.2.9 Serial Direction Control Register (SDCR)................................................................................................ 15.2.10 Inversion of SCK Pin Signal..................................................................................................................... 15.3 Operation................................................................................................................................................................ 15.3.1 Overview................................................................................................................................................... 15.3.2 Operation in Asynchronous Mode ............................................................................................................ 15.3.3 Multiprocessor Communication................................................................................................................ 15.3.4 Synchronous Operation............................................................................................................................. 15.4 SCI Interrupt Sources and the DMAC ................................................................................................................... 15.5 Usage Notes ........................................................................................................................................................... 15.5.1 TDR Write and TDRE Flag ...................................................................................................................... 15.5.2 Simultaneous Multiple Receive Errors ..................................................................................................... 15.5.3 Break Detection and Processing (Asynchoronous Mode Only)................................................................ 15.5.4 Sending a Break Signal (Asynchoronous Mode Only) ............................................................................. 15.5.5 Receive Error Flags and Transmitter Operation (Synchronous Mode Only) ............................................ 15.5.6 Receive Data Sampling Timing and Receive Margin in Asynchronous Mode......................................... 15.5.7 Constraints on DMAC Use ....................................................................................................................... 15.5.8 Cautions on Synchronous External Clock Mode ...................................................................................... 15.5.9 Caution on Synchronous Internal Clock Mode ......................................................................................... 15.5.10 Note on Writing to Registers During Transmit, Receive, and Transmit/Receive Operations................... 353 353 354 355 356 357 357 357 357 357 358 360 362 365 370 370 371 371 373 380 387 393 394 394 394 395 395 395 395 396 396 396 396 Section 16 Synchronous Serial Communication Unit (SSU) ...................................................................... 397 16.1 Features .................................................................................................................................................................. 16.2 Input/Output Pins ................................................................................................................................................... 16.3 Register Descriptions ............................................................................................................................................. 16.3.1 SS Control Register H (SSCRH)............................................................................................................... 16.3.2 SS Control Register L (SSCRL) ............................................................................................................... 16.3.3 SS Mode Register (SSMR) ....................................................................................................................... 16.3.4 SS Enable Register (SSER)....................................................................................................................... 16.3.5 SS Status Register (SSSR) ........................................................................................................................ 16.3.6 SS Transmit Data Register 0 to 3 (SSTDR0 to SSTDR3)......................................................................... 397 399 399 401 402 403 404 405 407 Rev. 5.00 Feb. 24, 2010 Page lxxxv of xciv REJ09B0177-0500 16.3.7 SS Receive Data Register 0 to 3 (SSRDR0 to SSRDR3) ......................................................................... 16.3.8 SS Shift Register (SSTRSR)..................................................................................................................... 16.4 Operation ............................................................................................................................................................... 16.4.1 Communication Clock .............................................................................................................................. 16.4.2 Relationship of Clock Phase, Polarity, and Data ...................................................................................... 16.4.3 Relationship between Data I/O Pins and the Shift Register...................................................................... 16.4.4 Data Input/Output Pins and Port IO Register Setting ............................................................................... 16.4.5 Data Transmission and Data Reception .................................................................................................... 16.4.6 SCS Pin Control and Conflict Errors ........................................................................................................ 16.5 Interrupt Requests .................................................................................................................................................. 16.6 Usage Note............................................................................................................................................................. 16.6.1 Note on Using the SSU ............................................................................................................................. 16.6.2 Point to Note when Setting Pins ............................................................................................................... 408 409 410 410 410 410 411 411 418 419 419 419 419 Section 17 Controller Area Network-II (HCAN-II) ....................................................................................... 421 17.1 Overview................................................................................................................................................................ 17.1.1 Features..................................................................................................................................................... 17.2 Architecture ........................................................................................................................................................... 17.2.1 Block Diagram.......................................................................................................................................... 17.2.2 Each Block Function................................................................................................................................. 17.2.3 Pin Configuration...................................................................................................................................... 17.2.4 Memory Map ............................................................................................................................................ 17.3 Mailboxes............................................................................................................................................................... 17.3.1 Mailbox Configuration.............................................................................................................................. 17.3.2 Message Control Field .............................................................................................................................. 17.3.3 Message Data Fields ................................................................................................................................. 17.3.4 Local Acceptance Filter Mask (LAFM)/Tx-Trigger Time (TTT)............................................................. 17.4 HCAN Control Registers ....................................................................................................................................... 17.4.1 Register Descriptions ................................................................................................................................ 17.4.2 Master Control Register_n (MCR_n) (n = 0, 1)........................................................................................ 17.4.3 General Status Register_n (GSR_n) (n = 0, 1).......................................................................................... 17.4.4 HCAN-II_Bit Configuration Register n (HCAN-II_BCR0_n, HCAN-II_BCR1_n) (n = 0, 1) ............... 17.4.5 Interrupt Register_n (IRR_n) (n = 0, 1) .................................................................................................... 17.4.6 Interrupt Mask Register_n (IMR_n) (n = 0, 1) ......................................................................................... 17.4.7 Transmit Error Counter_n (TEC_n) (n = 0, 1)/ Receive Error Counter_n (REC_n) (n = 0, 1)................. 17.5 HCAN Mailbox Registers...................................................................................................................................... 17.5.1 Transmit Wait Register n (TXPR0n, TXPR1n) (n = 0, 1) ........................................................................ 17.5.2 Transmit Wait Cancel Register n (TXCR1n, TXCR0n) (n = 0, 1) ........................................................... 17.5.3 Transmit Acknowledge Register n (TXACK1n, TXACK0n) (n = 0, 1) ................................................... 17.5.4 Abort Acknowledge Register n (ABACK1n, ABACK0n) (n = 0, 1)........................................................ 17.5.5 Receive Complete Register n (RXPR1n, RXPR0n) (n = 0, 1).................................................................. 17.5.6 Remote Request Register n (RFPR1n, RFPR0n) (n = 0, 1) ...................................................................... 17.5.7 Mailbox Interrupt Mask Register n (MBIMR1n, MBIMR0n) (n = 0, 1) .................................................. 17.5.8 Unread Message Status Register n (UMSR1n, UMSR0n) (n = 0, 1) ........................................................ 17.6 Timer Registers...................................................................................................................................................... 17.6.1 Timer Counter Register n (TCNTRn) (n = 0, 1) ....................................................................................... 17.6.2 Timer Control Register_n (TCR_n) (n = 0, 1) .......................................................................................... 17.6.3 Timer Status Register_n (TSR_n) (n = 0, 1) ............................................................................................. 17.6.4 Timer Mode Register_n (TMR_n) (n = 0, 1) ............................................................................................ 17.6.5 Timer Drift Correction Register n (TDCRn) (n = 0, 1)............................................................................. 17.6.6 Local Offset Register n (LOSRn) (n = 0, 1).............................................................................................. 17.6.7 Cycle Counter Register n (CCRn) (n = 0, 1)............................................................................................. Rev. 5.00 Feb. 24, 2010 Page lxxxvi of xciv REJ09B0177-0500 421 421 423 423 423 424 425 426 426 428 433 434 436 436 436 440 442 445 449 449 451 453 454 455 456 457 458 459 460 462 463 463 465 467 467 468 468 17.6.8 Cycle Counter Double-Buffer Register n (CCR_buf n) (n = 0, 1) ............................................................ 17.6.9 Cycle Maximum Register n (CMAXn) (n = 0, 1) ..................................................................................... 17.6.10 Input Capture Registers n (ICR0_cc n, ICR0_buf, ICR0_tm n, ICR1 n) (n = 0, 1) .................................. 17.6.11 Timer Compare Match Registers n (TCMR0n, TCMR1n, TCMR2n) (n = 0, 1) ...................................... 17.7 Operation................................................................................................................................................................ 17.7.1 Test Mode Settings ................................................................................................................................... 17.7.2 HCAN Settings ......................................................................................................................................... 17.7.3 Message Transmission Sequence.............................................................................................................. 17.7.4 Message Transmission Cancellation Sequence......................................................................................... 17.7.5 Message Receive Sequence ...................................................................................................................... 17.7.6 Reconfiguration of Mailboxes .................................................................................................................. 17.7.7 List of Registers ........................................................................................................................................ 17.7.8 Interrupt Sources....................................................................................................................................... 17.7.9 DMAC Interface ....................................................................................................................................... 17.7.10 HCAN-II Port Settings.............................................................................................................................. 17.7.11 CAN Bus Interface.................................................................................................................................... 17.8 Usage Notes ........................................................................................................................................................... 17.8.1 TXPR Setting during Reception ............................................................................................................... 17.8.2 Transmit Cancellation Setting immediately after Transmission Setting in Bus Idle................................. 17.8.3 Failure on Transmit Cancellation at Mailbox 31....................................................................................... 17.8.4 TXPR Setting during Transmission .......................................................................................................... 17.8.5 Time Triggered Transmission Setting/Timer Operation Disabled ............................................................ 17.8.6 Mailbox Access during HCAN Sleep Mode ............................................................................................. 17.8.7 Notes on Port Settings for 64-Buffer HCAN-II with One Channel .......................................................... 469 470 470 472 473 473 474 475 477 478 479 481 482 483 484 485 485 485 486 487 487 488 489 490 Section 18 A/D Converter ...................................................................................................................................... 491 18.1 Overview................................................................................................................................................................ 18.1.1 Features..................................................................................................................................................... 18.1.2 Block Diagram .......................................................................................................................................... 18.1.3 Pin Configuration...................................................................................................................................... 18.1.4 Register Configuration.............................................................................................................................. 18.2 Register Descriptions ............................................................................................................................................. 18.2.1 A/D Data Registers 0 to 31 (ADDR0 to ADDR31) .................................................................................. 18.2.2 A/D Control/Status Registers 0 and 1 (ADCSR0, ADCSR1) ................................................................... 18.2.3 A/D Control Registers 0 to 2 (ADCR0 to ADCR2).................................................................................. 18.2.4 A/D Control/Status Register 2 (ADCSR2)................................................................................................ 18.2.5 A/D Trigger Registers 0 to 2 (ADTRGR0 to ADTRGR2)........................................................................ 18.3 CPU Interface......................................................................................................................................................... 18.4 Operation................................................................................................................................................................ 18.4.1 Single Mode .............................................................................................................................................. 18.4.2 Scan Mode ................................................................................................................................................ 18.4.3 Analog Input Sampling and A/D Conversion Time.................................................................................. 18.4.4 External Triggering of A/D Conversion.................................................................................................... 18.4.5 A/D Converter Activation by ATU-II....................................................................................................... 18.4.6 ADEND Output Pin .................................................................................................................................. 18.5 Interrupt Sources and DMA Transfer Requests ..................................................................................................... 18.6 Usage Notes ........................................................................................................................................................... 18.6.1 A/D conversion accuracy definitions ........................................................................................................ 491 491 492 494 496 497 497 498 501 502 504 505 506 506 507 510 511 512 512 513 513 514 Section 19 Multi-Trigger A/D Converter (MTAD) ........................................................................................ 517 19.1 Overview................................................................................................................................................................ 517 19.1.1 Feature ...................................................................................................................................................... 517 Rev. 5.00 Feb. 24, 2010 Page lxxxvii of xciv REJ09B0177-0500 19.1.2 Block Diagram.......................................................................................................................................... 19.1.3 Input/Output Pins...................................................................................................................................... 19.1.4 Register Configuration.............................................................................................................................. 19.2 Register Descriptions ............................................................................................................................................. 19.2.1 A/D Trigger Control Registers 0 and 1 (ADTCR0 and ADTCR1)........................................................... 19.2.2 A/D Trigger Status Registers 0 and 1 (ADTSR0 and ADTSR1) .............................................................. 19.2.3 A/D Trigger Interrupt Enable Registers 0 and 1 (ADTIER0 and ADTIER1)........................................... 19.2.4 A/D Free-Running Counters (ADCNT0 and ADCNT1) .......................................................................... 19.2.5 A/D General Registers A and B (ADGR0A, ADGR0B, ADGR1A, and ADGR1B)................................ 19.2.6 A/D Cycle Registers 0 and 1 (ADCYLR0 and ADCYLR1)..................................................................... 19.2.7 A/D Duty Registers A and B (ADDR0A, ADDR0B, ADDR1A, and ADDR1B) .................................... 19.3 Operation ............................................................................................................................................................... 19.3.1 Overview................................................................................................................................................... 19.3.2 PWM Operation........................................................................................................................................ 19.3.3 Compare Match Operation........................................................................................................................ 19.3.4 Multi-Trigger A/D Conversion Operation ................................................................................................ 19.3.5 Interrupts................................................................................................................................................... 19.3.6 Usage Notes .............................................................................................................................................. 19.3.7 Operation Waveform Examples................................................................................................................ 518 519 519 520 520 522 524 526 526 527 527 528 528 528 529 529 533 533 534 Section 20 High-performance User Debug Interface (H-UDI) .................................................................. 20.1 Overview................................................................................................................................................................ 20.1.1 Features..................................................................................................................................................... 20.1.2 H-UDI Block Diagram.............................................................................................................................. 20.1.3 Pin Configuration...................................................................................................................................... 20.1.4 Register Configuration.............................................................................................................................. 20.2 External Signals ..................................................................................................................................................... 20.2.1 Test Clock (TCK) ..................................................................................................................................... 20.2.2 Test Mode Select (TMS)........................................................................................................................... 20.2.3 Test Data Input (TDI) ............................................................................................................................... 20.2.4 Test Data Output (TDO) ........................................................................................................................... 20.2.5 Test Reset (TRST) .................................................................................................................................... 20.3 Register Descriptions ............................................................................................................................................. 20.3.1 Instruction Register (SDIR) ...................................................................................................................... 20.3.2 Status Register (SDSR)............................................................................................................................. 20.3.3 Data Register (SDDR) .............................................................................................................................. 20.3.4 Bypass Register (SDBPR) ........................................................................................................................ 20.3.5 Boundary scan register (SDBSR) ............................................................................................................. 20.3.6 ID code register (SDIDR) ......................................................................................................................... 20.4 Operation ............................................................................................................................................................... 20.4.1 TAP Controller ......................................................................................................................................... 20.4.2 H-UDI Interrupt and Serial Transfer......................................................................................................... 20.4.3 H-UDI Reset ............................................................................................................................................. 20.5 Boundary Scan ....................................................................................................................................................... 20.5.1 Supported Instructions .............................................................................................................................. 20.5.2 Notes on Use............................................................................................................................................. 20.6 Usage Notes ........................................................................................................................................................... 537 537 537 538 539 539 540 540 540 540 540 540 541 541 542 543 543 543 555 556 556 556 558 559 559 560 561 Section 21 Advanced User Debugger (AUD) .................................................................................................. 565 21.1 Overview................................................................................................................................................................ 565 21.1.1 Features..................................................................................................................................................... 565 21.1.2 Block Diagram.......................................................................................................................................... 565 Rev. 5.00 Feb. 24, 2010 Page lxxxviii of xciv REJ09B0177-0500 21.2 Pin Configuration................................................................................................................................................... 21.2.1 Pin Descriptions ........................................................................................................................................ 21.3 Branch Trace Mode................................................................................................................................................ 21.3.1 Overview................................................................................................................................................... 21.3.2 Operation .................................................................................................................................................. 21.4 RAM Monitor Mode .............................................................................................................................................. 21.4.1 Overview................................................................................................................................................... 21.4.2 Communication Protocol .......................................................................................................................... 21.4.3 Operation .................................................................................................................................................. 21.5 Usage Notes ........................................................................................................................................................... 21.5.1 Initialization .............................................................................................................................................. 566 566 568 568 568 569 569 569 570 571 571 Section 22 Pin Function Controller (PFC) ........................................................................................................ 573 22.1 Overview................................................................................................................................................................ 573 22.2 Register Configuration ........................................................................................................................................... 577 22.3 Register Descriptions ............................................................................................................................................. 578 22.3.1 Port A IO Register (PAIOR)..................................................................................................................... 578 22.3.2 Port A Control Registers H and L (PACRH, PACRL) ............................................................................. 578 22.3.3 Port B IO Register (PBIOR) ..................................................................................................................... 582 22.3.4 Port B Control Registers H and L (PBCRH, PBCRL) .............................................................................. 582 22.3.5 Port B Invert Register (PBIR) ................................................................................................................... 586 22.3.6 Port C IO Register (PCIOR) ..................................................................................................................... 587 22.3.7 Port C Control Register (PCCR) ............................................................................................................... 587 22.3.8 Port D IO Register (PDIOR)..................................................................................................................... 589 22.3.9 Port D Control Registers H and L (PDCRH, PDCRL) ............................................................................. 589 22.3.10 Port E IO Register (PEIOR)...................................................................................................................... 592 22.3.11 Port E Control Register (PECR) ............................................................................................................... 593 22.3.12 Port F IO Register (PFIOR) ...................................................................................................................... 596 22.3.13 Port F Control Registers H and L (PFCRH, PFCRL) ............................................................................... 597 22.3.14 Port G IO Register (PGIOR)..................................................................................................................... 601 22.3.15 Port G Control Register (PGCR)............................................................................................................... 602 22.3.16 Port H IO Register (PHIOR)..................................................................................................................... 603 22.3.17 Port H Control Register (PHCR)............................................................................................................... 603 22.3.18 Port J IO Register (PJIOR)........................................................................................................................ 608 22.3.19 Port J Control Registers H and L (PJCRH, PJCRL) ................................................................................. 608 22.3.20 Port K IO Register (PKIOR)..................................................................................................................... 612 22.3.21 Port K Control Registers H and L (PKCRH, PKCRL) ............................................................................. 612 22.3.22 Port K Invert Register (PKIR) .................................................................................................................. 615 22.3.23 Port L IO Register (PLIOR)...................................................................................................................... 616 22.3.24 Port L Control Registers H and L (PLCRH, PLCRL)............................................................................... 616 22.3.25 Port L Invert Register (PLIR) ................................................................................................................... 620 Section 23 I/O Ports (I/O) ...................................................................................................................................... 621 23.1 Overview................................................................................................................................................................ 621 23.2 Port A ..................................................................................................................................................................... 621 23.2.1 Register Configuration.............................................................................................................................. 621 23.2.2 Port A Data Register (PADR) ................................................................................................................... 622 23.2.3 Port A Port Register (PAPR) .................................................................................................................... 622 23.3 Port B ..................................................................................................................................................................... 623 23.3.1 Register Configuration.............................................................................................................................. 623 23.3.2 Port B Data Register (PBDR) ................................................................................................................... 624 23.3.3 Port B Port Register (PBPR)..................................................................................................................... 624 Rev. 5.00 Feb. 24, 2010 Page lxxxix of xciv REJ09B0177-0500 23.4 Port C ..................................................................................................................................................................... 23.4.1 Register Configuration.............................................................................................................................. 23.4.2 Port C Data Register (PCDR) ................................................................................................................... 23.5 Port D..................................................................................................................................................................... 23.5.1 Register Configuration.............................................................................................................................. 23.5.2 Port D Data Register (PDDR)................................................................................................................... 23.5.3 Port D Port Register (PDPR) .................................................................................................................... 23.6 Port E ..................................................................................................................................................................... 23.6.1 Register Configuration.............................................................................................................................. 23.6.2 Port E Data Register (PEDR).................................................................................................................... 23.7 Port F...................................................................................................................................................................... 23.7.1 Register Configuration.............................................................................................................................. 23.7.2 Port F Data Register (PFDR) .................................................................................................................... 23.8 Port G..................................................................................................................................................................... 23.8.1 Register Configuration.............................................................................................................................. 23.8.2 Port G Data Register (PGDR)................................................................................................................... 23.9 Port H..................................................................................................................................................................... 23.9.1 Register Configuration.............................................................................................................................. 23.9.2 Port H Data Register (PHDR)................................................................................................................... 23.10 Port J ...................................................................................................................................................................... 23.10.1 Register Configuration.............................................................................................................................. 23.10.2 Port J Data Register (PJDR) ..................................................................................................................... 23.10.3 Port J Port Register (PJPR) ....................................................................................................................... 23.11 Port K..................................................................................................................................................................... 23.11.1 Register Configuration.............................................................................................................................. 23.11.2 Port K Data Register (PKDR)................................................................................................................... 23.12 Port L ..................................................................................................................................................................... 23.12.1 Register Configuration.............................................................................................................................. 23.12.2 Port L Data Register (PLDR).................................................................................................................... 23.12.3 Port L Port Register (PLPR) ..................................................................................................................... 23.13 POD (Port Output Disable) Control....................................................................................................................... 625 625 626 627 627 627 628 629 629 630 631 631 632 633 633 633 634 635 635 636 636 637 638 638 639 639 640 640 640 641 642 Section 24 ROM (SH7058S) ................................................................................................................................. 643 24.1 Features.................................................................................................................................................................. 643 24.2 Overview................................................................................................................................................................ 644 24.2.1 Block Diagram.......................................................................................................................................... 644 24.2.2 Operating Mode ........................................................................................................................................ 645 24.2.3 Mode Comparison..................................................................................................................................... 646 24.2.4 Flash Memory Configuration.................................................................................................................... 646 24.2.5 Block Division .......................................................................................................................................... 647 24.2.6 Programming/Erasing Interface ................................................................................................................ 648 24.3 Pin Configuration................................................................................................................................................... 649 24.4 Register Configuration........................................................................................................................................... 650 24.4.1 Registers ................................................................................................................................................... 650 24.4.2 Programming/Erasing Interface Registers ................................................................................................ 652 24.4.3 Programming/Erasing Interface Parameters ............................................................................................. 656 24.4.4 RAM Emulation Register (RAMER)........................................................................................................ 664 24.5 On-Board Programming Mode .............................................................................................................................. 666 24.5.1 Boot Mode ................................................................................................................................................ 666 24.5.2 User Program Mode.................................................................................................................................. 669 24.5.3 User Boot Mode........................................................................................................................................ 676 24.6 Protection ............................................................................................................................................................... 679 Rev. 5.00 Feb. 24, 2010 Page xc of xciv REJ09B0177-0500 24.7 24.8 24.9 24.10 24.6.1 Hardware Protection ................................................................................................................................. 24.6.2 Software Protection................................................................................................................................... 24.6.3 Error Protection......................................................................................................................................... Flash Memory Emulation in RAM......................................................................................................................... Usage Notes ........................................................................................................................................................... 24.8.1 Switching between User MAT and User Boot MAT ................................................................................ 24.8.2 Interrupts during Programming/Erasing.................................................................................................... 24.8.3 Other Notes ............................................................................................................................................... Programmer Mode ................................................................................................................................................. 24.9.1 Pin Arrangement of Socket Adapter ......................................................................................................... 24.9.2 Programmer Mode Operation ................................................................................................................... 24.9.3 Memory-Read Mode................................................................................................................................. 24.9.4 Auto-Program Mode ................................................................................................................................. 24.9.5 Auto-Erase Mode ...................................................................................................................................... 24.9.6 Status-Read Mode..................................................................................................................................... 24.9.7 Status Polling ............................................................................................................................................ 24.9.8 Time Taken in Transition to Programmer Mode ...................................................................................... 24.9.9 Notes on Programming in Programmer Mode .......................................................................................... Further Information................................................................................................................................................ 24.10.1 Serial Communication Interface Specification for Boot Mode................................................................. 24.10.2 AC Characteristics and Timing in Programmer Mode.............................................................................. 24.10.3 Storable Area for Procedure Program and Programming Data ................................................................. 679 679 680 682 685 685 686 688 690 690 692 693 694 694 695 695 695 695 696 696 716 722 Section 25 ROM (SH7059) ................................................................................................................................... 727 25.1 Features .................................................................................................................................................................. 25.2 Overview................................................................................................................................................................ 25.2.1 Block Diagram .......................................................................................................................................... 25.2.2 Operating Mode ........................................................................................................................................ 25.2.3 Mode Comparison..................................................................................................................................... 25.2.4 Flash Memory Configuration.................................................................................................................... 25.2.5 Block Division .......................................................................................................................................... 25.2.6 Programming/Erasing Interface ................................................................................................................ 25.3 Pin Configuration................................................................................................................................................... 25.4 Register Configuration ........................................................................................................................................... 25.4.1 Registers.................................................................................................................................................... 25.4.2 Programming/Erasing Interface Registers ................................................................................................ 25.4.3 Programming/Erasing Interface Parameters.............................................................................................. 25.4.4 RAM Emulation Register (RAMER)........................................................................................................ 25.5 On-Board Programming Mode .............................................................................................................................. 25.5.1 Boot Mode ................................................................................................................................................ 25.5.2 User Program Mode.................................................................................................................................. 25.5.3 User Boot Mode........................................................................................................................................ 25.6 Protection ............................................................................................................................................................... 25.6.1 Hardware Protection ................................................................................................................................. 25.6.2 Software Protection................................................................................................................................... 25.6.3 Error Protection......................................................................................................................................... 25.7 Flash Memory Emulation in RAM......................................................................................................................... 25.8 Usage Notes ........................................................................................................................................................... 25.8.1 Switching between User MAT and User Boot MAT ................................................................................ 25.8.2 Interrupts during Programming/Erasing.................................................................................................... 25.8.3 Other Notes ............................................................................................................................................... 25.9 Programmer Mode ................................................................................................................................................. 727 728 728 729 730 730 731 732 733 734 734 736 740 749 750 750 753 760 763 763 764 764 766 769 769 770 772 774 Rev. 5.00 Feb. 24, 2010 Page xci of xciv REJ09B0177-0500 25.9.1 Pin Arrangement of Socket Adapter ......................................................................................................... 25.9.2 Programmer Mode Operation ................................................................................................................... 25.9.3 Memory-Read Mode................................................................................................................................. 25.9.4 Auto-Program Mode ................................................................................................................................. 25.9.5 Auto-Erase Mode...................................................................................................................................... 25.9.6 Status-Read Mode..................................................................................................................................... 25.9.7 Status Polling ............................................................................................................................................ 25.9.8 Time Taken in Transition to Programmer Mode ...................................................................................... 25.9.9 Notes on Programming in Programmer Mode .......................................................................................... 25.10 Further Information................................................................................................................................................ 25.10.1 Serial Communication Interface Specification for Boot Mode................................................................. 25.10.2 AC Characteristics and Timing in Programmer Mode.............................................................................. 25.10.3 Storable Area for Procedure Program and Programming Data ................................................................. 774 776 777 778 778 779 779 779 779 780 780 800 806 Section 26 RAM ....................................................................................................................................................... 811 26.1 Overview................................................................................................................................................................ 811 26.2 Operation ............................................................................................................................................................... 812 Section 27 Power-Down State .............................................................................................................................. 813 27.1 Overview................................................................................................................................................................ 27.1.1 Power-Down States................................................................................................................................... 27.1.2 Pin Configuration...................................................................................................................................... 27.1.3 Related Registers ...................................................................................................................................... 27.2 Register Descriptions ............................................................................................................................................. 27.2.1 Standby Control Register (SBYCR) ......................................................................................................... 27.2.2 System Control Register 1 (SYSCR1) ...................................................................................................... 27.2.3 System Control Register 2 (SYSCR2) ...................................................................................................... 27.2.4 Notes on Register Access.......................................................................................................................... 27.3 Hardware Standby Mode ....................................................................................................................................... 27.3.1 Transition to Hardware Standby Mode ..................................................................................................... 27.3.2 Canceling Hardware Standby Mode ......................................................................................................... 27.3.3 Hardware Standby Mode Timing.............................................................................................................. 27.4 Software Standby Mode......................................................................................................................................... 27.4.1 Transition to Software Standby Mode ...................................................................................................... 27.4.2 Canceling Software Standby Mode........................................................................................................... 27.4.3 Software Standby Mode Application Example......................................................................................... 27.5 Sleep Mode ............................................................................................................................................................ 27.5.1 Transition to Sleep Mode.......................................................................................................................... 27.5.2 Canceling Sleep Mode .............................................................................................................................. 813 813 814 815 815 815 816 817 818 818 818 819 819 819 819 819 820 821 821 821 Section 28 Reliability .............................................................................................................................................. 823 28.1 Reliability............................................................................................................................................................... 823 Section 29 Electrical Characteristics .................................................................................................................. 825 29.1 Absolute Maximum Ratings .................................................................................................................................. 29.2 DC Characteristics ................................................................................................................................................. 29.3 AC Characteristics ................................................................................................................................................. 29.3.1 Timing for swicthing the power supply on/off ......................................................................................... 29.3.2 Clock timing ............................................................................................................................................. 29.3.3 Control Signal Timing .............................................................................................................................. 29.3.4 Bus Timing ............................................................................................................................................... 29.3.5 Advanced Timer Unit Timing and Advance Pulse Controller Timing ..................................................... Rev. 5.00 Feb. 24, 2010 Page xcii of xciv REJ09B0177-0500 825 826 837 837 838 840 842 845 29.3.6 I/O Port Timing......................................................................................................................................... 29.3.7 Watchdog Timer Timing........................................................................................................................... 29.3.8 Serial Communication Interface Timing................................................................................................... 29.3.9 HCAN Timing .......................................................................................................................................... 29.3.10 A/D Converter Timing .............................................................................................................................. 29.3.11 MTAD Timing .......................................................................................................................................... 29.3.12 H-UDI Timing .......................................................................................................................................... 29.3.13 AUD Timing ............................................................................................................................................. 29.3.14 UBC Trigger Timing................................................................................................................................. 29.3.15 Synchronous Serial Communication Unit Timing .................................................................................... 29.3.16 Measuring Conditions for AC Characteristics .......................................................................................... 29.4 A/D Converter Characteristics ............................................................................................................................... 29.5 Flash Memory Characteristics................................................................................................................................ 29.5.1 SH7058S ................................................................................................................................................... 29.5.2 SH7059 ..................................................................................................................................................... 29.6 Usage Note............................................................................................................................................................. 29.6.1 Notes on Connecting External Capacitor for Current Stabilization .......................................................... 29.6.2 Notes on Mode Pin Input .......................................................................................................................... 846 847 848 850 851 852 853 855 857 857 859 860 861 861 861 862 862 862 Appendix A On-chip peripheral module Registers ......................................................................................... 865 A.1 A.2 Address .................................................................................................................................................................. 865 Register States in Reset and Power-Down States .................................................................................................. 934 Appendix B Pin States ............................................................................................................................................ 939 Appendix C Product Lineup .................................................................................................................................. 943 Appendix D Package Dimensions ....................................................................................................................... 945 Main Revisions for This Edition ............................................................................................................................ 947 Rev. 5.00 Feb. 24, 2010 Page xciii of xciv REJ09B0177-0500 Rev. 5.00 Feb. 24, 2010 Page xciv of xciv REJ09B0177-0500 1. Overview Section 1 Overview 1.1 Features This LSI is a single-chip RISC microcontroller that integrates a RISC CPU core using an original Renesas architecture with peripheral functions required for system configuration. The CPU has a RISC-type instruction set. Basic instructions can be executed in one state (one system clock cycle), which greatly improves instruction execution speed. In addition, the 32-bit internal architecture enhances data processing power. With this CPU, it has become possible to assemble low-cost, high-performance/high-functionality systems even for applications such as real-time control, which could not previously be handled by microcontrollers because of their highspeed processing requirements. In addition, this LSI includes on-chip peripheral functions necessary for system configuration, such as a floating-point unit (FPU) , ROM , RAM, a direct memory access controller (DMAC), timers, a serial communication interface (SCI), controller area network-II (HCAN-II), A/D converter, interrupt controller (INTC), and I/O ports. ROM and SRAM can be directly connected by means of an external memory access support function, greatly reducing system cost. On-chip ROM is available as flash memory in the F-ZTAT* (Flexible Zero Turn Around Time) version. The flash memory can be programmed with a programmer that supports this LSI programming, and can also be programmed and erased by software. Since the programming/erasing control program is included as firmware, programming and erasing can be performed by calling this program with a user program. This enables the chip to be programmed by the user while mounted on a board. The features of this LSI are summarized in table 1.1. Note: * F-ZTAT is a trademark of Renesas Technology, Corp. Rev. 5.00 Feb. 24, 2010 Page 1 of 950 REJ09B0177-0500 1. Overview Table 1.1 Features Item Features CPU * Maximum operating frequency: 80 MHz * Original Renesas SH-2E CPU * 32-bit internal architecture * General register machine Operating states Sixteen 32-bit general registers Three 32-bit control registers Four 32-bit system registers * Instruction execution time: Basic instructions execute in one state (12.5 ns/instruction at 80 MHz operation) * Address space: Architecture supports 4 Gbytes * Five-stage pipeline * Operating modes Single-chip mode 8/16-bit bus expanded mode * Mode with on-chip ROM * Mode with no on-chip ROM * Processing states Reset state Program execution state Exception handling state Bus-released state Power-down state * Power-down state Sleep mode Software standby mode Hardware standby mode Module standby Multiplier * 32 x 32 64 multiply operations executed in two to four cycles 32 x 32 + 64 64 multiply-and-accumulate operations executed in two to four cycles Floating-point unit (FPU) * SuperH architecture coprocessor * Supports single-precision floating-point operations * Supports a subset of the data types specified by the IEEE standard * Supports invalid operation and division-by-zero exception detection (subset of IEEE standard) * Supports Round to Zero as the rounding mode (subset of IEEE standard) * Sixteen 32-bit floating-point data registers * Supports the FMAC instruction (multiply-and-accumulate instruction) * Supports the FDIV instruction (divide instruction) * Supports the FLDI0/FLDI1 instructions (constant 0/1 load instructions) * Instruction delay time: Two cycles for each of FMAC, FADD, FSUB, and FMUL instructions * Execution pitch: One cycle for each of FMAC, FADD, FSUB, and FMUL instructions Rev. 5.00 Feb. 24, 2010 Page 2 of 950 REJ09B0177-0500 1. Overview Item Features Clock pulse generator (CPG/PLL) * On-chip clock pulse generator (maximum operating frequency: 80 MHz) * Independent generation of CPU system clock and peripheral clock for peripheral modules * On-chip clock-multiplication PLL circuit (x8) * Internal clock frequency range: 5 to 10 MHz * Nine external interrupt pins (NMI, IRQ0 to IRQ7) * 123 internal interrupt sources (ATU-II x 75, SCI x 20, DMAC x 4, A/D x 5, WDT x 1, UBC x 1, CMT x 2, HCAN-II x 8, HUDI x 1, SSU* x 6 ) * 16 programmable priority levels * Requests an interrupt when the CPU or DMAC generates a bus cycle with specified conditions (interrupt can also be masked) * Trigger pulse output (UBCTRG) on break condition Interrupt controller (INTC) User break controller (UBC) Selection of trigger pulse width ( x1, x4, x8, x16) Bus state controller (BSC) * Simplifies configuration of an on-chip debugger * Supports external memory access (SRAM and ROM directly connectable) 8/16-bit bus space * 3.3 V bus interface * 16 MB address space divided into four areas, with the following parameters settable for each area: Bus size (8 or 16 bits) Number of wait cycles Chip select signals (CS0 to CS3) output for each area Direct memory access controller (DMAC) (4 channels) * Wait cycles can be inserted using an external WAIT signal * External access in minimum of two cycles * Provision for idle cycle insertion to prevent bus collisions * DMA transfer possible for the following devices: External memory, on-chip memory, on-chip peripheral modules (excluding DMAC, UBC, BSC) * DMA transfer requests by on-chip modules SCI, A/D converter, ATU-II, HCAN-II, SSU* * Cycle steal or burst mode transfer * Dual address mode Direct transfer mode Indirect transfer mode (channel 3 only) Note: * * Address reload function (channel 2 only) * Transfer data width: Byte/word/longword SSU: Synchronous Serial Communication Unit Rev. 5.00 Feb. 24, 2010 Page 3 of 950 REJ09B0177-0500 1. Overview Item Features Advanced timer unit-II (ATU-II) * Maximum 65 inputs or outputs can be processed Four 32-bit input capture inputs Thirty 16-bit input capture inputs/output compare outputs Sixteen 16-bit one-shot pulse outputs Eight 16-bit PWM outputs Six 8-bit event counters One gap detection function * I/O pin output inversion function Advanced pulse controller (APC) * Maximum eight pulse outputs on reception of ATU-II (channel 11) compare-match signal Watchdog timer (WDT) (1 channel) * Can be switched between watchdog timer and interval timer function * Internal reset, external signal, or interrupt generated by counter overflow * Two kinds of internal reset Power-on reset Manual reset Compare-match timer (CMT) (2 channels) * Selection of 4 counter input clocks * A compare-match interrupt can be requested independently for each channel Serial communication interface (SCI) (5 channels) * Selection of asynchronous or synchronous mode * Simultaneous transmission/reception (full-duplex) capability * Serial data communication possible between multiple processors (asynchronous mode) * Clock inversion function Synchronous serial communication unit (SSU) (2 channels) Controller area network-II (HCAN-II) (2 channels) * LSB-/MSB-first selection function for transmission * Support for master mode * Synchronous serial communications with devices having a different clock phase or polarity * Choice of 8/16/32-bit width of transmit/receive data * Full-duplex communication capability * Continuous serial communications * Choice of LSB-first or MSB-first transfer * Choice of clock source from among seven internal clocks * Five interrupt sources * CAN version: Bosch 2.0B active compatible * Buffer size (per channel): Transmit/receive x 31, receive-only x 1 * Receive message filtering capability Rev. 5.00 Feb. 24, 2010 Page 4 of 950 REJ09B0177-0500 1. Overview Item Features A/D converter * Thirty-two channels * Three sample-and-hold circuits * Selection of two conversion modes Independent operation of 12 channels x 2 and 8 channels x 1 Single conversion mode Scan mode * Continuous scan mode * Single-cycle scan mode * Can be activated by external trigger or ATU-II compare-match * 10-bit resolution * Accuracy: 2 LSB Multi-trigger A/D (MTAD) * While performing conversion on the specified channels in scan mode, A/D conversion on the channels for which conversion has been requested can be performed prior to the other channels when a compare match occurs with respect to the timer in the A/D converter High-performance user debug interface (H-UDI) * Compliant with IEEE1149.1 Five test signals (TCK, TDI, TD0, TMS, and TRST) TAP controller Instruction register Data register Bypass register * Test mode compliant with IEEE1149.1 Standard instructions: BYPASS, SAMPLE/PRELOAD, EXTEST Optional instructions: CLAMP, HIGHZ, IDCODE * H-UDI interrupt H-UDI interrupt request to INTC Advanced user debugger (AUD) * Eight dedicated pins * RAM monitor mode Data input/output frequency: 1/8 or less of the internal operating frequency () Possible to read/write to a module connected to the internal/external bus I/O ports (including timer I/O pins, address and data buses) * Branch address output mode * Dual-function input/output pins: 149 * Schmitt input pins: NMI, IRQn, RES, HSTBY, FWE, TCLK, IC, IC/OC, SCK, ADTRG * Input port protection Rev. 5.00 Feb. 24, 2010 Page 5 of 950 REJ09B0177-0500 1. Overview Item Features ROM * 1 MB Flash memory (SH7058S), 1.5 MB Flash memory (SH7059) * Flash memory: Divided into 16 blocks SH7058S 4 KB x 8 blocks 96 KB x 1 block 128 KB x 7 blocks SH7059 4 KB x 8 blocks 96 KB x 1 block 128 KB x 3 blocks 256 KB x 4 blocks * RAM emulation function (using 4 KB block) * Programming/erasing control program included as firmware * Flash memory programming methods Boot mode User program mode User boot mode Programmer mode RAM * 48 KB (SH7058S), 80 KB (SH7059) SRAM Rev. 5.00 Feb. 24, 2010 Page 6 of 950 REJ09B0177-0500 1. Overview PF13/CS3 PF12/CS2 PF11/CS1 PF10/CS0 PF5/A21/POD PF4/A20 PF3/A19 PF2/A18 PF1/A17 PF0/A16 PE15/A15 PE14/A14 PE13/A13 PE12/A12 PE11/A11 PE10/A10 PE9/A9 PE8/A8 PE7/A7 PE6/A6 PE5/A5 PE4/A4 PE3/A3 PE2/A2 PE1/A1 PE0/A0 Port/address signals Clock pulse generator RAM 80 KB (SH7059) 48 KB (SH7058S) Port/data signals ROM (flash) 1.5 MB (SH7059) 1.0 MB (SH7058S) CPU DMAC (4 channels) FPU Multiplier Interrupt controller PH15/D15 PH14/D14 PH13/D13 PH12/D12 PH11/D11 PH10/D10 PH9/D9 PH8/D8 PH7/D7 PH6/D6 PH5/D5 PH4/D4 PH3/D3 PH2/D2 PH1/D1 PH0/D0 BSC SCI (5 channels) SSU* (2 channels) HCAN (2 channels) ATU-II CMT (2 channels) AUD H-UDI A/D converter WDT : Peripheral address bus (19 bits) : Peripheral data bus (16 bits) : Internal address bus (32 bits) : Internal upper data bus (16 bits) : Internal lower data bus (16 bits) Note: * SSU: Synchronous Serial Communication Unit Port Port Port PJ15/TI9F PJ14/TI9E PJ13/TI9D PJ12/TI9C PJ11/TI9B PJ10/TI9A PJ9/TIO5D PJ8/TIO5C PJ7/TIO2H PJ6/TIO2G PJ5/TIO2F PJ4/TIO2E PJ3/TIO2D PJ2/TIO2C PJ1/TIO2B PJ0/TIO2A CK EXTAL XTAL PLLVCC PLLVSS PLLCAP Vcc (x8) PVcc1 (x4) PVcc2 (x6) VCL(x3) Vss (x21) AVref (x2) AVcc (x2) AVss (x2) AN31-0 AUDRST AUDMD AUDATA3-0 AUDCK AUDSYNC TMS TRST TDI TDO TCK PD0/TIO1A PD1/TIO1B PD2/TIO1C PD3/TIO1D PD4/TIO1E PD5/TIO1F PD6/TIO1G PD7/TIO1H PD8/PULS0 PD9/PULS1 PD10/PULS2 PD11/PULS3 PD12/PULS4 PD13/PULS6/HTxD0/HTxD1 PL0/TI10 PL1/TIO11A/IRQ6 PL2/TIO11B/IRQ7 PL3/TCLKB PL4/ADTRG0 PL5/ADTRG1 PL6/ADEND SSCK1/PL7/SCK2 PL8/SCK3 PL9/SCK4/IRQ5 PL10/HTxD0/HTxD1/HTxD0 & HTxD1 PL11/HRxD0/HRxD1/HRxD0 & HRxD1 SCS0/PL12/IRQ4 SCS1/PL13/IRQOUT Port/control signals PK15/TO8P PK14/TO8O PK13/TO8N PK12/TO8M PK11/TO8L PK10/TO8K PK9/TO8J PK8/TO8I PK7/TO8H PK6/TO8G PK5/TO8F PK4/TO8E PK3/TO8D PK2/TO8C PK1/TO8B PK0/TO8A RES HSTBY FWE MD2 MD1 MD0 NMI WDTOVF PF15/BREQ/SCS1 PF14/BACK/SCS0 PF8/WAIT PF9/RD PF7/WRH PF6/WRL Block Diagram Port 1.2 PA0/TI0A PA1/TI0B PA2/TI0C PA3/TI0D PA4/TIO3A PA5/TIO3B PA6/TIO3C PA7/TIO3D PA8/TIO4A/ADTO0A PA9/TIO4B/ADTO0B PA10/TIO4C/ADTO1A PA11/TIO4D/ADTO1B PA12/TIO5A PA13/TIO5B PA14/TxD0/SSO0 PA15/RxD0/SSI0 PB0/TO6A PB1/TO6B PB2/TO6C PB3/TO6D PB4/TO7A/TO8A PB5/TO7B/TO8B PB6/TO7C/TO8C PB7/TO7D/TO8D PB8/TxD3/TO8E PB9/RxD3/TO8F PB10/TxD4/HTxD0/TO8G PB11/RxD4/HRxD0/TO8H PB12/TCLKA/UBCTRG PB13/SCK0/SSCK0 PB14/SCK1/TCLKB/TI10 PB15/PULS5/SCK2/SSCK1 PC0/TxD1 PC1/RxD1 PC2/TxD2/SSO1 PC3/RxD2/SSI1 PC4/IRQ0 PG0/PULS7/HRxD0/HRxD1 PG1/IRQ1 PG2/IRQ2/ADEND PG3/IRQ3/ADTRG0 Figure 1.1 Block Diagram Rev. 5.00 Feb. 24, 2010 Page 7 of 950 REJ09B0177-0500 PD8/PULS0 PD9/PULS1 PD10/PULS2 PD11/PULS3 PD12/PULS4 PD13//PULS6/HTxD0/HTxD1 PE0/A0 PE1/A1 PE2/A2 PE3/A3 Vcc PE4/A4 Vss PE5/A5 PE6/A6 PE7/A7 PE8/A8 PE9/A9 PE10/A10 PVcc1 PE11/A11 Vss PE12/A12 PE13/A13 PE14/A14 PE15/A15 PF0/A16 PF1/A17 PF2/A18 VCL PF3/A19 Vss PF4/A20 PF5/A21/POD PF6/WRL PF7/WRH PF8/WAIT PF9/RD PVcc1 PF10/CS0 Vss PF11/CS1 PF12/CS2 PF13/CS3 SCS0/PF14/BACK SCS1/PF15/BREQ Vss CK Vcc MD2 EXTAL Vcc XTAL Vss MD1 FWE HSTBY RES MD0 PLLVcc PLLCAP PLLVss PH0/D0 PH1/D1 PH2/D2 PH3/D3 PH4/D4 PH5/D5 PH6/D6 PVcc1 PH7/D7 Vss PH8/D8 PH9/D9 Vcc PH10/D10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 PK7/TO8H Vcc PK6/TO8G PK5/TO8F PK4/TO8E PK3/TO8D PK2/TO8C PK1/TO8B Vss PK0/TO8A PVcc2 PJ15/TI9F PJ14/TI9E PJ13/TI9D PJ12/TI9C PJ11/TI9B PJ10/TI9A Vcc PJ9/TIO5D Vss PJ8/TIO5C PJ7/TIO2H PJ6/TIO2G PJ5/TIO2F PJ4/TIO2E PJ3/TIO2D PJ2/TIO2C PJ1/TIO2B PJ0/TIO2A PG3/IRQ3/ADTRG0 Vss PG2/IRQ2/ADEND PVcc2 PG1/IRQ1 PG0/PULS7/HRxD0/HRxD1 PC4/IRQ0 PC3/RxD2/SSI1 PC2/TxD2/SSO1 PC1/RxD1 PC0/TxD1 PB15/PULS5/SCK2/SSCK1 Vss PB14/SCK1/TCLKB/TI10 VCL PB13/SCK0/SSCK0 PB12/TCLKA/UBCTRG PB11/RxD4/HRxD0/TO8H PB10/TxD4/HTxD0/TO8G PB9/RxD3/TO8F PB8/TxD3/TO8E PB7/TO7D/TO8D PB6/TO7C/TO8C PB5/TO7B/TO8B PB4/TO7A/TO8A Vss PB3/TO6D PVcc2 PB2/TO6C PB1/TO6B PB0/TO6A PA15/RxD0/SSI0 PA14/TxD0/SSO0 PA13/TIO5B Vss PA12/TIO5A Vcc PA11/TIO4D/ADTO1B PA10/TIO4C/ADTO1A PA9/TIO4B/ADTO0B PA8/TIO4A/ADTO0A PA7/TIO3D PA6/TIO3C PA5/TIO3B PA4/TIO3A PA3/TI0D PA2/TI0C 1. Overview 1.3 Pin Description 1.3.1 Pin Arrangement Vss PK8/TO8I PK9/TO8J PK10/TO8K PK11/TO8L PK12/TO8M PK13/TO8N PVcc2 PK14/TO8O Vss PK15/TO8P PL0/TI10 PL1/TIO11A/IRQ6 PL2/TIO11B/IRQ7 PL3/TCLKB PL4/ADTRG0 PL5/ADTRG1 PL6/ADEND SSCK1/PL7/SCK2 PL8/SCK3 VCL PL9/SCK4/IRQ5 Vss PL10/HTxD0/HTxD1/HTxD0 & HTxD1 PL11/HRxD0/HRxD1/HRxD0 & HRxD1 SCS0/PL12/IRQ4 SCS1/PL13/IRQOUT TMS TRST TDI TDO TCK Vcc AUDRST Vss AUDMD AUDATA0 AUDATA1 AUDATA2 AUDATA3 AUDCK AUDSYNC PVcc2 PD0/TIO1A Vss PD1/TIO1B PD2/TIO1C PD3/TIO1D PD4/TIO1E PD5/TIO1F PD6/TIO1G PD7/TIO1H 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 (Top view) FP-256H INDEX Figure 1.2 Pin Arrangement (FP-256H) Rev. 5.00 Feb. 24, 2010 Page 8 of 950 REJ09B0177-0500 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 PVcc2 PA1/TI0B Vss PA0/TI0A WDTOVF AN31 AN30 AVss AVref AVcc AN29 AN28 AN27 AN26 AN25 AN24 AN23 AN22 AN21 AN20 AN19 AN18 AN17 AN16 AN15 AN14 AN13 AVcc AVref AVss AN12 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 Vss NMI PVcc1 PH15/D15 PH14/D14 PH13/D13 PH12/D12 PH11/D11 Vss 1. Overview PH5 /D5 PH13/D13 PH15/D15 20 NMI AN3 AN5 AN8 AVss AVcc AN15 AN16 AN19 AN21 AN24 AVcc AVss PA2/TI0C PA4/TIO3A Vss AN2 AN7 AN9 AVref AN13 AN18 AN22 AN23 AN28 AVref PVcc2 PA3/TI0D PA6/TIO3C PA7/TIO3D 19 PH2/D2 PH4/D4 PH7/D7 18 PLLVss PH1/D1 PH3/D3 PH8/D8 PH11/D11 PVcc1 AN1 AN4 AN10 AN11 AN14 AN20 AN26 AN27 AN31 Vss PA0/TI0A PA5/TIO3B 17 PLLVcc PLLCAP PH6/D6 PH9/D9 PH10/D10 Vcc Vss AN0 AN6 AN12 AN17 AN25 AN29 AN30 WDTOVF PA1/TI0B PA9/TIO4B/ PA11/TIO4D/ ADTO1B ADTO0B 16 HSTBY RES MD0 PVcc1 Vcc Vss XTAL Vss MD1 PH0/D0 PB0/TO6A PVcc2 EXTAL Vcc MD2 FWE CK Vss PF15/ BREQ/ SCS1 Vcc PH12/D12 PH14/D14 15 14 13 12 11 10 9 8 7 6 5 4 3 2 PF11/CS1 PF10/CS0 PF8/WAIT PF13/CS3 PF12/CS2 PF9/RD PVcc1 PF6/WRL PF5/A21/ POD PA8/TIO4A/ PA10/TIO4C/ ADTO0A ADTO1A PA12/ TIO5A PA14/ TxD0/ SSO0 PA13/ TIO5B PA15/ RxD0 SSI0 PB1/TO6B PB2/TO6C PB4/TO7A/ PB5/TO7B/ PB6/TO7C PB3/TO6D /TO8C TO8B TO8A PB9/RxD3 PB10/TxD4/ PB8/TxD3 PB7/TO7D/ HTxD0/TO8G /TO8E TO8D /TO8F PB13/ SCK0/ SSCK0 PF14/ BACK/ SCS0 Vss Vss Vss Vss PB15/PULS5/ PB11/RxD4/ PB12/TCLKA/ SCK2/SSCK1 HRxD0/TO8H UBCTRG Vss Vss Vss Vss Vss PC1/RxD1 PC0/TxD1 PF7/WRH Vss Vss Vss Vss PC2/TxD2/ PB14/SCK1/ PC3/RxD2 PC4/IRQ0 TCLKB/TI10 /SSI1 SSO1 Vss Vss Vss Vss Vss PVcc2 Vss VCL PG2/IRQ2/ PG0/PULS7/ ADEND HRxD0/HRxD1 Vss VCL PF4/A20 PF3/A19 PF2/A18 PF1/A17 PF0/A16 PE15/A15 PG3/IRQ3/ PJ3/TIO2D PJ2/TIO2C ADTRG0 PG1/IRQ1 Vss PJ8/TIO5C PJ7/TIO2H PJ4/TIO2E PJ0/TIO2A PE14/A14 PE13/A13 PE12/A12 PE11/A11 PE10/A10 PVcc1 PE9/A9 Vcc Vss PJ6/TIO2G PJ1/TIO2B PE8/A8 PE7/A7 PE6/A6 Vcc Vss PVcc2 PJ11/TI9B PJ5/TIO2F PE5/A5 PE4/A4 PE2/A2 PE1/A1 PD8/ PULS0 PD6/ TIO1G PE3/A3 PE0/A0 PD11/ PULS3 PD9/ PULS1 PD7/ TIO1H PD5/ TIO1F PD13/PULS6/ HTxD0/HTxD1 PD12/ PULS4 PD10/ PULS2 PD4/ TIO1E PD2/ TIO1C PD3/ TIO1D PD0/ TIO1A AUDCK AUDATA3 AUDATA1 B C D E F 1 A Index PD1/ TIO1B PL0/TI10 Vss PK8/TO8I PK6/ TO8G PL9/SCK4/ PL7/SCK2/ IRQ5 SSCK1 PL3/ TCLKB PVcc2 PK12/ TO8M PK10/ TO8K PK9/TO8J PK1/TO8B PJ14/TI9E PJ10/TI9A PL12/ IRQ4/ SCS0 PL11/HRxD0/ HRxD1/ HRxD0&HRxD1 VCL PL6/ ADEND PL1/TIO11A/ IRQ6 PK14/ TO8O PK11/ TO8L PK7/TO8H PK3/TO8D PK2/TO8C PJ12/TI9C TRST PL13/ IRQOUT/ SCS1 PL10/HTxD0/ HTxD1/ HTxD0&HTxD1 Vss PL5 / ADTRG1 PL2/TIO11B/ IRQ7 PK15/ TO8P PK13/ TO8N PK5/TO8F PK4/TO8E PK0/TO8A J K L M N P R T PVcc2 Vss TDI PL8/SCK3 AUDMD Vcc TMS AUDRST TCK AUDATA0 TDO G H Vss AUDSYNC AUDATA2 PL4/ ADTRG0 Vcc U PJ15/TI9F PJ13/TI9D PJ9/TIO5D V W Y TOP View Figure 1.3 Pin Assignments Rev. 5.00 Feb. 24, 2010 Page 9 of 950 REJ09B0177-0500 1. Overview 1.3.2 Pin Functions Table 1.2 summarizes the pin functions. Table 1.2 Pin Functions Pin No. Type Symbol FP-256H BP-272 Power supply VCC 11, 49, 52, 75, 139, 187, 203, 237 PVCC1 I/O Name Function Input D5, D13, B14, F17, U16, U6, U4, J3 Power supply Power supply for chip-internal and system ports (RES, MD2-MD0, FWE, HSTBY, NMI, CK, EXTAL, XTAL, H-UDI port). Connect all VCC pins to the system power supply. The chip will not operate if there are any open pins. 20, 39, 70, 83 C6, V11, D16, F18 Input Port power supply 1 Power supply for bus ports (ports E, F, and H). Connect all PVCC1 pins to the system bus power supply. The chip will not operate if there are any open pins. PVCC2 128, 148, 172, 194, 212, 247 U19, V15, V9, V5, Input P3, H4 Port power supply 2 Power supply for peripheral module ports (ports A, B, C, D, G, J, K, and L, the AUD port, and WDTOVF). Connect all PVCC2 pins to the system peripheral module power supply. The chip will not operate if there are any open pins. VCL 30, 161, 225 B9, Y11, M2 Internal stepdown power supply Pins for connection to a capacitor used for stablizing the voltage of the internal step-down power supply. Input Connect VSS to this pin through a (0.33,0.47)-F capacitor. The capacitor should be located near the pin. Do not connect an external power supply to the pin. VSS Flash memory FWE 13, 22, 32, 41, 47, 54, 72, 77, 85, 126, 141, 150, 163, 174, 185, 196, 205, 214, 227, 239, 249 A9, B13, B15, D7, Input D11, F19, G3, G17, J4, J9-12, K9-12, L9-12, M1, M9-12, P4, T18, U5, U9, V6, V16, W11 Ground 56 D14 Flash write enable Rev. 5.00 Feb. 24, 2010 Page 10 of 950 REJ09B0177-0500 Input For connection to ground. Connect all VSS pins to the system ground. The chip will not operate if there are any open pins. Connected to ground in normal operation. Apply VCC during on-board programming. 1. Overview Pin No. Type Symbol FP-256H BP-272 I/O Name Function Clock PLLVCC 60 A17 Input PLL power supply On-chip PLL oscillator power supply. PLL ground On-chip PLL oscillator ground. PLLVSS 62 A18 Input For power supply connection, see section 5, Clock Pulse Generator (CPG). For power supply connection, see section 5, Clock Pulse Generator (CPG). PLLCAP 61 B17 Input PLL capacitance On-chip PLL oscillator external capacitance connection pin. For external capacitance connection, see section 5, Clock Pulse Generator (CPG). System control Operating mode control Interrupts EXTAL 51 A14 Input XTAL 53 A15 Input/ Crystal output For connection to a crystal resonator. CK 48 A13 Output Peripheral clock Supplies the peripheral clock to peripheral devices. RES 58 B16 Input WDTOVF 124 R17 Output Watchdog WDT overflow output signal. timer overflow BREQ 46 C13 Input BACK 45 D12 Output Bus request acknowledge Indicates that the bus has been granted to an external device. The device that output the BREQ signal recognizes that the bus has been acquired when it receives the BACK signal. MD0 to MD2 59, 55, 50 C16, C15, C14 Input Mode setting These pins determine the operating mode. Do not change the input values during operation. HSTBY 57 A16 Input Hardware standby When driven low, this pin forces a transition to hardware standby mode. NMI 84 E20 Input Nonmaskable Nonmaskable interrupt request pin. interrupt Acceptance on the rising edge or falling edge can be selected. IRQ0 to IRQ7 169, 171, 173, 175, 230, 226, 217, 218 V10, Y8, W9, W8, Input K2, L3, P2, P1 231 K1 IRQOUT External clock For connection to a crystal resonator. An external clock source can also be connected to the EXTAL pin. Power-on reset Executes a power-on reset when driven low. Bus request Interrupt requests 0 to 7 Output Interrupt request output Driven low when an external device requests the bus. Maskable interrupt request pins. Level input or edge input can be selected. Indicates that an interrupt has been generated. Enables interrupt generation to be recognized in the bus-released state. Rev. 5.00 Feb. 24, 2010 Page 11 of 950 REJ09B0177-0500 1. Overview Pin No. Type Symbol FP-256H Address bus A0-A21 7-10, 12, 14-19, B3, D4, C4, A3, B4, A4, C5, B5, 21, 23-29, 31, A5, D6, B6, A6, 33, 34 C7, B7, A7, D8, C8, B8, A8, D9, C9, C10 Output Address bus Address output pins. Data bus D0-D15 63-69, 71, 73, 74, 76, 78-82 D15, B18, A19, C18, B19, B20, C17, C19, D18, D17, E17, E18, D19, C20, E19, D20 Input/ Data bus output 16-bit bidirectional data bus pins. Bus control CS0-CS3 40, 42-44 A11, A12, C12, B12 Output Chip select 0 to Chip select signals for external memory 3 or devices. RD 38 B11 Output Read Indicates reading from an external device. WRH 36 D10 Output Upper write Indicates writing of the upper 8 bits of external data. WRL 35 B10 Output Lower write Indicates writing of the lower 8 bits of external data. WAIT 37 A10 Input Wait Input for wait cycle insertion in bus cycles during external space access. TCLKA TCLKB 159, 162, 219 W12, Y10, N3 Input ATU-II timer clock input ATU-II counter external clock Input pins. TI0A-TI0D 125, 127, 129, 130 U18, T17, V20, V19 Input ATU-II input capture (channel 0) Channel 0 input capture input pins. TIO1A-TIO1H 248, 250-256 C1, G4, E2, B1, D2, F3, F4, E3 Input/ ATU-II input Channel 1 input capture input/output output capture/output compare output pins. compare (channel 1) TIO2A-TIO2H 176-183 Y7, Y6, V8, U8, W7, Y5, W6, V7 Input/ ATU-II input Channel 2 input capture input/output output capture/output compare output pins. compare (channel 2) TIO3A-TIO3D 131-134 W20, V18, W19, Y19 Channel 3 input capture input/output Input/ ATU-II input output capture/output compare/PWM output pins. compare/PWM output (channel 3) TIO4A-TIO4D 135-138 W18, U17, Y18, V17 Channel 4 input capture input/output Input/ ATU-II input output capture/output compare/PWM output pins. compare/PWM output (channel 4) Advanced timer unit-II (ATU-II) Rev. 5.00 Feb. 24, 2010 Page 12 of 950 REJ09B0177-0500 BP-272 I/O Name Function 1. Overview Pin No. Type Symbol FP-256H BP-272 I/O Name Function Advanced timer unit-II (ATU-II) Channel 5 input capture input/output TIO5A-TIO5D 140, 142, 184, 186W17, W16, U7, Y4 Input/ ATU-II input output capture/output compare/PWM output pins. compare/PWM output (channel 5) TO6A-TO6D 145-147, 149 U15, W15, Y15, Y14 Output ATU-II PWM output (channel 6) Channel 6 PWM output pins. TO7A-TO7D 151-154 U14, V14, W14, Y13 Output ATU-II PWM output (channel 7) Channel 7 PWM output pins. TO8A-TO8P 151-158, 195, 197-202, 204, 206-211, 213, 215 U14, V14, W14, Output ATU-II oneshot pulse Y13, W13, U13, (channel 8) V13, V12, W1, V3, W2, V2, V1, U1, T4, U2, R4, U3, T3, T2, R3, T1, R2, R1 Channel 8 down-counter one-shot pulse output pins. TI9A-TI9F 188-193 Y3, W5, Y2, W4, W3, V4 Input ATU-II event input (channel 9) Channel 9 event counter input pins. TI10 162, 216 Y10, N4 Input Channel 10 external clock input pin. ATU-II multiplied clock generation (channel 10) TIO11A, TIO11B 217, 218 P2, P1 Channel 11 input capture input/output Input/ ATU-II input output capture/output compare output pins. compare Advanced pulse controller (APC) PULS0-PULS7 1-6, 164, 170 E4, D3, C2, C3, B2, A2, U12, Y9 Output APC pulse outputs 0 to 7 APC pulse output pins. Serial communication interface (SCI) TxD0-TxD4 143, 165, 167, 155, 157 Y17, V11, W10, W13, V13 Output Transmit data SCI0 to SCI4 transmit data output pins. (channels 0 to 4) RxD0-RxD4 144, 166, 168, 156, 158 Y16, U11, U10, U13, V12 Input SCK0-SCK4 160, 162, 223, 224, 226, 164 SCI0 to SCI4 clock input/output pins. Y12, Y10, M3, L4, Input/ Serial clock L3, U12 output (channels 0 to 4) Receive data SCI0 to SCI4 receive data input pins. (channels 0 to 4) Rev. 5.00 Feb. 24, 2010 Page 13 of 950 REJ09B0177-0500 1. Overview Pin No. Type Symbol Synchronous serial SSO0 communication SSO1 unit (SSU) FP-256H BP-272 I/O 143 Y17, W10 Output Transmit data SSU0 and SSU1 transmit data output pins. (Channels 0 and 1) Y16, U10 Input Y12, U12, M3 Output SSU clock (Channels 0 and 1) 167 SSI0 144 SSI1 168 SSCK0 160 SSCK1 164, 223 SCS0 45, 230 SCS1 46, 231 Name Receive data (Channels 0 and 1) D12, K2, C13, K1 Input/ SSU chip output select (Channels 0 and 1) Function SSU0 and SSU1 receive data input pins. SSU0 and SSU1 clock output pins. SSU0 and SSU1 chip select input/output pins. Controller area network-II (HCAN-II) HTxD0, HTxD1 157, 228, 6 V13, L1, A2 Output Transmit data CAN bus transmit data output pins. HRxD0, HRxD1 158, 229, 170 V12, L2, Y9 input Receive data A/D converter AVCC 101, 119 K20, T20 Input Analog power A/D converter power supply. supply AVSS 99, 121 J20, U20 Input Analog ground A/D converter power supply. AVref 100, 120 K19, T19 Input Analog reference power supply Analog reference power supply input pins. AN0-AN31 86-98, 102-118, H17, G18, G19, 122, 123 F20, H18, G20, J17, H19, H20, J19, J18, K18, K17, L19, L18, L20, M20, L17, M19, N20, M18, P20, N19, P19, R20, M17, N18, P18, R19, N17, P17, R18 Input Analog input Analog signal input pins. ADTRG0, ADTRG1 175, 220, 221 W8, M4, N1 Input A/D conversion External trigger input pins for starting A/D trigger input conversion. ADEND 173, 222 W9, N2 Output ADEND output A/D2 channel 31 conversion timing monitor output pins. ADTO0A 135 W18 Output PWM output PWM output pin for multi-trigger A/D conversion. ADTO0B 136 U17 Output PWM output PWM output pin for multi-trigger A/D conversion. ADTO1A 137 Y18 Output PWM output PWM output pin for multi-trigger A/D conversion. ADTO1B 138 V17 Output PWM output PWM output pin for multi-trigger A/D conversion. Rev. 5.00 Feb. 24, 2010 Page 14 of 950 REJ09B0177-0500 CAN bus receive data input pins. 1. Overview Pin No. Type Symbol FP-256H BP-272 I/O User break controller (UBC) UBCTRG 159 W12 Output User break trigger output High-performance TCK user debug TMS interface (H-UDI) TDI Function UBC condition match trigger output pin. 236 J2 Input Test clock Test clock input pin. 232 K3 Input Test mode select Test mode select signal input pin. 234 K4 Input Test data input Instruction/data serial input pin. 235 H1 Output Test data output TRST 233 J1 Input AUDATA0- AUDATA3 241-244 G1, F1, G2, E1 Input/ AUD data output TDO Advanced user debugger (AUD) Name Instruction/data serial output pin. Test reset Initialization signal input pin. Branch trace mode: Branch destination address output pins. RAM monitor mode: Monitor address input / data input/output pins. AUDRST 238 H2 Input AUD reset Reset signal input pin. AUDMD 240 H3 Input AUD mode Mode select signal input pin. Branch trace mode: Low RAM monitor mode: High AUDCK 245 D1 Input/ AUD clock output Branch trace mode: Serial clock output pin. RAM monitor mode: Serial clock input pin. AUDSYNC 246 F2 Branch trace mode: Data start position Input/ AUD output synchronization identification signal output pin. signal RAM monitor mode: Data start position identification signal input pin. I/O ports POD 34 C10 Input PA0-PA15 125, 127, 129- 138, 140, 142- 144 U18, T17, V20, V19, W20, V18, W19, Y19, W18, U17, Y18, V17, W17, W16, Y17, Y16 Input/ Port A output General input/output port pins. 145-147, 149, U15, W15, Y15, 151-160, 162, 164 Y14, U14, V14, W14, Y13, W13, U13, V13, V12, W12, Y12, Y10, U12 Input/ Port B output General input/output port pins. PB0-PB15 Port output disable Input pin for port pin drive control when general port is set for output. Input or output can be specified bit by bit. Input or output can be specified bit by bit. Rev. 5.00 Feb. 24, 2010 Page 15 of 950 REJ09B0177-0500 1. Overview Pin No. Type Symbol FP-256H BP-272 I/O I/O ports PC0-PC4 165-169 V11, U11, W10, U10, V10 Input/ Port C output C1, G4, E2, B1, D2, F3, F4, E3, E4, D3, C2, C3, B2, A2 Input/ Port D output 7-10, 12, 14-19, B3, D4, C4, A3, 21, 23-26 B4, A4, C5, B5, A5, D6, B6, A6, C7, B7, A7, D8 Input/ Port E output 27-29, 31, 33-38, C8, B8, A8, D9, 40, 42-46 C9, C10, B10, D10, A10, B11, A11, A12, C12, B12, D12, C13 Input/ Port F output 170, 171, 173, 175 Input/ Port G output Input or output can be specified bit by bit. 63-69, 71, 73, 74, D15, B18, A19, 76, 78-82 C18, B19, B20, C17, C19, D18, D17, E17, E18, D19, C20, E19, D20 Input/ Port H output Input or output can be specified bit by bit. 176-184, 186, 188-193 Y7, Y6, V8, U8, W7, Y5, W6, V7, U7, Y4, Y3, W5, Y2, W4, W3, V4 Input/ Port J output 195, 197-202, 204, 206-211, 213, 215 W1, V3, W2, V2, V1, U1, T4, U2, R4, U3, T3, T2, R3, T1, R2, R1 Input/ Port K output 216-224, 226, 228-231 N4, P2, P1, N3, Input/ Port L M4, N1, N2, M3, output L4, L3, L1, L2, K2, K1 PD0-PD13 PE0-PE15 PF0-PF15 PG0-PG3 PH0-PH15 PJ0-PJ15 PK0-PK15 PL0-PL13 248, 250-256, 1-6 Rev. 5.00 Feb. 24, 2010 Page 16 of 950 REJ09B0177-0500 Y9, Y8, W9, W8 Name Function General input/output port pins. Input or output can be specified bit by bit. General input/output port pins. Input or output can be specified bit by bit. General input/output port pins. Input or output can be specified bit by bit. General input/output port pins. Input or output can be specified bit by bit. General input/output port pins. General input/output port pins. General input/output port pins. Input or output can be specified bit by bit. General input/output port pins. Input or output can be specified bit by bit. General input/output port pins. Input or output can be specified bit by bit. 1. Overview 1.3.3 Table 1.3 Pin Assignments Pin Assignments Pin No. FP-256H BP-272 MCU Mode Programmer Mode 1 E4 PD8/PULS0 NC 2 D3 PD9/PULS1 NC 3 C2 PD10/PULS2 NC 4 C3 PD11/PULS3 NC 5 B2 PD12/PULS4 NC 6 A2 PD13/PULS6/HTxD0/HTxD1 NC 7 B3 PE0/A0 A0 8 D4 PE1/A1 A1 9 C4 PE2/A2 A2 10 A3 PE3/A3 A3 11 D5 Vcc Vcc 12 B4 PE4/A4 A4 13 * Vss Vss 14 A4 PE5/A5 A5 15 C5 PE6/A6 A6 16 B5 PE7/A7 A7 17 A5 PE8/A8 A8 18 D6 PE9/A9 A9 19 B6 PE10/A10 A10 20 C6 PVcc1 Vcc 21 A6 PE11/A11 A11 22 * Vss Vss 23 C7 PE12/A12 A12 24 B7 PE13/A13 A13 25 A7 PE14/A14 A14 26 D8 PE15/A15 A15 27 C8 PF0/A16 A16 28 B8 PF1/A17 A17 29 A8 PF2/A18 A18 30 B9 VCL VCL 31 D9 PF3/A19 A19 32 * Vss Vss 33 C9 PF4/A20 A20 34 C10 PF5/A21/POD A21 35 B10 PF6/WRL NC 36 D10 PF7/WRH NC 37 A10 PF8/WAIT Vcc Rev. 5.00 Feb. 24, 2010 Page 17 of 950 REJ09B0177-0500 1. Overview Pin No. FP-256H BP-272 MCU Mode Programmer Mode 38 B11 PF9/RD NC 39 C11 PVcc1 Vcc 40 A11 PF10/CS0 NC 41 * Vss Vss 42 A12 PF11/CS1 Vcc 43 C12 PF12/CS2 Vcc 44 B12 PF13/CS3 Vss 45 D12 PF14/BACK/SCS0 NC 46 C13 PF15/BREQ/SCS1 Vcc 47 * Vss Vss 48 A13 CK NC 49 D13 Vcc Vcc 50 C14 MD2 Vss 51 A14 EXTAL EXTAL 52 B14 Vcc Vcc 53 A15 XTAL XTAL 54 * Vss Vss 55 C15 MD1 Vcc 56 D14 FWE FWE 57 A16 HSTBY Vcc 58 B16 RES RES 59 C16 MD0 Vcc 60 A17 PLLVcc PLLVcc 61 B17 PLLCAP PLLCAP 62 A18 PLLVss PLLVss 63 D15 PH0/D0 D0 64 B18 PH1/D1 D1 65 A19 PH2/D2 D2 66 C18 PH3/D3 D3 67 B19 PH4/D4 D4 68 B20 PH5/D5 D5 69 C17 PH6/D6 D6 70 D16 PVcc1 Vcc 71 C19 PH7/D7 D7 72 * Vss Vss 73 D18 PH8/D8 NC 74 D17 PH9/D9 NC 75 F17 Vcc Vcc 76 E17 PH10/D10 NC Rev. 5.00 Feb. 24, 2010 Page 18 of 950 REJ09B0177-0500 1. Overview Pin No. FP-256H BP-272 MCU Mode Programmer Mode 77 * Vss Vss 78 E18 PH11/D11 NC 79 D19 PH12/D12 NC 80 C20 PH13/D13 NC 81 E19 PH14/D14 NC 82 D20 PH15/D15 NC 83 F18 PVcc1 Vcc 84 E20 NMI Vss 85 * Vss Vss 86 H17 AN0 NC 87 G18 AN1 NC 88 G19 AN2 NC 89 F20 AN3 NC 90 H18 AN4 NC 91 G20 AN5 NC 92 J17 AN6 NC 93 H19 AN7 NC 94 H20 AN8 NC 95 J19 AN9 NC 96 J18 AN10 NC 97 K18 AN11 NC 98 K17 AN12 NC 99 J20 AVss Vss 100 K19 AVref Vcc 101 K20 AVcc Vcc 102 L19 AN13 NC 103 L18 AN14 NC 104 L20 AN15 NC 105 M20 AN16 NC 106 L17 AN17 NC 107 M19 AN18 NC 108 N20 AN19 NC 109 M18 AN20 NC 110 P20 AN21 NC 111 N19 AN22 NC 112 P19 AN23 NC 113 R20 AN24 NC 114 M17 AN25 NC 115 N18 AN26 NC Rev. 5.00 Feb. 24, 2010 Page 19 of 950 REJ09B0177-0500 1. Overview Pin No. FP-256H BP-272 MCU Mode Programmer Mode 116 P18 AN27 NC 117 R19 AN28 NC 118 N17 AN29 NC 119 T20 AVcc Vcc 120 T19 AVref Vcc 121 U20 AVss Vss 122 P17 AN30 NC 123 R18 AN31 NC 124 R17 WDTOVF NC 125 U18 PA0/TI0A NC 126 * Vss Vss 127 T17 PA1/TI0B NC 128 U19 PVcc2 Vcc 129 V20 PA2/TI0C NC 130 V19 PA3/TI0D NC 131 W20 PA4/TIO3A NC 132 V18 PA5/TIO3B NC 133 W19 PA6/TIO3C NC 134 Y19 PA7/TIO3D NC 135 W18 PA8/TIO4A/ADTO0A NC 136 U17 PA9/TIO4B/ADTO0B NC 137 Y18 PA10/TIO4C/ADTO1A NC 138 V17 PA11/TIO4D/ADTO1B NC 139 U16 Vcc Vcc 140 W17 PA12/TIO5A NC 141 * Vss Vss 142 W16 PA13/TIO5B NC 143 Y17 PA14/TxD0/SSO0 NC 144 Y16 PA15/RxD0/SSI0 NC 145 U15 PB0/TO6A NC 146 W15 PB1/TO6B NC 147 Y15 PB2/TO6C NC 148 V15 PVcc2 Vcc 149 Y14 PB3/TO6D NC 150 * Vss Vss 151 U14 PB4/TO7A/TO8A NC 152 V14 PB5/TO7B/TO8B NC 153 W14 PB6/TO7C/TO8C NC 154 Y13 PB7/TO7D/TO8D NC Rev. 5.00 Feb. 24, 2010 Page 20 of 950 REJ09B0177-0500 1. Overview Pin No. FP-256H BP-272 MCU Mode Programmer Mode 155 W13 PB8/TxD3/TO8E NC 156 U13 PB9/RxD3/TO8F NC 157 V13 PB10/TxD4/HTxD0/TO8G NC 158 V12 PB11/RxD4/HRxD0/TO8H NC 159 W12 PB12/TCLKA/UBCTRG NC 160 Y12 PB13/SCK0/SSCK0 NC 161 Y11 VCL VCL 162 Y10 PB14/SCK1/TCLKB/TI10 NC 163 * Vss Vss 164 U12 PB15/PULS5/SCK2/SSCK1 NC 165 V11 PC0/TxD1 NC 166 U11 PC1/RxD1 NC 167 W10 PC2/TxD2/SSO1 NC 168 U10 PC3/RxD2/SSI1 NC 169 V10 PC4/IRQ0 NC 170 Y9 PG0/PULS7/HRxD0/HRxD1 NC 171 Y8 PG1/IRQ1 NC 172 V9 PVcc2 Vcc 173 W9 PG2/IRQ2/ADEND NC 174 * Vss Vss 175 W8 PG3/IRQ3/ADTRG0 NC 176 Y7 PJ0/TIO2A NC 177 Y6 PJ1/TIO2B NC 178 V8 PJ2/TIO2C NC 179 U8 PJ3/TIO2D NC 180 W7 PJ4/TIO2E NC 181 Y5 PJ5/TIO2F NC 182 W6 PJ6/TIO2G NC 183 V7 PJ7/TIO2H NC 184 U7 PJ8/TIO5C NC 185 * Vss Vss 186 Y4 PJ9/TIO5D NC 187 U6 Vcc Vcc 188 Y3 PJ10/TI9A NC 189 W5 PJ11/TI9B NC 190 Y2 PJ12/TI9C NC 191 W4 PJ13/TI9D NC 192 W3 PJ14/TI9E NC 193 V4 PJ15/TI9F NC Rev. 5.00 Feb. 24, 2010 Page 21 of 950 REJ09B0177-0500 1. Overview Pin No. FP-256H BP-272 MCU Mode Programmer Mode 194 V5 PVcc2 Vcc 195 W1 PK0/TO8A NC 196 * Vss Vss 197 V3 PK1/TO8B NC 198 W2 PK2/TO8C NC 199 V2 PK3/TO8D NC 200 V1 PK4/TO8E NC 201 U1 PK5/TO8F NC 202 T4 PK6/TO8G NC 203 U4 Vcc Vcc 204 U2 PK7/TO8H NC 205 * Vss Vss 206 R4 PK8/TO8I NC 207 U3 PK9/TO8J NC 208 T3 PK10/TO8K NC 209 T2 PK11/TO8L NC 210 R3 PK12/TO8M NC 211 T1 PK13/TO8N NC 212 P3 PVcc2 Vcc 213 R2 PK14/TO8O NC 214 * Vss Vss 215 R1 PK15/TO8P NC 216 N4 PL0/TI10 NC 217 P2 PL1/TIO11A/IRQ6 NC 218 P1 PL2/TIO11B/IRQ7 CE 219 N3 PL3/TCLKB NC 220 M4 PL4/ADTRG0 NC 221 N1 PL5/ADTRG1 NC 222 N2 PL6/ADEND NC 223 M3 PL7/SCK2/SSCK1 NC 224 L4 PL8/SCK3 NC 225 M2 VCL VCL 226 L3 PL9/SCK4/IRQ5 WE 227 * Vss Vss 228 L1 PL10/HTxD0/HTxD1/HTxD0 & HTxD1 NC 229 L2 PL11/HRxD0/HRxD1/HRxD0 & HRxD1 NC 230 K2 PL12/IRQ4/SCS0 OE 231 K1 PL13/IRQOUT/SCS1 NC 232 K3 TMS NC Rev. 5.00 Feb. 24, 2010 Page 22 of 950 REJ09B0177-0500 1. Overview Pin No. FP-256H BP-272 MCU Mode Programmer Mode 233 J1 TRST NC 234 K4 TDI NC 235 H1 TDO NC 236 J2 TCK NC 237 J3 Vcc Vcc 238 H2 AUDRST NC 239 * Vss Vss 240 H3 AUDMD NC 241 G1 AUDATA0 NC 242 F1 AUDATA1 NC 243 G2 AUDATA2 NC 244 E1 AUDATA3 NC 245 D1 AUDCK NC 246 F2 AUDSYNC NC 247 H4 PVcc2 Vcc 248 C1 PD0/TIO1A NC 249 * Vss Vss 250 G4 PD1/TIO1B NC 251 E2 PD2/TIO1C NC 252 B1 PD3/TIO1D NC 253 D2 PD4/TIO1E NC 254 F3 PD5/TIO1F NC 255 F4 PD6/TIO1G NC 256 E3 PD7/TIO1H NC -- A1 NC NC -- A20 NC NC -- Y1 NC NC Y20 NC NC -- Note: * Vss is connected in the board. Rev. 5.00 Feb. 24, 2010 Page 23 of 950 REJ09B0177-0500 1. Overview Rev. 5.00 Feb. 24, 2010 Page 24 of 950 REJ09B0177-0500 2. CPU Section 2 CPU 2.1 Register Configuration The register set consists of sixteen 32-bit general registers, three 32-bit control registers and four 32-bit system registers. In addition, the FPU has eighteen internal registers: sixteen 32-bit floating-point registers and two 32-bit floating-point system registers. 2.1.1 General Registers (Rn) The sixteen 32-bit general registers (Rn) are numbered R0-R15. General registers are used for data processing and address calculation. R0 is also used as an index register. Several instructions have R0 fixed as their only usable register. R15 is used as the hardware stack pointer (SP). Saving and recovering the status register (SR) and program counter (PC) in exception processing is accomplished by referencing the stack using R15. Figure 2.1 shows the general registers. 31 0 R0*1 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15, SP (hardware stack pointer)*2 Notes: 1. 2. R0 functions as an index register in the indirect indexed register addressing mode and indirect indexed GBR addressing mode. In some instructions, R0 functions as a fixed source register or destination register. R15 functions as a hardware stack pointer (SP) during exception processing. Figure 2.1 General Registers Rev. 5.00 Feb. 24, 2010 Page 25 of 950 REJ09B0177-0500 2. CPU 2.1.2 Control Registers The 32-bit control registers consist of the 32-bit status register (SR), global base register (GBR), and vector base register (VBR). The status register indicates processing states. The global base register functions as a base address for the indirect GBR addressing mode to transfer data to the registers of on-chip peripheral modules. The vector base register functions as the base address of the exception processing vector area (including interrupts). Figure 2.2 shows the control registers. 31 SR 9 8 7 6 5 4 32 1 0 M Q I3 I2 I1 I0 SR: Status register ST T bit: The MOVT, CMP/cond, TAS, TST, BT (BT/S), BF (BF/S), SETT, CLRT, and FCMP/cond instructions use the T bit to indicate true (1) or false (0). The ADDV, ADDC, SUBV, SUBC, NEGC, DIV0U, DIV0S, DIV1, SHAR, SHAL, SHLR, SHLL, ROTR, ROTL, ROTCR, and ROTCL instructions also use the T bit to indicate carry/borrow or overflow/underflow. S bit: Used by the MAC instruction. Reserved bits. These bits always read 0. The write value should always be 0. Bits I3-I0: Interrupt mask bits. M and Q bits: Used by the DIV0U, DIV0S, and DIV1 instructions. Reserved bits. These bits always read 0. The write value should always be 0. 31 GBR 31 0 Global base register (GBR): Indicates the base address of the indirect GBR addressing mode. The indirect GBR addressing mode is used in data transfer for on-chip peripheral module register areas and in logic operations. 0 VBR Vector base register (VBR): Stores the base address of the exception processing vector area. Figure 2.2 Control Register Configuration Rev. 5.00 Feb. 24, 2010 Page 26 of 950 REJ09B0177-0500 2. CPU 2.1.3 System Registers System registers consist of four 32-bit registers: high and low multiply and accumulate registers (MACH and MACL), the procedure register (PR), and the program counter (PC). The multiply-and-accumulate registers store the results of multiply-and-accumulate operations. The procedure register stores the return address from a subroutine procedure. The program counter stores program addresses to control the flow of the processing. Figure 2.3 shows the system registers. 31 0 MACH MACL 31 0 Procedure register (PR): Stores the return address from a subroutine procedure. 0 Program counter (PC): Indicates the fourth byte (second instruction) after the current instruction. PR 31 Multiply-and-accumulate (MAC) registers high and low (MACH, MACL): Store the results of multiply-and-accumulate operations. PC Figure 2.3 System Register Configuration 2.1.4 Floating-Point Registers There are sixteen 32-bit floating-point registers, designated FR0 to FR15, which are used by floating-point instructions. FR0 functions as the index register for the FMAC instruction. These registers are incorporated into the floating-point unit (FPU). For details, see section 3, Floating-Point Unit (FPU). 31 0 FR0 FR0 functions as the index register for the FMAC instruction. FR1 FR2 FR3 FR4 FR5 FR6 FR7 FR8 FR9 FR10 FR11 FR12 FR13 FR14 FR15 Figure 2.4 Floating-Point Registers Rev. 5.00 Feb. 24, 2010 Page 27 of 950 REJ09B0177-0500 2. CPU 2.1.5 Floating-Point System Registers There are two 32-bit floating-point system registers: the floating-point communication register (FPUL) and the floatingpoint status/control register (FPSCR). FPUL is used for communication between the CPU and the floating-point unit (FPU). FPSCR indicates and stores status/control information relating to FPU exceptions. These registers are incorporated into the floating-point unit (FPU). For details, see section 3, Floating-Point Unit (FPU). 0 31 FPUL: FPUL 31 Floating-point communication register Used for communication between the CPU and the FPU. 0 FPSCR: Floating-point status/control register Indicates and stores status/control information relating to FPU exceptions. FPSCR Figure 2.5 Floating-Point System Registers 2.1.6 Initial Values of Registers Table 2.1 lists the values of the registers after reset. Table 2.1 Initial Values of Registers Classification Register Initial Value General registers R0-R14 Undefined R15 (SP) Value of the stack pointer in the vector address table SR Bits I3-I0 are 1111 (H'F), reserved bits are 0, and other bits are undefined GBR Undefined VBR H'00000000 MACH, MACL, PR Undefined PC Value of the program counter in the vector address table Floating-point registers FR0-FR15 Undefined Floating-point system registers FPUL Undefined FPSCR H'00040001 Control registers System registers 2.2 Data Formats 2.2.1 Data Format in Registers Register operands are always longwords (32 bits). When the memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register (figure 2.6). 31 0 Longword Figure 2.6 Data Format in Registers Rev. 5.00 Feb. 24, 2010 Page 28 of 950 REJ09B0177-0500 2. CPU 2.2.2 Data Formats in Memory Memory data formats are classified into bytes, words, and longwords. Byte data can be accessed from any address, but an address error will occur if an attempt is made to access word data starting from an address other than 2n or longword data starting from an address other than 4n. In such cases, the data accessed cannot be guaranteed. The hardware stack area, referred to by the hardware stack pointer (SP, R15), uses only longword data starting from address 4n because this area holds the program counter and status register (figure 2.7). Address m + 1 Address m Byte Address 2n Address 4n Address m + 2 23 31 Address m + 3 7 15 Byte Byte Word 0 Byte Word Longword Figure 2.7 Data Formats in Memory 2.2.3 Immediate Data Format Byte (8 bit) immediate data resides in an instruction code. Immediate data accessed by the MOV, ADD, and CMP/EQ instructions is sign-extended and handled in registers as longword data. Immediate data accessed by the TST, AND, OR, and XOR instructions is zero-extended and handled as longword data. Consequently, AND instructions with immediate data always clear the upper 24 bits of the destination register. Word or longword immediate data is not located in the instruction code, but instead is stored in a memory table. An immediate data transfer instruction (MOV) accesses the memory table using the PC relative addressing mode with displacement. 2.3 Instruction Features 2.3.1 RISC-Type Instruction Set All instructions are RISC type. This section details their functions. 16-Bit Fixed Length: All instructions are 16 bits long, increasing program code efficiency. One Instruction per Cycle: The microprocessor can execute basic instructions in one cycle using the pipeline system. Instructions are executed in 12.5 ns at 80 MHz. Data Length: Longword is the standard data length for all operations. Memory can be accessed in bytes, words, or longwords. Byte or word data accessed from memory is sign-extended and handled as longword data. Immediate data is sign-extended for arithmetic operations or zero-extended for logic operations. It also is handled as longword data (table 2.2). Rev. 5.00 Feb. 24, 2010 Page 29 of 950 REJ09B0177-0500 2. CPU Table 2.2 Sign Extension of Word Data This LSI CPU Description MOV.W @(disp,PC),R1 ADD R1,R0 Data is sign-extended to 32 bits, and R1 becomes ADD.W H'00001234. It is next operated upon by an ADD instruction. ......... .DATA.W Example of Conventional CPU #H'1234,R0 H'1234 Note: @(disp, PC) accesses the immediate data. Load-Store Architecture: Basic operations are executed between registers. For operations that involve memory access, data is loaded to the registers and executed (load-store architecture). Instructions such as AND that manipulate bits, however, are executed directly in memory. Delayed Branch Instructions: Unconditional branch instructions are delayed branch instructions. With a delayed branch instruction, the branch is taken after execution of the instruction following the delayed branch instruction. There are two types of conditional branch instructions: delayed branch instructions and ordinary branch instructions. Table 2.3 Delayed Branch Instructions This LSI CPU Description Example of Conventional CPU BRA TRGET Executes the ADD before branching to TRGET. ADD.W R1,R0 ADD R1,R0 BRA TRGET Multiply/Multiply-and-Accumulate Operations: 16-bit x 16-bit 32-bit multiply operations are executed in one to two cycles. 16-bit x 16-bit + 64-bit 64-bit multiply-and-accumulate operations are executed in two to three cycles. 32bit x 32-bit 64-bit multiply and 32-bit x 32-bit + 64bit 64-bit multiply-and-accumulate operations are executed in two to four cycles. T Bit: The T bit in the status register changes according to the result of the comparison, and in turn is the condition (true/false) that determines if the program will branch. The number of instructions that change the T bit is kept to a minimum to improve the processing speed (table 2.4). Table 2.4 T Bit This LSI CPU Description Example of Conventional CPU CMP/GE R1,R0 CMP.W R1,R0 BT TRGET0 BGE TRGET0 BF TRGET1 T bit is set when R0 R1. The program branches to TRGET0 when R0 R1 and to TRGET1 when R0 < R1. BLT TRGET1 ADD #1,R0 CMP/EQ #0,R0 BT TRGET T bit is not changed by ADD. SUB.W T bit is set when R0 = 0. The program branches if BEQ R0 = 0. #1,R0 TRGET Immediate Data: Byte (8-bit) immediate data resides in the instruction code. Word or longword immediate data is not input via instruction codes but is stored in a memory table. An immediate data transfer instruction (MOV) accesses the memory table using the PC relative addressing mode with displacement (table 2.5). Rev. 5.00 Feb. 24, 2010 Page 30 of 950 REJ09B0177-0500 2. CPU Table 2.5 Immediate Data Accessing Classification This LSI CPU Example of Conventional CPU 8-bit immediate MOV #H'12,R0 MOV.B #H'12,R0 16-bit immediate MOV.W @(disp,PC),R0 MOV.W #H'1234,R0 MOV.L #H'12345678,R0 ................. 32-bit immediate .DATA.W H'1234 MOV.L @(disp,PC),R0 ................. .DATA.L H'12345678 Note: @(disp, PC) accesses the immediate data. Absolute Address: When data is accessed by absolute address, the value already in the absolute address is placed in the memory table. Loading the immediate data when the instruction is executed transfers that value to the register and the data is accessed in the indirect register addressing mode (table 2.6). Table 2.6 Absolute Address Accessing Classification This LSI CPU Example of Conventional CPU Absolute address MOV.L @(disp,PC),R1 MOV.B MOV.B @R1,R0 @H'12345678,R0 .................. .DATA.L H'12345678 Note: @(disp,PC) accesses the immediate data. 16-Bit/32-Bit Displacement: When data is accessed by 16-bit or 32-bit displacement, the pre-existing displacement value is placed in the memory table. Loading the immediate data when the instruction is executed transfers that value to the register and the data is accessed in the indirect indexed register addressing mode (table 2.7). Table 2.7 Displacement Accessing Classification This LSI CPU Example of Conventional CPU 16-bit displacement MOV.W @(disp,PC),R0 MOV.W MOV.W @(R0,R1),R2 @(H'1234,R1),R2 .................. .DATA.W H'1234 Note: @(disp,PC) accesses the immediate data. Rev. 5.00 Feb. 24, 2010 Page 31 of 950 REJ09B0177-0500 2. CPU 2.3.2 Addressing Modes Table 2.8 describes addressing modes and effective address calculation. Table 2.8 Addressing Modes and Effective Addresses Addressing Mode Instruction Format Effective Address Calculation Equation Direct register addressing Rn The effective address is register Rn. (The operand is the contents of register Rn.) -- Indirect register addressing @Rn The effective address is the contents of register Rn. Rn Rn Post-increment indirect @Rn+ register addressing Rn The effective address is the contents of register Rn. A constant is added to the content of Rn after the instruction is executed. 1 is added for a byte operation, 2 for a word operation, and 4 for a longword operation. Rn Rn Rn + 1/2/4 Rn (After the instruction executes) Byte: Rn + 1 Rn Word: Rn + 2 Rn Longword: Rn + 4 Rn + 1/2/4 Pre-decrement indirect @-Rn register addressing The effective address is the value obtained by subtracting Byte: Rn - 1 Rn a constant from Rn. 1 is subtracted for a byte operation, 2 Word: Rn - 2 Rn for a word operation, and 4 for a longword operation. Longword: Rn - 4 Rn (Instruction Rn executed with Rn Rn - 1/2/4 - after calculation) Rn - 1/2/4 1/2/4 Indirect register addressing with displacement @(disp:4, Rn) The effective address is Rn plus a 4-bit displacement (disp). The value of disp is zero-extended, and remains the same for a byte operation, is doubled for a word operation, and is quadrupled for a longword operation. Byte: Rn + disp Word: Rn + disp x 2 Longword: Rn + disp x4 Rn disp (zero-extended) + Rn + disp x 1/2/4 x 1/2/4 Indirect indexed register addressing @(R0, Rn) The effective address is the Rn value plus R0. Rn + R0 Rev. 5.00 Feb. 24, 2010 Page 32 of 950 REJ09B0177-0500 Rn + R0 Rn + R0 2. CPU Addressing Mode Indirect GBR addressing with displacement Instruction Format @(disp:8, GBR) Effective Address Calculation Equation The effective address is the GBR value plus an 8-bit displacement (disp). The value of disp is zero-extended, and remains the same for a byte operation, is doubled for a word operation, and is quadrupled for a longword operation. Byte: GBR + disp Word: GBR + disp x 2 Longword: GBR + disp x 4 GBR disp (zero-extended) + GBR + disp x 1/2/4 x 1/2/4 Indirect indexed GBR addressing @(R0, GBR) The effective address is the GBR value plus R0. GBR + R0 GBR + GBR + R0 R0 Word: PC + disp x 2 Indirect PC addressing @(disp:8, PC) The effective address is the PC value plus an 8-bit with displacement displacement (disp). The value of disp is zero-extended, Longword: PC & and is doubled for a word operation, and quadrupled for H'FFFFFFFC + disp x a longword operation. For a longword operation, the lowest 4 two bits of the PC value are masked. PC & H'FFFFFFFC (for longword) + disp (zero-extended) PC + disp x 2 or PC & H'FFFFFFFC + disp x 4 x 2/4 Rev. 5.00 Feb. 24, 2010 Page 33 of 950 REJ09B0177-0500 2. CPU Addressing Mode Instruction Format PC relative addressing disp:8 Effective Address Calculation Equation The effective address is the PC value sign-extended with PC + disp x 2 an 8-bit displacement (disp), doubled, and added to the PC value. PC disp (sign-extended) + PC + disp x 2 x 2 disp:12 The effective address is the PC value sign-extended with PC + disp x 2 a 12-bit displacement (disp), doubled, and added to the PC value. PC disp (sign-extended) + PC + disp x 2 x 2 Rn The effective address is the register PC value plus Rn. PC + Rn PC + PC + Rn Rn Immediate addressing #imm:8 The 8-bit immediate data (imm) for the TST, AND, OR, and XOR instructions is zero-extended. -- #imm:8 The 8-bit immediate data (imm) for the MOV, ADD, and CMP/EQ instructions is sign-extended. -- #imm:8 The 8-bit immediate data (imm) for the TRAPA instruction -- is zero-extended and quadrupled. Rev. 5.00 Feb. 24, 2010 Page 34 of 950 REJ09B0177-0500 2. CPU 2.3.3 Instruction Format Table 2.9 lists the instruction formats for the source operand and the destination operand. The meaning of the operand depends on the instruction code. The symbols used are as follows: * * * * * xxxx: Instruction code mmmm: Source register nnnn: Destination register iiii: Immediate data dddd: Displacement Table 2.9 Instruction Formats Instruction Formats 0 format 15 Source Operand Destination Operand Example -- -- NOP -- nnnn: Direct register MOVT Rn Control register or system register nnnn: Direct register STS MACH,Rn Control register or system register nnnn: Indirect predecrement register STC.L SR,@-Rn mmmm: Direct register Control register or system register LDC Rm,SR mmmm: Indirect postincrement register Control register or system register LDC.L @Rm+,SR mmmm: Direct register -- JMP mmmm: PC relative using Rm -- BRAF Rm mmmm: Direct register nnnn: Direct register ADD Rm,Rn mmmm: Direct register nnnn: Indirect register MOV.L Rm,@Rn mmmm: Indirect postincrement register (multiplyand-accumulate) nnnn*: Indirect postincrement register (multiplyand-accumulate) MACH, MACL MAC.W @Rm+,@Rn+ mmmm: Indirect postincrement register nnnn: Direct register MOV.L @Rm+,Rn mmmm: Direct register nnnn: Indirect predecrement register MOV.L Rm,@-Rn mmmm: Direct register nnnn: Indirect indexed register MOV.L Rm,@(R0,Rn) mmmmdddd: Indirect register with displacement R0 (Direct register) MOV.B @(disp,Rn),R0 0 xxxx xxxx xxxx xxxx n format 15 0 xxxx nnnn xxxx m format 15 xxxx mmmm xxxx xxxx 0 xxxx nm format 15 0 xxxx nnnn mmmm xxxx md format 15 0 xxxx @Rm xxxx mmmm dddd Rev. 5.00 Feb. 24, 2010 Page 35 of 950 REJ09B0177-0500 2. CPU Instruction Formats nd4 format 15 xxxx xxxx nnnn d12 format 15 xxxx dddd nd8 format 15 xxxx nnnn i format 15 xxxx ni format 15 xxxx nnnn Note: dddd dddd * nnnndddd: Indirect register with displacement MOV.B R0,@(disp,Rn) mmmm: Direct register nnnndddd: Indirect register with displacement MOV.L Rm,@(disp,Rn) mmmmdddd: Indirect register with displacement nnnn: Direct register MOV.L @(disp,Rm),Rn dddddddd: Indirect GBR with displacement R0 (Direct register) MOV.L @(disp,GBR),R0 R0 (Direct register) dddddddd: Indirect GBR with displacement MOV.L R0,@(disp,GBR) dddddddd: PC relative with displacement R0 (Direct register) MOVA @(disp,PC),R0 -- dddddddd: PC relative BF label -- dddddddddddd: PC relative BRA label (label = disp + PC) dddddddd: PC relative with displacement nnnn: Direct register MOV.L @(disp,PC),Rn iiiiiiii: Immediate Indirect indexed GBR AND.B #imm,@(R0,GBR) iiiiiiii: Immediate R0 (Direct register) AND #imm,R0 iiiiiiii: Immediate -- TRAPA #imm iiiiiiii: Immediate nnnn: Direct register ADD #imm,Rn 0 dddd 0 dddd iiii dddd iiii 0 iiii Example dddd 0 xxxx R0 (Direct register) dddd 0 xxxx Destination Operand 0 nmd format 15 0 xxxx nnnn mmmm dddd d format 15 xxxx Source Operand iiii In multiply-and-accumulate instructions, nnnn is the source register. Rev. 5.00 Feb. 24, 2010 Page 36 of 950 REJ09B0177-0500 2. CPU 2.4 Instruction Set by Classification 2.4.1 Instruction Set by Classification Table 2.10 lists the instructions according to their classification. Table 2.10 Classification of Instructions Classification Types Operation Code Function No. of Instructions Data transfer 5 MOV Data transfer, immediate data transfer, peripheral module data transfer, structure data transfer 39 MOVA Effective address transfer MOVT T bit transfer Arithmetic operations Logic operations 21 6 SWAP Swap of upper and lower bytes XTRCT Extraction of the middle of registers connected ADD Binary addition ADDC Binary addition with carry ADDV Binary addition with overflow check CMP/cond Comparison DIV1 Division DIV0S Initialization of signed division 33 DIV0U Initialization of unsigned division DMULS Signed double-length multiplication DMULU Unsigned double-length multiplication DT Decrement and test EXTS Sign extension EXTU Zero extension MAC Multiply-and-accumulate, double-length multiply-and-accumulate operation MUL Double-length multiply operation MULS Signed multiplication MULU Unsigned multiplication NEG Negation NEGC Negation with borrow SUB Binary subtraction SUBC Binary subtraction with borrow SUBV Binary subtraction with underflow AND Logical AND NOT Bit inversion OR Logical OR TAS Memory test and bit set TST Logical AND and T bit set XOR Exclusive OR 14 Rev. 5.00 Feb. 24, 2010 Page 37 of 950 REJ09B0177-0500 2. CPU Classification Types Operation Code Function No. of Instructions Shift 10 ROTL One-bit left rotation 14 ROTR One-bit right rotation ROTCL One-bit left rotation with T bit ROTCR One-bit right rotation with T bit SHAL One-bit arithmetic left shift SHAR One-bit arithmetic right shift SHLL One-bit logical left shift SHLLn n-bit logical left shift SHLR One-bit logical right shift Branch System control 9 11 SHLRn n-bit logical right shift BF Conditional branch, conditional branch with delay (Branch when T = 0) BT Conditional branch, conditional branch with delay (Branch when T = 1) BRA Unconditional branch BRAF Unconditional branch BSR Branch to subroutine procedure BSRF Branch to subroutine procedure JMP Unconditional branch JSR Branch to subroutine procedure RTS Return from subroutine procedure CLRT T bit clear CLRMAC MAC register clear LDC Load to control register LDS Load to system register NOP No operation RTE Return from exception processing SETT T bit set SLEEP Transition to power-down mode STC Store control register data STS Store system register data TRAPA Trap exception handling Rev. 5.00 Feb. 24, 2010 Page 38 of 950 REJ09B0177-0500 11 31 2. CPU Classification Types Operation Code Function No. of Instructions Floating-point instructions 15 FABS 22 FPU-related CPU instructions Total: 2 79 Floating-point absolute value FADD Floating-point addition FCMP Floating-point comparison FDIV Floating-point division FLDI0 Floating-point load immediate 0 FLDI1 Floating-point load immediate 1 FLDS Floating-point load into system register FPUL FLOAT Integer-to-floating-point conversion FMAC Floating-point multiply-and-accumulate operation FMOV Floating-point data transfer FMUL Floating-point multiplication FNEG Floating-point sign inversion FSTS Floating-point store from system register FPUL FSUB Floating-point subtraction FTRC Floating-point conversion with rounding to integer LDS Load into floating-point system register STS Store from floating-point system register 8 172 Rev. 5.00 Feb. 24, 2010 Page 39 of 950 REJ09B0177-0500 2. CPU Table 2.11 shows the format used in tables 2.12 to 2.19, which list instruction codes, operation, and execution states in order by classification. Table 2.11 Instruction Code Format Item Format Explanation Instruction OP.Sz SRC,DEST OP: Operation code Sz: Size (B: byte, W: word, or L: longword) SRC: Source DEST: Destination Rm: Source register Rn: Destination register imm: Immediate data disp: Displacement*1 Instruction code MSB LSB mmmm: Source register nnnn: Destination register 0000: R0 0001: R1 1111: R15 iiii: Immediate data dddd: Displacement Operation , Direction of transfer (xx) Memory operand M/Q/T Flag bits in the SR & Logical AND of each bit | Logical OR of each bit ^ Exclusive OR of each bit ~ Logical NOT of each bit <<n n-bit left shift >>n n-bit right shift Execution cycles -- Value when no wait states are inserted*2 T bit -- Value of T bit after instruction is executed. An em-dash (--) in the column means no change. Notes: 1. Depending on the operand size, displacement is scaled x1, x2, or x4. For details, see the SH-2E Software Manual. 2. Instruction execution cycles: The execution cycles shown in the table are minimums. The actual number of cycles may be increased when (1) contention occurs between instruction fetches and data access, or (2) when the destination register of the load instruction (memory register) and the register used by the next instruction are the same. Rev. 5.00 Feb. 24, 2010 Page 40 of 950 REJ09B0177-0500 2. CPU Table 2.12 Data Transfer Instructions Execution Cycles T Bit Instruction Instruction Code Operation MOV #imm,Rn 1110nnnniiiiiiii #imm Sign extension Rn 1 -- MOV.W @(disp,PC),Rn 1001nnnndddddddd (disp x 2 + PC) Sign extension Rn 1 -- MOV.L @(disp,PC),Rn 1101nnnndddddddd (disp x 4 + PC) Rn 1 -- MOV 0110nnnnmmmm0011 Rm Rn 1 -- MOV.B Rm,@Rn 0010nnnnmmmm0000 Rm (Rn) 1 -- MOV.W Rm,@Rn 0010nnnnmmmm0001 Rm (Rn) 1 -- MOV.L Rm,@Rn 0010nnnnmmmm0010 Rm (Rn) 1 -- MOV.B @Rm,Rn 0110nnnnmmmm0000 (Rm) Sign extension Rn 1 -- MOV.W @Rm,Rn 0110nnnnmmmm0001 (Rm) Sign extension Rn 1 -- MOV.L @Rm,Rn 0110nnnnmmmm0010 (Rm) Rn 1 -- MOV.B Rm,@-Rn 0010nnnnmmmm0100 Rn-1 Rn, Rm (Rn) 1 -- MOV.W Rm,@-Rn 0010nnnnmmmm0101 Rn-2 Rn, Rm (Rn) 1 -- MOV.L Rm,@-Rn 0010nnnnmmmm0110 Rn-4 Rn, Rm (Rn) 1 -- MOV.B @Rm+,Rn 0110nnnnmmmm0100 (Rm) Sign extension Rn,Rm + 1 Rm 1 -- MOV.W @Rm+,Rn 0110nnnnmmmm0101 (Rm) Sign extension Rn,Rm + 2 Rm 1 -- MOV.L @Rm+,Rn 0110nnnnmmmm0110 (Rm) Rn,Rm + 4 Rm 1 -- MOV.B R0,@(disp,Rn) 10000000nnnndddd R0 (disp + Rn) 1 -- MOV.W R0,@(disp,Rn) 10000001nnnndddd R0 (disp x 2 + Rn) 1 -- MOV.L Rm,@(disp,Rn) 0001nnnnmmmmdddd Rm (disp x 4 + Rn) 1 -- MOV.B @(disp,Rm),R0 10000100mmmmdddd (disp + Rm) Sign extension 1 R0 -- MOV.W @(disp,Rm),R0 10000101mmmmdddd (disp x 2 + Rm) Sign extension R0 1 -- MOV.L @(disp,Rm),Rn 0101nnnnmmmmdddd (disp x 4 + Rm) Rn 1 -- MOV.B Rm,@(R0,Rn) 0000nnnnmmmm0100 Rm (R0 + Rn) 1 -- MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101 Rm (R0 + Rn) 1 -- MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110 Rm (R0 + Rn) 1 -- MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100 (R0 + Rm) Sign extension 1 Rn -- MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101 (R0 + Rm) Sign extension 1 Rn -- MOV.L @(R0,Rm),Rn 0000nnnnmmmm1110 (R0 + Rm) Rn 1 -- MOV.B R0,@(disp,GBR) 11000000dddddddd R0 (disp + GBR) 1 -- MOV.W R0,@(disp,GBR) 11000001dddddddd R0 (disp x 2 + GBR) 1 -- MOV.L R0,@(disp,GBR) 11000010dddddddd R0 (disp x 4 + GBR) 1 -- MOV.B @(disp,GBR),R0 11000100dddddddd (disp + GBR) Sign extension R0 1 -- Rm,Rn Rev. 5.00 Feb. 24, 2010 Page 41 of 950 REJ09B0177-0500 2. CPU Execution Cycles T Bit Instruction Instruction Code Operation MOV.W @(disp,GBR),R0 11000101dddddddd (disp x 2 + GBR) Sign extension R0 1 -- MOV.L @(disp,GBR),R0 11000110dddddddd (disp x 4 + GBR) R0 1 -- MOVA @(disp,PC),R0 11000111dddddddd disp x 4 + PC R0 1 -- MOVT Rn 0000nnnn00101001 T Rn 1 -- SWAP.B Rm,Rn 0110nnnnmmmm1000 Rm Swap bottom two bytes Rn 1 -- SWAP.W Rm,Rn 0110nnnnmmmm1001 Rm Swap two consecutive words Rn 1 -- XTRCT 0010nnnnmmmm1101 Rm: Middle 32 bits of Rn Rn 1 -- Rm,Rn Rev. 5.00 Feb. 24, 2010 Page 42 of 950 REJ09B0177-0500 2. CPU Table 2.13 Arithmetic Operation Instructions Instruction Instruction Code Operation Execution Cycles ADD Rm,Rn 0011nnnnmmmm1100 Rn + Rm Rn 1 ADD #imm,Rn 0111nnnniiiiiiii Rn + imm Rn 1 -- ADDC Rm,Rn 0011nnnnmmmm1110 Rn + Rm + T Rn, Carry T 1 Carry ADDV Rm,Rn 0011nnnnmmmm1111 Rn + Rm Rn, Overflow T 1 Overflow CMP/EQ #imm,R0 10001000iiiiiiii If R0 = imm, 1 T 1 Comparison result CMP/EQ Rm,Rn 0011nnnnmmmm0000 If Rn = Rm, 1 T 1 Comparison result CMP/HS Rm,Rn 0011nnnnmmmm0010 If Rn=Rm with unsigned data, 1 T 1 Comparison result CMP/GE Rm,Rn 0011nnnnmmmm0011 If Rn = Rm with signed data, 1 T 1 Comparison result CMP/HI Rm,Rn 0011nnnnmmmm0110 If Rn > Rm with unsigned data, 1 T 1 Comparison result CMP/GT Rm,Rn 0011nnnnmmmm0111 If Rn > Rm with signed data, 1 T 1 Comparison result CMP/PL Rn 0100nnnn00010101 If Rn > 0, 1 T 1 Comparison result CMP/PZ Rn 0100nnnn00010001 If Rn = 0, 1 T 1 Comparison result CMP/STR Rm,Rn 0010nnnnmmmm1100 If Rn and Rm have an equivalent byte, 1T 1 Comparison result DIV1 Rm,Rn 0011nnnnmmmm0100 Single-step division (Rn / Rm) 1 Calculation result DIV0S Rm,Rn 0010nnnnmmmm0111 MSB of Rn Q, MSB of Rm M, M ^ Q T 1 Calculation result DIV0U 0000000000011001 0 M/Q/T 1 0 DMULS.L Rm,Rn 0011nnnnmmmm1101 Signed operation of Rn x Rm MACH, MACL 32 x 32 64 bits 2 to 4* -- DMULU.L Rm,Rn 0011nnnnmmmm0101 Unsigned operation of Rn x Rm MACH, MACL 32 x 32 64 bits 2 to 4* -- DT 0100nnnn00010000 Rn - 1 Rn, when Rn is 0, 1 T. When Rn is nonzero, 0 T 1 Comparison result EXTS.B Rm,Rn 0110nnnnmmmm1110 Byte in Rm is sign-extended Rn 1 -- EXTS.W Rm,Rn 0110nnnnmmmm1111 Word in Rm is sign-extended Rn 1 -- EXTU.B Rm,Rn 0110nnnnmmmm1100 Byte in Rm is zero-extended Rn 1 -- EXTU.W Rm,Rn 0110nnnnmmmm1101 Word in Rm is zero-extended Rn 1 -- Rn T Bit -- MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111 Signed operation of 3/ -- (Rn) x (Rm) + MAC MAC 32 x 32 + 64 (2 to 4)* 64 bits MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111 Signed operation of 3/(2)* (Rn) x (Rm) + MAC MAC 16 x 16 + 64 64 bits -- MUL.L Rm,Rn 0000nnnnmmmm0111 Rn x Rm MACL, 32 x 32 32 bits 2 to 4* -- MULS.W Rm,Rn 0010nnnnmmmm1111 Signed operation of Rn x Rm MACL 16 x 16 32 bits 1 to 3* -- Rev. 5.00 Feb. 24, 2010 Page 43 of 950 REJ09B0177-0500 2. CPU Execution Cycles T Bit Instruction Instruction Code Operation MULU.W Rm,Rn 0010nnnnmmmm1110 Unsigned operation of Rn x Rm MACL 16 x 16 32 bits 1 to 3* -- NEG Rm,Rn 0110nnnnmmmm1011 0 - Rm Rn 1 -- NEGC Rm,Rn 0110nnnnmmmm1010 0 - Rm - T Rn, Borrow T 1 Borrow SUB Rm,Rn 0011nnnnmmmm1000 Rn - Rm Rn 1 -- SUBC Rm,Rn 0011nnnnmmmm1010 Rn - Rm - T Rn, Borrow T 1 Borrow SUBV Rm,Rn 0011nnnnmmmm1011 Rn - Rm Rn, Underflow T 1 Overflow Note: * The normal minimum number of execution cycles. (The number in parentheses is the number of cycles when there is contention with following instructions.) Table 2.14 Logic Operation Instructions Instruction Instruction Code Operation Execution Cycles AND Rm,Rn 0010nnnnmmmm1001 Rn & Rm Rn 1 -- AND #imm,R0 11001001iiiiiiii R0 & imm R0 1 -- AND.B #imm,@(R0,GBR) 11001101iiiiiiii (R0 + GBR) & imm (R0 + GBR) 3 -- NOT Rm,Rn 0110nnnnmmmm0111 ~Rm Rn 1 -- OR Rm,Rn 0010nnnnmmmm1011 Rn | Rm Rn 1 -- OR #imm,R0 11001011iiiiiiii R0 | imm R0 1 -- OR.B #imm,@(R0,GBR) 11001111iiiiiiii (R0 + GBR) | imm (R0 + GBR) 3 -- 4 Test result T Bit TAS.B @Rn 0100nnnn00011011 If (Rn) is 0, 1 T; 1 MSB of (Rn) TST Rm,Rn 0010nnnnmmmm1000 Rn & Rm; if the result is 0, 1 T 1 Test result TST #imm,R0 11001000iiiiiiii R0 & imm; if the result is 0, 1 T 1 Test result TST.B #imm,@(R0,GBR) 11001100iiiiiiii (R0 + GBR) & imm; if the result is 0, 1 T 3 Test result XOR Rm,Rn 0010nnnnmmmm1010 Rn ^ Rm Rn 1 -- XOR #imm,R0 11001010iiiiiiii R0 ^ imm R0 1 -- (R0 + GBR) ^ imm (R0 + GBR) 3 -- XOR.B #imm,@(R0,GBR) 11001110iiiiiiii Rev. 5.00 Feb. 24, 2010 Page 44 of 950 REJ09B0177-0500 2. CPU Table 2.15 Shift Instructions Instruction Instruction Code Operation Execution Cycles ROTL Rn 0100nnnn00000100 T Rn MSB 1 MSB ROTR Rn 0100nnnn00000101 LSB Rn T 1 LSB ROTCL Rn 0100nnnn00100100 T Rn T 1 MSB ROTCR Rn 0100nnnn00100101 T Rn T 1 LSB SHAL Rn 0100nnnn00100000 T Rn 0 1 MSB SHAR Rn 0100nnnn00100001 MSB Rn T 1 LSB SHLL Rn 0100nnnn00000000 T Rn 0 1 MSB SHLR Rn 0100nnnn00000001 0 Rn T 1 LSB SHLL2 Rn 0100nnnn00001000 Rn<<2 Rn 1 -- SHLR2 Rn 0100nnnn00001001 Rn>>2 Rn 1 -- SHLL8 Rn 0100nnnn00011000 Rn<<8 Rn 1 -- SHLR8 Rn 0100nnnn00011001 Rn>>8 Rn 1 -- SHLL16 Rn 0100nnnn00101000 Rn<<16 Rn 1 -- SHLR16 Rn 0100nnnn00101001 Rn>>16 Rn 1 -- Execution Cycles T Bit T Bit Table 2.16 Branch Instructions Instruction Instruction Code Operation BF label 10001011dddddddd If T = 0, disp x 2 + PC PC; if T = 1, nop 3/1* -- BF/S label 10001111dddddddd Delayed branch, if T = 0, disp x 2 + PC PC; if T = 1, nop 3/1* -- BT label 10001001dddddddd If T = 1, disp x 2 + PC PC; if T = 0, nop 3/1* -- BT/S label 10001101dddddddd Delayed branch, if T = 1, disp x 2 + PC PC; if T = 0, nop 2/1* -- BRA 1010dddddddddddd Delayed branch, disp x 2 + PC PC 2 -- BRAF Rm 0000mmmm00100011 Delayed branch, Rm + PC PC 2 -- BSR 1011dddddddddddd Delayed branch, PC PR, disp x 2 + PC PC 2 -- BSRF Rm 0000mmmm00000011 Delayed branch, PC PR, Rm + PC PC 2 -- JMP @Rm 0100mmmm00101011 Delayed branch, Rm PC 2 -- JSR @Rm 0100mmmm00001011 Delayed branch, PC PR, Rm PC 2 -- 0000000000001011 Delayed branch, PR PC 2 -- label label RTS Note: * One state when the program does not branch. Rev. 5.00 Feb. 24, 2010 Page 45 of 950 REJ09B0177-0500 2. CPU Table 2.17 System Control Instructions Instruction Instruction Code Operation Execution Cycles CLRT 0000000000001000 0T 1 CLRMAC 0000000000101000 0 MACH, MACL 1 -- LDC Rm,SR 0100mmmm00001110 Rm SR 1 LSB LDC Rm,GBR 0100mmmm00011110 Rm GBR 1 -- LDC Rm,VBR 0100mmmm00101110 Rm VBR 1 -- LDC.L @Rm+,SR 0100mmmm00000111 (Rm) SR, Rm + 4 Rm 3 LSB LDC.L @Rm+,GBR 0100mmmm00010111 (Rm) GBR, Rm + 4 Rm 3 -- LDC.L @Rm+,VBR 0100mmmm00100111 (Rm) VBR, Rm + 4 Rm 3 -- LDS Rm,MACH 0100mmmm00001010 Rm MACH 1 -- LDS Rm,MACL 0100mmmm00011010 Rm MACL 1 -- LDS Rm,PR 0100mmmm00101010 Rm PR 1 -- LDS.L @Rm+,MACH 0100mmmm00000110 (Rm) MACH, Rm + 4 Rm 1 -- LDS.L @Rm+,MACL 0100mmmm00010110 (Rm) MACL, Rm + 4 Rm 1 -- LDS.L @Rm+,PR 0100mmmm00100110 (Rm) PR, Rm + 4 Rm 1 -- NOP 0000000000001001 No operation 1 -- RTE 0000000000101011 Delayed branch, stack area PC/SR 4 -- SETT 0000000000011000 1T 1 1 SLEEP 0000000000011011 Sleep 3* -- T Bit 0 STC SR,Rn 0000nnnn00000010 SR Rn 1 -- STC GBR,Rn 0000nnnn00010010 GBR Rn 1 -- STC VBR,Rn 0000nnnn00100010 VBR Rn 1 -- STC.L SR,@-Rn 0100nnnn00000011 Rn - 4 Rn, SR (Rn) 2 -- STC.L GBR,@-Rn 0100nnnn00010011 Rn - 4 Rn, GBR (Rn) 2 -- STC.L VBR,@-Rn 0100nnnn00100011 Rn - 4 Rn, BR (Rn) 2 -- STS MACH,Rn 0000nnnn00001010 MACH Rn 1 -- STS MACL,Rn 0000nnnn00011010 MACL Rn 1 -- STS PR,Rn 0000nnnn00101010 PR Rn 1 -- STS.L MACH,@-Rn 0100nnnn00000010 Rn - 4 Rn, MACH (Rn) 1 -- STS.L MACL,@-Rn 0100nnnn00010010 Rn - 4 Rn, MACL (Rn) 1 -- STS.L PR,@-Rn 0100nnnn00100010 Rn - 4 Rn, PR (Rn) 1 -- TRAPA #imm 11000011iiiiiiii PC/SR stack area, (imm x 4 + VBR) PC 8 -- Note: * The number of execution cycles before the chip enters sleep mode: The execution cycles shown in the table are minimums. The actual number of cycles may be increased when (1) contention occurs between instruction fetches and data access, or (2) when the destination register of the load instruction (memory register) and the register used by the next instruction are the same. Rev. 5.00 Feb. 24, 2010 Page 46 of 950 REJ09B0177-0500 2. CPU Table 2.18 Floating-Point Instructions Instruction Instruction Code Operation Execution Cycles FABS FRn 1111nnnn01011101 |FRn| FRn 1 -- FADD T Bit FRm,FRn 1111nnnnmmmm0000 FRn + FRm FRn 1 -- FCMP/EQ FRm,FRn 1111nnnnmmmm0100 (FRn = FRm)? 1:0 T 1 Comparison result FCMP/GT FRm,FRn 1111nnnnmmmm0101 (FRn > FRm)? 1:0 T 1 Comparison result FDIV FRm,FRn 1111nnnnmmmm0011 FRn/FRm FRn 13 -- FLDI0 FRn 1111nnnn10001101 0x00000000 FRn 1 -- FLDI1 FRn 1111nnnn10011101 0x3F800000 FRn 1 -- FLDS FRm,FPUL 1111mmmm00011101 FRm FPUL 1 -- FLOAT FPUL,FRn 1111nnnn00101101 (float) FPUL FRn 1 -- FMAC FR0,FRm,FRn 1111nnnnmmmm1110 FR0 x FRm + FRn FRn 1 -- FMOV FRm, FRn 1111nnnnmmmm1100 FRm FRn 1 -- FMOV.S @(R0,Rm),FRn 1111nnnnmmmm0110 (R0 + Rm) FRn 1 -- FMOV.S @Rm+,FRn 1111nnnnmmmm1001 (Rm) FRn, Rm+ = 4 1 -- FMOV.S @Rm,FRn 1111nnnnmmmm1000 (Rm) FRn 1 -- FMOV.S FRm,@(R0,Rn) 1111nnnnmmmm0111 FRm (R0 + Rn) 1 -- FMOV.S FRm,@-Rn 1111nnnnmmmm1011 Rn- = 4, FRm (Rn) 1 -- FMOV.S FRm,@Rn 1111nnnnmmmm1010 FRm (Rn) 1 -- FMUL FRm,FRn 1111nnnnmmmm0010 FRn x FRm FRn 1 -- FNEG FRn 1111nnnn01001101 -FRn FRn 1 -- FSTS FPUL,FRn 1111nnnn00001101 FPUL FRn 1 -- FSUB FRm,FRn 1111nnnnmmmm0001 FRn - FRm FRn 1 -- FTRC FRm,FPUL 1111mmmm00111101 (long) FRm FPUL 1 -- T Bit Table 2.19 FPU-Related CPU Instructions Instruction Instruction Code Operation Execution Cycles LDS Rm,FPSCR 0100mmmm01101010 Rm FPSCR 1 -- LDS Rm,FPUL 0100mmmm01011010 Rm FPUL 1 -- LDS.L @Rm+, FPSCR 0100mmmm01100110 @Rm FPSCR, Rm+ = 4 1 -- LDS.L @Rm+, FPUL 0100mmmm01010110 @Rm FPUL, Rm+ = 4 1 -- STS FPSCR, Rn 0000nnnn01101010 FPSCR Rn 1 -- STS FPUL,Rn 0000nnnn01011010 FPUL Rn 1 -- STS.L FPSCR,@-Rn 0100nnnn01100010 Rn- = 4, FPCSR @Rn 1 -- STS.L FPUL,@-Rn 0100nnnn01010010 Rn- = 4, FPUL @Rn 1 -- Rev. 5.00 Feb. 24, 2010 Page 47 of 950 REJ09B0177-0500 2. CPU 2.5 Processing States 2.5.1 State Transitions The CPU has five processing states: power-on reset, exception processing, bus release, program execution and powerdown. Figure 2.8 shows the transitions between the states. From any state when RES = 0 and HSTBY = 1 Power-on reset state RES = 0 HSTBY = 1 NMI pin 0 1 RES = 1 When an interrupt source or DMA address error occurs Exception processing state Bus request cleared Bus request generated Exception processing source occurs Bus release state Bus request generated Bus request generated Exception processing ends Bus request cleared Bus request cleared Program execution state SBY bit cleared for SLEEP instruction SBY bit set for SLEEP instruction Sleep mode Software standby mode Hardware standby mode Power-down state From any state when RES = 0 and HSTBY = 0 Note: An internal reset due to the WDT causes a transition from the program execution state or sleep mode to the exception processing state. Figure 2.8 Transitions between Processing States Rev. 5.00 Feb. 24, 2010 Page 48 of 950 REJ09B0177-0500 2. CPU Power-On Reset State: The CPU resets in the reset state. When the HSTBY pin is driven high and the RES pin level goes low, the power-on reset state is entered. Exception Processing State: The exception processing state is a transient state that occurs when exception processing sources such as resets or interrupts alter the CPU's processing state flow. For a reset, the initial values of the program counter (PC) (execution start address) and stack pointer (SP) are fetched from the exception processing vector table and stored; the CPU then branches to the execution start address and execution of the program begins. For an interrupt, the stack pointer (SP) is accessed and the program counter (PC) and status register (SR) are saved to the stack area. The exception service routine start address is fetched from the exception processing vector table; the CPU then branches to that address and the program starts executing, thereby entering the program execution state. Program Execution State: In the program execution state, the CPU sequentially executes the program. Power-Down State: In the power-down state, the CPU operation halts and power consumption declines. The SLEEP instruction places the CPU in the sleep mode or the software standby mode. If the HSTBY pin is driven low when the RES pin is low, the CPU will enter the hardware standby mode. Bus Release State: In the bus release state, the CPU releases access rights to the bus to the device that has requested them. Rev. 5.00 Feb. 24, 2010 Page 49 of 950 REJ09B0177-0500 2. CPU Rev. 5.00 Feb. 24, 2010 Page 50 of 950 REJ09B0177-0500 3. Floating-Point Unit (FPU) Section 3 Floating-Point Unit (FPU) 3.1 Overview This LSI has an on-chip floating-point unit (FPU), The FPU's register configuration is shown in figure 3.1. Floating-point registers 31 0 FR0 functions as the index register for the FMAC instruction. FR0 FR1 FR2 FR3 FR4 FR5 FR6 FR7 FR8 FR9 FR10 FR11 FR12 FR13 FR14 FR15 Floating-point system registers 31 0 Floating-point communication register Specifies buffer as communication register between CPU and FPU*. 0 Floating-point status/control register Indicates status/control information relating to FPU exceptions*. FPUL 31 FPSCR Note: * For details, see section 3.2, Floating-Point Registers and Floating-Point System Registers. Figure 3.1 Overview of Register Configuration (Floating-Point Registers and Floating-Point System Registers) 3.2 Floating-Point Registers and Floating-Point System Registers 3.2.1 Floating-Point Register File This LSI has sixteen 32-bit single-precision floating-point registers. Register specifications are always made as 4 bits. In assembly language, the floating-point registers are specified as FR0, FR1, FR2, and so on. FR0 functions as the index register for the FMAC instruction. 3.2.2 Floating-Point Communication Register (FPUL) Information for transfer between the FPU and the CPU is transferred via the FPUL communication register, which resembles MACL and MACH in the integer unit. This LSI is provided with this communication register since the integer and floating-point formats are different. The 32-bit FPUL is a system register, and is accessed by the CPU by means of LDS and STS instructions. Rev. 5.00 Feb. 24, 2010 Page 51 of 950 REJ09B0177-0500 3. Floating-Point Unit (FPU) 3.2.3 Floating-Point Status/Control Register (FPSCR) This LSI has a floating-point status/control register (FPSCR) that functions as a system register accessed by means of LDS and STS instructions (figure 3.2). FPSCR can be written to by a user program. This register is part of the process context, and must be saved when the context is switched. It may also be necessary to save this register when a procedure call is made. FPSCR is a 32-bit register that controls the storage of detailed information relating to the rounding mode, asymptotic underflow (denormalized numbers), and FPU exceptions. The module stop bit that disables the FPU itself is provided in the module standby control register (MSTCR). For details, see section 27, Power-Down State. After a reset start, the FPU is enabled. Table 3.1 shows the flags corresponding the five kinds of FPU exception. A sixth flag is also provided as an FPU error flag that indicates an floating-point unit error state not covered by the other five flags. Table 3.1 Floating-Point Exception Flags Flag Meaning Support in this LSI E FPU error -- V Invalid operation Yes Z Division by zero Yes O Overflow (value not expressed) -- U Underflow (value not expressed) -- I Inexact (result not expressed) -- The bits in the cause field indicate the exception cause for the instruction executing at the time. The cause bits are modified by a floating-point instruction. These bits are set to 1 or cleared to 0 according to whether or not an exception state occurred during execution of a single instruction. The bits in the enable field specify the kinds of exception to be enabled, allowing the flow to be changed to exception processing. If the cause bit corresponding to an enable bit is set by the currently executing instruction, an exception occurs. The bits in the flag field are used to keep a tally of all exceptions that occur during a series of instructions. Once one of these bits is set by an instruction, it is not reset by a subsequent instruction. The bits in this field can only be reset by the explicit execution of a store operation on FPSCR. Rev. 5.00 Feb. 24, 2010 Page 52 of 950 REJ09B0177-0500 3. Floating-Point Unit (FPU) 31 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Cause field Reserved Enable field Flag field DN CE CV CZ CO CU CI EV EZ EO EU EI FV FZ FO FU FI RM Legend: DN: Denormalized bit In this LSI, this bit is always set to 1, and the source or destination operand of a denormalized number is 0. This bit cannot be modified even by an LDS instruction. CV: Invalid operation cause bit When 1: Indicates that an invalid operation exception occurred during execution of the current instruction. When 0: Indicates that an invalid operation exception has not occurred. CZ: Division-by-zero cause bit When 1: Indicates that a division-by-zero exception occurred during execution of the current instruction. When 0: Indicates that a division-by-zero exception has not occurred. EV: Invalid operation exception enable When 1: Enables invalid operation exception generation. When 0: An invalid operation exception is not generated, and a qNAN is returned as the result. EZ: Division-by-zero exception enable When 1: Enables exception generation due to division-by-zero during execution of the current instruction. When 0: A division-by-zero exception is not generated, and infinity with the sign (+ or -) of the current expression is returned as the result. FV: Invalid operation exception flag bit When 1: Indicates that an invalid operation exception occurred during instruction execution. When 0: Indicates that an invalid operation exception has not occurred. FZ: Division-by-zero exception flag bit When 1: Indicates that a division-by-zero exception occurred during instruction execution. When 0: Indicates that a division-by-zero exception has not occurred. RM: Rounding bit. In this LSI, the value of these bits is always 01, meaning that rounding to zero (RZ mode) is being used. These bits cannot be modified even by an LDS instruction. Note: In this LSI, the cause field EOUI bits (CE, CO, CU, and CI), enable field OUI bits (EO, EU, and EI), and flag field OUI bits (FO, FU, and FI), and the reserved area, are preset to 0, and cannot be modified even by using an LDS instruction. Figure 3.2 Floating-Point Status/Control Register Rev. 5.00 Feb. 24, 2010 Page 53 of 950 REJ09B0177-0500 3. Floating-Point Unit (FPU) 3.3 Floating-Point Format 3.3.1 Floating-Point Format This LSI supports single-precision floating-point operations, and fully complies with the IEEE754 floating-point standard. A floating-point number consists of the following three fields: * Sign (s) * Exponent (e) * Fraction (f) The exponent is expressed in biased form, as follows: e = E + bias The range of unbiased exponent E is Emin - 1 to Emax + 1. The two values Emin - 1 and Emax + 1 are distinguished as follows. Emin - 1 indicates zero (both positive and negative sign) and a denormalized number, and Emax + 1 indicates positive or negative infinity or a non-number (NaN). In a single-precision operation, the bias value is 127, Emin is -126, and Emax is 127. 31 30 23 22 s e 0 f Figure 3.3 Floating-Point Number Format Floating-point number value v is determined as follows: If E = Emax + 1 and f! = 0, v is a non-number (NaN) irrespective of sign s If E = Emax + 1 and f = 0, v = (-1)s (infinity) [positive or negative infinity] If Emin <= E <= Emax , v = (-1)s2E (1.f) [normalized number] If E = Emin - 1 and f! = 0, v = (-1)s2Emin (0.f) [denormalized number] If E = Emin - 1 and f = 0, v = (-1)s0 [positive or negative zero] 3.3.2 Non-Numbers (NaN) With non-number (NaN) representation in a single-precision operation value, at least one of bits 22 to 0 is set. If bit 22 is set, this indicates a signaling NaN (sNaN). If bit 22 is reset, the value is a quiet NaN (qNaN). The bit pattern of a non-number (NaN) is shown in the figure below. Bit N in the figure is set for a signaling NaN and reset for a quiet NaN. x indicates a don't care bit (with the proviso that at least one of bits 22 to 0 is set). In a non-number (NaN), the sign bit is a don't care bit. 31 30 x 23 22 11111111 0 Nxxxxxxxxxxxxxxxxxxxxxx Note: N = 1: sNaN N = 0: qNaN Figure 3.4 NaN Bit Pattern Rev. 5.00 Feb. 24, 2010 Page 54 of 950 REJ09B0177-0500 3. Floating-Point Unit (FPU) If a non-number (sNaN) is input in an operation that generates a floating-point value: * When the EV bit in the FPSCR register is reset, the operation result (output) is a quiet NaN (qNaN). * When the EV bit in the FPSCR register is set, an invalid operation exception will be generated. In this case, the contents of the operation destination register do not change. If a quiet NaN is input in an operation that generates a floating-point value, and a signaling NaN has not been input in that operation, the output will always be a quiet NaN irrespective of the setting of the EV bit in the FPSCR register. An exception will not be generated in this case. Refer to the SH-2E Software Manual for details of floating-point operations when a non-number (NaN) is input. 3.3.3 Denormalized Number Values For a denormalized number floating-point value, the biased exponent is expressed as 0, the fraction as a non-zero value, and the hidden bit as 0. In this LSI's floating-point unit, a denormalized number (operand source or operation result) is always flushed to 0 in a floating-point operation that generates a value (an operation other than copy). 3.3.4 Other Special Values Floating-point value representations include the seven different kinds of special values shown in table 3.2. Table 3.2 Representation of Special Values in Single-Precision Floating-Point Operations Specified by IEEE754 Standard Value Representation +0.0 0x00000000 -0.0 0x80000000 Denormalized number As described in section 3.3.3, Denormalized Number Values +INF 0x7F800000 -INF 0xFF800000 qNaN (quiet NaN) As described in section 3.3.2, Non-Numbers (NaN) sNaN (signaling NaN) As described in section 3.3.2, Non-Numbers (NaN) 3.4 Floating-Point Exception Model 3.4.1 Enable State Exceptions Invalid operation and division-by-zero exceptions are both placed in the enable state by setting the enable bit. All exceptions generated by the FPU are mapped as the same exception event. The meaning of a particular exception is determined by software by reading system register FPSCR and analyzing the information held there. 3.4.2 Disable State Exceptions If the EV enable bit is not set, a qNaN will be generated as the result of an invalid operation (except for FCMP and FTRC). If the EZ enable bit is not set, division-by-zero will return infinity with the sign (+ or -) of the current expression. Overflow will generate a finite number which is the largest value that can be expressed by an absolute value in the format, with the correct sign. Underflow will generate zero with the correct sign. If the operation result is inexact, the destination register will store that inexact result. Rev. 5.00 Feb. 24, 2010 Page 55 of 950 REJ09B0177-0500 3. Floating-Point Unit (FPU) 3.4.3 FPU Exception Event and Code All FPU exceptions have a vector table address offset in address H'00000034 as the same general exception event; that is, an FPU exception. 3.4.4 Floating-Point Data Arrangement in Memory Single-precision floating-point data is located in memory at a 4-byte boundary; that is, it is arranged in the same form as this LSI long integer. 3.4.5 Arithmetic Operations Involving Special Operands All arithmetic operations involving special operands (qNaN, sNaN, +INF, -INF, +0, -0) comply with the specifications of the IEEE754 standard. Refer to the SH-2E Software Manual for details. 3.5 Synchronization with CPU Synchronization with CPU: Floating-point instructions and CPU instructions are executed in turn, according to their order in the program, but in some cases operations may not be completed in the program order due to a difference in execution cycles. When a floating-point instruction accesses only FPU resources, there is no need for synchronization with the CPU, and a CPU instruction following an FPU instruction can finish its operation before completion of the FPU operation. Consequently, in an optimized program, it is possible to effectively conceal the execution cycle of a floatingpoint instruction that requires a long execution cycle, such as a divide instruction. On the other hand, a floating-point instruction that accesses CPU resources, such as a compare instruction, must be synchronized to ensure that the program order is observed. Floating-Point Instructions That Require Synchronization: Load, store, and compare instructions, and instructions that access the FPUL or FPSCR register, must be synchronized because they access CPU resources. Load and store instructions access a general register. Post-increment load and pre-decrement store instructions change the contents of a general register. A compare instruction modifies the T bit. An FPUL or FPSCR access instruction references or changes the contents of the FPUL or FPSCR register. These references and changes must all be synchronized with the CPU. 3.6 Usage Notes Of the arithmetic operations that come up with special operand in this FPU, the following two patterns generate values whose sign is different from that defined in IEEE754 Standard. (1) FADD FRm, FRn FRm = -INF (0xFF800000) FRn = MAX (0x7F7FFFFF) In this case, although the expectation value in IEEE754 is -INF (0xFF800000), the result is +INF (0xFF800000). (2) FSUB FRm, FRn FRm = +INF (0x7F800000) FRn = MAX (0x7F7FFFFF) In this case, although the expectation value in IEEE754 is -INF (0xFF800000), the result is +INF (0x7F800000). Rev. 5.00 Feb. 24, 2010 Page 56 of 950 REJ09B0177-0500 4. Operating Modes Section 4 Operating Modes 4.1 Operating Mode Selection This LSI has five operating modes that are selected by pins MD2 to MD0 and FWE. The mode setting pins should not be changed during operation of this LSI, and only the setting combinations shown in table 4.1 should be used. The PVCC1 power supply voltage must be within the range shown in table 4.1. Table 4.1 Operating Mode Selection Operating Mode No. FWE Pin Settings MD2 MD1 MD0 Mode Name On-Chip ROM Area 0 Bus Width PVCC1 Voltage Mode 0 0 1 0 0 MCU expanded mode Disabled 8 bits 3.3 V 0.3 V Mode 1 0 1 0 1 Mode 2 0 1 1 0 Mode 3 0 1 1 1 Mode 4 1 1 0 0 Mode 5 1 1 0 1 Mode 6 1 1 1 0 Mode 7 1 1 1 1 Mode 8 1 0 0 0 Mode 9 1 0 0 1 -- 0/1 0 1 1 16 bits Enabled Set by BCR1 MCU single-chip mode Enabled -- 5.0 V 0.5 V Boot mode Enabled Set by BCR1 3.3 V 0.3 V -- 5.0 V 0.5 V Set by BCR1 3.3 V 0.3 V -- 5.0 V 0.5 V Set by BCR1 3.3 V 0.3 V -- 5.0 V 0.5 V -- 3.3 V 0.3 V User program mode Enabled User boot mode Enabled Programmer mode -- There are two MCU operating modes: MCU single-chip mode and MCU expanded mode. Modes in which the flash memory can be programmed are boot mode, user boot mode and user program mode (the two on-board programming modes) and programmer mode in which programming is performed with an EPROM programmer (a type which supports programming of this device). For details, see section 24, ROM (SH7058S) and section 25, ROM (SH7059). Rev. 5.00 Feb. 24, 2010 Page 57 of 950 REJ09B0177-0500 4. Operating Modes Rev. 5.00 Feb. 24, 2010 Page 58 of 950 REJ09B0177-0500 5. Clock Pulse Generator (CPG) Section 5 Clock Pulse Generator (CPG) 5.1 Overview The clock pulse generator (CPG) supplies clock pulses inside this LSI chip and to external devices. This LSI CPG consists of an oscillator circuit and a PLL multiplier circuit. There are two methods of generating a clock with the CPG: by connecting a crystal resonator, or by inputting an external clock. The oscillator circuit oscillates at the same frequency as the input clock. Two types of clock signals, internal clock () and peripheral clock (P) signals, are supplied and used by this LSI. The internal clock signal (), with frequency eight times the frequency of the clock signal input from the EXTAL pin, is mainly supplied to the bus master modules. The peripheral clock signal (P), with frequency two times the frequency of the clock signal input from the EXTAL pin, is mainly supplied to the on-chip peripheral modules. The CK pin outputs the peripheral clock signal (P). The CPG is halted in software standby mode and hardware standby mode. 5.1.1 Block Diagram A block diagram of the clock pulse generator is shown in figure 5.1. CPG EXTAL Oscillator circuit PLLVcc XTAL PLLVss PLL multiplier circuit PLLcap CK pin (System clock) x2 x8 Peripheral clock (P) Internal clock () Figure 5.1 Block Diagram of Clock Pulse Generator Rev. 5.00 Feb. 24, 2010 Page 59 of 950 REJ09B0177-0500 5. Clock Pulse Generator (CPG) 5.1.2 Pin Configuration The pins relating to the clock pulse generator are shown in table 5.1. Table 5.1 CPG Pins Pin Name Abbreviation I/O Description External clock EXTAL Input Crystal oscillator or external clock input Crystal XTAL Input/output Crystal oscillator connection System clock CK Output System clock output PLL power supply PLLVCC Input PLL multiplier circuit power supply PLL ground PLLVSS Input PLL multiplier circuit ground PLL capacitance PLLCAP Input PLL multiplier circuit oscillation external capacitance pin 5.2 Frequency Ranges 5.2.1 Frequency Ranges The input frequency and operating frequency ranges are shown in table 5.2. Table 5.2 Input Frequency and Operating Frequency Input Frequency Range (MHz) PLL Multiplication Factor Internal Clock () Frequency Range (MHz) Peripheral Clock (P) Frequency Range (MHz) System Clock Frequency Range (MHz) 5 to 10 x8 40 to 80 10 to 20 10 to 20 Note: Crystal oscillator and external clock input Two types of clock signals, internal clock () and peripheral clock (P) signals, are supplied and used by this LSI. The internal clock signal (), with frequency eight times the frequency of the clock signal input from the EXTAL pin, is mainly supplied to the bus master modules such as CPU, FPU, and DMAC. The peripheral clock signal (P), with frequency two times the frequency of the clock signal input from the EXTAL pin, is mainly supplied to the on-chip peripheral modules. The CK pin outputs the peripheral clock signal (P) signal as the system clock signal. Rev. 5.00 Feb. 24, 2010 Page 60 of 950 REJ09B0177-0500 5. Clock Pulse Generator (CPG) Input clock (EXTAL pin) System clock (CK pin) Internal clock () Peripheral clock (P) Internal clock () = input clock x 8 Note: Since the input clock signal is multiplied by the PLL multiplier circuit, the phase relationships between the input clock signal and the other clock signals are not determined uniformly. Figure 5.2 Frequencies and Phases of Clock Signals 5.3 Clock Source Clock pulses can be supplied from a connected crystal oscillator or an external clock. 5.3.1 Connecting a Crystal Oscillator Circuit Configuration: Figure 5.3 shows an example of connecting a crystal oscillator. Use the damping resistance (Rd) shown in table 5.3. An AT-cut parallel-resonance type crystal oscillator should be used. Load capacitors (CL1, CL2) must be connected as shown in the figure. The clock pulses generated by the crystal oscillator and internal oscillator are sent to the PLL multiplier circuit, where a multiplied frequency is selected and supplied inside this LSI chip and to external devices. The crystal oscillator manufacturer should be consulted concerning the compatibility between the crystal oscillator and the chip. CL2 EXTAL CL1 XTAL Rd Note: CL1 = CL2 = 18 to 22 pF Figure 5.3 Connection of Crystal Oscillator (Example) Table 5.3 Damping Resistance Values (Recommended Values) Frequency (MHz) Parameter 5 10 Rd () 500 0 Rev. 5.00 Feb. 24, 2010 Page 61 of 950 REJ09B0177-0500 5. Clock Pulse Generator (CPG) Crystal Oscillator: Figure 5.4 shows an equivalent circuit of the crystal oscillator. Use a crystal oscillator with the characteristics listed in table 5.4. L CL Rs XTAL EXTAL Co Figure 5.4 Crystal Oscillator Equivalent Circuit Table 5.4 Crystal Oscillator Parameters (Recommended Values) Frequency (MHz) Parameter 5 10 Rs max () 100 50 Co max (pF) 7 7 The crystal oscillator manufacturer should be consulted concerning the compatibility between the crystal oscillator and the chip. 5.3.2 External Clock Input Method An example of external clock input connection is shown in figure 5.5. When the XTAL pin is placed in the open state, the parasitic capacitance should be 10 pF or less. Even when an external clock is input, provide for a wait of at least the oscillation settling time when powering on or exiting standby mode in order to secure the PLL settling time. Open External clock input XTAL EXTAL Figure 5.5 External Clock Input Method (Example) Rev. 5.00 Feb. 24, 2010 Page 62 of 950 REJ09B0177-0500 5. Clock Pulse Generator (CPG) 5.4 Usage Notes Notes on Board Design: Place the crystal oscillator and its load capacitors as close as possible to the XTAL and EXTAL pins. To prevent induction from interfering with correct oscillation, do not allow any signal lines to cross the XTAL or EXTAL lines (figure 5.6). Crossing of signal lines prohibited CL1 XTAL CL2 EXTAL Figure 5.6 Precautions for Oscillator Circuit System Board Design PLL Oscillation Power Supply: Separate PLLVCC and PLLVSS from the other VCC and VSS lines at the board power supply source, and be sure to insert bypass capacitors CPB and CB close to the pins. PLLCAP Rp PLLVCC CPB PLLVSS VCC CB VSS Recommended values CPB, CB: 0.1F Rp: 200 Figure 5.7 Points for Caution in PLL Power Supply Connection Rev. 5.00 Feb. 24, 2010 Page 63 of 950 REJ09B0177-0500 5. Clock Pulse Generator (CPG) PLLVSS PLLCAP PLLVCC XTAL VCC EXTAL VSS Figure 5.8 Actual Example of Board Design Rev. 5.00 Feb. 24, 2010 Page 64 of 950 REJ09B0177-0500 6. Exception Processing Section 6 Exception Processing 6.1 Overview 6.1.1 Types of Exception Processing and Priority Exception processing is started by four sources: resets, address errors, interrupts and instructions and have the priority shown in table 6.1. When several exception processing sources occur at once, they are processed according to the priority shown. Table 6.1 Types of Exception Processing and Priority Order Exception Source Priority Reset Power-on reset High Manual reset Address error CPU address error DMAC address error Instructions FPU exception Interrupt NMI User break H-UDI IRQ On-chip peripheral modules: Instructions * Direct memory access controller (DMAC) * Advanced timer unit-II (ATU-II) * Compare match timer 0 (CMT0) * Multi trigger A/D0 (MTAD0) * A/D converter channel 0 (A/D0) * Compare match timer 1 (CMT1) * Multi trigger A/D1 (MTAD1) * A/D converter channel 1 (A/D1) * A/D converter channel 2 (A/D2) * Serial communication interface (SCI) * Synchronous serial communication unit (SSU) * Controller area network 0 (HCAN0) * Watchdog timer (WDT) * Controller area network 1 (HCAN 1) Trap instruction (TRAPA instruction) General illegal instructions (undefined code) Illegal slot instructions (undefined code placed directly after a delay branch instruction*1 or instructions that rewrite the PC*2) Low Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF. 2. Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA, BF/S, BT/S, BSRF, BRAF. Rev. 5.00 Feb. 24, 2010 Page 65 of 950 REJ09B0177-0500 6. Exception Processing 6.1.2 Exception Processing Operations The exception processing sources are detected and begin processing according to the timing shown in table 6.2. Table 6.2 Timing of Exception Source Detection and Start of Exception Processing Exception Source Timing of Source Detection and Start of Processing Reset Power-on reset Starts when the RES pin changes from low to high or when the WDT overflows. Manual reset Starts when the WDT overflows. Address error Detected when instruction is decoded and starts when the previous executing instruction finishes executing. Interrupts Detected when instruction is decoded and starts when the previous executing instruction finishes executing. Instructions Trap instruction Starts from the execution of a TRAPA instruction. General illegal instructions Starts from the decoding of undefined code anytime except after a delayed branch instruction (delay slot). Illegal slot instructions Starts from the decoding of undefined code placed in a delayed branch instruction (delay slot) or of instructions that rewrite the PC. Floating point instructions Starts when a floating-point instruction causes an invalid operation exception (IEEE754 specification) or division-by-zero exception. When exception processing starts, the CPU operates as follows: 1. Exception processing triggered by reset: The initial values of the program counter (PC) and stack pointer (SP) are fetched from the exception processing vector table (PC and SP are respectively the H'00000000 and H'00000004 addresses for power-on resets and the H'00000008 and H'0000000C addresses for manual resets). See section 6.1.3, Exception Processing Vector Table, for more information. H'00000000 is then written to the vector base register (VBR) and H'F (1111) is written to the interrupt mask bits (I3-I0) of the status register (SR). The program begins running from the PC address fetched from the exception processing vector table. 2. Exception processing triggered by address errors, interrupts and instructions: SR and PC are saved to the stack indicated by R15. For interrupt exception processing, the interrupt priority level is written to the SR's interrupt mask bits (I3-I0). For address error and instruction exception processing, the I3-I0 bits are not affected. The start address is then fetched from the exception processing vector table and the program begins running from that address. 6.1.3 Exception Processing Vector Table Before exception processing begins running, the exception processing vector table must be set in memory. The exception processing vector table stores the start addresses of exception service routines. (The reset exception processing table holds the initial values of PC and SP.) All exception sources are given different vector numbers and vector table address offsets, from which the vector table addresses are calculated. During exception processing, the start addresses of the exception service routines are fetched from the exception processing vector table, which is indicated by this vector table address. Table 6.3 shows the vector numbers and vector table address offsets. Table 6.4 shows how vector table addresses are calculated. Rev. 5.00 Feb. 24, 2010 Page 66 of 950 REJ09B0177-0500 6. Exception Processing Table 6.3 Exception Processing Vector Table Exception Sources Vector Numbers Vector Table Address Offset PC 0 H'00000000-H'00000003 SP 1 H'00000004-H'00000007 PC 2 H'00000008-H'0000000B SP 3 H'0000000C-H'0000000F General illegal instruction 4 H'00000010-H'00000013 (Reserved by system) 5 H'00000014-H'00000017 Slot illegal instruction 6 H'00000018-H'0000001B (Reserved by system) 7 H'0000001C-H'0000001F 8 H'00000020-H'00000023 CPU address error 9 H'00000024-H'00000027 DMAC address error 10 H'00000028-H'0000002B NMI 11 H'0000002C-H'0000002F User break 12 H'00000030-H'00000033 FPU exception 13 H'00000034-H'00000037 H-UDI 14 H'00000038-H'0000003B (Reserved by system) 15 H'0000003C-H'0000003F Power-on reset Manual reset Interrupts Trap instruction (user vector) Interrupts On-chip peripheral module* Note: * : : 31 H'0000007C-H'0000007F 32 H'00000080-H'00000083 : : 63 H'000000FC-H'000000FF IRQ0 64 H'00000100-H'00000103 IRQ1 65 H'00000104-H'00000107 IRQ2 66 H'00000108-H'0000010B IRQ3 67 H'0000010C-H'0000010F IRQ4 68 H'00000110-H'00000113 IRQ5 69 H'00000114-H'00000117 IRQ6 70 H'00000118-H'0000011B IRQ7 71 H'0000011C-H'0000011F 72 H'00000120-H'00000124 : : 255 H'000003FC-H'000003FF The vector numbers and vector table address offsets for each on-chip peripheral module interrupt are given in table 7.3. Rev. 5.00 Feb. 24, 2010 Page 67 of 950 REJ09B0177-0500 6. Exception Processing Table 6.4 Calculating Exception Processing Vector Table Addresses Exception Source Vector Table Address Calculation Resets Vector table address = (vector table address offset) = (vector number) x 4 Address errors, interrupts, instructions Vector table address = VBR + (vector table address offset) = VBR + (vector number) x 4 Notes: 1. VBR: Vector base register 2. Vector table address offset: See table 6.3. 3. Vector number: See table 6.3. 6.2 Resets 6.2.1 Types of Reset A reset is the highest-priority exception processing source. There are two kinds of reset, power-on and manual. As shown in table 6.5, the CPU state is initialized in both a power-on reset and a manual reset. On-chip peripheral module registers are also initialized by a power-on reset, but not by a manual reset. Table 6.5 Exception Source Detection and Exception Processing Start Timing Conditions for Transition to Reset State Internal States Type RES WDT Overflow CPU/MULT/ FPU/INTC On-Chip eripheral Modules PFC, IO Port Power-on reset Low -- Initialized Initialized Initialized High Power-on reset Initialized Initialized Not initialized High Manual reset Initialized Not initialized Not initialized Manual reset 6.2.2 Power-On Reset Power-On Reset by Means of RES Pin: When the RES pin is driven low, the chip enters the power-on reset state. To reliably reset the chip, the RES pin should be kept at the low level for at least the duration of the oscillation settling time at power-on or when in standby mode (when the clock is halted), or at least 10 tcyc when the clock is running. In the power-on reset state, the CPU's internal state and all the on-chip peripheral module registers are initialized. In the power-on reset state, power-on reset exception processing starts when the RES pin is first driven low for a set period of time and then returned to high. The CPU operates as follows: 1. The initial value (execution start address) of the program counter (PC) is fetched from the exception processing vector table. 2. The initial value of the stack pointer (SP) is fetched from the exception processing vector table. 3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3-I0) of the status register (SR) are set to H'F (1111). 4. The values fetched from the exception processing vector table are set in the PC and SP, and the program begins executing. Be certain to always perform power-on reset processing when turning the system power on. Rev. 5.00 Feb. 24, 2010 Page 68 of 950 REJ09B0177-0500 6. Exception Processing Power-On Reset Initiated by WDT: When a setting is made for a power-on reset to be generated in the WDT's watchdog timer mode, and the WDT's TCNT overflows, the chip enters the power-on reset state. The pin function controller (PFC) registers and I/O port registers are not initialized by the reset signal generated by the WDT (these registers are only initialized by a power-on reset from off-chip). If reset caused by the input signal at the RES pin and a reset caused by WDT overflow occur simultaneously, the RES pin reset has priority, and the WOVF bit in RSTCSR is cleared to 0. When WDT-initiated power-on reset processing is started, the CPU operates as follows: 1. The initial value (execution start address) of the program counter (PC) is fetched from the exception processing vector table. 2. The initial value of the stack pointer (SP) is fetched from the exception processing vector table. 3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3-I0) of the status register (SR) are set to H'F (1111). 4. The values fetched from the exception processing vector table are set in the PC and SP, and the program begins executing. 6.2.3 Manual Reset When a setting is made for a manual reset to be generated in the WDT's watchdog timer mode, and the WDT's TCNT overflows, the chip enters the power-on reset state. When WDT-initiated manual reset processing is started, the CPU operates as follows: 1. The initial value (execution start address) of the program counter (PC) is fetched from the exception processing vector table. 2. The initial value of the stack pointer (SP) is fetched from the exception processing vector table. 3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3-I0) of the status register (SR) are set to H'F (1111). 4. The values fetched from the exception processing vector table are set in the PC and SP, and the program begins executing. When a manual reset is generated, the bus cycle is retained, but if a manual reset occurs while the bus is released or during DMAC burst transfer, manual reset exception processing will be deferred until the CPU acquires the bus. However, if the interval from generation of the manual reset until the end of the bus cycle is equal to or longer than the internal manual reset interval of 512 cycles, the internal manual reset source is ignored instead of being deferred, and manual reset exception processing is not executed. Rev. 5.00 Feb. 24, 2010 Page 69 of 950 REJ09B0177-0500 6. Exception Processing 6.3 Address Errors 6.3.1 Address Error Sources Address errors occur when instructions are fetched or data read or written, as shown in table 6.6. Table 6.6 Bus Cycles and Address Errors Bus Cycle Type Bus Master Bus Cycle Description Address Errors Instruction fetch CPU Instruction fetched from even address None (normal) Instruction fetched from odd address Address error occurs Instruction fetched from other than on-chip peripheral None (normal) module space* Data read/write CPU or DMAC Instruction fetched from on-chip peripheral module space* Address error occurs Instruction fetched from external memory space when in single chip mode Address error occurs Word data accessed from even address None (normal) Word data accessed from odd address Address error occurs Longword data accessed from a longword boundary None (normal) Longword data accessed from other than a longword boundary Address error occurs Byte or word data accessed in on-chip peripheral module space* None (normal) Longword data accessed in 16-bit on-chip peripheral None (normal) module space* Note: 6.3.2 * Longword data accessed in 8-bit on-chip peripheral module space* Address error occurs External memory space accessed when in single chip mode Address error occurs See section 9, Bus State Controller (BSC), for details of the on-chip peripheral module space. Address Error Exception Processing When an address error occurs, the bus cycle in which the address error occurred ends. When the executing instruction then finishes, address error exception processing starts up. The CPU operates as follows: 1. The status register (SR) is saved to the stack. 2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the last executed instruction. 3. The exception service routine start address is fetched from the exception processing vector table that corresponds to the address error that occurred and the program starts executing from that address. The jump that occurs is not a delayed branch. Rev. 5.00 Feb. 24, 2010 Page 70 of 950 REJ09B0177-0500 6. Exception Processing 6.4 Interrupts 6.4.1 Interrupt Sources Table 6.7 shows the sources that start up interrupt exception processing. These are divided into NMI, user breaks, H-UDI, IRQ, and on-chip peripheral modules. Table 6.7 Interrupt Sources Type Request Source Number of Sources NMI NMI pin (external input) 1 User break User break controller 1 H-UDI High-performance user debug interface 1 IRQ IRQ0-IRQ7 (external input) 8 On-chip peripheral module Direct memory access controller (DMAC) 4 Advanced timer unit-II (ATU-II) 75 Compare match timer (CMT) 2 A/D converter 3 Serial communication interface (SCI) 20 Synchronous communication unit (SSU) 6 Watchdog timer (WDT) 1 Controller area network-II (HCAN-II) 8 Each interrupt source is allocated a different vector number and vector table offset. See table 7.3, for more information on vector numbers and vector table address offsets. 6.4.2 Interrupt Priority Level The interrupt priority order is predetermined. When multiple interrupts occur simultaneously (overlap), the interrupt controller (INTC) determines their relative priorities and starts up processing according to the results. The priority order of interrupts is expressed as priority levels 0-16, with priority 0 the lowest and priority 16 the highest. The NMI interrupt has priority 16 and cannot be masked, so it is always accepted. The user break interrupt and H-UDI interrupt priority level is 15. IRQ interrupts and on-chip peripheral module interrupt priority levels can be set freely using the INTC's interrupt priority registers A through L (IPRA to IPRL) as shown in table 6.8. The priority levels that can be set are 0-15. Level 16 cannot be set. See section 7.3.1, Interrupt Priority Registers A-L (IPRA-IPRL), for details of the interrupt priority registers. Table 6.8 Interrupt Priority Order Type Priority Level Comment NMI 16 Fixed priority level. Cannot be masked. User break 15 Fixed priority level. H-UDI 15 Fixed priority level. IRQ 0-15 Set with interrupt priority level setting registers A through L (IPRA to IPRL). On-chip peripheral module 0-15 Set with interrupt priority level setting registers A through L (IPRA to IPRL). Rev. 5.00 Feb. 24, 2010 Page 71 of 950 REJ09B0177-0500 6. Exception Processing 6.4.3 Interrupt Exception Processing When an interrupt occurs, its priority level is ascertained by the interrupt controller (INTC). NMI is always accepted, but other interrupts are only accepted if they have a priority level higher than the priority level set in the interrupt mask bits (I3-I0) of the status register (SR). When an interrupt is accepted, exception processing begins. In interrupt exception processing, the CPU saves SR and the program counter (PC) to the stack. The priority level value of the accepted interrupt is written to SR bits I3-I0. For NMI, however, the priority level is 16, but the value set in I3-I0 is H'F (level 15). Next, the start address of the exception service routine is fetched from the exception processing vector table for the accepted interrupt, that address is jumped to and execution begins. See section 7.4, Interrupt Operation, for further details. 6.5 Exceptions Triggered by Instructions 6.5.1 Types of Exceptions Triggered by Instructions Exception processing can be triggered by trap instructions, general illegal instructions, and illegal slot instructions, and floating-point instructions, as shown in table 6.9. Table 6.9 Types of Exceptions Triggered by Instructions Type Source Instruction Trap instructions TRAPA Illegal slot instructions Undefined code placed immediately after a delayed branch instruction (delay slot) and instructions that rewrite the PC Comment Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA, BF/S, BT/S, BSRF, BRAF General illegal instructions Undefined code anywhere besides in a delay slot Floating-point instructions Instruction causing an invalid operation FADD, FSUB, FMUL, FDIV, FMAC, FCMP/EQ, exception defined in the IEEE754 FCMP/GT, FNEG, FABS, FTRC standard or a division-by-zero exception 6.5.2 Trap Instructions When a TRAPA instruction is executed, trap instruction exception processing starts up. The CPU operates as follows: 1. The status register (SR) is saved to the stack. 2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the TRAPA instruction. 3. The exception service routine start address is fetched from the exception processing vector table that corresponds to the vector number specified in the TRAPA instruction. That address is jumped to and the program starts executing. The jump that occurs is not a delayed branch. Rev. 5.00 Feb. 24, 2010 Page 72 of 950 REJ09B0177-0500 6. Exception Processing 6.5.3 Illegal Slot Instructions An instruction placed immediately after a delayed branch instruction is said to be placed in a delay slot. When the instruction placed in the delay slot is undefined code, illegal slot exception processing starts up when that undefined code is decoded. Illegal slot exception processing also starts up when an instruction that rewrites the program counter (PC) is placed in a delay slot. The processing starts when the instruction is decoded. The CPU handles an illegal slot instruction as follows: 1. The status register (SR) is saved to the stack. 2. The program counter (PC) is saved to the stack. The PC value saved is the jump address of the delayed branch instruction immediately before the undefined code or the instruction that rewrites the PC. 3. The exception service routine start address is fetched from the exception processing vector table that corresponds to the exception that occurred. That address is jumped to and the program starts executing. The jump that occurs is not a delayed branch. 6.5.4 General Illegal Instructions When undefined code placed anywhere other than immediately after a delayed branch instruction (i.e., in a delay slot) is decoded, general illegal instruction exception processing starts up. The CPU handles general illegal instructions in the same way as illegal slot instructions. Unlike processing of illegal slot instructions, however, the program counter value stored is the start address of the undefined code. When the FPU has been stopped by means of the module stop bit, floating-point instructions and FPU-related CPU instructions are treated as illegal instructions. 6.5.5 Floating-Point Instructions When the V or Z bit is set in the enable field of the FPSCR register, an FPU exception occurs. This indicates that a floating-point instruction has caused an invalid operation exception defined in the IEEE754 standard or a division-by-zero exception. Floating-point instructions which can cause an exception are as follows: FADD, FSUB, FMUL, FDIV, FMAC, FCMP/EQ, FCMP/GT, FNEG, FABS, FTRC An FPU exception occurs only if the corresponding enable bit is set. When the FPU detects an exception source, FPU operation is suspended and the occurrence of the exception is reported to the CPU. When exception processing is started, the CPU saves the SR and PC contents to the stack (the PC value saved is the start address of the instruction following the last instruction executed), and branches to the address stored in VBR + H'00000034. The exception flag bits in the FPSCR are always updated, regardless of whether or not an FPU exception is accepted, and remain set until the user clears them explicitly with an instruction. FPSCR cause bits change each time an FPU instruction is executed. Exception events other than those defined in the IEEE754 standard (i.e., underflow, overflow, and inexact exceptions) are detected by the FPU but do not result in the generation of any kind of exception. Neither is an FPU exception generated by a floating-point instruction relating to data transfer, such as FLOAT. Rev. 5.00 Feb. 24, 2010 Page 73 of 950 REJ09B0177-0500 6. Exception Processing 6.6 When Exception Sources Are Not Accepted When an address error or interrupt is generated after a delayed branch instruction or interrupt-disabled instruction, it is sometimes not accepted immediately but stored instead, as shown in table 6.10. When this happens, it will be accepted when an instruction that can accept the exception is decoded. Table 6.10 Generation of Exception Sources Immediately after a Delayed Branch Instruction or InterruptDisabled Instruction Exception Source Point of Occurrence Immediately after a delayed branch instruction*1 Immediately after an interrupt-disabled Immediately after an FPU Notes: 1. 2. 3. 4. instruction*2 instruction*3 Bus Error Interrupt FPU Exception Not accepted Not accepted Not accepted Not accepted Accepted Not accepted Accepted Not accepted*4 Not accepted Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF Interrupt-disabled instructions: LDC, LDC.L, STC, STC.L, LDS, LDS.L, STS, STS.L FPU instructions: Table 2.18 and table 2.19. In the SH-2 a bus error is accepted. Rev. 5.00 Feb. 24, 2010 Page 74 of 950 REJ09B0177-0500 6. Exception Processing 6.7 Stack Status after Exception Processing Ends The status of the stack after exception processing ends is as shown in table 6.11. Table 6.11 Stack Status After Exception Processing Ends Exception Type Stack Status Address error SP Address of instruction 32 bits after executed instruction SR 32 bits Address of instruction after TRAPA instruction 32 bits SR 32 bits Address of general illegal instruction 32 bits SR 32 bits Trap instruction SP General illegal instruction SP Interrupt SP Address of instruction after executed instruction 32 bits SR Illegal slot instruction SP 32 bits Jump destination address of delay branch instruction 32 bits SR 32 bits FPU exception SP Address of instruction after FPU exception instruction 32 bits SR 6.8 Usage Notes 6.8.1 Value of Stack Pointer (SP) 32 bits The value of the stack pointer must always be a multiple of four. If it is not, an address error will occur when the stack is accessed during exception processing. 6.8.2 Value of Vector Base Register (VBR) The value of the vector base register must always be a multiple of four. If it is not, an address error will occur when the vector table is accessed during exception processing. Rev. 5.00 Feb. 24, 2010 Page 75 of 950 REJ09B0177-0500 6. Exception Processing 6.8.3 Address Errors Caused by Stacking of Address Error Exception Processing When the stack pointer is not a multiple of four, an address error will occur during stacking of the exception processing (interrupts, etc.) and address error exception processing will start up as soon as the first exception processing is ended. Address errors will then also occur in the stacking for this address error exception processing. To ensure that address error exception processing does not go into an endless loop, no address errors are accepted at that point. This allows program control to be shifted to the address error exception service routine and enables error processing. When an address error occurs during exception processing stacking, the stacking bus cycle (write) is executed. During stacking of the status register (SR) and program counter (PC), the SP is decremented by 4 for both, so the value of SP will not be a multiple of four after the stacking either. The address value output during stacking is the SP value, so the address where the error occurred is itself output. This means the write data stacked will be undefined. Rev. 5.00 Feb. 24, 2010 Page 76 of 950 REJ09B0177-0500 7. Interrupt Controller (INTC) Section 7 Interrupt Controller (INTC) 7.1 Overview The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The INTC has registers for setting the priority of each interrupt which can be used by the user to order the priorities in which the interrupt requests are processed. 7.1.1 Features The INTC has the following features: * 16 levels of interrupt priority By setting the twelve interrupt-priority level registers, the priorities of IRQ interrupts and on-chip peripheral module interrupts can be set in 16 levels for different request sources. * NMI noise canceler function NMI input level bits indicate the NMI pin status. By reading these bits with the interrupt exception service routine, the pin status can be confirmed, enabling it to be used as a noise canceler. * Notification of interrupt occurrence can be reported externally (IRQOUT pin) For example, it is possible to request the bus if an external bus master is informed that a peripheral module interrupt request has occurred when the chip has released the bus. Rev. 5.00 Feb. 24, 2010 Page 77 of 950 REJ09B0177-0500 7. Interrupt Controller (INTC) 7.1.2 Block Diagram Figure 7.1 is a block diagram of the INTC. IRQOUT NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Input control CPU/ DMAC request judgment Priority ranking judgment Comparator Interrupt request SR UBC H-UDI DMAC ATU-II CMT A/D MTAD SCI SSU WDT HCAN-II (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) I3 I2 I1 I0 CPU ICR IPR ISR Module bus Bus interface INTC Legend: User break controller UBC: High-perfotmance user debug H-UDI: interface DMAC: Direct memory access controller ATU-II: Advanced timer unit-II Compare match timer CMT: A/D converter A/D: MTAD: Multi trigger A/D SCI: SSU: WDT: HCAN-II: ICR: ISR: IPRA-IPRL: SR: Serial communication interface Synchronous serial communication unit Watchdog timer Controller area network-II Interrupt control register IRQ status register Interrupt priority level setting registers A to L Status register Figure 7.1 INTC Block Diagram Rev. 5.00 Feb. 24, 2010 Page 78 of 950 REJ09B0177-0500 Internal bus IPRA-IPRL 7. Interrupt Controller (INTC) 7.1.3 Pin Configuration Table 7.1 shows the INTC pin configuration. Table 7.1 Pin Configuration Name Abbreviation I/O Function Non-maskable interrupt input pin NMI I Input of non-maskable interrupt request signal Interrupt request input pins IRQ0-IRQ7 I Input of maskable interrupt request signals Interrupt request output pin IRQOUT O Output of notification signal when an interrupt has occurred 7.1.4 Register Configuration The INTC has the 14 registers shown in table 7.2. These registers set the priority of the interrupts and control external interrupt input signal detection. Table 7.2 Register Configuration Name Abbr. R/W Initial Value Address Access Sizes Interrupt priority register A IPRA R/W H'0000 H'FFFF ED00 8, 16, 32 Interrupt priority register B IPRB R/W H'0000 H'FFFF ED02 8, 16, 32 Interrupt priority register C IPRC R/W H'0000 H'FFFF ED04 8, 16, 32 Interrupt priority register D IPRD R/W H'0000 H'FFFF ED06 8, 16, 32 Interrupt priority register E IPRE R/W H'0000 H'FFFF ED08 8, 16, 32 Interrupt priority register F IPRF R/W H'0000 H'FFFF ED0A 8, 16, 32 Interrupt priority register G IPRG R/W H'0000 H'FFFF ED0C 8, 16, 32 Interrupt priority register H IPRH R/W H'0000 H'FFFF ED0E 8, 16, 32 Interrupt priority register I IPRI R/W H'0000 H'FFFF ED10 8, 16, 32 Interrupt priority register J IPRJ R/W H'0000 H'FFFF ED12 8, 16, 32 Interrupt priority register K IPRK R/W H'0000 H'FFFF ED14 8, 16, 32 Interrupt priority register L IPRL R/W H'0000 H'FFFF ED16 8, 16, 32 Interrupt control register ICR R/W *1 H'FFFF ED18 8, 16, 32 H'0000 H'FFFF ED1A 8, 16, 32 IRQ status register ISR R/(W)* 2 Notes: In register access, four cycles are required for byte access and word access, and eight cycles for longword access. 1. The value when the NMI pin is high is H'8000; when the NMI pin is low, it is H'0000. 2. Only 0 can be written, in order to clear flags. Rev. 5.00 Feb. 24, 2010 Page 79 of 950 REJ09B0177-0500 7. Interrupt Controller (INTC) 7.2 Interrupt Sources There are five types of interrupt sources: NMI, user breaks, H-UDI, IRQ, and on-chip peripheral modules. Each interrupt has a priority expressed as a priority level (0 to 16, with 0 the lowest and 16 the highest). Giving an interrupt a priority level of 0 masks it. 7.2.1 NMI Interrupts The NMI interrupt has priority 16 and is always accepted. Input at the NMI pin is detected by edge. Use the NMI edge select bit (NMIE) in the interrupt control register (ICR) to select either the rising or falling edge. NMI interrupt exception processing sets the interrupt mask level bits (I3-I0) in the status register (SR) to level 15. 7.2.2 User Break Interrupt A user break interrupt has a priority of level 15, and occurs when the break condition set in the user break controller (UBC) is satisfied. User break interrupt requests are detected by edge and are held until accepted. User break interrupt exception processing sets the interrupt mask level bits (I3-I0) in the status register (SR) to level 15. For more information about the user break interrupt, see section 8, User Break Controller (UBC). 7.2.3 H-UDI Interrupt A serial debug interface (H-UDI) interrupt has a priority level of 15, and occurs when an H-UDI interrupt instruction is serially input. H-UDI interrupt requests are detected by edge and are held until accepted. H-UDI exception processing sets the interrupt mask level bits (I3-I0) in the status register (SR) to level 15. For more information about the H-UDI interrupt, see section 20, High-performance User Debug Interface (H-UDI). 7.2.4 IRQ Interrupts IRQ interrupts are requested by input from pins IRQ0-IRQ7. Set the IRQ sense select bits (IRQ0S-IRQ7S) of the interrupt control register (ICR) to select low level detection or falling edge detection for each pin. The priority level can be set from 0 to 15 for each pin using interrupt priority registers A and B (IPRA-IPRB). When IRQ interrupts are set to low level detection, an interrupt request signal is sent to the INTC during the period the IRQ pin is low. Interrupt request signals are not sent to the INTC when the IRQ pin becomes high. Interrupt request levels can be confirmed by reading the IRQ flags (IRQ0F-IRQ7F) of the IRQ status register (ISR). When IRQ interrupts are set to falling edge detection, interrupt request signals are sent to the INTC upon detecting a change on the IRQ pin from high to low level. IRQ interrupt request detection results are maintained until the interrupt request is accepted. Confirmation that IRQ interrupt requests have been detected is possible by reading the IRQ flags (IRQ0F-IRQ7F) of the IRQ status register (ISR), and by writing a 0 after reading a 1, IRQ interrupt request detection results can be withdrawn. In IRQ interrupt exception processing, the interrupt mask bits (I3-I0) of the status register (SR) are set to the priority level value of the accepted IRQ interrupt. Rev. 5.00 Feb. 24, 2010 Page 80 of 950 REJ09B0177-0500 7. Interrupt Controller (INTC) 7.2.5 On-Chip Peripheral Module Interrupts On-chip peripheral module interrupts are interrupts generated by the following on-chip peripheral modules: * * * * * * * * * Direct memory access controller (DMAC) Advanced timer unit-II (ATU-II) Compare match timer (CMT) A/D converter (A/D) Multi trigger A/D (MTAD) Serial communication interface (SCI) Synchronous serial communication unit (SSU) Watchdog timer (WDT) Controller area network-II (HCAN-II) A different interrupt vector is assigned to each interrupt source, so the exception service routine does not have to decide which interrupt has occurred. Priority levels between 0 and 15 can be assigned to individual on-chip peripheral modules in interrupt priority registers C-L (IPRC-IPRL). On-chip peripheral module interrupt exception processing sets the interrupt mask level bits (I3-I0) in the status register (SR) to the priority level value of the on-chip peripheral module interrupt that was accepted. 7.2.6 Interrupt Exception Vectors and Priority Rankings Table 7.3 lists interrupt sources and their vector numbers, vector table address offsets and interrupt priorities. Each interrupt source is allocated a different vector number and vector table address offset. Vector table addresses are calculated from vector numbers and address offsets. In interrupt exception processing, the exception service routine start address is fetched from the vector table indicated by the vector table address. See table 6.4, Calculating Exception Processing Vector Table Addresses, in section 6, Exception Processing. IRQ interrupts and on-chip peripheral module interrupt priorities can be set freely between 0 and 15 for each pin or module by setting interrupt priority registers A-L (IPRA-IPRL). The ranking of interrupt sources for IPRC-IPRL, however, must be the order listed under Priority within IPR Setting Range in table 7.3 and cannot be changed. A power-on reset assigns priority level 0 to IRQ interrupts and on-chip peripheral module interrupts. If the same priority level is assigned to two or more interrupt sources and interrupts from those sources occur simultaneously, their priority order is the default priority order indicated at the right in table 7.3. Rev. 5.00 Feb. 24, 2010 Page 81 of 950 REJ09B0177-0500 7. Interrupt Controller (INTC) Table 7.3 Interrupt Exception Processing Vectors and Priorities Interrupt Vector Vector Table Address Offset Interrupt Priority (Initial Value) Corresponding IPR (Bits) Priority within IPR Default Setting Range Priority Interrupt Source Vector No. NMI 11 H'0000002C to H'0000002F 16 -- -- UBC 12 H'00000030 to H'0000003B 15 -- -- H-UDI 14 H'00000038 to H'0000003B 15 -- -- IRQ0 64 H'00000100 to H'0000013B 0 to 15 (0) IPRA (15-12) -- IRQ1 65 H'00000104 to H'00000107 0 to 15 (0) IPRA (11-8) -- IRQ2 66 H'00000108 to H'0000010B 0 to 15 (0) IPRA (7-4) -- IRQ3 67 H'0000010C to H'0000010F 0 to 15 (0) IPRA (3-0) -- IRQ4 68 H'00000110 to H'00000113 0 to 15 (0) IPRB (15-12) -- IRQ5 69 H'00000114 to H'00000117 0 to 15 (0) IPRB (11-8) -- IRQ6 70 H'00000118 to H'0000011B 0 to 15 (0) IPRB (7-4) -- IRQ7 71 H'0000011C to H'0000011F 0 to 15 (0) IPRB (3-0) -- IPRC (15-12) 1 2 1 2 1 2 1 2 DMAC0 DEI0 72 H'00000120 to H'00000123 0 to 15 (0) DMAC1 DEI1 74 H'00000128 to H'0000012B 0 to 15 (0) DMAC2 DEI2 76 H'00000130 to H'00000133 0 to 15 (0) DMAC3 DEI3 78 H'00000138 to H'0000013B 0 to 15 (0) ATU0 ATU01 ITV1/ ITV2A/ ITV2B 80 H'00000140 to H'00000143 0 to 15 (0) IPRC (7-4) ATU02 ICI0A 84 H'00000150 to H'00000153 0 to 15 (0) IPRC (3-0) ICI0B 86 H'00000158 to H'0000015B ICI0C 88 H'00000160 to H'00000163 ICI0D 90 H'00000168 to H'0000016B OVI0 92 H'00000170 to H'00000173 ATU03 ATU04 Rev. 5.00 Feb. 24, 2010 Page 82 of 950 REJ09B0177-0500 0 to 15 (0) 0 to 15 (0) IPRC (11-8) IPRD (15-12) IPRD (11-8) High Low 7. Interrupt Controller (INTC) Interrupt Vector Vector No. Interrupt Source ATU1 ATU11 Interrupt Priority (Initial Value) Corresponding IPR (Bits) Priority within IPR Default Setting Range Priority 0 to 15 (0) IPRD (7-4) IMI1A/ CMI1 96 H'00000180 to H'00000183 IMI1B 97 H'00000184 to H'00000187 2 IMI1C 98 H'00000188 to H'0000018B 3 IMI1D 99 H'0000018C to H'0000018F IMI1E 100 H'00000190 to H'00000193 IMI1F 101 H'00000194 to H'00000197 2 IMI1G 102 H'00000198 to H'0000019B 3 IMI1H 103 H'0000019C to H'0000019F ATU13 OVI1A/ OVI1B 104 H'000001A0 to H'000001A3 0 to 15 (0) IPRE (15-12) ATU21 IMI2A/ CMI2A 108 H'000001B0 to H'000001B3 0 to 15 (0) IPRE (11-8) IMI2B/ CMI2B 109 H'000001B4 to H'000001B7 2 IMI2C/ CMI2C 110 H'000001B8 to H'000001BB 3 IMI2D/ CMI2D 111 H'000001BC to H'000001BF IMI2E/ CMI2E 112 H'000001C0 to H'000001C3 IMI2F/ CMI2F 113 H'000001C4 to H'000001C7 2 IMI2G/ CMI2G 114 H'000001C8 to H'000001CB 3 IMI2H/ CMI2H 115 H'000001CC to H'000001CF OVI2A/ OVI2B 116 H'000001D0 to H'000001D3 ATU12 ATU2 Vector Table Address Offset ATU22 ATU23 0 to 15 (0) 0 to 15 (0) IPRD (3-0) IPRE (7-4) 4 1 4 1 4 1 0 to 15 (0) IPRE (3-0) 1 High 4 Low Rev. 5.00 Feb. 24, 2010 Page 83 of 950 REJ09B0177-0500 7. Interrupt Controller (INTC) Interrupt Vector Vector No. Interrupt Source ATU3 ATU4 ATU5 ATU31 Interrupt Priority (Initial Value) Corresponding IPR (Bits) Priority within IPR Default Setting Range Priority 0 to 15 (0) IPRF (15-12) IMI3A 120 H'000001E0 to H'000001E3 IMI3B 121 H'000001E4 to H'000001E7 2 IMI3C 122 H'000001E8 to H'000001EB 3 IMI3D 123 H'000001EC to H'000001EF ATU32 OVI3 124 H'000001F0 to H'000001F3 0 to 15 (0) IPRF (11-8) ATU41 IMI4A 128 H'00000200 to H'00000203 0 to 15 (0) IPRF (7-4) IMI4B 129 H'00000204 to H'00000207 2 IMI4C 130 H'00000208 to H'0000020B 3 IMI4D 131 H'0000020C to H'0000020F ATU42 OVI4 132 H'00000210 to H'00000213 0 to 15 (0) IPRF (3-0) ATU51 IMI5A 136 H'00000220 to H'00000223 0 to 15 (0) IPRG (15-12) IMI5B 137 H'00000224 to H'00000227 2 IMI5C 138 H'00000228 to H'0000022B 3 IMI5D 139 H'0000022C to H'0000022F OVI5 140 H'00000230 to H'00000233 0 to 15 (0) IPRG (11-8) CMI6A 144 H'00000240 to H'00000243 0 to 15 (0) IPRG (7-4) CMI6B 145 H'00000244 to H'00000247 2 CMI6C 146 H'00000248 to H'0000024B 3 CMI6D 147 H'0000024C to H'0000024F ATU52 ATU6 Vector Table Address Offset Rev. 5.00 Feb. 24, 2010 Page 84 of 950 REJ09B0177-0500 1 4 1 4 1 4 1 4 High Low 7. Interrupt Controller (INTC) Interrupt Vector Vector No. Interrupt Source ATU7 ATU8 ATU81 ATU82 ATU83 ATU84 Vector Table Address Offset Interrupt Priority (Initial Value) Corresponding IPR (Bits) Priority within IPR Default Setting Range Priority 0 to 15 (0) IPRG (3-0) CMI7A 148 H'00000250 to H'00000253 CMI7B 149 H'00000254 to H'00000257 2 CMI7C 150 H'00000258 to H'0000025B 3 CMI7D 151 H'0000025C to H'0000025F OSI8A 152 H'00000260 to H'00000263 OSI8B 153 H'00000264 to H'00000267 2 OSI8C 154 H'00000268 to H'0000026B 3 OSI8D 155 H'0000026C to H'0000026F OSI8E 156 H'00000270 to H'00000273 OSI8F 157 H'00000274 to H'00000277 2 OSI8G 158 H'00000278 to H'0000027B 3 OSI8H 159 H'0000027C to H'0000027F OSI8I 160 H'00000280 to H'00000283 OSI8J 161 H'00000284 to H'00000287 2 OSI8K 162 H'00000288 to H'0000028B 3 OSI8L 163 H'0000028C to H'0000028F OSI8M 164 H'00000290 to H'00000293 OSI8N 165 H'00000294 to H'00000297 2 OSI8O 166 H'00000298 to H'0000029B 3 OSI8P 167 H'0000029C to H'0000029F 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) IPRH (15-12) IPRH (11-8) IPRH (7-4) IPRH (3-0) 1 4 1 4 1 4 1 4 1 4 High Low Rev. 5.00 Feb. 24, 2010 Page 85 of 950 REJ09B0177-0500 7. Interrupt Controller (INTC) Interrupt Vector Vector No. Interrupt Source ATU9 ATU91 Vector Table Address Offset Interrupt Priority (Initial Value) Corresponding IPR (Bits) Priority within IPR Default Setting Range Priority 0 to 15 (0) IPRI (15-12) CMI9A 168 H'000002A0 to H'000002A3 CMI9B 169 H'000002A4 to H'000002A7 2 CMI9C 170 H'000002A8 to H'000002AB 3 CMI9D 171 H'000002AC to H'000002AF CMI9E 172 H'000002B0 to H'000002B3 CMI9F 174 H'000002B8 to H'000002BB CMI10A 176 H'000002C0 to H'000002C3 CMI10B 178 H'000002C8 to H'000002CB ICI10A/ CMI10G 180 H'000002D0 to H'000002D3 0 to 15(0) IPRI (3-0) IMI11A 184 H'000002E0 to H'000002E3 0 to 15 (0) IPRJ (15-12) IMI11B 186 H'000002E8 to H'000002EB OVI11 187 H'000002EC to H'000002EF CMT0 CMTI0 188 H'000002F0 to H'000002F3 MTAD0 ADT0 189 H'000002F4 to H'000002F7 A/D0 ADI0 190 H'000002F8 to H'000002FB CMT1 CMTI1 192 H'00000300 to H'00000303 MTAD1 ADT1 193 H'00000304 to H'00000307 A/D1 ADI1 194 H'00000308 to H'0000030B A/D2 ADI2 196 H'00000310 to H'00000313 ATU92 ATU10 ATU101 ATU102 ATU11 Rev. 5.00 Feb. 24, 2010 Page 86 of 950 REJ09B0177-0500 0 to 15 (0) 0 to 15 (0) IPRI (11-8) IPRI (7-4) 14 4 1 2 1 2 1 High 2 0 to 15 (0) I PRJ (11-8) 3 1 2 0 to 15 (0) IPRJ (7-4) 3 1 2 0 to 15 (0) IPRJ (3-0) 3 Low 7. Interrupt Controller (INTC) Interrupt Vector Vector No. Interrupt Source SCI0/ SSU0* SCI1 SCI2/ SSU1* SCI3 SCI4 Note: * Vector Table Address Offset Interrupt Priority (Initial Value) Corresponding IPR (Bits) Priority within IPR Default Setting Range Priority 0 to 15 (0) IPRK (15-12) ERI0/ SSERI0 200 H'00000320 to H'00000323 RXI0/ SSRXI0 201 H'00000324 to H'00000327 2 TXI0/ SSTSI0 202 H'00000328 to H'0000032B 3 TEI0 203 H'0000032C to H'0000032F ERI1 204 H'00000330 to H'00000333 RXI1 205 H'00000334 to H'00000337 2 TXI1 206 H'00000338 to H'0000033B 3 TEI1 207 H'0000033C to H'0000033F ERI2/ SSERI1 208 H'00000340 to H'00000343 RXI2/ SSRXI1 209 H'00000344 to H'00000347 2 TXI2/ SSTSI1 210 H'00000348 to H'0000034B 3 TEI2 211 H'0000034C to H'0000034F ERI3 212 H'00000350 to H'00000353 RXI3 213 H'00000354 to H'00000357 2 TXI3 214 H'00000358 to H'0000035B 3 TEI3 215 H'0000035C to H'0000035F ERI4 216 H'00000360 to H'00000363 RXI4 217 H'00000364 to H'00000367 2 TXI4 218 H'00000368 to H'0000036B 3 TEI4 219 H'0000036C to H'0000036F 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) IPRK (11-8) IPRK (7-4) IPRK(3-0) IPRL (15-12) 1 4 1 4 1 4 1 4 1 4 High Low SSU: Synchronous Serial Communication Unit Rev. 5.00 Feb. 24, 2010 Page 87 of 950 REJ09B0177-0500 7. Interrupt Controller (INTC) Interrupt Vector Vector No. Interrupt Source HCAN0 Vector Table Address Offset Interrupt Priority (Initial Value) Corresponding IPR (Bits) Priority within IPR Default Setting Range Priority 0 to 15 (0) IPRL (11-8) ERS0 220 H'00000370 to H'00000373 OVR0 221 H'00000374 to H'00000377 2 RM0 222 H'00000378 to H'0000037B 3 SLE0 223 H'0000037C to H'0000037F WDT ITI 224 H'00000380 to H'00000383 0 to 15 (0) IPRL (7-4) HCAN1 ERS1 228 H'00000390 to H'00000393 0 to 15 (0) IPRL (3-0) OVR1 229 H'00000394 to H'00000397 2 RM1 230 H'00000398 to H'0000039B 3 SLE1 231 H'0000039C to H'0000039F 7.3 Description of Registers 7.3.1 Interrupt Priority Registers A-L (IPRA-IPRL) 1 4 1 4 High Low Bit: 15 14 13 12 11 10 9 8 Initial value: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W: R/W: Interrupt priority registers A-L (IPRA-IPRL) are 16-bit readable/writable registers that set priority levels from 0 to 15 for IRQ interrupts and on-chip peripheral module interrupts. Correspondence between interrupt request sources and each of the IPRA-IPRL bits is shown in table 7.4. Rev. 5.00 Feb. 24, 2010 Page 88 of 950 REJ09B0177-0500 7. Interrupt Controller (INTC) Table 7.4 Interrupt Request Sources and IPRA-IPRL Bits Register 15-12 11-8 7-4 3-0 Interrupt priority register A IRQ0 IRQ1 IRQ2 IRQ3 Interrupt priority register B IRQ4 IRQ5 IRQ6 IRQ7 Interrupt priority register C DMAC0, 1 DMAC2, 3 ATU01 ATU02 Interrupt priority register D ATU03 ATU04 ATU11 ATU12 Interrupt priority register E ATU13 ATU21 ATU22 ATU23 Interrupt priority register F ATU31 ATU32 ATU41 ATU42 Interrupt priority register G ATU51 ATU52 ATU6 ATU7 Interrupt priority register H ATU81 ATU82 ATU83 ATU84 Interrupt priority register I ATU91 ATU92 ATU101 ATU102 Interrupt priority register J ATU11 CMT0, A/D0, MTAD0 CMT1, A/D1, MTAD1 A/D2 Interrupt priority register K SCI0/SSU0* SCI1 SCI2/SSU1* SCI3 Interrupt priority register L SCI4 HCAN0 WDT HCAN1 As indicated in table 7.4, four IRQ pins or groups of 4 on-chip peripheral modules are allocated to each register. Each of the corresponding interrupt priority ranks are established by setting a value from H'0 (0000) to H'F (1111) in each of the four-bit groups 15-12, 11-8, 7-4 and 3-0. Interrupt priority rank becomes level 0 (lowest) by setting H'0, and level 15 (highest) by setting H'F. If multiple on-chip peripheral modules are assigned to the same bit (DMAC0 and DMAC1, DMAC2 and DMAC3, CMT0, A/D0, and MTAD0, CMT1, A/D1, and MTAD1, SCI0 and SSU0*, and SCI2 and SSU1*), those multiple modules are set to the same priority rank. IPRA-IPRL are initialized to H'0000 by a reset, in hardware standby mode and in software standby mode. Note: * SSU: Synchronous Serial Communication Unit 7.3.2 Interrupt Control Register (ICR) Bit: 15 14 13 12 11 10 9 8 NMIL -- -- -- -- -- -- NMIE Initial value: * 0 0 0 0 0 0 0 R/W: R R R R R R R R/W Bit: 7 6 5 4 3 2 1 0 IRQ0S IRQ1S IRQ2S IRQ3S IRQ4S IRQ5S IRQ6S IRQ7S 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: R/W: Note: * When NMI input is high: 1; when NMI input is low: 0 ICR is a 16-bit register that sets the input signal detection mode of the external interrupt input pin NMI and IRQ0 -IRQ7 and indicates the input signal level at the NMI pin. A reset, hardware standby mode, and software standby mode initialize ICR. Rev. 5.00 Feb. 24, 2010 Page 89 of 950 REJ09B0177-0500 7. Interrupt Controller (INTC) * Bit 15--NMI Input Level (NMIL): Sets the level of the signal input at the NMI pin. This bit can be read to determine the NMI pin level. This bit cannot be modified. Bit 15: NMIL Description 0 NMI input level is low 1 NMI input level is high * Bits 14 to 9--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 8--NMI Edge Select (NMIE) Bit 8: NMIE Description 0 Interrupt request is detected on falling edge of NMI input (Initial value) 1 Interrupt request is detected on rising edge of NMI input * Bits 7 to 0--IRQ0-IRQ7 Sense Select (IRQ0S-IRQ7S): These bits set the IRQ0-IRQ7 interrupt request detection mode. Bits 7-0: IRQ0S-IRQ7S Description 0 Interrupt request is detected on low level of IRQ input 1 Interrupt request is detected on falling edge of IRQ input 7.3.3 (Initial value) IRQ Status Register (ISR) Bit: 15 14 13 12 11 10 9 8 -- -- -- -- -- -- -- -- Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 IRQ0F IRQ1F IRQ2F IRQ3F IRQ4F IRQ5F IRQ6F IRQ7F 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: R/W: ISR is a 16-bit register that indicates the interrupt request status of the external interrupt input pins IRQ0-IRQ7. When IRQ interrupts are set to edge detection, held interrupt requests can be withdrawn by writing 0 to IRQnF after reading IRQnF = 1. A reset, hardware standby mode, and software standby mode initialize ISR. * Bits 15 to 8--Reserved: These bits are always read as 0. The write value should always be 0. Rev. 5.00 Feb. 24, 2010 Page 90 of 950 REJ09B0177-0500 7. Interrupt Controller (INTC) * Bits 7 to 0--IRQ0-IRQ7 Flags (IRQ0F-IRQ7F): These bits display the IRQ0-IRQ7 interrupt request status. Bits 7-0: IRQ0F-IRQ7F Detection Setting 0 Level detection Description No IRQn interrupt request exists [Clearing condition] When IRQn input is high Edge detection No IRQn interrupt request was detected (Initial value) [Clearing conditions] 1 Level detection * When 0 is written after reading IRQnF = 1 * When IRQn interrupt exception processing has been executed An IRQn interrupt request exists Setting condition: When IRQn input is low Edge detection An IRQn interrupt request was detected Setting condition: When a falling edge occurs at an IRQn input Note: n = 7 to 0 7.4 Interrupt Operation 7.4.1 Interrupt Sequence The sequence of interrupt operations is explained below. Figure 7.2 is a flowchart of the operations. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects the highest priority interrupt in the interrupt requests sent, following the priority levels set in interrupt priority registers A-L (IPRA-IPRL). Lower-priority interrupts are ignored. They are held pending until interrupt requests designated as edge-detect type are accepted. For IRQ interrupts, however, withdrawal is possible by accessing the IRQ status register (ISR). See section 7.2.4, IRQ Interrupts, for details. Interrupts held pending due to edge detection are cleared by a power-on reset or a manual reset. If two of these interrupts have the same priority level or if multiple interrupts occur within a single module, the interrupt with the highest default priority or the highest priority within its IPR setting range (as indicated in table 7.3) is selected. 3. The interrupt controller compares the priority level of the selected interrupt request with the interrupt mask bits (I3-I0) in the CPU's status register (SR). If the request priority level is equal to or less than the level set in I3-I0, the request is ignored. If the request priority level is higher than the level in bits I3-I0, the interrupt controller accepts the interrupt and sends an interrupt request signal to the CPU. 4. When the interrupt controller accepts an interrupt, a low level is output from the IRQOUT pin. 5. The CPU detects the interrupt request sent from the interrupt controller when it decodes the next instruction to be executed. Instead of executing the decoded instruction, the CPU starts interrupt exception processing (figure 7.4). 6. SR and PC are saved onto the stack. 7. The priority level of the accepted interrupt is copied to the interrupt mask level bits (I3 to I0) in the status register (SR). 8. When the accepted interrupt is sensed by level or is from an on-chip peripheral module, a high level is output from the IRQOUT pin. When the accepted interrupt is sensed by edge, a high level is output from the IRQOUT pin at the point when the CPU starts interrupt exception processing instead of instruction execution as noted in 5 above. However, if the interrupt controller accepts an interrupt with a higher priority than one it is in the process of accepting, the IRQOUT pin will remain low. 9. The CPU reads the start address of the exception service routine from the exception vector table for the accepted interrupt, jumps to that address, and starts executing the program there. This jump is not a delay branch. Rev. 5.00 Feb. 24, 2010 Page 91 of 950 REJ09B0177-0500 7. Interrupt Controller (INTC) Program execution state No Interrupt? Yes No NMI? Yes User break? Yes No H-UDI interrupt? Yes No Level 15 interrupt? IRQOUT = low level*1 Yes Save SR to stack Yes Save PC to stack I3 to I0 level 14? No Copy accept-interrupt level to I3 to I0 Yes No Level 14 interrupt? Yes Level 1 interrupt? I3 to I0 level 13? Yes No IRQOUT = high level*2 No Yes No I3 to I0 = level 0? No Read exception vector table Branch to exception service routine Notes: I3 to I0: Interrupt mask bits of status register 1. As IRQOUT is synchronized with a peripheral clock P, it may be output later than a CPU interrupt request. 2. When the accepted interrupt is sensed by edge, the IRQOUT pin becomes high level at the point when the CPU starts interrupt exception processing instead of instruction execution (before SR is saved to the stack). If the interrupt controller has accepted another interrupt with a higher priority and has output an interrupt request to the CPU, the IRQOUT pin will remain low. Figure 7.2 Interrupt Sequence Flowchart Rev. 5.00 Feb. 24, 2010 Page 92 of 950 REJ09B0177-0500 7. Interrupt Controller (INTC) 7.4.2 Stack after Interrupt Exception Processing Figure 7.3 shows the stack after interrupt exception processing. Address 4n-8 PC*1 32 bits 4n-4 SR 32 bits SP*2 4n Notes: 1. 2. PC: Start address of the next instruction (return destination instruction) after the executing instruction Always be certain that SP is a multiple of 4 Figure 7.3 Stack after Interrupt Exception Processing Rev. 5.00 Feb. 24, 2010 Page 93 of 950 REJ09B0177-0500 7. Interrupt Controller (INTC) 7.5 Interrupt Response Time Table 7.5 indicates the interrupt response time, which is the time from the occurrence of an interrupt request until the interrupt exception processing starts and fetching of the first instruction of the interrupt service routine begins. Figure 7.4 shows an example of pipeline operation when an IRQ interrupt is accepted. Table 7.5 Interrupt Response Time Number of States Item Peripheral Module NMI IRQ Notes Synchronizing input signal (synchronized with peripheral clock P) with internal clock and DMAC activation judgment 0 or 6 1 to 4 6 to 9 For the number of states required for each interrupt, see the note below. Compare identified interrupt 2 priority with SR mask level 2 2 Wait for completion of sequence currently being executed by CPU X ( 0) The longest sequence is for interrupt or address-error exception processing (X = 4 + m1 + m2 + m3 + m4). If an interrupt-masking instruction follows, however, the time may be even longer. Time from start of interrupt 5 + m1 + m2 + m3 Performs the PC and SR exception processing until saves and vector address fetch of first instruction of fetch. exception service routine starts Interrupt Total: (7 or 13) (8 or 11) (13 to 16) response time + m1 + m2 + m3 + X + m1 + m2 + m3 + X + m1 + m2 + m3 + X Minimum: 10 11 16 Maximum: 17 + 2 (m1 + m2 + m3) + m4 15 + 2 20 + 2 (m1 + m2 + m3) + m4 (m1 + m2 + m3) + m4 Notes: When m1 = m2 = m3 = m4 = 1 m1-m4 are the number of states needed for the following memory accesses. m1: SR save (longword write) m2: PC save (longword write) m3: Vector address read (longword read) m4: Fetch first instruction of interrupt service routine * Number of states needed for synchronization and DMAC activation judgment The relations between numbers of states needed for synchronizing an input signal (synchronized with the peripheral clock P) with the internal clock and DMAC activation judgment and vector numbers are shown below. 0 state: 9, 10, 12, 13, 14, 72, 74, 76, 78, 189, 193, and 224 6 states: Peripheral module interrupts other than vector number 222 (HCAN0/RM0) and the above. 7 states: Interrupts with vector number 222 requested by HCAN0 Mailbox 0 (the needed states for this interrupt differs from other interrupts with vector number 222 since the interrupt by HCAN0 Mailbox 0 can activate the DMAC.) 6 states: Interrupts with vector number 222 other than the above The same number of states is needed to cancel interrupt sources. Rev. 5.00 Feb. 24, 2010 Page 94 of 950 REJ09B0177-0500 7. Interrupt Controller (INTC) If the necessary number of states is not secured after flag clear of the interrupt source, the interrupt may occur again. Interrupt acceptance IRQ 5 + m1 + m2 + m3 6 to 9 IRQ synchronization 2 3 m1 m2 1 m3 1 Interrupt controller operation Instruction (instruction replaced by interrupt exception processing) Overrun fetch Interrupt service routine start instruction F D E E M M E M E E F F D E Legend: F: Instruction fetch (instruction fetched from memory where program is stored). D: Instruction decoding (fetched instruction is decoded). E: Instruction execution (data operation and address calculation is performed according to the results of decoding). M: Memory access (data in memory is accessed). Figure 7.4 Example of Pipeline Operation when an IRQ Interrupt is Accepted Rev. 5.00 Feb. 24, 2010 Page 95 of 950 REJ09B0177-0500 7. Interrupt Controller (INTC) 7.6 Data Transfer with Interrupt Request Signals The following data transfer can be carried out using interrupt request signals: * Activate DMAC only, without generating CPU interrupt Among interrupt sources, those designated as DMAC activating sources are masked and not input to the INTC. The masking condition is as follows: Mask condition = DME * (DE0 * source selection 0 + DE1 * source selection 1 + DE2 * source selection 2 + DE3 * source selection 3) 7.6.1 Handling CPU Interrupt Sources, but Not DMAC Activating Sources 1. Either do not select the DMAC as a source, or clear the DME bit to 0. 2. Activating sources are applied to the CPU when interrupts occur. 3. The CPU clears interrupt sources with its interrupt processing routine and performs the necessary processing. 7.6.2 Handling DMAC Activating Sources but Not CPU Interrupt Sources 1. Select the DMAC as a source and set the DME bit to 1. CPU interrupt sources are masked regardless of the interrupt priority level register settings. 2. Activating sources are applied to the DMAC when interrupts occur. 3. The DMAC clears activating sources at the time of data transfer. Rev. 5.00 Feb. 24, 2010 Page 96 of 950 REJ09B0177-0500 8. User Break Controller (UBC) Section 8 User Break Controller (UBC) 8.1 Overview The user break controller (UBC) provides functions that simplify program debugging. Break conditions are set in the UBC and a user break interrupt is generated according to the conditions of the bus cycle generated by the CPU or DMAC. This function makes it easy to design an effective self-monitoring debugger, enabling the chip to easily debug programs without using a large in-circuit emulator. 8.1.1 Features The features of the user break controller are: * The following break compare conditions can be set: Address CPU cycle/DMA cycle Instruction fetch or data access Read or write Operand size: byte/word/longword * User break interrupt generated upon satisfying break conditions A user-designed user break interrupt exception processing routine can be run. * Select either to break in the CPU instruction fetch cycle before the instruction is executed or after. * Satisfaction of a break condition can be output to the UBCTRG pin. Rev. 5.00 Feb. 24, 2010 Page 97 of 950 REJ09B0177-0500 8. User Break Controller (UBC) 8.1.2 Block Diagram Figure 8.1 shows a block diagram of the UBC. UBCR UBBR UBAMRH UBARH UBAMRL UBARL Internal bus Bus interface Module bus Break condition comparator User break interrupt generating circuit Interrupt request Interrupt controller Trigger output generating circuit Legend: UBARH, UBARL: UBAMRH, UBAMRL: UBBR: UBCR: UBCTRG pin output User break address registers H, L User break address mask registers H, L User break bus cycle register User break control register Figure 8.1 User Break Controller Block Diagram 8.1.3 Register Configuration The UBC has the six registers shown in table 8.1. Break conditions are established using these registers. Table 8.1 Register Configuration Name Abbr. R/W Initial Value Address* Access Size User break address register H UBARH R/W H'0000 H'FFFFEC00 8, 16, 32 User break address register L UBARL R/W H'0000 H'FFFFEC02 8, 16, 32 User break address mask register H UBAMRH R/W H'0000 H'FFFFEC04 8, 16, 32 User break address mask register L UBAMRL R/W H'0000 H'FFFFEC06 8, 16, 32 User break bus cycle register UBBR R/W H'0000 H'FFFFEC08 8, 16, 32 User break control register UBCR R/W H'0000 H'FFFFEC0A 8, 16, 32 Note: * In register access, four cycles are required for byte access and word access, and eight cycles for longword access. Rev. 5.00 Feb. 24, 2010 Page 98 of 950 REJ09B0177-0500 8. User Break Controller (UBC) 8.2 Register Descriptions 8.2.1 User Break Address Register (UBAR) UBARH: Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 UBA31 UBA30 UBA29 UBA28 UBA27 UBA26 UBA25 UBA24 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 UBA23 UBA22 UBA21 UBA20 UBA19 UBA18 UBA17 UBA16 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 UBA15 UBA14 UBA13 UBA12 UBA11 UBA10 UBA9 UBA8 UBARL: Bit: Initial value: R/W: Bit: Initial value: R/W: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 UBA7 UBA6 UBA5 UBA4 UBA3 UBA2 UBA1 UBA0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The user break address register (UBAR) consists of user break address register H (UBARH) and user break address register L (UBARL). Both are 16-bit readable/writable registers. UBARH stores the upper bits (bits 31 to 16) of the address of the break condition, while UBARL stores the lower bits (bits 15 to 0). UBARH and UBARL are initialized to H'0000 by a power-on reset, in module standby mode, and in software standby mode. * UBARH Bits 15 to 0--User Break Address 31 to 16 (UBA31 to UBA16): These bits store the upper bit values (bits 31 to 16) of the address of the break condition. * UBARL Bits 15 to 0--User Break Address 15 to 0 (UBA15 to UBA0): These bits store the lower bit values (bits 15 to 0) of the address of the break condition. Rev. 5.00 Feb. 24, 2010 Page 99 of 950 REJ09B0177-0500 8. User Break Controller (UBC) 8.2.2 User Break Address Mask Register (UBAMR) UBAMRH: Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 UBM31 UBM30 UBM29 UBM28 UBM27 UBM26 UBM25 UBM24 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 UBM23 UBM22 UBM21 UBM20 UBM19 UBM18 UBM17 UBM16 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 UBM15 UBM14 UBM13 UBM12 UBM11 UBM10 UBM9 UBM8 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 UBM7 UBM6 UBM5 UBM4 UBM3 UBM2 UBM1 UBM0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W UBAMRL: Bit: Initial value: R/W: Bit: Initial value: R/W: The user break address mask register (UBAMR) consists of user break address mask register H (UBAMRH) and user break address mask register L (UBAMRL). Both are 16-bit readable/writable registers. UBAMRH designates whether to mask any of the break address bits established in UBARH, and UBAMRL designates whether to mask any of the break address bits established in UBARL. UBAMRH and UBAMRL are initialized to H'0000 by a power-on reset, in module standby mode, and in software standby mode. * UBAMRH Bits 15 to 0--User Break Address Mask 31 to 16 (UBM31 to UBM16): These bits designate whether to mask the corresponding break address 31 to 16 bits (UBA31 to UBA16) established in UBARH. * UBAMRL Bits 15 to 0--User Break Address Mask 15 to 0 (UBM15 to UBM0): These bits designate whether to mask the corresponding break address 15 to 0 bits (UBA15 to UBA0) established in UBARL. Bits 15-0: UBMn Description 0 Break address UBAn is included in the break conditions 1 Break address UBAn is not included in the break conditions Note: n = 31 to 0 Rev. 5.00 Feb. 24, 2010 Page 100 of 950 REJ09B0177-0500 (Initial value) 8. User Break Controller (UBC) 8.2.3 User Break Bus Cycle Register (UBBR) Bit: 15 14 13 12 11 10 9 8 -- -- -- -- -- -- -- -- Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 CP1 CP0 ID1 ID0 RW1 RW0 SZ1 SZ0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: R/W: The user break bus cycle register (UBBR) is a 16-bit readable/writable register that selects from among the following four break conditions: 1. 2. 3. 4. CPU cycle/DMA cycle Instruction fetch/data access Read/write Operand size (byte, word, longword) UBBR is initialized to H'0000 by a power on reset, in module standby mode, and in software standby mode. * Bits 15 to 8--Reserved: These bits are always read as 0. The write value should always be 0. * Bits 7 and 6--CPU Cycle/DMA Cycle Select (CP1, CP0): These bits designate break conditions for CPU cycles or DMA cycles. Bit 7: CP1 Bit 6: CP0 Description 0 0 No user break interrupt occurs 1 Break on CPU cycles 1 0 Break on DMA cycles 1 Break on both CPU and DMA cycles (Initial value) * Bits 5 and 4--Instruction Fetch/Data Access Select (ID1, ID0): These bits select whether to break on instruction fetch and/or data access cycles. Bit 5: ID1 Bit 4: ID0 Description 0 0 No user break interrupt occurs 1 Break on instruction fetch cycles 0 Break on data access cycles 1 Break on both instruction fetch and data access cycles 1 (Initial value) Rev. 5.00 Feb. 24, 2010 Page 101 of 950 REJ09B0177-0500 8. User Break Controller (UBC) * Bits 3 and 2--Read/Write Select (RW1, RW0): These bits select whether to break on read and/or write cycles. Bit 3: RW1 Bit 2: RW0 Description 0 0 No user break interrupt occurs 1 Break on read cycles 1 0 Break on write cycles 1 Break on both read and write cycles (Initial value) * Bits 1 and 0--Operand Size Select (SZ1, SZ0): These bits select operand size as a break condition. Bit 1: SZ1 Bit 0: SZ0 Description 0 0 Operand size is not a break condition 1 Break on byte access 1 0 Break on word access 1 Break on longword access (Initial value) Note: When breaking on an instruction fetch, clear the SZ0 bit to 0. All instructions are considered to be word-size accesses (even when there are instructions in on-chip memory and two instruction fetches are performed simultaneously in one bus cycle). Operand size is word for instructions or determined by the operand size specified for the CPU/DMAC data access. It is not determined by the bus width of the space being accessed. 8.2.4 User Break Control Register (UBCR) Bit: 15 14 13 12 11 10 9 8 -- -- -- -- -- -- -- -- Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 -- -- -- -- -- CKS1 CKS0 UBID Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W The user break control register (UBCR) is a 16-bit readable/writable register that (1) enables or disables user break interrupts and (2) sets the pulse width of the UBCTRG signal output in the event of a break condition match. UBCR is initialized to H'0000 by a power-on reset, in module standby mode, and in software standby mode. * Bits 15 to 3--Reserved: These bits are always read as 0. The write value should always be 0. * Bits 2 and 1--Clock Select 1 and 0 (CKS1, CKS0): These bits specify the pulse width of the UBCTRG signal output in the event of a condition match. Rev. 5.00 Feb. 24, 2010 Page 102 of 950 REJ09B0177-0500 8. User Break Controller (UBC) Bit 2: CKS1 Bit 1: CKS0 Description 0 0 UBCTRG pulse width is /4 1 UBCTRG pulse width is /4 0 UBCTRG pulse width is /8 1 UBCTRG pulse width is /16 1 (Initial value) Note: : Internal clock * Bit 0--User Break Disable (UBID): Enables or disables user break interrupt request generation in the event of a user break condition match. Bit 0: UBID Description 0 User break interrupt request is enabled 1 User break interrupt request is disabled 8.3 Operation 8.3.1 Flow of the User Break Operation (Initial value) The flow from setting of break conditions to user break interrupt exception processing is described below: 1. The user break addresses are set in the user break address register (UBAR), the desired masked bits in the addresses are set in the user break address mask register (UBAMR) and the breaking bus cycle type is set in the user break bus cycle register (UBBR). If even one of the three groups of the UBBR's CPU cycle/DMA cycle select bits (CP1, CP0), instruction fetch/data access select bits (ID1, ID0), and read/write select bits (RW1, RW0) is set to 00 (no user break generated), no user break interrupt will be generated even if all other conditions are in agreement. When using user break interrupts, always be certain to establish bit conditions for all of these three groups. 2. The UBC uses the method shown in figure 8.2 to judge whether set conditions have been fulfilled. When the set conditions are satisfied, the UBC sends a user break interrupt request signal to the interrupt controller (INTC). At the same time, a condition match signal is output at the UBCTRG pin with the pulse width set in bits CKS1 and CKS0. 3. The interrupt controller checks the accepted user break interrupt request signal's priority level. The user break interrupt has priority level 15, so it is accepted only if the interrupt mask level in bits I3-I0 in the status register (SR) is 14 or lower. When the I3-I0 bit level is 15, the user break interrupt cannot be accepted but it is held pending until user break interrupt exception processing can be carried out. Consequently, user break interrupts within NMI exception service routines cannot be accepted, since the I3-I0 bit level is 15. However, if the I3-I0 bit level is changed to 14 or lower at the start of the NMI exception service routine, user break interrupts become acceptable thereafter. Section 7, Interrupt Controller (INTC), describes the handling of priority levels in greater detail. 4. The INTC sends the user break interrupt request signal to the CPU, which begins user break interrupt exception processing upon receipt. See section 7.4, Interrupt Operation, for details on interrupt exception processing. Rev. 5.00 Feb. 24, 2010 Page 103 of 950 REJ09B0177-0500 8. User Break Controller (UBC) UBARH/UBARL UBAMRH/UBAMRL 32 32 Internal address bits 31-0 32 CP1 CP0 ID1 ID0 32 32 CPU cycle DMA cycle Instruction fetch User break interrupt Data access RW1 RW0 SZ1 SZ0 Read cycle Write cycle Byte size Word size Longword size UBID Figure 8.2 Break Condition Judgment Method 8.3.2 Break on On-Chip Memory Instruction Fetch Cycle On-chip memory (on-chip ROM and/or RAM) is always accessed as 32 bits in one bus cycle. Therefore, two instructions can be retrieved in one bus cycle when fetching instructions from on-chip memory. At such times, only one bus cycle is generated, but by setting the start addresses of both instructions in the user break address register (UBAR) it is possible to cause independent breaks. In other words, when wanting to effect a break using the latter of two addresses retrieved in one bus cycle, set the start address of that instruction in UBAR. The break will occur after execution of the former instruction. Rev. 5.00 Feb. 24, 2010 Page 104 of 950 REJ09B0177-0500 8. User Break Controller (UBC) 8.3.3 Program Counter (PC) Values Saved Break on Instruction Fetch: The program counter (PC) value saved to the stack in user break interrupt exception processing is the address that matches the break condition. The user break interrupt is generated before the fetched instruction is executed. If a break condition is set in an instruction fetch cycle placed immediately after a delayed branch instruction (delay slot), or on an instruction that follows an interrupt-disabled instruction, however, the user break interrupt is not accepted immediately, but the break condition establishing instruction is executed. The user break interrupt is accepted after execution of the instruction that has accepted the interrupt. In this case, the PC value saved is the start address of the instruction that will be executed after the instruction that has accepted the interrupt. Break on Data Access (CPU/DMA): The program counter (PC) value is the top address of the next instruction after the last instruction executed before the user break exception processing started. When data access (CPU/DMA) is set as a break condition, the place where the break will occur cannot be specified exactly. The break will occur at the instruction fetched close to where the data access that is to receive the break occurs. 8.4 Examples of Use 8.4.1 Break on CPU Instruction Fetch Cycle 1. Register settings: UBARH = H'0000 UBARL = H'0404 UBBR = H'0054 UBCR = H'0000 Conditions set: Address: H'00000404 Bus cycle: CPU, instruction fetch, read (operand size not included in conditions) Interrupt requests enabled A user break interrupt will occur before the instruction at address H'00000404. If it is possible for the instruction at H'00000402 to accept an interrupt, the user break exception processing will be executed after execution of that instruction. The instruction at H'00000404 is not executed. The PC value saved is H'00000404. 2. Register settings: UBARH = H'0015 UBARL = H'389C UBBR = H'0058 UBCR = H'0000 Conditions set: Address: H'0015389C Bus cycle: CPU, instruction fetch, write (operand size not included in conditions) Interrupt requests enabled A user break interrupt does not occur because the instruction fetch cycle is not a write cycle. 3. Register settings: UBARH = H'0003 UBARL = H'0147 UBBR = H'0054 UBCR = H'0000 Conditions set: Address: H'00030147 Bus cycle: CPU, instruction fetch, read (operand size not included in conditions) Interrupt requests enabled A user break interrupt does not occur because the instruction fetch was performed for an even address. However, if the first instruction fetch address after the branch is an odd address set by these conditions, user break interrupt exception processing will be carried out after address error exception processing. Rev. 5.00 Feb. 24, 2010 Page 105 of 950 REJ09B0177-0500 8. User Break Controller (UBC) 8.4.2 Break on CPU Data Access Cycle 1. Register settings: UBARH = H'0012 UBARL = H'3456 UBBR = H'006A UBCR = H'0000 Conditions set: Address: H'00123456 Bus cycle: CPU, data access, write, word Interrupt requests enabled A user break interrupt occurs when word data is written into address H'00123456. 2. Register settings: UBARH = H'00A8 UBARL = H'0391 UBBR = H'0066 UBCR = H'0000 Conditions set: Address: H'00A80391 Bus cycle: CPU, data access, read, word Interrupt requests enabled A user break interrupt does not occur because the word access was performed on an even address. 8.4.3 Break on DMA Cycle 1. Register settings: UBARH = H'0076 UBARL = H'BCDC UBBR = H'00A7 UBCR = H'0000 Conditions set: Address: H'0076BCDC Bus cycle: DMA, data access, read, longword Interrupt requests enabled A user break interrupt occurs when longword data is read from address H'0076BCDC. 2. Register settings: UBARH = H'0023 UBARL = H'45C8 UBBR = H'0094 UBCR = H'0000 Conditions set: Address: H'002345C8 Bus cycle: DMA, instruction fetch, read (operand size not included in conditions) Interrupt requests enabled A user break interrupt does not occur because no instruction fetch is performed in the DMA cycle. Rev. 5.00 Feb. 24, 2010 Page 106 of 950 REJ09B0177-0500 8. User Break Controller (UBC) 8.5 Usage Notes 8.5.1 Simultaneous Fetching of Two Instructions Two instructions may be simultaneously fetched from on-chip memory. If a break condition is set on the second of these two instructions but the contents of the UBC break condition registers are changed so as to alter the break condition immediately after the first of the two instructions is fetched, a user break interrupt will still occur when the second instruction is fetched. 8.5.2 Instruction Fetches at Branches When a conditional branch instruction or TRAPA instruction causes a branch, the order of instruction fetching and execution is as follows: 1. When branching with a conditional branch instruction: BT and BF instructions When branching with a TRAPA instruction: TRAPA instruction Instruction fetch order: Branch instruction fetch next instruction overrun fetch overrun fetch of instruction after next branch destination instruction fetch Instruction execution order: Branch instruction execution branch destination instruction execution 2. When branching with a delayed conditional branch instruction: BT/S and BF/S instructions Instruction fetch order: Branch instruction fetch next instruction fetch (delay slot) overrun fetch of instruction after next branch destination instruction fetch Instruction execution order: Branch instruction execution delay slot instruction execution branch destination instruction execution Thus, when a conditional branch instruction or TRAPA instruction causes a branch, the branch destination instruction will be fetched after an overrun fetch of the next instruction or the instruction after next. However, as the instruction that is the object of the break does not break until fetching and execution of the instruction have been confirmed, the overrun fetches described above do not become objects of a break. If data accesses are also included as break conditions in addition to instruction fetch breaks, a break will occur because the instruction overrun fetch is also regarded as satisfying the data break condition. Rev. 5.00 Feb. 24, 2010 Page 107 of 950 REJ09B0177-0500 8. User Break Controller (UBC) 8.5.3 Contention between User Break and Exception Processing If a user break is set for the fetch of a particular instruction, and exception processing with higher priority than a user break is in contention and is accepted in the decode stage for that instruction (or the next instruction), user break exception processing may not be performed after completion of the higher-priority exception service routine (on return by RTE). Thus, if a user break condition is applied to the branch destination instruction fetch after a branch (BRA, BRAF, BT, BF, BT/S, BF/S, BSR, BSRF, JMP, JSR, RTS, RTE, exception processing), and that branch instruction accepts exception processing with higher priority than a user break interrupt, user break exception processing is not performed after completion of the higher-priority exception service routine. Therefore, a user break condition should not be set for the fetch of the branch destination instruction after a branch. 8.5.4 Break at Non-Delay Branch Instruction Jump Destination When a branch instruction with no delay slot (including exception processing) jumps to the jump destination instruction on execution of the branch, a user break will not be generated even if a user break condition has been set for the first jump destination instruction fetch. 8.5.5 User Break Trigger Output Information on internal bus condition matches monitored by the UBC is output as UBCTRG. The trigger width can be set with clock select bits 1 and 0 (CKS1, CKS0) in the user break control register (UBCR). If a condition matches occurs again during trigger output, the UBCTRG pin continues to output a low level, and outputs a pulse of the length set in bits CKS1 and CKS0 from the cycle in which the last condition match occurs. The trigger output conditions differ from those in the case of a user break interrupt when a CPU instruction fetch condition is satisfied. When a condition occurs in an overrun fetch instruction as described in section 8.5.2, Instruction Fetch at Branches, a user break interrupt is not requested but a trigger is output from the UBCTRG pin. In other CPU data accesses and DMAC bus cycles, pulse output is performed under conditions similar to user break interrupt conditions. Setting the user break interrupt disable (UBID) bit to 1 in UBCR enables trigger output to be monitored externally without requesting a user break interrupt. 8.5.6 Module Standby After a power-on reset the UBC is in the module standby state, in which the clock supply is halted. When using the UBC, the module standby state must be cleared before making UBC register settings. Module standby is controlled by the System Control Register 2 (SYSCR2). See section 27.2.3, System Control Register 2 (SYSCR2), for further details. Rev. 5.00 Feb. 24, 2010 Page 108 of 950 REJ09B0177-0500 9. Bus State Controller (BSC) Section 9 Bus State Controller (BSC) 9.1 Overview The bus state controller (BSC) divides up the address spaces and outputs control for various types of memory. This enables memories like SRAM and ROM to be linked directly to the chip without external circuitry, simplifying system design and enabling high-speed data transfer to be achieved in a compact system. 9.1.1 Features The BSC has the following features: * Address space is divided into four spaces A maximum linear 2 Mbytes for on-chip ROM effective mode, and a maximum 4 Mbytes for on-chip ROM disabled mode, for address space CS0 A maximum linear 4 Mbytes for each of address spaces CS1-CS3 Bus width can be selected for each space (8 or 16 bits) Wait states can be inserted by software for each space Wait state insertion with WAIT pin in external memory space access Outputs control signals for each space according to the type of memory connected * On-chip ROM and RAM interfaces On-chip RAM access of 32 bits in 1 state On-chip ROM access of 32 bits in 1 state for a read and 2 states for a write Rev. 5.00 Feb. 24, 2010 Page 109 of 950 REJ09B0177-0500 9. Bus State Controller (BSC) 9.1.2 Block Diagram WAIT On-chip memory control unit RAMER Wait control unit WCR Module bus Bus interface BCR1 CS0-CS3 Area control unit BCR2 RD Memory control unit WRH, WRL BREQ BACK Bus arbitration control unit BSC Legend: WCR: Wait control register RAMER: RAM emulation register BCR1: BCR2: Bus control register 1 Bus control register 2 Figure 9.1 BSC Block Diagram Rev. 5.00 Feb. 24, 2010 Page 110 of 950 REJ09B0177-0500 Internal bus Figure 9.1 shows the BSC block diagram. 9. Bus State Controller (BSC) 9.1.3 Pin Configuration Table 9.1 shows the bus state controller pin configuration. Table 9.1 Pin Configuration Name Abbr. I/O Description Address bus A21-A0 O Address output Data bus D15-D0 I/O 16-bit data bus Chip select CS0-CS3 O Chip select signals indicating the area being accessed Read RD O Strobe that indicates the read cycle for ordinary space/multiplex I/O Upper write WRH O Strobe that indicates a write cycle to the upper 8 bits (D15-D8) Lower write WRL O Strobe that indicates a write cycle to the lower 8 bits (D7-D0) Wait WAIT I Wait state request signal Bus request BREQ I Bus release request input Bus acknowledge BACK O Bus use enable output Notes: 1. When an 8-bit bus width is selected for external space, WRL is enabled. 2. When a 16-bit bus width is selected for external space, WRH and WRL are enabled. 9.1.4 Register Configuration The BSC has four registers. These registers are used to control wait states, bus width, and interfaces with memories like ROM and SRAM, as well as refresh control. The register configurations are listed in table 9.2. All registers are 16 bits. All BSC registers are all initialized by a power-on reset, in hardware standby mode and in software standby mode. Values are retained in a manual reset. Table 9.2 Register Configuration Name Abbr. R/W Initial Value Address Access Size Bus control register 1 BCR1 R/W H'000F H'FFFFEC20 8, 16, 32 Bus control register 2 BCR2 R/W H'FFFF H'FFFFEC22 8, 16, 32 Wait state control register WCR R/W H'7777 H'FFFFEC24 8, 16, 32 RAM emulation register RAMER R/W H'0000 H'FFFFEC26 8, 16, 32 Note: In register access, four cycles are required for byte access and word access, and eight cycles for longword access. Rev. 5.00 Feb. 24, 2010 Page 111 of 950 REJ09B0177-0500 9. Bus State Controller (BSC) 9.1.5 Address Map Figure 9.2 shows the address format used by this LSI. A31-A24 A23, A22 A0 A21 Output address: Output from the address pins CS space selection: Decoded, outputs to when A31 to A24 = 00000000 Space selection: Not output externally; used to select the type of space On-chip ROM space or CS0 to CS3 space when 00000000 (H'00) Reserved (do not access) when 00000001 to 11111110 (H'01 to H'FE) On-chip peripheral module space or on-chip RAM space when 11111111 (H'FF) Figure 9.2 Address Format This chip uses 32-bit addresses: * Bits A31 to A24 are used to select the type of space and are not output externally. * Bits A23 and A22 are decoded and output as chip select signals (CS0 to CS3) for the corresponding areas when bits A31 to A24 are 00000000. * A21 to A0 are output externally. Table 9.3 shows the address map. Table 9.3 Address Map (SH7058S) * On-chip ROM enabled mode Address Space Memory Size Bus Width H'0000 0000 to H'000F FFFF On-chip ROM On-chip ROM 1 MB 32 bits H'0010 0000 to H'001F FFFF Reserved Reserved H'0020 0000 to H'003F FFFF CS0 space External space 2 MB 8, 16 bits*1 H'0040 0000 to H'007F FFFF CS1 space External space 4 MB 8, 16 bits*1 H'0080 0000 to H'00BF FFFF CS2 space External space 4 MB 8, 16 bits*1 H'00C0 0000 to H'00FF FFFF CS3 space External space 4 MB 8, 16 bits*1 H'0100 0000 to H'FFFE FFFF Reserved Reserved H'FFFF 0000 to H'FFFF BFFF On-chip RAM On-chip RAM 48 KB 32 bits H'FFFF C000 to H'FFFF FFFF On-chip peripheral module On-chip peripheral module 16 KB 8, 16 bits Rev. 5.00 Feb. 24, 2010 Page 112 of 950 REJ09B0177-0500 9. Bus State Controller (BSC) * On-chip ROM disabled mode Address Space Memory Size Bus Width H'0000 0000 to H'003F FFFF CS0 space External space 4 MB 8, 16 bits* H'0040 0000 to H'007F FFFF CS1 space External space 4 MB 8, 16 bits*1 H'0080 0000 to H'00BF FFFF CS2 space External space 4 MB 8, 16 bits*1 H'00C0 0000 to H'00FF FFFF CS3 space External space 4 MB 8, 16 bits*1 H'0100 0000 to H'FFFE FFFF Reserved Reserved H'FFFF 0000 to H'FFFF BFFF On-chip RAM On-chip RAM 48 KB 32 bits H'FFFF C000 to H'FFFF FFFF On-chip peripheral module On-chip peripheral module 16 KB 8, 16 bits 2 Notes: 1. Selected by on-chip register (BCR1) settings. 2. Selected by the mode pin. Do not access reserved spaces. Operation cannot be guaranteed if they are accessed. Table 9.4 Address Map (SH7059) * On-chip ROM enabled mode Address Space Memory Size Bus Width H'0000 0000 to H'0017 FFFF On-chip ROM On-chip ROM 1.5 MB 32 bits H'0018 0000 to H'001F FFFF Reserved Reserved H'0020 0000 to H'003F FFFF CS0 space External space 2 MB 8, 16 bits*1 H'0040 0000 to H'007F FFFF CS1 space External space 4 MB 8, 16 bits*1 H'0080 0000 to H'00BF FFFF CS2 space External space 4 MB 8, 16 bits*1 H'00C0 0000 to H'00FF FFFF CS3 space External space 4 MB 8, 16 bits*1 H'0100 0000 to H'FFFE 7FFF Reserved Reserved H'FFFF 8000 to H'FFFF BFFF On-chip RAM On-chip RAM 80 KB 32 bits H'FFFF C000 to H'FFFF FFFF On-chip peripheral module On-chip peripheral module 16 KB 8, 16 bits Address Space Memory Size Bus Width H'0000 0000 to H'003F FFFF CS0 space External space 4 MB 8, 16 bits* H'0040 0000 to H'007F FFFF CS1 space External space 4 MB 8, 16 bits*1 H'0080 0000 to H'00BF FFFF CS2 space External space 4 MB 8, 16 bits*1 H'00C0 0000 to H'00FF FFFF CS3 space External space 4 MB 8, 16 bits*1 H'0100 0000 to H'FFFE 7FFF Reserved Reserved H'FFFF 8000 to H'FFFF BFFF On-chip RAM On-chip RAM 80 KB 32 bits H'FFFF C000 to H'FFFF FFFF On-chip peripheral module On-chip peripheral module 16 KB 8, 16 bits * On-chip ROM disabled mode 2 Notes: 1. Selected by on-chip register (BCR1) settings. 2. Selected by the mode pin. Do not access reserved spaces. Operation cannot be guaranteed if they are accessed. Rev. 5.00 Feb. 24, 2010 Page 113 of 950 REJ09B0177-0500 9. Bus State Controller (BSC) Table 9.5 Number of Access Cycles for Peripheral Module Registers Module Name Bus Width Number of Access Cycles ROM 8 Byte: 4 UBC, WDT, BSC, DMAC, INTC 16 Byte and word: 4, longword: 8 SCI 8 Byte: 8 to 11, word: 16 to 19 ATU, APC, CMT, PORT, HUDI, CPG, and power- 16 down state Byte and word: 8 to 11, longword: 16 to 19 AD, MTAD 8 Byte: 12 to 15, word: 24 to 27 SSU* 16 Byte and word: 12 to 15, longword: 24 to 27 HCAN 16 Byte and word: 12 to 15 + wait Note: * SSU: Synchronous Serial Communication Unit 9.2 Description of Registers 9.2.1 Bus Control Register 1 (BCR1) Bit: 15 14 13 12 11 10 9 8 -- -- -- -- -- -- -- -- Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 -- -- -- -- A3SZ A2SZ A1SZ A0SZ Initial value: 0 0 0 0 1 1 1 1 R/W: R R R R R/W R/W R/W R/W BCR1 is a 16-bit readable/writable register that specifies the bus size of the CS spaces. Write bits 15-0 of BCR1 during the initialization stage after a power-on reset, and do not change the values thereafter. In on-chip ROM enabled mode, do not access any of the CS spaces until after completion of register initialization. In on-chip ROM disabled mode, do not access any CS space other than CS0 until after completion of register initialization. BCR1 is initialized to H'000F by a power-on reset, in hardware standby mode, and in software standby mode. It is not initialized by a manual reset. * Bits 15-4--Reserved: The write value should always be 0. Operation cannot be guaranteed if 1 is written to these bits. * Bit 3--CS3 Space Size Specification (A3SZ): Specifies the CS3 space bus size. A 0 setting specifies byte (8-bit) size, and a 1 setting specifies word (16-bit) size. Bit 3: A3SZ Description 0 Byte (8-bit) size 1 Word (16-bit) size Rev. 5.00 Feb. 24, 2010 Page 114 of 950 REJ09B0177-0500 (Initial value) 9. Bus State Controller (BSC) * Bit 2--CS2 Space Size Specification (A2SZ): Specifies the CS2 space bus size. A 0 setting specifies byte (8-bit) size, and a 1 setting specifies word (16-bit) size. Bit 2: A2SZ Description 0 Byte (8-bit) size 1 Word (16-bit) size (Initial value) * Bit 1--CS1 Space Size Specification (A1SZ): Specifies the CS1 space bus size. A 0 setting specifies byte (8-bit) size, and a 1 setting specifies word (16-bit) size. Bit 1: A1SZ Description 0 Byte (8-bit) size 1 Word (16-bit) size (Initial value) * Bit 0--CS0 Space Size Specification (A0SZ): Specifies the CS0 space bus size A 0 setting specifies byte (8-bit) size, and a 1 setting specifies word (16-bit) size. Bit 0: A0SZ Description 0 Byte (8-bit) size 1 Word (16-bit) size (Initial value) Note: A0SZ is valid only in on-chip ROM enabled mode. In on-chip ROM disabled mode, the CS0 space bus size is specified by the mode pin. 9.2.2 Bus Control Register 2 (BCR2) Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 IW31 IW30 IW21 IW20 IW11 IW10 IW01 IW00 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 CW3 CW2 CW1 CW0 SW3 SW2 SW1 SW0 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W BCR2 is a 16-bit readable/writable register that specifies the number of idle cycles and CS signal assert extension of each CS space. BCR2 is initialized to H'FFFF by a power-on reset, in hardware standby mode, and in software standby mode. It is not initialized by a manual reset. * Bits 15-8--Idles between Cycles (IW31, IW30, IW21, IW20, IW11, IW10, IW01, IW00): These bits specify idle cycles inserted between consecutive accesses when the second one is to a different CS area after a read. Idles are used to prevent data conflict between ROM (and other memories, which are slow to turn the read data buffer off), fast memories, and I/O interfaces. Even when access is to the same area, idle cycles must be inserted when a read access is followed immediately by a write access. The idle cycles to be inserted comply with the area specification of the previous access. Refer to section 9.4, Waits between Access Cycles, for details. Rev. 5.00 Feb. 24, 2010 Page 115 of 950 REJ09B0177-0500 9. Bus State Controller (BSC) IW31, IW30 specify the idle between cycles for CS3 space; IW21, IW20 specify the idle between cycles for CS2 space; IW11, IW10 specify the idle between cycles for CS1 space and IW01, IW00 specify the idle between cycles for CS0 space. Bit 15: IW31 Bit 14: IW30 Description 0 0 No CS3 space idle cycle 1 Inserts one idle cycle 0 Inserts two idle cycles 1 Inserts three idle cycles Bit 12: IW20 Description 1 Bit 13: IW21 0 0 No CS2 space idle cycle 1 Inserts one idle cycle 0 Inserts two idle cycles 1 Inserts three idle cycles Bit 11: IW11 Bit 10: IW10 Description 0 0 No CS1 space idle cycle 1 Inserts one idle cycle 0 Inserts two idle cycles 1 Inserts three idle cycles Bit 9: IW01 Bit 8: IW00 Description 0 0 No CS0 space idle cycle 1 Inserts one idle cycle 0 Inserts two idle cycles 1 Inserts three idle cycles 1 1 1 (Initial value) (Initial value) (Initial value) (Initial value) * Bits 7-4--Idle Specification for Continuous Access (CW3, CW2, CW1, CW0): The continuous access idle specification makes insertions to clearly delineate the bus intervals by once negating the CSn signal when performing consecutive accesses to the same CS space. When a write immediately follows a read, the number of idle cycles inserted is the larger of the two values specified by IW and CW. Refer to section 9.4, Waits between Access Cycles, for details. CW3 specifies the continuous access idles for CS3 space; CW2 specifies the continuous access idles for CS2 space; CW1 specifies the continuous access idles for CS1 space and CW0 specifies the continuous access idles for CS0 space. Bit 7: CW3 Description 0 No CS3 space continuous access idle cycles 1 One CS3 space continuous access idle cycle Bit 6: CW2 Description 0 No CS2 space continuous access idle cycles 1 One CS2 space continuous access idle cycle Rev. 5.00 Feb. 24, 2010 Page 116 of 950 REJ09B0177-0500 (Initial value) (Initial value) 9. Bus State Controller (BSC) Bit 5: CW1 Description 0 No CS1 space continuous access idle cycles 1 One CS1 space continuous access idle cycle Bit 4: CW0 Description 0 No CS0 space continuous access idle cycles 1 One CS0 space continuous access idle cycle (Initial value) (Initial value) * Bits 3-0--CS Assert Extension Specification (SW3, SW2, SW1, SW0): The CS assert cycle extension specification is for making insertions to prevent extension of the RD signal, WRH signal, or WRL signal assert period beyond the length of the CSn signal assert period. Extended cycles insert one cycle before and after each bus cycle, which simplifies interfaces with external devices and also has the effect of extending the write data hold time. Refer to section 9.3.3, CS Assert Period Extension, for details. SW3 specifies the CS assert extension for CS3 space access; SW2 specifies the CS assert extension for CS2 space access; SW1 specifies the CS assert extension for CS1 space access and SW0 specifies the CS assert extension for CS0 space access. Bit 3: SW3 Description 0 No CS3 space CS assert extension 1 CS3 space CS assert extension Bit 2: SW2 Description 0 No CS2 space CS assert extension 1 CS2 space CS assert extension Bit 1: SW1 Description 0 No CS1 space CS assert extension 1 CS1 space CS assert extension Bit 0: SW0 Description 0 No CS0 space CS assert extension 1 CS0 space CS assert extension 9.2.3 (Initial value) (Initial value) (Initial value) (Initial value) Wait Control Register (WCR) Bit: 15 14 13 12 11 10 9 8 -- W32 W31 W30 -- W22 W21 W20 Initial value: 0 1 1 1 0 1 1 1 R/W: R R/W R/W R/W R R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 -- W12 W11 W10 -- W02 W01 W00 Initial value: 0 1 1 1 0 1 1 1 R/W: R R/W R/W R/W R R/W R/W R/W Rev. 5.00 Feb. 24, 2010 Page 117 of 950 REJ09B0177-0500 9. Bus State Controller (BSC) WCR is a 16-bit readable/writable register that specifies the number of wait cycles for each CS space. WCR is initialized to H'7777 by a power-on reset, in hardware standby mode, and in software standby mode. It is not initialized by a manual reset. * Bit 15--Reserved * Bits 14-12--CS3 Space Wait Specification (W32, W31, W30): These bits specify the number of waits for CS3 space access. Bit 14: W32 Bit 13: W31 Bit 12: W30 Description 0 0 0 No wait (external wait input disabled) 0 0 1 1 wait external wait input enabled 1 1 7 wait external wait input enabled 1 (Initial value) * Bit 11--Reserved * Bits 10-8--CS2 Space Wait Specification (W22, W21, W20): These bits specify the number of waits for CS2 space access. Bit 10: W22 Bit 9: W21 Bit 8: W20 Description 0 0 0 No wait (external wait input disabled) 0 0 1 1 wait external wait input enabled 1 1 7 wait external wait input enabled 1 (Initial value) * Bit 7--Reserved * Bits 6-4--CS1 Space Wait Specification (W12, W11, W10): These bits specify the number of waits for CS1 space access. Bit 6: W12 Bit 5: W11 Bit 4: W10 Description 0 0 0 No wait (external wait input disabled) 0 0 1 1 wait external wait input enabled 1 1 7 wait external wait input enabled 1 (Initial value) * Bit 3--Reserved * Bits 2-0--CS0 Space Wait Specification (W02, W01, W00): These bits specify the number of waits for CS0 space access. Bit 2: W02 Bit 1: W01 Bit 0: W00 Description 0 0 0 No wait (external wait input disabled) 0 0 1 1 wait external wait input enabled 1 1 7 wait external wait input enabled 1 Rev. 5.00 Feb. 24, 2010 Page 118 of 950 REJ09B0177-0500 (Initial value) 9. Bus State Controller (BSC) 9.2.4 RAM Emulation Register (RAMER) * SH7058S Bit: 15 14 13 12 11 10 9 8 -- -- -- -- -- -- -- -- Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 -- -- -- -- RAMS RAM2 RAM1 RAM0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R/W R/W R/W R/W The RAM emulation register (RAMER) is a 16-bit readable/writable register that selects the RAM area to be used when emulating realtime programming of flash memory. RAMER is initialized to H'0000 by a power-on reset, in hardware standby mode, and in software standby mode. It is not initialized by a manual reset. Note: To ensure correct operation of the RAM emulation function, the ROM for which RAM emulation is performed should not be accessed immediately after this register has been modified. Operation cannot be guaranteed if such an access is made. * Bits 15 to 4--Reserved: Only 0 should be written to these bits. Operation cannot be guaranteed if 1 is written. * Bit 3--RAM Select (RAMS): Used together with bits 2 to 0 to select or deselect flash memory emulation by RAM (table 9.6). When 1 is written to this bit, all flash memory blocks are write/erase-protected. This bit is ignored in modes with on-chip ROM disabled. * Bits 2 to 0--RAM Area Specification (RAM2 to RAM0): These bits are used together with the RAMS bit to designate the flash memory area to be overlapped onto RAM (table 9.6). Table 9.6 RAM Area Setting Method (SH7058S) RAM Area Bit 3: RAMS Bit 2: RAM2 Bit 1: RAM1 Bit 0: RAM0 H'FFFF0000 to H'FFFF0FFF 0 * * * H'00000000 to H'00000FFF 1 0 0 0 H'00001000 to H'00001FFF 1 0 0 1 H'00002000 to H'00002FFF 1 0 1 0 H'00003000 to H'00003FFF 1 0 1 1 H'00004000 to H'00004FFF 1 1 0 0 H'00005000 to H'00005FFF 1 1 0 1 H'00006000 to H'00006FFF 1 1 1 0 H'00007000 to H'00007FFF 1 1 1 1 Legend: *: Don't care Rev. 5.00 Feb. 24, 2010 Page 119 of 950 REJ09B0177-0500 9. Bus State Controller (BSC) * SH7059 Bit: 15 14 13 12 11 10 9 8 -- -- -- -- -- -- -- -- Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 -- -- -- -- RAMS -- -- RAM0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R/W R R R/W The RAM emulation register (RAMER) is a 16-bit readable/writable register that selects the RAM area to be used when emulating realtime programming of flash memory. RAMER is initialized to H'0000 by a power-on reset, in hardware standby mode, and in software standby mode. It is not initialized by a manual reset. Note: To ensure correct operation of the RAM emulation function, the ROM for which RAM emulation is performed should not be accessed immediately after this register has been modified. Operation cannot be guaranteed if such an access is made. * Bits 15 to 4, 2, 1--Reserved: Only 0 should be written to these bits. Operation cannot be guaranteed if 1 is written. * Bit 3--RAM Select (RAMS): Used together with bit 0 to select or deselect flash memory emulation by RAM (table 9.7). When 1 is written to this bit, all flash memory blocks are write/erase-protected. This bit is ignored in modes with on-chip ROM disabled. * Bit 0--RAM Area Specification (RAM0): These bits are used together with the RAMS bit to designate the flash memory area to be overlapped onto RAM (table 9.7). Table 9.7 RAM Area Setting Method (SH7059) RAM Area H'FFFE8000 to H'FFFEBFFF Bit 3: RAMS Bit 0: RAM0 0 * 1 3 1 0 2 3 1 1 H'00000000 to H'00003FFF* * H'00004000 to H'00007FFF* * Legend: *: Don't care Notes: 1. Simultaneously, H'00100000 to H'00103FFF is also overlapped by the same RAM area. 2. Simultaneously, H'00104000 to H'00107FFF is also overlapped by the same RAM area. 3. To prevent overlapping use of a RAM area, either leave one of the affected address areas unused or temporarily disable the RAM emulation function by changing the setting of RAMS to 0 before accessing the address area for which overlapping use is to be avoided. Rev. 5.00 Feb. 24, 2010 Page 120 of 950 REJ09B0177-0500 9. Bus State Controller (BSC) 9.3 Accessing External Space A strobe signal is output in external space accesses to provide primarily for SRAM or ROM direct connections. 9.3.1 Basic Timing Figure 9.3 shows the basic timing of external space access. External access bus cycles are performed in 2 states. T1 T2 CK Address CSn RD Read Data , Write Data Figure 9.3 Basic Timing of External Space Access Rev. 5.00 Feb. 24, 2010 Page 121 of 950 REJ09B0177-0500 9. Bus State Controller (BSC) 9.3.2 Wait State Control The number of wait states inserted into external space access states can be controlled using the WCR settings (figure 9.4). The specified number of TW cycles are inserted as software cycles at the timing shown in figure 9.4. T1 TW T2 CK Address Read Data , Write Data Figure 9.4 Wait State Timing of External Space Access (Software Wait Only) When the wait is specified by software using WCR, the wait input WAIT signal from outside is sampled. Figure 9.5 shows the WAIT signal sampling. The WAIT signal is sampled at the clock rise one cycle before the clock rise when the Tw state shifts to the T2 state. When using external waits, use a WCR setting of 1 state or more when extending CS assertion, and 2 states or more otherwise. T1 TW TW TW0 T2 CK Address Read Data , Write Data Figure 9.5 Wait State Timing of External Space Access (Two Software Wait States + WAIT Signal Wait State) Rev. 5.00 Feb. 24, 2010 Page 122 of 950 REJ09B0177-0500 9. Bus State Controller (BSC) 9.3.3 CS Assert Period Extension Idle cycles can be inserted to prevent extension of the RD, WRH, or WRL signal assert period beyond the length of the CSn signal assert period by setting the SW3-SW0 bits of BCR2. This allows for flexible interfaces with external circuitry. The timing is shown in figure 9.6. Th and Tf cycles are added respectively before and after the ordinary cycle. Only CSn is asserted in these cycles; RD, WRH, and WRL signals are not. Further, data is extended up to the Tf cycle, which is effective for gate arrays and the like, which have slower write operations. Th T1 T2 Tf CK Address Read Data , Write Data Figure 9.6 CS Assert Period Extension Function 9.4 Waits between Access Cycles When a read from a slow device is completed, data buffers may not go off in time to prevent data conflicts with the next access. If there is a data conflict during memory access, the problem can be solved by inserting a wait in the access cycle. To enable detection of bus cycle starts, waits can be inserted between access cycles during continuous accesses of the same CS space by negating the CSn signal once. 9.4.1 Prevention of Data Bus Conflicts For the two cases of write cycles after read cycles, and read cycles for a different area after read cycles, waits are inserted so that the number of idle cycles specified by the IW31 to IW00 bits of BCR2 occur. When idle cycles already exist between access cycles, only the number of empty cycles remaining beyond the specified number of idle cycles are inserted. Figure 9.7 shows an example of idles between cycles. In this example, one idle between CSn space cycles has been specified, so when a CSm space write immediately follows a CSn space read cycle, one idle cycle is inserted. Rev. 5.00 Feb. 24, 2010 Page 123 of 950 REJ09B0177-0500 9. Bus State Controller (BSC) T1 T2 Tidle T1 T2 CK Address , Data CSn space read Idle cycle CSm space write Figure 9.7 Idle Cycle Insertion Example IW31 and IW30 specify the number of idle cycles required after a CS3 space read either to read other external spaces, or for this chip, to perform write accesses. In the same manner, IW21 and IW20 specify the number of idle cycles after a CS2 space read, IW11 and IW10, the number after a CS1 space read, and IW01 and IW00, the number after a CS0 space read. 0 to 3 idle cycles can be specified. 9.4.2 Simplification of Bus Cycle Start Detection For consecutive accesses to the same CS space, waits are inserted to provide the number of idle cycles designated by bits CW3 to CW0 in BCR2. However, in the case of a write cycle after a read, the number of idle cycles inserted will be the larger of the two values designated by the IW and CW bits. When idle cycles already exist between access cycles, waits are not inserted. Figure 9.8 shows an example. A continuous access idle is specified for CSn space, and CSn space is consecutively write-accessed. Rev. 5.00 Feb. 24, 2010 Page 124 of 950 REJ09B0177-0500 9. Bus State Controller (BSC) T1 T2 Tidle T1 T2 CK Address , Data CSn space access Idle cycle CSn space access Figure 9.8 Same Space Consecutive Access Idle Cycle Insertion Example 9.5 Bus Arbitration This LSI has a bus arbitration function that, when a bus release request is received from an external device, releases the bus to that device. It also has three internal bus masters, the CPU, DMAC, and AUD. The priority ranking for determining bus right transfer between these bus masters is: Bus right request from external device > AUD > DMAC > CPU Therefore, an external device that generates a bus request is given priority even if the request is made during a DMAC burst transfer. The AUD does not acquire the bus during DMAC burst transfer, but at the end of the transfer. When the CPU has possession of the bus, the AUD has higher priority than the DMAC for bus acquisition. A bus request by an external device should be input at the BREQ pin. The signal indicating that the bus has been released is output from the BACK pin. Figure 9.9 shows the bus right release procedure. Rev. 5.00 Feb. 24, 2010 Page 125 of 950 REJ09B0177-0500 9. Bus State Controller (BSC) This LSI External device BREQ = Low BREQ accepted Bus right request Strobe pin: high-level output BACK confirmation Address, data, strobe pin: high impedance BACK = Low Bus right release response Bus right release status Bus right acquisition Figure 9.9 Bus Right Release Procedure 9.6 Memory Connection Examples Figures 9.10-9.13 show examples of the memory connections. 32 K x 8-bit ROM This LSI CSn CE RD OE A0-A14 D0-D7 A0-A14 I/O0-I/O7 Figure 9.10 Example of 8-Bit Data Bus Width ROM Connection 256 K x 16-bit ROM This LSI CSn CE RD OE A0 A1-A18 A0-A17 D0-D15 I/O0-I/O15 Figure 9.11 Example of 16-Bit Data Bus Width ROM Connection Rev. 5.00 Feb. 24, 2010 Page 126 of 950 REJ09B0177-0500 9. Bus State Controller (BSC) 128 K x 8-bit SRAM This LSI CSn CE RD OE A0-A16 A0-A16 WRL WE D0-D7 I/O0-I/O7 Figure 9.12 Example of 8-Bit Data Bus Width SRAM Connection This LSI CSn RD A0 A1-A17 WRH D8-D15 128 K x 8-bit SRAM CS OE A0-A16 WE I/O0-I/O7 WRL D0-D7 CS OE A0-A16 WE I/O0-I/O7 Figure 9.13 Example of 16-Bit Data Bus Width SRAM Connection Rev. 5.00 Feb. 24, 2010 Page 127 of 950 REJ09B0177-0500 9. Bus State Controller (BSC) Rev. 5.00 Feb. 24, 2010 Page 128 of 950 REJ09B0177-0500 10. Direct Memory Access Controller (DMAC) Section 10 Direct Memory Access Controller (DMAC) 10.1 Overview This LSI includes an on-chip four-channel direct memory access controller (DMAC). The DMAC can be used in place of the CPU to perform high-speed data transfers among external memories, memory-mapped external devices, and on-chip peripheral modules (except for the DMAC, BSC, and UBC). Using the DMAC reduces the burden on the CPU and increases the operating efficiency of the chip as a whole. 10.1.1 Features The DMAC has the following features: * * * * * * * * * * * Four channels 4-Gbyte address space in the architecture 8-, 16-, or 32-bit selectable data transfer length Maximum of 16 M (16,777,216) transfers Address modes Both the transfer source and transfer destination are accessed by address. There are two transfer modes: direct address and indirect address. Direct address transfer mode: Values set in a DMAC internal register indicate the accessed address for both the transfer source and transfer destination. Two bus cycles are required for one data transfer. Indirect address transfer mode: The value stored at the location pointed to by the address set in the DMAC internal transfer source register is used as the address. Operation is otherwise the same as for direct access. This function can only be set for channel 3. Four bus cycles are required for one data transfer. Channel function: Dual address mode is supported on all channels. Channel 2 has a source address reload function that reloads the source address every fourth transfer. Direct address transfer mode or indirect address transfer mode can be specified for channel 3. Reload function Enables automatic reloading of the value set in the first source address register every fourth DMA transfer. This function can be executed on channel 2 only. Transfer requests There are two DMAC transfer activation requests, as indicated below. Requests from on-chip peripheral modules: Transfer requests from on-chip modules such as the SCI or A/D. These can be received by all channels. Auto-request: The transfer request is generated automatically within the DMAC. Selectable bus modes: Cycle-steal mode or burst mode Fixed DMAC channel priority ranking CPU can be interrupted when the specified number of data transfers are complete. Rev. 5.00 Feb. 24, 2010 Page 129 of 950 REJ09B0177-0500 10. Direct Memory Access Controller (DMAC) 10.1.2 Block Diagram Figure 10.1 is a block diagram of the DMAC. DMAC module Circuit control SARn On-chip RAM Register control DARn Peripheral bus On-chip peripheral module Internal bus On-chip ROM DMATCRn Activation control CHCRn DMAOR HCAN0 ATU-II SCI0-SCI4 A/D converter 0-2 SSU0*, SSU1* DEIn Request priority control External ROM External I/O (memory mapped) External bus External RAM Bus interface Bus state controller Legend: DMA source address register SARn: DMA destination address register DARn: DMATCRn: DMA transfer count register DMA channel control register CHCRn: DMA operation register DMAOR: Notes: n = 0 to 3 * SSU: Synchronous Serial Communication Unit Figure 10.1 DMAC Block Diagram 10.1.3 Register Configuration Table 10.1 summarizes the DMAC registers. The DMAC has a total of 17 registers. Each channel has four registers, and one overall DMAC control register is shared by all channels. Rev. 5.00 Feb. 24, 2010 Page 130 of 950 REJ09B0177-0500 10. Direct Memory Access Controller (DMAC) Table 10.1 DMAC Registers Channel Name Abbr. R/W Initial Value Address Register Size Access Size 0 DMA source address SAR0 register 0 R/W Undefined H'FFFFECC0 32 bits 16, 32*2 DMA destination address register 0 DAR0 R/W Undefined H'FFFFECC4 32 bits 16, 32*2 DMA transfer count register 0 DMATCR0 R/W Undefined H'FFFFECC8 32 bits 16, 32*2 1 2 3 Shared Notes: 1. 2. 3. 4. DMA channel control CHCR0 register 0 R/W* H'00000000 H'FFFFECCC 32 bits 16, 32*2 DMA source address SAR1 register 1 R/W Undefined H'FFFFECD0 32 bits 16, 32*2 DMA destination address register 1 DAR1 R/W Undefined H'FFFFECD4 32 bits 16, 32*2 DMA transfer count register 1 DMATCR1 R/W Undefined H'FFFFECD8 32 bits 16, 32*3 DMA channel control CHCR1 register 1 R/W*1 H'00000000 H'FFFFECDC 32 bits 16, 32*2 DMA source address SAR2 register 2 R/W Undefined H'FFFFECE0 32 bits 16, 32*2 DMA destination address register 2 DAR2 R/W Undefined H'FFFFECE4 32 bits 16, 32*2 DMA transfer count register 2 DMATCR2 R/W Undefined H'FFFFECE8 32 bits 16, 32*3 DMA channel control CHCR2 register 2 R/W*1 H'00000000 H'FFFFECEC 32 bits 16, 32*2 DMA source address SAR3 register 3 R/W Undefined H'FFFFECF0 32 bits 16, 32*2 DMA destination address register 3 DAR3 R/W Undefined H'FFFFECF4 32 bits 16, 32*2 DMA transfer count register 3 DMATCR3 R/W Undefined H'FFFFECF8 32 bits 16, 32*3 DMA channel control CHCR3 register 3 R/W*1 H'00000000 H'FFFFECFC 32 bits 16, 32*2 DMA operation register R/W*1 H'0000 H'FFFFECB0 16 bits 16*4 DMAOR 1 Word access to a register takes four cycles, and longword access eight cycles. Do not attempt to access an empty address, as operation canot be guaranteed if this is done. Write 0 after reading 1 in bit 1 of CHCR0-CHCR3 and in bits 1 and 2 of DMAOR to clear flags. No other writes are allowed. For 16-bit access of SAR0-SAR3, DAR0-DAR3, and CHCR0-CHCR3, the 16-bit value on the side not accessed is held. DMATCR has a 24-bit configuration: bits 0-23. Writing to the upper 8 bits (bits 24-31) is invalid, and these bits always read 0. Do not use 32-bit access on DMAOR. Rev. 5.00 Feb. 24, 2010 Page 131 of 950 REJ09B0177-0500 10. Direct Memory Access Controller (DMAC) 10.2 Register Descriptions 10.2.1 DMA Source Address Registers 0-3 (SAR0-SAR3) Bit: 31 30 29 28 27 26 25 24 Initial value: -- -- -- -- -- -- -- -- R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 ... ... 2 1 0 ... ... R/W: Bit: Initial value: R/W: -- -- -- ... ... -- -- -- R/W R/W R/W ... ... R/W R/W R/W DMA source address registers 0-3 (SAR0-SAR3) are 32-bit readable/writable registers that specify the source address of a DMA transfer. These registers have a count function, and during a DMA transfer, they indicate the next source address. Specify a 16-bit boundary when performing 16-bit data transfers, and a 32-bit boundary when performing 32-bit data transfers. Operation cannot be guaranteed if any other addresses are set. The initial value after a power-on reset and in standby mode is undefined. 10.2.2 DMA Destination Address Registers 0-3 (DAR0-DAR3) Bit: 31 30 29 28 27 26 25 24 Initial value: -- -- -- -- -- -- -- -- R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 ... ... 2 1 0 ... ... R/W: Bit: Initial value: R/W: -- -- -- ... ... -- -- -- R/W R/W R/W ... ... R/W R/W R/W DMA destination address registers 0-3 (DAR0-DAR3) are 32-bit readable/writable registers that specify the destination address of a DMA transfer. These registers have a count function, and during a DMA transfer, they indicate the next destination address. Specify a 16-bit boundary when performing 16-bit data transfers, and a 32-bit boundary when performing 32-bit data transfers. Operation cannot be guaranteed if any other addresses are set. The value after a power-on reset and in standby mode is undefined. Rev. 5.00 Feb. 24, 2010 Page 132 of 950 REJ09B0177-0500 10. Direct Memory Access Controller (DMAC) 10.2.3 DMA Transfer Count Registers 0-3 (DMATCR0-DMATCR3) Bit: 31 30 29 28 27 26 25 24 -- -- -- -- -- -- -- -- Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 23 22 21 20 19 18 17 16 Initial value: -- -- -- -- -- -- -- -- R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 Initial value: -- -- -- -- -- -- -- -- R/W R/W R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 Initial value: -- -- -- -- -- -- -- -- R/W R/W R/W R/W R/W R/W R/W R/W R/W: R/W: R/W: DMA transfer count registers 0-3 (DMATCR0-DMATCR3) are 24-bit read/write registers that specify the transfer count for the channel (byte count, word count, or longword count) in bits 23 to 0. Specifying H'000001 gives a transfer count of 1, while H'000000 gives the maximum setting, 16,777,216 transfers. During DMAC operation, these registers indicate the remaining number of transfers. The upper 8 bits of DMATCR always read 0. The write value, also, should always be 0. The value after a power-on reset and in standby mode is undefined. Rev. 5.00 Feb. 24, 2010 Page 133 of 950 REJ09B0177-0500 10. Direct Memory Access Controller (DMAC) 10.2.4 DMA Channel Control Registers 0-3 (CHCR0-CHCR3) Bit: Initial value: 31 30 29 28 27 26 25 24 -- -- -- DI -- -- -- RO 0 0 0 0 0 0 0 0 R/W: R R R R/W* R R R R/W*2 Bit: 23 22 21 20 19 18 17 16 -- -- -- RS4 RS3 RS2 RS1 RS0 0 0 0 0 0 0 0 Initial value: 2 0 1 R/W: R R R R/W R/W R/W R/W* R/W Bit: 15 14 13 12 11 10 9 8 -- -- SM1 SM0 -- -- DM1 DM0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R/W R/W R R R/W R/W Bit: 7 6 5 4 3 2 1 0 -- -- TS1 TS0 TM IE TE DE 0 0 0 0 0 0 0 Initial value: R/W: R R R/W R/W R/W R/W R/(W)* 0 1 R/W Notes: 1. TE bit: Allows only a 0 write after reading 1. 2. The DI and RO bits may be absent, depending on the channel. DMA channel control registers 0-3 (CHCR0-CHCR3) are 32-bit readable/writable registers that designate the operation and transmission of each channel. CHCR register bits are initialized to H'00000000 by a power-on reset and in standby mode. * Bits 31-29, 27-25, 23-21, 15, 14, 11, 10, 7, 6--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 28--Direct/Indirect Select (DI): Specifies either direct address mode operation or indirect address mode operation for the channel 3 source address. This bit is valid only in CHCR3. This bit is always read as 0 in CHCR0-CHCR2, and the write value should always be 0. Bit 28: DI Description 0 Direct access mode operation for channel 3 1 Indirect access mode operation for channel 3 (Initial value) * Bit 24--Source Address Reload (RO): Selects whether to reload the source address initial value during channel 2 transfer. This bit is valid only for channel 2. This bit is always read as 0 in CHCR0, CHCR1, and CHCR3, and the write value should always be 0. Bit 24: RO Description 0 Does not reload source address 1 Reloads source address Rev. 5.00 Feb. 24, 2010 Page 134 of 950 REJ09B0177-0500 (Initial value) 10. Direct Memory Access Controller (DMAC) * Bits 20-16--Resource Select 4-0 (RS4-RS0): These bits specify the transfer request source. Bit 20: RS4 Bit 19: RS3 Bit 18: RS2 Bit 17: RS1 Bit 16: RS0 Description 0 0 0 0 0 No request*1 (Initial value) 1 SCI0 transmission 0 SCI0 reception 1 SCI1 transmission 0 SCI1 reception 1 SCI2 transmission 0 SCI2 reception 1 SCI3 transmission 0 SCI3 reception 1 SCI4 transmission 0 SCI4 reception 1 On-chip A/D0 0 On-chip A/D1 1 On-chip A/D2 0 SSU0 transmission*2 1 HCAN0 (RM0) 0 SSU0 reception*2 1 ATU-II (ICI0A) 0 ATU-II (ICI0B) 1 ATU-II (ICI0C) 0 ATU-II (ICI0D) 1 ATU-II (CMI6A) 0 ATU-II (CMI6B) 1 ATU-II (CMI6C) 0 ATU-II (CMI6D) 1 ATU-II (CMI7A) 0 ATU-II (CMI7B) 1 ATU-II (CMI7C) 0 ATU-II (CMI7D) 1 SSU1 transmission*2 0 SSU1 reception* 1 Auto-request 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 2 Notes: *1 Refer to no. 12 in section 10.5, Usage Notes. *2 SSU: Synchronous Serial Communication Unit Rev. 5.00 Feb. 24, 2010 Page 135 of 950 REJ09B0177-0500 10. Direct Memory Access Controller (DMAC) * Bits 13 and 12--Source Address Mode 1, 0 (SM1, SM0): These bits specify increment/decrement of the DMA transfer source address. Bit 13: SM1 Bit 12: SM0 Description 0 0 Source address fixed 0 1 Source address incremented (+1 during 8-bit transfer, +2 during 16-bit transfer, +4 during 32-bit transfer) 1 0 Source address decremented (-1 during 8-bit transfer, -2 during 16-bit transfer, -4 during 32-bit transfer) 1 1 Setting prohibited (Initial value) When the transfer source is specified at an indirect address, specify in source address register 3 (SAR3) the actual storage address of the data to be transferred as the data storage address (indirect address). During indirect address mode, SAR3 obeys the SM1/SM0 setting for increment/decrement. In this case, SAR3's increment/decrement is fixed at +4/-4 or 0, irrespective of the transfer data size specified by TS1 and TS0. * Bits 9 and 8--Destination Address Mode 1, 0 (DM1, DM0): These bits specify increment/decrement of the DMA transfer source address. Bit 9: DM1 Bit 8: DM0 Description 0 0 Destination address fixed 0 1 Destination address incremented (+1 during 8-bit transfer, +2 during 16-bit transfer, +4 during 32-bit transfer) 1 0 Destination address decremented (-1 during 8-bit transfer, -2 during 16-bit transfer, -4 during 32-bit transfer) 1 1 Setting prohibited (Initial value) * Bits 5 and 4--Transfer Size 1, 0 (TS1, TS0): These bits specify the size of the data for transfer. Bit 5: TS1 Bit 4: TS0 Description 0 0 Specifies byte size (8 bits) 0 1 Specifies word size (16 bits) 1 0 Specifies longword size (32 bits) 1 1 Setting prohibited (Initial value) * Bit 3--Transfer Mode (TM): Specifies the bus mode for data transfer. Bit 3: TM Description 0 Cycle-steal mode 1 Burst mode (Initial value) * Bit 2--Interrupt Enable (IE): When this bit is set to 1, interrupt requests are generated after the number of data transfers specified in DMATCR (when TE = 1). Bit 2: IE Description 0 Interrupt request not generated on completion of DMATCR-specified number of transfers (Initial value) 1 Interrupt request enabled on completion of DMATCR-specified number of transfers Rev. 5.00 Feb. 24, 2010 Page 136 of 950 REJ09B0177-0500 10. Direct Memory Access Controller (DMAC) * Bit 1--Transfer End (TE): This bit is set to 1 after the number of data transfers specified by DMATCR. At this time, if the IE bit is set to 1, an interrupt request is generated. If data transfer ends before TE is set to 1 (for example, due to an NMI or address error, or clearing of the DE bit or DME bit of DMAOR) TE is not set to 1. With this bit set to 1, data transfer is disabled even if the DE bit is set to 1. Bit 1: TE Description 0 DMATCR-specified number of transfers not completed (Initial value) [Clearing condition] 0 write after TE = 1 read, power-on reset, standby mode 1 DMATCR-specified number of transfers completed * Bit 0--DMAC Enable (DE): DE enables operation in the corresponding channel. Bit 0: DE Description 0 Operation of the corresponding channel disabled 1 Operation of the corresponding channel enabled (Initial value) Transfer is initiated if this bit is set to 1 when auto-request is specified (RS4-RS0 settings). With an on-chip module request, when a transfer request occurs after this bit is set to 1, transfer is initiated. If this bit is cleared during a data transfer, transfer is suspended. If the DE bit has been set, but TE = 1, then if the DME bit of DMAOR is 0, and the NMIF or AE bit of DMAOR is 1, the transfer enable state is not entered. 10.2.5 DMAC Operation Register (DMAOR) Bit: Note: 15 14 13 12 11 10 9 8 -- -- -- -- -- -- -- -- Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 -- -- -- -- -- AE NMIF DME Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R/(W)* R/(W)* R/W * Only a 0 write is valid after 1 is read at the AE and NMIF bits. DMAOR is a 16-bit readable/writable register that controls the overall operation of the DMAC. Register values are initialized to H'0000 by a power-on reset and in standby mode. * Bits 15-3--Reserved: These bits are always read as 0. The write value should always be 0. Rev. 5.00 Feb. 24, 2010 Page 137 of 950 REJ09B0177-0500 10. Direct Memory Access Controller (DMAC) * Bit 2--Address Error Flag (AE): Indicates that an address error has occurred during DMA transfer. If this bit is set during a data transfer, transfers on all channels are suspended. The CPU cannot write a 1 to the AE bit. Clearing is effected by a 0 write after a 1 read. Bit 2: AE Description 0 No address error, DMA transfer enabled (Initial value) [Clearing condition] Write AE = 0 after reading AE = 1 1 Address error, DMA transfer disabled [Setting condition] Address error due to DMAC * Bit 1--NMI Flag (NMIF): Indicates input of an NMI. This bit is set irrespective of whether the DMAC is operating or suspended. If this bit is set during a data transfer, transfers on all channels are suspended. The CPU is unable to write a 1 to the NMIF. Clearing is effected by a 0 write after a 1 read. Bit 1: NMIF Description 0 No NMI interrupt, DMA transfer enabled (Initial value) [Clearing condition] Write NMIF = 0 after reading NMIF = 1 1 NMI has occurred, DMC transfer disabled [Setting condition] NMI interrupt occurrence * Bit 0--DMAC Master Enable (DME): This bit enables activation of the entire DMAC. When the DME bit and DE bit of the CHCR register for the corresponding channel are set to 1, that channel is transfer-enabled. If this bit is cleared during a data transfer, transfers on all channels are suspended. Even when the DME bit is set, when the TE bit of CHCR is 1, or its DE bit is 0, transfer is disabled if the NMIF or AE bit in DMAOR is set to 1. Bit 0: DME Description 0 Operation disabled on all channels 1 Operation enabled on all channels 10.3 (Initial value) Operation When there is a DMA transfer request, the DMAC starts the transfer according to the channel priority order; when the transfer end conditions are satisfied, it ends the transfer. Transfers can be requested in two modes: auto-request and onchip peripheral module request. Transfer is performed only in dual address mode, and either direct or indirect address transfer mode can be used. The bus mode can be either burst or cycle-steal. 10.3.1 DMA Transfer Flow After the DMA source address registers (SAR), DMA destination address registers (DAR), DMA transfer count register (DMATCR), DMA channel control registers (CHCR), and DMA operation register (DMAOR) are set to the desired transfer conditions, the DMAC transfers data according to the following procedure: Rev. 5.00 Feb. 24, 2010 Page 138 of 950 REJ09B0177-0500 10. Direct Memory Access Controller (DMAC) 1. The DMAC checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0). 2. When a transfer request comes and transfer has been enabled, the DMAC transfers 1 transfer unit of data (determined by the TS0 and TS1 setting). For an auto-request, the transfer begins automatically when the DE bit and DME bit are set to 1. The DMATCR value will be decremented by 1 upon each transfer. The actual transfer flows vary by address mode and bus mode. 3. When the specified number of transfers have been completed (when DMATCR reaches 0), the transfer ends normally. If the IE bit of CHCR is set to 1 at this time, a DEI interrupt is sent to the CPU. 4. When an address error occurs in the DMAC or an NMI interrupt is generated, the transfer is aborted. Transfer is also aborted when the DE bit of CHCR or the DME bit of DMAOR is cleared to 0. Figure 10.2 is a flowchart of this procedure. Start Initial settings (SAR, DAR, DMATCR, CHCR, DMAOR) DE, DME = 1 and NMIF, AE, TE = 0? No Yes Transfer request occurs?*1 No *2 *3 Yes Bus mode Transfer (1 transfer unit); DMATCR - 1 DMATCR, SAR, and DAR updated DMATCR = 0? No Yes DEI interrupt request (when IE = 1) Does NMIF = 1, AE = 1, DE = 0, or DME = 0? Yes Transfer ends Does NMIF = 1, AE = 1, DE = 0, or DME = 0? Yes No Transfer aborted No Normal end Notes: 1. In auto-request mode, transfer begins when NMIF, AE, and TE are all 0, and the DE and DME bits are set to 1. 2. Cycle-steal mode 3. Burst mode Figure 10.2 DMAC Transfer Flowchart Rev. 5.00 Feb. 24, 2010 Page 139 of 950 REJ09B0177-0500 10. Direct Memory Access Controller (DMAC) 10.3.2 DMA Transfer Requests DMA transfer requests are generated in either the data transfer source or destination. Transfers can be requested in two modes: auto-request and on-chip peripheral module request. The request mode is selected in the RS4-RS0 bits of DMA channel control registers 0-3 (CHCR0-CHCR3). Auto-Request Mode: When there is no transfer request signal from an external source, as in a memory-to-memory transfer or a transfer between memory and an on-chip peripheral module unable to request a transfer, the auto-request mode allows the DMAC to automatically generate a transfer request signal internally. When the DE bits of CHCR0- CHCR3 and the DME bit of DMAOR are set to 1, the transfer begins (so long as the TE bits of CHCR0-CHCR3 and the NMIF and AE bits of DMAOR are all 0). On-Chip Peripheral Module Request Mode: In this mode a transfer is performed at the transfer request signal (interrupt request signal) of an on-chip peripheral module. As indicated in table 10.2, there are 30 transfer request signals: 12 from the advanced timer unit (ATU-II), which are compare match or input capture interrupts; the receive data full interrupts (RXI) and transmit data empty interrupts (TXI) of the five serial communication interfaces (SCI); the receive interrupt of HCAN0; and the A/D conversion end interrupts (ADI) of the three A/D converters; the receive data full interrupts (SSRXI), transmit data empty or transmit end interrupts (SSTSI) from two synchronous serial communication units (SSU*). When DMA transfers are enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0), a transfer is performed upon the input of a transfer request signal. When the transfer request is set to RXI (transfer request because the SCI's receive data register is full), the transfer source must be the SCI's receive data register (RDR). When the transfer request is set to TXI (transfer request because the SCI's transmit data register is empty), the transfer destination must be the SCI's transmit data register (TDR). If the transfer request is set to the A/D converter, the data transfer source must be the A/D converter register; if set to HCAN0, the transfer source must be HCAN0 message data. If the transfer request by the receive data full of the SSU* (SSRXI) is selected, the transfer destination must be the SS receive data register (SSRDR) of the SSU*. If the transmit data empty or transmit end of the SSU* (SSTSI) is selected, the transfer destination must be the SS transmit data register (SSTDR) of the SSU*. In on-chip peripheral module request mode, when the DMAC accepts the transfer request, the next request is ignored until a transfer ends in cycle steal mode or all transfers end in burst mode. Only when the address reload function is used, the next transfer request is accepted after the fourth transfer. Note: * SSU: Synchronous Serial Communication Unit Rev. 5.00 Feb. 24, 2010 Page 140 of 950 REJ09B0177-0500 10. Direct Memory Access Controller (DMAC) Table 10.2 Selecting On-Chip Peripheral Module Request Modes with the RS Bits DMAC Transfer Request Source DMAC Transfer Request Signal Transfer Source Transfer Destination Bus Mode Don't care* TDR0 Cycle-steal Don't care* Cycle-steal TDR1 Cycle-steal Don't care* Cycle-steal TDR2 Cycle-steal Don't care* Cycle-steal TDR3 Cycle-steal Don't care* Cycle-steal TDR4 Cycle-steal RXI4 (SCI4 receive-data- RDR4 full transfer request) Don't care* Cycle-steal A/D0 ADI0 (A/D0 ADDR0- conversion end interrupt) ADDR11 Don't care* Burst/cyclesteal 0 A/D1 ADI1 (A/D1 ADDR12- conversion end interrupt) ADDR23 Don't care* Burst/cyclesteal 1 A/D2 ADI2 (A/D2 ADDR24- conversion end interrupt) ADDR31 Don't care* Burst/cyclesteal 0 SSU0 transmit block SSTSI0 (transmitdata-empty or transmit-end transfer request of SSU0) Don't care* SSTDR0_0 to SSTDR3_0 Cycle-steal 1 HCAN0 MB0-MB31 Don't care* Burst/cyclesteal 0 SSU0 receive block SSRXI0 (receive-datafull transfer request of SSU0) SSRDR0_0 to SSRDR3_0 Don't care* Cycle-steal 1 ATU-II ICI0A (ICR0A input capture generation) Don't care* Don't care* Burst/cyclesteal 0 ATU-II ICI0B (ICR0B input capture generation) Don't care* Don't care* Burst/cyclesteal 1 ATU-II ICI0C (ICR0C input capture generation) Don't care* Don't care* Burst/cyclesteal 0 ATU-II ICI0D (ICR0D input capture generation) Don't care* Don't care* Burst/cyclesteal 1 ATU-II CMI6A (CYLR6A compare-match generation) Don't care* Don't care* Burst/cyclesteal RS4 RS3 RS2 RS1 RS0 0 0 0 0 1 SCI0 transmit block TXI0 (SCI0 transmitdata-empty transfer request) 1 0 SCI0 receive block 1 SCI1 transmit block TXI1 (SCI1 transmitdata-empty transfer request) 0 SCI1 receive block 1 SCI2 transmit block TXI2 (SCI2 transmitdata-empty transfer request) 0 SCI2 receive block 1 SCI3 transmit block TXI3 (SCI3 transmitdata-empty transfer request) 0 SCI3 receive block 1 SCI4 transmit block TXI4 (SCI4 transmitdata-empty transfer request) 0 SCI4 receive block 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 RXI0 (SCI0 receive-data- RDR0 full transfer request) Don't care* RXI1 (SCI1 receive-data- RDR1 full transfer request) Don't care* RXI2 (SCI2 receive-data- RDR2 full transfer request) Don't care* RXI3 (SCI3 receive-data- RDR3 full transfer request) RM0 (HCAN0 receive interrupt) Don't care* Rev. 5.00 Feb. 24, 2010 Page 141 of 950 REJ09B0177-0500 10. Direct Memory Access Controller (DMAC) Table 10.2 Selecting On-Chip Peripheral Module Request Modes with the RS Bits (cont) RS4 RS3 RS2 RS1 RS0 DMAC Transfer Request Source DMAC Transfer Request Signal Transfer Source Transfer Destination 1 0 1 1 0 ATU-II CMI6B (CYLR6B compare-match generation) Don't care* Don't care* Burst/cyclesteal 1 ATU-II CMI6C (CYLR6C compare-match generation) Don't care* Don't care* Burst/cyclesteal 0 ATU-II CMI6D (CYLR6D compare-match generation) Don't care* Don't care* Burst/cyclesteal 1 ATU-II CMI7A (CYLR7A compare-match generation) Don't care* Don't care* Burst/cyclesteal 0 ATU-II CMI7B (CYLR7B compare-match generation) Don't care* Don't care* Burst/cyclesteal 1 ATU-II CMI7C (CYLR7C compare-match generation) Don't care* Don't care* Burst/cyclesteal 0 ATU-II CMI7D (CYLR7D compare-match generation) Don't care* Don't care* Burst/cyclesteal 1 SSU1 transmit block SSTSI1 (transmitdata-empty or transmit-end transfer request of SSU1) Don't care* SSTDR0_1 to SSTDR3_1 Cycle-steal 0 SSU1 receive block SSRXI1 (receive-datafull transfer request of SSU1) SSRDR0_1 to SSRDR3_1 Don't care* Cycle-steal 1 0 0 1 1 0 1 Bus Mode Legend: SCI0, SCI1, SCI2, SCI3, SCI4: Serial communication interface channels 0-4 A/D0, A/D1, A/D2: A/D converter channels 0-2 HCAN0: Controller area network-II channel 0 ATU-II: Advanced timer unit-II SSU0, SSU1: Synchronous Serial Communication unit channels 0-1 TDR0, TDR1, TDR2, TDR3, TDR4: SCI0-SCI4 transmit data registers RDR0, RDR1, RDR2, RDR3, RDR4: SCI0-SCI4 receive data registers ADDR0-ADDR11: A/D0 data registers ADDR12-ADDR23: A/D1 data registers ADDR24-ADDR31: A/D2 data registers MB0-MB31: HCAN0 message data SSTDR0_0 to SSTDR3_0, SSTDR0_1 to SSTDR3_1: SS transmit data registers of SSU0 and SSU1 SSRDR0_0 to SSRDR3_0, SSRDR0_1 to SSRDR3_1: SS receive data registers of SSU0 and SSU1 Note: * External memory, memory-mapped external device, on-chip memory, on-chip peripheral module (excluding DMAC, BSC, and UBC) Rev. 5.00 Feb. 24, 2010 Page 142 of 950 REJ09B0177-0500 10. Direct Memory Access Controller (DMAC) 10.3.3 Channel Priority When the DMAC receives simultaneous transfer requests on two or more channels, it selects a channel according to the following priority order: * CH0 > CH1 > CH2 > CH3 10.3.4 DMA Transfer Types The DMAC supports the transfers shown in table 10.3. It operates in dual address mode, in which both the transfer source and destination addresses are output. The dual address mode consists of a direct address mode, in which the output address value is the object of a direct data transfer, and an indirect address mode, in which the output address value is not the object of the data transfer, but the value stored at the output address becomes the transfer object address. The actual transfer operation timing varies with the bus mode. The DMAC has two bus modes: cycle-steal mode and burst mode. Table 10.3 Supported DMA Transfers Transfer Destination Transfer Source External Memory Memory-Mapped External Device On-Chip Memory On-Chip Peripheral Module External memory Supported Supported Supported Supported Memory-mapped external device Supported Supported Supported Supported On-chip memory Supported Supported Supported Supported On-chip peripheral module Supported Supported Supported Supported Rev. 5.00 Feb. 24, 2010 Page 143 of 950 REJ09B0177-0500 10. Direct Memory Access Controller (DMAC) 10.3.5 Dual Address Mode Dual address mode is used for access of both the transfer source and destination by address. Transfer source and destination can be accessed either internally or externally. Dual address mode is subdivided into two other modes: direct address transfer mode and indirect address transfer mode. Direct Address Transfer Mode: Data is read from the transfer source during the data read cycle, and written to the transfer destination during the write cycle, so transfer is conducted in two bus cycles. At this time, the transfer data is temporarily stored in the DMAC. With the kind of external memory transfer shown in figure 10.3, data is read from one of the memories by the DMAC during a read cycle, then written to the other external memory during the subsequent write cycle. Figure 10.4 shows the timing for this operation. 1st bus cycle DMAC SAR Data bus Address bus DAR Memory Transfer source module Transfer destination module Data buffer The SAR value is taken as the address, and data is read from the transfer source module and stored temporarily in the DMAC. 2nd bus cycle DMAC SAR Data buffer Data bus Address bus DAR Memory Transfer source module Transfer destination module The DAR value is taken as the address, and data stored in the DMAC's data buffer is written to the transfer destination module. Figure 10.3 Direct Address Operation in Dual Address Mode Rev. 5.00 Feb. 24, 2010 Page 144 of 950 REJ09B0177-0500 10. Direct Memory Access Controller (DMAC) CK A21-A0 Transfer source address Transfer destination address CSn D15-D0 RD WRH, WRL Figure 10.4 Direct Address Transfer Timing in Dual Address Mode Indirect Address Transfer Mode: In this mode the memory address storing the data actually to be transferred is specified in the DMAC internal transfer source address register (SAR3). Therefore, in indirect address transfer mode, the DMAC internal transfer source address register value is read first. This value is first stored in the DMAC. Next, the read value is output as the address, and the value stored at that address is again stored in the DMAC. Finally, the subsequent read value is written to the address specified by the transfer destination address register, ending one cycle of DMAC transfer. In indirect address mode (figure 10.5), the transfer destination, transfer source, and indirect address storage destination are all 16-bit external memory locations, and transfer in this example is conducted in 16-bit or 8-bit units. Timing for this transfer example is shown in figure 10.6. In indirect address mode, one NOP cycle (figure 10.6) is required until the data read as the indirect address is output to the address bus. When transfer data is 32-bit, the third and fourth bus cycles each need to be doubled, giving a required total of six bus cycles and one NOP cycle for the whole operation. Rev. 5.00 Feb. 24, 2010 Page 145 of 950 REJ09B0177-0500 10. Direct Memory Access Controller (DMAC) 1st and 2nd bus cycles DMAC SAR3 Data bus Temporary buffer Address bus DAR3 Memory Transfer source module Transfer destination module Data buffer The SAR3 value is taken as the address, memory data is read, and the value is stored in the temporary buffer. Since the value read at this time is used as the address, it must be 32 bits. If data bus is 16 bits wide when accessed to an external memory space, two bus cycles are necessary. 3rd bus cycle DMAC SAR3 Data bus Temporary buffer Address bus DAR3 Memory Data buffer Transfer source module Transfer destination module The value in the temporary buffer is taken as the address, and data is read from the transfer source module to the data buffer. 4th bus cycle DMAC SAR3 Data buffer Data bus Temporary buffer Address bus DAR3 Memory Transfer source module Transfer destination module The DAR3 value is taken as the address, and the value in the data buffer is written to the transfer destination module. Note: Memory, transfer source, and transfer destination modules are shown here. In practice, any connection can be made as long as it is within the address space. Figure 10.5 Dual Address Mode and Indirect Address Operation (16-Bit-Width External Memory Space) Rev. 5.00 Feb. 24, 2010 Page 146 of 950 REJ09B0177-0500 10. Direct Memory Access Controller (DMAC) CK A21-A0 Transfer source address (H) Transfer source address (L) NOP Indirect address Transfer destination address CSn D15-D0 Indirect address (H) Internal address bus Transfer source address 1 Internal data bus Indirect address (L) Transfer data Transfer data Indirect address NOP Transfer data Indirect address Transfer data 2 DMAC indirect address buffer Indirect address DMAC data buffer Transfer data RD WRH, WRL Address read cycle (1st) (2nd) NOP cycle Data read cycle Data write cycle (3rd) (4th) Notes: 1. The internal address bus is controlled by the port and does not change. 2. The DMAC does not latch the value until 32-bit data is read from the internal data bus. Figure 10.6 Dual Address Mode and Indirect Address Transfer Timing Example 1 External Memory Space External Memory Space (External memory space has 16-bit width) Figure 10.7 shows an example of timing in indirect address mode when transfer source and indirect address storage locations are in internal memory, the transfer destination is an on-chip peripheral module with 2-cycle access space, and transfer data is 8-bit. Since the indirect address storage destination and the transfer source are in internal memory, these can be accessed in one cycle. The transfer destination is 2-cycle access space, so two data write cycles are required. One NOP cycle is required until the data read as the indirect address is output to the address bus. Rev. 5.00 Feb. 24, 2010 Page 147 of 950 REJ09B0177-0500 10. Direct Memory Access Controller (DMAC) CK Internal address bus NOP Indirect address Transfer destination address Indirect address NOP Transfer data Transfer source address Internal data bus DMAC indirect address buffer Transfer data Indirect address DMAC data buffer Transfer data Address read cycle (1st) NOP cycle (2nd) Data read cycle (3rd) Data write cycle (4th) Figure 10.7 Dual Address Mode and Indirect Address Transfer Timing Example 2 Internal Memory Space Internal Memory Space 10.3.6 Bus Modes Select the appropriate bus mode in the TM bits of CHCR0-CHCR3. There are two bus modes: cycle-steal and burst. Cycle-Steal Mode: In cycle-steal mode, the bus right is given to another bus master after each one-transfer-unit (8-bit, 16bit, or 32-bit) DMAC transfer. When the next transfer request occurs, the bus right is obtained from the other bus master and a transfer is performed for one transfer unit. When that transfer ends, the bus right is passed to the other bus master. This is repeated until the transfer end conditions are satisfied. Cycle-steal mode can be used with all categories of transfer destination, transfer source and transfer request. Figure 10.8 shows an example of DMA transfer timing in cycle-steal mode. Bus control returned to CPU Bus cycle CPU CPU CPU DMAC DMAC Read/Write CPU DMAC DMAC CPU CPU Read/Write Figure 10.8 DMA Transfer Timing Example in Cycle-Steal Mode Burst Mode: Once the bus right is obtained, transfer is performed continuously until the transfer end condition is satisfied. Rev. 5.00 Feb. 24, 2010 Page 148 of 950 REJ09B0177-0500 10. Direct Memory Access Controller (DMAC) Figure 10.9 shows an example of DMA transfer timing in burst mode. Bus cycle CPU CPU CPU DMAC DMAC DMAC DMAC DMAC DMAC Read/Write Read/Write CPU Read/Write Figure 10.9 DMA Transfer Timing Example in Burst Mode 10.3.7 Relationship between Request Modes and Bus Modes by DMA Transfer Category Table 10.4 shows the relationship between request modes and bus modes by DMA transfer category. Table 10.4 Relationship between Request Modes and Bus Modes by DMA Transfer Category Address Mode Transfer Category Request Mode Bus Mode Transfer Usable Size (Bits) Channels Dual Any*1 B/C 8/16/32 0-3 1 B/C 8/16/32 0-3 Memory-mapped external device and memory-mapped external device 1 Any* B/C 8/16/32 0-3 External memory and on-chip memory Any*1 B/C External memory and external memory External memory and memory-mapped external device Any* 2 8/16/32 3 0-3 4 External memory and on-chip peripheral module Any* B/C* 8/16/32* 0-3 Memory-mapped external device and on-chip memory Any*1 B/C 8/16/32 0-3 Memory-mapped external device and on-chip peripheral module Any*2 B/C*3 8/16/32*4 0-3 B/C 8/16/32 0-3 On-chip memory and on-chip memory On-chip memory and on-chip peripheral module On-chip peripheral module and on-chip peripheral module 1 Any* 2 Any* 2 Any* 3 B/C* B/C* 3 4 0-3 4 0-3 8/16/32* 8/16/32* Legend: B: Burst C: Cycle-steal Notes: 1. Auto-request or on-chip peripheral module request enabled. However, in the case of an on-chip peripheral 5 module request, it is not possible to specify the SCI, HCAN0, SSU* , or A/D converter for the transfer request source. 2. Auto-request or on-chip peripheral module request possible. However, if the transfer request source is also the 5 SCI, HCAN0, SSU* , or A/D converter, the transfer source or transfer destination must be same as the transfer source. 5 3. When the transfer request source is the SCI, or SSU* , only cycle-steal mode is possible. 4. Access size permitted by the on-chip peripheral module register that is the transfer source or transfer destination. 5. SSU: Synchronous Serial Communication Unit 10.3.8 Bus Mode and Channel Priorities If, for example, a transfer request is issued for channel 0 while transfer is in progress on lower-priority channel 1 in burst mode, transfer is started immediately on channel 0. In this case, if channel 0 is set to burst mode, channel 1 transfer is continued after completion of all transfers on channel 0. If channel 0 is set to cycle-steal mode, channel 1 transfer is continued only if a channel 0 transfer request has not been issued; if a transfer request is issued, channel 0 transfer is started immediately. Rev. 5.00 Feb. 24, 2010 Page 149 of 950 REJ09B0177-0500 10. Direct Memory Access Controller (DMAC) 10.3.9 Source Address Reload Function Channel 2 has a source address reload function. This returns to the first value set in the source address register (SAR2) every four transfers by setting the RO bit of CHCR2 to 1. Figure 10.10 illustrates this operation. Figure 10.11 is a timing chart for use of channel 2 only with the following transfer conditions set: burst mode, auto-request, 16-bit transfer data size, SAR2 incremented, DAR2 fixed, reload function on. DMAC DMAC control block RO bit = 1 CHCR2 Count signal Reload signal Reload control DMATCR2 Address bus Transfer request SAR2 (initial value) Reload signal SAR2 4th count Figure 10.10 Source Address Reload Function CK Internal address bus Internal data bus SAR2 DAR2 SAR2+2 SAR2 data DAR2 SAR2+4 SAR2+2 data DAR2 SAR2+6 DAR2 SAR2+4 data SAR2 SAR2+6 data DAR2 SAR2 data 1st channel 2 transfer 2nd channel 2 transfer 3rd channel 2 transfer 4th channel 2 transfer 5th channel 2 transfer SAR2 output DAR2 output SAR2+2 output DAR2 output SAR2+4 output DAR2 output SAR2+6 output DAR2 output SAR2 output DAR2 output After SAR2+6 output, SAR2 is reloaded Bus right is returned one time in four Figure 10.11 Source Address Reload Function Timing Chart The reload function can be executed whether the transfer data size is 8, 16, or 32 bits. DMATCR2, which specifies the number of transfers, is decremented by 1 at the end of every single-transfer-unit transfer, regardless of whether the reload function is on or off. Therefore, when using the reload function in the on state, a multiple of 4 must be specified in DMATCR2. Operation will not be guaranteed if any other value is set. Also, the counter which counts the occurrence of four transfers for address reloading is reset by clearing of the DME bit in DMAOR or the DE bit in CHCR2, setting of the transfer end flag (the TE bit in CHCR2), NMI input, and setting of the AE flag (address error generation in DMAC transfer), as well as by a reset and in software standby mode, but SAR2, DAR2, DMATCR2, and other registers are not reset. Consequently, when one of these sources occurs, there is a mixture of initialized counters and uninitialized registers in the DMAC, and incorrect operation may result if a restart is executed in this state. Therefore, Rev. 5.00 Feb. 24, 2010 Page 150 of 950 REJ09B0177-0500 10. Direct Memory Access Controller (DMAC) when one of the above sources, other than TE setting, occurs during use of the address reload function, SAR, DAR2, and DMATCR2 settings must be carried out before re-execution. 10.3.10 DMA Transfer Ending Conditions The DMA transfer ending conditions vary for individual channels ending and for all channels ending together. Individual Channel Ending Conditions: There are two ending conditions. A transfer ends when the value of the channel's DMA transfer count register (DMATCR) is 0, or when the DE bit of the channel's CHCR is cleared to 0. * When DMATCR is 0: When the DMATCR value becomes 0 and the corresponding channel's DMA transfer ends, the transfer end flag bit (TE) is set in CHCR. If the IE (interrupt enable) bit has been set, a DMAC interrupt (DEI) request is sent to the CPU. * When DE of CHCR is 0: Software can halt a DMA transfer by clearing the DE bit in the channel's CHCR. The TE bit is not set when this happens. Conditions for Ending on All Channels Simultaneously: Transfers on all channels end when the NMIF (NMI flag) bit or AE (address error flag) bit is set to 1 in DMAOR, or when the DME bit in DMAOR is cleared to 0. * When the NMIF or AE bit is set to 1 in DMAOR: When an NMI interrupt or DMAC address error occurs, the NMIF or AE bit is set to 1 in DMAOR and all channels stop their transfers. The DMAC obtains the bus right, and if these flags are set to 1 during execution of a transfer, DMAC halts operation when the transfer processing currently being executed ends, and transfers the bus right to the other bus master. Consequently, even if the NMIF or AE bit is set to 1 during a transfer, the DMA source address register (SAR), designation address register (DAR), and transfer count register (DMATCR) are all updated. The TE bit is not set. To resume the transfers after NMI interrupt or address error processing, the NMIF or AE flag must be cleared. To avoid restarting a transfer on a particular channel, clear its DE bit to 0 in CHCR. When the processing of a one-unit transfer is complete: In a dual address mode direct address transfer, even if an address error occurs or the NMI flag is set during read processing, the transfer will not be halted until after completion of the following write processing. In such a case, SAR, DAR, and DMATCR values are updated. In the same manner, the transfer is not halted in indirect address transfers until after the final write processing has ended. * When DME is cleared to 0 in DMAOR: Clearing the DME bit to 0 in DMAOR aborts the transfers on all channels. The TE bit is not set. 10.3.11 DMAC Access from CPU The space addressed by the DMAC is 4-cycle space. Therefore, when the CPU becomes the bus master and accesses the DMAC, a minimum of four internal clock cycles () are required for one bus cycle. Also, since the DMAC is located in word space, while a word-size access to the DMAC is completed in one bus cycle, a longword-size access is automatically divided into two word accesses, requiring two bus cycles (eight internal clock cycles). These two bus cycles are executed consecutively; a different bus cycle is never inserted between the two word accesses. This applies to both write accesses and read accesses. Rev. 5.00 Feb. 24, 2010 Page 151 of 950 REJ09B0177-0500 10. Direct Memory Access Controller (DMAC) 10.4 Examples of Use 10.4.1 Example of DMA Transfer between On-Chip SCI and External Memory In this example, on-chip serial communication interface channel 0 (SCI0) receive data is transferred to external memory using DMAC channel 0. Table 10.5 indicates the transfer conditions and the set values of each of the registers. Table 10.5 Transfer Conditions and Register Set Values for Transfer between On-chip SCI and External Memory Transfer Conditions Register Value Transfer source: RDR0 of on-chip SCI0 SAR0 H'FFFFF005 Transfer destination: external memory DAR0 H'00400000 Transfer count: 64 times DMATCR0 H'00000040 Transfer source address: fixed CHCR0 H'00020105 DMAOR H'0001 Transfer destination address: incremented Transfer request source: SCI0 (RDR0) Bus mode: cycle-steal Transfer unit: byte Interrupt request generation at end of transfer DMAC master enable on 10.4.2 Example of DMA Transfer between A/D Converter and On-Chip Memory (Address Reload On) In this example, on-chip A/D converter channel 0 is the transfer source and on-chip memory is the transfer destination, and the address reload function is on. Table 10.6 indicates the transfer conditions and the set values of each of the registers. Table 10.6 Transfer Conditions and Register Set Values for Transfer between A/D Converter and On-Chip Memory Transfer Conditions Register Value Transfer source: on-chip A/D converter ch1 (A/D1) SAR2 H'FFFFF820 Transfer destination: on-chip memory DAR2 H'FFFF6000 Transfer count: 128 times (reload count 32 times) DMATCR2 H'00000080 Transfer source address: incremented CHCR2 H'010C110D DMAOR H'0001 Transfer destination address: incremented Transfer request source: A/D converter ch1 (A/D1) Bus mode: burst Transfer unit: byte Interrupt request generation at end of transfer DMAC master enable on Rev. 5.00 Feb. 24, 2010 Page 152 of 950 REJ09B0177-0500 10. Direct Memory Access Controller (DMAC) When address reload is on, the SAR2 value returns to its initially set value every four transfers. In the above example, when a transfer request is input from the A/D1, the byte-size data is first read in from the H'FFFFF820 register of on-chip A/D1 and that data is written to internal address H'FFFF6000. Because a byte-size transfer was performed, the SAR2 and DAR2 values at this point are H'FFFFF821 and H'FFFF6001, respectively. Also, because this is a burst transfer, the bus right remains secured, so continuous data transfer is possible. When four transfers are completed, if address reload is off, execution continues with the fifth and sixth transfers and the SAR2 value continues to increment from H'FFFFF824 to H'FFFFF825 to H'FFFFF826 and so on. However, when address reload is on, DMAC transfer is halted upon completion of the fourth transfer and the bus right request signal to the CPU is cleared. At this time, the value stored in SAR2 is not H'FFFFF823 H'FFFFF824, but H'FFFFF823 H'FFFFF820, a return to the initially set address. The DAR2 value always continues to be decremented regardless of whether address reload is on or off. The DMAC internal status, due to the above operation after completion of the fourth transfer, is indicated in table 10.7 for both address reload on and off. Table 10.7 DMAC Internal Status Item Address Reload On Address Reload Off SAR2 H'FFFFF820 H'FFFFF824 DAR2 H'FFFF6004 H'FFFF6004 DMATCR2 H'0000007C H'0000007C Bus right Released Retained DMAC operation Halted Processing continues Interrupts Not issued Not issued Transfer request source flag clear Executed Not executed Notes: 1. Interrupts are executed until the DMATCR2 value becomes 0, and if the IE bit of CHCR2 is set to 1, are issued regardless of whether address reload is on or off. 2. If transfer request source flag clears are executed until the DMATCR2 value becomes 0, they are executed regardless of whether address reload is on or off. 3. Designate burst mode when using the address reload function. There are cases where abnormal operation will result if it is used in cycle-steal mode. 4. Designate a multiple of four for the DMATCR2 value when using the address reload function. There are cases where abnormal operation will result if anything else is designated. To execute transfers after the fifth transfer when address reload is on, have the transfer request source issue another transfer request signal. Rev. 5.00 Feb. 24, 2010 Page 153 of 950 REJ09B0177-0500 10. Direct Memory Access Controller (DMAC) 10.4.3 Example of DMA Transfer between External Memory and SCI1 Transmitting Side (Indirect Address on) In this example, DMAC channel 3 is used, indirect address designated external memory is the transfer source, and the SCI1 transmitting side is the transfer destination. Table 10.8 indicates the transfer conditions and the set values of each of the registers. Table 10.8 Transfer Conditions and Register Set Values for Transfer between External Memory and SCI1 Transmitting Side Transfer Conditions Register Value Transfer source: external memory SAR3 H'00400000 Value stored in address H'00400000 -- H'00450000 Value stored in address H'00450000 -- H'55 Transfer destination: on-chip SCI TDR1 DAR3 H'FFFFF00B Transfer count: 10 times DMATCR3 H'0000000A Transfer source address: incremented CHCR3 H'10031001 DMAOR H'0001 Transfer destination address: fixed Transfer request source: SCI1 (TDR1) Bus mode: cycle-steal Transfer unit: byte Interrupt request not generated at end of transfer DMAC master enable on When indirect address mode is on, the data stored in the address set in SAR is not used as the transfer source data. In the case of indirect addressing, the value stored in the SAR address is read, then that value is used as the address and the data read from that address is used as the transfer source data, then that data is stored in the address designated by DAR. In the table 10.8 example, when a transfer request from TDR1 of SCI1 is generated, a read of the address located at H'00400000, which is the value set in SAR3, is performed first. The data H'00450000 is stored at this H'00400000 address, and the DMAC first reads this H'00450000 value. It then uses this read value of H'00450000 as an address and reads the value of H'55 that is stored in the H'00450000 address. It then writes the value H'55 to address H'FFFFF00B designated by DAR3 to complete one indirect address transfer. With indirect addressing, the first executed data read from the address set in SAR3 always results in a longword size transfer regardless of the TS0 and TS1 bit designations for transfer data size. However, the transfer source address fixed and increment or decrement designations are according to the SM0 and SM1 bits. Consequently, despite the fact that the transfer data size designation is byte in this example, the SAR3 value at the end of one transfer is H'00400004. The write operation is exactly the same as an ordinary dual address transfer write operation. Rev. 5.00 Feb. 24, 2010 Page 154 of 950 REJ09B0177-0500 10. Direct Memory Access Controller (DMAC) 10.5 Usage Notes 1. Only word (16-bit) access can be used on the DMA operation register (DMAOR). All other registers can be accessed in word (16-bit) or longword (32-bit) units. 2. When rewriting the RS0-RS4 bits of CHCR0-CHCR3, first clear the DE bit to 0 (clear the DE bit to 0 before modifying CHCR). 3. When an NMI interrupt is input, the NMIF bit of DMAOR is set even when the DMAC is not operating. 4. Clear the DME bit of DMAOR to 0 and make certain that any transfer request processing accepted by the DMAC has been completed before entering standby mode. 5. Do not access the DMAC, BSC, or UBC on-chip peripheral modules from the DMAC. 6. When activating the DMAC, make the CHCR settings as the final step. Abnormal operation may result if any other registers are set last. 7. After the DMATCR count becomes 0 and the DMA transfer ends normally, always write 0 to DMATCR, even when executing the maximum number of transfers on the same channel. Abnormal operation may result if this is not done. 8. Designate burst mode as the transfer mode when using the address reload function. Abnormal operation may result in cycle-steal mode. 9. Designate a multiple of four for the DMATCR value when using the address reload function, otherwise abnormal operation may result. 10. Do not access empty DMAC register addresses. Operation cannot be guaranteed when empty addresses are accessed. 11. If DMAC transfer is aborted by NMIF or AE setting, or DME or DE clearing, during DMAC execution with address reload on, the SAR2, DAR2, and DMATCR2 settings should be made before re-executing the transfer. The DMAC may not operate correctly if this is not done. 12. Do not set the DE bit to 1 while bits RS0 to RS4 in CHCR0 to CHCR3 are still set to "no request." Rev. 5.00 Feb. 24, 2010 Page 155 of 950 REJ09B0177-0500 10. Direct Memory Access Controller (DMAC) Rev. 5.00 Feb. 24, 2010 Page 156 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) Section 11 Advanced Timer Unit-II (ATU-II) 11.1 Overview This LSI has an on-chip advanced timer unit-II (ATU-II) with one 32-bit timer channel and eleven 16-bit timer channels. 11.1.1 Features ATU-II features are summarized below. * Capability to process up to 65 pulse inputs and outputs * Prescaler Input clock to channels 0 and 10 scaled in 1 stage, input clock to channels 1 to 8 and 11 scaled in 2 stages 1/1 to 1/32 clock scaling possible in initial stage for channels 0 to 8, 10, and 11 1/1, 1/2, 1/4, 1/8, 1/16, or 1/32 scaling possible in second stage for channels 1 to 8 and 11 External clock TCLKA, TCLKB selection also possible for channels 1 to 5 and 11 TI10, TI10 multiplication (compensation) selection possible for channels 1 to 5: AGCK, AGCKM * Channel 0 has four 32-bit input capture lines, allowing the following operations: Rising-edge, falling-edge, or both-edge detection selectable DMAC can be activated at capture timing Channel 10 compare-match signal can be captured as a trigger Interval interrupt generation function generates three interval interrupts as selected. CPU interruption or A/D converter (AD0, 1, 2) activation possible Capture interrupt and counter overflow interrupt can be generated * Channel 1 has one 16-bit output compare register, eight general registers, and one dedicated input capture register. The output compare register can also be selected for one-shot pulse offset in combination with the channel 8 down-counter. General registers (GR1A-H) can be used as input capture or output compare registers Waveform output by means of compare-match: Selection of 0 output, 1 output, or toggle output Input capture function: Rising-edge, falling-edge, or both-edge detection Channel 0 input signal (TI0A) can be captured as trigger Provision for forcible cutoff of channel 8 down-counters (DCNT8A-H) Compare-match interrupts/capture interrupts and counter overflow interrupts can be generated * Channel 2 has eight 16-bit output compare registers, eight general registers, and one dedicated input capture register. The output compare registers can also be selected for one-shot pulse offset in combination with the channel 8 downcounter. General registers (GR2A-H) can be used as input capture or output compare registers Waveform output by means of compare-match: Selection of 0 output, 1 output, or toggle output Input capture function: Rising-edge, falling-edge, or both-edge detection Channel 0 input signal (TI0A) can be captured as trigger Provision for forcible cutoff of channel 8 down-counters (DCNT8I-P) Compare-match interrupts/capture interrupts and counter overflow interrupts can be generated * Channels 3 to 5 each have four general registers, allowing the following operations: Selection of input capture, output compare, PWM mode Waveform output by means of compare-match: Selection of 0 output, 1 output, or toggle output Input capture function: Rising-edge, falling-edge, or both-edge detection Rev. 5.00 Feb. 24, 2010 Page 157 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * * * * * * * Channel 9 compare-match signal can be captured as trigger (channel 3 only) Compare-match interrupts/capture interrupts can be generated Channels 6 and 7 have four 16-bit duty registers, four cycle registers, and four buffer registers, allowing the following operations: Any cycle and duty from 0 to 100% can be set Duty buffer register value transferred to duty register every cycle Interrupts can be generated every cycle Complementary PWM output can be set (channel 6 only) Channel 8 has sixteen 16-bit down-counters for one-shot pulse output, allowing the following operations: One-shot pulse generation by down-counter Down-counter can be rewritten during count Interrupt can be generated at end of down-count Offset one-shot pulse function available Can be linked to channel 1 and 2 output compare functions Reload function can be set to eight 16-bit down-counters (DCNT8I to DCNT8P) Channel 9 has six event counters and six general registers, allowing the following operations: Event counters can be cleared by compare-match Rising-edge, falling-edge, or both-edge detection available for external input Compare-match signal can be input to channel 3 Channel 10 has a 32-bit output compare and input capture register, free-running counter, 16-bit free-running counter, output compare/input capture register, reload register, 8-bit event counter, and output compare register, and 16-bit reload counter, allowing the following operations: Capture on external input pin edge input Reload count possible with 1/32, 1/64, 1/128, or 1/256 times the captured value Internal clock generated by reload counter underflow can be used as 16-bit free-running counter input Channel 1 and 2 free-running counter clearing capability Channel 11 has one 16-bit free-running counter and two 16-bit general registers, allowing the following operations: Two general registers can be used for input capture/output compare Waveform output at compare-match: Selection of 0, 1, or toggle output Input capture function: Selection of rising edge, falling edge, or both edge detection Compare-match signal can be output to APC by using a general register as an output compare register High-speed access to internal 16-bit bus High-speed access to 16-bit bus for 16-bit registers: timer counters, compare registers, and capture registers 75 interrupt sources Four input capture interrupt requests, one overflow interrupt request, and one interval interrupt request for channel 0 Sixteen dual input capture/compare-match interrupt requests and two counter overflow interrupt requests for channels 1 and 2 Twelve dual input capture/compare-match interrupt requests and three overflow interrupt requests for channels 3 to 5 Eight compare-match interrupts for channels 6 and 7 Sixteen one-shot end interrupt requests for channel 8 Six compare-match interrupts for channel 9 Two compare-match interrupts and one dual-function input capture/compare-match interrupt for channel 10 Two dual input capture/compare-match interrupt requests and one overflow interrupt request for channel 11 Rev. 5.00 Feb. 24, 2010 Page 158 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * Direct memory access controller (DMAC) activation The DMAC can be activated by a channel 0 input capture interrupt (ICI0A-D) The DMAC can be activated by a channel 6 cycle register 6 compare-match interrupt (CMI6A-D) The DMAC can be activated by a channel 7 cycle register 7 compare-match interrupt (CMI7A-D) * A/D converter activation The A/D converter can be activated by detection of 1 in bits ITVA6-13 of the channel 0 interval interrupt request registers (ITVRR1, ITVRR2A, ITVRR2B) Table 11.1 lists the functions of the ATU-II. Table 11.1 ATU-II Functions Item Counter configuration Clock sources Counters Channel 0 Channel 1 P-P/32 (P-P/32) x (1/2 ) (P-P/32) x (1/2 ) (P-P/32) x (1/2 ) (n = 0-5) (n = 0-5) (n = 0-5) TCLKA, TCLKB, AGCK, AGCKM TCLKA, TCLKB, AGCK, AGCKM TCLKA, TCLKB, AGCK, AGCKM TCNT0H, TCNT0L Channel 2 n Channels 3-5 n n TCNT1A, TCNT1B TCNT2A, TCNT2B TCNT3-5 General registers -- GR1A-H GR2A-H GR3A-D, GR4A-D, GR5A-D Dedicated input ICR0AH, ICR0AL, capture ICR0BH, ICR0BL, ICR0CH, ICR0CL, ICR0DH, ICR0DL OSBR1 OSBR2 -- Dedicated output -- compare OCR1 OCR2A-2H -- PWM output -- -- Duty: GR3A-C, GR4A-C, GR5A-C -- Cycle: GR3D, GR4D, GR5D Input pins TI0A-D -- -- -- I/O pins -- TIO1A-H TIO2A-H TIO3A-D, TIO4A-D, TIO5A-D Output pins -- -- -- -- Counter clearing function -- -- -- O Interrupt sources 6 sources 9 sources 9 sources 15 sources Dual input capture/ compare-match x 8, overflow x 1* Dual input capture/ compare-match x 12, overflow x 3 Interval x 1, Dual input capture/ input capture x 4, overflowcompare-match x 8, x1 overflow x 1 (* Same vector) Inter-channel and inter-module connection signals A/D converter activation by interval interrupt request, DMAC activation by input capture interrupt, channel 10 comparematch signal capture trigger input Channel 9 compareCompare-match signal Compare-match signal trigger output to channel 8 trigger output to channel 8 match signal input to capture trigger one-shot pulse output one-shot pulse output down-counter down-counter (Channel 3 only) Channel 10 compareChannel 10 comparematch signal counter clear match signal counter clear input input Rev. 5.00 Feb. 24, 2010 Page 159 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) Item Channels 6, 7 Counter Clock sources configuration (P-P/32) x (1/2 ) Channel 8 (P-P/32) x (1/2 ) (n = 0-5) (n = 0-5) n n Channel 9 Channel 10 Channel 11 -- (P-P/32) (P-P/32) x (1/2 ) (n = 0-5) n TCLKA, TCLKB Counters TCNT6A-D, TCNT7A-D DCNT8A-P ECNT9A-F TCNT10AH, TCNT10AL, TCNT10B-H TCNT11 General registers -- -- -- -- GR11A, GR11B Dedicated input -- capture -- -- ICR10AH, ICR10AL -- Dedicated -- output compare -- GR9A-F GR10G, OCR/0AH, -- OCR/0AL, OCR/0B, NCR10, TCCLR10 PWM output CYLR6A-D, CYLR7A-D, DTR6A-D, DTR7A-D, BFR6A-D, BFR7A-D -- -- -- -- Input pins -- -- TI9A-F TI10 -- I/O pins -- -- -- -- TIO11A, TIO11B Output pins TO6A-D, TO7A-D TO8A-P -- -- -- Counter clearing function O -- O O -- Interrupt sources 8 sources 16 sources 6 sources 3 sources 3 sources Compare-match x 8 Underflow x 16 Inter-channel and inter-module DMAC activation connection signals compare-match signal output Legend: O: Available --: Not available Rev. 5.00 Feb. 24, 2010 Page 160 of 950 REJ09B0177-0500 Compare-match x 6 Compare-match x 2, dual input capture/comparematch x 1 Dual input capture/comparematch x 2, overflow x 1 Compare-match Compare-match Compare-match Channel 1 and 2 signal output to APC signal channel 0 signal channel 3 compare-match signal trigger input to capture trigger output capture trigger output one-shot pulse Channel 1 and 2 output down-counter counter clear output 11. Advanced Timer Unit-II (ATU-II) 11.1.2 Pin Configuration Table 11.2 shows the pin configuration of the ATU-II. When these external pin functions are used, the pin function controller (PFC) should also be set in accordance with the ATU-II settings. If there are a number of pins with the same function, make settings so that only one of the pins is used. For details, see section 22, Pin Function Controller (PFC). Table 11.2 ATU-II Pins Channel Name Abbreviation I/O Function Common Clock input A TCLKA Input External clock A input pin Clock input B TCLKB Input External clock B input pin Input capture 0A TI0A Input ICR0AH, ICR0AL input capture input pin Input capture 0B TI0B Input ICR0BH, ICR0BL input capture input pin Input capture 0C TI0C Input ICR0CH, ICR0CL input capture input pin Input capture 0D TI0D Input ICR0DH, ICR0DL input capture input pin Input capture/output compare 1A TIO1A Input/output GR1A output compare output/input capture input Input capture/output compare 1B TIO1B Input/output GR1B output compare output/input capture input Input capture/output compare 1C TIO1C Input/output GR1C output compare output/input capture input Input capture/output compare 1D TIO1D Input/output GR1D output compare output/input capture input Input capture/output compare 1E TIO1E Input/output GR1E output compare output/input capture input Input capture/output compare 1F TIO1F Input/output GR1F output compare output/input capture input Input capture/output compare 1G TIO1G Input/output GR1G output compare output/input capture input Input capture/output compare 1H TIO1H Input/output GR1H output compare output/input capture input Input capture/output compare 2A TIO2A Input/output GR2A output compare output/input capture input Input capture/output compare 2B TIO2B Input/output GR2B output compare output/input capture input Input capture/output compare 2C TIO2C Input/output GR2C output compare output/input capture input Input capture/output compare 2D TIO2D Input/output GR2D output compare output/input capture input Input capture/output compare 2E TIO2E Input/output GR2E output compare output/input capture input Input capture/output compare 2F TIO2F Input/output GR2F output compare output/input capture input Input capture/output compare 2G TIO2G Input/output GR2G output compare output/input capture input Input capture/output compare 2H TIO2H Input/output GR2H output compare output/input capture input 0 1 2 Rev. 5.00 Feb. 24, 2010 Page 161 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) Channel Name Abbreviation I/O Function 3 Input capture/output compare 3A TIO3A Input/output GR3A output compare output/input capture input/PWM output pin (PWM mode) Input capture/output compare 3B TIO3B Input/output GR3B output compare output/input capture input/PWM output pin (PWM mode) Input capture/output compare 3C TIO3C Input/output GR3C output compare output/input capture input/PWM output pin (PWM mode) Input capture/output compare 3D TIO3D Input/output GR3D output compare output/input capture input Input capture/output compare 4A TIO4A Input/output GR4A output compare output/input capture input/PWM output pin (PWM mode) Input capture/output compare 4B TIO4B Input/output GR4B output compare output/input capture input/PWM output pin (PWM mode) Input capture/output compare 4C TIO4C Input/output GR4C output compare output/input capture input/PWM output pin (PWM mode) Input capture/output compare 4D TIO4D Input/output GR4D output compare output/input capture input Input capture/output compare 5A TIO5A Input/output GR5A output compare output/input capture input/PWM output pin (PWM mode) Input capture/output compare 5B TIO5B Input/output GR5B output compare output/input capture input/PWM output pin (PWM mode) Input capture/output compare 5C TIO5C Input/output GR5C output compare output/input capture input/PWM output pin (PWM mode) Input capture/output compare 5D TIO5D Input/output GR5D output compare output/input capture input Output compare 6A TO6A Output PWM output pin Output compare 6B TO6B Output PWM output pin Output compare 6C TO6C Output PWM output pin Output compare 6D TO6D Output PWM output pin Output compare 7A TO7A Output PWM output pin Output compare 7B TO7B Output PWM output pin Output compare 7C TO7C Output PWM output pin Output compare 7D TO7D Output PWM output pin 4 5 6 7 Rev. 5.00 Feb. 24, 2010 Page 162 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) Channel Name Abbreviation I/O Function 8 One-shot pulse 8A TO8A Output One-shot pulse output pin One-shot pulse 8B TO8B Output One-shot pulse output pin One-shot pulse 8C TO8C Output One-shot pulse output pin 9 One-shot pulse 8D TO8D Output One-shot pulse output pin One-shot pulse 8E TO8E Output One-shot pulse output pin One-shot pulse 8F TO8F Output One-shot pulse output pin One-shot pulse 8G TO8G Output One-shot pulse output pin One-shot pulse 8H TO8H Output One-shot pulse output pin One-shot pulse 8I TO8I Output One-shot pulse output pin One-shot pulse 8J TO8J Output One-shot pulse output pin One-shot pulse 8K TO8K Output One-shot pulse output pin One-shot pulse 8L TO8L Output One-shot pulse output pin One-shot pulse 8M TO8M Output One-shot pulse output pin One-shot pulse 8N TO8N Output One-shot pulse output pin One-shot pulse 8O TO8O Output One-shot pulse output pin One-shot pulse 8P TO8P Output One-shot pulse output pin Event input 9A TI9A Input GR9A event input Event input 9B TI9B Input GR9B event input Event input 9C TI9C Input GR9C event input Event input 9D TI9D Input GR9D event input Event input 9E TI9E Input GR9E event input Event input 9F TI9F Input GR9F event input 10 Input capture TI10 Input ICR10AH, ICR10AL input capture input 11 Input capture/output compare 11A TIO11A Input/output GR11A output compare output/input capture input Input capture/output compare 11B TIO11B Input/output GR11B output compare output/input capture input Rev. 5.00 Feb. 24, 2010 Page 163 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) 11.1.3 Register Configuration Table 11.3 summarizes the ATU-II registers. Table 11.3 ATU-II Registers Channel Name Abbrevia tion R/W Initial Value Address Access Size Section (Bits) No. Common Timer start register 1 TSTR1 R/W H'00 H'FFFFF401 8, 16, 32 11.2.1 Timer start register 2 TSTR2 R/W H'00 H'FFFFF400 Timer start register 3 TSTR3 R/W H'00 H'FFFFF402 Prescaler register 1 PSCR1 R/W H'00 H'FFFFF404 8 11.2.2 Prescaler register 2 PSCR2 R/W H'00 H'FFFFF406 Prescaler register 3 PSCR3 R/W H'00 H'FFFFF408 Prescaler register 4 PSCR4 R/W H'00 H'FFFFF40A Free-running counter 0H TCNT0H R/W H'0000 H'FFFFF430 32 11.2.15 Free-running counter 0L TCNT0L R/W H'0000 Input capture register 0AH ICR0AH R H'0000 Input capture register 0AL ICR0AL R H'0000 Input capture register 0BH ICR0BH R H'0000 Input capture register 0BL ICR0BL R H'0000 Input capture register 0CH ICR0CH R H'0000 Input capture register 0CL ICR0CL R H'0000 Input capture register 0DH ICR0DH R H'0000 Input capture register 0DL ICR0DL R H'0000 Timer interval interrupt request register 1 ITVRR1 R/W H'00 H'FFFFF424 Timer interval interrupt request register 2A ITVRR2A R/W H'00 H'FFFFF426 Timer interval interrupt request register 2B ITVRR2B R/W H'00 H'FFFFF428 Timer I/O control register TIOR0 R/W H'00 H'FFFFF42A 11.2.4 0 1 H'FFFFF434 11.2.19 H'FFFFF438 H'FFFFF43C H'FFFFF420 8 11.2.7 8 11.2.7 Timer status register 0 TSR0 R/(W)* H'0000 H'FFFFF42C 16 11.2.5 Timer interrupt enable register 0 TIER0 R/W H'0000 H'FFFFF42E 11.2.6 Free-running counter 1A TCNT1A R/W H'0000 H'FFFFF440 Free-running counter 1B TCNT1B R/W H'0000 H'FFFFF442 General register 1A GR1A R/W H'FFFF H'FFFFF444 General register 1B GR1B R/W H'FFFF H'FFFFF446 General register 1C GR1C R/W H'FFFF H'FFFFF448 General register 1D GR1D R/W H'FFFF H'FFFFF44A General register 1E GR1E R/W H'FFFF H'FFFFF44C General register 1F GR1F R/W H'FFFF H'FFFFF44E General register 1G GR1G R/W H'FFFF H'FFFFF450 General register 1H GR1H R/W H'FFFF H'FFFFF452 Rev. 5.00 Feb. 24, 2010 Page 164 of 950 REJ09B0177-0500 16 11.2.15 11.2.20 11. Advanced Timer Unit-II (ATU-II) Channel Name Abbrevia tion R/W Initial Value Address Access Size Section (Bits) No. 1 Output compare register 1 OCR1 R/W H'FFFF H'FFFFF454 16 Offset base register 1 OSBR1 R H'0000 H'FFFFF456 Timer I/O control register 1A TIOR1A R/W H'00 H'FFFFF459 Timer I/O control register 1B TIOR1B R/W H'00 H'FFFFF458 Timer I/O control register 1C TIOR1C R/W H'00 H'FFFFF45B Timer I/O control register 1D TIOR1D R/W H'00 H'FFFFF45A Timer control register 1A TCR1A R/W H'00 H'FFFFF45D Timer control register 1B TCR1B R/W H'00 H'FFFFF45C Timer status register 1A TSR1A R/(W)* H'0000 2 11.2.18 11.2.21 8, 16 11.2.4 11.2.3 H'FFFFF45E 16 11.2.5 Timer status register 1B TSR1B R/(W)* H'0000 H'FFFFF460 Timer interrupt enable register 1A TIER1A R/W H'0000 H'FFFFF462 Timer interrupt enable register 1B TIER1B R/W H'0000 H'FFFFF464 Trigger mode register TRGMDR R/W H'00 H'FFFFF466 8 11.2.8 Free-running counter 2A TCNT2A R/W H'0000 H'FFFFF600 16 11.2.15 Free-running counter 2B TCNT2B R/W H'0000 H'FFFFF602 General register 2A GR2A R/W H'FFFF H'FFFFF604 General register 2B GR2B R/W H'FFFF H'FFFFF606 General register 2C GR2C R/W H'FFFF H'FFFFF608 General register 2D GR2D R/W H'FFFF H'FFFFF60A General register 2E GR2E R/W H'FFFF H'FFFFF60C General register 2F GR2F R/W H'FFFF H'FFFFF60E General register 2G GR2G R/W H'FFFF H'FFFFF610 General register 2H GR2H R/W H'FFFF H'FFFFF612 Output compare register 2A OCR2A R/W H'FFFF H'FFFFF614 Output compare register 2B OCR2B R/W H'FFFF H'FFFFF616 Output compare register 2C OCR2C R/W H'FFFF H'FFFFF618 Output compare register 2D OCR2D R/W H'FFFF H'FFFFF61A Output compare register 2E OCR2E R/W H'FFFF H'FFFFF61C Output compare register 2F OCR2F R/W H'FFFF H'FFFFF61E Output compare register 2G OCR2G R/W H'FFFF H'FFFFF620 Output compare register 2H OCR2H R/W H'FFFF H'FFFFF622 Offset base register 2 OSBR2 R H'0000 H'FFFFF624 Timer I/O control register 2A TIOR2A R/W H'00 H'FFFFF627 Timer I/O control register 2B TIOR2B R/W H'00 H'FFFFF626 Timer I/O control register 2C TIOR2C R/W H'00 H'FFFFF629 Timer I/O control register 2D TIOR2D R/W H'00 H'FFFFF628 Timer control register 2A TCR2A R/W H'00 H'FFFFF62B Timer control register 2B TCR2B R/W H'00 H'FFFFF62A 11.2.6 11.2.20 11.2.18 11.2.21 8, 16 11.2.4 11.2.3 Rev. 5.00 Feb. 24, 2010 Page 165 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) Channel Name Abbrevia tion R/W 2 Timer status register 2A TSR2A R/(W)* H'0000 3-5 3 4 5 6 Initial Value Address Access Size Section (Bits) No. H'FFFFF62C 16 11.2.5 Timer status register 2B TSR2B R/(W)* H'0000 H'FFFFF62E Timer interrupt enable register 2A TIER2A R/W H'0000 H'FFFFF630 Timer interrupt enable register 2B TIER2B R/W H'0000 H'FFFFF632 Timer status register 3 TSR3 R/(W)* H'0000 H'FFFFF480 Timer interrupt enable register 3 TIER3 R/W H'0000 H'FFFFF482 Timer mode register TMDR R/W H'00 H'FFFFF484 Free-running counter 3 TCNT3 R/W H'0000 H'FFFFF4A0 16 11.2.15 General register 3A GR3A R/W H'FFFF H'FFFFF4A2 11.2.20 General register 3B GR3B R/W H'FFFF H'FFFFF4A4 General register 3C GR3C R/W H'FFFF H'FFFFF4A6 General register 3D GR3D R/W H'FFFF H'FFFFF4A8 Timer I/O control register 3A TIOR3A R/W H'00 H'FFFFF4AB 8, 16 Timer I/O control register 3B TIOR3B R/W H'00 H'FFFFF4AA Timer control register 3 TCR3 R/W H'00 H'FFFFF4AC 8 11.2.3 Free-running counter 4 TCNT4 R/W H'0000 H'FFFFF4C0 16 11.2.15 General register 4A GR4A R/W H'FFFF H'FFFFF4C2 11.2.20 General register 4B GR4B R/W H'FFFF H'FFFFF4C4 General register 4C GR4C R/W H'FFFF H'FFFFF4C6 General register 4D GR4D R/W H'FFFF H'FFFFF4C8 Timer I/O control register 4A TIOR4A R/W H'00 H'FFFFF4CB 8, 16 Timer I/O control register 4B TIOR4B R/W H'00 H'FFFFF4CA Timer control register 4 TCR4 R/W H'00 H'FFFFF4CC 8 11.2.3 Free-running counter 5 TCNT5 R/W H'0000 H'FFFFF4E0 16 11.2.15 General register 5A GR5A R/W H'FFFF H'FFFFF4E2 11.2.20 General register 5B GR5B R/W H'FFFF H'FFFFF4E4 General register 5C GR5C R/W H'FFFF H'FFFFF4E6 General register 5D GR5D R/W H'FFFF H'FFFFF4E8 Timer I/O control register 5A TIOR5A R/W H'00 H'FFFFF4EB 8, 16 Timer I/O control register 5B TIOR5B R/W H'00 H'FFFFF4EA Timer control register 5 TCR5 R/W H'00 H'FFFFF4EC 8 11.2.3 Free-running counter 6A TCNT6A R/W H'0001 H'FFFFF500 11.2.15 Free-running counter 6B TCNT6B R/W H'0001 H'FFFFF502 Free-running counter 6C TCNT6C R/W H'0001 H'FFFFF504 Free-running counter 6D TCNT6D R/W H'0001 H'FFFFF506 Cycle register 6A CYLR6A R/W H'FFFF H'FFFFF508 Cycle register 6B CYLR6B R/W H'FFFF H'FFFFF50A Cycle register 6C CYLR6C R/W H'FFFF H'FFFFF50C Cycle register 6D CYLR6D R/W H'FFFF H'FFFFF50E Rev. 5.00 Feb. 24, 2010 Page 166 of 950 REJ09B0177-0500 11.2.6 16 11.2.5 11.2.6 8 16 11.2.9 11.2.4 11.2.4 11.2.4 11.2.22 11. Advanced Timer Unit-II (ATU-II) Channel Name Abbrevia tion R/W Initial Value Address Access Size Section (Bits) No. 6 Buffer register 6A BFR6A R/W H'FFFF H'FFFFF510 16 7 8 Buffer register 6B BFR6B R/W H'FFFF H'FFFFF512 Buffer register 6C BFR6C R/W H'FFFF H'FFFFF514 Buffer register 6D BFR6D R/W H'FFFF H'FFFFF516 Duty register 6A DTR6A R/W H'FFFF H'FFFFF518 Duty register 6B DTR6B R/W H'FFFF H'FFFFF51A Duty register 6C DTR6C R/W H'FFFF H'FFFFF51C Duty register 6D DTR6D R/W H'FFFF H'FFFFF51E Timer control register 6A TCR6A R/W H'00 H'FFFFF521 H'00 11.2.23 11.2.24 8, 16 11.2.3 16 11.2.5 Timer control register 6B TCR6B R/W Timer status register 6 TSR6 R/(W)* H'0000 H'FFFFF522 H'FFFFF520 Timer interrupt enable register 6 TIER6 R/W H'0000 H'FFFFF524 PWM mode register PMDR R/W H'00 H'FFFFF526 8 11.2.10 Free-running counter 7A TCNT7A R/W H'0001 H'FFFFF580 16 11.2.15 Free-running counter 7B TCNT7B R/W H'0001 H'FFFFF582 Free-running counter 7C TCNT7C R/W H'0001 H'FFFFF584 Free-running counter 7D TCNT7D R/W H'0001 H'FFFFF586 Cycle register 7A CYLR7A R/W H'FFFF H'FFFFF588 Cycle register 7B CYLR7B R/W H'FFFF H'FFFFF58A Cycle register 7C CYLR7C R/W H'FFFF H'FFFFF58C Cycle register 7D CYLR7D R/W H'FFFF H'FFFFF58E Buffer register 7A BFR7A R/W H'FFFF H'FFFFF590 Buffer register 7B BFR7B R/W H'FFFF H'FFFFF592 Buffer register 7C BFR7C R/W H'FFFF H'FFFFF594 Buffer register 7D BFR7D R/W H'FFFF H'FFFFF596 Duty register 7A DTR7A R/W H'FFFF H'FFFFF598 Duty register 7B DTR7B R/W H'FFFF H'FFFFF59A Duty register 7C DTR7C R/W H'FFFF H'FFFFF59C Duty register 7D DTR7D R/W H'FFFF H'FFFFF59E Timer control register 7A TCR7A R/W H'00 H'FFFFF5A1 8, 16 Timer control register 7B TCR7B R/W H'00 H'FFFFF5A0 Timer status register 7 TSR7 R/(W)* H'0000 H'FFFFF5A2 16 11.2.5 Timer interrupt enable register 7 TIER7 R/W H'0000 H'FFFFF5A4 11.2.6 Down-counter 8A DCNT8A R/W H'0000 H'FFFFF640 Down-counter 8B DCNT8B R/W H'0000 H'FFFFF642 Down-counter 8C DCNT8C R/W H'0000 H'FFFFF644 Down-counter 8D DCNT8D R/W H'0000 H'FFFFF646 Down-counter 8E DCNT8E R/W H'0000 H'FFFFF648 Down-counter 8F DCNT8F R/W H'0000 H'FFFFF64A 11.2.6 11.2.22 11.2.23 11.2.24 16 11.2.3 11.2.16 Rev. 5.00 Feb. 24, 2010 Page 167 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) Channel Name Abbrevia tion R/W Initial Value Address 8 Down-counter 8G DCNT8G R/W H'0000 H'FFFFF64C 16 Down-counter 8H DCNT8H R/W H'0000 H'FFFFF64E Down-counter 8I DCNT8I R/W H'0000 H'FFFFF650 Down-counter 8J DCNT8J R/W H'0000 H'FFFFF652 Down-counter 8K DCNT8K R/W H'0000 H'FFFFF654 Down-counter 8L DCNT8L R/W H'0000 H'FFFFF656 Down-counter 8M DCNT8M R/W H'0000 H'FFFFF658 Down-counter 8N DCNT8N R/W H'0000 H'FFFFF65A Down-counter 8O DCNT8O R/W H'0000 H'FFFFF65C Down-counter 8P DCNT8P R/W H'0000 H'FFFFF65E Reload register 8 RLDR8 R/W H'0000 H'FFFFF660 11.2.25 Timer connection register TCNR R/W H'0000 H'FFFFF662 11.2.12 One-shot pulse terminate register OTR R/W H'0000 H'FFFFF664 11.2.13 Down-count start register DSTR R/W H'0000 H'FFFFF666 11.2.11 Timer control register 8 TCR8 R/W H'00 H'FFFFF668 Timer status register 8 TSR8 R/(W)* H'0000 H'FFFFF66A 16 11.2.5 Timer interrupt enable register 8 TIER8 R/W H'FFFFF66C 11.2.6 Reload enable register RLDENR R/W H'00 H'FFFFF66E 8 11.2.14 Event counter 9A ECNT9A R/W H'00 H'FFFFF680 11.2.17 Event counter 9B ECNT9B R/W H'00 H'FFFFF682 Event counter 9C ECNT9C R/W H'00 H'FFFFF684 Event counter 9D ECNT9D R/W H'00 H'FFFFF686 Event counter 9E ECNT9E R/W H'00 H'FFFFF688 Event counter 9F ECNT9F R/W H'00 H'FFFFF68A General register 9A GR9A R/W H'FF H'FFFFF68C 9 10 H'0000 General register 9B GR9B R/W H'FF H'FFFFF68E General register 9C GR9C R/W H'FF H'FFFFF690 General register 9D GR9D R/W H'FF H'FFFFF692 General register 9E GR9E R/W H'FF H'FFFFF694 General register 9F GR9F R/W H'FF H'FFFFF696 Timer control register 9A TCR9A R/W H'00 H'FFFFF698 Timer control register 9B TCR9B R/W H'00 H'FFFFF69A Timer control register 9C TCR9C R/W H'00 H'FFFFF69C Access Size Section (Bits) No. 8 8 11.2.16 11.2.3 11.2.20 11.2.3 Timer status register 9 TSR9 R/(W)* H'0000 H'FFFFF69E 16 11.2.5 Timer interrupt enable register 9 TIER9 R/W H'0000 H'FFFFF6A0 11.2.6 Free-running counter 10AH TCNT10AH R/W H'0000 H'FFFFF6C0 32 11.2.26 Free-running counter 10AL TCNT10AL R/W H'0001 Event counter 10B TCNT10B R/W H'00 H'FFFFF6C4 8 Reload counter 10C TCNT10C R/W H'0001 H'FFFFF6C6 16 Rev. 5.00 Feb. 24, 2010 Page 168 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) Channel Name Abbrevia tion R/W Initial Value Address 10 Correction counter 10D TCNT10D R/W H'00 H'FFFFF6C8 8 11 Note: * Access Size Section (Bits) No. Correction angle counter 10E TCNT10E R/W H'0000 H'FFFFF6CA 16 Correction angle counter 10F TCNT10F R/W H'0001 H'FFFFF6CC Free-running counter 10G TCNT10G R/W H'0000 H'FFFFF6CE Input capture register 10AH ICR10AH R H'0000 H'FFFFF6D0 32 Input capture register 10AL ICR10AL R H'0000 Output compare register 10AH OCR10AH R/W H'FFFF Output compare register 10AL OCR10AL R/W H'FFFF Output compare register 10B OCR10B R/W H'FF Reload register 10C RLD10C R/W H'0000 H'FFFFF6DA 16 General register 10G GR10G R/W H'FFFF H'FFFFF6DC Noise canceler counter 10H TCNT10H R/W H'00 H'FFFFF6DE 8 Noise canceler register 10 NCR10 R/W H'FF H'FFFFF6E0 Timer I/O control register 10 TIOR10 R/W H'00 H'FFFFF6E2 Timer control register 10 TCR10 R/W H'00 H'FFFFF6E4 Correction counter clear register 10 TCCLR10 R/W H'0000 H'FFFFF6E6 16 Timer status register 10 R/(W)* H'0000 TSR10 11.2.26 H'FFFFF6D4 H'FFFFF6D8 8 11.2.26 H'FFFFF6E8 Timer interrupt enable register 10 TIER10 R/W H'0000 H'FFFFF6EA Free-running counter 11 TCNT11 R/W H'0000 H'FFFFF5C0 16 11.2.15 General register 11A GR11A R/W H'FFFF H'FFFFF5C2 11.2.20 General register 11B GR11B R/W H'FFFF H'FFFFF5C4 Timer I/O control register 11 TIOR11 R/W H'00 H'FFFFF5C6 8 11.2.4 Timer control register 11 TCR11 R/W H'00 H'FFFFF5C8 11.2.3 Timer status register 11 TSR11 R/(W)* H'0000 H'FFFFF5CA 16 11.2.5 Timer interrupt enable register 11 TIER11 R/W H'FFFFF5CC 11.2.6 H'0000 Only a 0 write after a read is enabled. Rev. 5.00 Feb. 24, 2010 Page 169 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) 11.1.4 Block Diagrams Overall Block Diagram of ATU-II: Figure 11.1 shows an overall block diagram of the ATU-II. Clock selection Interrupts Inter-module connection signals External pins Bus interface Inter-module address bus TSTR3 TSTR2 TSTR1 16-bit timer channel 11 ........ Channel 10 Counter and register control, and comparator 16-bit timer channel 1 P I/O interrupt control IC/OC control 32-bit timer channel 0 Prescaler TCLKA TCLKB Module data bus Inter-module data bus Legend: TSTR1, 2, 3: Timer start registers (8 bits) Interrupts: ITV0-ITV2, OVI0, OVI1A, OVI1B, OVI2A, OVI2B, OVI3-OVI5, OVI11, ICI0A-ICI0D, IMI1A-IMI1H, CMI1, IMI2A-IMI2H, CMI2A-CMI2H, IMI3A-IMI3D, IMI4A-IMI4D, IMI5A-IMI5D, CMI6A-CMI6D, CMI7A-CMI7D, OSI8A-OSI8P, CMI9A-CMI9F, CMI10A, CMI10B, ICI10A, CMI10G, IMI11A, IMI11B External pins: TI0A-TI0D, TIO1A-TIO1H, TIO2A-TIO2H, TIO3A-TIO3D, TIO4A-TIO4D, TIO5A-TIO5D, TO6A-TO6D, TO7A-TO7D, TO8A-TO8P, TI9A-TI9F, TI10, TIO11A-TIO11B Inter-module connection signals: Signals to A/D converter, signals to direct memory access controller (DMAC), signals to advanced pulse controller (APC) Figure 11.1 Overall Block Diagram of ATU-II Rev. 5.00 Feb. 24, 2010 Page 170 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) Block Diagram of Channel 0: Figure 11.2 shows a block diagram of ATU-II channel 0. STR0 Prescaler 1 ICR0AH ICR0BH ICR0CH ICR0DH TCNT0H ICR0AL ICR0BL ICR0CL ICR0DL TCNT0L TIOR0 TIER0 ITVRR1 ITVRR2A ITVRR2B TSR0 TI0A TI0B TI0C TI0D TRGOD (OCR10B compare-match signal) Control logic A/D converter trigger Overflow interrupt signal Interval interrupt I/O control OSBR (ch1, ch2) Internal data bus and address bus Figure 11.2 Block Diagram of Channel 0 Rev. 5.00 Feb. 24, 2010 Page 171 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) Block Diagram of Channel 1: Figure 11.3 shows a block diagram of ATU-II channel 1. STR1A/1B, 2B Prescaler 1 TCLKA TCLKB TI10 (AGCK) TI10 multiplication (AGCKM) Comparator Clock selection logic (2 systems: A, B) TI0A(capture signal from CH0) GR1A GR1B GR1C GR1D GR1E GR1F GR1G GR1H OSBR1 TCNT1A TRG1A (counter clear trigger from CH10) TRG1B (counter clear trigger from CH10) Control logic OCR1 TCNT1B TIOR1A TIOR1B TIOR1C TIOR1D TCR1A TCR1B TSR1A TSR1B TIER1A TIER1B TRGMDR One-shot start trigger (CH8) TIO1A TIO1B TIO1C TIO1D TIO1E TIO1F TIO1G TIO1H One-shot terminate trigger (CH8) I/O control Overflow interrupt x 1 Input capture/output compare interrupts x 8 Internal data bus and address bus Figure 11.3 Block Diagram of Channel 1 Rev. 5.00 Feb. 24, 2010 Page 172 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) Block Diagram of Channel 2: Figure 11.4 shows a block diagram of ATU-II channel 2. STR2A/1B, 2B Prescaler 1 TCLKA TCLKB TI10 (AGCKM) TI10 multiplication (AGCK) Comparator Clock selection logic TI0A (couter clear trigger from CH0) GR2A GR2B GR2C GR2D GR2E GR2F GR2G GR2H OSBR2 TCNT2A TRG2A (counter clear trigger from CH10) TRG2B (counter clear trigger from CH10) Control logic OCR2A OCR2B OCR2C OCR2D OCR2E OCR2F OCR2G OCR2H TCNT2B TIOR2A TIOR2B TIOR2C TIOR2D TCR2A TCR2B TSR2A TSR2B TIER2A TIER2B TIO2A TIO2B TIO2C TIO2D TIO2E TIO2F TIO2G TIO2H One-shot start trigger (CH8) One-shot terminate trigger (CH8) I/O control Overflow interrupt x 1 Input capture/output compare interrupts x 8 Internal data bus and address bus Figure 11.4 Block Diagram of Channel 2 Rev. 5.00 Feb. 24, 2010 Page 173 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) Block Diagram of Channels 3 to 5: Figure 11.5 shows a block diagram of ATU-II channels 3, 4, and 5. STR3 to 5 Prescaler 1 Clock selection logic (3 systems: CH3, 4, 5) TCLKA TCLKB TI10 (AGCK) Comparator TI10 multiplication (AGCKM) Channel 9 comparematch trigger GR3A ** * GR3D TCNT3 TIOR3A TIOR3B TCR3 GR4A ** * GR4D TCNT4 Control logic TIOR4A TIOR4B TCR4 GR5A ** * GR5D TCNT5 TIOR5A TIOR5B TCR5 TMDR TIER3 TSR3 TIO3A TIO3B TIO3C TIO3D TIO4A TIO4B TIO4C TIO4D TIO5A TIO5B TIO5C TIO5D I/O control Overflow interrupts x 3 Input capture/output compare interrupts x 12 Internal data bus and address bus Figure 11.5 Block Diagram of Channels 3 to 5 Rev. 5.00 Feb. 24, 2010 Page 174 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) Block Diagram of Channels 6 and 7: Figure 11.6 shows a block diagram of ATU-II channels 6 and 7. STR6x, 7x Prescaler 2 Comparator Clock selection logic (A-D independent) BFR6A CYLR6A DTR6A TCNT6A BFR6B CYLR6B DTR6B TCNT6B BFR6C CYLR6C DTR6C TCNT6C Control logic BFR6D CYLR6D DTR6D TCNT6D TCR6A TCR6B TSR6 TIER6 PMDR TO6A TO6B TO6C TO6D I/O control Compare-match interrupts x 4 Internal data bus and address bus Note: Channel 7 has no PMDR7. Figure 11.6 Block Diagram of Channel 6 (Same Configuration for Channel 7) Rev. 5.00 Feb. 24, 2010 Page 175 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) Block Diagram of Channel 8: Figure 11.7 shows a block diagram of ATU-II channel 8. Prescaler 1 Clock selection (2 systems: A-H, I-P) Comparator DCNT8A DCNT8B DCNT8C DCNT8D One-shot start trigger (CH1, 2) One-shot terminate trigger (CH1, 2) * * * * DCNT8M DCNT8N DCNT8O DCNT8P Control logic RLDR8 TCNR OTR DSTR TCR8 TSR8 TIER8 RLDENR TO8A TO8B * * * * I/O control TO8O TO8P Down-count end interrupts x 16 (OSI) Internal data bus and address bus Figure 11.7 Block Diagram of Channel 8 Rev. 5.00 Feb. 24, 2010 Page 176 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) Block Diagram of Channel 9: Figure 11.8 shows a block diagram of ATU-II channel 9. GR9A ECNT9A Comparator GR9B ECNT9B GR9C ECNT9C GR9D ECNT9D GR9E ECNT9E Control logic GR9F ECNT9F TCR9A TCR9B TCR9C TSR9 TIER9 TI9A TI9B TI9C TI9D TI9E TI9F Channel 3 capture trigger x 4 I/O control Compare-match interrupts x 6 Internal data bus and address bus Figure 11.8 Block Diagram of Channel 9 Rev. 5.00 Feb. 24, 2010 Page 177 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) Block Diagram of Channel 10: Figure 11.9 shows a block diagram of ATU-II channel 10. STR10 Prescaler 4 ICR10AH OCR10AH TCNT10AH ICR10AL OCR10AL TCNT10AL OCR10B TCNT10B RLD10C TCNT10C TCNT10D TCNT10E TCNT10F Control logic GR10G TCNT10G NCR10 TCNT10H TCCLR10 TIOR10 TCR10 TIER10 TSR10 TI10 I/O control Internal data bus and address bus Figure 11.9 Block Diagram of Channel 10 Rev. 5.00 Feb. 24, 2010 Page 178 of 950 REJ09B0177-0500 TRG1A, 1B, 2A, 2B (Counter clear trigger) TRG0D (OCR10B comparematch signal) Frequency multiplication clock Frequency multiplication correction clock Output compare interrupts x 2 Input capture / output compare interrupt x 1 11. Advanced Timer Unit-II (ATU-II) Block Diagram of Channel 11: Figure 11.10 shows a block diagram of ATU-II channel 11. STR11 Prescaler 4 TCLKA TCLKB Comparator Clock selection logic GR11A GR11B TCNT11 TIOR11 TCR11 TSR11 TIER11 TIO11A TIO11B Control logic APC output compare-match timing signals x 2 I/O control Overflow interrupt x 1 Input capture/output compare interrupts x 2 Internal data bus and address bus Figure 11.10 Block Diagram of Channel 11 Rev. 5.00 Feb. 24, 2010 Page 179 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) 11.1.5 Inter-Channel and Inter-Module Signal Communication Diagram Figure 11.11 shows the connections between channels and between modules in the ATU-II. Channel 0 TI0A ICR0A ICR0B ICR0C ICR0D ITVRR1 ITVRR2A ITVRR2B A/D converter activation DMAC activation Channel 10 Capture trigger OCR10B Channel 1 TCNT1A TCNT1B Capture trigger OSBR1 GR1A GR1B OCR1 GR1H OSBR2 TCNT2A TCNT2B OCR2A OCR2B GR2A GR2B TCNT10F ** * Channel 2 ** * ** * OCR2H GR2H TI10(AGCK) TI10 multiplication (AGCKM) Counter clear trigger TI10(AGCK) TI10 multiplication (AGCKM) Channel 8 One-shot start One-shot terminate DCNT8A DCNT8B DCNT8C DCNT8D DCNT8E DCNT8F DCNT8G DCNT8H DCNT8I DCNT8J DCNT8K DCNT8L DCNT8M DCNT8N DCNT8O DCNT8P TI10(AGCK) TI10 multiplication (AGCKM) Channel 3 GR3A GR3B GR3C GR3D Channel 4 TI10(AGCK) TI10 multiplication (AGCKM) Channel 5 TI10(AKCK) TI10 multiplication (AGCKM) Capture trigger Channel 9 Channel 6, 7 GR9A GR9B GR9C GR9D GR9E GR9F TCNT6, 7x CYLR6, 7x DTR6, 7x BFR6, 7x X: A, B, C, D Channel 11 TCNT11 GR11A GR11B Compare-match signal transmission to advanced pulse controller (APC) Figure 11.11 Inter-Module Communication Signals Rev. 5.00 Feb. 24, 2010 Page 180 of 950 REJ09B0177-0500 DMAC activation (compare-match) 11. Advanced Timer Unit-II (ATU-II) 11.1.6 Prescaler Diagram Figure 11.12 shows a diagram of the ATU-II prescalers. Input clock P Channel 0 Prescaler 1 Channel 1 Channel 2 TCLKA TCLKB Channel 3 Edge detection Channel 4 Channel 5 Channel 8 Channel 10 TI10 TI9A TI9B TI9C TI9D TI9E TI9F Prescaler 2 Channel 6 Prescaler 3 Channel 7 Prescaler 4 Channel 11 Channel 9 Timer control register Figure 11.12 Prescaler Diagram Rev. 5.00 Feb. 24, 2010 Page 181 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) 11.2 Register Descriptions 11.2.1 Timer Start Registers (TSTR) The timer start registers (TSTR) are 8-bit registers. The ATU-II has three TSTR registers. Channel Abbreviation Function 0, 1, 2, 3, 4, 5, 10 TSTR1 Free-running counter operation/stop setting 6, 7 TSTR2 11 TSTR3 Timer Start Register 1 (TSTR1) Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 STR10 STR5 STR4 STR3 STR1B, 2B STR2A STR1A STR0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W TSTR1 is an 8-bit readable/writable register that starts and stops the free-running counter (TCNT) in channels 0 to 5 and 10. TSTR1 is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. * Bit 7--Counter Start 10 (STR10): Starts and stops channel 10 counters (TCNT10A, 10C, 10D, 10E, 10F, and 10G). TCNT10B and 10H are not stopped. Bit 7: STR10 Description 0 TCNT10 is halted 1 TCNT10 counts (Initial value) * Bit 6--Counter Start 5 (STR5): Starts and stops free-running counter 5 (TCNT5). Bit 6: STR5 Description 0 TCNT5 is halted 1 TCNT5 counts (Initial value) * Bit 5--Counter Start 4 (STR4): Starts and stops free-running counter 4 (TCNT4). Bit 5: STR4 Description 0 TCNT4 is halted 1 TCNT4 counts (Initial value) * Bit 4--Counter Start 3 (STR3): Starts and stops free-running counter 3 (TCNT3). Bit 4: STR3 Description 0 TCNT3 is halted 1 TCNT3 counts Rev. 5.00 Feb. 24, 2010 Page 182 of 950 REJ09B0177-0500 (Initial value) 11. Advanced Timer Unit-II (ATU-II) * Bit 3--Counter Start 1B, 2B (STR1B, STR2B): Starts and stops free-running counters 1B and 2B (TCNT1B, TCNT2B). Bit 3:STR1B, STR2B Description 0 TCNT1B and TCNT2B are halted 1 TCNT1B and TCNT2B count (Initial value) * Bit 2--Counter Start 2A (STR2A): Starts and stops free-running counter 2A (TCNT2A). Bit 2: STR2A Description 0 TCNT2A is halted 1 TCNT2A counts (Initial value) * Bit 1--Counter Start 1A (STR1A): Starts and stops free-running counter 1A (TCNT1A). Bit 1: STR1A Description 0 TCNT1A is halted 1 TCNT1A counts (Initial value) * Bit 0--Counter Start 0 (STR0): Starts and stops free-running counter 0 (TCNT0). Bit 0: STR0 Description 0 TCNT0 is halted 1 TCNT0 counts (Initial value) Timer Start Register 2 (TSTR2) Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 STR7D STR7C STR7B STR7A STR6D STR6C STR6B STR6A 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W TSTR2 is an 8-bit readable/writable register that starts and stops the free-running counter (TCNT) in channels 6 and 7. TSTR2 is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. * Bit 7--Counter Start 7D (STR7D): Starts and stops free-running counter 7D (TCNT7D). Bit 7: STR7D Description 0 TCNT7D is halted 1 TCNT7D counts (Initial value) * Bit 6--Counter Start 7C (STR7C): Starts and stops free-running counter 7C (TCNT7C). Bit 6: STR7C Description 0 TCNT7C is halted 1 TCNT7C counts (Initial value) Rev. 5.00 Feb. 24, 2010 Page 183 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * Bit 5--Counter Start 7B (STR7B): Starts and stops free-running counter 7B (TCNT7B). Bit 5: STR7B Description 0 TCNT7B is halted 1 TCNT7B counts (Initial value) * Bit 4--Counter Start 7A (STR7A): Starts and stops free-running counter 7A (TCNT7A). Bit 4: STR7A Description 0 TCNT7A is halted 1 TCNT7A counts (Initial value) * Bit 3--Counter Start 6D (STR6D): Starts and stops free-running counter 6D (TCNT6D). Bit 3: STR6D Description 0 TCNT6D is halted 1 TCNT6D counts (Initial value) * Bit 2--Counter Start 6C (STR6C): Starts and stops free-running counter 6C (TCNT6C). Bit 2: STR6C Description 0 TCNT6C is halted 1 TCNT6C counts (Initial value) * Bit 1--Counter Start 6B (STR6B): Starts and stops free-running counter 6B (TCNT6B). Bit 1: STR6B Description 0 TCNT6B is halted 1 TCNT6B counts (Initial value) * Bit 0--Counter Start 6A (STR6A): Starts and stops free-running counter 6A (TCNT6A). Bit 0: STR6A Description 0 TCNT6A is halted 1 TCNT6A counts (Initial value) Timer Start Register 3 (TSTR3) Bit: 7 6 5 4 3 2 1 0 -- -- -- -- -- -- -- STR11 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/W TSTR3 is an 8-bit readable/writable register that starts and stops the free-running counter (TCNT11) in channel 11. TSTR3 is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. Rev. 5.00 Feb. 24, 2010 Page 184 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * Bits 7 to 1--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 0--Counter Start 11 (STR11): Starts and stops free-running counter 11 (TCNT11). Bit 0: STR11 Description 0 TCNT11 is halted 1 TCNT11 counts 11.2.2 (Initial value) Prescaler Registers (PSCR) The prescaler registers (PSCR) are 8-bit registers. The ATU-II has four PSCR registers. Channel Abbreviation Function 0, 1, 2, 3, 4, 5, 8, 11 PSCR1 Prescaler setting for respective channels 6 PSCR2 7 PSCR3 10 PSCR4 PSCRx is an 8-bit writable register that enables the first-stage counter clock ' input to each channel to be set to any value from P/1 to P/32. Bit: 7 6 5 4 3 2 1 0 -- -- -- PSCxE PSCxD PSCxC PSCxB PSCxA Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R/W R/W R/W R/W R/W Note: x = 1 to 4 Input counter clock ' is determined by setting PSCxA to PSCxE: ' is P/1 when the set value is H'00, and P/32 when H'1F. PSCRx is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. The internal clock ' set with this register can undergo further second-stage scaling to create clock " for channels 1 to 8 and 11, the setting being made in the timer control register (TCR). * Bits 7 to 5--Reserved: These bits cannot be modified. * Bits 4 to 0--Prescaler (PSCxE, PSCxD, PSCxC, PSCxB, PSCxA): These bits specify frequency division of first-stage counter clock ' input to the corresponding channel. Rev. 5.00 Feb. 24, 2010 Page 185 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) 11.2.3 Timer Control Registers (TCR) The timer control registers (TCR) are 8-bit registers. The ATU-II has 16 TCR registers: two each for channels 1 and 2, one each for channels 3, 4, 5, 8, and 11, two each for channels 6 and 7, and three for channel 9. For details of channel 10, see section 11.2.26, Channel 10 Registers. Channel Abbreviation Function 1 TCR1A, TCR1B Internal clock/external clock/TI10 input clock selection 2 TCR2A, TCR2B 3 TCR3 4 TCR4 5 TCR5 6 TCR6A, TCR6B 7 TCR7A, TCR7B 8 TCR8 9 TCR9A, TCR9B, TCR9C External clock selection/setting of channel 3 trigger in event of compare-match 11 TCR11 Internal clock/external clock selection Internal clock selection Each TCR is an 8-bit readable/writable register that selects whether an internal clock or external clock is used for channels 1 to 5 and 11. For channels 6 to 8, TCR selects an internal clock, and for channel 9, an external clock. When an internal clock is selected, TCR selects the value of " further scaled from clock ' scaled with prescaler register (PSCR). Scaled clock " can be selected, for channels 1 to 8 and 11 only, from ', '/2, '/4, '/8, '/16, and '/32 (only ' is available for channel 0). Edge detection is performed on the rising edge. When an external clock is selected, TCR selects whether TCLKA, TCLKB (channels 1 to 5 and 11 only), TI10 pin input (channels 1 to 5 only), or a TI10 pin input multiplied clock (channels 1 to 5 only) is used, and also performs edge selection. Each TCR is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. Timer Control Registers 1A, 1B, 2A, 2B (TCR1A, TCR1B, TCR2A, TCR2B) TCR1A, TCR2A Bit: 7 6 5 4 3 2 1 0 -- -- CKEGA1 CKEGA0 CKSELA3 CKSELA2 CKSELA1 CKSELA0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R/W R/W R/W R/W R/W R/W TCR1B, TCR2B Bit: 7 6 5 4 3 2 1 0 -- -- CKEGB1 CKEGB0 CKSELB3 CKSELB2 CKSELB1 CKSELB0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R/W R/W R/W R/W R/W R/W * Bits 7 and 6--Reserved: These bits are always read as 0. The write value should always be 0. Rev. 5.00 Feb. 24, 2010 Page 186 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * Bits 5 and 4--Clock Edge 1 and 0 (CKEGx1, CKEGx0): These bits select the count edge(s) for external clock TCLKA and TCLKB input. Bit 5: CKEGx1 Bit 4: CKEGx0 Description 0 0 Rising edges counted 1 Falling edges counted 0 Both rising and falling edges counted 1 Count disabled 1 (Initial value) Note: x = A or B * Bits 3 to 0--Clock Select A3 to A0, B3 to B0 (CKSELA3 to CKSELA0, CKSELB3 to CKSELB0): These bits select whether an internal clock or external clock is used. When an internal clock is selected, scaled clock " is selected from ', '/2, '/4, '/8, '/16, and '/32. When an external clock is selected, TCLKA, TCLKB, TI10 pin input, or a TI10 pin input multiplied clock is selected. When TI10 pin input and TI10 pin input clock multiplication are selected, set CKEG1 and CKEG0 in TCR10 so that TI10 input is possible. Bit 3: CKSELx3 Bit 2: CKSELx2 Bit 1: CKSELx1 Bit 0: CKSELx0 Description 0 0 0 0 Internal clock ": counting on ' 1 Internal clock ": counting on '/2 0 Internal clock ": counting on '/4 1 Internal clock ": counting on '/8 0 Internal clock ": counting on '/16 1 Internal clock ": counting on '/32 0 External clock: counting on TCLKA pin input 1 External clock: counting on TCLKB pin input 1 1 0 1 1 0 0 1 (Initial value) 0 Counting on TI10 pin input (AGCK) 1 Counting on multiplied (corrected)(AGCKM) TI10 pin input clock 1 * Setting prohibited * * Setting prohibited Legend: *: Don't care Note: x = A or B Timer Control Registers 3 to 5 (TCR3, TCR4, TCR5) Bit: 7 6 5 4 3 2 1 0 -- -- CKEG1 CKEG0 CKSEL3 CKSEL2 CKSEL1 CKSEL0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R/W R/W R/W R/W R/W R/W * Bits 7 and 6--Reserved: These bits are always read as 0. The write value should always be 0. Rev. 5.00 Feb. 24, 2010 Page 187 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * Bits 5 and 4--Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the count edge(s) for external clock TCLKA and TCLKB input. Bit 5: CKEG1 Bit 4: CKEG0 Description 0 0 Rising edges counted 1 Falling edges counted 0 Both rising and falling edges counted 1 Count disabled 1 (Initial value) * Bits 3 to 0--Clock Select 3 to 0 (CKSEL3 to CKSEL0): These bits select whether an internal clock or external clock is used. When an internal clock is selected, scaled clock " is selected from ', '/2, '/4, '/8, '/16, and '/32. When an external clock is selected, TCLKA, TCLKB, TI10 pin input, or a TI10 pin input multiplied clock is selected. When TI10 pin input and TI10 pin input clock multiplication are selected, set CKEG1 and CKEG0 in TCR10 so that TI10 input is possible. Bit 3: CKSEL3 Bit 2: CKSEL2 Bit 1: CKSEL1 Bit 0: CKSEL0 Description 0 0 0 0 Internal clock ": counting on ' 1 Internal clock ": counting on '/2 0 Internal clock ": counting on '/4 1 Internal clock ": counting on '/8 0 Internal clock ": counting on '/16 1 Internal clock ": counting on '/32 0 External clock: counting on TCLKA pin input 1 External clock: counting on TCLKB pin input 0 Counting on TI10 pin input (AGCK) 1 Counting on multiplied (corrected)(AGCKM) TI10 pin input clock 1 * Setting prohibited * * Setting prohibited 1 1 0 1 1 0 1 0 Legend: *: Don't care Rev. 5.00 Feb. 24, 2010 Page 188 of 950 REJ09B0177-0500 (Initial value) 11. Advanced Timer Unit-II (ATU-II) Timer Control Registers 6A, 6B, 7A, 7B (TCR6A, TCR6B, TCR7A, TCR7B) TCR6A, TCR7A Bit: 7 6 5 4 3 2 1 0 -- CKSELB2 CKSELB1 CKSELB0 -- CKSELA2 CKSELA1 CKSELA0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R R/W R/W R/W 7 6 5 4 3 2 1 0 -- CKSELD2 CKSELD1 CKSELD0 -- CKSELC2 CKSELC1 CKSELC0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R R/W R/W R/W TCR6B, TCR7B Bit: * Bit 7--Reserved: This bit is always read as 0. The write value should always be 0. * Bits 6 to 4--Clock Select B2 to B0, D2 to D0 (CKSELB2 to CKSELB0, CKSELD2 to CKSELD0): These bits select clock ", scaled from the internal clock source, from ', '/2, '/4, '/8, '/16, and '/32. Bit 6: CKSELx2 Bit 5: CKSELx1 Bit 4: CKSELx0 Description 0 0 0 Internal clock ": counting on ' 1 Internal clock ": counting on '/2 1 0 Internal clock ": counting on '/4 1 Internal clock ": counting on '/8 0 Internal clock ": counting on '/16 1 Internal clock ": counting on '/32 0 Setting prohibited 1 Setting prohibited 1 0 1 (Initial value) Note: x = B or D * Bit 3--Reserved: This bit is always read as 0. The write value should always be 0. Rev. 5.00 Feb. 24, 2010 Page 189 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * Bits 2 to 0--Clock Select A2 to A0, C2 to C0 (CKSELA2 to CKSELA0, CKSELC2 to CKSELC0): These bits select clock ", scaled from the internal clock source, from ', '/2, '/4, '/8, '/16, and '/32. Bit 2: CKSELx2 Bit 1 CKSELx1 Bit 0 CKSELx0 Description 0 0 0 Internal clock ": counting on ' 1 Internal clock ": counting on '/2 0 Internal clock ": counting on '/4 1 Internal clock ": counting on '/8 0 Internal clock ": counting on '/16 1 Internal clock ": counting on '/32 0 Setting prohibited 1 Setting prohibited 1 1 0 1 (Initial value) Note: x = A or C Timer Control Register 8 (TCR8) Bit: 7 6 5 4 3 2 1 0 -- CKSELB2 CKSELB1 CKSELB0 -- CKSELA2 CKSELA1 CKSELA0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R R/W R/W R/W The CKSELAx bits relate to DCNT8A to DCNT8H, and the CKSELBx bits relate to DCNT8I to DCNT8P. * Bit 7--Reserved: This bit is always read as 0. The write value should always be 0. * Bits 6 to 4--Clock Select B2 to B0 (CKSELB2 to CKSELB0): These bits, relating to counters DCNT8I to DCNT8P, select clock ", scaled from the internal clock source, from ', '/2, '/4, '/8, '/16, and '/32. Bit 6: CKSELB2 Bit 5: CKSELB1 Bit 4: CKSELB0 Description 0 0 0 Internal clock ": counting on ' 1 Internal clock ": counting on '/2 0 Internal clock ": counting on '/4 1 Internal clock ": counting on '/8 0 Internal clock ": counting on '/16 1 Internal clock ": counting on '/32 0 Setting prohibited 1 Setting prohibited 1 1 0 1 * Bit 3--Reserved: This bit is always read as 0. The write value should always be 0. Rev. 5.00 Feb. 24, 2010 Page 190 of 950 REJ09B0177-0500 (Initial value) 11. Advanced Timer Unit-II (ATU-II) * Bits 2 to 0--Clock Select A2 to A0 (CKSELA2 to CKSELA0): These bits, relating to counters DCNT8A to DCNT8H, select clock ", scaled from the internal clock source, from ', '/2, '/4, '/8, '/16, and '/32. Bit 2: CKSELA2 Bit 1: CKSELA1 Bit 0: CKSELA0 Description 0 0 0 Internal clock ": counting on ' 1 Internal clock ": counting on '/2 1 0 Internal clock ": counting on '/4 1 Internal clock ": counting on '/8 0 Internal clock ": counting on '/16 1 Internal clock ": counting on '/32 0 Setting prohibited 1 Setting prohibited 1 0 1 (Initial value) Timer Control Registers 9A, 9B, 9C (TCR9A, TCR9B, TCR9C) TCR9A Bit: 7 6 5 4 3 2 1 0 -- TRG3BEN EGSELB1 EGSELB0 -- TRG3AEN EGSELA1 EGSELA0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 -- TRG3DEN EGSELD1 EGSELD0 -- TRG3CEN EGSELC1 EGSELC0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 -- -- EGSELF1 EGSELF0 -- -- EGSELE1 EGSELE0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R/W R/W R R R/W R/W TCR9B TCR9C * Bit 7--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 6--Trigger Channel 3BEN, 3DEN (TRG3BEN, TRG3DEN): These bits select the channel 9 event counter compare-match signal channel 3 input capture trigger. Bit 6: TRG3xEN Description 0 Channel 3 input capture trigger in event of channel 9 compare-match (ECNT9x = GR9x) is disabled (Initial value) 1 Channel 3 input capture trigger in event of channel 9 compare-match (ECNT9x = GR9x) is enabled Note: x = B or D Rev. 5.00 Feb. 24, 2010 Page 191 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * Bits 5 and 4--Edge Select B1, B0, D1, D0, F1, F0 (EGSELB1, EGSELB0, EGSELD1, EGSELD0, EGSELF1, EGSELF0): These bits select the event counter counted edge(s). Bit 5: EGSELx1 Bit 4: EGSELx0 Description 0 0 Count disabled 1 Rising edges counted 0 Falling edges counted 1 Both rising and falling edges counted 1 (Initial value) Note: x = B, D, or F * Bit 3--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 2--Trigger Channel 3AEN, 3CEN (TRG3AEN, TRG3CEN): These bits select the channel 9 event counter compare-match signal channel 3 input capture trigger. Bit 2: TRG3xEN Description 0 Channel 3 input capture trigger in event of channel 9 compare-match (ECNT9x = GR9x) is disabled (Initial value) 1 Channel 3 input capture trigger in event of channel 9 compare-match (ECNT9x = GR9x) is enabled Note: x = A or C * Bits 1 and 0--Edge Select A1, A0, C1, C0, E1, E0 (EGSELA1, EGSELA0, EGSELC1, EGSELC0, EGSELE1, EGSELE0): These bits select the event counter counted edge(s). Bit 1: EGSELx1 Bit 0: EGSELx0 Description 0 0 Count disabled 1 Rising edges counted 0 Falling edges counted 1 Both rising and falling edges counted 1 (Initial value) Note: x = A, C, or E Timer Control Register 11 (TCR11) Bit: 7 6 5 4 3 2 1 0 -- -- CKEG1 CKEG0 -- CKSELA2 CKSELA1 CKSELA0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R/W R/W R R/W R/W R/W * Bits 7, 6, and 3--Reserved: These bits are always read as 0. The write value should always be 0. * Bits 5 and 4--Edge Select: These bits select the event counter counted edge(s). Bit 5: CKEG1 Bit 4: CKEG0 Description 0 0 Rising edges counted 1 Falling edges counted 1 0 Both rising and falling edges counted 1 Count disabled Rev. 5.00 Feb. 24, 2010 Page 192 of 950 REJ09B0177-0500 (Initial value) 11. Advanced Timer Unit-II (ATU-II) * Bits 2 to 0--Clock Select A2 to A0 (CKSELA2 to CKSELA0): These bits select clock ", scaled from the internal clock source, from ', '/2, '/4, '/8, '/16, and '/32. Bit 2: CKSELA2 Bit 1: CKSELA1 Bit 0: CKSELA0 Description 0 0 0 Internal clock ": counting on ' 1 Internal clock ": counting on '/2 1 0 Internal clock ": counting on '/4 1 Internal clock ": counting on '/8 0 Internal clock ": counting on '/16 1 Internal clock ": counting on '/32 0 External clock: counting on TCLKA pin input 1 External clock: counting on TCLKB pin input 1 0 1 11.2.4 (Initial value) Timer I/O Control Registers (TIOR) The timer I/O control registers (TIOR) are 8-bit registers. The ATU-II has 16 TIOR registers: one for channel 0, four each for channels 1 and 2, two each for channels 3 to 5, and one for channel 11. For details of channel 10, see section 11.2.26, Channel 10 Registers. Channel Abbreviation Function 0 TIOR0 ICR0 edge detection setting 1 TIOR1A-1D GR input capture/compare-match switching, edge detection/output value setting 2 TIOR2A-2D 3 TIOR3A, TIOR3B 4 TIOR4A, TIOR4B 5 TIOR5A, TIOR5B 11 TIOR11 GR input capture/compare-match switching, edge detection/output value setting, TCNT3 to TCNT5 clear enable/disable setting GR input capture/compare-match switching, edge detection/output value setting Each TIOR is an 8-bit readable/writable register used to select the functions of dedicated input capture registers and general registers. For dedicated input capture registers (ICR), TIOR performs edge detection setting. For general registers (GR), TIOR selects use as an input capture register or output compare register, and performs edge detection setting. For channels 3 to 5, TIOR also selects enabling or disabling of free-running counter (TCNT) clearing in the event of a compare-match. Timer I/O Control Register 0 (TIOR0) Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 IO0D1 IO0D0 IO0C1 IO0C0 IO0B1 IO0B0 IO0A1 IO0A0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W TIOR0 specifies edge detection for input capture registers ICR0A to ICR0D. TIOR0 is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. Rev. 5.00 Feb. 24, 2010 Page 193 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * Bits 7 and 6--I/O Control 0D1 and 0D0 (IO0D1, IO0D0): These bits select TI0D pin input capture signal edge detection. Bit 7: IO0D1 Bit 6: IO0D0 Description 0 0 Input capture disabled (input capture possible in TCNT10B compare-match) (Initial value) 1 Input capture in ICR0D on rising edge 1 0 Input capture in ICR0D on falling edge 1 Input capture in ICR0D on both rising and falling edges * Bits 5 and 4--I/O Control 0C1 and 0C0 (IO0C1, IO0C0): These bits select TI0C pin input capture signal edge detection. Bit 5: IO0C1 Bit 4: IO0C0 Description 0 0 Input capture disabled 1 Input capture in ICR0C on rising edge 0 Input capture in ICR0C on falling edge 1 Input capture in ICR0C on both rising and falling edges 1 (Initial value) * Bits 3 and 2--I/O Control 0B1 and 0B0 (IO0B1, IO0B0): These bits select TI0B pin input capture signal edge detection. Bit 3: IO0B1 Bit 2: IO0B0 Description 0 0 Input capture disabled 1 Input capture in ICR0B on rising edge 0 Input capture in ICR0B on falling edge 1 Input capture in ICR0B on both rising and falling edges 1 (Initial value) * Bits 1 and 0--I/O Control 0A1 and 0A0 (IO0A1, IO0A0): These bits select TI0A pin input capture signal edge detection. Bit 1: IO0A1 Bit 0: IO0A0 Description 0 0 Input capture disabled 1 Input capture in ICR0A on rising edge 1 0 Input capture in ICR0A on falling edge 1 Input capture in ICR0A on both rising and falling edges Rev. 5.00 Feb. 24, 2010 Page 194 of 950 REJ09B0177-0500 (Initial value) 11. Advanced Timer Unit-II (ATU-II) Timer I/O Control Registers 1A to 1D (TIOR1A to TIOR1D) TIOR1A Bit: 7 6 5 4 3 2 1 0 -- IO1B2 IO1B1 IO1B0 -- IO1A2 IO1A1 IO1A0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 -- IO1D2 IO1D1 IO1D0 -- IO1C2 IO1C1 IO1C0 TIOR1B Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 TIOR1C -- IO1F2 IO1F1 IO1F0 -- IO1E2 IO1E1 IO1E0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 -- IO1H2 IO1H1 IO1H0 -- IO1G2 IO1G1 IO1G0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R R/W R/W R/W TIOR1D Registers TIOR1A to TIOR1D specify whether general registers GR1A to GR1H are used as input capture or comparematch registers, and also perform edge detection and output value setting. Each TIOR is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. * Bit 7--Reserved: This bit is always read as 0. The write value should always be 0. Rev. 5.00 Feb. 24, 2010 Page 195 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * Bits 6 to 4--I/O Control 1B2 to 1B0, 1D2 to 1D0, 1F2 to 1F0, 1H2 to 1H0 (IO1B2 to IO1B0, IO1D2 to IO1D0, IOF12 to IO1F0, IO1H2 to IO1H0): These bits select the general register (GR) function. Bit 6:IO1x2 Bit 5:IO1x1 Bit 4:IO1x0 Description 0 0 0 GR is an output compare register 1 1 0 1 Note: Compare-match disabled; pin output undefined (Initial value) 1 0 output on GR compare-match 0 1 output on GR compare-match 1 Toggle output on GR compare-match 0 GR is an input capture register Input capture disabled (GR cannot be written to) 1 Input capture in GR on rising edge at TIO1x pin (GR cannot be written to) 0 Input capture in GR on falling edge at TIO1x pin (GR cannot be written to) 1 Input capture in GR on both rising and falling edges at TIO1x pin (GR cannot be written to) x = B, D, F, or H * Bit 3--Reserved: This bit is always read as 0. The write value should always be 0. * Bits 2 to 0--I/O Control 1A2 to 1A0, 1C2 to 1C0, 1E2 to 1E0, 1G2 to 1G0 (IO1A2 to IO1A0, IO1C2 to IO1C0, IO1E2 to IO1E0, IO1G2 to IO1G0): These bits select the general register (GR) function. Bit 2:IO1x2 Bit 1:IO1x1 Bit 0:IO1x0 Description 0 0 0 GR is an output compare register 1 1 0 1 0 output on GR compare-match 0 1 output on GR compare-match 1 Toggle output on GR compare-match 0 1 1 Compare-match disabled; pin output undefined (Initial value) GR is an input capture register Input capture disabled Input capture in GR on rising edge at TIO1x pin (GR cannot be written to) 0 Input capture in GR on falling edge at TIO1x pin (GR cannot be written to) 1 Input capture in GR on both rising and falling edges at TIO1x pin (GR cannot be written to) Note: x = A, C, E, or G Rev. 5.00 Feb. 24, 2010 Page 196 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) Timer I/O Control Registers 2A to 2D (TIOR2A to TIOR2D) TIOR2A Bit: 7 6 5 4 3 2 1 0 -- IO2B2 IO2B1 IO2B0 -- IO2A2 IO2A1 IO2A0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 -- IO2D2 IO2D1 IO2D0 -- IO2C2 IO2C1 IO2C0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 -- IO2F2 IO2F1 IO2F0 -- IO2E2 IO2E1 IO2E0 TIOR2B TIOR2C Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 TIOR2D -- IO2H2 IO2H1 IO2H0 -- IO2G2 IO2G1 IO2G0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R R/W R/W R/W Registers TIOR2A to TIOR2D specify whether general registers GR2A to GR2H are used as input capture or comparematch registers, and also perform edge detection and output value setting. Each TIOR is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. * Bit 7--Reserved: This bit is always read as 0. The write value should always be 0. Rev. 5.00 Feb. 24, 2010 Page 197 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * Bits 6 to 4--I/O Control 2B2 to 2B0, 2D2 to 2D0, 2F2 to 2F0, 2H2 to 2H0 (IO2B2 to IO2B0, IO2D2 to IO2D0, IO2F2 to IO2F0, IO2H2 to IO2H0): These bits select the general register (GR) function. Bit 6:IO2x2 Bit 5:IO2x1 Bit 4:IO2x0 Description 0 0 0 GR is an output compare register 1 1 0 1 0 output on GR compare-match 0 1 output on GR compare-match 1 Toggle output on GR compare-match 0 GR is an input capture register 1 1 Compare-match disabled; pin output undefined (Initial value) Input capture disabled Input capture in GR on rising edge at TIO2x pin (GR cannot be written to) 0 Input capture in GR on falling edge at TIO2x pin (GR cannot be written to) 1 Input capture in GR on both rising and falling edges at TIO2x pin (GR cannot be written to) Note: x = B, D, F, or H * Bit 3--Reserved: This bit is always read as 0. The write value should always be 0. * Bits 2 to 0--I/O Control 2A2 to 2A0, 2C2 to 2C0, 2E2 to 2E0, 2G2 to 2G0 (IO2A2 to IO2A0, IO2C2 to IO2C0, IO2E2 to IO2E0, IO2G2 to IO2G0): These bits select the general register (GR) function. Bit 2:IO2x2 Bit 1:IO2x1 Bit 0:IO2x0 Description 0 0 0 GR is an output compare register 1 1 0 1 0 output on GR compare-match 0 1 output on GR compare-match 1 Toggle output on GR compare-match 0 GR is an input capture register 1 1 Compare-match disabled; pin output undefined (Initial value) Input capture disabled Input capture in GR on rising edge at TIO2x pin (GR cannot be written to) 0 Input capture in GR on falling edge at TIO2x pin (GR cannot be written to) 1 Input capture in GR on both rising and falling edges at TIO2x pin (GR cannot be written to) Note: x = A, C, E, or G Timer I/O Control Registers 3A, 3B, 4A, 4B, 5A, 5B (TIOR3A, TIOR3B, TIOR4A, TIOR4B, TIOR5A, TIOR5B) TIOR3A, TIOR4A, TIOR5A Bit: Initial value: R/W: Note: 7 6 5 4 3 2 1 0 CCIxB IOxB2 IOxB1 IOxB0 CCIxA IOxA2 IOxA1 IOxA0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W x = 3 to 5 Rev. 5.00 Feb. 24, 2010 Page 198 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) TIOR3B, TIOR4B, TIOR5B Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 CCIxD IOxD2 IOxD1 IOxD0 CCIxC IOxC2 IOxC1 IOxC0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Note: x = 3 to 5 TIOR3A, TIOR3B, TIOR4A, TIOR4B, TIOR5A, and TIOR5B specify whether general registers GR3A to GR3D, GR4A to GR4D, and GR5A to GR5D are used as input capture or compare-match registers, and also perform edge detection and output value setting. They also select enabling or disabling of free-running counter (TCNT3 to TCNT5) clearing on compare-match. Each TIOR is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. * Bit 7--Clear Counter Enable Flag 3B, 4B, 5B, 3D, 4D, 5D (CCI3B, CCI4B, CCI5B, CCI3D, CCI4D, CCI5D): These bits select enabling or disabling of free-running counter (TCNT) clearing. Bit 7: CCIxx Description 0 TCNT clearing disabled 1 TCNT cleared on GR compare-match (Initial value) Note: xx = 3B, 4B, 5B, 3D, 4D, or 5D TCNT is cleared on compare-match only when GR is functioning as an output compare register. * Bits 6 to 4--I/O Control 3B2 to 3B0, 4B2 to 4B0, 5B2 to 5B0, 3D2 to 3D0, 4D2 to 4D0, 5D2 to 5D0 (IO3B2 to IO3B0, IO4B2 to IO4B0, IO5B2 to IO5B0, IO3D2 to IO3D0, IO4D2 to IO4D0, IO5D2 to IO5D0): These bits select the general register (GR) function. Bit 6:IOxx2 Bit 5:IOxx1 Bit 4:IOxx0 Description 0 0 0 GR is an output compare register 1 1 0 1 Compare-match disabled; pin output undefined (Initial value) 1 0 output on GR compare-match 0 1 output on GR compare-match 1 Toggle output on GR compare-match 0 GR is an input capture register Input capture disabled (In channel 3 only, GR cannot be written to) 1 (input capture by channel 3 and 9 compare-match enabled) Input capture in GR on rising edge at TIOxx pin (GR cannot be written to) 0 1 Input capture in GR on falling edge at TIOxx pin (GR cannot be written to) Input capture in GR on both rising and falling edges at TIOxx pin (GR cannot be written to) Note: xx = 3B, 4B, 5B, 3D, 4D, or 5D Rev. 5.00 Feb. 24, 2010 Page 199 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * Bit 3--Clear Counter Enable Flag 3A, 4A, 5A, 3C, 4C, 5C (CCI3A, CCI4A, CCI5A, CCI3C, CCI4C, CCI5C): These bits select enabling or disabling of free-running counter (TCNT) clearing. Bit 3: CCIxx Description 0 TCNT clearing disabled 1 TCNT cleared on GR compare-match (Initial value) Note: xx = 3A, 4A, 5A, 3C, 4C, or 5C TCNT is cleared on compare-match only when GR is functioning as an output compare register. * Bits 2 to 0--I/O Control 3A2 to 3A0, 4A2 to 4A0, 5A2 to 5A0, 3C2 to 3C0, 4C2 to 4C0, 5C2 to 5C0 (IO3A2 to IO3A0, IO4A2 to IO4A0, IO5A2 to IO5A0, IO3C2 to IO3C0, IO4C2 to IO4C0, IO5C2 to IO5C0): These bits select the general register (GR) function. Bit 2:IOxx2 Bit 1:IOxx1 Bit 0:IOxx0 Description 0 0 0 GR is an output compare register 1 1 0 1 Compare-match disabled; pin output undefined (Initial value) 1 0 output on GR compare-match 0 1 output on GR compare-match 1 Toggle output on GR compare-match 0 GR is an input capture register Input capture disabled (In channel 3 only, GR cannot be written to) 1 (input capture by channel 3 and 9 compare-match enabled) Input capture in GR on rising edge at TIOxx pin (GR connot be written to) 0 1 Input capture in GR on falling edge at TIOxx pin (GR connot be written to) Input capture in GR on both rising and falling edges at TIOxx pin (GR connot be written to) Note: xx = 3A, 4A, 5A, 3C, 4C, or 5C Timer I/O Control Register 11 (TIOR11) TIOR11 Bit: 7 6 5 4 3 2 1 0 -- IO11B2 IO11B1 IO11B0 -- IO11A2 IO11A1 IO11A0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R R/W R/W R/W TIOR11 specifies whether general registers GR11A and GR11B are used as input capture or compare-match registers, and also performs edge detection and output value setting. TIOR11 is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. * Bit 7--Reserved: This bit is always read as 0. The write value should always be 0. Rev. 5.00 Feb. 24, 2010 Page 200 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * Bits 6 to 4--I/O Control 11B2 to 11B0 (IO11B2 to IO11B0): These bits select the general register (GR) function. Bit 6:IO11B2 Bit 5:IO11B1 Bit 4:IO11B0 Description 0 0 0 GR is an output compare register 1 1 0 1 0 output on GR compare-match 0 1 output on GR compare-match 1 Toggle output on GR compare-match 0 1 1 Compare-match disabled; pin output undefined (Initial value) GR is an input capture register Input capture disabled Input capture in GR on rising edge at TIO11B pin (GR cannot be written to) 0 Input capture in GR on falling edge at TIO11B pin (GR cannot be written to) 1 Input capture in GR on both rising and falling edges at TIO11B pin (GR cannot be written to) * Bit 3--Reserved: This bit is always read as 0. The write value should always be 0. * Bits 2 to 0--I/O Control 11A2 to 11A0 (IO11A2 to IO11A0): These bits select the general register (GR) function. Bit 2:IO11A2 Bit 1:IO11A1 Bit 0:IO11A0 Description 0 0 0 GR is an output compare register 1 1 0 1 0 output on GR compare-match 0 1 output on GR compare-match 1 Toggle output on GR compare-match 0 1 1 Compare-match disabled; pin output undefined (Initial value) GR is an input capture register Input capture disabled Input capture in GR on rising edge at TIO11A pin (GR cannot be written to) 0 Input capture in GR on falling edge at TIO11A pin (GR cannot be written to) 1 Input capture in GR on both rising and falling edges at TIO11A pin (GR cannot be written to) Rev. 5.00 Feb. 24, 2010 Page 201 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) 11.2.5 Timer Status Registers (TSR) The timer status registers (TSR) are 16-bit registers. The ATU-II has 11 TSR registers: one each for channels 0, 6 to 9, and 11, two each for channels 1 and 2, and one for channels 3 to 5. For details of channel 10, see section 11.2.26, Channel 10 Registers. Channel Abbreviation Function 0 TSR0 Indicates input capture, interval interrupt, and overflow status 1 TSR1A, TSR1B Indicate input capture, compare-match, and overflow status 2 TSR2A, TSR2B 3 TSR3 Indicates input capture, compare-match, and overflow status 6 TSR6 Indicate cycle register compare-match status 7 TSR7 8 TSR8 Indicates down-counter output end (low) status 9 TSR9 Indicates event counter compare-match status 11 TSR11 Indicates input capture, compare-match, and overflow status 4 5 The TSR registers are 16-bit readable/writable registers containing flags that indicate free-running counter (TCNT) overflow, channel 0 input capture or interval interrupt generation, channel 3, 4, 5, and 11 general register input capture or compare-match, channel 6 and 7 compare-matches, channel 8 down-counter output end, and channel 9 event counter compare-matches. Each flag is an interrupt source, and issues an interrupt request to the CPU if the interrupt is enabled by the corresponding bit in the timer interrupt enable register (TIER). Each TSR is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. Timer Status Register 0 (TSR0) TSR0 indicates the status of channel 0 interval interrupts, input capture, and overflow. Bit: 15 14 13 12 11 10 9 8 -- -- -- -- -- -- -- -- Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 IIF2B IIF2A IIF1 OVF0 ICF0D ICF0C ICF0B ICF0A 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Initial value: R/W: Note: * Only 0 can be written to clear the flag. * Bits 15 to 8--Reserved: These bits are always read as 0. The write value should always be 0. Rev. 5.00 Feb. 24, 2010 Page 202 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * Bit 7--Interval Interrupt Flag 2B (IIF2B): Status flag that indicates the generation of an interval interrupt. Bit 7: IIF2B Description 0 [Clearing condition] When IIF2B is read while set to 1, then 0 is written to IIF2B 1 [Setting condition] When interval interrupt selected by ITVRR2B is generated (Initial value) * Bit 6--Interval Interrupt Flag 2A (IIF2A): Status flag that indicates the generation of an interval interrupt. Bit 6: IIF2A Description 0 [Clearing condition] When IIF2A is read while set to 1, then 0 is written to IIF2A 1 [Setting condition] When interval interrupt selected by ITVRR2A is generated (Initial value) * Bit 5--Interval Interrupt Flag 1 (IIF1): Status flag that indicates the generation of an interval interrupt. Bit 5: IIF1 Description 0 [Clearing condition] When IIF1 is read while set to 1, then 0 is written to IIF1 1 [Setting condition] When interval interrupt selected by ITVRR1 is generated (Initial value) * Bit 4--Overflow Flag 0 (OVF0): Status flag that indicates TCNT0 overflow. Bit 4: OVF0 Description 0 [Clearing condition] When OVF0 is read while set to 1, then 0 is written to OVF0 1 [Setting condition] When the TCNT0 value overflows (from H'FFFFFFFF to H'00000000) (Initial value) * Bit 3--Input Capture Flag 0D (ICF0D): Status flag that indicates ICR0D input capture. Bit 3: ICF0D Description 0 [Clearing condition] When ICF0D is read while set to 1, then 0 is written to ICF0D 1 [Setting condition] When the TCNT0 value is transferred to the input capture register by an input capture signal. Also set by input capture with a channel 10 compare match as the trigger (Initial value) * Bit 2--Input Capture Flag 0C (ICF0C): Status flag that indicates ICR0C input capture. Bit 2: ICF0C Description 0 [Clearing condition] When ICF0C is read while set to 1, then 0 is written to ICF0C 1 [Setting condition] When the TCNT0 value is transferred to the input capture register by an input capture signal (Initial value) Rev. 5.00 Feb. 24, 2010 Page 203 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * Bit 1--Input Capture Flag 0B (ICF0B): Status flag that indicates ICR0B input capture. Bit 1: ICF0B Description 0 [Clearing condition] When ICF0B is read while set to 1, then 0 is written to ICF0B 1 [Setting condition] When the TCNT0 value is transferred to the input capture register by an input capture signal (Initial value) * Bit 0--Input Capture Flag 0A (ICF0A): Status flag that indicates ICR0A input capture. Bit 0: ICF0A Description 0 [Clearing condition] When ICF0A is read while set to 1, then 0 is written to ICF0A 1 [Setting condition] When the TCNT0 value is transferred to the input capture register by an input capture signal (Initial value) Timer Status Registers 1A and 1B (TSR1A, TSR1B) TSR1A: TSR1A indicates the status of channel 1 input capture, compare-match, and overflow. Bit: 15 14 13 12 11 10 9 8 -- -- -- -- -- -- -- OVF1A Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/(W)* Bit: 7 6 5 4 3 2 1 0 IMF1H IMF1G IMF1F IMF1E IMF1D IMF1C IMF1B IMF1A 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Initial value: R/W: Note: * Only 0 can be written, to clear the flag. * Bits 15 to 9--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 8--Overflow Flag 1A (OVF1A): Status flag that indicates TCNT1A overflow. Bit 8: OVF1A Description 0 [Clearing condition] When OVF1A is read while set to 1, then 0 is written to OVF1A 1 [Setting condition] When the TCNT1A value overflows (from H'FFFF to H'0000) Rev. 5.00 Feb. 24, 2010 Page 204 of 950 REJ09B0177-0500 (Initial value) 11. Advanced Timer Unit-II (ATU-II) * Bit 7--Input Capture/Compare-Match Flag 1H (IMF1H): Status flag that indicates GR1H input capture or comparematch. Bit 7: IMF1H Description 0 [Clearing condition] When IMF1H is read while set to 1, then 0 is written to IMF1H 1 [Setting conditions] * When the TCNT1A value is transferred to GR1H by an input capture signal while GR1H is functioning as an input capture register * (Initial value) When TCNT1A = GR1H while GR1H is functioning as an output compare register * Bit 6--Input Capture/Compare-Match Flag 1G (IMF1G): Status flag that indicates GR1G input capture or comparematch. Bit 6: IMF1G Description 0 [Clearing condition] When IMF1G is read while set to 1, then 0 is written to IMF1G 1 [Setting conditions] * When the TCNT1A value is transferred to GR1G by an input capture signal while GR1G is functioning as an input capture register * (Initial value) When TCNT1A = GR1G while GR1G is functioning as an output compare register * Bit 5--Input Capture/Compare-Match Flag 1F (IMF1F): Status flag that indicates GR1F input capture or comparematch. Bit 5: IMF1F Description 0 [Clearing condition] When IMF1F is read while set to 1, then 0 is written to IMF1F 1 [Setting conditions] * When the TCNT1A value is transferred to GR1F by an input capture signal while GR1F is functioning as an input capture register * (Initial value) When TCNT1A = GR1F while GR1F is functioning as an output compare register * Bit 4--Input Capture/Compare-Match Flag 1E (IMF1E): Status flag that indicates GR1E input capture or comparematch. Bit 4: IMF1E Description 0 [Clearing condition] When IMF1E is read while set to 1, then 0 is written to IMF1E 1 [Setting conditions] * When the TCNT1A value is transferred to GR1E by an input capture signal while GR1E is functioning as an input capture register * (Initial value) When TCNT1A = GR1E while GR1E is functioning as an output compare register Rev. 5.00 Feb. 24, 2010 Page 205 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * Bit 3--Input Capture/Compare-Match Flag 1D (IMF1D): Status flag that indicates GR1D input capture or comparematch. Bit 3: IMF1D Description 0 [Clearing condition] When IMF1D is read while set to 1, then 0 is written to IMF1D 1 [Setting conditions] * When the TCNT1A value is transferred to GR1D by an input capture signal while GR1D is functioning as an input capture register * (Initial value) When TCNT1A = GR1D while GR1D is functioning as an output compare register * Bit 2--Input Capture/Compare-Match Flag 1C (IMF1C): Status flag that indicates GR1C input capture or comparematch. Bit 2: IMF1C Description 0 [Clearing condition] When IMF1C is read while set to 1, then 0 is written to IMF1C 1 [Setting conditions] * When the TCNT1A value is transferred to GR1C by an input capture signal while GR1C is functioning as an input capture register * (Initial value) When TCNT1A = GR1C while GR1C is functioning as an output compare register * Bit 1--Input Capture/Compare-Match Flag 1B (IMF1B): Status flag that indicates GR1B input capture or comparematch. Bit 1: IMF1B Description 0 [Clearing condition] When IMF1B is read while set to 1, then 0 is written to IMF1B 1 [Setting conditions] * When the TCNT1A value is transferred to GR1B by an input capture signal while GR1B is functioning as an input capture register * (Initial value) When TCNT1A = GR1B while GR1B is functioning as an output compare register * Bit 0--Input Capture/Compare-Match Flag 1A (IMF1A): Status flag that indicates GR1A input capture or comparematch. Bit 0: IMF1A Description 0 [Clearing condition] When IMF1A is read while set to 1, then 0 is written to IMF1A 1 [Setting conditions] * When the TCNT1A value is transferred to GR1A by an input capture signal while GR1A is functioning as an input capture register * (Initial value) When TCNT1A = GR1A while GR1A is functioning as an output compare register Rev. 5.00 Feb. 24, 2010 Page 206 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) TSR1B: TSR1B indicates the status of channel 1 compare-match and overflow. Bit: Note: 15 14 13 12 11 10 9 8 -- -- -- -- -- -- -- OVF1B Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/(W)* Bit: 7 6 5 4 3 2 1 0 -- -- -- -- -- -- -- CMF1 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/(W)* * Only 0 can be written, to clear the flag. * Bits 15 to 9--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 8--Overflow Flag 1B (OVF1B): Status flag that indicates TCNT1B overflow. Bit 8: OVF1B Description 0 [Clearing condition] When OVF1B is read while set to 1, then 0 is written to OVF1B 1 [Setting condition] When the TCNT1B value overflows (from H'FFFF to H'0000) (Initial value) * Bits 7 to 1--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 0--Compare-Match Flag 1 (CMF1): Status flag that indicates OCR1 compare-match. Bit 0: CMF1 Description 0 [Clearing condition] When CMF1 is read while set to 1, then 0 is written to CMF1 1 [Setting condition] When TCNT1B = OCR1 (Initial value) Timer Status Registers 2A and 2B (TSR2A, TSR2B) TSR2A: TSR2A indicates the status of channel 2 input capture, compare-match, and overflow. Bit: 15 14 13 12 11 10 9 8 -- -- -- -- -- -- -- OVF2A Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/(W)* Bit: 7 6 5 4 3 2 1 0 IMF2H IMF2G IMF2F IMF2E IMF2D IMF2C IMF2B IMF2A 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Initial value: R/W: Note: * Only 0 can be written to clear the flag. * Bits 15 to 9--Reserved: These bits are always read as 0. The write value should always be 0. Rev. 5.00 Feb. 24, 2010 Page 207 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * Bit 8--Overflow Flag 2A (OVF2A): Status flag that indicates TCNT2A overflow. Bit 8: OVF2A Description 0 [Clearing condition] When OVF2A is read while set to 1, then 0 is written to OVF2A 1 [Setting condition] When the TCNT2A value overflows (from H'FFFF to H'0000) (Initial value) * Bit 7--Input Capture/Compare-Match Flag 2H (IMF2H): Status flag that indicates GR2H input capture or comparematch. Bit 7: IMF2H Description 0 [Clearing condition] When IMF2H is read while set to 1, then 0 is written to IMF2H 1 [Setting conditions] * When the TCNT2A value is transferred to GR2H by an input capture signal while GR2H is functioning as an input capture register * (Initial value) When TCNT2A = GR2H while GR2H is functioning as an output compare register * Bit 6--Input Capture/Compare-Match Flag 2G (IMF2G): Status flag that indicates GR2G input capture or comparematch. Bit 6: IMF2G Description 0 [Clearing condition] When IMF2G is read while set to 1, then 0 is written to IMF2G 1 [Setting conditions] * When the TCNT2A value is transferred to GR2G by an input capture signal while GR2G is functioning as an input capture register * (Initial value) When TCNT2A = GR2G while GR2G is functioning as an output compare register * Bit 5--Input Capture/Compare-Match Flag 2F (IMF2F): Status flag that indicates GR2F input capture or comparematch. Bit 5: IMF2F Description 0 [Clearing condition] When IMF2F is read while set to 1, then 0 is written to IMF2F 1 [Setting conditions] * When the TCNT2A value is transferred to GR2F by an input capture signal while GR2F is functioning as an input capture register * (Initial value) When TCNT2A = GR2F while GR2F is functioning as an output compare register Rev. 5.00 Feb. 24, 2010 Page 208 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * Bit 4--Input Capture/Compare-Match Flag 2E (IMF2E): Status flag that indicates GR2E input capture or comparematch. Bit 4: IMF2E Description 0 [Clearing condition] When IMF2E is read while set to 1, then 0 is written to IMF2E 1 [Setting conditions] * When the TCNT2A value is transferred to GR2E by an input capture signal while GR2E is functioning as an input capture register * (Initial value) When TCNT2A = GR2E while GR2E is functioning as an output compare register * Bit 3--Input Capture/Compare-Match Flag 2D (IMF2D): Status flag that indicates GR2D input capture or comparematch. Bit 3: IMF2D Description 0 [Clearing condition] When IMF2D is read while set to 1, then 0 is written to IMF2D 1 [Setting conditions] * When the TCNT2A value is transferred to GR2D by an input capture signal while GR2D is functioning as an input capture register * (Initial value) When TCNT2A = GR2D while GR2D is functioning as an output compare register * Bit 2--Input Capture/Compare-Match Flag 2C (IMF2C): Status flag that indicates GR2C input capture or comparematch. Bit 2: IMF2C Description 0 [Clearing condition] When IMF2C is read while set to 1, then 0 is written to IMF2C 1 [Setting conditions] * When the TCNT2A value is transferred to GR2C by an input capture signal while GR2C is functioning as an input capture register * (Initial value) When TCNT2A = GR2C while GR2C is functioning as an output compare register * Bit 1--Input Capture/Compare-Match Flag 2B (IMF2B): Status flag that indicates GR2B input capture or comparematch. Bit 1: IMF2B Description 0 [Clearing condition] When IMF2B is read while set to 1, then 0 is written to IMF2B 1 [Setting conditions] (Initial value) * When the TCNT2A value is transferred to GR2B by an input capture signal while GR2B is functioning as an input capture register * When TCNT2A = GR2B while GR2B is functioning as an output compare register Rev. 5.00 Feb. 24, 2010 Page 209 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * Bit 0--Input Capture/Compare-Match Flag 2A (IMF2A): Status flag that indicates GR2A input capture or comparematch. Bit 0: IMF2A Description 0 [Clearing condition] When IMF2A is read while set to 1, then 0 is written to IMF2A 1 [Setting conditions] * When the TCNT2A value is transferred to GR2A by an input capture signal while GR2A is functioning as an input capture register * (Initial value) When TCNT2A = GR2A while GR2A is functioning as an output compare register TSR2B: TSR2B indicates the status of channel 2 compare-match and overflow. Bit: 14 13 12 11 10 9 8 -- -- -- -- -- -- -- OVF2B Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/(W)* Bit: 7 6 5 4 3 2 1 0 CMF2H CMF2G CMF2F CMF2E CMF2D CMF2C CMF2B CMF2A Initial value: R/W: Note: 15 * 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Only 0 can be written to clear the flag. * Bits 15 to 9--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 8--Overflow Flag 2B (OVF2B): Status flag that indicates TCNT2B overflow. Bit 8: OVF2B Description 0 [Clearing condition] When OVF2B is read while set to 1, then 0 is written to OVF2B 1 [Setting condition] When the TCNT2B value overflows (from H'FFFF to H'0000) (Initial value) * Bit 7--Compare-Match Flag 2H (CMF2H): Status flag that indicates OCR2H compare-match. Bit 7: CMF2H Description 0 [Clearing condition] When CMF2H is read while set to 1, then 0 is written to CMF2H 1 [Setting condition] When TCNT2B = OCR2H Rev. 5.00 Feb. 24, 2010 Page 210 of 950 REJ09B0177-0500 (Initial value) 11. Advanced Timer Unit-II (ATU-II) * Bit 6--Compare-Match Flag 2G (CMF2G): Status flag that indicates OCR2G compare-match. Bit 6: CMF2G Description 0 [Clearing condition] When CMF2G is read while set to 1, then 0 is written to CMF2G 1 [Setting condition] When TCNT2B = OCR2G (Initial value) * Bit 5--Compare-Match Flag 2F (CMF2F): Status flag that indicates OCR2F compare-match. Bit 5: CMF2F Description 0 [Clearing condition] When CMF2F is read while set to 1, then 0 is written to CMF2F 1 [Setting condition] When TCNT2B = OCR2F (Initial value) * Bit 4--Compare-Match Flag 2E (CMF2E): Status flag that indicates OCR2E compare-match. Bit 4: CMF2E Description 0 [Clearing condition] When CMF2E is read while set to 1, then 0 is written to CMF2E 1 [Setting condition] When TCNT2B = OCR2E (Initial value) * Bit 3--Compare-Match Flag 2D (CMF2D): Status flag that indicates OCR2D compare-match. Bit 3: CMF2D Description 0 [Clearing condition] When CMF2D is read while set to 1, then 0 is written to CMF2D 1 [Setting condition] When TCNT2B = OCR2D (Initial value) * Bit 2--Compare-Match Flag 2C (CMF2C): Status flag that indicates OCR2C compare-match. Bit 2: CMF2C Description 0 [Clearing condition] When CMF2C is read while set to 1, then 0 is written to CMF2C 1 [Setting condition] When TCNT2B = OCR2C (Initial value) * Bit 1--Compare-Match Flag 2B (CMF2B): Status flag that indicates OCR2B compare-match. Bit 1: CMF2B Description 0 [Clearing condition] When CMF2B is read while set to 1, then 0 is written to CMF2B 1 [Setting condition] When TCNT2B = OCR2B (Initial value) Rev. 5.00 Feb. 24, 2010 Page 211 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * Bit 0--Compare-Match Flag 2A (CMF2A): Status flag that indicates OCR2A compare-match. Bit 0: CMF2A Description 0 [Clearing condition] When CMF2A is read while set to 1, then 0 is written to CMF2A 1 [Setting condition] When TCNT2B = OCR2A (Initial value) Timer Status Register 3 (TSR3) TSR3 indicates the status of channel 3 to 5 input capture, compare-match, and overflow. Bit: 15 14 13 12 11 10 9 8 -- OVF5 IMF5D IMF5C IMF5B IMF5A OVF4 IMF4D Initial value: 0 0 0 0 0 0 0 0 R/W: R R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Bit: 7 6 5 4 3 2 1 0 IMF4C IMF4B IMF4A OVF3 IMF3D IMF3C IMF3B IMF3A 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Initial value: R/W: Note: * Only 0 can be written to clear the flag. * Bit 15--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 14--Overflow Flag 5 (OVF5): Status flag that indicates TCNT5 overflow. Bit 14: OVF5 Description 0 [Clearing condition] When OVF5 is read while set to 1, then 0 is written to OVF5 1 [Setting condition] When the TCNT5 value overflows (from H'FFFF to H'0000) (Initial value) * Bit 13--Input Capture/Compare-Match Flag 5D (IMF5D): Status flag that indicates GR5D input capture or comparematch. Bit 13: IMF5D Description 0 [Clearing condition] When IMF5D is read while set to 1, then 0 is written to IMF5D 1 [Setting conditions] * When the TCNT5 value is transferred to GR5D by an input capture signal while GR5D is functioning as an input capture register (Initial value) * When TCNT5 = GR5D while GR5D is functioning as an output compare register * When TCNT5 = GR5D while GR5D is functioning as a cycle register in PWM mode Rev. 5.00 Feb. 24, 2010 Page 212 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * Bit 12--Input Capture/Compare-Match Flag 5C (IMF5C): Status flag that indicates GR5C input capture or comparematch. The flag is not set in PWM mode. Bit 12: IMF5C Description 0 [Clearing condition] When IMF5C is read while set to 1, then 0 is written to IMF5C 1 [Setting conditions] * When the TCNT5 value is transferred to GR5C by an input capture signal while GR5C is functioning as an input capture register * (Initial value) When TCNT5 = GR5C while GR5C is functioning as an output compare register * Bit 11--Input Capture/Compare-Match Flag 5B (IMF5B): Status flag that indicates GR5B input capture or comparematch. The flag is not set in PWM mode. Bit 11: IMF5B Description 0 [Clearing condition] When IMF5B is read while set to 1, then 0 is written to IMF5B 1 [Setting conditions] * When the TCNT5 value is transferred to GR5B by an input capture signal while GR5B is functioning as an input capture register * (Initial value) When TCNT5 = GR5B while GR5B is functioning as an output compare register * Bit 10--Input Capture/Compare-Match Flag 5A (IMF5A): Status flag that indicates GR5A input capture or comparematch. The flag is not set in PWM mode. Bit 10: IMF5A Description 0 [Clearing condition] When IMF5A is read while set to 1, then 0 is written to IMF5A 1 [Setting conditions] * When the TCNT5 value is transferred to GR5A by an input capture signal while GR5A is functioning as an input capture register * (Initial value) When TCNT5 = GR5A while GR5A is functioning as an output compare register * Bit 9--Overflow Flag 4 (OVF4): Status flag that indicates TCNT4 overflow. Bit 9: OVF4 Description 0 [Clearing condition] When OVF4 is read while set to 1, then 0 is written to OVF4 1 [Setting condition] When the TCNT4 value overflows (from H'FFFF to H'0000) (Initial value) Rev. 5.00 Feb. 24, 2010 Page 213 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * Bit 8--Input Capture/Compare-Match Flag 4D (IMF4D): Status flag that indicates GR4D input capture or comparematch. Bit 8: IMF4D Description 0 [Clearing condition] When IMF4D is read while set to 1, then 0 is written to IMF4D 1 [Setting conditions] * When the TCNT4 value is transferred to GR4D by an input capture signal while GR4D is functioning as an input capture register (Initial value) * When TCNT4 = GR4D while GR4D is functioning as an output compare register * When TCNT4 = GR4D while GR4D is functioning as a PWM mode synchronous register * Bit 7--Input Capture/Compare-Match Flag 4C (IMF4C): Status flag that indicates GR4C input capture or comparematch. The flag is not set in PWM mode. Bit 7: IMF4C Description 0 [Clearing condition] When IMF4C is read while set to 1, then 0 is written to IMF4C 1 [Setting conditions] * When the TCNT4 value is transferred to GR4C by an input capture signal while GR4C is functioning as an input capture register * (Initial value) When TCNT4 = GR4C while GR4C is functioning as an output compare register * Bit 6--Input Capture/Compare-Match Flag 4B (IMF4B): Status flag that indicates GR4B input capture or comparematch. The flag is not set in PWM mode. Bit 6: IMF4B Description 0 [Clearing condition] When IMF4B is read while set to 1, then 0 is written to IMF4B 1 [Setting conditions] * When the TCNT4 value is transferred to GR4B by an input capture signal while GR4B is functioning as an input capture register * (Initial value) When TCNT4 = GR4B while GR4B is functioning as an output compare register * Bit 5--Input Capture/Compare-Match Flag 4A (IMF4A): Status flag that indicates GR4A input capture or comparematch. The flag is not set in PWM mode. Bit 5: IMF4A Description 0 [Clearing condition] When IMF4A is read while set to 1, then 0 is written to IMF4A 1 [Setting conditions] * When the TCNT4 value is transferred to GR4A by an input capture signal while GR4A is functioning as an input capture register * (Initial value) When TCNT4 = GR4A while GR4A is functioning as an output compare register Rev. 5.00 Feb. 24, 2010 Page 214 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * Bit 4--Overflow Flag 3 (OVF3): Status flag that indicates TCNT3 input capture or compare-match. Bit 4: OVF3 Description 0 [Clearing condition] When OVF3 is read while set to 1, then 0 is written to OVF3 1 [Setting condition] When the TCNT3 value overflows (from H'FFFF to H'0000) (Initial value) * Bit 3--Input Capture/Compare-Match Flag 3D (IMF3D): Status flag that indicates GR3D input capture or comparematch. Bit 3: IMF3D Description 0 [Clearing condition] When IMF3D is read while set to 1, then 0 is written to IMF3D 1 [Setting conditions] * When the TCNT3 value is transferred to GR3D by an input capture signal while GR3D is functioning as an input capture register. However, IMF3D is not set by input capture with a channel 9 compare match as the trigger (Initial value) * When TCNT3 = GR3D while GR3D is functioning as an output compare register * When TCNT3 = GR3D while GR3D is functioning as a synchronous register in PWM mode * Bit 2--Input Capture/Compare-Match Flag 3C (IMF3C): Status flag that indicates GR3C input capture or comparematch. The flag is not set in PWM mode. Bit 2: IMF3C Description 0 [Clearing condition] When IMF3C is read while set to 1, then 0 is written to IMF3C 1 [Setting conditions] * When the TCNT3 value is transferred to GR3C by an input capture signal while GR3C is functioning as an input capture register. However, IMF3C is not set by input capture with a channel 9 compare match as the trigger * (Initial value) When TCNT3 = GR3C while GR3C is functioning as an output compare register * Bit 1--Input Capture/Compare-Match Flag 3B (IMF3B): Status flag that indicates GR3B input capture or comparematch. The flag is not set in PWM mode. Bit 1: IMF3B Description 0 [Clearing condition] When IMF3B is read while set to 1, then 0 is written to IMF3B 1 [Setting conditions] * When the TCNT3 value is transferred to GR3B by an input capture signal while GR3B is functioning as an input capture register. However, IMF3B is not set by input capture with a channel 9 compare match as the trigger * (Initial value) When TCNT3 = GR3B while GR3B is functioning as an output compare register Rev. 5.00 Feb. 24, 2010 Page 215 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * Bit 0--Input Capture/Compare-Match Flag 3A (IMF3A): Status flag that indicates GR3A input capture or comparematch. The flag is not set in PWM mode. Bit 0: IMF3A Description 0 [Clearing condition] When IMF3A is read while set to 1, then 0 is written to IMF3A 1 [Setting conditions] * When the TCNT3 value is transferred to GR3A by an input capture signal while GR3A is functioning as an input capture register. However, IMF3A is not set by input capture with a channel 9 compare match as the trigger * (Initial value) When TCNT3 = GR3A while GR3A is functioning as an output compare register Timer Status Registers 6 and 7 (TSR6, TSR7) TSR6 and TRS7 indicate the channel 6 and 7 free-running counter up-count and down-count status, and cycle register compare status. Bit: 15 14 13 12 11 10 9 8 -- -- -- -- -- -- -- -- Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 UDxD UDxC UDxB UDxA CMFxD CMFxC CMFxB CMFxA Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R/(W)* R/(W)* R/(W)* R/(W)* Notes: x = 6 or 7 * Only 0 can be written to clear the flag. UDxA to UDxD relate to TSR6 only. Bits relating to TSR7 always read 0. * Bits 15 to 8--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 7--Count-Up/Count-Down Flag 6D (UD6D): Status flag that indicates the TCNT6D count operation. Bit 7: UD6D Description 0 Free-running counter TCNT6D operates as an up-counter 1 Free-running counter TCNT6D operates as a down-counter * Bit 6--Count-Up/Count-Down Flag 6C (UD6C): Status flag that indicates the TCNT6C count operation. Bit 6: UD6C Description 0 Free-running counter TCNT6C operates as an up-counter 1 Free-running counter TCNT6C operates as a down-counter Rev. 5.00 Feb. 24, 2010 Page 216 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * Bit 5--Count-Up/Count-Down Flag 6B (UD6B): Status flag that indicates the TCNT6B count operation. Bit 5: UD6B Description 0 Free-running counter TCNT6B operates as an up-counter 1 Free-running counter TCNT6B operates as a down-counter * Bit 4--Count-Up/Count-Down Flag 6A (UD6A): Status flag that indicates the TCNT6A count operation. Bit 4: UD6A Description 0 Free-running counter TCNT6A operates as an up-counter 1 Free-running counter TCNT6A operates as a down-counter * Bit 3--Cycle Register Compare-Match Flag 6D/7D (CMF6D/CMF7D): Status flag that indicates CYLRxD comparematch. Bit 3: CMFxD Description 0 [Clearing condition] When CMFxD is read while set to 1, then 0 is written to CMFxD 1 [Setting conditions] * When TCNTxD = CYLRxD (in non-complementary PWM mode) * (Initial value) When TCNT6D = H'0000 in a down-count (in complementary PWM mode) Note: x = 6 or 7 * Bit 2--Cycle Register Compare-Match Flag 6C/7C (CMF6C/CMF7C): Status flag that indicates CYLRxC comparematch. Bit 2: CMFxC Description 0 [Clearing condition] When CMFxC is read while set to 1, then 0 is written to CMFxC 1 [Setting conditions] * When TCNTxC = CYLRxC (in non-complementary PWM mode) * (Initial value) When TCNT6C = H'0000 in a down-count (in complementary PWM mode) Note: x = 6 or 7 * Bit 1--Cycle Register Compare-Match Flag 6B/7B (CMF6B/CMF7B): Status flag that indicates CYLRxB comparematch. Bit 1: CMFxB Description 0 [Clearing condition] When CMFxB is read while set to 1, then 0 is written to CMFxB 1 [Setting conditions] * When TCNTxB = CYLRxB (in non-complementary PWM mode) * (Initial value) When TCNT6B = H'0000 in a down-count (in complementary PWM mode) Note: x = 6 or 7 Rev. 5.00 Feb. 24, 2010 Page 217 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * Bit 0--Cycle Register Compare-Match Flag 6A/7A (CMF6A/CMF7A): Status flag that indicates CYLRxA comparematch. Bit 0: CMFxA Description 0 [Clearing condition] When CMFxA is read while set to 1, then 0 is written to CMFxA 1 [Setting conditions] * When TCNTxA = CYLRxA (in non-complementary PWM mode) * (Initial value) When TCNT6A = H'0000 in a down-count (in complementary PWM mode) Note: x = 6 or 7 Timer Status Register 8 (TSR8) TSR8 indicates the channel 8 one-shot pulse status. Bit: Initial value: R/W: Bit: Initial value: R/W: Note: * 15 14 13 12 11 10 9 8 OSF8P OSF8O OSF8N OSF8M OSF8L OSF8K OSF8J OSF8I 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* 7 6 5 4 3 2 1 0 OSF8H OSF8G OSF8F OSF8E OSF8D OSF8C OSF8B OSF8A 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Only 0 can be written to clear the flag. * Bit 15--One-Shot Pulse Flag 8P (OSF8P): Status flag that indicates a DCNT8P one-shot pulse. Bit 15: OSF8P Description 0 [Clearing condition] When OSF8P is read while set to 1, then 0 is written to OSF8P 1 [Setting condition] When DCNT8P underflows (Initial value) * Bit 14--One-Shot Pulse Flag 8O (OSF8O): Status flag that indicates a DCNT8O one-shot pulse. Bit 14: OSF8O Description 0 [Clearing condition] When OSF8O is read while set to 1, then 0 is written to OSF8O 1 [Setting condition] When DCNT8O underflows Rev. 5.00 Feb. 24, 2010 Page 218 of 950 REJ09B0177-0500 (Initial value) 11. Advanced Timer Unit-II (ATU-II) * Bit 13--One-Shot Pulse Flag 8N (OSF8N): Status flag that indicates a DCNT8N one-shot pulse. Bit 13: OSF8N Description 0 [Clearing condition] When OSF8N is read while set to 1, then 0 is written to OSF8N 1 [Setting condition] When DCNT8N underflows (Initial value) * Bit 12--One-Shot Pulse Flag 8M (OSF8M): Status flag that indicates a DCNT8M one-shot pulse. Bit 12: OSF8M Description 0 [Clearing condition] When OSF8M is read while set to 1, then 0 is written to OSF8M 1 [Setting condition] When DCNT8M underflows (Initial value) * Bit 11--One-Shot Pulse Flag 8L (OSF8L): Status flag that indicates a DCNT8L one-shot pulse. Bit 11: OSF8L Description 0 [Clearing condition] When OSF8L is read while set to 1, then 0 is written to OSF8L 1 [Setting condition] When DCNT8L underflows (Initial value) * Bit 10--One-Shot Pulse Flag 8K (OSF8K): Status flag that indicates a DCNT8K one-shot pulse. Bit 10: OSF8K Description 0 [Clearing condition] When OSF8K is read while set to 1, then 0 is written to OSF8K 1 [Setting condition] When DCNT8K underflows (Initial value) * Bit 9--One-Shot Pulse Flag 8J (OSF8J): Status flag that indicates a DCNT8J one-shot pulse. Bit 9: OSF8J Description 0 [Clearing condition] When OSF8J is read while set to 1, then 0 is written to OSF8J 1 [Setting condition] When DCNT8J underflows (Initial value) * Bit 8--One-Shot Pulse Flag 8I (OSF8I): Status flag that indicates a DCNT8I one-shot pulse. Bit 8: OSF8I Description 0 [Clearing condition] When OSF8I is read while set to 1, then 0 is written to OSF8I 1 [Setting condition] When DCNT8I underflows (Initial value) Rev. 5.00 Feb. 24, 2010 Page 219 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * Bit 7--One-Shot Pulse Flag 8H (OSF8H): Status flag that indicates a DCNT8H one-shot pulse. Bit 7: OSF8H Description 0 [Clearing condition] When OSF8H is read while set to 1, then 0 is written to OSF8H 1 [Setting condition] When DCNT8H underflows (Initial value) * Bit 6--One-Shot Pulse Flag 8G (OSF8G): Status flag that indicates a DCNT8G one-shot pulse. Bit 6: OSF8G Description 0 [Clearing condition] When OSF8G is read while set to 1, then 0 is written to OSF8G 1 [Setting condition] When DCNT8G underflows (Initial value) * Bit 5--One-Shot Pulse Flag 8F (OSF8F): Status flag that indicates a DCNT8F one-shot pulse. Bit 5: OSF8F Description 0 [Clearing condition] When OSF8F is read while set to 1, then 0 is written to OSF8F 1 [Setting condition] When DCNT8F underflows (Initial value) * Bit 4--One-Shot Pulse Flag 8E (OSF8E): Status flag that indicates a DCNT8E one-shot pulse. Bit 4: OSF8E Description 0 [Clearing condition] When OSF8E is read while set to 1, then 0 is written to OSF8E 1 [Setting condition] When DCNT8E underflows (Initial value) * Bit 3--One-Shot Pulse Flag 8D (OSF8D): Status flag that indicates a DCNT8D one-shot pulse. Bit 3: OSF8D Description 0 [Clearing condition] When OSF8D is read while set to 1, then 0 is written to OSF8D 1 [Setting condition] When DCNT8D underflows (Initial value) * Bit 2--One-Shot Pulse Flag 8C (OSF8C): Status flag that indicates a DCNT8C one-shot pulse. Bit 2: OSF8C Description 0 [Clearing condition] When OSF8C is read while set to 1, then 0 is written to OSF8C 1 [Setting condition] When DCNT8C underflows Rev. 5.00 Feb. 24, 2010 Page 220 of 950 REJ09B0177-0500 (Initial value) 11. Advanced Timer Unit-II (ATU-II) * Bit 1--One-Shot Pulse Flag 8B (OSF8B): Status flag that indicates a DCNT8B one-shot pulse. Bit 1: OSF8B Description 0 [Clearing condition] When OSF8B is read while set to 1, then 0 is written to OSF8B 1 [Setting condition] When DCNT8B underflows (Initial value) * Bit 0--One-Shot Pulse Flag 8A (OSF8A): Status flag that indicates a DCNT8A one-shot pulse. Bit 0: OSF8A Description 0 [Clearing condition] When OSF8A is read while set to 1, then 0 is written to OSF8A 1 [Setting condition] When DCNT8A underflows (Initial value) Timer Status Register 9 (TSR9) TSR9 indicates the channel 9 event counter compare-match status. Bit: Note: 15 14 13 12 11 10 9 8 -- -- -- -- -- -- -- -- Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 -- -- CMF9F CMF9E CMF9D CMF9C CMF9B CMF9A Initial value: 0 0 0 0 0 0 0 0 R/W: R R R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* * Only 0 can be written to clear the flag. * Bits 15 to 6--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 5--Compare-Match Flag 9F (CMF9F): Status flag that indicates GR9F compare-match. Bit 5: CMF9F Description 0 [Clearing condition] When CMF9F is read while set to 1, then 0 is written to CMF9F 1 [Setting condition] When the next edge is input while ECNT9F = GR9F (Initial value) * Bit 4--Compare-Match Flag 9E (CMF9E): Status flag that indicates GR9E compare-match. Bit 4: CMF9E Description 0 [Clearing condition] When CMF9E is read while set to 1, then 0 is written to CMF9E 1 [Setting condition] When the next edge is input while ECNT9E = GR9E (Initial value) Rev. 5.00 Feb. 24, 2010 Page 221 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * Bit 3--Compare-Match Flag 9D (CMF9D): Status flag that indicates GR9D compare-match. Bit 3: CMF9D Description 0 [Clearing condition] When CMF9D is read while set to 1, then 0 is written to CMF9D 1 [Setting condition] When the next edge is input while ECNT9D = GR9D (Initial value) * Bit 2--Compare-Match Flag 9C (CMF9C): Status flag that indicates GR9C compare-match. Bit 2: CMF9C Description 0 [Clearing condition] When CMF9C is read while set to 1, then 0 is written to CMF9C 1 [Setting condition] When the next edge is input while ECNT9C = GR9C (Initial value) * Bit 1--Compare-Match Flag 9B (CMF9B): Status flag that indicates GR9B compare-match. Bit 1: CMF9B Description 0 [Clearing condition] When CMF9B is read while set to 1, then 0 is written to CMF9B 1 [Setting condition] When the next edge is input while ECNT9B = GR9B (Initial value) * Bit 0--Compare-Match Flag 9A (CMF9A): Status flag that indicates GR9A compare-match. Bit 0: CMF9A Description 0 [Clearing condition] When CMF9A is read while set to 1, then 0 is written to CMF9A 1 [Setting condition] When the next edge is input while ECNT9A = GR9A (Initial value) Timer Status Register 11 (TSR11) TSR11 indicates the status of channel 11 input capture, compare-match, and overflow. Bit: Note: 15 14 13 12 11 10 9 8 -- -- -- -- -- -- -- OVF11 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/(W)* Bit: 7 6 5 4 3 2 1 0 -- -- -- -- -- -- IMF11B IMF11A Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R/(W)* R/(W)* * Only 0 can be written to clear the flag. Rev. 5.00 Feb. 24, 2010 Page 222 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * Bits 15 to 9--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 8--Overflow Flag 11 (OVF11): Status flag that indicates TCNT11 overflow. Bit 8: OVF11 Description 0 [Clearing condition] When OVF11 is read while set to 1, then 0 is written to OVF11 1 [Setting condition] When the TCNT11 value overflows (from H'FFFF to H'0000) (Initial value) * Bits 7 to 2--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 1--Input Capture/Compare-Match Flag 11B (IMF11B): Status flag that indicates GR11B input capture or compare-match. Bit 1: IMF11B Description 0 [Clearing condition] When IMF11B is read while set to 1, then 0 is written to IMF11B 1 [Setting conditions] * When the TCNT11 value is transferred to GR11B by an input capture signal while GR11B is functioning as an input capture register * (Initial value) When TCNT11 = GR11B while GR11B is functioning as an output compare register * Bit 0--Input Capture/Compare-Match Flag 11A (IMF11A): Status flag that indicates GR11A input capture or compare-match. Bit 0: IMF11A Description 0 [Clearing condition] When IMF11A is read while set to 1, then 0 is written to IMF11A 1 [Setting conditions] * When the TCNT11 value is transferred to GR11A by an input capture signal while GR11A is functioning as an input capture register * (Initial value) When TCNT11 = GR11A while GR11A is functioning as an output compare register Rev. 5.00 Feb. 24, 2010 Page 223 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) 11.2.6 Timer Interrupt Enable Registers (TIER) The timer interrupt enable registers (TIER) are 16-bit registers. The ATU-II has 11 TIER registers: one each for channels 0, 6 to 9, and 11, two each for channels 1 and 2, and one for channels 3 to 5. For details of channel 10, see section 11.2.26, Channel 10 Registers. Channel Abbreviation Function 0 TIER0 Controls input capture, and overflow interrupt request enabling/disabling. 1 TIER1A, TIER1B Control input capture, compare-match, and overflow interrupt request enabling/disabling. 2 TIER2A, TIER2B 3 TIER3 Controls input capture, compare-match, and overflow interrupt request enabling/disabling. 6 TIER6 Control cycle register compare-match interrupt request enabling/disabling. 7 TIER7 8 TIER8 Controls down-counter output end (low) interrupt request enabling/disabling. 9 TIER9 Controls event counter compare-match interrupt request enabling/disabling. 11 TIER11 Controls input capture, compare-match, and overflow interrupt request enabling/disabling. 4 5 The TIER registers are 16-bit readable/writable registers that control enabling/disabling of free-running counter (TCNT) overflow interrupt requests, channel 0 input capture interrupt requests, channel 1 to 5 and 11 general register input capture/compare-match interrupt requests, channel 6 and 7 compare-match interrupt requests, channel 8 down-counter output end interrupt requests, and channel 9 event counter compare-match interrupt requests. Each TIER is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. Timer Interrupt Enable Register 0 (TIER0) TIER0 controls enabling/disabling of channel 0 input capture and overflow interrupt requests. Bit: 15 14 13 12 11 10 9 8 -- -- -- -- -- -- -- -- Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 -- -- -- OVE0 ICE0D ICE0C ICE0B ICE0A Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R/W R/W R/W R/W R/W * Bits 15 to 5--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 4--Overflow Interrupt Enable 0 (OVE0): Enables or disables interrupt requests by the overflow flag (OVF0) in TSR0 when OVF0 is set to 1. Bit 4: OVE0 Description 0 OVI0 interrupt requested by OVF0 is disabled 1 OVI0 interrupt requested by OVF0 is enabled Rev. 5.00 Feb. 24, 2010 Page 224 of 950 REJ09B0177-0500 (Initial value) 11. Advanced Timer Unit-II (ATU-II) * Bit 3--Input Capture Interrupt Enable 0D (ICE0D): Enables or disables interrupt requests by the input capture flag (ICF0D) in TSR0 when ICF0D is set to 1. Setting the DMAC while interrupt requests are enabled allows the DMAC to be activated by an interrupt request. Bit 3: ICE0D Description 0 ICI0D interrupt requested by ICF0D is disabled 1 ICI0D interrupt requested by ICF0D is enabled (Initial value) * Bit 2--Input Capture Interrupt Enable 0C (ICE0C): Enables or disables interrupt requests by the input capture flag (ICF0C) in TSR0 when ICF0C is set to 1. Setting the DMAC while interrupt requests are enabled allows the DMAC to be activated by an interrupt request. Bit 2: ICE0C Description 0 ICI0C interrupt requested by ICF0C is disabled 1 ICI0C interrupt requested by ICF0C is enabled (Initial value) * Bit 1--Input Capture Interrupt Enable 0B (ICE0B): Enables or disables interrupt requests by the input capture flag (ICF0B) in TSR0 when ICF0B is set to 1. Setting the DMAC while interrupt requests are enabled allows the DMAC to be activated by an interrupt request. Bit 1: ICE0B Description 0 ICI0B interrupt requested by ICF0B is disabled 1 ICI0B interrupt requested by ICF0B is enabled (Initial value) * Bit 0--Input Capture Interrupt Enable 0A (ICE0A): Enables or disables interrupt requests by the input capture flag (ICF0A) in TSR0 when ICF0A is set to 1. Setting the DMAC while interrupt requests are enabled allows the DMAC to be activated by an interrupt request. Bit 0: ICE0A Description 0 ICI0A interrupt requested by ICF0A is disabled 1 ICI0A interrupt requested by ICF0A is enabled (Initial value) Timer Interrupt Enable Registers 1A and 1B (TIER1A, TIER1B) TIER1A: TIER1A controls enabling/disabling of channel 1 input capture, compare-match, and overflow interrupt requests. Bit: 15 14 13 12 11 10 9 8 Bit name: -- -- -- -- -- -- -- OVE1A Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/W Bit: 7 6 5 4 3 2 1 0 IME1H IME1G IME1F IME1E IME1D IME1C IME1B IME1A Bit name: Initial value: R/W: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Rev. 5.00 Feb. 24, 2010 Page 225 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * Bits 15 to 9--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 8--Overflow Interrupt Enable 1A (OVE1A): Enables or disables interrupt requests by OVF1A in TSR1A when OVF1A is set to 1. Bit 8: OVE1A Description 0 OVI1A interrupt requested by OVF1A is disabled 1 OVI1A interrupt requested by OVF1A is enabled (Initial value) * Bit 7--Input Capture/Compare-Match Interrupt Enable 1H (IME1H): Enables or disables interrupt requests by IMF1H in TSR1A when IMF1H is set to 1. Bit 7: IME1H Description 0 IMI1H interrupt requested by IMF1H is disabled 1 IMI1H interrupt requested by IMF1H is enabled (Initial value) * Bit 6--Input Capture/Compare-Match Interrupt Enable 1G (IME1G): Enables or disables interrupt requests by IMF1G in TSR1A when IMF1G is set to 1. Bit 6: IME1G Description 0 IMI1G interrupt requested by IMF1G is disabled 1 IMI1G interrupt requested by IMF1G is enabled (Initial value) * Bit 5--Input Capture/Compare-Match Interrupt Enable 1F (IME1F): Enables or disables interrupt requests by IMF1F in TSR1A when IMF1F is set to 1. Bit 5: IME1F Description 0 IMI1F interrupt requested by IMF1F is disabled 1 IMI1F interrupt requested by IMF1F is enabled (Initial value) * Bit 4--Input Capture/Compare-Match Interrupt Enable 1E (IME1E): Enables or disables interrupt requests by IMF1E in TSR1A when IMF1E is set to 1. Bit 4: IME1E Description 0 IMI1E interrupt requested by IMF1E is disabled 1 IMI1E interrupt requested by IMF1E is enabled (Initial value) * Bit 3--Input Capture/Compare-Match Interrupt Enable 1D (IME1D): Enables or disables interrupt requests by IMF1D in TSR1A when IMF1D is set to 1. Bit 3: IME1D Description 0 IMI1D interrupt requested by IMF1D is disabled 1 IMI1D interrupt requested by IMF1D is enabled Rev. 5.00 Feb. 24, 2010 Page 226 of 950 REJ09B0177-0500 (Initial value) 11. Advanced Timer Unit-II (ATU-II) * Bit 2--Input Capture/Compare-Match Interrupt Enable 1C (IME1C): Enables or disables interrupt requests by IMF1C in TSR1A when IMF1C is set to 1. Bit 2: IME1C Description 0 IMI1C interrupt requested by IMF1C is disabled 1 IMI1C interrupt requested by IMF1C is enabled (Initial value) * Bit 1--Input Capture/Compare-Match Interrupt Enable 1B (IME1B): Enables or disables interrupt requests by IMF1B in TSR1A when IMF1B is set to 1. Bit 1: IME1B Description 0 IMI1B interrupt requested by IMF1B is disabled 1 IMI1B interrupt requested by IMF1B is enabled (Initial value) * Bit 0--Input Capture/Compare-Match Interrupt Enable 1A (IME1A): Enables or disables interrupt requests by IMF1A in TSR1A when IMF1A is set to 1. Bit 0: IME1A Description 0 IMI1A interrupt requested by IMF1A is disabled 1 IMI1A interrupt requested by IMF1A is enabled (Initial value) TIER1B: TIER1B controls enabling/disabling of channel 1 compare-match and overflow interrupt requests. Bit: 15 14 13 12 11 10 9 8 -- -- -- -- -- -- -- OVE1B Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/W Bit: 7 6 5 4 3 2 1 0 -- -- -- -- -- -- -- CME1 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/W * Bits 15 to 9--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 8--Overflow Interrupt Enable 1B (OVE1B): Enables or disables interrupt requests by OVF1B in TSR1B when OVF1B is set to 1. Bit 8: OVE1B Description 0 OVI1B interrupt requested by OVF1B is disabled 1 OVI1B interrupt requested by OVF1B is enabled (Initial value) * Bits 7 to 1--Reserved: These bits are always read as 0. The write value should always be 0. Rev. 5.00 Feb. 24, 2010 Page 227 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * Bit 0--Compare-Match Interrupt Enable 1 (CME1): Enables or disables interrupt requests by CMF1 in TSR1B when CMF1 is set to 1. Bit 0: CME1 Description 0 CMI1 interrupt requested by CMF1 is disabled 1 CMI1 interrupt requested by CMF1 is enabled (Initial value) Timer Interrupt Enable Registers 2A and 2B (TIER2A, TIER2B) TIER2A: TIER2A controls enabling/disabling of channel 2 input capture, compare-match, and overflow interrupt requests. Bit: 15 14 13 12 11 10 9 8 -- -- -- -- -- -- -- OVE2A Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/W Bit: 7 6 5 4 3 2 1 0 IME2H IME2G IME2F IME2E IME2D IME2C IME2B IME2A Initial value: R/W: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W * Bits 15 to 9--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 8--Overflow Interrupt Enable 2A (OVE2A): Enables or disables interrupt requests by OVF2A in TSR2A when OVF2A is set to 1. Bit 8: OVE2A Description 0 OVI2A interrupt requested by OVF2A is disabled 1 OVI2A interrupt requested by OVF2A is enabled (Initial value) * Bit 7--Input Capture/Compare-Match Interrupt Enable 2H (IME2H): Enables or disables interrupt requests by IMF2H in TSR2A when IMF2H is set to 1. Bit 7: IME2H Description 0 IMI2H interrupt requested by IMF2H is disabled 1 IMI2H interrupt requested by IMF2H is enabled (Initial value) * Bit 6--Input Capture/Compare-Match Interrupt Enable 2G (IME2G): Enables or disables interrupt requests by IMF2G in TSR2A when IMF2G is set to 1. Bit 6: IME2G Description 0 IMI2G interrupt requested by IMF2G is disabled 1 IMI2G interrupt requested by IMF2G is enabled Rev. 5.00 Feb. 24, 2010 Page 228 of 950 REJ09B0177-0500 (Initial value) 11. Advanced Timer Unit-II (ATU-II) * Bit 5--Input Capture/Compare-Match Interrupt Enable 2F (IME2F): Enables or disables interrupt requests by IMF2F in TSR2A when IMF2F is set to 1. Bit 5: IME2F Description 0 IMI2F interrupt requested by IMF2F is disabled 1 IMI2F interrupt requested by IMF2F is enabled (Initial value) * Bit 4--Input Capture/Compare-Match Interrupt Enable 2E (IME2E): Enables or disables interrupt requests by IMF2E in TSR2A when IMF2E is set to 1. Bit 4: IME2E Description 0 IMI2E interrupt requested by IMF2E is disabled 1 IMI2E interrupt requested by IMF2E is enabled (Initial value) * Bit 3--Input Capture/Compare-Match Interrupt Enable 2D (IME2D): Enables or disables interrupt requests by IMF2D in TSR2A when IMF2D is set to 1. Bit 3: IME2D Description 0 IMI2D interrupt requested by IMF2D is disabled 1 IMI2D interrupt requested by IMF2D is enabled (Initial value) * Bit 2--Input Capture/Compare-Match Interrupt Enable 2C (IME2C): Enables or disables interrupt requests by IMF2C in TSR2A when IMF2C is set to 1. Bit 2: IME2C Description 0 IMI2C interrupt requested by IMF2C is disabled 1 IMI2C interrupt requested by IMF2C is enabled (Initial value) * Bit 1--Input Capture/Compare-Match Interrupt Enable 2B (IME2B): Enables or disables interrupt requests by IMF2B in TSR2A when IMF2B is set to 1. Bit 1: IME2B Description 0 IMI2B interrupt requested by IMF2B is disabled 1 IMI2B interrupt requested by IMF2B is enabled (Initial value) * Bit 0--Input Capture/Compare-Match Interrupt Enable 2A (IME2A): Enables or disables interrupt requests by IMF2A in TSR2A when IMF2A is set to 1. Bit 0: IME2A Description 0 IMI2A interrupt requested by IMF2A is disabled 1 IMI2A interrupt requested by IMF2A is enabled (Initial value) Rev. 5.00 Feb. 24, 2010 Page 229 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) TIER2B: TIER2B controls enabling/disabling of channel 2 compare-match and overflow interrupt requests. Bit: 15 14 13 12 11 10 9 8 -- -- -- -- -- -- -- OVE2B Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/W Bit: 7 6 5 4 3 2 1 0 CME2H CME2G CME2F CME2E CME2D CME2C CME2B CME2A 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: R/W: * Bits 15 to 9--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 8--Overflow Interrupt Enable 2B (OVE2B): Enables or disables interrupt requests by OVF2B in TSR2B when OVF2B is set to 1. Bit 8: OVE2B Description 0 OVI2B interrupt requested by OVF2B is disabled 1 OVI2B interrupt requested by OVF2B is enabled (Initial value) * Bit 7--Compare-Match Interrupt Enable 2H (CME2H): Enables or disables interrupt requests by CMF2F in TSR2B when CMF2H is set to 1. Bit 7: CME2H Description 0 CMI2H interrupt requested by CMF2H is disabled 1 CMI2H interrupt requested by CMF2H is enabled (Initial value) * Bit 6--Compare-Match Interrupt Enable 2G (CME2G): Enables or disables interrupt requests by CMF2G in TSR2B when CMF2G is set to 1. Bit 6: CME2G Description 0 CMI2G interrupt requested by CMF2G is disabled 1 CMI2G interrupt requested by CMF2G is enabled (Initial value) * Bit 5--Compare-Match Interrupt Enable 2F (CME2F): Enables or disables interrupt requests by CMF2F in TSR2B when CMF2F is set to 1. Bit 5: CME2F Description 0 CMI2F interrupt requested by CMF2F is disabled 1 CMI2F interrupt requested by CMF2F is enabled (Initial value) * Bit 4--Compare-Match Interrupt Enable 2E (CME2E): Enables or disables interrupt requests by CMF2E in TSR2B when CMF2E is set to 1. Bit 4: CME2E Description 0 CMI2E interrupt requested by CMF2E is disabled 1 CMI2E interrupt requested by CMF2E is enabled Rev. 5.00 Feb. 24, 2010 Page 230 of 950 REJ09B0177-0500 (Initial value) 11. Advanced Timer Unit-II (ATU-II) * Bit 3--Compare-Match Interrupt Enable 2D (CME2D): Enables or disables interrupt requests by CMF2D in TSR2B when CMF2D is set to 1. Bit 3: CME2D Description 0 CMI2D interrupt requested by CMF2D is disabled 1 CMI2D interrupt requested by CMF2D is enabled (Initial value) * Bit 2--Compare-Match Interrupt Enable 2C (CME2C): Enables or disables interrupt requests by CMF2C in TSR2B when CMF2C is set to 1. Bit 2: CME2C Description 0 CMI2C interrupt requested by CMF2C is disabled 1 CMI2C interrupt requested by CMF2C is enabled (Initial value) * Bit 1--Compare-Match Interrupt Enable 2B (CME2BB): Enables or disables interrupt requests by CMF2B in TSR2B when CMF2B is set to 1. Bit 1: CME2B Description 0 CMI2B interrupt requested by CMF2B is disabled 1 CMI2B interrupt requested by CMF2B is enabled (Initial value) * Bit 0--Compare-Match Interrupt Enable 2A (CME2A): Enables or disables interrupt requests by CMF2A in TSR2B when CMF2A is set to 1. Bit 0: CME2A Description 0 CMI2A interrupt requested by CMF2A is disabled 1 CMI2A interrupt requested by CMF2A is enabled (Initial value) Timer Interrupt Enable Register 3 (TIER3) TIER3 controls enabling/disabling of channel 3 to 5 input capture, compare-match, and overflow interrupt requests. Bit: 15 14 13 12 11 10 9 8 -- OVE5 IME5D IME5C IME5B IME5A OVE4 IME4D Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R/W R/W R/W R/W Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 IME4C IME4B IME4A OVE3 IME3D IME3C IME3B IME3A 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W * Bit 15--Reserved: This bit is always read as 0. The write value should always be 0. Rev. 5.00 Feb. 24, 2010 Page 231 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * Bit 14--Overflow Interrupt Enable 5 (OVE5): Enables or disables interrupt requests by OVF5 in TSR3 when OVF5 is set to 1. Bit 14: OVE5 Description 0 OVI5 interrupt requested by OVF5 is disabled 1 OVI5 interrupt requested by OVF5 is enabled (Initial value) * Bit 13--Input Capture/Compare-Match Interrupt Enable 5D (IME5D): Enables or disables interrupt requests by IMF5D in TSR3 when IMF5D is set to 1. Bit 13: IME5D Description 0 IMI5D interrupt requested by IMF5D is disabled 1 IMI5D interrupt requested by IMF5D is enabled (Initial value) * Bit 12--Input Capture/Compare-Match Interrupt Enable 5C (IME5C): Enables or disables interrupt requests by IMF5C in TSR3 when IMF5C is set to 1. Bit 12: IME5C Description 0 IMI5C interrupt requested by IMF5C is disabled 1 IMI5C interrupt requested by IMF5C is enabled (Initial value) * Bit 11--Input Capture/Compare-Match Interrupt Enable 5B (IME5B): Enables or disables interrupt requests by IMF5B in TSR3 when IMF5B is set to 1. Bit 11: IME5B Description 0 IMI5B interrupt requested by IMF5B is disabled 1 IMI5B interrupt requested by IMF5B is enabled (Initial value) * Bit 10--Input Capture/Compare-Match Interrupt Enable 5A (IME5A): Enables or disables interrupt requests by IMF5A in TSR3 when IMF5A is set to 1. Bit 10: IME5A Description 0 IMI5A interrupt requested by IMF5A is disabled 1 IMI5A interrupt requested by IMF5A is enabled (Initial value) * Bit 9--Overflow Interrupt Enable 4 (OVE4): Enables or disables interrupt requests by OVF4 in TSR3 when OVF4 is set to 1. Bit 9: OVE4 Description 0 OVI4 interrupt requested by OVF4 is disabled 1 OVI4 interrupt requested by OVF4 is enabled Rev. 5.00 Feb. 24, 2010 Page 232 of 950 REJ09B0177-0500 (Initial value) 11. Advanced Timer Unit-II (ATU-II) * Bit 8--Input Capture/Compare-Match Interrupt Enable 4D (IME4D): Enables or disables interrupt requests by IMF4D in TSR3 when IMF4D is set to 1. Bit 8: IME4D Description 0 IMI4D interrupt requested by IMF4D is disabled 1 IMI4D interrupt requested by IMF4D is enabled (Initial value) * Bit 7--Input Capture/Compare-Match Interrupt Enable 4C (IME4C): Enables or disables interrupt requests by IMF4C in TSR3 when IMF4C is set to 1. Bit 7: IME4C Description 0 IMI4C interrupt requested by IMF4C is disabled 1 IMI4C interrupt requested by IMF4C is enabled (Initial value) * Bit 6--Input Capture/Compare-Match Interrupt Enable 4B (IME4B): Enables or disables interrupt requests by IMF4B in TSR3 when IMF4B is set to 1. Bit 6: IME4B Description 0 IMI4B interrupt requested by IMF4B is disabled 1 IMI4B interrupt requested by IMF4B is enabled (Initial value) * Bit 5--Input Capture/Compare-Match Interrupt Enable 4A (IME4A): Enables or disables interrupt requests by IMF4A in TSR3 when IMF4A is set to 1. Bit 5: IME4A Description 0 IMI4A interrupt requested by IMF4A is disabled 1 IMI4A interrupt requested by IMF4A is enabled (Initial value) * Bit 4--Overflow Interrupt Enable 3 (OVE3): Enables or disables interrupt requests by OVF3 in TSR3 when OVF3 is set to 1. Bit 4: OVE3 Description 0 OVI3 interrupt requested by OVF3 is disabled 1 OVI3 interrupt requested by OVF3 is enabled (Initial value) * Bit 3--Input Capture/Compare-Match Interrupt Enable 3D (IME3D): Enables or disables interrupt requests by IMF3D in TSR3 when IMF3D is set to 1. Bit 3: IME3D Description 0 IMI3D interrupt requested by IMF3D is disabled 1 IMI3D interrupt requested by IMF3D is enabled (Initial value) Rev. 5.00 Feb. 24, 2010 Page 233 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * Bit 2--Input Capture/Compare-Match Interrupt Enable 3C (IME3C): Enables or disables interrupt requests by IMF3C in TSR3 when IMF3C is set to 1. Bit 2: IME3C Description 0 IMI3C interrupt requested by IMF3C is disabled 1 IMI3C interrupt requested by IMF3C is enabled (Initial value) * Bit 1--Input Capture/Compare-Match Interrupt Enable 3B (IME3B): Enables or disables interrupt requests by IMF3B in TSR3 when IMF3B is set to 1. Bit 1: IME3B Description 0 IMI3B interrupt requested by IMF3B is disabled 1 IMI3B interrupt requested by IMF3B is enabled (Initial value) * Bit 0--Input Capture/Compare-Match Interrupt Enable 3A (IME3A): Enables or disables interrupt requests by IMF3A in TSR3 when IMF3A is set to 1. Bit 0: IME3A Description 0 IMI3A interrupt requested by IMF3A is disabled 1 IMI3A interrupt requested by IMF3A is enabled (Initial value) Timer Interrupt Enable Registers 6 and 7 (TIER6, TIER7) TIER6 and TIER7 control enabling/disabling of channel 6 and 7 cycle register compare interrupt requests. Bit: 15 14 13 12 11 10 9 8 -- -- -- -- -- -- -- -- Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 -- -- -- -- CMExD CMExC CMExB CMExA Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R/W R/W R/W R/W Note: x = 6 or 7 * Bits 15 to 4--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 3--Cycle Register Compare-Match Interrupt Enable 6D/7D (CME6D/CME7D): Enables or disables interrupt requests by CMFxD in TSR6 or TSR7 when CMFxD is set to 1. Setting the DMAC while interrupt requests are enabled allows the DMAC to be activated by an interrupt request. Bit 3: CMExD Description 0 CMIxD interrupt requested by CMFxD is disabled 1 CMIxD interrupt requested by CMFxD is enabled Note: x = 6 or 7 Rev. 5.00 Feb. 24, 2010 Page 234 of 950 REJ09B0177-0500 (Initial value) 11. Advanced Timer Unit-II (ATU-II) * Bit 2--Cycle Register Compare-Match Interrupt Enable 6C/7C (CME6C/CME7C): Enables or disables interrupt requests by CMFxC in TSR6 or TSR7 when CMFxC is set to 1. Setting the DMAC while interrupt requests are enabled allows the DMAC to be activated by an interrupt request. Bit 2: CMExC Description 0 CMIxC interrupt requested by CMFxC is disabled 1 CMIxC interrupt requested by CMFxC is enabled (Initial value) Note: x = 6 or 7 * Bit 1--Cycle Register Compare-Match Interrupt Enable 6B/7B (CME6B/CME7B): Enables or disables interrupt requests by CMFxB in TSR6 or TSR7 when CMFxB is set to 1. Setting the DMAC while interrupt requests are enabled allows the DMAC to be activated by an interrupt request. Bit 1: CMExB Description 0 CMIxB interrupt requested by CMFxB is disabled 1 CMIxB interrupt requested by CMFxB is enabled (Initial value) Note: x = 6 or 7 * Bit 0--Cycle Register Compare-Match Interrupt Enable 6A/7A (CME6A/CME7A): Enables or disables interrupt requests by CMFxA in TSR6 or TSR7 when CMFxA is set to 1. Setting the DMAC while interrupt requests are enabled allows the DMAC to be activated by an interrupt request. Bit 0: CMExA Description 0 CMIxA interrupt requested by CMFxA is disabled 1 CMIxA interrupt requested by CMFxA is enabled (Initial value) Note: x = 6 or 7 Timer Interrupt Enable Register 8 (TIER8) TIER8 controls enabling/disabling of channel 8 one-shot pulse interrupt requests. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 OSE8P OSE8O OSE8N OSE8M OSE8L OSE8K OSE8J OSE8I 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 OSE8H OSE8G OSE8F OSE8E OSE8D OSE8C OSE8B OSE8A 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W * Bit 15--One-Shot Pulse Interrupt Enable 8P (OSE8P): Enables or disables interrupt requests by OSF8P in TSR8 when OSF8P is set to 1. Bit 15: OSE8P Description 0 OSI8P interrupt requested by OSF8P is disabled 1 OSI8P interrupt requested by OSF8P is enabled (Initial value) Rev. 5.00 Feb. 24, 2010 Page 235 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * Bit 14--One-Shot Pulse Interrupt Enable 8O (OSE8O): Enables or disables interrupt requests by OSF8O in TSR8 when OSF8O is set to 1. Bit 14: OSE8O Description 0 OSI8O interrupt requested by OSF8O is disabled 1 OSI8O interrupt requested by OSF8O is enabled (Initial value) * Bit 13--One-Shot Pulse Interrupt Enable 8N (OSE8N): Enables or disables interrupt requests by OSF8N in TSR8 when OSF8N is set to 1. Bit 13: OSE8N Description 0 OSI8N interrupt requested by OSF8N is disabled 1 OSI8N interrupt requested by OSF8N is enabled (Initial value) * Bit 12--One-Shot Pulse Interrupt Enable 8M (OSE8M): Enables or disables interrupt requests by OSF8M in TSR8 when OSF8M is set to 1. Bit 12: OSE8M Description 0 OSI8M interrupt requested by OSF8M is disabled 1 OSI8M interrupt requested by OSF8M is enabled (Initial value) * Bit 11--One-Shot Pulse Interrupt Enable 8L (OSE8L): Enables or disables interrupt requests by OSF8L in TSR8 when OSF8L is set to 1. Bit 11: OSE8L Description 0 OSI8L interrupt requested by OSF8L is disabled 1 OSI8L interrupt requested by OSF8L is enabled (Initial value) * Bit 10--One-Shot Pulse Interrupt Enable 8K (OSE8K): Enables or disables interrupt requests by OSF8K in TSR8 when OSF8K is set to 1. Bit 10: OSE8K Description 0 OSI8K interrupt requested by OSF8K is disabled 1 OSI8K interrupt requested by OSF8K is enabled (Initial value) * Bit 9--One-Shot Pulse Interrupt Enable 8J (OSE8J): Enables or disables interrupt requests by OSF8J in TSR8 when OSF8J is set to 1. Bit 9: OSE8J Description 0 OSI8J interrupt requested by OSF8J is disabled 1 OSI8J interrupt requested by OSF8J is enabled Rev. 5.00 Feb. 24, 2010 Page 236 of 950 REJ09B0177-0500 (Initial value) 11. Advanced Timer Unit-II (ATU-II) * Bit 8--One-Shot Pulse Interrupt Enable 8I (OSE8I): Enables or disables interrupt requests by OSF8I in TSR8 when OSF8I is set to 1. Bit 8: OSE8I Description 0 OSI8I interrupt requested by OSF8I is disabled 1 OSI8I interrupt requested by OSF8I is enabled (Initial value) * Bit 7--One-Shot Pulse Interrupt Enable 8H (OSE8H): Enables or disables interrupt requests by OSF8H in TSR8 when OSF8H is set to 1. Bit 7: OSE8H Description 0 OSI8H interrupt requested by OSF8H is disabled 1 OSI8H interrupt requested by OSF8H is enabled (Initial value) * Bit 6--One-Shot Pulse Interrupt Enable 8G (OSE8G): Enables or disables interrupt requests by OSF8G in TSR8 when OSF8G is set to 1. Bit 6: OSE8G Description 0 OSI8G interrupt requested by OSF8G is disabled 1 OSI8G interrupt requested by OSF8G is enabled (Initial value) * Bit 5--One-Shot Pulse Interrupt Enable 8F (OSE8F): Enables or disables interrupt requests by OSF8F in TSR8 when OSF8F is set to 1. Bit 5: OSE8F Description 0 OSI8F interrupt requested by OSF8F is disabled 1 OSI8F interrupt requested by OSF8F is enabled (Initial value) * Bit 4--One-Shot Pulse Interrupt Enable 8E (OSE8E): Enables or disables interrupt requests by OSF8E in TSR8 when OSF8E is set to 1. Bit 4: OSE8E Description 0 OSI8E interrupt requested by OSF8E is disabled 1 OSI8E interrupt requested by OSF8E is enabled (Initial value) * Bit 3--One-Shot Pulse Interrupt Enable 8D (OSE8D): Enables or disables interrupt requests by OSF8D in TSR8 when OSF8D is set to 1. Bit 3: OSE8D Description 0 OSI8D interrupt requested by OSF8D is disabled 1 OSI8D interrupt requested by OSF8D is enabled (Initial value) Rev. 5.00 Feb. 24, 2010 Page 237 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * Bit 2--One-Shot Pulse Interrupt Enable 8C (OSE8C): Enables or disables interrupt requests by OSF8C in TSR8 when OSF8C is set to 1. Bit 2: OSE8C Description 0 OSI8C interrupt requested by OSF8C is disabled 1 OSI8C interrupt requested by OSF8C is enabled (Initial value) * Bit 1--One-Shot Pulse Interrupt Enable 8B (OSE8B): Enables or disables interrupt requests by OSF8B in TSR8 when OSF8B is set to 1. Bit 1: OSE8B Description 0 OSI8B interrupt requested by OSF8B is disabled 1 OSI8B interrupt requested by OSF8B is enabled (Initial value) * Bit 0--One-Shot Pulse Interrupt Enable 8A (OSE8A): Enables or disables interrupt requests by OSF8A in TSR8 when OSF8A is set to 1. Bit 0: OSE8A Description 0 OSI8A interrupt requested by OSF8A is disabled 1 OSI8A interrupt requested by OSF8A is enabled (Initial value) Timer Interrupt Enable Register 9 (TIER9) TIER9 controls enabling/disabling of channel 9 event counter compare-match interrupt requests. Bit: 15 14 13 12 11 10 9 8 -- -- -- -- -- -- -- -- Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 -- -- CME9F CME9E CME9D CME9C CME9B CME9A Initial value: 0 0 0 0 0 0 0 0 R/W: R R R/W R/W R/W R/W R/W R/W * Bits 15 to 6--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 5--Compare-Match Interrupt Enable 9F (CME9F): Enables or disables interrupt requests by CMF9F in TSR9 when CMF9F is set to 1. Bit 5: CME9F Description 0 CMI9F interrupt requested by CMF9F is disabled 1 CMI9F interrupt requested by CMF9F is enabled Rev. 5.00 Feb. 24, 2010 Page 238 of 950 REJ09B0177-0500 (Initial value) 11. Advanced Timer Unit-II (ATU-II) * Bit 4--Compare-Match Interrupt Enable 9E (CME9E): Enables or disables interrupt requests by CMF9E in TSR9 when CMF9E is set to 1. Bit 4: CME9E Description 0 CMI9E interrupt requested by CMF9E is disabled 1 CMI9E interrupt requested by CMF9E is enabled (Initial value) * Bit 3--Compare-Match Interrupt Enable 9D (CME9D): Enables or disables interrupt requests by CMF9D in TSR9 when CMF9D is set to 1. Bit 3: CME9D Description 0 CMI9D interrupt requested by CMF9D is disabled 1 CMI9D interrupt requested by CMF9D is enabled (Initial value) * Bit 2--Compare-Match Interrupt Enable 9C (CME9C): Enables or disables interrupt requests by CMF9C in TSR9 when CMF9C is set to 1. Bit 2: CME9C Description 0 CMI9C interrupt requested by CMF9C is disabled 1 CMI9C interrupt requested by CMF9C is enabled (Initial value) * Bit 1--Compare-Match Interrupt Enable 9B (CME9B): Enables or disables interrupt requests by CMF9B in TSR9 when CMF9B is set to 1. Bit 1: CME9B Description 0 CMI9B interrupt requested by CMF9B is disabled 1 CMI9B interrupt requested by CMF9B is enabled (Initial value) * Bit 0--Compare-Match Interrupt Enable 9A (CME9A): Enables or disables interrupt requests by CMF9A in TSR9 when CMF9A is set to 1. Bit 0: CME9A Description 0 CMI9A interrupt requested by CMF9A is disabled 1 CMI9A interrupt requested by CMF9A is enabled (Initial value) Rev. 5.00 Feb. 24, 2010 Page 239 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) Timer Interrupt Enable Register 11 (TIER11) TIER11 controls enabling/disabling of channel 11 input capture, compare-match, and overflow interrupt requests. Bit: 15 14 13 12 11 10 9 8 -- -- -- -- -- -- -- OVE11 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/W Bit: 7 6 5 4 3 2 1 0 -- -- -- -- -- -- IME11B IME11A Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R/W R/W * Bits 15 to 9--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 8--Overflow Interrupt Enable 11 (OVE11): Enables or disables interrupt requests by OVF11 in TSR11 when OVF11 is set to 1. Bit 8: OVE11 Description 0 OVI11 interrupt requested by OVF11 is disabled 1 OVI11 interrupt requested by OVF11 is enabled (Initial value) * Bits 7 to 2--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 1--Input Capture/Compare-Match Interrupt Enable 11B (IME11B): Enables or disables interrupt requests by IMF11B in TSR11 when IMF11B is set to 1. Bit 1: IME11B Description 0 IMI11B interrupt requested by IMF11B is disabled 1 IMI11B interrupt requested by IMF11B is enabled (Initial value) * Bit 0--Input Capture/Compare-Match Interrupt Enable 11A (IME11A): Enables or disables interrupt requests by IMF11A in TSR11 when IMF11A is set to 1. Bit 0: IME11A Description 0 IMI11A interrupt requested by IMF11A is disabled 1 IMI11A interrupt requested by IMF11A is enabled Rev. 5.00 Feb. 24, 2010 Page 240 of 950 REJ09B0177-0500 (Initial value) 11. Advanced Timer Unit-II (ATU-II) 11.2.7 Interval Interrupt Request Registers (ITVRR) The interval interrupt request registers (ITVRR) are 8-bit registers. The ATU-II has three ITVRR registers in channel 0. Channel Abbreviation Function 0 ITVRR1 TCNT0 bit 6 to 9 interval interrupt generation and A/D2 converter activation ITVRR2A TCNT0 bit 10 to 13 interval interrupt generation and A/D0 converter activation ITVRR2B TCNT0 bit 10 to 13 interval interrupt generation and A/D1 converter activation Interval Interrupt Request Register 1 (ITVRR1) Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 ITVA9 ITVA8 ITVA7 ITVA6 ITVE9 ITVE8 ITVE7 ITVE6 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W ITVRR1 is an 8-bit readable/writable register that detects the rise of bits corresponding to the channel 0 free-running counter (TCNT0) and controls cyclic interrupt output and A/D2 converter activation. ITVRR1 is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. * Bit 7--A/D2 Converter Interval Activation Bit 9 (ITVA9): A/D2 converter activation setting bit corresponding to bit 9 in TCNT0. The rise of bit 9 in TCNT0 is ANDed with ITVA9, and the result is output to the A/D2 converter as an activation signal. Bit 7: ITVA9 Description 0 A/D2 converter activation by rise of TCNT0 bit 9 is disabled 1 A/D2 converter activation by rise of TCNT0 bit 9 is enabled (Initial value) * Bit 6--A/D2 Converter Interval Activation Bit 8 (ITVA8): A/D2 converter activation setting bit corresponding to bit 8 in TCNT0. The rise of bit 8 in TCNT0 is ANDed with ITVA8, and the result is output to the A/D2 converter as an activation signal. Bit 6: ITVA8 Description 0 A/D2 converter activation by rise of TCNT0 bit 8 is disabled 1 A/D2 converter activation by rise of TCNT0 bit 8 is enabled (Initial value) * Bit 5--A/D2 Converter Interval Activation Bit 7 (ITVA7): A/D2 converter activation setting bit corresponding to bit 7 in TCNT0. The rise of bit 7 in TCNT0 is ANDed with ITVA7, and the result is output to the A/D2 converter as an activation signal. Bit 5: ITVA7 Description 0 A/D2 converter activation by rise of TCNT0 bit 7 is disabled 1 A/D2 converter activation by rise of TCNT0 bit 7 is enabled (Initial value) Rev. 5.00 Feb. 24, 2010 Page 241 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * Bit 4--A/D2 Converter Interval Activation Bit 6 (ITVA6): A/D2 converter activation setting bit corresponding to bit 6 in TCNT0. The rise of bit 6 in TCNT0 is ANDed with ITVA6, and the result is output to the A/D2 converter as an activation signal. Bit 4: ITVA6 Description 0 A/D2 converter activation by rise of TCNT0 bit 6 is disabled 1 A/D2 converter activation by rise of TCNT0 bit 6 is enabled (Initial value) * Bit 3--Interval Interrupt Bit 9 (ITVE9): INTC interval interrupt setting bit corresponding to bit 9 in TCNT0. The rise of bit 9 in TCNT0 is ANDed with ITVE9, the result is stored in IIF1 in TSR0, and an interrupt request is sent to the CPU. Bit 3: ITVE9 Description 0 Interrupt request (ITV1) by rise of TCNT0 bit 9 is disabled 1 Interrupt request (ITV1) by rise of TCNT0 bit 9 is enabled (Initial value) * Bit 2--Interval Interrupt Bit 8 (ITVE8): INTC interval interrupt setting bit corresponding to bit 8 in TCNT0. The rise of bit 8 in TCNT0 is ANDed with ITVE8, the result is stored in IIF1 in TSR0, and an interrupt request is sent to the CPU. Bit 2: ITVE8 Description 0 Interrupt request (ITV1) by rise of TCNT0 bit 8 is disabled 1 Interrupt request (ITV1) by rise of TCNT0 bit 8 is enabled (Initial value) * Bit 1--Interval Interrupt Bit 7 (ITVE7): INTC interval interrupt setting bit corresponding to bit 7 in TCNT0. The rise of bit 7 in TCNT0 is ANDed with ITVE7, the result is stored in IIF1 in TSR0, and an interrupt request is sent to the CPU. Bit 1: ITVE7 Description 0 Interrupt request (ITV1) by rise of TCNT0 bit 7 is disabled 1 Interrupt request (ITV1) by rise of TCNT0 bit 7 is enabled (Initial value) * Bit 0--Interval Interrupt Bit 6 (ITVE6): INTC interval interrupt setting bit corresponding to bit 6 in TCNT0. The rise of bit 6 in TCNT0 is ANDed with ITVE6, the result is stored in IIF1 in TSR0, and an interrupt request is sent to the CPU. Bit 0: ITVE6 Description 0 Interrupt request (ITV1) by rise of TCNT0 bit 6 is disabled 1 Interrupt request (ITV1) by rise of TCNT0 bit 6 is enabled Rev. 5.00 Feb. 24, 2010 Page 242 of 950 REJ09B0177-0500 (Initial value) 11. Advanced Timer Unit-II (ATU-II) Interval Interrupt Request Registers 2A and 2B (ITVRR2A, ITVRR2B) Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 ITVA13x ITVA12x ITVA11x ITVA10x ITVE13x ITVE12x ITVE11x ITVE10x 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Note: x = A or B * Bit 7--A/D0 / A/D1 Converter Interval Activation Bit 13A/13B (ITVA13A/ITVA13B): A/D0 or A/D1 (ITVRR2A: A/D0; ITVRR2B: A/D1) converter activation setting bit corresponding to bit 13 in TCNT0. The rise of bit 13 in TCNT0 is ANDed with ITVA13x, and the result is output to the A/D0 or A/D1 converter as an activation signal. Bit 7: ITVA13x Description 0 A/D0 or A/D1 converter activation by rise of TCNT0 bit 13 is disabled 1 A/D0 or A/D1 converter activation by rise of TCNT0 bit 13 is enabled (Initial value) Note: x = A or B * Bit 6--A/D0 / A/D1 Converter Interval Activation Bit 12A/12B (ITVA12A/ITVA12B): A/D0 or A/D1 (ITVRR2A: A/D0; ITVRR2B: A/D1) converter activation setting bit corresponding to bit 12 in TCNT0. The rise of bit 12 in TCNT0 is ANDed with ITVA12x, and the result is output to the A/D0 or A/D1 converter as an activation signal. Bit 6: ITVA12x Description 0 A/D0 or A/D1 converter activation by rise of TCNT0 bit 12 is disabled 1 A/D0 or A/D1 converter activation by rise of TCNT0 bit 12 is enabled (Initial value) Note: x = A or B * Bit 5--A/D0 / A/D1 Converter Interval Activation Bit 11A/11B (ITVA11A/ITVA11B): A/D0 or A/D1 (ITVRR2A: A/D0; ITVRR2B: A/D1) converter activation setting bit corresponding to bit 11 in TCNT0. The rise of bit 11 in TCNT0 is ANDed with ITVA11x, and the result is output to the A/D0 or A/D1 converter as an activation signal. Bit 5: ITVA11x Description 0 A/D0 or A/D1 converter activation by rise of TCNT0 bit 11 is disabled 1 A/D0 or A/D1 converter activation by rise of TCNT0 bit 11 is enabled (Initial value) Note: x = A or B * Bit 4--A/D0 / A/D1 Converter Interval Activation Bit 10A/10B (ITVA10A/ITVA10B): A/D0 or A/D1 (ITVRR2A: A/D0; ITVRR2B: A/D1) converter activation setting bit corresponding to bit 10 in TCNT0. The rise of bit 10 in TCNT0 is ANDed with ITVA10x, and the result is output to the A/D0 or A/D1 converter as an activation signal. Bit 4: ITVA10x Description 0 A/D0 or A/D1 converter activation by rise of TCNT0 bit 10 is disabled 1 A/D0 or A/D1 converter activation by rise of TCNT0 bit 10 is enabled (Initial value) Note: x = A or B Rev. 5.00 Feb. 24, 2010 Page 243 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * Bit 3--Interval Interrupt Bit 13A/13B (ITVE13A/ITVE13B): INTC interval interrupt setting bit corresponding to bit 13 in TCNT0. The rise of bit 13 in TCNT0 is ANDed with ITVE13x, the result is stored in IIF2x in TSR0, and an interrupt request is sent to the CPU. Bit 3: ITVE13x Description 0 Interrupt request (ITV2x) by rise of TCNT0 bit 13 is disabled 1 Interrupt request (ITV2x) by rise of TCNT0 bit 13 is enabled (Initial value) Note: x = A or B * Bit 2--Interval Interrupt Bit 12A/12B (ITVE12A/ITVE12B): INTC interval interrupt setting bit corresponding to bit 12 in TCNT0. The rise of bit 12 in TCNT0 is ANDed with ITVE12x, the result is stored in IIF2x in TSR0, and an interrupt request is sent to the CPU. Bit 2: ITVE12x Description 0 Interrupt request (ITV2x) by rise of TCNT0 bit 12 is disabled 1 Interrupt request (ITV2x) by rise of TCNT0 bit 12 is enabled (Initial value) Note: x = A or B * Bit 1--Interval Interrupt Bit 11A/11B (ITVE11A/ITVE11B): INTC interval interrupt setting bit corresponding to bit 11 in TCNT0. The rise of bit 11 in TCNT0 is ANDed with ITVE11x, the result is stored in IIF2x in TSR0, and an interrupt request is sent to the CPU. Bit 1: ITVE11x Description 0 Interrupt request (ITV2x) by rise of TCNT0 bit 11 is disabled 1 Interrupt request (ITV2x) by rise of TCNT0 bit 11 is enabled (Initial value) Note: x = A or B * Bit 0--Interval Interrupt Bit 10 (ITVE10): INTC interval interrupt setting bit corresponding to bit 10 in TCNT0. The rise of bit 10 in TCNT0 is ANDed with ITVE10x, the result is stored in IIF2x in TSR0, and an interrupt request is sent to the CPU. Bit 0: ITVE10x Description 0 Interrupt request (ITV2x) by rise of TCNT0 bit 10 is disabled 1 Interrupt request (ITV2x) by rise of TCNT0 bit 10 is enabled Note: x = A or B For details, see section 11.3.7, Interval Timer Operation. Rev. 5.00 Feb. 24, 2010 Page 244 of 950 REJ09B0177-0500 (Initial value) 11. Advanced Timer Unit-II (ATU-II) 11.2.8 Trigger Mode Register (TRGMDR) The trigger mode register (TRGMDR) is an 8-bit register. The ATU-II has one TRGMDR register. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 TRGMD -- -- -- -- -- -- -- 0 0 0 0 0 0 0 0 R/W R R R R R R R TRGMDR is an 8-bit readable/writable register that selects whether a channel 1 compare-match is used as a channel 8 one-shot pulse start trigger or as a one-shot pulse terminate trigger when channel 1 and channel 8 are used in combination. TRGMDR is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. * Bit 7--Trigger Mode Selection Register (TRGMD): Selects the channel 8 one-shot pulse start trigger/one-shot pulse terminate trigger setting. Bit 7: TRGMD Description 0 One-shot pulse start trigger (TCNT1B = OCR1) (Initial value) One-shot pulse terminate trigger (TCNT1A = GR1A-GR1H) 1 One-shot pulse start trigger (TCNT1A = GR1A-GR1H) One-shot pulse terminate trigger (TCNT1B = OCR1) * Bits 6 to 0--Reserved: These bits are always read as 0. The write value should always be 0. 11.2.9 Timer Mode Register (TMDR) The timer mode register (TMDR) is an 8-bit register. The ATU-II has one TDR register. Bit: 7 6 5 4 3 2 1 0 -- -- -- -- -- T5PWM T4PWM T3PWM Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R/W R/W R/W TMDR is an 8-bit readable/writable register that specifies whether channels 3 to 5 are used in input capture/output compare mode or PWM mode. TMDR is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. * Bits 7 to 3--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 2--PWM Mode 5 (T5PWM): Selects whether channel 5 operates in input capture/output compare mode or PWM mode. Bit 2: T5PWM Description 0 Channel 5 operates in input capture/output compare mode 1 Channel 5 operates in PWM mode (Initial value) Rev. 5.00 Feb. 24, 2010 Page 245 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) When bit T5PWM is set to 1 to select PWM mode, pins TIO5A to TIO5C become PWM output pins, general register 5D (GR5D) functions as a cycle register, and general registers 5A to 5C (GR5A to GR5C) function as duty registers. Settings in the timer I/O control registers (TIOR5A, TIOR5B) are invalid, and general registers 5A to 5D (GR5A to GR5D) can be written to. Do not use the TIO5D pin as a timer output. * Bit 1--PWM Mode 4 (T4PWM): Selects whether channel 4 operates in input capture/output compare mode or PWM mode. Bit 1: T4PWM Description 0 Channel 4 operates in input capture/output compare mode 1 Channel 4 operates in PWM mode (Initial value) When bit T4PWM is set to 1 to select PWM mode, pins TIO4A to TIO4C become PWM output pins, general register 4D (GR4D) functions as a cycle register, and general registers 4A to 4C (GR4A to GR4C) function as duty registers. Settings in the timer I/O control registers (TIOR4A, TIOR4B) are invalid, and general registers 4A to 4D (GR4A to GR4D) can be written to. Do not use the TIO4D pin as a timer output. * Bit 0--PWM Mode 3 (T3PWM): Selects whether channel 3 operates in input capture/output compare mode or PWM mode. Bit 0: T3PWM Description 0 Channel 3 operates in input capture/output compare mode 1 Channel 3 operates in PWM mode (Initial value) When bit T3PWM is set to 1 to select PWM mode, pins TIO3A to TIO3C become PWM output pins, general register 3D (GR3D) functions as a cycle register, and general registers 3A to 3C (GR3A to GR3C) function as duty registers. Settings in the timer I/O control registers (TIOR3A, TIOR3B) are invalid, and general registers 3A to 3D (GR3A to GR3D) can be written to. Do not use the TIO3D pin as a timer output. 11.2.10 PWM Mode Register (PMDR) The PWM mode register (PMDR) is an 8-bit register. The ATU-II has one PMDR register. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 DTSELD DTSELC DTSELB DTSELA CNTSELD CNTSELC CNTSELB CNTSELA 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PMDR is an 8-bit readable/writable register that selects whether channel 6 PWM output is set to on-duty/off-duty, or to non-complementary PWM mode/complementary PWM mode. PMDR is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. * Bit 7--Duty Selection Register D (DTSELD): Selects whether channel 6D TO6D output PWM is set to on-duty or to off-duty. Bit 7: DTSELD Description 0 TO6D PWM output is on-duty 1 TO6D PWM output is off-duty Rev. 5.00 Feb. 24, 2010 Page 246 of 950 REJ09B0177-0500 (Initial value) 11. Advanced Timer Unit-II (ATU-II) * Bit 6--Duty Selection Register C (DTSELC): Selects whether channel 6C TO6C output PWM is set to on-duty or to off-duty. Bit 6: DTSELC Description 0 TO6C PWM output is on-duty 1 TO6C PWM output is off-duty (Initial value) * Bit 5--Duty Selection Register B (DTSELB): Selects whether channel 6B TO6B output PWM is set to on-duty or to off-duty. Bit 5: DTSELB Description 0 TO6B PWM output is on-duty 1 TO6B PWM output is off-duty (Initial value) * Bit 4--Duty Selection Register A (DTSELA): Selects whether channel 6A TO6A output PWM is set to on-duty or to off-duty. Bit 4: DTSELA Description 0 TO6A PWM output is on-duty 1 TO6A PWM output is off-duty (Initial value) * Bit 3--Counter Selection Register D (CNTSELD): Selects whether channel 6D PWM is set to non-complementary PWM mode or to complementary PWM mode. Bit 3: CNTSELD Description 0 TCNT6D is set to non-complementary PWM mode 1 TCNT6D is set to complementary PWM mode (Initial value) * Bit 2--Counter Selection Register C (CNTSELC): Selects whether channel 6C PWM is set to non-complementary PWM mode or to complementary PWM mode. Bit 2: CNTSELC Description 0 TCNT6C is set to non-complementary PWM mode 1 TCNT6C is set to complementary PWM mode (Initial value) * Bit 1--Counter Selection Register B (CNTSELB): Selects whether channel 6B PWM is set to non-complementary PWM mode or to complementary PWM mode. Bit 1: CNTSELB Description 0 TCNT6B is set to non-complementary PWM mode 1 TCNT6B is set to complementary PWM mode (Initial value) Rev. 5.00 Feb. 24, 2010 Page 247 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * Bit 0--Counter Selection Register A (CNTSELA): Selects whether channel 6A PWM is set to non-complementary PWM mode or to complementary PWM mode. Bit 0: CNTSELA Description 0 TCNT6A is set to non-complementary PWM mode 1 TCNT6A is set to complementary PWM mode (Initial value) 11.2.11 Down-Count Start Register (DSTR) The down-count start register (DSTR) is a 16-bit register. The ATU-II has one DSTR register in channel 8. Bit: Initial value: R/W: Bit: Initial value: R/W: Note: * 15 14 13 12 11 10 9 8 DST8P DST8O DST8N DST8M DST8L DST8K DST8J DST8I 0 0 0 0 0 0 0 0 R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* 7 6 5 4 3 2 1 0 DST8H DST8G DST8F DST8E DST8D DST8C DST8B DST8A 0 0 0 0 0 0 0 0 R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Only 1 can be written. DSTR is a 16-bit readable/writable register that starts the channel 8 down-counter (DCNT). When the one-shot pulse function is used, a value of 1 can be set in a DST8x bit at any time by the user program, except when the corresponding DCNT8x value is H'0000. The DST8x bits are cleared to 0 automatically when the DCNT value overflows. When the offset one-shot pulse function is used, DST8x is automatically set to 1 (except when the DCNT8x value is H'0000) when a compare-match occurs between the channel 1 or 2 free-running counter (TCNT) and a general register (GR) or the output compare register (OCR1) while the corresponding timer connection register (TCNR) bit is set to 1. As regards DST8I to DST8P, if the RLDEN bit in the reload enable register (RLDENR) is set to 1 and the reload register (RLDR8) value is not H'0000, a reload is performed into the corresponding DCNT8x, and the DST8x bit is set to 1. DST8x is automatically cleared to 0 when the DCNT8x vaue underflows, or by input of a channel 1 or 2 one-shot terminate trigger signal set in the trigger mode register (TRGMDR) while the corresponding one-shot pulse terminate register (OTR) bit is set to 1, whichever occurs first. DCNT8x is cleared to H'0000 when underflow occurs. DSTR is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. For details, see sections 11.3.5, One-Shot Pulse Function, and 11.3.6, Offset One-Shot Pulse Function and Output Cutoff Function. Rev. 5.00 Feb. 24, 2010 Page 248 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * Bit 15--Down-Count Start 8P (DST8P): Starts down-counter 8P (DCNT8P). Bit 15: DST8P 0 Description DCNT8P is halted (Initial value) [Clearing condition] When the DCNT8P value underflows, or on channel 2 (GR2H) compare-match 1 DCNT8P counts [Setting conditions] * One-shot pulse function: Set by user program (DCNT8P H'0000) * Offset one-shot pulse function: Set on OCR2H compare-match (DCNT8P H'0000 or reload possible) or by user program (DCNT8P H'0000) * Bit 14--Down-Count Start 8O (DST8O): Starts down-counter 8O (DCNT8O). Bit 14: DST8O Description 0 DCNT8O is halted (Initial value) [Clearing condition] When the DCNT8O value underflows, or on channel 2 (GR2G) compare-match 1 DCNT8O counts [Setting conditions] * One-shot pulse function: Set by user program (DCNT8O H'0000) * Offset one-shot pulse function: Set on OCR2G compare-match (DCNT8O H'0000 or reload possible) or by user program (DCNT8O H'0000) * Bit 13--Down-Count Start 8N (DST8N): Starts down-counter 8N (DCNT8N). Bit 13: DST8N Description 0 DCNT8N is halted (Initial value) [Clearing condition] When the DCNT8N value underflows, or on channel 2 (GR2F) compare-match 1 DCNT8N counts [Setting conditions] * One-shot pulse function: Set by user program (DCNT8N H'0000) * Offset one-shot pulse function: Set on OCR2F compare-match (DCNT8N H'0000 or reload possible) or by user program (DCNT8N H'0000) * Bit 12--Down-Count Start 8M (DST8M): Starts down-counter 8M (DCNT8M). Bit 12: DST8M 0 Description DCNT8M is halted (Initial value) [Clearing condition] When the DCNT8M value underflows, or on channel 2 (GR2E) compare-match 1 DCNT8M counts [Setting conditions] * One-shot pulse function: Set by user program (DCNT8M H'0000) * Offset one-shot pulse function: Set on OCR2E compare-match (DCNT8M H'0000 or reload possible) or by user program (DCNT8M H'0000) Rev. 5.00 Feb. 24, 2010 Page 249 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * Bit 11--Down-Count Start 8L (DST8L): Starts down-counter 8L (DCNT8L). Bit 11: DST8L 0 Description DCNT8L is halted (Initial value) [Clearing condition] When the DCNT8L value underflows, or on channel 2 (GR2D) compare-match 1 DCNT8L counts [Setting conditions] * One-shot pulse function: Set by user program (DCNT8L H'0000) * Offset one-shot pulse function: Set on OCR2D compare-match (DCNT8L H'0000 or reload possible) or by user program (DCNT8L H'0000) * Bit 10--Down-Count Start 8K (DST8K): Starts down-counter 8K (DCNT8K). Bit 10: DST8K Description 0 DCNT8K is halted (Initial value) [Clearing condition] When the DCNT8K value underflows, or on channel 2 (GR2C) compare-match 1 DCNT8K counts [Setting conditions] * One-shot pulse function: Set by user program (DCNT8K H'0000) * Offset one-shot pulse function: Set on OCR2C compare-match (DCNT8K H'0000 or reload possible) or by user program (DCNT8K H'0000) * Bit 9--Down-Count Start 8J (DST8J): Starts down-counter 8J (DCNT8J). Bit 9: DST8J Description 0 DCNT8J is halted (Initial value) [Clearing condition] When the DCNT8J value underflows, or on channel 2 (GR2B) compare-match 1 DCNT8J counts [Setting conditions] * One-shot pulse function: Set by user program (DCNT8J H'0000) * Offset one-shot pulse function: Set on OCR2B compare-match (DCNT8J H'0000 or reload possible) or by user program (DCNT8J H'0000) * Bit 8--Down-Count Start 8I (DST8I): Starts down-counter 8I (DCNT8I). Bit 8: DST8I 0 Description DCNT8I is halted (Initial value) [Clearing condition] When the DCNT8I value underflows, or on channel 2 (GR2A) compare-match 1 DCNT8I counts [Setting conditions] * One-shot pulse function: Set by user program (DCNT8I H'0000) * Offset one-shot pulse function: Set on OCR2A compare-match (DCNT8I H'0000 or reload possible) or by user program (DCNT8I H'0000) Rev. 5.00 Feb. 24, 2010 Page 250 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * Bit 7--Down-Count Start 8H (DST8H): Starts down-counter 8H (DCNT8H). Bit 7: DST8H 0 Description DCNT8H is halted (Initial value) [Clearing condition] When the DCNT8H value underflows, or on channel 1 (GR1H or OCR1) compare-match 1 DCNT8H counts [Setting conditions] * One-shot pulse function: Set by user program (DCNT8H H'0000) * Offset one-shot pulse function: Set on OCR1 compare-match or GR1H compare-match, or by user program (DCNT8H H'0000) * Bit 6--Down-Count Start 8G (DST8G): Starts down-counter 8G (DCNT8G). Bit 6: DST8G Description 0 DCNT8G is halted (Initial value) [Clearing condition] When the DCNT8G value underflows, or on channel 1 (GR1G or OCR1) compare-match 1 DCNT8G counts [Setting conditions] * One-shot pulse function: Set by user program (DCNT8G H'0000) * Offset one-shot pulse function: Set on OCR1 compare-match or GR1G compare-match, or by user program (DCNT8G H'0000) * Bit 5--Down-Count Start 8F (DST8F): Starts down-counter 8F (DCNT8F). Bit 5: DST8F Description 0 DCNT8F is halted (Initial value) [Clearing condition] When the DCNT8F value underflows, or on channel 1 (GR1F or OCR1) compare-match 1 DCNT8F counts [Setting conditions] * One-shot pulse function: Set by user program (DCNT8F H'0000) * Offset one-shot pulse function: Set on OCR1 compare-match or GR1F compare-match, or by user program (DCNT8F H'0000) * Bit 4--Down-Count Start 8E (DST8E): Starts down-counter 8E (DCNT8E). Bit 4: DST8E 0 Description DCNT8E is halted (Initial value) [Clearing condition] When the DCNT8E value underflows, or on channel 1 (GR1E or OCR1) compare-match 1 DCNT8E counts [Setting conditions] * One-shot pulse function: Set by user program (DCNT8E H'0000) * Offset one-shot pulse function: Set on OCR1 compare-match or GR1E compare-match, or by user program (DCNT8E H'0000) Rev. 5.00 Feb. 24, 2010 Page 251 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * Bit 3--Down-Count Start 8D (DST8D): Starts down-counter 8D (DCNT8D). Bit 3: DST8D 0 Description DCNT8D is halted (Initial value) [Clearing condition] When the DCNT8D value underflows, or on channel 1 (GR1D or OCR1) compare-match 1 DCNT8D counts [Setting conditions] * One-shot pulse function: Set by user program (DCNT8D H'0000) * Offset one-shot pulse function: Set on OCR1 compare-match or GR1D compare-match, or by user program (DCNT8D H'0000) * Bit 2--Down-Count Start 8C (DST8C): Starts down-counter 8C (DCNT8C). Bit 2: DST8C Description 0 DCNT8C is halted (Initial value) [Clearing condition] When the DCNT8C value underflows, or on channel 1 (GR1C or OCR1) compare-match 1 DCNT8C counts [Setting conditions] * One-shot pulse function: Set by user program (DCNT8C H'0000) * Offset one-shot pulse function: Set on OCR1 compare-match or GR1C compare-match, or by user program (DCNT8C H'0000) * Bit 1--Down-Count Start 8B (DST8B): Starts down-counter 8B (DCNT8B). Bit 1: DST8B Description 0 DCNT8B is halted (Initial value) [Clearing condition] When the DCNT8B value underflows, or on channel 1 (GR1B or OCR1) compare-match 1 DCNT8B counts [Setting conditions] * One-shot pulse function: Set by user program (DCNT8B H'0000) * Offset one-shot pulse function: Set on OCR1 compare-match or GR1B compare-match, or by user program (DCNT8B H'0000) * Bit 0--Down-Count Start 8A (DST8A): Starts down-counter 8A (DCNT8A). Bit 0: DST8A 0 Description DCNT8A is halted (Initial value) [Clearing condition] When the DCNT8A value underflows, or on channel 1 (GR1A or OCR1) compare-match 1 DCNT8A counts [Setting conditions] * One-shot pulse function: Set by user program (DCNT8A H'0000) * Offset one-shot pulse function: Set on OCR1 compare-match or GR1A compare-match, or by user program (DCNT8A H'0000) Rev. 5.00 Feb. 24, 2010 Page 252 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) 11.2.12 Timer Connection Register (TCNR) The timer connection register (TCNR) is a 16-bit register. The ATU-II has one TCNR register in channel 8. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 CN8P CN8O CN8N CN8M CN8L CN8K CN8J CN8I 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 CN8H CN8G CN8F CN8E CN8D CN8C CN8B CN8A 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W TCNR is a 16-bit readable/writable register that enables or disables connection between the channel 8 down-count start register (DSTR) and channel 1 and 2 compare-match signals (down-count start triggers). Channel 1 down-count start triggers A to H are channel 1 OCR1 compare-match signals or GR1x compare-match signals (set in TRGMDR). Channel 2 down-count start triggers A to H are channel 2 OCR2x compare-match signals. When GR1x compare-matches are used, set TIOR1A to TIOR1D to allow compare-matches. TCNR is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. For details, see sections 11.3.5, One-Shot Pulse Function, and 11.3.6, Offset One-Shot Pulse Function and Output Cutoff Function. * Bit 15--Connection Flag 8P (CN8P): Enables or disables connection between DST8P and the channel 2 down-count start trigger. Bit 15: CN8P Description 0 Connection between DST8P and channel 2 down-count start trigger H is disabled (Initial value) 1 Connection between DST8P and channel 2 down-count start trigger H is enabled * Bit 14--Connection Flag 8O (CN8O): Enables or disables connection between DST8O and the channel 2 down-count start trigger. Bit 14: CN8O Description 0 Connection between DST8O and channel 2 down-count start trigger G is disabled (Initial value) 1 Connection between DST8O and channel 2 down-count start trigger G is enabled * Bit 13--Connection Flag 8N (CN8N): Enables or disables connection between DST8N and the channel 2 down-count start trigger. Bit 13: CN8N Description 0 Connection between DST8N and channel 2 down-count start trigger F is disabled (Initial value) 1 Connection between DST8N and channel 2 down-count start trigger F is enabled Rev. 5.00 Feb. 24, 2010 Page 253 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * Bit 12--Connection Flag 8M (CN8M): Enables or disables connection between DST8M and the channel 2 down-count start trigger. Bit 12: CN8M Description 0 Connection between DST8M and channel 2 down-count start trigger E is disabled (Initial value) 1 Connection between DST8M and channel 2 down-count start trigger E is enabled * Bit 11--Connection Flag 8L (CN8L): Enables or disables connection between DST8L and the channel 2 down-count start trigger. Bit 11: CN8L Description 0 Connection between DST8L and channel 2 down-count start trigger D is disabled (Initial value) 1 Connection between DST8L and channel 2 down-count start trigger D is enabled * Bit 10--Connection Flag 8K (CN8K): Enables or disables connection between DST8K and the channel 2 down-count start trigger. Bit 10: CN8K Description 0 Connection between DST8K and channel 2 down-count start trigger C is disabled (Initial value) 1 Connection between DST8K and channel 2 down-count start trigger C is enabled * Bit 9--Connection Flag 8J (CN8J): Enables or disables connection between DST8J and the channel 2 down-count start trigger. Bit 9: CN8J Description 0 Connection between DST8J and channel 2 down-count start trigger B is disabled (Initial value) 1 Connection between DST8J and channel 2 down-count start trigger B is enabled * Bit 8--Connection Flag 8I (CN8I): Enables or disables connection between DST8I and the channel 2 down-count start trigger. Bit 8: CN8I Description 0 Connection between DST8I and channel 2 down-count start trigger A is disabled (Initial value) 1 Connection between DST8I and channel 2 down-count start trigger A is enabled * Bit 7--Connection Flag 8H (CN8H): Enables or disables connection between DST8H and the channel 1 down-count start trigger. Bit 7: CN8H Description 0 Connection between DST8H and channel 1 down-count start trigger H is disabled (Initial value) 1 Connection between DST8H and channel 1 down-count start trigger H is enabled Rev. 5.00 Feb. 24, 2010 Page 254 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * Bit 6--Connection Flag 8G (CN8G): Enables or disables connection between DST8G and the channel 1 down-count start trigger. Bit 6: CN8G Description 0 Connection between DST8G and channel 1 down-count start trigger G is disabled (Initial value) 1 Connection between DST8G and channel 1 down-count start trigger G is enabled * Bit 5--Connection Flag 8F (CN8F): Enables or disables connection between DST8F and the channel 1 down-count start trigger. Bit 5: CN8F Description 0 Connection between DST8F and channel 1 down-count start trigger F is disabled (Initial value) 1 Connection between DST8F and channel 1 down-count start trigger F is enabled * Bit 4--Connection Flag 8E (CN8E): Enables or disables connection between DST8E and the channel 1 down-count start trigger. Bit 4: CN8E Description 0 Connection between DST8E and channel 1 down-count start trigger E is disabled (Initial value) 1 Connection between DST8E and channel 1 down-count start trigger E is enabled * Bit 3--Connection Flag 8D (CN8D): Enables or disables connection between DST8D and the channel 1 down-count start trigger. Bit 3: CN8D Description 0 Connection between DST8D and channel 1 down-count start trigger D is disabled (Initial value) 1 Connection between DST8D and channel 1 down-count start trigger D is enabled * Bit 2--Connection Flag 8C (CN8C): Enables or disables connection between DST8C and the channel 1 down-count start trigger. Bit 2: CN8C Description 0 Connection between DST8C and channel 1 down-count start trigger C is disabled (Initial value) 1 Connection between DST8C and channel 1 down-count start trigger C is enabled * Bit 1--Connection Flag 8B (CN8B): Enables or disables connection between DST8B and the channel 1 down-count start trigger. Bit 1: CN8B Description 0 Connection between DST8B and channel 1 down-count start trigger B is disabled (Initial value) 1 Connection between DST8B and channel 1 down-count start trigger B is enabled Rev. 5.00 Feb. 24, 2010 Page 255 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * Bit 0--Connection Flag 8A (CN8A): Enables or disables connection between DST8A and the channel 1 down-count start trigger. Bit 0: CN8A Description 0 Connection between DST8A and channel 1 down-count start trigger A is disabled (Initial value) 1 Connection between DST8A and channel 1 down-count start trigger A is enabled 11.2.13 One-Shot Pulse Terminate Register (OTR) The one-shot pulse terminate register (OTR) is a 16-bit register. The ATU-II has one OTR register in channel 8. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 OTEP OTEO OTEN OTEM OTEL OTEK OTEJ OTEI 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 OTEH OTEG OTEF OTEE OTED OTEC OTEB OTEA 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W OTR is a 16-bit readable/writable register that enables or disables forced termination of channel 8 one-shot pulse output by channel 1 and 2 compare-match signals. When one-shot pulse output is forcibly terminated, the corresponding DSTR bit and down-counter are cleared, and the corresponding TSR8 bit is set. The channel 1 one-shot pulse terminate signal is generated by GR1A to GR1H compare-matches and OCR1 compare-match (see TRGMDR). The channel 2 one-shot pulse terminate signal is generated by GR2A to GR2H compare-matches. To generate the terminate signal with GR1A to GR1H and GR2A to GR2H, select the respective compare-matches in TIOR1A to TIOR1D. OTR is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. * Bit 15--One-Shot Pulse Terminate Enable P (OTEP): Enables or disables forced termination of output by channel 2 down-counter terminate trigger H. Bit 15: OTEP Description 0 Forced termination of TO8P by down-counter terminate trigger is disabled 1 Forced termination of TO8P by down-counter terminate trigger is enabled (Initial value) * Bit 14--One-Shot Pulse Terminate Enable O (OTEO): Enables or disables forced termination of output by channel 2 down-counter terminate trigger G. Bit 14: OTEO Description 0 Forced termination of TO8O by down-counter terminate trigger is disabled 1 Forced termination of TO8O by down-counter terminate trigger is enabled Rev. 5.00 Feb. 24, 2010 Page 256 of 950 REJ09B0177-0500 (Initial value) 11. Advanced Timer Unit-II (ATU-II) * Bit 13--One-Shot Pulse Terminate Enable N (OTEN): Enables or disables forced termination of output by channel 2 down-counter terminate trigger F. Bit 13: OTEN Description 0 Forced termination of TO8N by down-counter terminate trigger is disabled 1 Forced termination of TO8N by down-counter terminate trigger is enabled (Initial value) * Bit 12--One-Shot Pulse Terminate Enable M (OTEM): Enables or disables forced termination of output by channel 2 down-counter terminate trigger E. Bit 12: OTEM Description 0 Forced termination of TO8M by down-counter terminate trigger is disabled 1 Forced termination of TO8M by down-counter terminate trigger is enabled (Initial value) * Bit 11--One-Shot Pulse Terminate Enable L (OTEL): Enables or disables forced termination of output by channel 2 down-counter terminate trigger D. Bit 11: OTEL Description 0 Forced termination of TO8L by down-counter terminate trigger is disabled 1 Forced termination of TO8L by down-counter terminate trigger is enabled (Initial value) * Bit 10--One-Shot Pulse Terminate Enable K (OTEK): Enables or disables forced termination of output by channel 2 down-counter terminate trigger C. Bit 10: OTEK Description 0 Forced termination of TO8K by down-counter terminate trigger is disabled 1 Forced termination of TO8K by down-counter terminate trigger is enabled (Initial value) * Bit 9--One-Shot Pulse Terminate Enable J (OTEJ): Enables or disables forced termination of output by channel 2 down-counter terminate trigger B. Bit 9: OTEJ Description 0 Forced termination of TO8J by down-counter terminate trigger is disabled 1 Forced termination of TO8J by down-counter terminate trigger is enabled (Initial value) * Bit 8--One-Shot Pulse Terminate Enable I (OTEI): Enables or disables forced termination of output by channel 2 down-counter terminate trigger A. Bit 8: OTEI Description 0 Forced termination of TO8I by down-counter terminate trigger is disabled 1 Forced termination of TO8I by down-counter terminate trigger is enabled (Initial value) Rev. 5.00 Feb. 24, 2010 Page 257 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * Bit 7--One-Shot Pulse Terminate Enable H (OTEH): Enables or disables forced termination of output by channel 1 down-counter terminate trigger H. Bit 7: OTEH Description 0 Forced termination of TO8H by down-counter terminate trigger is disabled 1 Forced termination of TO8H by down-counter terminate trigger is enabled (Initial value) * Bit 6--One-Shot Pulse Terminate Enable G (OTEG): Enables or disables forced termination of output by channel 1 down-counter terminate trigger G. Bit 6: OTEG Description 0 Forced termination of TO8G by down-counter terminate trigger is disabled 1 Forced termination of TO8G by down-counter terminate trigger is enabled (Initial value) * Bit 5--One-Shot Pulse Terminate Enable F (OTEF): Enables or disables forced termination of output by channel 1 down-counter terminate trigger F. Bit 5: OTEF Description 0 Forced termination of TO8F by down-counter terminate trigger is disabled 1 Forced termination of TO8F by down-counter terminate trigger is enabled (Initial value) * Bit 4--One-Shot Pulse Terminate Enable E (OTEE): Enables or disables forced termination of output by channel 1 down-counter terminate trigger E. Bit 4: OTEE Description 0 Forced termination of TO8E by down-counter terminate trigger is disabled 1 Forced termination of TO8E by down-counter terminate trigger is enabled (Initial value) * Bit 3--One-Shot Pulse Terminate Enable D (OTED): Enables or disables forced termination of output by channel 1 down-counter terminate trigger D. Bit 3: OTED Description 0 Forced termination of TO8D by down-counter terminate trigger is disabled 1 Forced termination of TO8D by down-counter terminate trigger is enabled (Initial value) * Bit 2--One-Shot Pulse Terminate Enable C (OTEC): Enables or disables forced termination of output by channel 1 down-counter terminate trigger C. Bit 2: OTEC Description 0 Forced termination of TO8C by down-counter terminate trigger is disabled 1 Forced termination of TO8C by down-counter terminate trigger is enabled Rev. 5.00 Feb. 24, 2010 Page 258 of 950 REJ09B0177-0500 (Initial value) 11. Advanced Timer Unit-II (ATU-II) * Bit 1--One-Shot Pulse Terminate Enable B (OTEB): Enables or disables forced termination of output by channel 1 down-counter terminate trigger B. Bit 1: OTEB Description 0 Forced termination of TO8B by down-counter terminate trigger is disabled 1 Forced termination of TO8B by down-counter terminate trigger is enabled (Initial value) * Bit 0--One-Shot Pulse Terminate Enable A (OTEA): Enables or disables forced termination of output by channel 1 down-counter terminate trigger A. Bit 0: OTEA Description 0 Forced termination of TO8A by down-counter terminate trigger is disabled 1 Forced termination of TO8A by down-counter terminate trigger is enabled (Initial value) 11.2.14 Reload Enable Register (RLDENR) The reload enable register (RLDENR) is an 8-bit register. The ATU-II has one RLDENR register in channel 8. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 RLDEN -- -- -- -- -- -- -- 0 0 0 0 0 0 0 0 R/W R R R R R R R RLDENR is an 8-bit readable/writable register that enables or disables loading of the reload register8 (RLDR8) value into the down-counters (DCNT8I to DCNT8P). Loading is performed on generation of a channel 2 compare-match signal oneshot pulse start trigger. Reloading is not performed if there is no linkage with channel 2 (one-shot pulse function), or while the down-counter (DCNT8I to DCNT8P) is running. RLDENR is initialized to H'00 by a power-on reset and in hardware standby mode and software standby mode. * Bit 7--Reload Enable (RLDEN): Enables or disables loading of the RLDR value into DCNT8I to DCNT8P. Bit 7: RLDEN Description 0 Loading of reload register value into down-counters is disabled 1 Loading of reload register value into down-counters is enabled (Initial value) * Bits 6 to 0--Reserved: These bits are always read as 0. The write value should always be 0. Rev. 5.00 Feb. 24, 2010 Page 259 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) 11.2.15 Free-Running Counters (TCNT) The free-running counters (TCNT) are 32- or 16-bit up- or up/down-counters. The ATU-II has 17 TCNT counters: one 32bit TCNT in channel 0, and sixteen 16-bit TCNTs in each of channels 1 to 7 and 11. For details of the channel 10 freerunning counters, see section 11.2.26, Channel 10 Registers. Channel Abbreviation Function 0 TCNT0H, TCNT0L 32-bit up-counter (initial value H'00000000) 1 TCNT1A, TCNT1B 16-bit up-counters (initial value H'0000) 2 TCNT2A, TCNT2B 3 TCNT3 4 TCNT4 5 TCNT5 6 TCNT6A-D 16-bit up/down-counters (initial value H'0001) 7 TCNT7A-D 16-bit up-counters (initial value H'0001) 11 TCNT11 16-bit up-counter (initial value H'0000) Free-Running Counter 0 (TCNT0H, TCNT0L): Free-running counter 0 (comprising TCNT0H and TCNT0L) is a 32-bit readable/writable register that counts on an input clock. The counter is started when the corresponding bit in the timer start register (TSTR1) is set to 1. The input clock is selected with prescaler register 1 (PSCR1). Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W: R/W: When TCNT0 overflows (from H'FFFFFFFF to H'00000000), the OVF0 overflow flag in the timer status register (TSR0) is set to 1. TCNT0 can only be accessed by a longword read or write. Word reads or writes should not be used. TCNT0 is initialized to H'00000000 by a power-on reset, and in hardware standby mode and software standby mode. Free-Running Counters 1A, 1B, 2A, 2B, 3, 4, 5, 11 (TCNT1A, TCNT1B, TCNT2A, TCNT2B, TCNT3, TCNT4, TCNT5, TCNT11): Free-running counters 1A, 1B, 2A, 2B, 3, 4, 5, and 11 (TCNT1A, TCNT1B, TCNT2A, TCNT2B, TCNT3, TCNT4, TCNT5, TCNT11) are 16-bit readable/writable registers that count on an input clock. Counting is started when the corresponding bit in the timer start register (TSTR1 or TSTR3) is set to 1. The input clock is selected with prescaler register 1 (PSCR1) and the timer control register (TCR). Rev. 5.00 Feb. 24, 2010 Page 260 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit name: Initial value: R/W: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The TCNT1A, TCNT1B, TCNT2A, and TCNT2B counters are cleared if incremented during counter clear trigger input from channel 10. TCNT3 to TCNT5 counter clearing is performed by a compare-match with the corresponding general register, according to the setting in TIOR. When one of counters TCNT1A/1B/2A/2B/3/4/5/11 overflows (from H'FFFF to H'0000), the overflow flag (OVF) for the corresponding channel in the timer status register (TSR) is set to 1. TCNT1A, TCNT1B, TCNT2A, TCNT2B, TCNT3, TCNT4, TCNT5, and TCNT11 can only be accessed by a word read or write. TCNT1A, TCNT1B, TCNT2A, TCNT2B, TCNT3, TCNT4, TCNT5, and TCNT11 are initialized to H'0000 by a poweron reset, and in hardware standby mode and software standby mode. TCNT1A, TCNT1B, TCNT2A, TCNT2B, TCNT3, TCNT4, and TCNT5 can count on external clock (TCLKA or TCLKB) input. TCNT1A, TCNT1B, TCNT2A, TCNT2B, TCNT3, TCNT4, and TCNT5 can count on an external interrupt clock (TI10) (AGCK) generated in channel 10 and on a channel 10 multiplied clock (AGCKM). Free-Running Counters 6A to 6D and 7A to 7D (TCNT6A to TCNT6D, TCNT7A to TCNT7D): Free-running counters 6A to 6D and 7A to 7D (TCNT6A to TCNT6D, TCNT7A to TCNT7D) are 16-bit readable/writable registers. Channel 6 and 7 counts are started by the timer start register (TSTR2). The clock input to channels 6 and 7 is selected with prescaler registers 2 and 3 (PSCR2, PSCR3) and timer control registers 6 and 7 (TCR6, TCR7). Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCNT6A to TCNT6D (in non-complementary PWM mode) and TCNT7A to TCNT7D are cleared by a compare-match with the cycle register (CYLR). TCNT6A to TCNT6D (in complementary PWM mode) count up and down between zero and the cycle register value. TCNT6A to TCNT6D and TCNT7A to TCNT7D are connected to the CPU by an internal 16-bit bus, and can only be accessed by a word read or write. TCNT6A to TCNT6D and TCNT7A to TCNT7D are initialized to H'0001 by a power-on reset, and in hardware standby mode and software standby mode. Rev. 5.00 Feb. 24, 2010 Page 261 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) 11.2.16 Down-Counters (DCNT) The DCNT registers are 16-bit down-counters. The ATU-II has 16 DCNT counters in channel 8. Channel Abbreviation Function 8 DCNT8A, DCNT8B, DCNT8C, DCNT8D, DCNT8E, DCNT8F, DCNT8G, DCNT8H, DCNT8I, DCNT8J, DCNT8K, DCNT8L, DCNT8M, DCNT8N, DCNT8O, DCNT8P 16-bit down-counters Down-Counters 8A to 8P (DCNT8A to DCNT8P): Down-counters 8A to 8P (DCNT8A to DCNT8P) are 16-bit readable/writable registers that count on an input clock. The input clock is selected with prescaler register 1 (PSCR1) and the timer control register (TCR). Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit name: Initial value: R/W: When the one-shot pulse function is used, DCNT8x starts counting down when the corresponding DSTR bit is set to 1 by the user program after the DCNT8x value has been set. When the DCNT8x value underflows, DSTR and DCNT8x are automatically cleared to 0, and the count is stopped. At the same time, the corresponding channel 8 timer status register 8 (TSR8) status flag is set to 1. When the offset one-shot pulse function is used, on compare-match with a channel 1 or 2 general register (GR) or output compare register (OCR) (the compare-match setting being made in the trigger mode register (TRGMDR) (for channel 1 only) ) when the corresponding timer connection register (TCNR) bit is 1, the corresponding down-count start register (DSTR) bit is automatically set to 1 and the down-count is started. When the DCNT8x value underflows, the corresponding DSTR bit and DCNT8x are automatically cleared to 0, the count is stopped, and the output is inverted, or, if a one-shot terminate register (OTR) setting has been made to forcibly terminate output by means of a trigger, DSTR is cleared to 0 by a channel 1 or 2 compare-match between GR and OCR, the count is forcibly terminated, and the output is inverted. The output is inverted for whichever is first. When the output is inverted, the corresponding channel 8 TSR8 status flag is set to 1. The DCNT8x counters can only be accessed by a word read or write. The DCNT8x counters are initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. For details, see sections 11.3.5, One-Shot Pulse Function, and 11.3.6, Offset One-Shot Pulse Function and Output Cutoff Function. Rev. 5.00 Feb. 24, 2010 Page 262 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) 11.2.17 Event Counters (ECNT) The event counters (ECNT) are 8-bit up-counters. The ATU-II has six ECNT counters in channel 9. Channel Abbreviation Function 9 ECNT9A, ECNT9B,ECNT9C, ECNT9D,ECNT9E, ECNT9F 8-bit event counters The ECNT counters are 8-bit readable/writable registers that count on detection of an input signal from input pins TI9A to TI9F. Rising edge, falling edge, or both rising and falling edges can be selected for edge detection. Bit: 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W: When a compare-match with GR9 corresponding to an ECNT9x counter occurs, the compare-match flag (CMF9) in the timer status register (TSR9) is set to 1. When a compare-match with GR occurs, the ECNT9x counter is cleared automatically. The ECNT9x counters can only be accessed by a byte read or write. The ECNT9x counters are initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. 11.2.18 Output Compare Registers (OCR) The output compare registers (OCR) are 16-bit registers. The ATU-II has nine OCR registers: one in channel 1 and eight in channel 2. For details of the channel 10 free-running counters, see section 11.2.26, Channel 10 Registers. Channel Abbreviation Function 1 OCR1 Output compare registers 2 OCR2A, OCR2B, OCR2C, OCR2D, OCR2E, OCR2F, OCR2G, OCR2H Output Compare Registers 1 and 2A to 2H (OCR1, OCR2A to OCR2H) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W: The OCR registers are 16-bit readable/writable registers that have an output compare register function. The OCR and free-running counter (TCNT1B, TCNT2B) values are constantly compared, and if the two values match, the CMF bit in the timer status register (TSR) is set to 1. If channels 1 and 2 and channel 8 are linked by the timer connection register (TCNR), the corresponding channel 8 down-counter (DCNT) is started at the same time. The OCR registers can only be accessed by a word read or write. The OCR registers are initialized to H'FFFF by a power-on reset, and in hardware standby mode and software standby mode. Rev. 5.00 Feb. 24, 2010 Page 263 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) 11.2.19 Input Capture Registers (ICR) The input capture registers (ICR) are 32-bit registers. The ATU-II has four 32-bit ICR registers in channel 0. For details of the channel 10 free-running counters, see section 11.2.26, Channel 10 Registers. Channel Abbreviation Function 0 ICR0AH, ICR0AL, ICR0BH, ICR0BL, ICR0CH, ICR0CL, ICR0DH, ICR0DL Dedicated input capture registers Input Capture Registers 0AH, 0AL to 0DH, 0DL (ICR0AH, ICR0AL to ICR0DH, ICR0DL) Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R The ICR registers are 32-bit read-only registers used exclusively for input capture. These dedicated input capture registers store the TCNT0 value on detection of an input capture signal from an external source. The corresponding TSR0 bit is set to 1 at this time. The input capture signal edge to be detected is specified by timer I/O control register TIOR0. By setting the TRG0DEN bit in TCR10, ICR0DH and ICR0DL can also be used for input capture in a compare match between TCNT10B and OCR10B. The ICR registers can only be accessed by a longword read. Word reads should not be used. The ICR registers are initialized to H'00000000 by a power-on reset, and in hardware standby mode and software standby mode. 11.2.20 General Registers (GR) The general registers (GR) are 16-bit registers. The ATU-II has 36 general registers: eight each in channels 1 and 2, four each in channels 3 to 5, six in channel 9, and two in channel 11. For details of the channel 10 free-running counters, see section 11.2.26, Channel 10 Registers. Channel Abbreviation Function 1 GR1A-GR1H Dual-purpose input capture and output compare registers 2 GR2A-GR2H 3 GR3A-GR3D 4 GR4A-GR4D 5 GR5A-GR5D 9 GR9A-GR9F Dedicated output compare registers 11 GR11A, GR11B Dual-purpose input capture and output compare registers Rev. 5.00 Feb. 24, 2010 Page 264 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) General Registers 1A to 1H and 2A to 2H (GR1A to GR1H, GR2A to GR2H) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W: These GR registers are 16-bit readable/writable registers with both input capture and output compare functions. Function switching is performed by means of the timer I/O control registers (TIOR). When a general register is used for input capture, it stores the TCNT1A or TCNT2A value on detection of an input capture signal from an external source. The corresponding IMF bit in TSR is set to 1 at this time. The input capture signal edge to be detected is specified by the corresponding TIOR. When a general register is used for output compare, the GR value and free-running counter (TCNT1A, TCNT2A) value are constantly compared, and when both values match, the IMF bit in the timer status register (TSR) is set to 1. If connection of channels 1 and 2 and channel 8 is specified in the timer connection register (TCNR), the corresponding channel 8 down-counter (DCNT) is started. Compare-match output is specified by the corresponding TIOR. The GR registers can only be accessed by a word read or write. The GR registers are initialized to H'FFFF by a power-on reset, and in hardware standby mode and software standby mode. General Registers 3A to 3D, 4A to 4D, 5A to 5D, 11A and 11B (GR3A to GR3D, GR4A to GR4D, GR5A to GR5D, GR11A and GR11B) Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W These GR registers are 16-bit readable/writable registers with both input capture and output compare functions. Function switching is performed by means of the timer I/O control registers (TIOR). When a general register is used for input capture, it stores the corresponding TCNT value on detection of an input capture signal from an external source. The corresponding IMF bit in TSR is set to 1 at this time. The input capture signal edge to be detected is specified by the corresponding TIOR. GR3A to GR3D can also be used for input capture with a channel 9 compare-match as the trigger. In this case, the corresponding IMF bit in TSR is not set. When a general register is used for output compare, the GR value and free-running counter (TCNT) value are constantly compared, and when both values match, the IMF bit in the timer status register (TSR) is set to 1. Compare-match output is specified by the corresponding TIOR. GRIIA and GR11B compare-match signals are transmitted to the advanced pulse controller (APC). For details, see section 12, Advanced Pulse Controller (APC). The GR registers can only be accessed by a word read or write. The GR registers are initialized to H'FFFF by a power-on reset, and in hardware standby mode and software standby mode. Rev. 5.00 Feb. 24, 2010 Page 265 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) General Registers 9A to 9F (GR9A to GR9F) Bit: 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W: These GR registers are 8-bit readable/writable registers with a compare-match function. The GR value and event counter (ECNT) value are constantly compared, and when both values match a compare-match signal is generated and the next edge is input, the corresponding CMF bit in TSR is set to 1. In addition, channel 3 (GR3A to GR3D) input capture can be generated by GR9A to GR9D compare-matches. This function is set by TRG3xEN in the timer control register (TCR). The GR registers can be accessed by a byte read or write. The GR registers are initialized to H'FF by a power-on reset, and in hardware standby mode and software standby mode. 11.2.21 Offset Base Registers (OSBR) The offset base registers (OSBR) are 16-bit registers. The ATU-II has two OSBR registers, one each in channels 1 and 2. Channel Abbreviation Function 1 OSBR1 2 OSBR2 Dedicated input capture registers with the same input trigger signal as that for channel 0 ICR0A Offset Base Registers 1 and 2 (OSBR1, OSBR2) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R OSBR1 and OSBR2 are 16-bit read-only registers used exclusively for input capture. OSBR0 and OSBR1 use the same input trigger signal (TI0A) as that for the channel 0 input capture register (ICR0A), and store the TCNT1A or TCNT2A value on detection of an edge. The OSBR registers can only be accessed by a word read. The OSBR registers are initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. For details, see sections 11.3.8, Twin-Capture Function. Rev. 5.00 Feb. 24, 2010 Page 266 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) 11.2.22 Cycle Registers (CYLR) The cycle registers (CYLR) are 16-bit registers. The ATU-II has eight cycle registers, four each in channels 6 and 7. Channel Abbreviation Function 6 CYLR6A- CYLR6D 16-bit PWM cycle registers 7 CYLR7A- CYLR7D Cycle Registers (CYLR6A to CYLR6D, CYLR7A to CYLR7D) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W: The CYLR registers are 16-bit readable/writable registers used for PWM cycle storage. The CYLR value is constantly compared with the corresponding free-running counter (TCNT6A to TCNT6D, TCNT7A to TCNT7D) value, and when the two values match, the corresponding timer start register (TSR) bit (CMF6A to CMF6D, CMF7A to CMF7D) is set to 1, and the free-running counter (TCNT6A to TCNT6D, TCNT7A to TCNT7D) is cleared. At the same time, the buffer register (BFR) value is transferred to the duty register (DTR). The corresponding output pins (TO6A to TO6D, TO7A to TO7D) go to 0 output when the BFR value is H'0000. In other cases, they go to 1 output. The CYLR registers can only be accessed by a word read or write. The CYLR registers are initialized to H'FFFF by a power-on reset, and in hardware standby mode and software standby mode. For details of the CYLR, BFR, and DTR registers, see section 11.3.9, PWM Timer Function. 11.2.23 Buffer Registers (BFR) The buffer registers (BFR) are 16-bit registers. The ATU-II has eight buffer registers, four each in channels 6 and 7. Channel Abbreviation Function 6 BFR6A-BFR6D 16-bit PWM buffer registers 7 BFR7A-BFR7D Buffer register (BFR) value is transferred to duty register (DTR) on compare-match of corresponding cycle register (CYLR) Buffer Registers (BFR6A to BFR6D, BFR7A to BFR7D) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W: The BFR registers are 16-bit readable/writable registers that store the value to be transferred to the duty register (DTR) in the event of a cycle register (CYLR) compare-match. The BFR registers can only be accessed by a word read or write. Rev. 5.00 Feb. 24, 2010 Page 267 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) The BFR registers are initialized to H'FFFF by a power-on reset, and in hardware standby mode and software standby mode. 11.2.24 Duty Registers (DTR) The duty registers (DTR) are 16-bit registers. The ATU-II has eight duty registers, four each in channels 6 and 7. Channel Abbreviation Function 6 DTR6A-DTR6D 16-bit PWM duty registers 7 DTR7A-DTR7D Duty Registers (DTR6A to DTR6D, DTR7A to DTR7D) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W: The DTR registers are 16-bit readable/writable registers used for PWM duty storage. The DTR value is constantly compared with the corresponding free-running counter (TCNT6A to TCNT6D, TCNT7A to TCNT7D) value, and when the two values match, the corresponding channel output pin (TO6A to TO6D, TO7A to TO7D) goes to 0 output. Also, when CYLR and the corresponding the free-running counter match, the corresponding BFR value is loaded. Set a value in the range 0 to CYLR for DTR; do not set a value greater than CYLR. The DTR registers can only be accessed by a word read or write. The DTR registers are initialized to H'FFFF by a power-on reset, and in hardware standby mode and software standby mode. 11.2.25 Reload Register (RLDR) The reload register is a 16-bit register. The ATU-II has one RLDR register in channel 8. Reload Register 8 (RLDR8) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W: RLDR8 is a 16-bit readable/writable register. When reload is enabled (by a setting in RLDENR) and DSTR8I to DSTR8P are set to 1 by the channel 2 compare-match signal one-shot pulse start trigger, the reload register value is transferred to DCNT8I to DCNT8P before the down-count is started. The reload register value is not transferred when the one-shot pulse function is used independently, without linkage to channel 2, or when down-counters DCNT8I to DCNT8P are running. RLDR8 can only be accessed by a word read or write. RLDR is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. Rev. 5.00 Feb. 24, 2010 Page 268 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) 11.2.26 Channel 10 Registers Counters (TCNT) Channel 10 has seven TCNT counters: one 32-bit TCNT, four 16-bit TCNTs, and two 8-bit TCNTs. The input clock is selected with prescaler register 4 (PSCR4). Count operations are performed by setting STR10 to 1 in timer start register 1 (TSTR1). Channel Abbreviation Function 10 TCNT10AH, AL 32-bit free-running counter (initial value H'00000001) TCNT10B 8-bit event counter (initial value H'00) TCNT10C 16-bit reload counter (initial value H'0001) TCNT10D 8-bit correction counter (initial value H'00) TCNT10E 16-bit correction counter (initial value H'0000) TCNT10F 16-bit correction counter (initial value H'0001) TCNT10G 16-bit free-running counter (initial value H'0000) Free-Running Counter 10AH, AL (TCNT10AH, TCNT10AL): Free-running counter 10AH, AL (comprising TCNT10AH and TCNT10AL) is a 32-bit readable/writable register that counts on an input clock and is cleared to initial value by input capture input (TI10) (AGCK). Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCNT10A can only be accessed by a longword read or write. Word reads or writes should not be used. TCNT10A is initialized to H'00000001 by a power-on reset, and in hardware standby mode and software standby mode. Event Counter 10B (TCNT10B): Event counter 10B (TCNT10B) is an 8-bit readable/writable register that counts on external clock input (TI10) (AGCK). For this operation, TI10 input must be set with bits CKEG1 and CKEG0 in TCR10. TI10 input will be counted even if halting of the count operation is specified by bit STR10 in TSTR1. Bit: 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W: TCNT10B can only be accessed by a byte read or write. TCNT10B is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. Rev. 5.00 Feb. 24, 2010 Page 269 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) Reload Counter 10C (TCNT10C): Reload counter 10C (TCNT10C) is a 16-bit readable/writable register. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W: When TCNT10C = H'0001 in the down-count operation, the value in the reload register (RLD10C) is transferred to TCNT10C, and a multiplied clock (AGCK1) is generated. TCNT10C is connected to the CPU via an internal 16-bit bus, and can only be accessed by a word read or write. TCNT10C is initialized to H'0001 by a power-on reset, and in hardware standby mode and software standby mode. Correction Counter 10D (TCNT10D): Correction counter 10D (TCNT10D) is an 8-bit readable/writable register that counts on external clock input (TI10) after transfer of the counter value to correction counter E (TCNT10E). Set TI10 input with bits CKEG1 and CKEG0 in TCR10. Transfer and counting will not be performed on TI10 input unless the count operation is enabled by bit STR10 in TSTR1. Bit: 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W: At the external clock input (TI10) (AGCK) timing, the value in this counter is shifted according to the multiplication factor set by bits PIM1 and PIM0 in timer I/O control register 10 (TIOR10) and transferred to correction counter E (TCNT10E). TCNT10D can only be accessed by a byte read or write. TCNT10D is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. Correction Counter 10E (TCNT10E): Correction counter 10E (TCNT10E) is a 16-bit readable/writable register that loads the TCNT10D shift value at the external input (TI10) timing, and counts on the multiplied clock (AGCK1) output by reload counter 10C (TCNT10C). However, if CCS in timer I/O control register 10 (TIOR10) is set to 1, when the TCNT10D shifted value is reached the count is halted. Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCNT10E can only be accessed by a word read or write. TCNT10E is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. Correction Counter 10F (TCNT10F): Correction counter 10F (TCNT10F) is a 16-bit readable/writable register that counts up on P clock cycles if the counter value is smaller than the correction counter 10E (TCNT10E) value when the STR10 bit in TSTR1 has been set for counter operation. The count is halted by a match with the correction counter clear register (TCCLR10). If TI10 is input when TCNT10D = H'00, TCNT10F is initialized and correction is carried out. When TCNT10F = TCCLR10, TCNT10F is cleared to H'0001. While TCNT10F TCCLR10, TCNT10F is incremented automatically until it reaches the TCCLR10 value, and is then cleared to H'0001. Rev. 5.00 Feb. 24, 2010 Page 270 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) A corrected clock (AGCKM) is output following correction each time this counter is incremented. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W: TCNT10F is can only be accessed by a word read or write. TCNT10F is initialized to H'0001 by a power-on reset, and in hardware standby mode and software standby mode. Free-Running Counter 10G (TCNT10G): Free-running counter 10G (TCNT10G) is a 16-bit readable/writable register that counts up on the multiplied clock (AGCK1). TCNT10G is initialized to H'0000 by input from external input (TI10) (AGCK). Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W: TCNT10G can only be accessed by a word read or write. TCNT10G is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. Registers There are six registers in channel 10: a 32-bit ICR, 32-bit OCR, 16-bit GR, 16-bit RLD, 16-bit TCCLR, and 8-bit OCR. Channel Abbreviation Function 10 ICR10AH, AL 32-bit input capture register (initial value H'00000000) OCR10AH, AL 32-bit output compare register (initial value H'FFFFFFFF) OCR10B 8-bit output compare register (initial value H'FF) RLD10C 16-bit reload register (initial value H'0000) GR10G 16-bit general register (initial value H'FFFF) TCCLR10 16-bit correction counter clear register (initial value H'0000) Rev. 5.00 Feb. 24, 2010 Page 271 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) Input Capture Register 10AH, AL (ICR10AH, ICR10AL): Input capture register 10AH, AL (comprising ICR10AH and ICR10AL) is a 32-bit read-only register to which the TCNT10AH, AL value is transferred on external input (TI10) (AGCK). At the same time, ICF10A in timer status register 10 (TSR10) is set to 1. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R R R R ICR10A is initialized to H'00000000 by a power-on reset, and in hardware standby mode and software standby mode. Output Compare Register 10AH, AL (OCR10AH, OCR10AL): Output compare register 10AH, AL (comprising OCR10AH and OCR10AL) is a 32-bit readable/writable register that is constantly compared with free-running counter 10AH, AL (TCNT10AH, TCNT10AL). When both values match, CMF10A in timer status register 10 (TSR10) is set to 1. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W: R/W: OCR10A is initialized to H'FFFFFFFF by a power-on reset, and in hardware standby mode and software standby mode. Output Compare Register 10B (OCR10B): Output compare register 10B (OCR10B) is an 8-bit readable/writable register that is constantly compared with free-running counter 10B (TCNT10B). When AGCK is input with both values matching, CMF10B in timer status register 10 (TSR10) is set to 1. Bit: 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W: OCR10B is initialized to H'FF by a power-on reset, and in hardware standby mode and software standby mode. Reload Register 10C (RLD10C): Reload register 10C (RLD10C) is a 16-bit readable/writable register. When STR10 in timer start register 1 (TSTR1) is 1 and RLDEN in the timer I/O control register (TIOR10) is 0, and the value of TCNT10A is captured into input capture register 10A (ICR10A), the ICR10A capture value is shifted according to the multiplication factor set by bits PIM1 and PIM0 in TIOR10 before being transferred to RLD10C. The contents of reload register 10C (RLD10C) are loaded when reload counter 10C (TCNT10C) reaches H'0001. Rev. 5.00 Feb. 24, 2010 Page 272 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RLD10C is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. General Register 10G (GR10G): General register 10G (GR10G) is a 16-bit readable/writable register with an output compare function. Function switching is performed by means of timer I/O control register 10 (TIOR10). The GR10G value and free-running counter 10G (TCNT10G) value are constantly compared, and when AGCK is input with both values matching, CMF10G in timer status register 10 (TSR10) is set to 1. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W: GR10G is initialized to H'FFFF by a power-on reset, and in hardware standby mode and software standby mode. Correction Counter Clear Register 10 (TCCLR10): Correction counter clear register 10 (TCCLR10) is a 16-bit readable/writable register. TCCLR10 is constantly compared with TCNT10F, and when the two values match, TCNT10F halts. TCNTxx can be cleared at this time by setting TRGxxEN (xx = 1A, 1B, 2A, 2B) in TCR10. Then, when TCNT10D is H'00 and TI10 is input, TCNT10F is cleared to H'0001. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W: TCCLR10 is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. Noise Canceler Registers There are two 8-bit noise canceler registers in channel 10: TCNT10H and NCR10. Channel Abbreviation Function 10 TCNT10H Noise canceler counter (Initial value H'00) NCR10 Noise canceler compare-match register (Initial value H'FF) Rev. 5.00 Feb. 24, 2010 Page 273 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) Noise Canceler Counter 10H (TCNT10H): Noise canceler counter 10H (TCNT10H) is an 8-bit readable/writable register. When the noise canceler function is enabled, TCNT10H starts counting up on P x 10, with the signal from external input (TI10) (AGCK) as a trigger. The counter operates even if STR10 is cleared to 0 in the timer start register (TSTR1). TI10 input is masked while the counter is running. When the count matches the noise canceler register (NCR10) value, the counter is cleared and TI10 input masking is released. Bit: 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W: TCNT10H is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. Noise Canceler Register 10 (NCR10): Noise canceler register 10 (NCR10) is an 8-bit readable/writable register used to set the upper count limit of noise canceler counter 10H (TCNT10H). TCNT10H is constantly compared with NCR10 during the count, and when a compare-match occurs the TCNT10H counter is halted and input signal masking is released. Bit: 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W: NCR10 is initialized to H'FF by a power-on reset, and in hardware standby mode and software standby mode. Channel 10 Control Registers There are four control registers in channel 10. Channel Abbreviation Function 10 TIOR10 Reload setting, counter correction setting, external input (TI10) edge interval multiplier setting GR compare-match setting TCR10 (Initial value H'00) TCCLR10 counter clear source Noise canceler function enabling/disabling selection External input (TI10) edge selection (Initial value H'00) TSR10 Input capture/compare-match status (Initial value H'0000) TIER10 Input capture/compare-match interrupt request enabling/disabling selection (Initial value H'0000) Timer I/O Control Register 10 (TIOR10): TIOR10 is an 8-bit readable/writable register that selects the value for multiplication of the external input (TI10) edge interval. It also makes a setting for using the general register (GR10G) for output compare, and makes the edge detection setting. TIOR10 is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 RLDEN CCS PIM1 PIM0 -- IO10G2 IO10G1 IO10G0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W -- R/W R/W R/W Rev. 5.00 Feb. 24, 2010 Page 274 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * Bit 7--Reload Enable (RLDEN): Enables or disables transfer of the input capture register 10A (ICR10A) value to reload register 10C (RLD10C). Bit 7: RLDEN Description 0 Transfer of ICR10A value to RLD10C on input capture is enabled 1 Transfer of ICR10A value to RLD10C on input capture is disabled (Initial value) * Bit 6--Counter Clock Select (CCS): Selects the operation of correction counter 10E (TCNT10E). Set the multiplication factor with bits PIM1 and PIM0. Bit 6: CCS Description 0 TCNT10E count is not halted when TCNT10D x multiplication factor = TCNT10E* (Initial value) 1 TCNT10E count is halted when TCNT10D x multiplication factor = TCNT10E* Note: * When [TCNT10D x multiplication factor] matches the value of TCNT10E with bits 8 to 0 masked * Bits 5 and 4--Pulse Interval Multiplier (PIM1, PIM0): These bits select the external input (TI10) cycle multiplier. Bit 5: PIM1 Bit 4: PIM0 Description 0 0 Counting on external input cycle x 32 1 Counting on external input cycle x 64 1 0 Counting on external input cycle x 128 1 Counting on external input cycle x 256 (Initial value) * Bit 3--Reserved: This bit is always read as 0. The write value should always be 0. * Bits 2 to 0--I/O Control 10G2 to 10G0 (IO10G2 to IO10G0): These bits select the function of general register 10G (GR10G). Bit 2: IO10G2 Bit 1: IO10G1 Bit 0: IO10G0 Description 0 0 0 GR is an output compare register 1 Legend: Compare-match disabled (Initial value) 1 GR10G = TCNT10G compare-match 1 * Cannot be used * * Cannot be used *: Don't care Timer Control Register 10 (TCR10): TCR10 is an 8-bit readable/writable register that selects the correction counter clear register (TCCLR10) compare-match counter clear source, enables or disables the noise canceler function, and selects the external input (TI10) edge. TCR10 is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 TRG2BEN TRG1BEN TRG2AEN TRG1AEN TRG0DEN NCE CKEG1 CKEG0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Rev. 5.00 Feb. 24, 2010 Page 275 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * Bit 7--Trigger 2B Enable (TRG2BEN): Enables or disables counter clearing for channel 2 TCNT2B. When clearing is enabled, set the correction angle clock (AGCKM) as the TCNT2B count clock. If TCNT2B counts while clearing is enabled, TCNT2B will be cleared. Bit 7: TRG2BEN Description 0 Channel 2 counter B (TCNT2B) clearing when correction counter clear register (TCCLR10) = correction counter (TCNT10F) is disabled (Initial value) 1 Channel 2 counter B (TCNT2B) clearing when correction counter clear register (TCCLR10) = correction counter (TCNT10F) is enabled * Bit 6--Trigger 1B Enable (TRG1BEN): Enables or disables counter clearing for channel 1 TCNT1B. When clearing is enabled, set the correction angle clock (AGCKM) as the TCNT1B count clock. If TCNT1B counts while clearing is enabled, TCNT1B will be cleared. Bit 6: TRG1BEN Description 0 Channel 1 counter B (TCNT1B) clearing when correction counter clear register (TCCLR10) = correction counter (TCNT10F) is disabled (Initial value) 1 Channel 1 counter B (TCNT1B) clearing when correction counter clear register (TCCLR10) = correction counter (TCNT10F) is enabled * Bit 5--Trigger 2A Enable (TRG2AEN): Enables or disables counter clearing for channel 2 TCNT2A. When clearing is enabled, set the correction angle clock (AGCKM) as the TCNT2A count clock. If TCNT2A counts while clearing is enabled, TCNT2A will be cleared. Bit 5: TRG2AEN Description 0 Channel 2 counter 2A (TCNT2A) clearing when correction counter clear register (TCCLR10) = correction counter (TCNT10F) is disabled (Initial value) 1 Channel 2 counter 2A (TCNT2A) clearing when correction counter clear register (TCCLR10) = correction counter (TCNT10F) is enabled * Bit 4--Trigger 1A Enable (TRG1AEN): Enables or disables counter clearing for channel 1 TCNT1A. When clearing is enabled, set the correction angle clock (AGCKM) as the TCNT1A count clock. If TCNT1A counts while clearing is enabled, TCNT1A will be cleared. Bit 4: TRG1AEN Description 0 Channel 1 counter 1A (TCNT1A) clearing when correction counter clear register (TCCLR10) = correction counter (TCNT10F) is disabled (Initial value) 1 Channel 1 counter 1A (TCNT1A) clearing when correction counter clear register (TCCLR10) = correction counter (TCNT10F) is enabled * Bit 3--Trigger 0D Enable (TRG0DEN): Enables or disables channel 0 ICR0D input capture signal requests. Bit 3: TRG0DEN Description 0 Capture requests for channel 0 input capture register (ICR0D) on event counter (TCNT10B) compare-match are disabled (Initial value) 1 Capture requests for channel 0 input capture register (ICR0D) on event counter (TCNT10B) compare-match are enabled Rev. 5.00 Feb. 24, 2010 Page 276 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * Bit 2--Noise Canceler Enable (NCE): Enables or disables the noise canceler function. Bit 2: NCE Description 0 Noise canceler function is disabled 1 Noise canceler function is enabled (Initial value) * Bits 1 and 0--Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the channel 10 external input (TI10) edge(s). The clock (AGCK) is generated by the detected edge(s). Bit 1: CKEG1 Bit 0: CKEG0 Description 0 0 TI10 input disabled 1 TI10 input rising edges detected 0 TI10 input falling edges detected 1 TI10 input rising and falling edges both detected 1 (Initial value) Timer Status Register 10 (TSR10): TSR10 is a 16-bit readable/writable register that indicates the occurrence of channel 10 input capture or compare-match. Each flag is an interrupt source, and issues an interrupt request to the CPU if the interrupt is enabled by the corresponding bit in timer interrupt enable register 10 (TIER10). TSR10 is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. Bit: 15 14 13 12 11 10 9 8 -- -- -- -- -- -- -- -- 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 -- -- -- -- CMF10G CMF10B ICF10A CMF10A Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R/(W)* R/(W)* R/(W)* R/(W)* Initial value: Note: * Only 0 can be written to clear the flag. * Bits 15 to 4--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 3--Compare-Match Flag 10G (CMF10G): Status flag that indicates GR10G compare-match. Bit 3: CMF10G Description 0 [Clearing condition] When CMF10G is read while set to 1, then 0 is written to IMF10G 1 [Setting condition] When TCNT10G = GR10G (Initial value) Rev. 5.00 Feb. 24, 2010 Page 277 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) * Bit 2--Compare-Match Flag 10B (CMF10B): Status flag that indicates OCR10B compare-match. Bit 2: CMF10B Description 0 [Clearing condition] When CMF10B is read while set to 1, then 0 is written to CMF10B 1 [Setting condition] When TCNT10B is incremented while TCNT10B = OCR10B (Initial value) * Bit 1--Input Capture Flag 10A (ICF10A): Status flag that indicates ICR10A input capture. Bit 1: ICF10A Description 0 [Clearing condition] When ICR10A is read while set to 1, then 0 is written to ICR10A 1 [Setting condition] When the TCNT10A value is transferred to ICR10A by an input capture signal (Initial value) * Bit 0--Compare-Match Flag 10A (CMF10A): Status flag that indicates OCR10A compare-match. Bit 0: CMF10A Description 0 [Clearing condition] When CMF10A is read while set to 1, then 0 is written to CMF10A 1 [Setting condition] When TCNT10A = OCR10A (Initial value) Timer Interrupt Enable Register 10 (TIER10): TIER10 is a 16-bit readable/writable register that controls enabling/disabling of channel 10 input capture and compare-match interrupt requests. TIER10 is initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. Bit: 15 14 13 12 11 10 9 8 -- -- -- -- -- -- -- -- Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 -- -- -- IREG CME10G CME10B ICE10A CME10A Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R/W R/W R/W R/W R/W * Bits 15 to 5--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 4--Interrupt Enable Edge G (IREG): Specifies TSR10 CMF10G interrupt request timing. Bit 4: IREG Description 0 Interrupt is requested when CMF10G becomes 1 1 Interrupt is requested by next external input (TI10) (AGCK) after CMF10G becomes 1 Rev. 5.00 Feb. 24, 2010 Page 278 of 950 REJ09B0177-0500 (Initial value) 11. Advanced Timer Unit-II (ATU-II) * Bit 3--Compare-Match Interrupt Enable 10G (CME10G): Enables or disables interrupt requests by CMF10G in TSR10 when CMF10G is set to 1. Bit 3: CME10G Description 0 CMI10G interrupt requested by CMF10G is disabled 1 CMI10G interrupt requested by CMF10G is enabled (Initial value) * Bit 2--Compare-Match Interrupt Enable 10B (CME10B): Enables or disables interrupt requests by CMF10B in TSR10 when CMF10B is set to 1. Bit 2: CME10B Description 0 CMI10B interrupt requested by CMF10B is disabled 1 CMI10B interrupt requested by CMF10B is enabled (Initial value) * Bit 1--Input Capture Interrupt Enable 10A (ICE10A): Enables or disables interrupt requests by ICF10A in TSR10 when ICF10A is set to 1. Bit 1: ICE10A Description 0 ICI10A interrupt requested by ICF10A is disabled 1 ICI10A interrupt requested by ICF10A is enabled (Initial value) * Bit 0--Compare-Match Interrupt Enable 10A (CME10A): Enables or disables interrupt requests by CMF10A in TSR10 when CMF10A is set to 1. Bit 0: CME10A Description 0 CMI10A interrupt requested by CMF10A is disabled 1 CMI10A interrupt requested by CMF10A is enabled (Initial value) Rev. 5.00 Feb. 24, 2010 Page 279 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) 11.3 Operation 11.3.1 Overview The ATU-II has twelve timers of eight kinds in channels 0 to 11. It also has a built-in prescaler that generates input clocks, and it is possible to generate or select internal clocks of the required frequency independently of circuitry outside the ATU-II. The operation of each channel and the prescaler is outlined below. Channel 0: Channel 0 has a 32-bit free-running counter (TCNT0) and four 32-bit input capture registers (ICR0A to ICR0D). TCNT0 is an up-counter that performs free-running operation. An interrupt request can be generated on counter overflow. The four input capture registers (ICR0A to ICR0D) capture the free-running counter (TCNT0) value by means of input from the corresponding external signal input pin (TI0A to TI0D). For capture by means of input from an external signal input pin, rising edge, falling edge, or both edges can be selected in the timer I/O control register (TIOR0). In the case of input capture register 0D (ICR0D) only, capture can be performed by means of a compare-match between freerunning counter 10B (TCNT10B) and compare-match register 10B (OCR10B), by making a setting in timer control register 10 (TCR10). In this case, capture is performed even if an input capture disable setting has been made for TIOR0. In each case, the DMAC can be activated or an interrupt requested when capture occurs. Channel 0 also has three interval interrupt request registers (ITVRR1, ITVRR2A, and ITVRR2B). A/D converter (AD0 to AD2) activation can be selected by setting 1 in ITVA6 to ITVA13 in ITVRR, and an interrupt request to the CPU by setting 1 in ITVE6 to ITVE13. These operations are performed when the corresponding bit of bits 6 to 13 in TCNT0 changes to 1, enabling use as an interval timer function. Channel 1: Channel 1 has two 16-bit free-running counters (TCNT1A and TCNT1B), eight 16-bit general registers (GR1A to GR1H), and a 16-bit output compare register (OCR1). TCNT1A and TCNT1B are up-counters that perform free-running operation. When the clock generated in channel 10 (described below) is selected, these counters can be cleared at the count specified in channel 10. Each counter can generate an interrupt request when it overflows. The eight general registers (GR1A to GR1H) can be used as input capture or output compare registers using the corresponding external signal I/O pin (TIO1A to TIO1H). When used for input capture, the free-running counter (TCNT1A) value is captured by means of input from the corresponding external signal I/O pin (TIO1A to TIO1H). Rising edge, falling edge, or both edges can be selected for the input capture signal in the timer I/O control registers (TIOR1A to TIOR1D). When used for output compare, compare-match with the free-running counter (TCNT1A) is performed. For the output from the external signal I/O pins by compare-match, 0 output, 1 output, or toggle output can be selected in the timer I/O control registers (TIOR1A to TIOR1D). When used as output compare registers, a compare-match can be used as a one-shot pulse start/terminate trigger by setting the channel 8 timer connection register (TCNR) and one-shot pulse terminate register (OTR), and using these in combination with the down-counters (DCNT8A to DCNT8H). Start/terminate trigger selection is performed by means of the trigger mode register (TRGMDR). In the case of the output compare register (OCR1), a TCNT1B compare-match can be used as a one-shot pulse start trigger, in the same way as the general registers, in combination with channel 8 down-counters DCNT8A to DCNT8H. An interrupt can be requested on the occurrence of the respective input capture or compare-match. In addition, channel 1 has a 16-bit dedicated input capture register (OSBR1). The channel 0 TI0A input pin can also be used as the OSBR1 trigger input, enabling use of a twin-capture function. Channel 2: Channel 2 has two 16-bit free-running counters (TCNT2A and TCNT2B), eight 16-bit general registers (GR2A to GR2H), and eight 16-bit output compare registers (OCR2A to OCR2H). Rev. 5.00 Feb. 24, 2010 Page 280 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) TCNT2A and TCNT2B are up-counters that perform free-running operation. When the clock generated in channel 10 (described below) is selected, these counters can be cleared at the count specified in channel 10. Each counter can generate an interrupt request when it overflows. The eight general registers (GR2A to GR2H) can be used as input capture or output compare registers using the corresponding external signal I/O pin (TIO2A to TIO2H). When used for input capture, the free-running counter (TCNT2A) value is captured by means of input from the corresponding external signal I/O pin (TIO2A to TIO2H). Rising edge, falling edge, or both edges can be selected for the input capture signal in the timer I/O control registers (TIOR2A to TIOR2D). When used for output compare, compare-match with the free-running counter (TCNT2A) is performed. For the output from the external signal I/O pins by compare-match, 0 output, 1 output, or toggle output can be selected in the timer I/O control registers (TIOR2A to TIOR2D). When used as output compare registers, a compare-match can be used as a one-shot pulse terminate trigger by setting the channel 8 one-shot pulse terminate register (OTR), and using this in combination with the down-counters (DCNT8I to DCNT8P). In the case of the output compare registers (OCR2A to OCR2H), a TCNT2B compare-match can be used as a one-shot pulse start trigger by setting the channel 8 timer connection register (TCNR), and using this in combination with the downcounters (DCNT8I to DCNT8P). An interrupt can be requested on the occurrence of the respective input capture or compare-match. In addition, channel 2 has a 16-bit dedicated input capture register (OSBR2). The channel 0 TI0A input pin can also be used as the OSBR2 trigger input, enabling use of a twin-capture function. Channels 3 to 5: Channels 3 to 5 each have a 16-bit free-running counter (TCNT3 to TCNT5) and four 16-bit general registers (GR3A to GR3D, GR4A to GR4D, GR5A to GR5D). TCNT3 to TCNT5 are up-counters that perform freerunning operation. Channels 3 to 5 each have a 16-bit free-running counter (TCNT3 to TCNT5) and four 16-bit general registers (GR3A to GR3D, GR4A to GR4D, GR5A to GR5D). TCNT3 to TCNT5 are up-counters that perform freerunning operation. In addition, counter clearing can be performed by compare-match by making a setting in the timer I/O control register (TIOR3A, TIOR3B, TIOR4A, TIOR4B, TIOR5A, TIOR5B). Each counter can generate an interrupt request when it overflows. The four general registers (GR3A to GR3D, GR4A to GR4D, GR5A to GR5D) each have corresponding external signal I/O pins (TIO3A to TIO3D, TIO4A to TIO4D, TIO5A to TIO5D), and can be used as input capture or output compare registers. When used for input capture, the free-running counter (TCNT3 to TCNT5) value is captured by means of input from the corresponding external signal I/O pin (TIO3A to TIO3D, TIO4A to TIO4D, TIO5A to TIO5D). Rising edge, falling edge, or both edges can be selected for the input capture signal in the timer I/O control registers (TIOR3A, TIOR3B, TIOR4A, TIOR4B, TIOR5A, TIOR5B). Also, in use for input capture, input capture can be performed using a compare-match between a channel 9 event counter (ECNT9A to ECNT9D), described later, and a general register (GR9A to GR9D) as the trigger (channel 3 only). In this case, capture is performed even if an input capture disable setting has been made for TIOR3A to TIOR3D. When used for output compare, compare-match with the free-running counter (TCNT3 to TCNT5) is performed. For the output from the external signal I/O pins by compare-match, 0 output, 1 output, or toggle output can be selected in the timer I/O control registers (TIOR3A, TIOR3B, TIOR4A, TIOR4B, TIOR5A, TIOR5B). An interrupt can be requested on the occurrence of the respective input capture or compare-match. However, in the case of input capture using channel 9 as a trigger, an interrupt request from channel 3 cannot be used. By selecting PWM mode in the timer mode register (TMDR), PWM output can be obtained, with three outputs for each. In this case, GR3D, GR4D, and GR5D are automatically used as cycle registers, and GR3A to GR3C, GR4A to GR4C, GR5A to GR5C, as duty registers. TCNT3 to TCNT5 are cleared by the corresponding GR3D, GR4D, or GR5D comparematch. Channels 6 and 7: Channels 6 and 7 each have 16-bit free-running counters (TCNT6A to TCNT6D, TCNT7A to TCNT7D), 16-bit cycle registers (CYLR6A to CYLR6D, CYLR7A to CYLR7D), 16-bit duty registers (DTR6A to DTR6D, DTR7A to DTR7D), and buffer registers (BFR6A to BFR6D, BFR7A to BFR7D). Channels 6 and 7 also each have external output pins (TO6A to TO6D, TO7A to TO7D), and can be used as buffered PWM timers. The TCNT registers are up-counters, and 0 is output to the corresponding external output pin when the TCNT value matches the DTR Rev. 5.00 Feb. 24, 2010 Page 281 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) value (when DTR CYLR). When the TCNT value matches the CYLR value (when DTR H'0000), 1 is output to the external output pin, TCNT is initialized to H'0001, and the BFR value is transferred to DTR. Thus, the configuration of channels 6 and 7 enables them to perform waveform output with the CYLR value as the cycle and the DTR value as the duty, and to use BFR to absorb the time lag between setting of data in DTR and compare-match occurrence. When DTR = CYLR, 1 is output continuously to the external output pin, giving a duty of 100%. When DTR = H'0000, 0 is output continuously to the external output pin, giving a duty of 0%. Do not set a value in DTR that will result in the condition DTR > CYLR. To set H'0000 to DTR, not write H'0000 directly to DTR but set H'0000 to BFR and then transfer the value to DTR. Writing H'0000 directly to DTR may not give a duty of 0%. In channel 6, TCNT can also be designated for complementary PWM output by means of the PWM mode register (PMDR). When the corresponding TSTR is set to 1, TCNT starts counting up, then switches to a down-count when the count matches the CYLR value. When TCNT reaches H'0000, it starts counting up again. When TCNT = DTR, the corresponding TO6A to TO6D output changes. Whether TCNT is counting up or down can be ascertained from the timer status register (TSR6). DMAC activation and interrupt request generation, respectively, are possible when TCNT = CYLR in asynchronous PWM mode, and when TCNT = H'0000 in complementary PWM mode. Channel 8: Channel 8 has sixteen 16-bit down-counters (DCNT8A to DCNT8P). The down-counters have corresponding external signal output pins, and can generate one-shot pulses. Setting a value in DCNT and setting the corresponding bit to 1 in the down-count start register (DSTR) starts DCNT operation and simultaneously outputs 1 to the external output pin. When DCNT counts down to H'0000, it stops and outputs 0 to the external output pin. An interrupt can be requested when DCNT underflows. Down-counter operation can be coupled with the channel 1 or channel 2 output compare function by means of settings in the timer connection register (TCNR) and one-shot pulse terminate register (OTR), respectively, so that DCNT8I to DCNT8H count operations are started and stopped from channel 1, and DCNT8I to DCNT8P count operations from channel 2. DCNT8I to DCNT8P have a reload register (RLDR), and a setting in the reload enable register (RLDEN) enables count operations to be started after reading the value from this register. Channel 9: Channel 9 has six 8-bit event counters (ECNT9A to ECNT9F) and six 8-bit general registers (GR9A to GR9F). The event counters are up-counters, each with a corresponding external input pin (ECNT9A to ECNT9F). The event counter value is incremented by input from the corresponding external input pin. Incrementing on the rising edge, falling edge, or both edges can be selected by means of settings in the timer control registers (TCR9A to TCR9C). An event counter is cleared by edge input after a match with the corresponding general register. An interrupt can requested when an event counter is cleared. Timer control register (TCR9A, TCR9B) settings can be made to enable event counters ECNT9A to ECNT9D to send a compare-match signal to channel 3 when the count matches the corresponding general register (GR9A to GR9D), allowing input capture to be performed on channel 3. This enables the pulse input interval to be measured. Channel 10: Channel 10 generates a multiplied clock based on external input, and supplies this to channels 1 to 5. Channel 10 is divided into three blocks: (1) an inter-edge measurement block, (2) a multiplied clock generation block, and (3) a multiplied clock correction block. (1) Inter-edge measurement block This block has a 32-bit free-running counter (TCNT10A), 32-bit input capture register (ICR10A), 32-bit output compare register (OCR10A), 8-bit event counter (TCNT10B), 8-bit output compare register (OCR10B), 8-bit noise canceler counter (TCNT10H), and 8-bit noise canceler compare-match register (NCR10). Rev. 5.00 Feb. 24, 2010 Page 282 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) The 32-bit free-running counter (TCNT10A) is an up-counter that performs free-running operations. When input capture is performed by means of TI10 input, this counter is cleared to H'00000001. When free-running counter (TCNT10A) reaches the value set in the output compare register (OCR10A), a compare-match interrupt can be requested. The input capture register (ICR10A) has an external signal input pin (TI10), and the free-running counter (TCNT10A) value can be captured by means of input from TI10. Rising edge, falling edge, or both edges can be selected by making a setting in bits CKEG1 and CKEG0 in the timer control register (TCR10). The TI10 input has a noise canceler function, which can be enabled by setting the NCE bit in the timer control register (TCR10). When the counter value is captured, TCNT10A is cleared to 0 and an interrupt can be requested. The captured value can be transferred to the multiplied clock generation block reload register (RLD10C). The 8-bit event counter (TCNT10B) is an up-counter that is incremented by TI10 input. When the event counter (TCNT10B) value reaches the value set in the output compare register (OCR10B), a compare-match interrupt can be requested. By setting the TRG0DEN bit in the timer control register (TCR10), a capture request can also be issued for the channel 0 input capture register 0D (ICR0D) when compare-match occurs. The 8-bit noise canceler counter (TCNT10H) and 8-bit noise canceler compare-match register (NCR10) are used to set the period for which the noise canceler functions. By setting a value in the noise canceler compare-match register (TCNT10H) and setting the NCE bit in the timer control register (TCR10), TI10 input is masked when it occurs. At the same time as TI10 input is masked, the noise canceler counter (TCNT10H) starts counting up on the Px10 clock. When the noise canceler counter (TCNT10H) value matches the noise canceler compare-match register (NCR10) value, the noise canceler counter (TCNT10H) is cleared to H'0000 and TI10 input masking is cleared. (2) Multiplied clock generation block This block has 16-bit reload counters (TCNT10C, RLD10C), a 16-bit register free-running counter (TCNT10G), and a 16-bit general register (GR10G). 16-bit reload counter 10C (RLD10C) is captured by 32-bit input capture register 10A (ICR10A), and when RLDEN in the timer I/O control register (TIOR10) is 0, the value captured in input capture register 10A is transferred to the multiplied clock generation block reload register (RLD10C). The value transferred can be selected from 1/32, 1/64, 1/128, or 1/256 the original value, according to the setting of bits PIM1 and PIM0 in TIOR10. 16-bit reload counter 10C (TCNT10C) performs down-count operations. When TCNT10C reaches H'0001, the value is read automatically from the reload buffer (RLD10C), internal clock AGCK1 is generated, and the down-count operation is repeated. Internally generated AGCK1 is input as a clock to the multiplied clock correction block 16-bit correction counter (TCNT10E) and 16-bit free-running counter 10G (TCNT10G). 16-bit register free-running counter 10G (TCNT10G) counts on AGCK1 generated by TCNT10C. It is initialized to H'0000 by external input from TI10. The 16-bit general register (GR10G) can be used in a compare-match with free-running counter 10G (TCNT10G) by setting bits IO10G2 to IO10G0 in the timer I/O control register (TIOR10). An interrupt can be requested when a compare-match occurs. Also, by setting timer interrupt enable register 10 (TIER10), an interrupt can be request in the event of TI10 input after a compare-match. (3) Multiplied clock correction block This block has three 16-bit correction counters (TCNT10D, TCNT10E, TCNT10F) and a 16-bit correction counter clear register (TCCLR10). When 32-bit input capture register 10A (ICR10A) performs a capture operation due to input from external input pin TI10, the value in correction counter 10D (TCNT10D) is transferred to TCNT10E and TCNT10D is incremented. The value transferred to TCNT10E is 32, 64, 128, or 256 times the TCNT10D value, according to the setting of bits PIM1 and PIM0 in the timer I/O control register (TIOR10). 16-bit correction counter 10E (TCNT10E) counts up on AGCK1 generated by reload counter 10C (TCNT10C, RLD10C) in the multiplied clock generation block. However, by setting the CCS bit in the timer I/O control register (TIOR10), it is possible to stop free-running counter 10E (TCNT10E) when the free-running counter 10D (TCNT10D) multiplication value specified by PIM1 and PIM0 and the free-running counter 10E (TCNT10E) value match. The multiplied TCNT10D value is transferred when input capture register 10A (ICR10A) performs a capture operation due to TI10 input. Rev. 5.00 Feb. 24, 2010 Page 283 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) 16-bit correction counter 10F (TCNT10F) has P as its input and is constantly compared with 16-bit correction counter 10E (TCNT10E). When the 16-bit correction counter 10F (TCNT10F) value is smaller than that in 16-bit correction counter 10E (TCNT10E), it is incremented and generates count-up AGCKM. When the 16-bit correction counter 10F (TCNT10F) value exceeds that in 16-bit correction counter 10E (TCNT10E), no count-up operation is performed. The TI10 multiplied signal (AGCKM) generated when TCNT10F is incremented is output to the channel 1 to 5 freerunning counters (TCNT1A, TCNT1B, TCNT2A, TCNT2B, TCNT3, TCNT4, TCNT5), and an up-count can be performed on AGCKM by setting this as the counter clock on each channel. TCNT10F is constantly compared with the 16-bit correction counter clear register (TCCLR10), and when the free-running counter 10F (TCNT10F) and correction counter clear register (TCCLR10) values match, the TCNT10F up-count stops. Setting TRG1AEN, TRG1BEN, TRG2AEN, and TRG2BEN in the timer control register (TCR10) enables the channel 1 and 2 free-running counters (TCNT1A, TCNT1B, TCNT2A, TCNT2B) to be cleared at this time. If TI10 is input when TCNT10D = H'0000, initialization and correction operations are performed. When TCNT10F = TCCLR10, TCNT10F is cleared to H'0001. When TCNT10F TCCLR10, TCNT10F automatically counts up to the TCCLR10 value, and is cleared to H'0001. Channel 11: Channel 11 has a 16-bit free-running counter (TCNT11) and two 16-bit general registers (GR11A and GR11B). TCNT11 is an up-counter that performs free-running operation. The counter can generate an interrupt request when it overflows. The two general registers (GR11A and GR11B) each have a corresponding external signal I/O pin (TIO11A, TIO11B), and can be used as input capture or output compare registers. When used for input capture, the free-running counter (TCNT11) value is captured by means of input from the corresponding external signal I/O pin (TIO11A, TIO11B). Rising edge, falling edge, or both edges can be selected for the input capture signal in the timer I/O control register (TIOR11). When used for output compare, compare-match with the free-running counter (TCNT11) is performed. For the output from the external signal I/O pins by compare-match, 0 output, 1 output, or toggle output can be selected in the timer I/O control register (TIOR11). An interrupt can be requested on the occurrence of the respective input capture or compare-match. When the two general registers (GR11A and GR11B) are designated for compare-match use, a compare-match signal can be output to the APC. Prescaler: The ATU-II has a dedicated prescaler with a 2-stage configuration. The first stage comprises 5-bit prescalers (PSCR1 to PSCR4) that generate a 1/m clock (where m = 1 to 32) with respect to clock P. The second prescaler stage allows selection of a clock obtained by further scaling the clock from the first stage by 2n (where n = 0 to 5) according to the timer control registers for the respective channels (TCR1A, TCR1B, TCR2A, TCR2B, TCR3 to TCR5, TCR6A, TCR6B, TCR7A, TCR7B, TCR8, TCR11). The prescalers of channels 1 to 8 and 11 have a 2-stage configuration, while the channel 0 and 10 prescalers only have a first stage. The first-stage prescaler is common to channels 0 to 5, 8, and 11, and it is not possible to set different firststage division ratios for each. Channels 6, 7, and 10 each have a first-stage prescaler, and different first-stage division ratios can be set for each. 11.3.2 Free-Running Counter Operation and Cyclic Counter Operation The free-running counters (TCNT) in ATU-II channels 0 to 5 and 11 start counting up as free-running counters when the corresponding timer start register (TSTR) bit is set to 1. When TCNT overflows (channel 0: from H'FFFFFFFF to H'00000000; channels 1 to 5 and 11: from H'FFFF to H'0000), the OVF bit in the timer status register (TSR) is set to 1. If the OVE bit in the corresponding timer interrupt enable register (TIER) is set to 1 at this time, an interrupt request is sent to the CPU. After overflowing, TCNT starts counting up again from H'00000000 or H'0000. If the TSTR value is cleared to 0 during TCNT operation, the corresponding TCNT halts. In this case, TCNT is not reset. If external output is being performed from the GR for the corresponding TCNT, the output value does not change. Channel 0 free-running counter operation is shown in figure 11.13. Rev. 5.00 Feb. 24, 2010 Page 284 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) P TSTR1 STR0 TCNT0 Clock 00000001 TCNT0 00000002 00000003 00000004 00000005 00000006 FFFFFFFD FFFFFFFE FFFFFFFF 00000000 00000001 00000002 Cleared by software TSR0 OVF0 Figure 11.13 Free-Running Counter Operation and Overflow Timing The free-running counters (TCNT) in ATU-II channels 6 and 7 perform cyclic count operations unconditionally. With channel 3 to 5 free-running counters (TCNT), when the corresponding T3PWM to T5PWM bit in the timer mode register (TMDR) is set to 1, or the corresponding CCI bit in the timer I/O control register (TIOR) is set to 1 when bits T3PWM to T5PWM are 0, the counter for the relevant channel performs a cyclic count. The relevant TCNT counter is cleared by a compare-match of TCNT with GR3D, GR4D, or GR5D in channel 3 to 5, or CYLR in channels 6 and 7 (counter clear function). TCNT starts counting up as a cyclic counter when the corresponding STR bit in TSTR is set to 1 after the TMDR setting is made. When the count value matches the GR3D, GR4D, GR5D, or CYLR value, the corresponding IMF3D, IMF4D, or IMF5D bit in the timer status register (TSR) (or the CMF bit in TSR6 or TSR7 for channels 6 and 7) is set to 1, and TCNT is cleared to H'0000 (H'0001 in channels 6 and 7). If the corresponding TIER bit is set to 1 at this time, an interrupt request is sent to the CPU. After the compare-match, TCNT starts counting up again from H'0000 (H'0001 in channels 6 and 7). Figure 11.14 shows the operation when channel 3 is used as a cyclic counter (with a cycle setting of H'0008). P TCNT3 Clock TCNT3 GR3D (period) 0008 0000 0001 0002 0003 0008 0007 0008 0000 0001 0002 0003 0004 0005 0008 Cleared by software Cleared by software TSR3 IMF3D Figure 11.14 Example of Cyclic Counter Operation 11.3.3 Compare-Match Function Designating general registers in channels 1 to 5 and 11 (GR1A to GR1H, GR2A to GR2H, GR3A to GR3D, GR4A to GR4D, GR5A to GR5D, GR11A, GR11B) for compare-match operation in the timer I/O control registers (TIOR1 to TIOR5, TIOR11) enables compare-match output to be performed at the corresponding external pins (TIO1A to TIO1H, TIO2A to TIO2H, TIO3A to TIO3D, TIO4A to TIO4D, TIO5A to TIO5D, TIO11A, TIO11B). A free-running counter (TCNT) starts counting up when 1 is set in the timer status register (TSTR). When the desired number is set beforehand in GR, and the TCNT value matches the GR value, the timer status register (TSR) bit corresponding to GR is set and a waveform is output from the corresponding external pin. 1 output, 0 output, or toggle output can be selected by means of a setting in TIOR. If the appropriate interrupt enable register (TIER) setting is made, an interrupt request will be sent to the CPU when a compare-match occurs. Rev. 5.00 Feb. 24, 2010 Page 285 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) To perform internal interrupts by compare-match or compare-match flag polling processing without performing comparematch output, designate the corresponding compare-match output pin as a general I/O pin and select 1 output, 0 output, or toggle output on compare-match in TIOR. Channel 1 and 2 compare-match registers (OCR1, OCR2A to OCR2H) perform compare-match operations unconditionally. However, there are no corresponding output pins. If the appropriate TIER setting is made, an interrupt request will be sent to the CPU when a compare-match occurs. Channel 1 and 2 GR and OCR registers can send a trigger/terminate signal to channel 8 when a compare-match occurs. In this case, settings should be made in the trigger mode register (TRGMDR), timer connection register (TCNR), and oneshot pulse terminate register (OTR). An example of compare-match operation is shown in figure 11.15. In the example in figure 11.15, channel 1 is activated, and external output is performed with toggle output specified for GR1A, 1 output for GR1B, and 0 output for GR1C. P TCNT1 Clock TCNT1 003C 003D 003E GR1A-1C 003F 0040 007E 007F 003E 0080 0081 0082 0083 0084 0085 0081 TIO1A TIO1B TIO1C TSR1 IMF1A-1D Cleared by software Cleared by software Channel 8 start/terminate trigger signal Figure 11.15 Compare-Match Operation 11.3.4 Input Capture Function If input capture registers (ICR0A to ICR0D) and general registers (GR1A to GR1H, GR2A to GR2H, GR3A to GR3D, GR4A to GR4D, GR5A to GR5D, GR11A, GR11B) in channels 1 to 5 and 11 are designated for input capture operation in the timer I/O control registers (TIOR0 to TIOR5, TIOR11), input capture is performed when an edge is input at the corresponding external pins (TI0A to TI0D, TIO1A to TIO1H, TIO2A to TIO2H, TIO3A to TIO3D, TIO4A to TIO4D, TIO5A to TIO5D). A free-running counter (TCNT) starts counting up when a setting is made in the timer start register (TSTR). When an edge is input at an external pin corresponding to ICR or GR, the corresponding timer status register (TSR) bit is set and the TCNT value is transferred to ICR or GR. Rising-edge, falling-edge, or both-edge detection can be selected. By making the appropriate setting in the interrupt enable register (TIER), an interrupt request can be sent to the CPU. An example of input capture operation is shown in figure 11.16. In the example in figure 11.16, channel 1 is activated, and input capture operation is performed with both-edge detection specified for TIO1A, rising-edge detection for TIO1B, and falling-edge detection for TIO1C. Rev. 5.00 Feb. 24, 2010 Page 286 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) P TCNT1 Clock TCNT1 0000 0001 0002 0003 0004 0005 5678 5679 567A 567B 567C 567D 567E TIO1A-1C GR1A 0003 567A GR1B 0003 0003 GR1C 567A Cleared by software Cleared by software TSR1 IMF1A TSR1 IMF1B TSR1 IMF1C Figure 11.16 Input Capture Operation 11.3.5 One-Shot Pulse Function Channel 8 has sixteen down-counters (DCNT8A to DCNT8P) and corresponding external pins (TO8A to TO8P) which can be used as one-shot pulse output pins. When a value is set beforehand in DCNT and the corresponding bit in the down-counter start register (DSTR) is set, DCNT starts counting down, and at the same time 1 is output from the corresponding external pin. When DCNT reaches H'0000 the down-count stops, the corresponding bit in the timer status register (TSR) is set, and 0 is output from the external pin. The corresponding bit in DSTR is cleared automatically. By making the appropriate setting in the interrupt enable register (TIER), an interrupt request can be sent to the CPU. An example of one-shot pulse operation is shown in figure 11.17. In the example in figure 11.17, H'0005 is set in DCNT and a down-count is started. P DSTR DST8A DCNT Clock Synchronized with down-counter clock TO8A DCNT8A 0005 0004 0003 0002 0001 0000 Cleared by software TSR8 Figure 11.17 One-Shot Pulse Output Operation Rev. 5.00 Feb. 24, 2010 Page 287 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) 11.3.6 Offset One-Shot Pulse Function and Output Cutoff Function By making an appropriate setting in the timer connection register (TCNR), down-counting by channel 8 down-counters (DCNT8A to DCNT8P) can be started using compare-match signals from channel 1 general registers (GR1A to GR1H) or channel 1 and 2 compare-match registers (OCR1, OCR2A to OCR2H). DCNT8A to DCNT8H are connected to channel 1 OCR1 or GR1A to GR1H, and DCNT8I to DCNT8P are connected to channel 2 OCR2A to OCR2H or GR2A to GR2H. This enables one-shot pulse output from the external pin (TO8A to TO8P) corresponding to DCNT. The down-count can be forcibly stopped by making a setting in the one-shot pulse terminate register (OTR). On channel 1, down-count start or termination by a GR or OCR compare-match can be selected with the trigger mode register (TRGMDR). Making a setting in the timer start register (TSTR) starts an up-count by a free-running counter (TCNT) in channel 1 or 2. When TCNT matches GR or OCR while connection is enabled by TCNR, the corresponding DSTR is automatically set and DCNT starts counting down. At the same time, 1 is output from the corresponding external pin (TO8A to TO8P). By making the appropriate setting in the interrupt enable register (TIER), an interrupt request can be sent to the CPU. When TCNT1 matches GR or OCR, or TCNT2 matches GR, while channel 8 one-shot pulse termination by a channel 1 or 2 compare-match signal is enabled by OTR, the corresponding DSTR is automatically cleared and DCNT stops counting down. DCNT is cleared to H'0000 at this time, and must be rewritten before the down-count is restarted. DCNT8I to DCNT8P are connected to the reload register (RLDR8), and when the DSTR corresponding to DCNT8I to DCNT8P is set, the DCNT8I to DCNT8P counter loads RLDR8 before starting the down-count. An example of the offset one-shot pulse output function and output cutoff function is shown in figure 11.18. P First prescaler 1 Second prescaler 1 Start trigger (OSTRG1A-P) Terminate trigger (OSTRG0A-P) Down-count start trigger (corresponding bit) Down-counter 10A-10P clock One-shot pulse (TOA10-TOP10) Down-counter 10A-10P Synchronized with down-counter clock 0009 0008 0007 0006 0005 0004 0003 0000 One-shot end detection signal One-shot end interrupt (flag) Figure 11.18 Offset One-Shot Pulse Output Function and Output Cutoff Function Operation 11.3.7 Interval Timer Operation The interval interrupt request registers (ITVRR1, ITVRR2A, ITVRR2B) are connected to bits 6 to 9 and 10 to 13 of the channel 0 free-running counter (TCNT0). The ITVRR registers are 8-bit registers; the upper 4 bits (ITVA) are used for A/D converter activation, and the lower 4 bits (ITVE) are used for interrupt requests. ITVRR1 is connected to A/D converter 2 (AD2), ITVRR2A to A/D converter 0 (AD0), and ITVRR2B to A/D converter 1 (AD1). Rev. 5.00 Feb. 24, 2010 Page 288 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) When the ITVA bit for the desired timing is set, the A/D converter is activated when the corresponding bit of TCNT0 changes to 1. When the ITVE bit for the desired timing is set, an interrupt can be requested when the corresponding bit of TCNT0 changes to 1. At this time, the corresponding bit of the timer status register (TSR0) is set. There are four interrupt sources for the respective ITVRR registers, but there is only one interrupt vector. To suppress interrupts and A/D converter activation, ITVRR bits should be cleared to 0. An example of interval timer function operation is shown in figure 11.19. In the example in figure 11.19, TCNT0 is started by setting ITVE to 1 in ITVRR1. P TCNT0 Clock TCNT0 0000003C 0000003D 0000003E 0000003F 00000040 0000007E 0000007F Internal detection signal In case of bit 6 detection 00000080 00000081 00000082 00000083 00000084 00000085 In case of bit 7 detection AD activation trigger Figure 11.19 Interval Timer Function 11.3.8 Twin-Capture Function Channel 0 input capture register ICR0A, channel 1 offset base register 1 (OSBR1), and channel 2 offset base register 2 (OSBR2) can be made to perform input capture in response to the same trigger by means of a setting in timer I/O control register 0 (TIOR0). When TCNT0, TCNT1A, and TCNT2A in channel 0, channel 1, and channel 2 are started by a setting in the timer start register (TSTR), and an edge of TI0A input (a trigger signal) is detected, the TCNT1A value is transferred to OSBR1, and the TCNT2A value to OSBR2. Edge detection is as described in section 11.3.4, Input Capture Function. An example of twin-capture operation is shown in figure 11.20. P TCNT1A Clock TCNT1A 0000 0001 0002 0003 0004 0005 5678 5679 567A 567B 567C 567D 567E Edge detection signal (from channel 0) OSBR1 0003 567A Figure 11.20 Twin-Capture Operation Rev. 5.00 Feb. 24, 2010 Page 289 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) 11.3.9 PWM Timer Function Channels 6 and 7 can be used unconditionally as PWM timers using external pins (TO6A to TO6D, TO7A to TO7D). In channels 6 and 7, when the corresponding bit is set in the timer start register (TSTR) and the free-running counter (TCNT) is started, the counter counts up until its value matches the corresponding cycle register (CYLR). When TCNT matches CYLR, it is cleared to H'0001 and starts counting up again from that value. At this time, 1 is output from the corresponding external pin. An interrupt request can be sent to the CPU by setting the corresponding bit in the timer interrupt enable register (TIER). If a value has been set in the duty register (DTR), when TCNT matches DTR, 0 is output to the corresponding external pin. If the DTR value is H'0000, the output does not change (0% duty). To set H'0000 to DTR, not write H'0000 directly to DTR but set H'0000 to BFR and then transfer the value to DTR. Writing H'0000 directly to DTR may not give a duty of 0%. A duty of 100% is specified by setting DTR = CYLR. Do not set a value in DTR that will result in the condition DTR > CYLR. Channels 6 and 7 have buffers (BFR); the BFR value is transferred to DTR when TCNT matches CYLR. The duty value written into BFR is reflected in the output value in the cycle following that in which BFR is written to. An example of PWM timer operation is shown in figure 11.21. In the example in figure 11.21, H'0004 is set in channel 6 CYLR6A, and H'0002, H'0000 (0%), H'0004 (100%), and H'0001 in BFR6A. P STR6A TCNT6A Clock TCNT6A 0001 0002 0003 0004 0001 0002 0003 0004 0001 0002 0003 0004 0001 0002 0003 0004 0001 0002 0003 0004 CYLR6A Data = 0000 Data = 0004 Data = 0001 Write to BFR6A BFR6A 0002 0002 DTR6A TO6A 0004 0000 * PWM output does not change for one cycle after activation Cleared by software 0001 0000 0004 Cleared by software 0001 Cleared by software TSR6 CMF6A Cycle Cycle Cycle Duty = 0% Cycle Duty = 100% Cycle Note: * Since the retained value is output, the PWM output is not guaranteed for one cycle after activation. Figure 11.21 PWM Timer Operation Channel 6 can be used in complementary PWM mode by making a setting in the PWM mode control register (PMDR). On-duty or off-duty can also be selected with a setting in PMDR. When TCNT6 is started by a setting in TSTR, it starts counting up. When TCNT6 reaches the CYLR6 value, it starts counting down, and on reaching H'000, starts counting up again. The counter status is shown by TSR6. When TCNT6 underflows, an interrupt request can be sent to the CPU by setting the corresponding bit in TIER. When TCNT6 matches the duty register (DTR6) value, the output is inverted. The output prior to the match depends on the PMDR setting. When Rev. 5.00 Feb. 24, 2010 Page 290 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) a value including dead time is set in DTR6, a maximum of 4-phase PWM output is possible. Data transfer from BFR6 to DTR6 is performed when TCNT6 underflows. An example of channel 6 complementary PWM mode operation is shown in figure 11.22. In the example in figure 11.22, H'0004 is set in channel 6 CYLR6A, and H'0002, H'0003, H'0004 (100%), and H'0000 (0%) in BFR6A. P STR6A TCNT6A Clock TCNT6A TSR6 UD6A 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 03 04 03 02 01 00 01 02 03 04 03 02 01 00 01 02 03 04 03 02 01 00 01 02 03 04 03 02 01 00 01 02 03 04 03 02 01 Down Down Up Down Up Down Up CYLR6A Down Up Up 0004 Data = 0003 Data = 0004 Data = 0000 Write to BFR6A BFR6A 0003 0002 DTR6A 0002 0004 0003 0000 0004 0000 * TO6A PWM output does not change for one cycle after activation Cleared by software Cleared by software Cleared by software Cleared by software TSR6 CMF6A Cycle Cycle Cycle Cycle Duty=100% Cycle Duty=0% Note: * Since the retained value is output, the PWM output is not guaranteed for one cycle after activation. Figure 11.22 Complementary PWM Mode Operation 11.3.10 Channel 3 to 5 PWM Function PWM mode is selected for channels 3 to 5 by setting the corresponding bits to 1 in the timer mode register (TMDR), enabling the channels to operate as PWM timers with the same cycle. In PWM mode, general registers D (GR3D, GR4D, GR5D) are used as cycle registers, and general registers A to C (GR3A to GR3C, GR4A to GR4C, GR5A to GR5C) as duty registers. The external pins (TIO3A to TIO3C, TIO4A to TIO4C, TIO5A to TIO5C) corresponding to the GRs used as duty registers are used as PWM outputs. External pins TIO3D, TIO4D, and TIO5D should not be used as timer outputs. The free-running counter (TCNT) is started by making a setting in the timer start register (TSTR), and when TCNT reaches the cycle register (GR3D, GR4D, GR5D) value, a compare-match is generated and TCNT starts counting up again from H'0000. At the same time, the corresponding bit is set in the timer status register (TSR) and 1 is output from the corresponding external pin. When TCNT reaches the duty register (GR3A to GR3C, GR4A to GR4C, GR5A to GR5C) value, 0 is output to the external pin. The corresponding status flag is not set. When PWM operation is performed by starting the free-running counter from its initial value of H'0000, PWM output is not performed for one cycle. To perform immediate PWM output, the value in the cycle register must be set in the free-running counter before the counter is started. If PWM operation is performed after setting H'FFFF in the cycle register, the cycle register's compare-match flag and overflow flag will be set simultaneously. Rev. 5.00 Feb. 24, 2010 Page 291 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) Note that 0% or 100% duty output is not possible in channel 3 to 5 PWM mode. An example of channel 3 to 5 PWM mode operation is shown in figure 11.23. In the example in figure 11.23, H'0008 is set in GR3D, H'0002 is set in GR3A, GR3B, and GR3C, and channel 3 is activated; then, during operation, H'0000 is set in GR3A, GR3B, and GR3C, and output is performed to external pins TIOA3 to TIOC3. Note that 0% duty output is not possible even though H'0000 is set. P TCNT3 Clock TCNT3 GR3D 0008 0000 0001 0002 0003 0007 0008 0008 0000 0001 0002 0003 0004 0005 0008 Rewritten by software GR3A 3C (pulse width) 0002 0000 TIO3A TIO3C Cleared by software Cleared by software TSR3 Figure 11.23 Channel 3 to 5 PWM Mode Operation 11.3.11 Event Count Function and Event Cycle Measurement Channel 9 has six 8-bit event counters (ECNT9A to ECNT9F) and corresponding general registers (GR9A to GR9F). Each event counter has an external pin (TI9A to TI9F). Each ECNT9 operates unconditionally as an event counter. When an edge is input from the external pin, ECNT9 is incremented. When ECNT9 matches the value set in GR9, it is cleared, and then counts up when an edge is again input at the external pin. By making the appropriate setting in the interrupt enable register (TIER) beforehand, an interrupt request can be sent to the CPU on compare-match. For ECNT9A to ECNT9D, a trigger can be transmitted to channel 3 when a compare-match occurs. In channel 3, if the channel 9 trigger input is set in the timer I/O control register (TIOR) and the corresponding bit is set to 1 in the timer start register (TSTR), the TCNT3 value is captured in the corresponding general register (GR3A to GR3D) when an ECNT9A to ECNT9D compare-match occurs. This enables the event cycle to be measured. An example of event count operation is shown in figure 11.24. In this example, ECNT9A counts up on both-edge, fallingedge, and rising-edge detection, H'10 is set in GR9A, and a compare-match is generated. An example of event cycle measurement operation is shown in figure 11.25. In this example, GR3A in channel 3 captures TCNT3 in response to a trigger from channel 9. Rev. 5.00 Feb. 24, 2010 Page 292 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) P TI9A Edge detection signal ECNT9A Clock ECNT9A 00 01 02 03 10 GR9A 00 05 06 10 Cleared by software TSR9 CMF9A Capture trigger To channel 3 Falling edge Rising and falling edges Rising edge Figure 11.24 Event Count Operation P TCNT3 Clock TCNT3 0000 0001 0002 0003 0004 0005 5678 5679 567A 567B 567C 567D 567E Compare-match trigger (from channel 9) GR3A TSR3 IMF3A 567A 0004 Cleared by software Figure 11.25 Event Cycle Measurement Operation 11.3.12 Channel 10 Functions Inter-Edge Measurement Function and Edge Input Cessation Detection Function:32-bit input capture register 10A (ICR10A) and 32-bit output compare register 10A (OCR10A) in channel 10 unconditionally perform input capture and compare-match operations, respectively. These registers are connected to 32-bit free-running counter TCNT10A. When the corresponding bit is set in the timer start register (TSTR), the entire channel 10 starts operating. ICR10A has an external input pin (TI10), and when an edge is input at this input pin, ICR10A captures the TCNT10A value. At this time, TCNT10A is cleared to H'00000001. The captured value is transferred to the read register (RLD10C) in the multiplied clock generation block. By making the appropriate setting in the interrupt enable register (TIER), an interrupt request can be sent to the CPU. This allows inter-edge measurement to be carried out. When TCNT10A reaches the value set in OCR10A, a compare-match interrupt can be requested. In this way it is possible to detect the cessation of edge input beyond the time set in OCR10A. The input edge from TI10 is synchronized internally; the internal signal is AGCK. Noise cancellation is possible for edges input at TI10 using the timer 10H (TCNT10H) input cancellation function by setting the NCE bit in timer control register TCR10. When an edge is input at TI10, TCNT10H starts and input is disabled until it reaches compare-match register NCR10. Rev. 5.00 Feb. 24, 2010 Page 293 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) Edge input operation without noise cancellation is shown in figure 11.26, edge input operation with noise cancellation in figure 11.27, and TCNT10A capture operation and compare-match operation in figure 11.28. P TI10 After internal synchronization 1 After internal synchronization 2 AGCK AGCK operation TCNT clock When rising edge is set When falling edge is set When rising and falling edges are set Figure 11.26 Edge Input Operation (Without Noise Cancellation) P TI10 AGCK Noise cancellation period External edge mask period External edge mask period P x 10 (clock) TCNT10H 0 NCR10 1 0 1 AGCK operation TCNT clock Note: When rising and falling edges are set Figure 11.27 Edge Input Operation (With Noise Cancellation) Rev. 5.00 Feb. 24, 2010 Page 294 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) P TSTR1 STR10 TCNT10A Clock TCNT10A 00000001 00000002 00000003 12345677 1234 5678 00000001 55555555 55555556 55555557 AGCK Capture transfer signal TCNT reset signal ICR10A 00000000 12345678 Cleared by software TSR10 IMF10A OCR10A 55555556 TSR10 CMF10A Cleared by software Figure 11.28 TCNT10A Capture Operation and Compare-Match Operation Internally synchronized AGCK is counted by event count 10B (TCNT10B), and when TCNT10B reaches the value set beforehand in compare-match register 10B (OCR10B), a compare-match occurs, and the compare-match trigger signal is transmitted to channel 0. By setting the corresponding bit in TIER, an interrupt request can be sent to the CPU. Figure 11.29 shows TCNT10B compare-match operation. P AGCK TCNT10B Clock TCNT10B 00 01 55 56 OCR10B 55 TSR10 CMF10B Cleared by software Channel 0 trigger Figure 11.29 TCNT10B Compare-Match Operation Multiplied Clock Generation Function: The channel 10 16-bit reload counter (TCNT10C, RLD10C) and 16-bit freerunning counter 10G (TCNT10G) can be used to multiply the interval between edges input from external pin TI10 by 32, 64, 128, or 256. The value captured in ICR10A above is multiplied by 1/32, 1/64, 1/128, or 1/256 according to the value set in the timer I/O control register (TIOR10), and transferred to the reload buffer (RLD10C). At the same time, the same value is transferred to 16-bit reload counter 10C (TCNT10C) and a down-count operation is started. When this counter reaches H'0001, the value is read automatically from RLD10C and the down-count operation is repeated. When this reload occurs, a multiplied clock signal (AGCK1) is generated. AGCK1 is converted to a corrected clock (AGCKM) by the multiplied clock correction function described in the following section. Rev. 5.00 Feb. 24, 2010 Page 295 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) Channel 10 can also perform compare-match operation by means of the multiplied clock (AGCK1) using general register 10G (GR10G) and 16-bit free-running counter 10G (TCNT10G). TCNT10G is incremented unconditionally by AGCK1. By making the appropriate setting in the interrupt enable register (TIER), an interrupt request can be sent to the CPU when TCNT10G and GR10G match. The timing of this interrupt can be selected with the IREG bit in TIER as either on occurrence of the compare-match or on input of the first TI10 edge after the compare-match. TCNT10C operation is shown in figure 11.30, and TCNT10G compare-match operation in figure 11.31. P STR10 AGCK ICR10A 00000000 00000020 1ck Shifter output 1ck 0000 0001 Initial value set by software 0002 RLD10C RLD10C write enable signal TCNT10C 0001 Not loaded when RLDEN = 1 0002 0001 0001 0002 0002 0001 0001 0001 0001 0001 RLD10C load signal AGCK1 RLDEN RLDEN set to 0 by software RLDEN set to 1 by software Note: In case of multiplication factor of 32 Figure 11.30 TCNT10C Operation P AGCK AGCK1 Cleared by AGCK Write by software TCNT10G 0000 0001 0002 0034 0035 0036 0034 GR10G When IREG = 1 TSR10 CMF10G When IREG = 0 TSR10 CMF10G Figure 11.31 TCNT10G Compare-Match Operation Rev. 5.00 Feb. 24, 2010 Page 296 of 950 REJ09B0177-0500 0000 0001 11. Advanced Timer Unit-II (ATU-II) Multiplied Clock Correction Function: Channel 10's three 16-bit correction counters (TCNT10D, TCNT10E, TCNT10F) and correction counter clear register (TCCLR10) have a correction function that makes the interval between edges input from TI10 the frequency multiplication value set in TIOR10. When AGCK is input, the value in TCNT10D multiplied by the multiplication factor set in TIOR10 is transferred to TCNT10E. At the same time, TCNT10D is incremented. TCNT10E counts up on AGCK1. TCNT10E loads TCNT10D on AGCK, and counts up again on AGCK1. Using the counter correction select bit (CCS) in TIOR10, it is possible to select whether or not TCNT10E is halted when TCNT10D = TCNT10E. TCNT10F has the peripheral clock (P) as its input and is constantly compared with TCNT10E. When the TCNT10F value is smaller than that in TCNT10E, TCNT10F is incremented and outputs a corrected multiplied clock signal (AGCKM). When the TCNT10F value exceeds the TCNT10E value, no count-up operation is performed. AGCKM is output to the channel 1 to 5 free-running counters (TCNT1 to TCNT5). Channel 10 also has a correction counter clear register (TCCLR10). The correction counters (TCNT10D, TCNT10E, TCNT10F) and channel 1 and 2 free-running counters (TCNT1 and TCNT2) can be cleared when TCNT10F reaches the value set in TCCLR10. TCNT10D operation is shown in figure 11.32, TCNT10E operation in figure 11.33, TCNT10F operation (at startup) in figure 11.34, TCNT10F operation (end of cycle, acceleration, deceleration) in figure 11.35, and TCNT10F operation (end of cycle, steady-state) in figure 11.36. P STR10 AGCK TCNT10D Clock TCNT10D Shifter output 00 01 02 03 0000 0020 0040 0060 Note: In case of multiplication factor of 32 Figure 11.32 TCNT10D Operation Rev. 5.00 Feb. 24, 2010 Page 297 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) P STR10 AGCK AGCK1 Initial value load TCNT10E valid Corrected value load 0024 00 00 TCNT10E TCNT10D (shift amount) Corrected value load 0001 0002 0003 0000 0004 0022 0023 0020 0021 0038 0022 0020 0039 00 41 0040 0040 00 42 00 43 00 44 0060 Note: In case of multiplication factor of 32 Figure 11.33 TCNT10E Operation P STR10 AGCK TCNT10E Clock 0024 0000 TCNT10E TCNT10F 0001 0080 0002 0001 0003 0002 0004 0003 0004 0022 0023 0022 0020 0023 0021 0022 0023 0024 0025 0026 0025 0024 0027 0026 0027 Same value as cycle register set by software AGCKM TCNT clock operating on AGCKM TCNT1, TCNT2 0000 0001 0002 0003 0022 0023 0024 0025 0026 TCNT1, TCNT2 reset trigger TCNT10D 00 01 02 Note: Multiplication factor of 32, TCCLR10 = H'0080 Figure 11.34 TCNT10F Operation (At Startup) Rev. 5.00 Feb. 24, 2010 Page 298 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) P STR10 AGCK TCNT10E Clock TCNT10E 005A 0061 0062 0063 0065 0064 0066 0076 0077 0079 0078 007A 00 00 TCNT10F 0001 0002 0003 0080 0060 00 62 005A 0063 0064 0065 0066 0076 0077 0078 0079 00 01 007A 0002 0003 AGCKM TCNT clock operating on AGCKM TCNT1, TCNT2 00 62 005A 0063 0064 0065 00 66 0076 0077 TCNT1, TCNT2 reset trigger TCNT10D 0078 0079 00 0002 01 0000 007A 0003 Cleared to H'00 by software 03 04 01 00 Note: Multiplication factor of 32, TCCLR10 = H'0080 Figure 11.35 TCNT10F Operation (End of Cycle, Acceleration, Deceleration) P STR10 AGCK TCNT10E Clock TCNT10E 005A 0061 0062 0063 0065 0064 0066 007F 007E 0080 0081 0082 00 00 0001 0003 0002 0060 TCNT10F 005A 00 62 0063 0064 0065 0066 007E 007F 0080 0001 0002 0003 AGCKM TCNT clock operating on AGCKM TCNT1, TCNT2 005A 00 62 0063 0064 00 0065 66 007E 007F 0000 0001 0002 TCNT1, TCNT2 reset trigger Set to H'00 by software TCNT10D 03 04 01 00 Note: Multiplication factor of 32, TCCLR10 = H'0080 Figure 11.36 TCNT10F Operation (End of Cycle, Steady-State) Rev. 5.00 Feb. 24, 2010 Page 299 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) 11.4 Interrupts The ATU has 75 interrupt sources of five kinds: input capture interrupts, compare-match interrupts, overflow interrupts, underflow interrupts, and interval interrupts. 11.4.1 Status Flag Setting Timing IMF (ICF) Setting Timing in Input Capture: When an input capture signal is generated, the IMF bit and ICF bit are set to 1 in the timer status register (TSR), and the TCNT value is simultaneously transferred to the corresponding GR, ICR, and OSBR. The timing in this case is shown in figure 11.37. In the example in figure 11.37, a signal is input from an external pin, and input capture is performed on detection of a rising edge. CK tTICS (input capture input setup time) Input capture input Internal input capture signal TCNT N GR (ICR) N Interrupt status flag IMF (ICF) Interrupt request signal IMI (ICI) Figure 11.37 IMF (ICF) Setting Timing in Input Capture IMF (ICF) Setting Timing in Compare-Match: The IMF bit and CMF bit are set to 1 in the timer status register (TSR) by the compare-match signal generated when the general register (GR) output compare register (OCR), or cycle register (CYLR) value matches the timer counter (TCNT) value. The compare-match signal is generated in the last state of the match (when the matched TCNT count value is updated). The timing in this case is shown in figure 11.38. Rev. 5.00 Feb. 24, 2010 Page 300 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) CK TCNT input clock N TCNT GR (OCR, CYLR) N+1 N Compare-match signal Interrupt status flag IMF (CMF) Interrupt request signal IMI (CMI) Figure 11.38 IMF (CMF) Setting Timing in Compare-Match OVF Setting Timing in Overflow: When TCNT overflows (from H'FFFF to H'0000, or from H'FFFFFFFF to H'00000000), the OVF bit is set to 1 in the timer status register (TSR). The timing in this case is shown in figure 11.39. CK TCNT input clock TCNT H'FFFF H'0000 Overflow signal Interrupt status flag OVF Interrupt request signal OVI Figure 11.39 OVF Setting Timing in Overflow Rev. 5.00 Feb. 24, 2010 Page 301 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) OSF Setting Timing in Underflow: When a down-counter (DCNT) counts down from H'0001 to H'0000 on DCNT input clock input, the OSF bit is set to 1 in the timer status register (TSR) when the next DCNT input clock pulse is input (when underflow occurs). The timing in this case is shown in figure 11.40. CK DCNT input clock DCNT H'0001 H'0000 H'0000 Underflow signal Interrupt status flag OSF Interrupt request signal OSI Figure 11.40 OSF Setting Timing in Underflow Timing of IIF Setting by Interval Timer: When 1 is generated by ANDing the rise of bit 10-13 in free-running counter TCNT0L with bit ITVE0-ITVE3 in the interval interrupt request register (ITVRR), the IIF bit is set to 1 in the timer status register (TSR). The timing in this case is shown in figure 11.41. TCNT0 value N in the figure is the counter value when TCNT0L bit 6-13 changes to 1. (For example, N = H'00000400 in the case of bit 10, H'00000800 in the case of bit 11, etc.) CK TCNT input clock TCNT0 N-1 N Internal interval signal Interrupt status flag IIF Interrupt request signal Figure 11.41 Timing of IIF Setting Timing by Interval Timer Rev. 5.00 Feb. 24, 2010 Page 302 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) 11.4.2 Status Flag Clearing Clearing by CPU Program: The interrupt status flag is cleared when the CPU writes 0 to the flag after reading it while set to 1. The procedure and timing in this case are shown in figure 11.42. TSR write cycle T1 T2 Start CK Read 1 from TSR Address TSR address Internal write signal Write 0 to TSR Interrupt status flag IMF, ICF, CMF, OVF, OSF, IIF Interrupt status flag cleared Interrupt request signal Figure 11.42 Procedure and Timing for Clearing by CPU Program Clearing by DMAC: The interrupt status flag (ICF0A to ICF0D, CMF6A to CMF6D, CMF7A to CMF7D) is cleared automatically during data transfer when the DMAC is activated by input capture or compare-match. The procedure and timing in this case are shown in figure 11.43. CK Start Clear request signal from DMAC Activate DMAC Interrupt status flag cleared during data transfer Interrupt status flag clear signal Interrupt status flag ICF0B, CMF6 Interrupt request signal Figure 11.43 Procedure and Timing for Clearing by DMAC Rev. 5.00 Feb. 24, 2010 Page 303 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) 11.5 CPU Interface 11.5.1 Registers Requiring 32-Bit Access Free-running counters 0 and 10A (TCNT0, TCNT10A), input capture registers 0A to 0D and 10A (ICR0A to ICR0D, ICR10A), and output compare register 10A (OCR10A) are 32-bit registers. As these registers are connected to the CPU via an internal 16-bit data bus, a read or write (read only, in the case of ICR0A to ICR0D and ICR10A) is automatically divided into two 16-bit accesses. Figure 11.44 shows a read from TCNT0, and figure 11.45 a write to TCNT0. When reading TCNT0, in the first read the TCNT0H (upper 16-bit) value is output to the internal data bus, and at the same time, the TCNT0L (lower 16-bit) value is output to an internal buffer register. Then, in the second read, the TCNT0L (lower 16-bit) value held in the internal buffer register is output to the internal data bus. When writing to TCNT0, in the first write the upper 16 bits are output to an internal buffer register. Then, in the second write, the lower 16 bits are output to TCNT0L, and at the same time, the upper 16 bits held in the internal buffer register are output to TCNT0H to complete the write. The above method performs simultaneous reading and simultaneous writing of 32-bit data, preventing contention with an up-count. Internal data bus H CPU 1st read operation Module data bus H Bus interface TCNT0H Internal buffer register L TCNT0L Module data bus Internal data bus L CPU 2nd read operation Bus interface Module data bus L Internal buffer register Figure 11.44 Read from TCNT0 Rev. 5.00 Feb. 24, 2010 Page 304 of 950 REJ09B0177-0500 TCNT0H TCNT0L 11. Advanced Timer Unit-II (ATU-II) 1st write operation Internal data bus H CPU Bus interface H Internal buffer register TCNT0H Module data bus Internal data bus L CPU TCNT0L Module data bus Internal buffer H register 2nd write operation Bus interface L TCNT0H TCNT0L Module data bus Figure 11.45 Write to TCNT0 11.5.2 Registers Permitting 8-Bit, 16-Bit, or 32-Bit Access Timer registers 1, 2, and 3 (TSTR1, TSTR2, TSTR3) are 8-bit registers. As these registers are connected to the CPU via an internal 16-bit data bus, a simultaneous 32-bit read or write access to TSTR1, TSTR2, and TSTR3 is automatically divided into two 16-bit accesses. Figure 11.46 shows a read from TSTR, and figure 11.47 a write to TSTR. When reading TSTR, in the first read the TSTR1 and TSTR2 (upper 16-bit) value is output to the internal data bus. Then, in the second read, the TSTR3 (lower 16-bit) value is output to the internal data bus. When writing to TSTR, in the first write the upper 16 bits are written to TSTR1 and TSTR2. Then, in the second write, the lower 16 bits are written to TSTR3. Note that, with the above method, in a 32-bit write the write timing is not the same for TSTR1/TSTR2 and TSTR3. For information on 8-bit and 16-bit access, see section 11.5.4, 8-Bit or 16-Bit Accessible Registers. Internal data bus H CPU Internal data bus L CPU 1st read operation Module data bus H Bus interface TSTR2 TSTR1 TSTR3 2nd read operation Bus interface TSTR2 Module data bus L TSTR1 TSTR3 Figure 11.46 Read from TSTR1, TSTR2, and TSTR3 Rev. 5.00 Feb. 24, 2010 Page 305 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) 1st write operation Internal data bus H CPU Bus interface H TSTR2 TSTR1 TSTR3 Module data bus Internal data bus L CPU 2nd write operation Bus interface L TSTR2 TSTR1 TSTR3 Module data bus Figure 11.47 Write to TSTR1, TSTR2 and TSTR3 11.5.3 Registers Requiring 16-Bit Access The free-running counters (TCNT; but excluding TCNT0, TCNT10A, TCNT10B, TCNT10D, and TCNT10H), the general registers (GR; but excluding GR9A to GR9D), down-counters (DCNT), offset base register (OSBR), cycle registers (CYLR), buffer registers (BFR), duty registers (DTR), timer connection register (TCNR), one-shot pulse terminate register (OTR), down-count start register (DSTR), output compare registers (OCR: but excluding OCR10B), reload registers (RLDR8, RLD10C), correction counter clear register (TCCLR10), timer interrupt enable register (TIER), and timer status register (TSR) are 16-bit registers. These registers are connected to the CPU via an internal 16-bit data bus, and can be read or written (read only, in the case of OSBR) a word at a time. Figure 11.48 shows the operation when performing a word read or write access to TCNT1A. Internal data bus CPU Bus interface Module data bus TCNT1A Figure 11.48 TCNT1A Read/Write Operation 11.5.4 8-Bit or 16-Bit Accessible Registers The timer control registers (TCR1A, TCR1B, TCR2A, TCR2B, TCR6A, TCR6B, TCR7A, TCR7B), timer I/O control registers (TIOR1A to TIOR1D, TIOR2A to TIOR2D, TIOR3A, TIOR3B, TIOR4A, TIOR4B, TIOR5A, TIOR5B), and the timer start register (TSTR1, TSTR2, TSTR3) are 8-bit registers. These registers are connected to the CPU with the upper 8 bits or lower 8 bits of the internal 16-bit data bus, and can be read or written a byte at a time. In addition, a pair of 8-bit registers for which only the least significant bit of the address is different, such as timer I/O control register 1A (TIOR1A) and timer I/O control register 1B (TIOR1B), can be read or written in combination a word at a time. Figures 11.49 and 11.50 show the operation when performing individual byte read or write accesses to TIOR1A and TIOR1B. Figure 11.51 shows the operation when performing a word read or write access to TIOR1A and TIOR1B simultaneously. Rev. 5.00 Feb. 24, 2010 Page 306 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) Internal data bus CPU Bus interface Only upper 8 bits used Module data bus Only upper 8 bits used TIOR1B TIOR1A Figure 11.49 Byte Read/Write Access to TIOR1B Internal data bus CPU Bus interface Only lower 8 bits used Module data bus Only lower 8 bits used TIOR1B TIOR1A Figure 11.50 Byte Read/Write Access to TIOR1A Internal data bus CPU Bus interface Module data bus TIOR1B TIOR1A Figure 11.51 Word Read/Write Access to TIOR1A and TIOR1B 11.5.5 Registers Requiring 8-Bit Access The timer mode register (TMDR), prescaler register (PSCR), timer I/O control registers (TIOR0, TIOR10, TIOR11), trigger mode register (TRGMDR), interval interrupt request register (ITVRR), timer control registers (TCR3, TCR4, TCR5, TCR8, TCR9A to TCR9C, TCR10, TCR11), PWM mode register (PMDR), reload enable register (RLDENR), free-running counters (TCNT10B, TCNT10D, TCNT10H), event counter (ECNT), general registers (GR9A to GR9F), output compare register (OCR10B), and noise canceler register (NCR) are 8-bit registers. These registers are connected to the CPU with the upper 8 bits of the internal 16-bit data bus, and can be read or written a byte at a time. Figure 11.52 shows the operation when performing individual byte read or write accesses to ITVRR1. Internal data bus CPU Only upper 8 bits used Bus interface Module data bus ITVRR1 Only upper 8 bits used Figure 11.52 Byte Read/Write Access to ITVRR1 11.6 Sample Setup Procedures Sample setup procedures for activating the various ATU-II functions are shown below. Sample Setup Procedure for Input Capture: An example of the setup procedure for input capture is shown in figure 11.53. Rev. 5.00 Feb. 24, 2010 Page 307 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) Start Select counter clock 1 Set port-ATU-II connection 2 Set input waveform edge detection 3 Start counter 4 1. Select the first-stage counter clock ' in prescaler register (PSCR) and the second-stage counter clock " with the CKSEL bit in the timer control register (TCR). When selecting an external clock, also select the external clock edge type with the CKEG bit in TCR. 2. Set the port control register, corresponding to the port for signal input as the input capture trigger, to ATU input capture input. 3. Select rising edge, falling edge, or both edges as the input capture signal input edge(s) with the timer I/O control register (TIOR). If necessary, a timer interrupt request can be sent to the CPU on input capture by making the appropriate setting in the interrupt enable register (TIER). In channel 0, setting the DMAC allows DMAC activation to be performed. 4. Set the corresponding bit to 1 in the timer start register (TSTR) to start the free-running counter (TCNT) for the relevant channel. Note: When input capture occurs, the counter value is always captured, irrespective of free-running counter (TCNT) activation. Input capture operation Figure 11.53 Sample Setup Procedure for Input Capture Sample Setup Procedure for Waveform Output by Output Compare-Match: An example of the setup procedure for waveform output by output compare-match is shown in figure 11.54. Start Select counter clock 1 Set port-ATU-II connection 2 Select waveform output mode 3 Set output timing 4 Start counter 5 1. Select the first-stage counter clock ' in prescaler register (PSCR), and the second-stage counter clock " with the CKSEL bit in the timer control register (TCR). When selecting an external clock, also select the external clock edge type with the CKEG bit in TCR. 2. Set the port control register corresponding to the waveform output port to ATU output compare-match output. Also set the corresponding bit to 1 in the port IO register to specify the output attribute for the port. 3. Select 0, 1, or toggle output for output compare-match output with the timer I/O control register (TIOR). If necessary, a timer interrupt request can be sent to the CPU on output compare-match by making the appropriate setting in the interrupt enable register (TIER). 4. Set the timing for compare-match generation in the ATU general register (GR) corresponding to the port set in (2). 5. Set the corresponding bit to 1 in the timer start register (TSTR) to start the free-running counter (TCNT). Waveform output is performed from the relevant port when the TCNT value and GR value match. Waveform output Figure 11.54 Sample Setup Procedure for Waveform Output by Output Compare-Match Rev. 5.00 Feb. 24, 2010 Page 308 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) Sample Setup Procedure for Channel 0 Input Capture Triggered by Channel 10 Compare-Match: An example of the setup procedure for compare-match signal transmission is shown in figure 11.55. Start Set compare-match 1 Set TCR10 2 Start counter 3 1. Set the timing for compare-match generation in the channel 10 output compare register (OCR10B). 2. Set the TRG0DEN bit to 1 in the channel 10 timer control register (TCR10). 3. Set the corresponding bit to 1 in the timer start register (TSTR) to start the channel 10 free-running counter (TCNT10B). On compare-match between TCNT10 and OCR10B, the compare-match signal is transmitted to channel 0 as the channel 0 ICR0D input capture signal. Signal transmission Figure 11.55 Sample Setup Procedure for Compare-Match Signal Transmission Sample Setup Procedure for One-Shot pulse Output: An example of the setup procedure for one-shot pulse output is shown in figure 11.56. Start Select counter clock 1 Set port-ATU-II connection 2 Set pulse width 3 Start down-count 4 1. Set the first-stage counter clock ' in prescaler register 1 (PSCR1), and select the second-stage counter clock " with the CKSEL bit in timer control register8 TCR8. 2. Set port K control registers H and L (PKCRH, PKCRL) corresponding to the waveform output port to ATU one-shot pulse output. Also set the corresponding bit to 1 in the port K IO register (PKIOR) to specify the output attribute. 3. Set the one-shot pulse width in the down-counter (DCNT) corresponding to the port set in (2). If necessary, a timer interrupt request can be sent to the CPU when the downcounter underflows by making the appropriate setting in the interrupt enable register (TIER8). 4. Set the corresponding bit (DST8A to DST8P) to 1 in the down-count start register (DSTR) to start the down-counter (DCNT). One-shot pulse output Figure 11.56 Sample Setup Procedure for One-Shot Pulse Output Rev. 5.00 Feb. 24, 2010 Page 309 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) Sample Setup Procedure for Offset One-Shot Pulse Output/Cutoff Operation: An example of the setup procedure for offset one-shot pulse output is shown in figure 11.57. Start Select counter clock 1 Set port-ATU-II connection 2 Set pulse width 3 Set offset width 4 Set offset operation 5 Start count 6 1. Set the first-stage counter clock ' in prescaler register 1 (PSCR1), and select the second-stage counter clock " with the CKSEL bit in the timer control register (TCR1, TCR2, TCR8). 2. Set port K control registers H and L (PKCRH, PKCRL) corresponding to the waveform output port to ATU one-shot pulse output. Also set the corresponding bit to 1 in the port K IO register (PKIOR) to specify the output attribute 3. Set the one-shot pulse width in the down-counter (DCNT) corresponding to the port set in (2). If necessary, a timer interrupt request can be sent to the CPU when the downcounter underflows by making the appropriate setting in the interrupt enable register (TIER8). 4. Set the offset width in the channel 1 or 2 general register (GR1A--GR1H, GR2A--GR2H) connected to the downcounter (DCNT) corresponding to the port set in (2), and in the output compare register (OCR1, OCR2A--OCR2H). Set the timer I/O control register (TIOR1A--TIOR1D, TIOR2A--TIOR2D) to the compare-match enabled state. 5. Set the start/terminate trigger by means of the trigger mode register (TRGMDR), timer connection register (TCNR), and one-shot pulse terminate register (OTR), so that it corresponds to the port set in (2). 6. Set the corresponding bit to 1 in the timer start register (TSTR) to start the channel 1 or 2 free-running counter (TCNT1, TCNT2). When the TCNT value and GR value or OCR value match, the corresponding DCNT starts counting down or is forcibly cleared, and one-shot pulse output is performed. Offset one-shot pulse output Figure 11.57 Sample Setup Procedure for Offset One-Shot Pulse Output Rev. 5.00 Feb. 24, 2010 Page 310 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) Sample Setup Procedure for Interval Timer Operation: An example of the setup procedure for interval timer operation is shown in figure 11.58. Start Select counter clock Set interval Start counter 1 1. Set the first-stage counter clock ' in prescaler register 1 (PSCR1). 2. Set the ITVE bit to be used in the interval interrupt request register (ITVRR) to 1. An interrupt request can be sent to the CPU when the corresponding bit changes to 1 in the 2 channel 0 free-running counter (TCNT0). To start A/D converter sampling, set the ITVA bit to be used in ITVRR to 1. 3. Set bit 0 to 1 in the timer start register (TSTR) to start 3 TCNT0. Interrupt request to CPU or start of A/D sampling Figure 11.58 Sample Setup Procedure for Interval Timer Operation Sample Setup Procedure for PWM Timer Operation (Channels 3 to 5 ): An example of the setup procedure for PWM timer operation (channels 3 to 5 ) is shown in figure 11.59. Start Select counter clock 1 Set port-ATU-II connection 2 Set PWM timer 3 Set GR 4 Start count 5 1. Set the first-stage counter clock ' in prescaler register 1 (PSCR1), and select the second-stage counter clock " with the CKSEL bit in the timer control register (TCR). When selecting an external clock, at the same time select the external clock edge type with the CKEG bit in TCR. 2. Set the port control registers (PxCRH, PxCRL) corresponding to the waveform output port to ATU output compare-match output. Also set the corresponding bit to 1 in the port IO register (PxIOR) to specify the output attribute. 3. Set bit T3PWM-T5PWM in the timer mode register (TMDR) to PWM mode. When PWM mode is set, the timer operates in PWM mode irrespective of the timer I/O control register (TIOR) contents, and general registers (GR3A to GR3D, GR4A to GR4D, GR5A to GR5D) can be written to. 4. The GR3A-GR3C, GR4A-GR4C, and GR5A-GR5C ATU general registers are used as duty registers (DTR), and the GR3D, GR4D, and GR5D ATU general registers as cycle registers (CYLR). Set the PWM waveform output 0 output timing in DTR, and the PWM waveform output 1 output timing in CYLR. Also, if necessary, interrupt requests can be sent to the CPU at the 0/1 output timing by making a setting in the timer interrupt enable register (TIER). 5. Set the corresponding bit to 1 in the timer start register (TSTR) to start the free-running counter (TCNT) for the relevant channel. PWM waveform output Figure 11.59 Sample Setup Procedure for PWM Timer Operation (Channels 3 to 5) Rev. 5.00 Feb. 24, 2010 Page 311 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) Sample Setup Procedure for PWM Timer Operation (Channels 6 and 7): An example of the setup procedure for PWM timer operation (channels 6 and 7) is shown in figure 11.60. Start Select counter clock 1 Set port-ATU-II connection 2 Set CYLR, BFR, DTR 3 Start count 4 PWM waveform output 1. Set the first-stage counter clock ' in prescaler register 2 and 3 (PSCR2, PSCR3), and select the second-stage counter clock " with the CKSEL bit in the timer control register (TCR6A, TCR6B, TCR7A, TCR7B). 2. Set the port B control register L (PBCRL) corresponding to the waveform output port to ATU PWM output. 3. Set PWM waveform output 1 output timing in the cycle register (CYLR6A to CYLR6D, CYLR7A to CYLR7D), and set the PWM waveform output 0 output timing in the buffer register (BFR6A to BFR6D, BFR7A to BFR7D) and duty register (DTR6A to DTR6D, DTR7A to DTR7D). If necessary, an interrupt request can be sent to the CPU on a compare-match between the CYLR value and the freerunning counter (TCNT) value by making the appropriate setting in the interrupt enable register (TIERE). In addition, setting the DMAC allows DMAC activation to be performed. 4. Set the corresponding bit to 1 in the timer start register (TSTR) to start the TCNT counter for the relevant channel. Notes: 1. Do not make a setting in DTR after the counter is started. Use BFR to make a DTR setting. 2. 0% duty is specified by setting H'0000 in the duty register (DTR), and 100% duty is specified by setting buffer register (BFR) = cycle register (CYLR). Do not set BFR > CYLR. Figure 11.60 Sample Setup Procedure for PWM Timer Operation (Channels 6 and 7) Rev. 5.00 Feb. 24, 2010 Page 312 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) Sample Setup Procedure for Event Counter Operation: An example of the setup procedure for event counter operation is shown in figure 11.61. Start Set number of events 1 Set port-ATU-II connection 2 Select counter clock 3 Start event input 4 1. Set the number of events to be counted in a general register (GR9A to GR9D). Also, if necessary, an interrupt request can be sent to the CPU upon compare-match by making a setting in the timer interrupt enable register (TIER). 2. Set the port control register, corresponding to the port for signal input to the event counter, to ATU event counter input. 3. Select the event counter count edge with the EGSEL bits in the channel 9 timer control register (TCR9A to TCR9C). 4. Input a signal to the event counter input pin. Event counter operation Figure 11.61 Sample Setup Procedure for Event Counter Operation Sample Setup Procedure for Channel 3 Input Capture Triggered by Channel 9 Compare-Match: An example of the setup procedure for compare-match signal transmission is shown in figure 11.62. Start Set port-ATU-II commection 1 Set input capture 2 Select compare-match 3 Start counter 4 Start event input 5 1. Set the port control register, corresponding to the port for signal input to the event counter, to ATU event counter input. 2. Set the channel 3 timer I/O control register (TIOR3A, TIOR3B), and select the input capture disable setting for the general registers (GR3A to GR3D). Input from pins TIO3A to TIO3D is masked. 3. Select the event counter count edge with the EGSEL bits in the channel 9 timer control register (TCR9A, TCR9B), and set the TRG3xEN bit to 1. Set the timing for capture in the general register (GR9A to GR9D). 4. Set bit STR3 to 1 in the timer start register (TSTR) to start the channel 3 free-running counter (TCNT3). 5. Input a signal to the event counter input pin. Note: An interrupt request can be sent to the CPU upon channel 9 compare-match by making a setting in the timer interrupt enable register (TIER), but an interrupt request cannot be sent to the CPU upon channel 3 input capture. Input capture operation Figure 11.62 Sample Setup Procedure for Compare-Match Signal Transmission Rev. 5.00 Feb. 24, 2010 Page 313 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) Sample Setup Procedure for Channel 10 Missing-Teeth Detection: An example of the setup procedure for missingteeth detection is shown in figure 11.63. Start Set port-ATU-II connection 1 Select counter clock 2 Set compare-match 3 Set missing-teeth timing 4 Start counter 5 1. Set port B control register H (PBCRH) or port L control register L (PLCRL), corresponding to the port for input of the external signal (missing-teeth signal), to ATU edge input (TI10). 2. Set 1st-stage counter clock ' in prescaler register 4 (PSCR4). Set the external input (TI10) cycle multiplication factor with the PIM bits in timer I/O control register 10 (TIOR10), and enable reload register 10C (RLD10C) updating with the RLDEN bit. Select the external input edge type with the CKEG bits in timer control register 10 (TCR10). 3. Set general register 10G (GR10G) to the compare-match function with bit IO10G in TIOR10. Also, an interrupt request can be sent to the CPU upon compare-match by making a setting in interrupt enable register 10 (TIER10). 4. Set the timing for compare-match generation in GR10G according to the multiplication factor and number of missingteeths in the missing-teeth interval set in (1). 5. Set the corresponding bit to 1 in timer start register 1 (TSTR1) to start the channel 10 count. A compare-match occurs when the values in free-running counter 10G (TCNT10G) and GR10G match. Interrupt requests to CPU Note: The TCNT10G counter clock is generated according to the external input edge interval and multiplication factor selected in (1), and the counter is cleared to H'0000 by an external input edge. Figure 11.63 Sample Setup Procedure for Missing-Teeth Detection Rev. 5.00 Feb. 24, 2010 Page 314 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) 11.7 Usage Notes Note that the kinds of operation and contention described below occur during ATU operation. Contention between TCNT Write and Clearing by Compare-Match: With channel 3 to 7 free-running counters (TCNT3 to TCNT5, TCNT6A to TCNT6D, TCNT7A to TCNT7D), if a compare-match occurs in the T2 state of a CPU write cycle when counter clearing by compare-match has been set, or when PWM mode is used, the write to TCNT has priority and TCNT clearing is not performed. The compare-match remains valid, and writing of 1 to the interrupt status flag and waveform output to an external destination are performed in the same way as for a normal compare-match. The timing in this case is shown in figure 11.64. T1 T2 P Address TCNT address Internal write signal Compare-match signal Counter clear signal TCNT CPU write value Interrupt status flag External output signal (1 output) Figure 11.64 Contention between TCNT Write and Clear Rev. 5.00 Feb. 24, 2010 Page 315 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) Contention between TCNT Write and Increment: If a write to a channel 0 to 11 free-running counter (TCNT0, TCNT1A, TCNT1B, TCNT2A, TCNT2B, TCNT3 to TCNT5, TCNT6A to TCNT6D, TCNT7A to TCNT7D, TCNT10A to TCNT10H, TCNT11), down-counter (DCNT8A to DCNT8P), or event counter 9 (ECNT9A to ECNT9F) is performed while that counter is counting up or down, the write to the counter has priority and the counter is not incremented or decremented. The timing in this case is shown in figure 11.65. In this example, the CPU writes H'5555 at the point at which TCNT is to be incremented from H'1001 to H'1002. T1 T2 P TCNT input clock Address TCNT address Internal write signal TCNT 1001 5555 (CPU write value) 5556 Figure 11.65 Contention between TCNT Write and Increment Rev. 5.00 Feb. 24, 2010 Page 316 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) Contention between TCNT Write and Counter Clearing by Overflow: With channel 0 to 5 and 11 free-running counters (TCNT0, TCNT1A, TCNT1B, TCNT2A, TCNT2B, TCNT3 to TCNT5, TCNT11), if overflow occurs in the T2 state of a CPU write cycle, the write to TCNT has priority and TCNT is not cleared. Writing of 1 to the interrupt status flag (OVF) due to the overflow is performed in the same way as for normal overflow. The timing in this case is shown in figure 11.66. In this example, H'5555 is written at the point at which TCNT overflows. T1 T2 P TCNT input clock Address TCNT address Internal write signal Overflow signal TCNT FFFF 5555 (CPU write value) 5556 Interrupt status flag (OVF) Figure 11.66 Contention between TCNT Write and Overflow Rev. 5.00 Feb. 24, 2010 Page 317 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) Contention between Interrupt Status Flag Setting by Interrupt Generation and Clearing: If an event such as input capture/compare-match or overflow/underflow occurs in the T2 state of an interrupt status flag 0 write cycle by the CPU, clearing by the 0 write has priority and the interrupt status flag is cleared. The timing in this case is shown in figure 11.67. TSR write cycle T1 T2 P Address TSR address 0 written to TSR Internal write signal TCNT GR N N+1 N Compare-match signal Interrupt status flag IMF Figure 11.67 Contention between Interrupt Status Flag Setting by Compare-Match and Clearing Contention between DTR Write and BFR Value transfer by Buffer Function: In channels 6 and 7, if there is contention between transfer of the buffer register (BFR) value to the corresponding duty register (DTR) due to a cycle register (CYLR) compare-match, and a write to DTR by the CPU, the CPU write value is written to DTR. Figure 11.68 shows an example in which contention arises when the BFR value is H'AAAA and the value to be written to DTR is H'5555. P Address Internal write signal DTR address H'5555 written to DTR Compare-match signal BFR DTR H'AAAA H'5555 Figure 11.68 Contention between DTR Write and BFR Value Transfer by Buffer Function Rev. 5.00 Feb. 24, 2010 Page 318 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) Contention between Interrupt Status Flag Clearing by DMAC and Setting by Input Capture/Compare-Match: If a clear request signal is generated by the DMAC when the interrupt status flag (ICF0A to ICF0D, CMF6A to CMF6D, CMF7A to CMF7D) is set by input capture (ICR0A to ICR0D) or compare-match (CYLR6A to CYLR6D, CYLR7A to CYLR7D), clearing by the DMAC has priority and the interrupt status flag is not set. The timing in this case is shown in figure 11.69. P DMAC clear request signal Interrupt status flag clear signal Input capture/ compare-match signal Interrupt status flag ICF0A to ICF0D, CMF6A to CMF6D, CMF7A to CMF7D Figure 11.69 Contention between Interrupt Status Flag Clearing by DMAC and Setting by Input Capture/Compare-Match Halting of a Down-Counter by the CPU: A down-counter (DCNT) can be halted by writing H'0000 to it. The CPU cannot write 0 directly to the down-count start register (DSTR); instead, by setting DCNT to H'0000, the corresponding DSTR bit is cleared to 0 and the count is stopped. However, the OSF bit in the timer status register (TSR) is set when DCNT underflows. Note that when H'0000 is written to DCNT, the corresponding DSTR bit is not cleared to 0 immediately; it is cleared to 0, and the down-counter is stopped, when underflow occurs following the H'0000 write. The timing in this case is shown in figure 11.70. P DCNT input clock DCNT Internal write signal N H'0000 H'0000 H'0000 written to DCNT DSTR TSR Port output (one-shot pulse) Figure 11.70 Halting of a Down-Counter by the CPU Rev. 5.00 Feb. 24, 2010 Page 319 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) Input Capture Operation when Free-Running Counter is Halted: In channels 0 to 5, channel 10, or channel 11, if input capture setting is performed and a trigger signal is input from the input pin, the TCNT value will be transferred to the corresponding general register (GR) or input capture register (ICR) irrespective of whether the free-running counter (TCNT) is running or halted, and the IMF or ICF bit will be set in the timer status register (TSR). The timing in this case is shown in figure 11.71. P Timer status register TSR Internal input capture signal TCNT GR (ICR) N N Interrupt status flag IMF (ICF) Figure 11.71 Input Capture Operation before Free-Running Counter is Started Rev. 5.00 Feb. 24, 2010 Page 320 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) Contention between DCNT Write and Counter Clearing by Underflow: If an underflow occurs in the T2 state of the channel 8 down-counter (DCNT8A to DCNT8P) write cycle by the CPU and the DCNT is stopped, the retention of the H'0000 value has priority and the write to the DCNT by the CPU is not performed. Setting the status flag (OSF) to 1 at the underflow timing is performed in the same way as for a normal underflow. The timing in this case is shown in figure 11.72. In this example, a write of H'5555 to DCNT is attempted at the same time as DCNT underflows. Note: In the SH7055, a write to DCNT from the CPU is not attempted, but retention of H'0000 takes precedence. Note that its operation is different. T1 T2 P DCNT input clock Address DCNT address Write data 5555 Internal write signal Underflow signal H'5555 is written due to the DCNT write priority DCNT 0001 0000 5555 Interrupt status flag (OSF) Figure 11.72 Contention between DCNT Write and Underflow Rev. 5.00 Feb. 24, 2010 Page 321 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) Contention between DSTR Bit Setting by CPU and Clearing by Underflow: If underflow occurs in the T2 state of a down-counter start register (DSTR) "1" write cycle by the CPU, clearing to 0 by the underflow has priority, and the corresponding bit of DSTR is not set to 1. The timing in this case is shown in figure 11.73. STR write cycle T1 T2 P Address DSTR address 1 written to DSTR Internal write signal DCNT 0001 0000 0000 Underflow signal Down-count start register Figure 11.73 Contention between DSTR Bit Setting by CPU and Clearing by Underflow Timing of Prescaler Register (PSCR), Timer Control Register (TCR), and Timer Mode Register (TMDR) Setting: Settings in the prescaler register (PSCR), timer control register (TCR), and timer mode register (TMDR) should be made before the counter is started. Operation is not guaranteed if these registers are modified while the counter is running. Also, the counter must not be started until Po has been input 32 times after setting PSCR1 to PSCR4. Interrupt Status Flag Clearing Procedure: When an interrupt status flag is cleared to 0 by the CPU, it must first be read before 0 is written to it. Correct operation cannot be guaranteed if 0 is written without first reading the flag. Setting H'0000 in Free-Running Counters 6A to 6D, 7A to 7D (TCNT6A to TCNT6D, TCNT7A to TCNT7D): If H'0000 is written to a channel 6 and 7 free-running counter (TCNT6A to TCNT6D, TCNT7A to TCNT7D), and the counter is started, the interval up to the first compare-match with the cycle register (CYLR) and duty register (DTR) will be a maximum of one TCNT input clock cycle longer than the set value. With subsequent compare-matches, the correct waveform will be output for the CYLR and DTR values. Register Values when a Free-Running Counter (TCNT) Halts: If the timer start register (TSTR) value is set to 0 during counter operation, only incrementing of the corresponding free-running counter (TCNT) is stopped, and neither the freerunning counter (TCNT) nor any other ATU registers are initialized. The external output value at the time TSTR is cleared to 0 will continue to be output. TCNT0 Writing and Interval Timer Operation: If the CPU program writes 1 to a bit in free-running counter 0 (TCNT0) corresponding to a bit set to 1 in the interval interrupt request register (ITVRR) when that TCNT0 bit is 0, TCNT0 bit 6, 7, 8, 9, 10, 11, 12, or 13 will be detected as having changed from 0 to 1, and an interrupt request will be sent to INTC and A/D sampling will be started. While the count is halted with the STR0 bit cleared to 0 in timer start register 1 (TSTR1), the bit transition from 0 to 1 will still be detected. Rev. 5.00 Feb. 24, 2010 Page 322 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) Automatic TSR Clearing by DMAC Activation by the ATU: Automatic clearing of TSR is performed after completion of the transfer when the DMAC is in burst mode, and each time the DMAC returns the bus in cycle steal mode. Interrupt Status Flag Setting/Resetting: With TSR, a 0 write to a bit is possible even if overlapping events occur for the same bit before writing 0 after reading 1 to clear that bit. (The duplicate events are not accepted.) External Output Values in Software Standby Mode and Pin State after Software Standby Mode Release: In software standby mode, the ATU registers and external output values are initialized. The pin state is high impedance. Since the settings of the pin function controller (PFC) are initialized, the PFC must be set again to use the function of the ATU-II external pins after software standby release. Contention between TCNT Clearing from Channel 10 and TCNT Overflow: When a channel 1 or 2 free-running counter (TCNT1A, TCNT1B, TCNT2A, TCNT2B) overflows, it is cleared to H'0000. If a clear signal from the channel 10 correction counter clear register (TCCLR) is input at the same time, setting 1 to the overflow interrupt status flag (OVF) due to the overflow is still performed in the same way as for a normal overflow. Contention between Channel 10 Reload Register Transfer Timing and Write: If there is contention between a multiplied-output transfer from the input capture register (ICR10A) to the channel 10 reload register (RLDR10C), and the timing of a CPU write to that register, the CPU write has priority and the multiplied output is ignored. Contention between Channel 10 Reload Timing and Write to TCNT10C: If there is contention between a multipliedoutput transfer from the input capture register (ICR10A) to the channel 10 reload register (RLDR10C), and a CPU write to the reload counter (TCNT10C), the CPU write has priority and the multiplied output is ignored. ATU Pin Setting: Since input capture or count operation may be occurred when a port is set to the ATU pin function, the following points must be noted. When using a port for input capture input, the corresponding TIOR register must be in the input capture disabled state when the port is set. Regarding channel 10 TI10 input, TCR10 must be in the TI10 input disabled state when the port is set. When using a port for external clock input, the STR bit for the corresponding channel must be in the count operation disabled state when the port is set. When using a port for event input, the corresponding TCR register must be in the count operation disabled state when the port is set. Regarding TCLKB and TI10 input, although input is assigned to a number of pins, when using TCLKB and TI10 input, only one pin should be enabled. Writing to ROM Area Immediately after ATU Register Write: If a write cycle for a ROM address for which address bit 11 = 0 and address bit 12 = 1 (H'00001000 to H'000017FF, H'00003000 to H'000037FF, H'00005000 to H'000057FF, ..., H'0007F000 to H'0007F7FF, ..., H'000FF000 to H'000FF7FF) occurs immediately after an ATU register write cycle, the value, or part of the value, written to ROM will be written to the ATU register. The following measures should be taken to prevent this. * Do not perform a CPU write to a ROM address immediately after an ATU register write cycle. For example, an instruction arrangement in which an MOV instruction that writes to the ATU is located at an even-word address (4n address), and is immediately followed by an MOV instruction that writes to a ROM area, will meet the bug conditions. * Do not perform an AUD write to any of the above ROM addresses immediately after an ATU register write cycle. For example, in the case of a write to overlap RAM when using the RAM emulation function, the write should be performed to the on-chip RAM area address, not the overlapping ROM area address. * Do not perform a DMAC write to an ATU register when a ROM address write operation occurs. Rev. 5.00 Feb. 24, 2010 Page 323 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) 11.8 ATU-II Registers and Pins Table 11.4 ATU-II Registers and Pins Channel Register Name*1 Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Channel 8 Channel 9 Channel 10 Channel 11 TSTR (3) TSTR1 TSTR1 TSTR1 TSTR1 TSTR1 TSTR1 TSTR2 TSTR2 - - TSTR1 TSTR3 PSCR (4) PSCR1 PSCR1 PSCR1 PSCR1 PSCR1 PSCR1 PSCR2 PSCR3 PSCR1 - PSCR4 PSCR1 TCNT (25) TCNT0H, TCNT0L TCNT1A, TCNT1B TCNT2A, TCNT2B TCNT3 TCNT4 TCNT5 TCNT6A to TCNT7A to - TCNT6D TCNT7D - TCNT10AH, TCNT11 DCNT (16) - - - - - - - - DCNT8A to - DCNT8P ECNT (6) - - - - - - - - TCR (17) - TCR1A, TCR1B TCR2A, TCR2B TCR3 TCR4 TCR5 TCR6A, TCR6B TIOR (17) TIOR0 TIOR1A to TIOR2A to TIOR3A, TIOR1D TIOR2D TIOR3B TIOR4A, TIOR4B TIOR5A, TIOR5B TSR (12) TSR0 TSR1A, TSR1B TSR2A, TSR2B TSR3 TSR3 TIER (12) TIER0 TIER1A, TIER1B TIER2A, TIER2B TIER3 ITVRR (3) ITVRR1, - ITVRR2A, ITVRR2B - GR (37) - ICR (5) TCNT10AL, TCNT10B to TCNT10H - - - ECNT9A to - ECNT9F - TCR7A, TCR7B TCR8 TCR9A to TCR10 TCR9C TCR11 - - - - TIOR10 TIOR11 TSR3 TSR6 TSR7 TSR8 TSR9 TSR10 TSR11 TIER3 TIER3 TIER6 TIER7 TIER8 TIER9 TIER10 TIER11 - - - - - - - - - GR2A to GR2H GR3A to GR3D GR4A to GR4D GR5A to GR5D - - - GR9A to GR9F GR10G GR11A, GR11B ICR0AH, - ICR0AL to ICR0DH, ICR0DL - - - - - - - - ICR10AH, - ICR10AL OCR (11) - OCR1 OCR2A to - OCR2H - - - - - - OCR10AH, - OCR10AL, OCR10B OSBR (2) - OSBR1 OSBR2 - - - - - - - - GR1A to GR1H - TRGMDR (1) - TRGMDR - - - - - - - - - - TMDR (1) - - - TMDR TMDR TMDR - - - - - - CYLR (8) - - - - - - CYLR6A to CYLR7A to - CYLR6D CYLR7D - - - BFR (8) - - - - - - BFR6A to BFR6D - - - - DTR (8) - - - - - - DTR6A to DTR7A to - DTR6D DTR7D - - - PMDR (1) - - - - - - PMDR - - - - - RLDR (1) - - - - - - - - RLDR - - - TCNR (1) - - - - - - - - TCNR - - - OTR (1) - - - - - - - - OTR - - - DSTR (1) - - - - - - - - DSTR - - - RLDENR (1) - - - - - - - - RLDENR - - - RLD (1) - - - - - - - - - - RLD10C - NCR (1) - - - - - - - - - - NCR10 - Rev. 5.00 Feb. 24, 2010 Page 324 of 950 REJ09B0177-0500 BFR7A to BFR7D 11. Advanced Timer Unit-II (ATU-II) Channel Register Name*1 TCCLR (1) 2 Pins* Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Channel 8 Channel 9 Channel 10 Channel 11 - - - - - - - - - - TCCLR10 - TI0A to D TIO1A to H, TCLKA, TCLKB TIO2A to H, TCLKA, TCLKB TIO3A to D, TCLKA, TCLKB TIO4A to D, TCLKA, TCLKB TIO5A to D, TCLKA, TCLKB TO6A to D TO7A to D TO8A to P TI9A to F T10 TIO11A, TIO11B, TCLKA, TCLKB Notes: 1. Figures in parentheses show the number of registers. A 32-bit register is shown as a single register. 2. Pin functions should be set as described in section 22, Pin Function Controller (PFC). Rev. 5.00 Feb. 24, 2010 Page 325 of 950 REJ09B0177-0500 11. Advanced Timer Unit-II (ATU-II) Rev. 5.00 Feb. 24, 2010 Page 326 of 950 REJ09B0177-0500 12. Advanced Pulse Controller (APC) Section 12 Advanced Pulse Controller (APC) 12.1 Overview This LSI has an on-chip advanced pulse controller (APC) that can generate a maximum of eight pulse outputs, using the advanced timer unit II (ATU-II) as the time base. 12.1.1 Features The features of the APC are summarized below. * Maximum eight pulse outputs The pulse output pins can be selected from among eight pins. Multiple settings are possible. * Output trigger provided by advanced timer unit II (ATU-II) channel 11 Pulse 0 output and 1 output is performed using the compare-match signal generated by the ATU-II channel 11 compare-match register as the trigger. Rev. 5.00 Feb. 24, 2010 Page 327 of 950 REJ09B0177-0500 12. Advanced Pulse Controller (APC) 12.1.2 Block Diagram Figure 12.1 shows a block diagram of the advanced pulse controller. ATU-II Internal/external clock TCNT11 GR11A Compare GR11B Comparematch signal Comparematch signal Set Bit 7 Reset Bit 15 PULS7 Set POPCR (pulse output port setting register) Bit 6 Reset Bit 14 PULS6 Set Bit 5 Reset Bit 13 PULS5 Set Bit 4 Reset Bit 12 PULS4 Set Bit 3 Reset Bit 11 PULS3 Set Bit 2 Reset Bit 10 PULS2 Set Bit 1 Reset Bit 9 PULS1 Set Bit 0 Legend: POPCR: Pulse output port control register Reset Bit 8 APC Figure 12.1 Advanced Pulse Controller Block Diagram Rev. 5.00 Feb. 24, 2010 Page 328 of 950 REJ09B0177-0500 PULS0 12. Advanced Pulse Controller (APC) 12.1.3 Pin Configuration Table 12.1 summarizes the advanced pulse controller's output pins. Table 12.1 Advanced Pulse Controller Pins Pin Name I/O Function PULS0 Output APC pulse output 0 PULS1 Output APC pulse output 1 PULS2 Output APC pulse output 2 PULS3 Output APC pulse output 3 PULS4 Output APC pulse output 4 PULS5 Output APC pulse output 5 PULS6 Output APC pulse output 6 PULS7 Output APC pulse output 7 12.1.4 Register Configuration Table 12.2 summarizes the advanced pulse controller's register. Table 12.2 Advanced Pulse Controller Register Name Abbreviation R/W Initial Value Address Access Size Pulse output port control register POPCR R/W H'0000 H'FFFFF700 8, 16 12.2 Register Descriptions 12.2.1 Pulse Output Port Control Register (POPCR) The pulse output port control register (POPCR) is a 16-bit readable/writable register. POPCR is initialized to H'0000 by a power-on reset, in hardware standby mode, and in software standby mode. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 PULS7 ROE PULS6 ROE PULS5 ROE PULS4 ROE PULS3 ROE PULS2 ROE PULS1 ROE PULS0 ROE 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PULS7 SOE PULS6 SOE PULS5 SOE PULS4 SOE PULS3 SOE PULS2 SOE PULS1 SOE PULS0 SOE 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Rev. 5.00 Feb. 24, 2010 Page 329 of 950 REJ09B0177-0500 12. Advanced Pulse Controller (APC) * Bits 15 to 8--PULS7 to PULS0 Reset Output Enable (PULS7ROE to PULS0ROE): These bits enable or disable 0 output to the APC pulse output pins (PULS7 to PULS0) bit by bit. Bits 15 to 8: PULS7ROE to PULS0ROE Description 0 0 output to APC pulse output pin (PULS7--PULS0) is disabled 1 0 output to APC pulse output pin (PULS7--PULS0) is enabled (Initial value) When one of these bits is set to 1, 0 is output from the corresponding pin on a compare-match between the GR11B and TCNT11 values. * Bits 7 to 0--PULS7 to PULS0 Set Output Enable (PULS7SOE to PULS0SOE): These bits enable or disable 1 output to the APC pulse output pins (PULS7 to PULS0) bit by bit. Bits 7 to 0: PULS7SOE to PULS0SOE Description 0 1 output to APC pulse output pin (PULS7--PULS0) is disabled 1 1 output to APC pulse output pin (PULS7--PULS0) is enabled (Initial value) When one of these bits is set to 1, 1 is output from the corresponding pin on a compare-match between the GR11A and TCNT11 values. 12.3 Operation 12.3.1 Overview APC pulse output is enabled by designating multiplex pins for APC pulse output with the pin function controller (PFC), and setting the corresponding bits to 1 in the pulse output port control register (POPCR). When general register 11A (GR11A) in the advanced timer unit II (ATU-II) subsequently generates a compare-match signal, 1 is output from the pins set to 1 by bits 7 to 0 in POPCR. When general register 11B (GR11B) generates a compare-match signal, 0 is output from the pins set to 1 by bits 15 to 8 in POPCR. 0 is output from the output-enabled state until the first compare-match occurs. The advanced pulse controller output operation is shown in figure 12.2. Rev. 5.00 Feb. 24, 2010 Page 330 of 950 REJ09B0177-0500 12. Advanced Pulse Controller (APC) CR Upper 8 bits of POPCR Compare-match signal GR11B Reset signal Port function selection APC output pins (PULS0 to PULS7) Set signal Compare-match signal GR11A Lower 8 bits of POPCR Figure 12.2 Advanced Pulse Controller Output Operation 12.3.2 Advanced Pulse Controller Output Operation Example of Setting Procedure for Advanced Pulse Controller Output Operation: Figure 12.3 shows an example of the setting procedure for advanced pulse controller output operation. 1. Set general registers GR11A and GR11B as output compare registers with the timer I/O control register (TIOR). 2. Set the pulse rise point with GR11A and the pulse fall point with GR11B. 3. Select the timer counter 11 (TCNT11) counter clock with the timer prescale register (PSCR). TCNT11 can only be cleared by an overflow. 4. Enable the respective interrupts with the timer interrupt enable register (TIER). 5. Set the pins for 1 output and 0 output with POPCR. 6. Set the control register for the port to be used by the APC to the APC output pin function. 7. Set the STR bit to 1 in the timer start register (TSTR) to start timer counter 11 (TCNT11). 8. Each time a compare-match interrupt is generated, update the GR value and set the next pulse output time. 9. Each time a compare-match interrupt is generated, update the POPCR value and set the next pin for pulse output. Rev. 5.00 Feb. 24, 2010 Page 331 of 950 REJ09B0177-0500 12. Advanced Pulse Controller (APC) APC output operation GR function selection 1 GR setting 2 Count operation setting 3 Interrupt request setting 4 APC setting Rise/fall port setting 5 Port setting Port output setting 6 Start count 7 ATU-II settings ATU-II setting Compare-match? No Yes ATU-II setting APC setting GR setting 8 Rise/fall port setting 9 Figure 12.3 Example of Setting Procedure for Advanced Pulse Controller Output Operation Rev. 5.00 Feb. 24, 2010 Page 332 of 950 REJ09B0177-0500 12. Advanced Pulse Controller (APC) Example of Advanced Pulse Controller Output Operation: Figure 12.4 shows an example of advanced pulse controller output operation. 1. Set ATU-II registers GR11A and GR11B (to be used for output trigger generation) as output compare registers. Set the rise point in GR11A and the fall point in GR11B, and enable the respective compare-match interrupts. 2. Write H'0101 to POPCR. 3. Start the TCNT11 count, when a GR11A compare-match occurs, 1 is output from the PULS0 pin. When a GR11B compare-match occurs, 0 is output from the PULS0 pin. 4. Pulse output widths and output pins can be continually changed by successively rewriting GR11A, GR11B, and POPCR in response to compare-match interrupts. 5. By setting POPCR to a value such as H'E0E0, pulses can be output from up to eight pins in response to a single compare-match. Cleared on overflow TCNT value Rewritten Rewritten Rewritten Rewritten Rewritten Rewritten Rewritten Rewritten Rewritten Rewritten GR11B GR11A H'0000 POPCR 0101 0202 0404 0808 1010 E0E0 PULS0 PULS1 PULS2 PULS3 PULS4 PULS5 PULS6 PULS7 Figure 12.4 Example of Advanced Pulse Controller Output Operation Rev. 5.00 Feb. 24, 2010 Page 333 of 950 REJ09B0177-0500 12. Advanced Pulse Controller (APC) 12.4 Usage Notes Contention between Compare-Match Signals: If the same value is set for both GR11A and GR11B, and 0 output and 1 output are both enabled for the same pin by the POPCR settings, 0 output has priority on pins PULS0 to PULS7 when compare-matches occur. TCNT value H'FFFF H'8000 GR11A H'8000 GR11B H'8000 POPCR H'0101 PULS0 pin Pin output is 0 Figure 12.5 Example of Compare-Match Contention Rev. 5.00 Feb. 24, 2010 Page 334 of 950 REJ09B0177-0500 13. Watchdog Timer (WDT) Section 13 Watchdog Timer (WDT) 13.1 Overview The watchdog timer (WDT) is a 1-channel timer for monitoring system operations. If a system encounters a problem (crashes, for example) and the timer counter overflows without being rewritten correctly by the CPU, an overflow signal (WDTOVF) is output externally. The WDT can simultaneously generate an internal reset signal for the entire chip. When the watchdog function is not needed, the WDT can be used as an interval timer. In the interval timer operation, an interval timer interrupt is generated at each counter overflow. 13.1.1 Features The WDT has the following features: * Works in watchdog timer mode or interval timer mode * Outputs WDTOVF in watchdog timer mode When the counter overflows in watchdog timer mode, overflow signal WDTOVF is output externally. It is possible to select whether to reset the chip internally when this happens. Either the power-on reset or manual reset signal can be selected as the internal reset signal. * Generates interrupts in interval timer mode When the counter overflows, it generates an interval timer interrupt. * Works with eight counter input clocks Rev. 5.00 Feb. 24, 2010 Page 335 of 950 REJ09B0177-0500 13. Watchdog Timer (WDT) 13.1.2 Block Diagram Figure 13.1 is the block diagram of the WDT. Interrupt control Clock WDTOVF Clock select Reset control Internal reset signal* TCNT RSTCSR /2 /64 /128 /256 /512 /1024 /4096 /8192 Internal clock sources TCSR Bus interface Module bus Internal data bus Overflow ITI (interrupt signal) WDT Legend: TCSR: Timer control/status register TCNT: Timer counter RSTCSR: Reset control/status register Note: * The internal reset signal can be generated by making a register setting. Figure 13.1 WDT Block Diagram 13.1.3 Pin Configuration Table 13.1 shows the pin configuration. Table 13.1 Pin Configuration Pin Abbreviation I/O Function Watchdog timer overflow WDTOVF O Outputs the counter overflow signal in watchdog timer mode Rev. 5.00 Feb. 24, 2010 Page 336 of 950 REJ09B0177-0500 13. Watchdog Timer (WDT) 13.1.4 Register Configuration Table 13.2 summarizes the three WDT registers. They are used to select the clock, switch the WDT mode, and control the reset signal. Table 13.2 WDT Registers Address Name Abbreviation R/W Initial Value Write* Read*2 Timer control/status register TCSR R/(W)*3 H'18 H'FFFFEC10 H'FFFFEC10 Timer counter TCNT R/W H'00 Reset control/status register RSTCSR R/(W)* 3 1 H'FFFFEC11 H'1F H'FFFFEC12 H'FFFFEC13 Notes: In register access, four cycles are required for both byte access and word access. 1. Write by word transfer. These registers cannot be written in bytes or longwords. 2. Read by byte transfer. These registers cannot be read in words or longwords. 3. Only 0 can be written to bit 7 to clear the flag. 13.2 Register Descriptions 13.2.1 Timer Counter (TCNT) TCNT is an 8-bit readable/writable upcounter. (TCNT differs from other registers in that it is more difficult to write to. See section 13.2.4, Register Access, for details.) When the timer enable bit (TME) in the timer control/status register (TCSR) is set to 1, the watchdog timer counter starts counting pulses of an internal clock selected by clock select bits 2 to 0 (CKS2 to CKS0) in TCSR. When the value of TCNT overflows (changes from H'FF to H'00), a watchdog timer overflow signal (WDTOVF) or interval timer interrupt (ITI) is generated, depending on the mode selected in the WT/IT bit in TCSR. TCNT is initialized to H'00 by a power-on reset, in hardware and software standby modes, and when the TME bit is cleared to 0. Bit: Initial value: R/W: 13.2.2 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Timer Control/Status Register (TCSR) The timer control/status register (TCSR) is an 8-bit readable/writable register. (TCSR differs from other registers in that it is more difficult to write to. See section 13.2.4, Register Access, for details.) TCSR performs selection of the timer counter (TCNT) input clock and mode. TCSR is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. Bit: Initial value: R/W: Note: * 7 6 5 4 3 2 1 0 OVF WT/IT TME - - CKS2 CKS1 CKS0 0 0 0 1 1 0 0 0 R/(W)* R/W R/W R R R/W R/W R/W The only operation permitted on the OVF bit is a write of 0 after reading 1. Rev. 5.00 Feb. 24, 2010 Page 337 of 950 REJ09B0177-0500 13. Watchdog Timer (WDT) * Bit 7--Overflow Flag (OVF): Indicates that TCNT has overflowed from H'FF to H'00 in interval timer mode. This flag is not set in the watchdog timer mode. Bit 7: OVF Description 0 No overflow of TCNT in interval timer mode (Initial value) [Clearing condition] When 0 is written to OVF after reading OVF 1 TCNT overflow in interval timer mode * Bit 6--Timer Mode Select (WT/IT): Selects whether to use the WDT as a watchdog timer or interval timer. When TCNT overflows, the WDT either generates an interval timer interrupt (ITI) or generates a WDTOVF signal, depending on the mode selected. Bit 6: WT/IT Description 0 Interval timer mode: interval timer interrupt (ITI) request to the CPU when TCNT overflows (Initial value) 1 Watchdog timer mode: WDTOVF signal output externally when TCNT overflows. (Section 13.2.3, Reset Control/Status Register (RSTCSR), describes in detail what happens when TCNT overflows in watchdog timer mode.) * Bit 5--Timer Enable (TME): Enables or disables the timer. Bit 5: TME Description 0 Timer disabled: TCNT is initialized to H'00 and count-up stops 1 Timer enabled: TCNT starts counting. A WDTOVF signal or interrupt is generated when TCNT overflows. (Initial value) * Bits 4 and 3--Reserved: These bits are always read as 1. The write value should always be 1. * Bits 2 to 0--Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock sources for input to TCNT. The clock signals are obtained by dividing the frequency of the system clock (). Description Bit 2: CKS2 Bit 1: CKS1 Bit 0: CKS0 Clock Source 0 0 0 /2 0 0 1 /64 204.8 s 0 1 0 /128 409.6 s 0 1 1 /256 0.8 ms 1 0 0 /512 1.6 ms 1 0 1 /1024 3.3 ms 1 1 0 /4096 13.1 ms 1 1 /8192 26.2 ms 1 Note: * (Initial value) Overflow Interval* ( = 80 MHz) 6.4 s The overflow interval listed is the time from when the TCNT begins counting at H'00 until an overflow occurs. Rev. 5.00 Feb. 24, 2010 Page 338 of 950 REJ09B0177-0500 13. Watchdog Timer (WDT) 13.2.3 Reset Control/Status Register (RSTCSR) RSTCSR is an 8-bit readable/writable register. (RSTCSR differs from other registers in that it is more difficult to write. See section 13.2.4, Register Access, for details.) It controls output of the internal reset signal generated by timer counter (TCNT) overflow. RSTCR is initialized to H'1F by input of a reset signal from the RES pin, but is not initialized by the internal reset signal generated by overflow of the WDT. It is initialized to H'1F in hardware standby mode and software standby mode. Bit: 7 6 5 4 3 2 1 0 WOVF RSTE RSTS - - - - - Initial value: R/W: Note: * 0 0 0 1 1 1 1 1 R/(W)* R/W R/W R R R R R Only 0 can be written to bit 7 to clear the flag. * Bit 7--Watchdog Timer Overflow Flag (WOVF): Indicates that TCNT has overflowed (H'FF to H'00) in watchdog timer mode. This flag is not set in interval timer mode. Bit 7: WOVF 0 Description No TCNT overflow in watchdog timer mode (Initial value) [Clearing condition] When 0 is written to WOVF after reading WOVF 1 Set by TCNT overflow in watchdog timer mode * Bit 6--Reset Enable (RSTE): Selects whether to reset the chip internally if TCNT overflows in watchdog timer mode. Bit 6: RSTE Description 0 Not reset when TCNT overflows (Initial value) LSI not reset internally, but TCNT and TCSR reset within WDT. 1 Reset when TCNT overflows * Bit 5--Reset Select (RSTS): Selects the kind of internal reset to be generated when TCNT overflows in watchdog timer mode. Bit 5: RSTS Description 0 Power-on reset 1 Manual reset (Initial value) * Bits 4 to 0--Reserved: These bits are always read as 1. The write value should always be 1. 13.2.4 Register Access The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in that they are more difficult to write to. The procedures for writing and reading these registers are given below. Writing to TCNT and TCSR: These registers must be written by a word transfer instruction. They cannot be written by byte transfer instructions. TCNT and TCSR both have the same write address. The write data must be contained in the lower byte of the written word. The upper byte must be H'5A (for TCNT) or H'A5 (for TCSR) (figure 13.2). This transfers the write data from the lower byte to TCNT or TCSR. Rev. 5.00 Feb. 24, 2010 Page 339 of 950 REJ09B0177-0500 13. Watchdog Timer (WDT) Writing to TCNT 15 Address: H'FFFFEC10 8 7 H'5A 0 Write data Writing to TCSR 15 Address: H'FFFFEC10 8 7 H'A5 0 Write data Figure 13.2 Writing to TCNT and TCSR Writing to RSTCSR: RSTCSR must be written by a word access to address H'FFFFEC12. It cannot be written by byte transfer instructions. Procedures for writing 0 to WOVF (bit 7) and for writing to RSTE (bit 6) and RSTS (bit 5) are different, as shown in figure 13.3. To write 0 to the WOVF bit, the write data must be H'A5 in the upper byte and H'00 in the lower byte. This clears the WOVF bit to 0. The RSTE and RSTS bits are not affected. To write to the RSTE and RSTS bits, the upper byte must be H'5A and the lower byte must be the write data. The values of bits 6 and 5 of the lower byte are transferred to the RSTE and RSTS bits, respectively. The WOVF bit is not affected. Writing 0 to the WOVF bit 15 Address: H'FFFFEC12 8 7 H'A5 0 H'00 Writing to the RSTE and RSTS bits 15 Address: H'FFFFEC12 8 H'5A 7 0 Write data Figure 13.3 Writing to RSTCSR Reading from TCNT, TCSR, and RSTCSR: TCNT, TCSR, and RSTCSR are read like other registers. Use byte transfer instructions. The read addresses are H'FFFFEC10 for TCSR, H'FFFFEC11 for TCNT, and H'FFFFEC13 for RSTCSR. 13.3 Operation 13.3.1 Watchdog Timer Mode To use the WDT as a watchdog timer, set the WT/IT and TME bits in TCSR to 1. Software must prevent TCNT overflow by rewriting the TCNT value (normally by writing H'00) before overflow occurs. No TCNT overflows will occur while the system is operating normally, but if TCNT fails to be rewritten and overflows occur due to a system crash or the like, a WDTOVF signal is output externally (figure 13.4). The WDTOVF signal can be used to reset the system. The WDTOVF signal is output for 128 clock cycles. If the RSTE bit in RSTCSR is set to 1, a signal to reset the chip will be generated internally simultaneous with the WDTOVF signal when TCNT overflows. Either a power-on reset or a manual reset can be selected by the RSTS bit in RSTCSR. The internal reset signal is output for 512 clock cycles. Rev. 5.00 Feb. 24, 2010 Page 340 of 950 REJ09B0177-0500 13. Watchdog Timer (WDT) When a WDT overflow reset is generated simultaneously with a reset input at the RES pin, the RES reset takes priority, and the WOVF bit in RSTCSR is cleared to 0. The following registers are not initialized by a WDT reset signal: * PFC (pin function controller) registers * I/O port registers These registers are initialized only by an external power-on reset. TCNT value Overflow H'FF H'00 Time WT/IT = 1 TME = 1 H'00 written in TCNT WOVF = 1 WT/IT = 1 H'00 written TME = 1 in TCNT WDTOVF and internal reset generated WDTOVF signal 128 clock cycles Internal reset signal* 512 clock cycles Legend: WT/IT: Timer mode select bit TME: Timer enable bit Note: * Internal reset signal occurs only when the RSTE bit is set to 1. Figure 13.4 Operation in Watchdog Timer Mode Rev. 5.00 Feb. 24, 2010 Page 341 of 950 REJ09B0177-0500 13. Watchdog Timer (WDT) 13.3.2 Interval Timer Mode To use the WDT as an interval timer, clear WT/IT to 0 and set TME to 1 in TCSR. An interval timer interrupt (ITI) is generated each time the timer counter overflows. This function can be used to generate interval timer interrupts at regular intervals (figure 13.5). TCNT value Overflow H'FF Overflow Overflow Overflow H'00 Time WT/IT = 0 TME = 1 ITI ITI ITI ITI Legend: ITI: Interval timer interrupt request generation Figure 13.5 Operation in Interval Timer Mode 13.3.3 Timing of Setting the Overflow Flag (OVF) In interval timer mode, when TCNT overflows, the OVF flag in TCSR is set to 1 and an interval timer interrupt (ITI) is simultaneously requested (figure 13.6). CK H'FF TCNT H'00 Overflow signal (internal signal) OVF Figure 13.6 Timing of Setting OVF 13.3.4 Timing of Setting the Watchdog Timer Overflow Flag (WOVF) When TCNT overflows in watchdog timer mode, the WOVF bit in RSTCSR is set to 1 and a WDTOVF signal is output. When the RSTE bit in RSTCSR is set to 1, TCNT overflow enables an internal reset signal to be generated for the entire chip (figure 13.7). Rev. 5.00 Feb. 24, 2010 Page 342 of 950 REJ09B0177-0500 13. Watchdog Timer (WDT) CK H'FF TCNT H'00 Overflow signal (internal signal) WOVF Figure 13.7 Timing of Setting WOVF 13.4 Usage Notes 13.4.1 TCNT Write and Increment Contention If a timer counter increment clock pulse is generated during the T3 state of a write cycle to TCNT, the write takes priority and the timer counter is not incremented (figure 13.8). TCNT write cycle T1 T2 T3 CK Address TCNT address Internal write signal TCNT input clock TCNT N M Counter write data Figure 13.8 Contention between TCNT Write and Increment 13.4.2 Changing CKS2 to CKS0 Bit Values If the values of bits CKS2 to CKS0 in the timer control/status register (TCSR) are rewritten while the WDT is running, the count may not increment correctly. Always stop the watchdog timer (by clearing the TME bit to 0) before changing the values of bits CKS2 to CKS0. 13.4.3 Changing between Watchdog Timer/Interval Timer Modes To prevent incorrect operation, always stop the watchdog timer (by clearing the TME bit to 0) before switching between interval timer mode and watchdog timer mode. Rev. 5.00 Feb. 24, 2010 Page 343 of 950 REJ09B0177-0500 13. Watchdog Timer (WDT) 13.4.4 System Reset by WDTOVF Signal If a WDTOVF signal is input to the RES pin, the chip cannot be initialized correctly. Avoid logical input of the WDTOVF output signal to the RES input pin. To reset the entire system with the WDTOVF signal, use the circuit shown in figure 13.9. This LSI Reset input Reset signal to entire system RES WDTOVF Figure 13.9 Example of System Reset Circuit Using WDTOVF Signal 13.4.5 Internal Reset in Watchdog Timer Mode If the RSTE bit is cleared to 0 in watchdog timer mode, the chip will not be reset internally when a TCNT overflow occurs, but TCNT and TCSR in the WDT will be reset. Because the internal clock obtained by dividing the system clock() is also reset at this time, the SCI, A/D converter, and CMT that use the internal clock may not operate correctly from hereafter. To continue using these modules, initialize them before use. 13.4.6 Manual Reset in Watchdog Timer When an internal reset is effected by TCNT overflow in watchdog timer mode, the processor waits until the end of the bus cycle at the time of manual reset generation before making the transition to manual reset exception processing. Therefore, the bus cycle is retained in a manual reset, but if a manual reset occurs while the bus is released or during DMAC burst transfer, manual reset exception processing will be deferred until the CPU acquires the bus. However, if the interval from generation of the manual reset until the CPU acquires the bus cycle is equal to or longer than the internal manual reset interval of 512 cycles, the internal manual reset source is ignored instead of being deferred, and manual reset exception processing is not executed. Rev. 5.00 Feb. 24, 2010 Page 344 of 950 REJ09B0177-0500 14. Compare Match Timer (CMT) Section 14 Compare Match Timer (CMT) 14.1 Overview This LSI has an on-chip compare match timer (CMT) comprising two 16-bit timer channels. The CMT has 16-bit counters and can generate interrupts at set intervals. 14.1.1 Features The CMT has the following features: * Four types of counter input clock can be selected One of four internal clocks (P/8, P/32, P/128, P/512) can be selected independently for each channel. * Interrupt sources A compare match interrupt can be requested independently for each channel. 14.1.2 Block Diagram Figure 14.1 shows a block diagram of the CMT. P/32 CMI1 P/8 Module bus P/512 P/128 Clock selection CMCNT1 Control circuit CMCSR1 Clock selection CMCNT0 Comparator CMCOR0 CMCSR0 CMSTR Control circuit P/512 P/128 Comparator P/8 CMCOR1 P/32 CM10 Bus interface CMT Legend: CMSTR: CMCSR: CMCOR: CMCNT: CMI: Internal bus Compare match timer start register Compare match timer control/status register Compare match timer constant register Compare match timer counter Compare match interrupt Figure 14.1 CMT Block Diagram Rev. 5.00 Feb. 24, 2010 Page 345 of 950 REJ09B0177-0500 14. Compare Match Timer (CMT) 14.1.3 Register Configuration Table 14.1 summarizes the CMT register configuration. Table 14.1 Register Configuration Channel Name Shared 0 1 Note: Abbreviation R/W Initial Value Address Access Size (Bits) Compare match timer startCMSTR register R/W H'0000 H'FFFFF710 8, 16, 32 Compare match timer control/status register 0 CMCSR0 R/(W)* H'0000 H'FFFFF712 8, 16, 32 Compare match timer counter 0 CMCNT0 R/W H'0000 H'FFFFF714 8, 16, 32 Compare match timer constant register 0 CMCOR0 R/W H'FFFF H'FFFFF716 8, 16, 32 Compare match timer control/status register 1 CMCSR1 R/(W)* H'0000 H'FFFFF718 8, 16, 32 Compare match timer counter 1 CMCNT1 R/W H'0000 H'FFFFF71A 8, 16, 32 Compare match timer constant register 1 CMCOR1 R/W H'FFFF H'FFFFF71C 8, 16, 32 * Only 0 can be written to the CMCSR0 and CMCSR1 CMF bits to clear the flags. 14.2 Register Descriptions 14.2.1 Compare Match Timer Start Register (CMSTR) The compare match timer start register (CMSTR) is a 16-bit register that selects whether to operate or halt the channel 0 and channel 1 counters (CMCNT). It is initialized to H'0000 by a power-on reset and in the standby modes. Bit: 15 14 13 12 11 10 9 8 - - - - - - - - Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 - - - - - - STR1 STR0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R/W R/W * Bits 15-2--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 1--Count Start 1 (STR1): Selects whether to operate or halt compare match timer counter 1. Bit 1: STR1 Description 0 CMCNT1 count operation halted 1 CMCNT1 count operation Rev. 5.00 Feb. 24, 2010 Page 346 of 950 REJ09B0177-0500 (Initial value) 14. Compare Match Timer (CMT) * Bit 0--Count Start 0 (STR0): Selects whether to operate or halt compare match timer counter 0. Bit 0: STR0 Description 0 CMCNT0 count operation halted 1 CMCNT0 count operation 14.2.2 (Initial value) Compare Match Timer Control/Status Register (CMCSR) The compare match timer control/status register (CMCSR) is a 16-bit register that indicates the occurrence of compare matches, sets the enable/disable status of interrupts, and establishes the clock used for incrementation. It is initialized to H'0000 by a power-on reset and in the standby modes. Bit: 15 14 13 12 11 10 9 8 - - - - - - - - Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: Initial value: R/W: Note: * 7 6 5 4 3 2 1 0 CMF CMIE - - - - CKS1 CKS0 0 0 0 0 0 0 0 0 R/(W)* R/W R R R R R/W R/W Only 0 can be written to clear the flag. * Bits 15-8 and 5-2--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 7--Compare Match Flag (CMF): This flag indicates whether or not the CMCNT and CMCOR values have matched. Bit 7: CMF Description 0 CMCNT and CMCOR values have not matched (Initial value) [Clearing condition] Write 0 to CMF after reading 1 from it 1 CMCNT and CMCOR values have matched * Bit 6--Compare Match Interrupt Enable (CMIE): Selects whether to enable or disable a compare match interrupt (CMI) when the CMCNT and CMCOR values have matched (CMF = 1). Bit 6: CMIE Description 0 Compare match interrupt (CMI) disabled 1 Compare match interrupt (CMI) enabled (Initial value) Rev. 5.00 Feb. 24, 2010 Page 347 of 950 REJ09B0177-0500 14. Compare Match Timer (CMT) * Bits 1 and 0--Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock input to CMCNT from among the four internal clocks obtained by dividing the peripheral clock (P). When the STR bit of CMSTR is set to 1, CMCNT begins incrementing with the clock selected by CKS1 and CKS0. Bit 1: CKS1 Bit 0: CKS0 Description 0 0 P/8 1 P/32 0 P/128 1 P/512 1 14.2.3 (Initial value) Compare Match Timer Counter (CMCNT) The compare match timer counter (CMCNT) is a 16-bit register used as an up-counter for generating interrupt requests. When an internal clock is selected with the CKS1 and CKS0 bits of the CMCSR register and the STR bit of CMSTR is set to 1, CMCNT begins incrementing with that clock. When the CMCNT value matches that of the compare match timer constant register (CMCOR), CMCNT is cleared to H'0000 and the CMF flag of CMCSR is set to 1. If the CMIE bit of CMCSR is set to 1 at this time, a compare match interrupt (CMI) is requested. CMCNT is initialized to H'0000 by a power-on reset and in the standby modes. It is not initialized by a manual reset. Bit: 15 14 13 12 11 10 9 8 Initial value: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W: R/W: 14.2.4 Compare Match Timer Constant Register (CMCOR) The compare match timer constant register (CMCOR) is a 16-bit register that sets the period for compare match with CMCNT. CMCOR is initialized to H'FFFF by a power-on reset and in the standby modes. It is not initialized by a manual reset. Bit: 15 14 13 12 11 10 9 8 Initial value: 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W: R/W: Rev. 5.00 Feb. 24, 2010 Page 348 of 950 REJ09B0177-0500 14. Compare Match Timer (CMT) 14.3 Operation 14.3.1 Cyclic Count Operation When an internal clock is selected with the CKS1, CKS0 bits of the CMCSR register and the STR bit of CMSTR is set to 1, CMCNT begins incrementing with the selected clock. When the CMCNT counter value matches that of the compare match constant register (CMCOR), the CMCNT counter is cleared to H'0000 and the CMF flag of the CMCSR register is set to 1. If the CMIE bit of the CMCSR register is set to 1 at this time, a compare match interrupt (CMI) is requested. The CMCNT counter begins counting up again from H'0000. Figure 14.2 shows the compare match counter operation. CMCNT value Counter cleared by CMCOR compare match CMCOR H'0000 Time Figure 14.2 Counter Operation 14.3.2 CMCNT Count Timing One of four clocks (P/8, P/32, P/128, P/512) obtained by dividing the peripheral clock (P) can be selected by the CKS1 and CKS0 bits of CMCSR. Figure 14.3 shows the timing. P Internal clock CMCNT input clock CMCNT N-1 N N+1 Figure 14.3 Count Timing 14.4 Interrupts 14.4.1 Interrupt Sources and DTC Activation The CMT has a compare match interrupt for each channel, with independent vector addresses allocated to each of them. The corresponding interrupt request is output when interrupt request flag CMF is set to 1 and interrupt enable bit CMIE has also been set to 1. When activating CPU interrupts by interrupt request, the priority between the channels can be changed by means of interrupt controller settings. See section 7, Interrupt Controller (INTC), for details. Rev. 5.00 Feb. 24, 2010 Page 349 of 950 REJ09B0177-0500 14. Compare Match Timer (CMT) 14.4.2 Compare Match Flag Set Timing The CMF bit of the CMCSR register is set to 1 by the compare match signal generated when the CMCOR register and the CMCNT counter match. The compare match signal is generated upon the final state of the match (timing at which the CMCNT counter matching count value is updated). Consequently, after the CMCOR register and the CMCNT counter match, a compare match signal will not be generated until a CMCNT counter input clock occurs. Figure 14.4 shows the CMF bit set timing. P CMCNT input clock 0 N CMCNT N CMCOR Compare match signal CMF CMI Figure 14.4 CMF Set Timing 14.4.3 Compare Match Flag Clear Timing The CMF bit of the CMCSR register is cleared by writing a 0 to it after reading a 1. Figure 14.5 shows the timing when the CMF bit is cleared by the CPU. CMCSR write cycle T1 T2 P CMF Figure 14.5 Timing of CMF Clear by the CPU Rev. 5.00 Feb. 24, 2010 Page 350 of 950 REJ09B0177-0500 14. Compare Match Timer (CMT) 14.5 Usage Notes Take care that the contentions described in sections 14.5.1 to 14.5.3 do not arise during CMT operation. 14.5.1 Contention between CMCNT Write and Compare Match If a compare match signal is generated during the T2 state of the CMCNT counter write cycle, the CMCNT counter clear has priority, so the write to the CMCNT counter is not performed. Figure 14.6 shows the timing. CMCNT write cycle T1 T2 P Address CMCNT Internal write signal Compare match signal CMCNT N H'0000 Figure 14.6 CMCNT Write and Compare Match Contention 14.5.2 Contention between CMCNT Word Write and Incrementation If an increment occurs during the T2 state of the CMCNT counter word write cycle, the counter write has priority, so no increment occurs. Figure 14.7 shows the timing. CMCNT write cycle T1 T2 P Address CMCNT Internal write signal CMCNT input clock CMCNT N M CMCNT write data Figure 14.7 CMCNT Word Write and Increment Contention Rev. 5.00 Feb. 24, 2010 Page 351 of 950 REJ09B0177-0500 14. Compare Match Timer (CMT) 14.5.3 Contention between CMCNT Byte Write and Incrementation If an increment occurs during the T2 state of the CMCNT byte write cycle, the counter write has priority, so no increment of the write data results on the side on which the write was performed. The byte data on the side on which writing was not performed is also not incremented, so the contents are those before the write. Figure 14.8 shows the timing when an increment occurs during the T2 state of the CMCNTH write cycle. CMCNT write cycle T1 T2 P Address CMCNTH Internal write signal CMCNT input clock CMCNTH N M CMCNTH write data CMCNTL X X Figure 14.8 CMCNT Byte Write and Increment Contention Rev. 5.00 Feb. 24, 2010 Page 352 of 950 REJ09B0177-0500 15. Serial Communication Interface (SCI) Section 15 Serial Communication Interface (SCI) 15.1 Overview This LSI has a serial communication interface (SCI) with five independent channels. The SCI supports both asynchronous and synchronous serial communication. It also has a multiprocessor communication function for serial communication between two or more processors, and a clock inverted input/output function. 15.1.1 Features The SCI has the following features: * Selection of asynchronous or synchronous as the serial communication mode Asynchronous mode Serial data communication is synchronized in character units. The SCI can communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous communication interface adapter (ACIA), or any other chip that employs standard asynchronous serial communication. It can also communicate with two or more other processors using the multiprocessor communication function. There are twelve selectable serial data communication formats. * Data length: seven or eight bits * Stop bit length: one or two bits * Parity: even, odd, or none * Multiprocessor bit: one or none * Receive error detection: parity, overrun, and framing errors * Break detection: by reading the RxD level directly when a framing error occurs Synchronous mode Serial data communication is synchronized with a clock signal. The SCI can communicate with other chips having a synchronous communication function. There is one serial data communication format. * Data length: eight bits * Receive error detection: overrun errors * Serial clock inverted input/output * Full duplex communication: The transmitting and receiving sections are independent, so the SCI can transmit and receive simultaneously. Both sections use double buffering, so continuous data transfer is possible in both the transmit and receive directions. * On-chip baud rate generator with selectable bit rates * Internal or external transmit/receive clock source: baud rate generator (internal) or SCK pin (external) * Four types of interrupts: Transmit-data-empty, transmit-end, receive-data-full, and receive-error interrupts are requested independently. The transmit-data-empty and receive-data-full interrupts can start the direct memory access controller (DMAC) to transfer data. * Selection of LSB-first or MSB-first transfer (8-bit length) This selection is available regardless of the communication mode. (The descriptions in this section are based on LSBfirst transfer.) Rev. 5.00 Feb. 24, 2010 Page 353 of 950 REJ09B0177-0500 15. Serial Communication Interface (SCI) 15.1.2 Block Diagram Bus interface Figure 15.1 shows a block diagram of the SCI. Module data bus RDR TDR Internal data bus BRR SSR SCR SMR RxD RSR TSR Baud rate generator SDCR Transmit/ receive control TxD Parity generation P P/4 P/16 P/64 Clock Parity check External clock SCK TEI TXI RXI ERI SCI Legend: RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR: SCR: SSR: BRR: SDCR: Serial mode register Serial control register Serial status register Bit rate register Serial direction control register Figure 15.1 SCI Block Diagram Rev. 5.00 Feb. 24, 2010 Page 354 of 950 REJ09B0177-0500 15. Serial Communication Interface (SCI) 15.1.3 Pin Configuration Table 15.1 summarizes the SCI pins by channel. Table 15.1 SCI Pins Channel Pin Name Abbreviation Input/Output Function 0 Serial clock pin SCK0 Input/output SCI0 clock input/output Receive data pin RxD0 Input SCI0 receive data input Transmit data pin TxD0 Output SCI0 transmit data output Serial clock pin SCK1 Input/output SCI1 clock input/output Receive data pin RxD1 Input SCI1 receive data input Transmit data pin TxD1 Output SCI1 transmit data output Serial clock pin SCK2 Input/output SCI2 clock input/output Receive data pin RxD2 Input SCI2 receive data input Transmit data pin TxD2 Output SCI2 transmit data output Serial clock pin SCK3 Input/output SCI3 clock input/output Receive data pin RxD3 Input SCI3 receive data input Transmit data pin TxD3 Output SCI3 transmit data output Serial clock pin SCK4 Input/output SCI4 clock input/output 1 2 3 4 Receive data pin RxD4 Input SCI4 receive data input Transmit data pin TxD4 Output SCI4 transmit data output Note: In the text the pins are referred to as SCK, RxD, and TxD, omitting the channel number. Rev. 5.00 Feb. 24, 2010 Page 355 of 950 REJ09B0177-0500 15. Serial Communication Interface (SCI) 15.1.4 Register Configuration Table 15.2 summarizes the SCI internal registers. These registers select the communication mode (asynchronous or synchronous), specify the data format and bit rate, and control the transmitter and receiver sections. Table 15.2 Registers Channel Name Abbreviation R/W Initial Value Address*2 Access Size 0 Serial mode register 0 SMR0 R/W H'00 H'FFFFF000 8, 16 Bit rate register 0 BRR0 R/W H'FF H'FFFFF001 Serial control register 0 SCR0 R/W H'00 H'FFFFF002 Transmit data register 0 TDR0 R/W H'FF H'FFFFF003 1 2 3 4 1 Serial status register 0 SSR0 R/(W) * H'84 H'FFFFF004 Receive data register 0 RDR0 R H'00 H'FFFFF005 Serial direction control register 0 SDCR0 R/W H'F2 H'FFFFF006 8 Serial mode register 1 SMR1 R/W H'00 H'FFFFF008 8, 16 Bit rate register 1 BRR1 R/W H'FF H'FFFFF009 Serial control register 1 SCR1 R/W H'00 H'FFFFF00A Transmit data register 1 TDR1 R/W H'FF H'FFFFF00B 1 Serial status register 1 SSR1 R/(W) * H'84 H'FFFFF00C Receive data register 1 RDR1 R H'00 H'FFFFF00D Serial direction control register 1 SDCR1 R/W H'F2 H'FFFFF00E 8 Serial mode register 2 SMR2 R/W H'00 H'FFFFF010 8, 16 Bit rate register 2 BRR2 R/W H'FF H'FFFFF011 Serial control register 2 SCR2 R/W H'00 H'FFFFF012 Transmit data register 2 TDR2 R/W H'FF H'FFFFF013 1 Serial status register 2 SSR2 R/(W) * H'84 H'FFFFF014 Receive data register 2 RDR2 R H'00 H'FFFFF015 Serial direction control register 2 SDCR2 R/W H'F2 H'FFFFF016 8 Serial mode register 3 SMR3 R/W H'00 H'FFFFF018 8, 16 Bit rate register 3 BRR3 R/W H'FF H'FFFFF019 Serial control register 3 SCR3 R/W H'00 H'FFFFF01A Transmit data register 3 TDR3 R/W H'FF H'FFFFF01B Serial status register 3 SSR3 R/(W) *1 H'84 H'FFFFF01C Receive data register 3 RDR3 R H'00 H'FFFFF01D Serial direction control register 3 SDCR3 R/W H'F2 H'FFFFF01E 8 Serial mode register 4 SMR4 R/W H'00 H'FFFFF020 8, 16 Bit rate register 4 BRR4 R/W H'FF H'FFFFF021 Serial control register 4 SCR4 R/W H'00 H'FFFFF022 Transmit data register 4 TDR4 R/W H'FF H'FFFFF023 Serial status register 4 SSR4 R/(W) *1 H'84 H'FFFFF024 Receive data register 4 RDR4 R H'00 H'FFFFF025 Serial direction control register 4 SDCR4 R/W H'F2 H'FFFFF026 Notes: 1. Only 0 can be written to clear the flags. 2. Do not access empty addresses. Rev. 5.00 Feb. 24, 2010 Page 356 of 950 REJ09B0177-0500 8 15. Serial Communication Interface (SCI) 15.2 Register Descriptions 15.2.1 Receive Shift Register (RSR) Bit: 7 6 5 4 3 2 1 0 R/W: - - - - - - - - The receive shift register (RSR) receives serial data. Data input at the RxD pin is loaded into RSR in the order received, LSB (bit 0) first, converting the data to parallel form. When one byte has been received, it is automatically transferred to RDR. The CPU cannot read or write to RSR directly. 15.2.2 Receive Data Register (RDR) Bit: 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R The receive data register (RDR) stores serial receive data. The SCI completes the reception of one byte of serial data by moving the received data from the receive shift register (RSR) into RDR for storage. RSR is then ready to receive the next data. This double buffering allows the SCI to receive data continuously. The CPU can read but not write to RDR. RDR is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. It is not initialized by a manual reset. 15.2.3 Transmit Shift Register (TSR) Bit: 7 6 5 4 3 2 1 0 R/W: - - - - - - - - The transmit shift register (TSR) transmits serial data. The SCI loads transmit data from the transmit data register (TDR) into TSR, then transmits the data serially from the TxD pin, LSB (bit 0) first. After transmitting one data byte, the SCI automatically loads the next transmit data from TDR into TSR and starts transmitting again. If the TDRE bit of SSR is 1, however, the SCI does not load the TDR contents into TSR. The CPU cannot read or write to TSR directly. 15.2.4 Transmit Data Register (TDR) Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Rev. 5.00 Feb. 24, 2010 Page 357 of 950 REJ09B0177-0500 15. Serial Communication Interface (SCI) The transmit data register (TDR) is an 8-bit register that stores data for serial transmission. When the SCI detects that the transmit shift register (TSR) is empty, it moves transmit data written in TDR into TSR and starts serial transmission. Continuous serial transmission is possible by writing the next transmit data in TDR during serial transmission from TSR. The CPU can always read and write to TDR. TDR is initialized to H'FF by a power-on reset, and in hardware standby mode and software standby mode. It is not initialized by a manual reset. 15.2.5 Serial Mode Register (SMR) Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 C/A CHR PE O/E STOP MP CKS1 CKS0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The serial mode register (SMR) is an 8-bit register that specifies the SCI serial communication format and selects the clock source for the baud rate generator. The CPU can always read to SMR. The CPU should only perform write operations when making initial settings. Do not use the CPU to perform writes during transmit, receive, or transmit/receive operation. SMR is initialized to H'00 by a power-on reset and in hardware standby mode. The value is not retained in software standby mode and it is initialized after release. It is not initialized by a manual reset. * Bit 7--Communication Mode (C/A): Selects whether the SCI operates in asynchronous or synchronous mode. Bit 7: C/A Description 0 Asynchronous mode 1 Synchronous mode (Initial value) * Bit 6--Character Length (CHR): Selects 7-bit or 8-bit data in asynchronous mode. In synchronous mode, the data length is always eight bits, regardless of the CHR setting. Bit 6: CHR Description 0 Eight-bit data 1 Seven-bit data (Initial value) When 7-bit data is selected, the MSB (bit 7) of the transmit data register is not transmitted. LSB-first/MSB-first selection is not available. * Bit 5--Parity Enable (PE): Selects whether to add a parity bit to transmit data and to check the parity of receive data, in asynchronous mode. In synchronous mode and when using a multiprocessor format, a parity bit is neither added nor checked, regardless of the PE bit setting. Bit 5: PE Description 0 Parity bit not added or checked 1 Parity bit added and checked (Initial value) When PE is set to 1, an even or odd parity bit is added to transmit data, depending on the parity mode (O/E bit) setting. Receive data parity is checked according to the even/odd (O/E bit) setting. Rev. 5.00 Feb. 24, 2010 Page 358 of 950 REJ09B0177-0500 15. Serial Communication Interface (SCI) * Bit 4--Parity Mode (O/E): Selects even or odd parity when parity bits are added and checked. The O/E setting is used only in asynchronous mode and only when the parity enable bit (PE) is set to 1 to enable parity addition and checking. The O/E setting is invalid in synchronous mode, in asynchronous mode when parity bit addition and checking is disabled, and when using a multiprocessor format. Bit 4: O/E Description 0 Even parity (Initial value) If even parity is selected, the parity bit is added to transmit data to make an even number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an even number of 1s in the received character and parity bit combined. 1 Odd parity If odd parity is selected, the parity bit is added to transmit data to make an odd number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an odd number of 1s in the received character and parity bit combined. * Bit 3--Stop Bit Length (STOP): Selects one or two bits as the stop bit length in asynchronous mode. This setting is used only in asynchronous mode. It is ignored in synchronous mode because no stop bits are added. In receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of the next incoming character. Bit 3: STOP Description 0 One stop bit (Initial value) In transmitting, a single bit of 1 is added at the end of each transmitted character. 1 Two stop bits In transmitting, two 1-bits are added at the end of each transmitted character. * Bit 2--Multiprocessor Mode (MP): Selects multiprocessor format. When multiprocessor format is selected, settings of the parity enable (PE) and parity mode (O/E) bits are ignored. The MP bit setting is used only in asynchronous mode; it is ignored in synchronous mode. For the multiprocessor communication function, see section 15.3.3, Multiprocessor Communication. Bit 2: MP Description 0 Multiprocessor function disabled 1 Multiprocessor format selected (Initial value) * Bits 1 and 0--Clock Select 1 and 0 (CKS1, CKS0): These bits select the internal clock source of the on-chip baud rate generator. Four clock sources are available: P, P/4, P/16, or P/64 (P is the peripheral clock). For further information on the clock source, bit rate register settings, and baud rate, see section 15.2.8, Bit Rate Register (BRR). Bit 1: CKS1 Bit 0: CKS0 Description 0 0 P 1 P/4 0 P/16 1 P/64 1 (Initial value) Rev. 5.00 Feb. 24, 2010 Page 359 of 950 REJ09B0177-0500 15. Serial Communication Interface (SCI) 15.2.6 Serial Control Register (SCR) Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The serial control register (SCR) operates the SCI transmitter/receiver, selects the serial clock output in asynchronous mode, enables/disables interrupt requests, and selects the transmit/receive clock source. The CPU can always read/write to SCR. SCR is initialized to H'00 by a power-on reset and in hardware standby mode. The value is not retained in software standby mode and it is initialized after release. It is not initialized by a manual reset. * Bit 7--Transmit Interrupt Enable (TIE): Enables or disables the transmit-data-empty interrupt (TXI) requested when the transmit data register empty bit (TDRE) in the serial status register (SSR) is set to 1 by transfer of serial transmit data from TDR to TSR. Bit 7: TIE 0 Description Transmit-data-empty interrupt request (TXI) is disabled (Initial value) The TXI interrupt request can be cleared by reading TDRE after it has been set to 1, then clearing TDRE to 0, or by clearing TIE to 0. 1 Transmit-data-empty interrupt request (TXI) is enabled * Bit 6--Receive Interrupt Enable (RIE): Enables or disables the receive-data-full interrupt (RXI) requested when the receive data register full bit (RDRF) in the serial status register (SSR) is set to 1 by transfer of serial receive data from RSR to RDR. It also enables or disables receive-error interrupt (ERI) requests. Bit 6: RIE Description 0 Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are disabled (Initial value) RXI and ERI interrupt requests can be cleared by reading the RDRF flag or error flag (FER, PER, or ORER) after it has been set to 1, then clearing the flag to 0, or by clearing RIE to 0. 1 Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are enabled * Bit 5--Transmit Enable (TE): Enables or disables the SCI serial transmitter. Bit 5: TE Description 0 Transmitter disabled (Initial value) The transmit data register empty bit (TDRE) in the serial status register (SSR) is locked at 1. 1 Transmitter enabled Serial transmission starts when the transmit data register empty (TDRE) bit in the serial status register (SSR) is cleared to 0 after writing of transmit data into TDR. Select the transmit format in SMR before setting TE to 1. Rev. 5.00 Feb. 24, 2010 Page 360 of 950 REJ09B0177-0500 15. Serial Communication Interface (SCI) * Bit 4--Receive Enable (RE): Enables or disables the SCI serial receiver. Bit 4: RE Description 0 Receiver disabled (Initial value) Clearing RE to 0 does not affect the receive flags (RDRF, FER, PER, ORER). These flags retain their previous values. 1 Receiver enabled Serial reception starts when a start bit is detected in asynchronous mode, or synchronous clock input is detected in synchronous mode. Select the receive format in SMR before setting RE to 1. * Bit 3--Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE setting is used only in asynchronous mode, and only if the multiprocessor mode bit (MP) in the serial mode register (SMR) is set to 1 during reception. The MPIE setting is ignored in synchronous mode or when the MP bit is cleared to 0. Bit 3: MPIE 0 Description Multiprocessor interrupts are disabled (normal receive operation) (Initial value) [Clearing conditions] 1 * When the MPIE bit is cleared to 0 * When data with MPB = 1 is received Multiprocessor interrupts are enabled. Receive-data-full interrupt requests (RXI), receiveerror interrupt requests (ERI), and setting of the RDRF, FER, and ORER status flags in the serial status register (SSR) are disabled until data with the multiprocessor bit set to 1 is received. The SCI does not transfer receive data from RSR to RDR, does not detect receive errors, and does not set the RDRF, FER, and ORER flags in the serial status register (SSR). When it receives data that includes MPB = 1, MPB is set to 1, and the SCI automatically clears MPIE to 0, generates RXI and ERI interrupts (if the TIE and RIE bits in SCR are set to 1), and allows the FER and ORER bits to be set. * Bit 2--Transmit-End Interrupt Enable (TEIE): Enables or disables the transmit-end interrupt (TEI) requested if TDR does not contain valid transmit data when the MSB is transmitted. Bit 2: TEIE Description 0 Transmit-end interrupt (TEI) requests are disabled* 1 Transmit-end interrupt (TEI) requests are enabled* Note: * (Initial value) The TEI request can be cleared by reading the TDRE bit in the serial status register (SSR) after it has been set to 1, then clearing TDRE to 0 and clearing the transmit end (TEND) bit to 0; or by clearing the TEIE bit to 0. Rev. 5.00 Feb. 24, 2010 Page 361 of 950 REJ09B0177-0500 15. Serial Communication Interface (SCI) * Bits 1 and 0--Clock Enable 1 and 0 (CKE1, CKE0): These bits select the SCI clock source and enable or disable clock output from the SCK pin. Depending on the combination of CKE1 and CKE0, the SCK pin can be used for serial clock output, or serial clock input. Select the SCK pin function by using the pin function controller (PFC). The CKE0 setting is valid only in asynchronous mode, and only when the SCI is internally clocked (CKE1 = 0). The CKE0 setting is ignored in synchronous mode, or when an external clock source is selected (CKE1 = 1). For further details on selection of the SCI clock source, see table 15.9. 1 Bit 1: CKE1 Bit 0: CKE0 Description* 0 0 Asynchronous mode Internal clock, SCK pin used for input pin (input signal is ignored) or output pin (output level is undefined)*2 Synchronous mode Internal clock, SCK pin used for synchronous clock output* Asynchronous mode Internal clock, SCK pin used for clock output*3 Synchronous mode Internal clock, SCK pin used for synchronous clock output External clock, SCK pin used for clock input*4 0 1 1 0 Asynchronous mode Synchronous mode External clock, SCK pin used for synchronous clock input 1 1 Asynchronous mode External clock, SCK pin used for clock input*4 Synchronous mode External clock, SCK pin used for synchronous clock input 2 Notes: 1. The SCK pin is multiplexed with other functions. Use the pin function controller (PFC) to select the SCK function for this pin, as well as the I/O direction. 2. Initial value. 3. The output clock frequency is the same as the bit rate. 4. The input clock frequency is 16 times the bit rate. 15.2.7 Serial Status Register (SSR) Bit: Initial value: R/W: Note: * 7 6 5 4 3 2 1 0 TDRE RDRF ORER FER PER TEND MPB MPBT 1 0 0 0 0 1 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W This bit can be written to when its value is read as 1, and it cannot be written to when its value is read as 0. The serial status register (SSR) is an 8-bit register containing multiprocessor bit values, and status flags that indicate the SCI operating status. The CPU can always read and write to SSR, but when the TDRE, RDRF, ORER, PER, or PEF bit is read as 1 it becomes writable, and when it is read as 0 it is not writable. As examples of ways to prevent a flag from being set inadvertently by a write operation, either prohibit writing 1 to the bit during the period from when it is read as 1 and the next time it is read as 0, or write 0 immediately after the bit is cleared to 0, so that it is always in a not writable state except when performing a flag clearing operation. Bits 2 (TEND) and 1 (MPB) are read-only bits that cannot be written. SSR is initialized to H'84 by a power-on reset, and in hardware standby mode and software standby mode. It is not initialized by a manual reset. Rev. 5.00 Feb. 24, 2010 Page 362 of 950 REJ09B0177-0500 15. Serial Communication Interface (SCI) * Bit 7--Transmit Data Register Empty (TDRE): Indicates that the SCI has loaded transmit data from TDR into TSR and new serial transmit data can be written in TDR. Bit 7: TDRE 0 Description TDR contains valid transmit data [Clearing conditions] 1 * When 0 is written to TDRE after reading TDRE = 1 * When the DMAC writes data in TDR TDR does not contain valid transmit data (Initial value) [Setting conditions] * Power-on reset, hardware standby mode, or software standby mode * When the TE bit in SCR is 0 * When data is transferred from TDR to TSR, enabling new data to be written in TDR * When 1 is written after the first clearing condition is met * Bit 6--Receive Data Register Full (RDRF): Indicates that RDR contains received data. Bit 6: RDRF 0 Description RDR does not contain valid receive data (Initial value) [Clearing conditions] 1 * Power-on reset, hardware standby mode, or software standby mode * When 0 is written to RDRF after reading RDRF = 1 * When the DMAC reads data from RDR RDR contains valid received data [Setting conditions] * RDRF is set to 1 when serial data is received normally and transferred from RSR to RDR * When 1 is written after the second clearing condition is met Note: RDR and RDRF are not affected by detection of receive errors or by clearing of the RE bit to 0 in the serial control register. They retain their previous contents. If RDRF is still set to 1 when reception of the next data ends, an overrun error (ORER) occurs and the receive data is lost. * Bit 5--Overrun Error (ORER): Indicates that data reception ended abnormally due to an overrun error. Bit 5: ORER Description 0 Receiving is in progress or has ended normally (Initial value) Clearing the RE bit to 0 in the serial control register does not affect the ORER bit, which retains its previous value. [Clearing conditions] 1 * Power-on reset, hardware standby mode, or software standby mode * When 0 is written to ORER after reading ORER = 1 A receive overrun error occurred RDR continues to hold the data received before the overrun error, so subsequent receive data is lost. Serial receiving cannot continue while ORER is set to 1. In synchronous mode, serial transmitting is disabled. [Setting conditions] * ORER is set to 1 if reception of the next serial data ends when RDRF is set to 1 * When 1 is written after the second clearing condition is met Rev. 5.00 Feb. 24, 2010 Page 363 of 950 REJ09B0177-0500 15. Serial Communication Interface (SCI) * Bit 4--Framing Error (FER): Indicates that data reception ended abnormally due to a framing error in asynchronous mode. Bit 4: FER 0 Description Receiving is in progress or has ended normally (Initial value) Clearing the RE bit to 0 in the serial control register does not affect the FER bit, which retains its previous value. [Clearing conditions] 1 * Power-on reset, hardware standby mode, or software standby mode * When 0 A receive framing error occurred When the stop bit length is two bits, only the first bit is checked to see if it is a 1. The second stop bit is not checked. When a framing error occurs, the SCI transfers the receive data into RDR but does not set RDRF. Serial receiving cannot continue while FER is set to 1. In synchronous mode, serial transmitting is also disabled. [Setting conditions] * FER is set to 1 if the stop bit at the end of receive data is checked and found to be 0 * When 1 is written after the second clearing condition is met * Bit 3--Parity Error (PER): Indicates that data reception (with parity) ended abnormally due to a parity error in asynchronous mode. Bit 3: PER 0 Description Receiving is in progress or has ended normally (Initial value) Clearing the RE bit to 0 in the serial control register does not affect the PER bit, which retains its previous value. [Clearing conditions] 1 * Power-on reset, hardware standby mode, or software standby mode * When 0 is written to PER after reading PER = 1 A receive parity error occurred When a parity error occurs, the SCI transfers the receive data into RDR but does not set RDRF. Serial receiving cannot continue while PER is set to 1. [Setting conditions] * PER is set to 1 if the number of 1s in receive data, including the parity bit, does not match the even or odd parity setting of the parity mode bit (O/E) in the serial mode register (SMR) * When 1 is written after the second clearing condition is met Rev. 5.00 Feb. 24, 2010 Page 364 of 950 REJ09B0177-0500 15. Serial Communication Interface (SCI) * Bit 2--Transmit End (TEND): Indicates that when the last bit of a serial character was transmitted, TDR did not contain valid data, so transmission has ended. TEND is a read-only bit and cannot be written. Bit 2: TEND Description 0 Transmission is in progress [Clearing conditions] 1 * When 0 is written to TDRE after reading TDRE = 1 * When the DMAC writes data in TDR End of transmission (Initial value) [Setting conditions] * Power-on reset, hardware standby mode, or software standby mode * When the TE bit in SCR is 0 * If TDRE = 1 when the last bit of a one-byte serial transmit character is transmitted * Bit 1--Multiprocessor Bit (MPB): Stores the value of the multiprocessor bit in receive data when a multiprocessor format is selected for receiving in asynchronous mode. MPB is a read-only bit and cannot be written. Bit 1: MPB Description 0 Multiprocessor bit value in receive data is 0 (Initial value) If RE is cleared to 0 when a multiprocessor format is selected, the MPB retains its previous value. 1 Multiprocessor bit value in receive data is 1 * Bit 0--Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit added to transmit data when a multiprocessor format is selected for transmitting in asynchronous mode. The MPBT setting is ignored in synchronous mode, when a multiprocessor format is not selected, or when the SCI is not transmitting. Bit 0: MPBT Description 0 Multiprocessor bit value in transmit data is 0 1 Multiprocessor bit value in transmit data is 1 15.2.8 (Initial value) Bit Rate Register (BRR) Bit: 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W: The bit rate register (BRR) is an 8-bit register that, together with the baud rate generator clock source selected by the CKS1 and CKS0 bits in the serial mode register (SMR), determines the serial transmit/receive bit rate. The CPU can always read to BRR. The CPU should only perform write operations when making initial settings. Do not use the CPU to perform writes during transmit, receive, or transmit/receive operation. BRR is initialized to H'FF by a power-on reset and in hardware standby mode. The value is not retained in software standby mode and it is initialized after release. It is not initialized by a manual reset. Each channel has independent baud rate generator control, so different values can be set for each channel. Table 15.3 lists examples of BRR settings in the asynchronous mode; table 15.4 lists examples of BBR settings in the clock synchronous mode. Rev. 5.00 Feb. 24, 2010 Page 365 of 950 REJ09B0177-0500 15. Serial Communication Interface (SCI) Table 15.3 Bit Rates and BRR Settings in Asynchronous Mode P (MHz) 10 11.0592 12 Bit Rate (Bits/s) n N Error (%) n N Error (%) n N Error (%) 110 2 177 -0.25 2 195 0.19 2 212 0.03 150 2 129 0.16 2 143 0.00 2 155 0.16 300 2 64 0.16 2 71 0.00 2 77 0.16 600 1 129 0.16 1 143 0.00 1 155 0.16 1200 1 64 0.16 1 71 0.00 1 77 0.16 2400 0 129 0.16 0 143 0.00 0 155 0.16 4800 0 64 0.16 0 71 0.00 0 77 0.16 9600 0 32 -1.36 0 35 0.00 0 28 0.16 14400 0 21 -1.36 0 23 0.00 0 25 0.16 19200 0 15 1.73 0 19 0.00 0 19 -2.34 28800 0 10 -1.36 0 11 0.00 0 12 0.16 31250 0 9 0.00 0 10 0.54 0 11 0.00 38400 0 7 1.73 0 8 0.00 0 9 -2.34 P (MHz) 12.288 14 14.7456 Bit Rate (Bits/s) n N Error (%) n N Error (%) n N Error (%) 110 2 217 0.08 2 248 -0.17 3 64 0.70 150 2 159 0.00 2 181 0.16 2 191 0.00 300 2 79 0.00 2 90 0.16 2 95 0.00 600 1 159 0.00 1 181 0.16 1 191 0.00 1200 1 79 0.00 1 90 0.16 1 95 0.00 2400 0 159 0.00 0 181 0.16 0 191 0.00 4800 0 79 0.00 0 90 0.16 0 95 0.00 9600 0 39 0.00 0 45 -0.93 0 47 0.00 14400 0 26 -1.23 0 29 1.27 0 31 0.00 19200 0 19 0.00 0 22 -0.93 0 23 0.00 28800 0 12 2.56 0 14 1.27 0 15 0.00 31250 0 11 2.40 0 13 0.00 0 14 -1.70 38400 0 9 0.00 0 10 3.57 0 11 0.00 Rev. 5.00 Feb. 24, 2010 Page 366 of 950 REJ09B0177-0500 15. Serial Communication Interface (SCI) P (MHz) 16 17.2032 18 Bit Rate (Bits/s) n N Error (%) n N Error (%) n N Error (%) 110 3 70 0.03 3 75 0.48 3 79 -0.12 150 2 207 0.16 2 223 0.00 2 233 0.16 300 2 103 0.16 2 111 0.00 2 116 0.16 600 1 207 0.16 1 223 0.00 1 233 0.16 1200 1 103 0.16 1 111 0.00 1 116 0.16 2400 0 207 0.16 0 223 0.00 0 233 0.16 4800 0 103 0.16 0 111 0.00 0 116 0.16 9600 0 51 0.16 0 55 0.00 0 58 -0.69 14400 0 34 -0.79 0 36 0.90 0 38 0.16 19200 0 25 0.16 0 27 0.00 0 28 1.02 28800 0 16 2.12 0 18 -1.75 0 19 -2.34 31250 0 15 0.00 0 16 1.20 0 17 0.00 38400 0 12 0.16 0 13 0.00 0 14 -2.34 (MHz) 18.432 19.6608 20 Bit Rate (Bits/s) n N Error (%) n N Error (%) n N Error (%) 110 3 81 -0.22 3 86 0.31 3 88 -0.25 150 2 239 0.00 2 255 0.00 3 64 0.16 300 2 119 0.00 2 127 0.00 2 129 0.16 600 1 239 0.00 1 255 0.00 2 64 0.16 1200 1 119 0.00 1 127 0.00 1 129 0.16 2400 0 239 0.00 0 255 0.00 1 64 0.16 4800 0 119 0.00 0 127 0.00 0 129 0.16 9600 0 59 0.00 0 63 0.00 0 64 0.16 14400 0 39 0.00 0 42 -0.78 0 42 0.94 19200 0 29 0.00 0 31 0.00 0 32 -1.36 28800 0 19 0.00 0 20 1.59 0 21 -1.36 31250 0 17 2.40 0 19 -1.70 0 19 0.00 38400 0 14 0.00 0 15 0.00 0 15 1.73 Rev. 5.00 Feb. 24, 2010 Page 367 of 950 REJ09B0177-0500 15. Serial Communication Interface (SCI) Table 15.4 Bit Rates and BRR Settings in Synchronous Mode P (MHz) 10 12 16 Bit Rate (Bits/s) n N n N n N 250 - - 3 187 3 249 500 - - 3 93 3 1k - - 2 187 2.5 k 1 249 2 5k 1 124 1 10 k 0 249 1 74 25 k 0 99 0 119 50 k 0 49 0 59 100 k 0 24 0 250 k 0 9 500 k 0 4 1M 2.5 M 0 0* 20 n N 124 - - 2 249 - - 74 2 99 2 124 149 1 199 2 249 1 99 1 124 0 159 1 199 0 79 0 99 29 0 39 0 49 0 11 0 15 0 19 0 5 0 7 0 9 0 2 0 3 0 4 0 0* - - 0 1 0 0* 5M Legend: Blank:No setting available -:Setting possible, but error occurs *:Continuous transmission/reception not possible Note: Settings with an error of 1% or less are recommended. The BRR setting is calculated as follows: Asynchronous mode: N= P 64 x 22n-1 x B x 106 - 1 Synchronous mode: N= P 8 x 22n-1 x B x 106 - 1 B: Bit rate (bits/s) N: Baud rate generator BRR setting (0 N 255) Pf: Peripheral module operating frequency (MHz) (1/2 of system clock) n: Baud rate generator input clock (n = 0 to 3) (See the following table for the clock sources and value of n.) SMR Settings n Clock Source CKS1 CKS2 0 P 0 0 1 P/4 0 1 2 P/16 1 0 3 P/64 1 1 Rev. 5.00 Feb. 24, 2010 Page 368 of 950 REJ09B0177-0500 15. Serial Communication Interface (SCI) The bit rate error in asynchronous mode is calculated as follows: P x 106 Error (%) = - 1 x 100 2n-1 (N + 1) x B x 64 x 2 Table 15.5 indicates the maximum bit rates in asynchronous mode when the baud rate generator is being used for various frequencies. Tables 15.6 and 15.7 show the maximum rates for external clock input. Table 15.5 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode) Settings P (MHz) Maximum Bit Rate (Bits/s) n N 10 312500 0 0 11.0592 345600 0 0 12 375000 0 0 12.288 384000 0 0 14 437500 0 0 14.7456 460800 0 0 16 500000 0 0 17.2032 537600 0 0 18 562500 0 0 18.432 576000 0 0 19.6608 614400 0 0 20 625000 0 0 Table 15.6 Maximum Bit Rates during External Clock Input (Asynchronous Mode) P (MHz) External Input Clock (MHz) Maximum Bit Rate (Bits/s) 10 2.5000 156250 11.0592 2.7648 172800 12 3.0000 187500 12.288 3.0720 192000 14 3.5000 218750 14.7456 3.6864 230400 16 4.0000 250000 17.2032 4.3008 268800 18 4.5000 281250 18.432 4.6080 288000 19.6608 4.9152 307200 20 5.0000 312500 Rev. 5.00 Feb. 24, 2010 Page 369 of 950 REJ09B0177-0500 15. Serial Communication Interface (SCI) Table 15.7 Maximum Bit Rates during External Clock Input (Clock Synchronous Mode) P (MHz) External Input Clock (MHz) Maximum Bit Rate (Bits/s) 10 1.6667 1666666.7 12 2.0000 2000000.0 14 2.3333 2333333.3 16 2.6667 2666666.7 18 3.0000 3000000.0 20 3.3333 3333333.3 15.2.9 Serial Direction Control Register (SDCR) Bit: 7 6 5 4 3 2 1 0 - - - - DIR - - - Initial value: 1 1 1 1 0 0 1 0 R/W: R R R R R/W R R R The DIR bit in the serial direction control register (SDCR) selects LSB-first or MSB-first transfer. With an 8-bit data length, LSB-first/MSB-first selection is available regardless of the communication mode. With a 7-bit data length, LSBfirst transfer must be selected. The description in this section assumes LSB-first transfer. The CPU can always read from SDCR. The CPU should only write to SDCR when making initial settings. Do not use the CPU to write to SDCR during transmit, receive, or transmit/receive operation. SDCR is initialized to H'F2 by a power-on reset and in the hardware standby mode. The value is not retained in software standby mode and it is initialized after release. It is not initialized by a manual reset. * Bits 7-4--Reserved: The write value should always be 1. If 0 is written to these bits, correct operation cannot be guaranteed. * Bit 3--Data Transfer Direction (DIR): Selects the serial/parallel conversion format. Valid for an 8-bit transmit/receive format. Bit 3: DIR 0 Description TDR contents are transmitted in LSB-first order (Initial value) Receive data is stored in RDR in LSB-first order 1 TDR contents are transmitted in MSB-first order Receive data is stored in RDR in MSB-first order * Bit 2--Reserved: The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. * Bit 1--Reserved: This bit is always read as 1, and cannot be modified. * Bit 0--Reserved: The write value should always be 0. If 1 is written to this bit, correct operation cannot be guaranteed. 15.2.10 Inversion of SCK Pin Signal The signal input from the SCK pin and the signal output from the SCK pin can be inverted by means of a port control register setting. See section 22, Pin function Controller (PFC), for details. Rev. 5.00 Feb. 24, 2010 Page 370 of 950 REJ09B0177-0500 15. Serial Communication Interface (SCI) 15.3 Operation 15.3.1 Overview For serial communication, the SCI has an asynchronous mode in which characters are synchronized individually, and a synchronous mode in which communication is synchronized with clock pulses. Asynchronous synchronous mode and the transmission format are selected in the serial mode register (SMR), as shown in table 15.8. The SCI clock source is selected by the C/A bit in the serial mode register (SMR) and the CKE1 and CKE0 bits in the serial control register (SCR), as shown in table 15.9. Asynchronous Mode: * Data length is selectable: seven or eight bits. * Parity and multiprocessor bits are selectable, as well as the stop bit length (one or two bits). These selections determine the transmit/receive format and character length. * In receiving, it is possible to detect framing errors (FER), parity errors (PER), overrun errors (ORER), and the break state. * An internal or external clock can be selected as the SCI clock source. When an internal clock is selected, the SCI operates using the on-chip baud rate generator clock, and can output a clock with a frequency matching the bit rate. When an external clock is selected, the external clock input must have a frequency 16 times the bit rate. (The onchip baud rate generator is not used.) Synchronous Mode: * The communication format has a fixed 8-bit data length. * In receiving, it is possible to detect overrun errors (ORER). * An internal or external clock can be selected as the SCI clock source. When an internal clock is selected, the SCI operates using the on-chip baud rate generator clock, and outputs a serial clock signal to external devices. When an external clock is selected, the SCI operates on the input serial clock. The on-chip baud rate generator is not used. Rev. 5.00 Feb. 24, 2010 Page 371 of 950 REJ09B0177-0500 15. Serial Communication Interface (SCI) Table 15.8 Serial Mode Register Settings and SCI Communication Formats SMR Settings SCI Communication Format Mode Bit 7 C/A Bit 6 CHR Bit 5 PE Bit 2 MP Bit 3 STOP Data Length Parity Bit Multiprocessor Bit Stop Bit Length Asynchronous 0 0 0 0 0 8-bit Absent Absent 1 bit 1 1 0 0 0 2 bits 1 bit Present 1 1 2 bits 7-bit Absent 1 bit 1 2 bits Present 0 1 1 bit 2 bits 1 Asynchronous (multiprocessor format) 0 1 * * 1 1 * 0 * * 1 8-bit Absent Present * 1 bit 2 bits 1 bit 7-bit 1 * Synchronous 0 2 bits 8-bit * Absent None Note: Asterisks (*) in the table indicate don't-care bits. Table 15.9 SMR and SCR Settings and SCI Clock Source Selection SMR SCR Settings SCI Transmit/Receive Clock Mode Bit 7 C/A Bit 1 CKE1 Bit 0 CKE0 Clock Source SCK Pin Function* Asynchronous 0 0 0 Internal SCI does not use the SCK pin 1 1 0 Outputs a clock with frequency matching the bit rate External Inputs a clock with frequency 16 times the bit rate Internal Outputs the serial clock or the inverted serial clock External Inputs the serial clock or the inverted serial clock 1 Synchronous 1 0 0 1 1 0 1 Note: * Select the function in combination with the pin function controller (PFC). Rev. 5.00 Feb. 24, 2010 Page 372 of 950 REJ09B0177-0500 15. Serial Communication Interface (SCI) 15.3.2 Operation in Asynchronous Mode In asynchronous mode, each transmitted or received character begins with a start bit and ends with a stop bit. Serial communication is synchronized one character at a time. The transmitting and receiving sections of the SCI are independent, so full duplex communication is possible. The transmitter and receiver are both double buffered, so data can be written and read while transmitting and receiving are in progress, enabling continuous transmitting and receiving. Figure 15.2 shows the general format of asynchronous serial communication. In asynchronous serial communication, the communication line is normally held in the marking (high) state. The SCI monitors the line and starts serial communication when the line goes to the space (low) state, indicating a start bit. One serial character consists of a start bit (low), data (LSB first), parity bit (high or low), and stop bit (high), in that order. When receiving in asynchronous mode, the SCI synchronizes on the falling edge of the start bit. The SCI samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate. Receive data is latched at the center of each bit. (LSB) 1 Serial data 0 D0 Idling (marking) 1 (MSB) D1 D2 D3 D4 D5 Start bit D6 D7 0/1 1 1 Parity bit Stop bit 1 or no bit 1 or 2 bits Transmit/receive data 1 bit 7 or 8 bits One unit of communication data (character or frame) Figure 15.2 Data Format in Asynchronous Communication (Example: 8-bit Data with Parity and Two Stop Bits) Rev. 5.00 Feb. 24, 2010 Page 373 of 950 REJ09B0177-0500 15. Serial Communication Interface (SCI) Transmit/Receive Formats: Table 15.10 shows the 12 communication formats that can be selected in asynchronous mode. The format is selected by settings in the serial mode register (SMR). Table 15.10 Serial Communication Formats (Asynchronous Mode) SMR Bits Serial Transmit/Receive Format and Frame Length CHR PE MP STOP 1 2 3 4 5 6 7 8 9 10 11 12 0 0 0 0 START 8-bit data STOP 0 0 0 1 START 8-bit data STOP STOP 0 1 0 0 START 8-bit data P STOP 0 1 0 1 START 8-bit data P STOP STOP 1 0 0 0 START 7-bit data STOP 1 0 0 1 START 7-bit data STOP STOP 1 1 0 0 START 7-bit data P STOP 1 1 0 1 START 7-bit data P STOP STOP 0 - 1 0 START 8-bit data MPB STOP 0 - 1 1 START 8-bit data MPB STOP STOP 1 - 1 0 START 7-bit data MPB STOP 1 - 1 1 START 7-bit data MPB STOP STOP Legend: START: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit Note: -: Don't-care bits. Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in the serial mode register (SMR) and bits CKE1 and CKE0 in the serial control register (SCR) (table 15.9). When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the desired bit rate. When the SCI operates on an internal clock, it can output a clock signal at the SCK pin. The frequency of this output clock is equal to the bit rate. The phase is aligned as in figure 15.3 so that the rising edge of the clock occurs at the center of each transmit data bit. Rev. 5.00 Feb. 24, 2010 Page 374 of 950 REJ09B0177-0500 15. Serial Communication Interface (SCI) 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 frame Figure 15.3 Output Clock and Communication Data Phase Relationship (Asynchronous Mode) Data Transmit/Receive Operation SCI Initialization (Asynchronous Mode): Before transmitting or receiving, clear the TE and RE bits to 0 in the serial control register (SCR), then initialize the SCI as follows. When changing the operation mode or communication format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing TE to 0 sets TDRE to 1 and initializes the transmit shift register (TSR). Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags and receive data register (RDR), which retain their previous contents. When an external clock is used, the clock should not be stopped during initialization or subsequent operation. SCI operation becomes unreliable if the clock is stopped. Figure 15.4 is a sample flowchart for initializing the SCI. The procedure is as follows (the steps correspond to the numbers in the flowchart): Initialize Clear TE and RE bits to 0 in SCR Set CKE1 and CKE0 bits in SCR (TE and RE bits are 0) 1 Select transmit/receive format in SMR and SDCR 2 Set value in BRR 3 Wait 1-bit interval elapsed? No Yes Set TE or RE to 1 in SCR; Set RIE, TIE, TEIE, and MPIE as necessary 4 1. Select the clock source in the serial control register (SCR). Leave RIE, TIE, TEIE, MPIE, TE, and RE cleared to 0. If clock output is selected in asynchronous mode, clock output starts immediately after the setting is made in SCR. 2. Select the communication format in the serial mode register (SMR) and serial direction control register (SDCR). 3. Write the value corresponding to the bit rate in the bit rate register (BRR) (unless an external clock is used). 4. Wait for at least the interval required to transmit or receive one bit, then set TE or RE in the serial control register (SCR) to 1.* Also set RIE, TIE, TEIE, and MPIE as necessary. Setting TE or RE enables the SCI to use the TxD or RxD pin. Note: * In simultaneous transmit/receive operation, the TE bit and RE bit must be cleared to 0 or set to 1 simultaneously. End Figure 15.4 Sample Flowchart for SCI Initialization Transmitting Serial Data (Asynchronous Mode): Figure 15.5 shows a sample flowchart for transmitting serial data. The procedure is as follows (the steps correspond to the numbers in the flowchart): Rev. 5.00 Feb. 24, 2010 Page 375 of 950 REJ09B0177-0500 15. Serial Communication Interface (SCI) Initialization 1 Start of transmission Read TDRE bit in SSR 2 No TDRE = 1? Yes Write transmit data to TDR and clear TDRE bit in SSR to 0 3 All data transmitted? No Yes Read TEND bit in SSR No TEND = 1? 1. SCI initialization: Set the TxD pin using the PFC. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. 2. SCI status check and transmit data write: Read the serial status register (SSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (TDR) and clear TDRE to 0. 3. Continue transmitting serial data: Read the TDRE bit to check whether it is safe to write (if it reads 1); if so, write data in TDR, then clear TDRE to 0. When the DMAC is started by a transmit-data-empty interrupt request (TXI) in order to write data in TDR, the TDRE bit is checked and cleared automatically. 4. To output a break at the end of serial transmission, first clear the port data register (DR) to 0, then clear the TE bit to 0 in SCR and use the PFC to establish the TxD pin as an output port. Yes No Output break signal? 4 Yes Note: Do not write to SMR, SCR, BRR, or SDCR between the start and the end of a transmit operation. However, this does not apply to operation 5. Clear port DR to 0 Clear TE bit in SCR to 0; select theTxD pin as an output port with the PFC 5 End of transmission Figure 15.5 Sample Flowchart for Transmitting Serial Data In transmitting serial data, the SCI operates as follows: 1. The SCI monitors the TDRE bit in SSR. When TDRE is cleared to 0, the SCI recognizes that the transmit data register (TDR) contains new data, and loads this data from TDR into the transmit shift register (TSR). 2. After loading the data from TDR into TSR, the SCI sets the TDRE bit to 1 and starts transmitting. If the transmit-dataempty interrupt enable bit (TIE) is set to 1 in SCR, the SCI requests a transmit-data-empty interrupt (TXI) at this time. Serial transmit data is transmitted in the following order from the TxD pin: a. Start bit: one 0-bit is output. b. Transmit data: seven or eight bits of data are output, LSB first. c. Parity bit or multiprocessor bit: one parity bit (even or odd parity) or one multiprocessor bit is output. Formats in which neither a parity bit nor a multiprocessor bit is output can also be selected. d. Stop bit: one or two 1-bits (stop bits) are output. Rev. 5.00 Feb. 24, 2010 Page 376 of 950 REJ09B0177-0500 15. Serial Communication Interface (SCI) e. Marking: output of 1-bits continues until the start bit of the next transmit data. 3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI loads new data from TDR into TSR, outputs the stop bit, then begins serial transmission of the next frame. If TDRE is 1, the SCI sets the TEND bit to 1 in SSR, outputs the stop bit, then continues output of 1-bits (marking). If the transmit-end interrupt enable bit (TEIE) in SCR is set to 1, a transmit-end interrupt (TEI) is requested. Figure 15.6 shows an example of SCI transmit operation in asynchronous mode. 1 Serial data Start bit 0 Parity Stop Start bit bit bit Data D0 D1 D7 0/1 1 0 Data D0 D1 Parity Stop bit bit D7 0/1 1 1 Idling (marking) TDRE TEND TXI TXI interrupt interrupt handler writes request data in TDR and clears TDRE to 0 TXI interrupt request TEI interrupt request 1 frame Figure 15.6 SCI Transmit Operation in Asynchronous Mode (Example: 8-Bit Data with Parity and One Stop Bit) Receiving Serial Data (Asynchronous Mode): Figures 15.7 and 15.8 show a sample flowchart for receiving serial data. The procedure is as follows (the steps correspond to the numbers in the flowchart). Rev. 5.00 Feb. 24, 2010 Page 377 of 950 REJ09B0177-0500 15. Serial Communication Interface (SCI) Initialization 1 Start of reception Read ORER, PER, and FER bits in SSR PER, FER, ORER = 1? Yes 2 Error handling No Read RDRF bit in SSR No 3 RDRF = 1? Yes Read receive data in RDR and clear RDRF bit in SSR to 0 No 4 All data received? Yes Clear RE bit in SCR to 0 5 1. SCI initialization: Set the RxD pin using the PFC. 2. Receive error handling and break detection: If a receive error occurs, read the ORER, PER, and FER bits of SSR to identify the error. After executing the necessary error handling, clear ORER, PER, and FER all to 0. Receiving cannot resume if ORER, PER or FER remain set to 1. When a framing error occurs, the RxD pin can be read to detect the break state. 3. SCI status check and receive-data read: Read the serial status register (SSR), check that RDRF is set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0. The RXI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1. 4. Continue receiving serial data: Read RDR and the RDRF bit and clear RDRF to 0 before the stop bit of the current frame is received. If the DMAC is started by a receive-data-full interrupt (RXI) to read RDR, the RDRF bit is cleared automatically so this step is unnecessary. Note: Do not write to SMR, SCR, BRR, or SDCR between the start and the end of a receive operation. However, this does not apply to operation 5. End of reception Figure 15.7 Sample Flowchart for Receiving Serial Data (1) Rev. 5.00 Feb. 24, 2010 Page 378 of 950 REJ09B0177-0500 15. Serial Communication Interface (SCI) Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Break? Yes No Framing error handling No Clear RE bit in SCR to 0 5 PER = 1? Yes Parity error handling Clear ORER, PER, and FER to 0 in SSR Note: Do not write to SMR, SCR, BRR, or SDCR between the start and the end of a receive operation. However, this does not apply to operation 5. End Figure 15.8 Sample Flowchart for Receiving Serial Data (2) In receiving, the SCI operates as follows: 1. The SCI monitors the communication line. When it detects a start bit (0), the SCI synchronizes internally and starts receiving. 2. Receive data is shifted into RSR in order from the LSB to the MSB. 3. The parity bit and stop bit are received. After receiving these bits, the SCI makes the following checks: a. Parity check. The number of 1s in the receive data must match the even or odd parity setting of the O/E bit in SMR. b. Stop bit check. The stop bit value must be 1. If there are two stop bits, only the first stop bit is checked. c. Status check. RDRF must be 0 so that receive data can be loaded from RSR into RDR. If the data passes these checks, the SCI sets RDRF to 1 and stores the receive data in RDR. If one of the checks fails (receive error), the SCI operates as indicated in table 15.11. Note: When a receive error occurs, further receiving is disabled. While receiving, the RDRF bit is not set to 1, so be sure to clear the error flags. Rev. 5.00 Feb. 24, 2010 Page 379 of 950 REJ09B0177-0500 15. Serial Communication Interface (SCI) 4. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in SCR, the SCI requests a receive-data-full interrupt (RXI). If one of the error flags (ORER, PER, or FER) is set to 1 and the receive-data-full interrupt enable bit (RIE) in SCR is also set to 1, the SCI requests a receive-error interrupt (ERI). Table 15.11 Receive Error Conditions and SCI Operation Receive Error Abbreviation Condition Data Transfer Overrun error ORER Receiving of next data ends while RDRF is still set to 1 in SSR Receive data not loaded from RSR into RDR Framing error FER Stop bit is 0 Receive data loaded from RSR into RDR Parity error PER Parity of receive data differs from even/odd parity setting in SMR Receive data loaded from RSR into RDR Figure 15.9 shows an example of SCI receive operation in asynchronous mode. 1 Serial data Start bit 0 Parity Stop Start bit bit bit Data D0 D1 D7 0/1 1 0 Parity Stop bit bit Data D0 D1 D7 0/1 1 1 Idling (marking) RDRF RXI interrupt request FER 1 frame RXI interrupt handler reads data in RDR and clears RDRF to 0. Framing error generates ERI interrupt request. Figure 15.9 SCI Receive Operation (Example: 8-Bit Data with Parity and One Stop Bit) 15.3.3 Multiprocessor Communication The multiprocessor communication function enables several processors to share a single serial communication line for sending and receiving data. The processors communicate in the asynchronous mode using a format with an additional multiprocessor bit (multiprocessor format). In multiprocessor communication, each receiving processor is addressed by a unique ID. A serial communication cycle consists of an ID-sending cycle that identifies the receiving processor, and a data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from data-sending cycles. The transmitting processor starts by sending the ID of the receiving processor with which it wants to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor sends transmit data with the multiprocessor bit cleared to 0. Receiving processors skip incoming data until they receive data with the multiprocessor bit set to 1. When they receive data with the multiprocessor bit set to 1, receiving processors compare the data with their IDs. The receiving processor with a matching ID continues to receive further incoming data. Processors with IDs not matching the received data skip further incoming data until they again receive data with the multiprocessor bit set to 1. Multiple processors can send and receive data in this way. Figure 15.10 shows an example of communication among processors using the multiprocessor format. Rev. 5.00 Feb. 24, 2010 Page 380 of 950 REJ09B0177-0500 15. Serial Communication Interface (SCI) Communication Formats: Four formats are available. Parity-bit settings are ignored when the multiprocessor format is selected. For details see table 15.8. Clock: See the description in the asynchronous mode section. Transmitting processor Serial communication line Receiving processor A Receiving processor B Receiving processor C Receiving processor D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial data H'01 H'AA (MPB = 1) ID-transmit cycle: receiving processor address Legend: MPB: Multiprocessor bit (MPB = 0) Data-transmit cycle: data sent to receiving processor specified by ID Figure 15.10 Communication among Processors Using Multiprocessor Format (Example: Sending Data H'AA to Receiving Processor A) Data Transmit/Receive Operation Transmitting Multiprocessor Serial Data: Figure 15.11 shows a sample flowchart for transmitting multiprocessor serial data. The procedure is as follows (the steps correspond to the numbers in the flowchart): Rev. 5.00 Feb. 24, 2010 Page 381 of 950 REJ09B0177-0500 15. Serial Communication Interface (SCI) Initialization 1 Start of transmission Read TDRE bit in SSR TDRE = 1? 2 No Yes Write transmit data in TDR and set MPBT in SSR Clear TDRE bit to 0 All data transmitted? No 3 Yes Read TEND bit in SSR TEND = 1? No Note: Do not write to SMR, SCR, BRR, or SDCR between the start and the end of a transmit operation. However, this does not apply to operation 5. Yes Output break signal? 1. SCI initialization: Set the TxD pin using the PFC. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. 2. SCI status check and transmit data write: Read the serial status register (SSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (TDR). Also set MPBT (multiprocessor bit transfer) to 0 or 1 in SSR. Finally, clear TDRE to 0. 3. Continue transmitting serial data: Read the TDRE bit to check whether it is safe to write (if it reads 1); if so, write data in TDR, then clear TDRE to 0. When the DMAC is started by a transmit-data-empty interrupt request (TXI) to write data in TDR, the TDRE bit is checked and cleared automatically. 4. Output a break at the end of serial transmission: Set the data register (DR) of the port to 0, then clear TE to 0 in SCR and set the TxD pin function as output port with the PFC. No 4 Yes Clear port DR to 0 Clear TE bit in SCR to 0; select theTxD pin function as an output port with the PFC 5 End of transmission Figure 15.11 Sample Flowchart for Transmitting Multiprocessor Serial Data Rev. 5.00 Feb. 24, 2010 Page 382 of 950 REJ09B0177-0500 15. Serial Communication Interface (SCI) In transmitting serial data, the SCI operates as follows: 1. The SCI monitors the TDRE bit in SSR. When TDRE is cleared to 0 the SCI recognizes that the transmit data register (TDR) contains new data, and loads this data from TDR into the transmit shift register (TSR). 2. After loading the data from TDR into TSR, the SCI sets the TDRE bit to 1 and starts transmitting. If the transmit-dataempty interrupt enable bit (TIE) in SCR is set to 1, the SCI requests a transmit-data-empty interrupt (TXI) at this time. Serial transmit data is transmitted in the following order from the TxD pin: a. Start bit: one 0-bit is output. b. Transmit data: seven or eight bits are output, LSB first. c. Multiprocessor bit: one multiprocessor bit (MPBT value) is output. d. Stop bit: one or two 1-bits (stop bits) are output. e. Marking: output of 1-bits continues until the start bit of the next transmit data. 3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI loads data from TDR into TSR, outputs the stop bit, then begins serial transmission of the next frame. If TDRE is 1, the SCI sets the TEND bit in SSR to 1, outputs the stop bit, then continues output of 1-bits in the marking state. If the transmit-end interrupt enable bit (TEIE) in SCR is set to 1, a transmit-end interrupt (TEI) is requested at this time. Figure 15.12 shows an example of SCI receive operation in the multiprocessor format. 1 Multiprocessor bit Stop Start Data bit bit Start bit Serial data 0 D0 D1 D7 0/1 1 0 Multiprocessor bit Stop Data bit D0 D1 D7 0/1 1 1 Idling (marking) TDRE TEND TXI interrupt request TXI interrupt handler writes data in TDR and clears TDRE to 0 TXI interrupt request TEI interrupt request 1 frame Figure 15.12 SCI Multiprocessor Transmit Operation (Example: 8-Bit Data with Multiprocessor Bit and One Stop Bit) Receiving Multiprocessor Serial Data: Figures 15.13 and 15.14 show a sample flowchart for receiving multiprocessor serial data. The procedure for receiving multiprocessor serial data is as follows (the steps correspond to the numbers in the flowchart): Rev. 5.00 Feb. 24, 2010 Page 383 of 950 REJ09B0177-0500 15. Serial Communication Interface (SCI) Initialization 1 Start of reception Set MPIE bit in SCR to 1 1. SCI initialization: Set the RxD pin using the PFC. 2. ID receive cycle: Set the MPIE bit in the serial control register (SCR) to 1. 3. SCI status check and compare to ID reception: Read the serial status register (SSR), check that RDRF is set to 1, then read data from the receive data register (RDR) and compare with the processor's own ID. If the ID does not match the receive data, set MPIE to 1 again and clear RDRF to 0. If the ID matches the receive data, clear RDRF to 0. 4. Receive error handling and break detection: If a receive error occurs, read the ORER and FER bits in SSR to identify the error. After executing the necessary error handling, clear both ORER and FER to 0. Receiving cannot resume if ORER or FER remain set to 1. When a framing error occurs, the RxD pin can be read to detect the break state. 5. SCI status check and data receiving: Read SSR, check that RDRF is set to 1, then read data from the receive data register (RDR). 2 Read ORER and FER bits in SSR FER = 1? or ORER =1? Yes No Read RDRF bit in SSR No 3 RDRF = 1? Yes Read receive data from RDR No Is ID the station's ID? Yes Read ORER and FER bits in SSR FER = 1? or ORER =1? Yes No Read RDRF bit in SSR RDRF = 1? 5 Note: Do not write to SMR, SCR, BRR, or SDCR between the start and the end of a receive operation. However, this does not apply to operation 6. No Yes Read receive data from RDR 4 No Error handling All data received? Yes Clear RE bit in SCR to 0 6 End of reception Figure 15.13 Sample Flowchart for Receiving Multiprocessor Serial Data (1) Rev. 5.00 Feb. 24, 2010 Page 384 of 950 REJ09B0177-0500 15. Serial Communication Interface (SCI) Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Break? Yes No Framing error handling Clear ORER and FER bits in SSR to 0 End Clear RE bit in SCR to 0 6 Note: Do not write to SMR, SCR, BRR, or SDCR between the start and the end of a receive operation. However, this does not apply to operation 6. Figure 15.14 Sample Flowchart for Receiving Multiprocessor Serial Data (2) Figure 15.15 shows examples of SCI receive operation using a multiprocessor format. Rev. 5.00 Feb. 24, 2010 Page 385 of 950 REJ09B0177-0500 15. Serial Communication Interface (SCI) 1 Serial data Start bit Data (ID1) 0 D0 D1 Stop Start Data MPB bit bit (data 1) D7 1 1 0 D0 D1 Stop MPB bit D7 0 1 1 Idling (marking) MPB MPIE RDRF RDR value ID1 RXI interrupt request (multiprocessor interrupt), MPIE = 0 RXI interrupt handler reads data in RDR and clears RDRF to 0 Not station's ID, so MPIE is set to 1 again No RXI interrupt, RDR maintains state (A) ID Does Not Match 1 Serial data Start bit 0 Data (ID2) D0 D1 Stop Start Data MPB bit bit (data 2) D7 1 1 0 D0 D1 Stop MPB bit D7 0 1 1 Idling (marking) MPB MPIE RDRF RDR value ID1 RXI interrupt request (multiprocessor interrupt), MPIE = 0 ID2 RXI interrupt handler reads data in RDR and clears RDRF to 0 Station's ID, so receiving MPIE continues, with data bit is again received by the RXI set to 1 interrupt processing routine (B) ID Matches Figure 15.15 SCI Receive Operation (Example: 8-Bit Data with Multiprocessor Bit and One Stop Bit) Rev. 5.00 Feb. 24, 2010 Page 386 of 950 REJ09B0177-0500 Data 2 15. Serial Communication Interface (SCI) 15.3.4 Synchronous Operation In synchronous mode, the SCI transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCI transmitter and receiver are independent, so full duplex communication is possible while sharing the same clock. The transmitter and receiver are also double buffered, so continuous transmitting or receiving is possible by reading or writing data while transmitting or receiving is in progress. Figure 15.16 shows the general format in synchronous serial communication. Transfer direction One unit (character or frame) of communication data * * Serial clock LSB Serial data Bit 0 MSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Note: * High except in continuous transmitting or receiving. Figure 15.16 Data Format in Synchronous Communication In synchronous serial communication, each data bit is output on the communication line from one falling edge of the serial clock to the next. Data is guaranteed valid at the rising edge of the serial clock. In each character, the serial data bits are transmitted in order from the LSB (first) to the MSB (last). After output of the MSB, the communication line remains in the state of the MSB. In synchronous mode, the SCI transmits or receives data by synchronizing with the rise of the serial clock. Communication Format: The data length is fixed at eight bits. No parity bit or multiprocessor bit can be added. Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in the serial mode register (SMR) and bits CKE1 and CKE0 in the serial control register (SCR). See table 15.9. When the SCI operates on an internal clock, it outputs the clock signal at the SCK pin. Eight clock pulses are output per transmitted or received character. When the SCI is not transmitting or receiving, the clock signal remains in the high state. An overrun error occurs only during the receive operation, and the serial clock is output until the RE bit is cleared to 0. To perform a receive operation in one-character units, select an external clock for the clock source. Transmitting and Receiving Data SCI Initialization (Synchronous Mode): Before transmitting or receiving, software must clear the TE and RE bits to 0 in the serial control register (SCR), then initialize the SCI as follows. When changing the mode or communication format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing TE to 0 sets TDRE to 1 and initializes the transmit shift register (TSR). Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags and receive data register (RDR), which retain their previous contents. Figure 15.17 is a sample flowchart for initializing the SCI. Rev. 5.00 Feb. 24, 2010 Page 387 of 950 REJ09B0177-0500 15. Serial Communication Interface (SCI) Start of initialization Clear TE and RE bits to 0 in SCR Set CKE1 and CKE0 bits in SCR (RIE, TIE, TEIE, MPIE,TE, and RE are 0) 1 Select transmit/receive format in SMR and SDCR 2 Set value in BRR 3 Wait 1-bit interval elapsed? Note: * In simultaneous transmit/receive operation, the TE bit and RE bit must be cleared to 0 or set to 1 simultaneously. No Yes Set TE and RE to 1 in SCR; Set RIE, TIE, TEIE, and MPIE bits 1. Select the clock source in the serial control register (SCR). Leave RIE, TIE, TEIE, MPIE, TE, and RE cleared to 0. 2. Select the communication format in the serial mode register (SMR) and serial direction control register (SDCR). 3. Write the value corresponding to the bit rate in the bit rate register (BRR) (unless an external clock is used). 4. Wait for at least the interval required to transmit or receive one bit, then set TE or RE in the serial control register (SCR) to 1.* Also set RIE, TIE, TEIE, and MPIE. The TxD, RxD pins becomes usable in response to the PFC corresponding bits and the TE, RE bit settings. 4 End of initialization Figure 15.17 Sample Flowchart for SCI Initialization Rev. 5.00 Feb. 24, 2010 Page 388 of 950 REJ09B0177-0500 15. Serial Communication Interface (SCI) Transmitting Serial Data (Synchronous Mode): Figure 15.18 shows a sample flowchart for transmitting serial data. The procedure is as follows (the steps correspond to the numbers in the flowchart): Initialization 1 Start of transmission 2 Read TDRE flag in SSR No TDRE = 1? Yes Write transmit data in TDR and clear TDRE flag to 0 in SSR 1. SCI initialization: Set the TxD pin function with the PFC. 2. SCI status check and transmit data write: Read SSR, check that the TDRE flag is 1, then write transmit data in TDR and clear the TDRE flag to 0. 3. To continue transmitting serial data: After checking that the TDRE flag is 1, indicating that data can be written, write data in TDR, then clear the TDRE flag to 0. When the DMAC is activated by a transmit-data-empty interrupt request (TXI) to write data in TDR, the TDRE flag is checked and cleared automatically. Note: Do not write to SMR, SCR, BRR, or SDCR between the start and the end of a transmit operation. However, this does not apply to operation 4. No All data transmitted? 3 Yes Read TEND flag in SSR TEND = 1? No Yes Clear TE bit to 0 in SCR 4 End of transmission Figure 15.18 Sample Flowchart for Serial Transmitting Rev. 5.00 Feb. 24, 2010 Page 389 of 950 REJ09B0177-0500 15. Serial Communication Interface (SCI) Figure 15.19 shows an example of SCI transmit operation. Transfer direction Serial clock LSB Serial data Bit 0 MSB Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt request TXI interrupt TXI interrupt handler writes request data in TDR and clears TDRE to 0 TEI interrupt request 1 frame Figure 15.19 Example of SCI Transmit Operation SCI serial transmission operates as follows. 1. The SCI monitors the TDRE bit in SSR. When TDRE is cleared to 0 the SCI recognizes that the transmit data register (TDR) contains new data and loads this data from TDR into the transmit shift register (TSR). 2. After loading the data from TDR into TSR, the SCI sets the TDRE bit to 1 and starts transmitting. If the transmit-dataempty interrupt enable bit (TIE) in SCR is set to 1, the SCI requests a transmit-data-empty interrupt (TXI) at this time. If clock output mode is selected, the SCI outputs eight serial clock pulses. If an external clock source is selected, the SCI outputs data in synchronization with the input clock. Data is output from the TxD pin in order from the LSB (bit 0) to the MSB (bit 7). 3. The SCI checks the TDRE bit when it outputs the MSB (bit 7). If TDRE is 0, the SCI loads data from TDR into TSR, then begins serial transmission of the next frame. If TDRE is 1, the SCI sets the TEND bit in SSR to 1, transmits the MSB, then holds the transmit data pin (TxD) in the MSB state. If the transmit-end interrupt enable bit (TEIE) in SCR is set to 1, a transmit-end interrupt (TEI) is requested at this time. 4. After the end of serial transmission, the SCK pin is held in the high state. Receiving Serial Data (Synchronous Mode): Figures 15.20 and 15.21 show a sample flowchart for receiving serial data. When switching from asynchronous mode to synchronous mode, make sure that ORER, PER, and FER are cleared to 0. If PER or FER is set to 1, the RDRF bit will not be set and both transmitting and receiving will be disabled. The procedure for receiving serial data is as follows (the steps correspond to the numbers in the flowchart): Rev. 5.00 Feb. 24, 2010 Page 390 of 950 REJ09B0177-0500 15. Serial Communication Interface (SCI) Initialization 1 Start of reception Read ORER bit in SSR Yes ORER = 1? 2 No Error handling Read RDRF bit in SSR No 3 1. SCI initialization: Set the RxD pin using the PFC. 2. Receive error handling: If a receive error occurs, read the ORER bit in SSR to identify the error. After executing the necessary error handling, clear ORER to 0. Transmitting/receiving cannot resume if ORER remains set to 1. 3. SCI status check and receive data read: Read the serial status register (SSR), check that RDRF is set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0. The RXI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1. 4. Continue receiving serial data: Read RDR, and clear RDRF to 0 before the MSB (bit 7) of the current frame is received. If the DMAC is started by a receive-data-full interrupt (RXI) to read RDR, the RDRF bit is cleared automatically so this step is unnecessary. RDRF = 1? Yes Read receive data from RDR and clear RDRF bit in SSR to 0 4 No All data received? Yes Clear RE bit in SCR to 0 5 End of reception Note: Do not write to SMR, SCR, BRR, or SDCR between the start and the end of a receive operation. However, this does not apply to operation 5. Figure 15.20 Sample Flowchart for Serial Receiving (1) Error handling Overrun error handling Clear ORER bit in SSR to 0 End Figure 15.21 Sample Flowchart for Serial Receiving (2) Rev. 5.00 Feb. 24, 2010 Page 391 of 950 REJ09B0177-0500 15. Serial Communication Interface (SCI) Figure 15.22 shows an example of the SCI receive operation. Transfer direction Serial clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RDRF ORER RXI interrupt request Read data with RXI interrupt processing routine and clear RDRF bit to 0 RXI interrupt request ERI interrupt request generated by overrun error 1 frame Figure 15.22 Example of SCI Receive Operation In receiving, the SCI operates as follows: 1. The SCI synchronizes with serial clock input or output and initializes internally. 2. Receive data is shifted into RSR in order from the LSB to the MSB. After receiving the data, the SCI checks that RDRF is 0 so that receive data can be loaded from RSR into RDR. If this check passes, the SCI sets RDRF to 1 and stores the receive data in RDR. If the check does not pass (receive error), the SCI operates as indicated in table 15.11 and no further transmission or reception is possible. If the error flag is set to 1, the RDRF bit is not set to 1 during reception, even if the RDRF bit is 0 cleared. When restarting reception, be sure to clear the error flag. 3. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in SCR, the SCI requests a receive-data-full interrupt (RXI). If the ORER bit is set to 1 and the receive-data-full interrupt enable bit (RIE) in SCR is also set to 1, the SCI requests a receive-error interrupt (ERI). Rev. 5.00 Feb. 24, 2010 Page 392 of 950 REJ09B0177-0500 15. Serial Communication Interface (SCI) Transmitting and Receiving Serial Data Simultaneously (Synchronous Mode): Figure 15.23 shows a sample flowchart for transmitting and receiving serial data simultaneously. The procedure is as follows (the steps correspond to the numbers in the flowchart): Initialization 1 Start of transmission/reception Read TDRE bit in SSR No 2 TDRE = 1? Yes Write transmit data in TDR and clear TDRE bit in SSR to 0 Read ORER bit in SSR ORER = 1? Yes 3 Error handling No Read RDRF bit in SSR No 4 RDRF = 1? Yes Read receive data in RDR, and clear RDRF bit in SSR to 0 No 5 All data transmitted/ received? 1. SCI initialization: Set the TxD and RxD pins using the PFC. 2. SCI status check and transmit data write: Read the serial status register (SSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (TDR) and clear TDRE to 0. The TXI interrupt can also be used to determine if the TDRE bit has changed from 0 to 1. 3. Receive error handling: If a receive error occurs, read the ORER bit in SSR to identify the error. After executing the necessary error handling, clear ORER to 0. Transmitting/receiving cannot resume if ORER remains set to 1. 4. SCI status check and receive data read: Read the serial status register (SSR), check that RDRF is set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0. The RXI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1. 5. Continue transmitting and receiving serial data: Read the RDRF bit and RDR, and clear RDRF to 0 before the MSB (bit 7) of the current frame is received. Also read the TDRE bit to check whether it is safe to write (if it reads 1); if so, write data in TDR, then clear TDRE to 0 before the MSB (bit 7) of the current frame is transmitted. When the DMAC is started by a transmitdata-empty interrupt request (TXI) to write data in TDR, the TDRE bit is checked and cleared automatically. When the DMAC is started by a receive-data-full interrupt (RXI) to read RDR, the RDRF bit is cleared automatically. Yes Clear TE and RE bits in SCR to 0 6 End of transmission/reception Notes: 1. In switching from transmitting or receiving to simultaneous transmitting and receiving, clear both TE and RE to 0, then set both TE and RE to 1 simultaneously. 2. Do not write to SMR, SCR, BRR, or SDCR between the start and the end of a transmit/receive operation. However, this does not apply to operation 6. Figure 15.23 Sample Flowchart for Serial Transmission and Reception 15.4 SCI Interrupt Sources and the DMAC The SCI has four interrupt sources: transmit-end (TEI), receive-error (ERI), receive-data-full (RXI), and transmit-dataempty (TXI). Table 15.12 lists the interrupt sources and indicates their priority. These interrupts can be enabled and disabled by the TIE, RIE, and TEIE bits in the serial control register (SCR). Each interrupt request is sent separately to the interrupt controller. TXI is requested when the TDRE bit in SSR is set to 1. TXI can start the direct memory access controller (DMAC) to transfer data. TDRE is automatically cleared to 0 when the DMAC writes data in the transmit data register (TDR). RXI is requested when the RDRF bit in SSR is set to 1. RXI can start the DMAC to transfer data. RDRF is automatically cleared to 0 when the DMAC reads the receive data register (RDR). Rev. 5.00 Feb. 24, 2010 Page 393 of 950 REJ09B0177-0500 15. Serial Communication Interface (SCI) ERI is requested when the ORER, PER, or FER bit in SSR is set to 1. ERI cannot start the DMAC. TEI is requested when the TEND bit in SSR is set to 1. TEI cannot start the DMAC. Where the TXI interrupt indicates that transmit data writing is enabled, the TEI interrupt indicates that the transmit operation is complete. Table 15.12 SCI Interrupt Sources Interrupt Source Description DMAC Activation Priority ERI Receive error (ORER, PER, or FER) No High RXI Receive data full (RDRF) Yes TXI Transmit data empty (TDRE) Yes TEI Transmit end (TEND) No 15.5 Low Usage Notes Sections 15.5.1 to 15.5.10 provide information concerning use of the SCI. 15.5.1 TDR Write and TDRE Flag The TDRE bit in the serial status register (SSR) is a status flag indicating loading of transmit data from TDR into TSR. The SCI sets TDRE to 1 when it transfers data from TDR to TSR. Data can be written to TDR regardless of the TDRE bit status. If new data is written in TDR when TDRE is 0, however, the old data stored in TDR will be lost because the data has not yet been transferred to TSR. Before writing transmit data to TDR, be sure to check that TDRE is set to 1. 15.5.2 Simultaneous Multiple Receive Errors Table 15.13 indicates the state of the SSR status flags when multiple receive errors occur simultaneously. When an overrun error occurs, the RSR contents cannot be transferred to RDR, so receive data is lost. Table 15.13 SSR Status Flags and Transfer of Receive Data SSR Status Flags Receive Error Status RDRF ORER FER PER Receive Data Transfer RSR RDR Overrun error 1 1 0 0 X Framing error 0 0 1 0 O Parity error 0 0 0 1 O Overrun error + framing error 1 1 1 0 X Overrun error + parity error 1 1 0 1 X Framing error + parity error 0 0 1 1 O Overrun error + framing error + parity error 1 1 1 1 X Legend: O: Receive data is transferred from RSR to RDR. X: Receive data is not transferred from RSR to RDR. Rev. 5.00 Feb. 24, 2010 Page 394 of 950 REJ09B0177-0500 15. Serial Communication Interface (SCI) 15.5.3 Break Detection and Processing (Asynchoronous Mode Only) Break signals can be detected by reading the RxD pin directly when a framing error (FER) is detected. In the break state, the input from the RxD pin consists of all 0s, so FER is set and the parity error flag (PER) may also be set. In the break state, the SCI receiver continues to operate, so if the FER bit is cleared to 0, it will be set to 1 again. 15.5.4 Sending a Break Signal (Asynchoronous Mode Only) The TxD pin becomes a general I/O pin with the I/O direction and level determined by the I/O port data register (DR) and pin function controller (PFC) control register (CR). These conditions allow break signals to be sent. The DR value is substituted for the marking status until the PFC is set. Consequently, the output port is set to initially output a 1. To send a break in serial transmission, first clear the DR to 0, then establish the TxD pin as an output port using the PFC. When TE is cleared to 0, the transmission section is initialized regardless of the present transmission status. 15.5.5 Receive Error Flags and Transmitter Operation (Synchronous Mode Only) When a receive error flag (ORER, PER, or FER) is set to 1, the SCI will not start transmitting even if TDRE is set to 1. Be sure to clear the receive error flags to 0 before starting to transmit. Note that clearing RE to 0 does not clear the receive error flags. 15.5.6 Receive Data Sampling Timing and Receive Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a base clock with a frequency of 16 times the transfer rate. In receiving, the SCI synchronizes internally with the falling edge of the start bit, which it samples on the base clock. Receive data is latched on the rising edge of the eighth base clock pulse (figure 15.24). 16 clocks 8 clocks 0 78 15 0 78 15 0 5 Base clock -7.5 clocks Receive data (RxD) +7.5 clocks Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 15.24 Receive Data Sampling Timing in Asynchronous Mode The receive margin in asynchronous mode can therefore be expressed as: M = 0.5 - D - 0.5 1 (1 + F) x 100% - (L - 0.5) F - N 2N M : Receive margin (%) N : Ratio of clock frequency to bit rate (N = 16) D : Clock duty cycle (D = 0 - 1.0) L : Frame length (L = 9 - 12) F : Absolute deviation of clock frequency Rev. 5.00 Feb. 24, 2010 Page 395 of 950 REJ09B0177-0500 15. Serial Communication Interface (SCI) From the equation above, if F = 0 and D = 0.5 the receive margin is 46.875%: D = 0.5, F = 0 M = (0.5 - 1/(2 x 16)) x 100% = 46.875% This is a theoretical value. A reasonable margin to allow in system designs is 20-30%. 15.5.7 Constraints on DMAC Use * When using an external clock source for the serial clock, update TDR with the DMAC, and then after the elapse of five peripheral clocks (P) or more, input a transmit clock. If a transmit clock is input in the first four P clocks after TDR is written, an error may occur (figure 15.25). * Before reading the receive data register (RDR) with the DMAC, select the receive-data-full (RXI) interrupt of the SCI as a start-up source. SCK t TDRE D0 D1 D2 D3 D4 D5 D6 D7 Note: During external clock operation, an error may occur if t is 4 P clocks or less. Figure 15.25 Example of Synchronous Transmission with DMAC 15.5.8 Cautions on Synchronous External Clock Mode * Set TE = RE = 1 only when external clock SCK is 1. * Do not set TE = RE = 1 until at least four P clocks after external clock SCK has changed from 0 to 1. * When receiving, RDRF is 1 when RE is cleared to zero 2.5-3.5 P clocks after the rising edge of the RxD D7 bit SCK input, but copying to RDR is not possible. 15.5.9 Caution on Synchronous Internal Clock Mode When receiving, RDRF is 1 when RE is cleared to zero 1.5 P clocks after the rising edge of the RxD D7 bit SCK output, but copying to RDR is not possible. 15.5.10 Note on Writing to Registers During Transmit, Receive, and Transmit/Receive Operations Do not write to SMR, SCR, BRR, or SDCR after setting the TE or RE bit in SCR to 1 to start a transmit, receive, or transmit/receive operation. Also, do not overwrite the contents of these registers with identical values. However, the above restriction does not apply to a write operation to clear the TE or RE bit in SCR to 0 at the end of a transmit, receive, or transmit/receive operation. Read operations are always possible. Rev. 5.00 Feb. 24, 2010 Page 396 of 950 REJ09B0177-0500 16. Synchronous Serial Communication Unit (SSU) Section 16 Synchronous Serial Communication Unit (SSU) This LSI has two independent synchronous serial communication unit (SSU) channels. The SSU has a master mode in which the LSI outputs a clock as a master device for synchronous serial communication. Synchronous serial communication can be performed with devices having different clock polarity or clock phase. Figure 16.1 is a block diagram of the SSU. 16.1 * * * * * * * * Features Support for master mode Synchronous serial communications with devices having a different clock phase or polarity Choice of 8/16/32-bit width of transmit/receive data Full-duplex communication capability The shift register is incorporated, enabling transmission and reception to be executed simultaneously. Continuous serial communications Choice of LSB-first or MSB-first transfer Choice of a clock source /4, /8, /16, /32, /64, /128, or /256 Five interrupt sources transmit-end, transmit-data-register-empty, receive-data-full, overrun-error, and conflict error Rev. 5.00 Feb. 24, 2010 Page 397 of 950 REJ09B0177-0500 16. Synchronous Serial Communication Unit (SSU) Bus interface Figure 16.1 shows a block diagram of the SSU. Module data bus Internal data bus SSCRH SSTDR 0 SSRDR 0 SSTDR 1 SSRDR 1 SSTDR 2 SSRDR 2 SSTDR 3 SSRDR 3 SSCRL OEI SSMR CEI SSER RXI SSSR TXI Control circuit TEI Clock Clock selector Shiftin Shiftout SSTRSR /4 /8 /16 /32 /64 /128 /256 Selector SSO SSI SCS SSCK (External clock) Legend: SS control register H SSCRH: SS control register L SSCRL: SS mode register SSMR: SS enable register SSER: SS status register SSSR: SSTDR0 to SSTDR3: SS transmit data register 0 to 3 SSRDR0 to SSRDR3: SS receive data register 0 to 3 SS transmit/recive shift register SSTRSR: Figure 16.1 Block Diagram of SSU Rev. 5.00 Feb. 24, 2010 Page 398 of 950 REJ09B0177-0500 16. Synchronous Serial Communication Unit (SSU) 16.2 Input/Output Pins Table 16.1 shows the SSU pin configuration. Table 16.1 Pin Configuration Name Pin Name* I/O Function 0 SSCK0 O SSU clock output of channel 0 SSI0 I SSU data input of channel 0 SSO0 O SSU data output of channel 0 SCS0 I/O SSU chip select input/output of channel 0 SSCK1 O SSU clock output of channel 1 SSI1 I SSU data input of channel 1 SSO1 O SSU data output of channel 1 SCS1 I/O SSU chip select input/output of channel 1 1 Note: 16.3 * Channel numbers are omitted. Pin names in this section are written as follows: SSCK, SSI, SSO, and SCS. Register Descriptions The SSU has the following registers. (1) Channel 0 * * * * * * * * * * * * * * SS control register H_0 (SSCRH_0) SS control register L_0 (SSCRL_0) SS mode register_0 (SSMR_0) SS enable register_0 (SSER_0) SS status register_0 (SSSR_0) SS transmit data register 0_0 (SSTDR0_0) SS transmit data register 1_0 (SSTDR1_0) SS transmit data register 2_0 (SSTDR2_0) SS transmit data register 3_0 (SSTDR3_0) SS receive data register 0_0 (SSRDR0_0) SS receive data register 1_0 (SSRDR1_0) SS receive data register 2_0 (SSRDR2_0) SS receive data register 3_0 (SSRDR3_0) SS shift register _0 (SSTRSR_0) (2) Channel 1 * * * * * * * * * SS control register H_1 (SSCRH_1) SS control register L_1 (SSCRL_1) SS mode register_1 (SSMR_1) SS enable register_1 (SSER_1) SS status register_1 (SSSR_1) SS transmit data register 0_1 (SSTDR0_1) SS transmit data register 1_1 (SSTDR1_1) SS transmit data register 2_1 (SSTDR2_1) SS transmit data register 3_1 (SSTDR3_1) Rev. 5.00 Feb. 24, 2010 Page 399 of 950 REJ09B0177-0500 16. Synchronous Serial Communication Unit (SSU) * * * * * SS receive data register 0_1 (SSRDR0_1) SS receive data register 1_1 (SSRDR1_1) SS receive data register 2_1 (SSRDR2_1) SS receive data register 3_1 (SSRDR3_1) SS shift register _1 (SSTRSR_1) Table16.2 Register Configuration Channel Register Name Abbreviation Address Number of Bits Data Bus Width Initial Value CH0 SS control register H_0 SSCRH_0 H'FFFFFC00 8 bits 16 bits H'08 SS control register L_0 SSCRL_0 H'FFFFFC01 H'00 SS mode register_0 SSMR_0 H'FFFFFC02 H'00 SS enable register_0 SSER_0 H'FFFFFC03 H'00 SS transmit data register 0_0 SSTDR0_0 H'FFFFFC04 H'00 SS transmit data register 1_0 SSTDR1_0 H'FFFFFC05 H'00 SS transmit data register 2_0 SSTDR2_0 H'FFFFFC06 H'00 SS transmit data register 3_0 SSTDR3_0 H'FFFFFC07 H'00 SS receive data register 0_0 SSRDR0_0 H'FFFFFC08 H'00 SS receive data register 1_0 SSRDR1_0 H'FFFFFC09 H'00 SS receive data register 2_0 SSRDR2_0 H'FFFFFC0A H'00 SS receive data register 3_0 SSRDR3_0 H'FFFFFC0B H'00 SS status register_0 SSSR_0 H'FFFFFC0C H'04 SS control register H_1 SSCRH_1 H'FFFFFC10 H'08 SS control register L_1 SSCRL_1 H'FFFFFC11 H'00 SS mode register_1 SSMR_1 H'FFFFFC12 H'00 SS enable register_1 SSER_1 H'FFFFFC13 H'00 SS transmit data register 0_1 SSTDR0_1 H'FFFFFC14 H'00 SS transmit data register 1_1 SSTDR1_1 H'FFFFFC15 H'00 SS transmit data register 2_1 SSTDR2_1 H'FFFFFC16 H'00 SS transmit data register 3_1 SSTDR3_1 H'FFFFFC17 H'00 SS receive data register 0_1 SSRDR0_1 H'FFFFFC18 H'00 SS receive data register 1_1 SSRDR1_1 H'FFFFFC19 H'00 SS receive data register 2_1 SSRDR2_1 H'FFFFFC1A H'00 SS receive data register 3_1 SSRDR3_1 H'FFFFFC1B H'00 SS status register_1 SSSR_1 H'FFFFFC1C H'04 CH1 Rev. 5.00 Feb. 24, 2010 Page 400 of 950 REJ09B0177-0500 16. Synchronous Serial Communication Unit (SSU) 16.3.1 SS Control Register H (SSCRH) SSCRH specifies SSO pin output value selection, SSCK pin selection, and SCS pin selection. Bit: 7 6 5 4 3 2 1 0 MSS -- -- SOL SOLP SCKS CSS1 CSS0 0 0 0 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: R/W: Bit Bit Name Initial Value R/W Description 7 MSS 0 R/W Master Selection This bit must be set to 1 in order to use the SSU. When the CE bit in SSSR is set, this bit is automatically cleared. Reset this bit to 1 when restarting communication. 0: Reserved. (Initial value) 1: Master mode enabled. 6, 5 All 0 Reserved This bit is always read as 0. The write value should always be 0. 4 SOL 0 R/W Serial Data Output Value Selection The output level of serial data, which retains that of the last bit, can be modified by operating this bit before or after transmission. When modifying the output level, clear the SOLP bit to 0. The modified output level is retained until the start of the next transmit operation. Since writing to this bit during data transmission causes malfunctions, this bit should not be modified. 0: Serial data output is modified to low level. (Initial value) 1: Serial data output is modified to high level. 3 SOLP 0 R SOL Bit Write Protect When modifying the output level for serial data, either set SOL to 1 and clear SOLP to 0 or clear both SOL and SOLP to 0. 0: Output level can be modified by the SOL value 1: This bit is always read as 1 and cannot be modified. (Initial value) 2 SCKS 0 R/W SSCK Output Selection To set the SSCK pin to function as a serial clock pin, set this bit to 1 after setting the pin function controller (PFC) to the SSCK function. 0: High-level output. (Initial value) 1: Serial clock output. Rev. 5.00 Feb. 24, 2010 Page 401 of 950 REJ09B0177-0500 16. Synchronous Serial Communication Unit (SSU) Bit Bit Name Initial Value R/W Description 1 CSS1 0 R/W SCS Pin Selection 0 CSS0 0 R/W Select that the SCS pin functions as a port or SCS input or output. However, when MSS = 0, the SCS pin functions as an input pin regardless of the CSS1 and CSS0 settings. 00: Reserved. (Initial value) 01: Functions as SCS input 10: Functions as SCS automatic input/output (however, functions as SCS input before and after communication and outputs a low level during communication) 11: Functions as SCS automatic output (however, outputs a high level before and after communication and outputs a low level during communication) SSCRH is initialized by a power-on reset, hardware standby mode, and software standby mode. It is not initialized by a manual reset. 16.3.2 SS Control Register L (SSCRL) SSCRL selects software reset and transmit/receive data width. Bit: 7 6 5 4 3 2 1 0 -- -- SRES -- -- -- DATS1 DATS Initial value: R/W: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 7, 6 All 0 Reserved These bits are always read as 0. The write value should always be 0. 5 SRES 0 R/W Software Reset Setting this bit to 1 forcibly resets the SSU internal sequencer. After that, this bit is automatically cleared. The ORER, TEND, TDRE, RDRF, and CE bits in SSSR and the TE and RE bits in SSER are also initialized. Values of other bits for SSU registers are held. To stop communication, set this bit to 1 to reset the SSU internal sequencer. 4 to 2 1 DATS1 0 R/W Transmit/Receive Data Length Selection 0 DATS0 0 R/W Select serial data length from 8, 16, and 32 bits. 00: 8 bits (Initial value) All 0 Reserved These bits are always read as 0 and cannot be modified. 01: 16 bits 10: 32 bits 11: Setting invalid SSCRL is initialized by a power-on reset, hardware standby mode and software standby mode. It is not initialized by a manual reset. Rev. 5.00 Feb. 24, 2010 Page 402 of 950 REJ09B0177-0500 16. Synchronous Serial Communication Unit (SSU) 16.3.3 SS Mode Register (SSMR) SSMR selects the MSB first/LSB first, clock phase, clock polarity, and communication clock rate of synchronous serial communication. Bit: 7 6 5 4 3 2 1 0 MLS CPOS CPHS -- -- CKS2 CKS1 CKS0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: R/W: Bit Bit Name Initial Value R/W Description 7 MLS 0 R/W MSB First/LSB First Selects the serial data is communication in MSB first or LSB first. 0: LSB first (Initial value) 1: MSB first 6 CPOS 0 R/W Clock Polarity Selection Selects SSCK clock polarity. 0: High output in idle mode, and low output in active mode (Initial value) 1: Low output in idle mode, and high output in active mode 5 CPHS 0 R/W Clock Phase Selection Selects SSCK clock phase. 0: Data changes at the first edge. (Initial value) 1: Data is latched at the first edge. 4, 3 All 0 Reserved These bits are always read as 0. The write value should always be 0. 2 CKS2 0 R/W Communication Clock Rate Selection 1 CKS1 0 R/W 0 CKS0 0 R/W Select the communication clock rate (prescaler division rate) when an internal clock is selected. 000: Reserved (Initial value) 001: P/4 010: P/8 011: P/16 100: P/32 101: P/64 110: P/128 111: P/256 SSMR is initialized by a power-on reset, hardware standby mode and software standby mode. It is not initialized by a manual reset. Rev. 5.00 Feb. 24, 2010 Page 403 of 950 REJ09B0177-0500 16. Synchronous Serial Communication Unit (SSU) 16.3.4 SS Enable Register (SSER) SSER controls the transmit enable, receive enable, and interrupt request enable. Bit: 7 6 5 4 3 2 1 0 TE RE -- -- TEIE TIE RIE CEIE Initial value: R/W: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 7 TE 0 R/W Transmit Enable When this bit is set to 1, transmission is enabled. 6 RE 0 R/W Receive Enable When this bit is set to 1, reception is enabled. 5, 4 All 0 Reserved 3 TEIE 0 R/W Transmit End Interrupt Enable 2 TIE 0 R/W Transmit Interrupt Enable These bits are always read as 0. The write value should always be 0. When this bit is set to 1, TEI interrupt request is enabled. When this bit is set to 1, TXI interrupt request is enabled. 1 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI interrupt request and OEI interrupt request are enabled. 0 CEIE 0 R/W Conflict Error Interrupt Enable When this bit is set to 1, CEI interrupt request is enabled. SSER is initialized to H'00 by a power-on reset and hardware standby mode. The value is not retained in software standby mode and it is initialized after release. It is not initialized by a manual reset. Rev. 5.00 Feb. 24, 2010 Page 404 of 950 REJ09B0177-0500 16. Synchronous Serial Communication Unit (SSU) 16.3.5 SS Status Register (SSSR) SSSR is a status flag register for interrupts. Bit: Initial value: R/W: Note: * 7 6 5 4 3 2 1 0 -- ORER -- -- TEND TDRE RDRF CE 0 0 0 0 0 1 0 0 R/W R/(W)* R/W R/W R/(W)* R/(W)* R/(W)* R/(W)* Write 0 to clear the flag. Bit Bit Name Initial Value R/W Description 7 0 Reserved These bits are always read as 0. The write value should always be 0. 6 ORER 0 R/W Overrun Error If the next data is received while RDRF = 1, an overrun error occurs, indicating abnormal termination. SSRDR stores 1-frame receive data before an overrun error occurs and loses data received later. While ORER = 1, continuous serial reception cannot be continued. Serial transmission cannot be continued, either. [Setting condition] * When the next reception data is transferred to SSRDR while RDRF = 1 [Clearing condition] * When 0 is written to ORER after reading ORER = 1 5, 4 All 0 Reserved These bits are always read as 0. The write value should always be 0. 3 TEND 0 R Transmit End [Setting condition] * When the last bit of transmit data is transmitted with TDRE = 1 [Clearing conditions] 2 TDRE 1 R/W * When 0 is written to the TEND bit after reading TEND = 1 * When data is written to SSTDR Transmit Data Empty Indicates whether or not SSTDR contains transmit data. [Setting conditions] * When the TE bit in SSER is 0 * When data is transferred from SSTDR to SSTRSR and SSTDR is ready to be written to. [Clearing conditions] * When 0 is written to the TDRE bit after reading TDRE = 1 * When data is written to SSTDR with TE = 1 Rev. 5.00 Feb. 24, 2010 Page 405 of 950 REJ09B0177-0500 16. Synchronous Serial Communication Unit (SSU) Bit Bit Name Initial Value R/W Description 1 RDRF 0 R/W Receive Data Register Full Indicates whether or not SSRDR contains received data. [Setting condition] * When receive data is transferred from SSTRSR to SSRDR after successful data reception [Clearing conditions] 0 CE 0 R/W * When 0 is written to RDRF after reading RDRF = 1 * When received data is read from SSRDR Conflict Error Indicates that a conflict error has occurred when 0 is externally input via the SCS pin with MSS = 1. Serial receive operation cannot continue if CE has been set to 1. Furthermore, serial transmit operation cannot continue. Before restarting communication, do not fail to set SRES in SSCRL to 1 to reset the internal sequencer and make the initial settings shown in figure 16.4. [Setting condition] When a low level is input to the SCS pin in master device mode (MSS in SSCRH = 1) [Clearing condition] * * When 0 is written to the CE bit after reading CE = 1 SSSR is initialized by a power-on reset, hardware standby mode, and software standby mode. It is not initialized by a manual reset. Rev. 5.00 Feb. 24, 2010 Page 406 of 950 REJ09B0177-0500 16. Synchronous Serial Communication Unit (SSU) 16.3.6 SS Transmit Data Register 0 to 3 (SSTDR0 to SSTDR3) SSTDR is an 8-bit register that stores transmit data. When 8-bit data length is selected by bits DATS1 and DATS0 in SSCRL, SSTDR0 is valid. When 16-bit data length is selected, SSTDR0 and SSTDR1 are valid. When 32-bit data length is selected, SSTDR0 to SSTDR3 are valid. Do not access invalid bits in SSTDR. When the SSU detects that SSTRSR is empty, it transfers the transmit data written in SSTDR to SSTRSR and starts transmission. If the next transmit data has already been written to SSTDR during serial transmission, the SSU transfers the written data to SSTRSR to continue transmission. Although SSTDR can be read or written to by the CPU and DMAC at all times, to achieve reliable serial transmission, write transmit data to SSTDR after confirming that the TDRE bit in SSSR is set to 1, and ensure that the write data size matches the data length specified by DATS1 and DATS0. SSTDR0 Bit: Initial value: 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W: SSTDR1 R/W: SSTDR2 R/W: SSTDR3 R/W: Table 16.3 DATS Bit Settings and SSTDR Bit Status DATS [1:0] (SSCRL [1:0] SSTDR 00 01 10 11 (Setting Invalid) 0 Valid Valid Valid Invalid 1 Invalid Valid Valid Invalid 2 Invalid Invalid Valid Invalid 3 Invalid Invalid Valid Invalid Rev. 5.00 Feb. 24, 2010 Page 407 of 950 REJ09B0177-0500 16. Synchronous Serial Communication Unit (SSU) SSTDR is initialized by a power-on reset, hardware standby mode, and software standby mode. It is not initialized by a manual reset. 16.3.7 SS Receive Data Register 0 to 3 (SSRDR0 to SSRDR3) SSRDR is an 8-bit register that stores receive data. When 8-bit data length is selected by bits DATS1 and DATS0 in SSCRL, SSRDR0 is valid. When 16-bit data length is selected, SSRDR0 and SSRDR1 are valid. When 32-bit data length is selected, SSRDR0 to SSRDR3 are valid. Do not access invalid bits in SSRDR. When the SSU has received 1-byte data, it transfers the received serial data from SSTRSR to SSRDR where it is stored. After this, SSTRSR is receive-enabled. Since SSTRSR and SSRDR function as a double buffer in this way, continuous receive operations can be performed. Read SSRDR after confirming that the RDRF bit in the SSSR register is set to 1, and ensure that the read data size matches the data length specified by DATS1 and DATS0. SSRDR is a read-only register. SSRDR cannot be written to by the CPU. SSRDR0 Bit: 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R SSRDR1 SSRDR2 SSRDR3 Rev. 5.00 Feb. 24, 2010 Page 408 of 950 REJ09B0177-0500 16. Synchronous Serial Communication Unit (SSU) Table 16.4 DATS Bit Settings and SSRDR Bit Status DATS [1:0] (SSCRL [1:0]) SSRDR 00 01 10 11 (Setting Invalid) 0 Valid Valid Valid Invalid 1 Invalid Valid Valid Invalid 2 Invalid Invalid Valid Invalid 3 Invalid Invalid Valid Invalid SSRDR is initialized by a power-on reset, hardware standby mode, and software standby mode. It is not initialized by a manual reset. 16.3.8 SS Shift Register (SSTRSR) SSTRSR is a shift register that transmits and receives serial data. When data from SSTDR to SSTRSR is transferred with MLS = 0, bit 0 of transmit data is bit 0 in the SSTDR contents (LSB first communication). When data from SSTDR to SSTRSR is transferred with MLS = 1, bit 0 of transmit data is bit 7 in the SSTDR contents (MSB first communication). To perform serial data transmission, the SSU transfers data starting from LSB (bit 0) in SSTRSR to the SSO pin. In reception, the SSU sets serial data that has been input from the SSI pin to SSTRSR starting from LSB (bit 0) and converts it into parallel data. When 1-byte data has been received, the SSTRSR contents are automatically transferred to SSRDR. SSTRSR cannot be directly accessed by the CPU. Rev. 5.00 Feb. 24, 2010 Page 409 of 950 REJ09B0177-0500 16. Synchronous Serial Communication Unit (SSU) 16.4 Operation 16.4.1 Communication Clock The communication clock source can be selected from among seven internal clocks. When using this module, first set the pin function controller (PFC) to match the SSU setting, then set SCKS in SSCRH to 1 to select serial clock output. When communication starts, the clock with the communication rate specified by bits CKS2 to CKS0 in SSMR is output from the SSCK pin. 16.4.2 Relationship of Clock Phase, Polarity, and Data The relationship of clock phase, polarity, and communication data depends on the combination of CPOS and CPHS in SSMR. Figure 16.2 shows the relationship. Setting the MLS bit specifies that MSB or LSB first communication. When MLS = 0, data is transferred from the LSB to MSB. When MLS = 1, data is transferred from the MSB to LSB. (1) When CPHS = 0 SCS SSCK (CPOS = 0) SSCK (CPOS = 1) SSI, SSO Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 (2) When CPHS = 1 SCS SSCK (CPOS = 0) SSCK (CPOS = 1) SSI, SSO Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Figure 16.2 Relationship of Clock Phase, Polarity, and Data 16.4.3 Relationship between Data I/O Pins and the Shift Register Figure 16.3 shows the connections between the data I/O pins and the SS shift register (SSTRSR). When TE=1, and RE=1 SSCK Shift register (SSTRSR) SSO SSI Figure 16.3 Relationship between Data I/O Pins and the Shift Register Rev. 5.00 Feb. 24, 2010 Page 410 of 950 REJ09B0177-0500 16. Synchronous Serial Communication Unit (SSU) 16.4.4 Data Input/Output Pins and Port IO Register Setting When the SSU is used, for each data input/output pin during the initialization, the SSU function must be selected by the port control register and the input/output direction must be set by the port IO register depending on the mode. Table 16.5 shows port IO register settings in each mode. Table 16.5 Port IO Register Setting in SSU I/O port Register Channel 0 Channel 1 SSCK0 SSI0 SSO0 SSCK1 SSI1 SSO1 TE RE PB13IOR PA15IOR PA14IOR PB15IOR or PL7IOR PC3IOR PC2IOR 0 0 1 * * 1 * * 0 0 0 0 1 1 0 1 1 1 Legend: *: Don't care 16.4.5 Data Transmission and Data Reception The SSU performs data communications using the bus: the clock line (SSCK), data input (SSI), data output (SSO), and chip select (SCS). * SSU Initialization Figure 16.4 shows an example of the SSU initialization. Before transmitting and receiving data, first clear the TE and RE bits in SSER to 0, then initialize the SSU. Note: When the operating mode or transfer format is changed for example, the TE and RE bits must be cleared to 0. When the TE bit is cleared to 0, the TDRE bit is set to 1. Note that clearing the RE bit to 0 does not initialize the values of the RDRF and ORER bits or the contents of SSRDR. Rev. 5.00 Feb. 24, 2010 Page 411 of 950 REJ09B0177-0500 16. Synchronous Serial Communication Unit (SSU) Start initialization Clear TE and RE bits in SSER to 0 [1] Set up pins SSCK, SSI, and SSO for use as inputs or outputs. [2] Specify master, SSO pin output value selection, SSCK output selection, and SCS pin selection. [3] Specify transmit/receive data length. [1] [2] Set PFC register Specify CSS1, CSS0, MSS, SOL, and SCKS bits in SSCRH [3] Specify bits DATS1 and DATS0 in SSCRL [4] Specify CKS2 to CKS0, MLS, CPOS, and CPHS bits in SSMR [5] Simultaneously set bits TE, RE, TEIE, TIE, RIE, and CEIE in SSER [4] Specify MSB first/LSB first selection, clock polarity selection, clock phase selection, and communication clock rate selection. [5] Specify enable/disable of interrupt request to the CPU. End Figure 16.4 Example of SSU Initialization * Data Transmission Figure 16.5 shows an example of transmission operation, and figure 16.6 shows an example of data transmission flowchart. When transmitting data, the SSU operates as shown below. Writing transmit data to SSTDR after the TE bit is set to 1 clears the TDRE bit to 0, and the SSTDR contents is transferred to SSTRSR. After that, the SSU sets the TDRE bit to 1 and starts transmission. At this time, if the TIE bit in SSER is set to 1, a TXI interrupt is generated. When 1-frame data has been communication with the TDRE bit cleared to 0, the SSTDR contents are transferred to SSTRSR to start the next transmission. When the 8th bit of transmit data has been transferred with the TDRE bit set to 1, the TEND bit in SSSR is set to 1 and the state is retained. At this time, if the TEIE bit is set to 1, a TEI interrupt is generated. After transmission, the output level of the SSCK pin is fixed at a high level when CPOS = 0 and at a low level when CPOS = 1. While the ORER bit in SSSR is set to 1, transmission is not performed. Check that the ORER bit is cleared to 0. Rev. 5.00 Feb. 24, 2010 Page 412 of 950 REJ09B0177-0500 16. Synchronous Serial Communication Unit (SSU) (1) When 8-bit data length is selected (SSTDR0 is valid) with CPOS = 0 and CPHS = 0 1 frame 1 frame SCS SSCK SSO Bit Bit Bit Bit Bit Bit Bit Bit 0 1 2 3 4 5 6 7 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 SSTDR0 (LSB first transmission) SSTDR0 (MSB first transmission) TDRE TEND LSI operation User operation TXI interrupt generated TEI interrupt generated TXI interrupt generated Data written to SSTDR0 TEI interrupt generated Data written to SSTDR0 (2) When 16-bit data length is selected (SSTDR0 and SSTDR1 are valid) with CPOS = 0 and CPHS = 0 1 frame SCS SSCK SSO (LSB first) Bit Bit Bit Bit Bit Bit Bit Bit 0 1 2 3 4 5 6 7 SSO (MSB first) Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 SSTDR1 SSTDR0 Bit Bit Bit Bit Bit Bit Bit Bit 0 1 2 3 4 5 6 7 SSTDR0 SSTDR1 TDRE TEND LSI operation User operation Data written to SSTDR0 to SSTDR1 (3) When 32-bit data length is selected (SSTDR0 and SSTDR3 are valid) with CPOS = 0 and CPHS = 0 1 frame SCS SSCK SSO (LSB first) Bit 0 to Bit Bit 7 0 SSTDR3 SSO (MSB first) Bit 7 to Bit Bit 0 7 SSTDR0 to Bit Bit 7 0 SSTDR2 to Bit 0 SSTDR1 to Bit 7 SSTDR1 Bit 7 to Bit 0 Bit Bit 0 7 SSTDR2 to Bit 7 SSTDR0 to Bit 0 SSTDR3 TDRE TEND LSI operation User operation Data written to SSTDR0 to SSTDR3 TXI interrupt generated TEI interrupt generated Figure 16.5 Example of Transmission Operation Rev. 5.00 Feb. 24, 2010 Page 413 of 950 REJ09B0177-0500 16. Synchronous Serial Communication Unit (SSU) Start [1] Initialization [2] Read TDRE in SSSR TDRE = 1? [1] Initialization: Specify the settings such as transmit data format. No Yes Write transmit data to SSTDR [2] Check the SSU state and write transmit data: Write transmit data to SSTDR after reading and confirming that the TDRE bit is 1. The TDRE bit is automaticallu cleared to 0 and transmission is started by writing data to SSTDR. When data is written to SSTDR, transmission starts. TDRE automatically cleared to 0 Data transferd from SSTDR to SSTRSR Set TDRE to 1 to start transmission [3] Continuous data transmission? Yes [3] Procedure for continuous data transmission: To continue data transmission, confirm that the TDRE bit is 1 meaning tha SSTDR is ready to be written to. After that, data can be written to SSTDR. The TDRE bit is automatically cleared to 0 by writing data to SSTDR. No Read TEND in SSSR TEND = 1? No [4] Procedure to end data transmission: To end data transmission, clear the TE bit to 0 once transmission of the last bit is complete. Yes Clear TEND to 0 [4] Has the 1-bit-transfer period elapsed? Yes No Clear TE in SSER to 0 End transmission Note: Hatching boxes represent SSU internal operations. Figure 16.6 Example of Data Transmission Flowchart * Data Reception Figure 16.7 shows an example of reception operation, and figure 16.8 shows an example of data reception flowchart. When receiving data, the SSU operates as shown below. After the SSU sets the RE bit to 1 and dummy-reads SSRDR, data reception is started. When 1-frame data has been received, the RDRF bit in SSSR is set to 1 and the received data is stored in SSRDR. At this time, if the RIE bit is set to 1, an RXI interrupt is generated. The RDRF bit is automatically cleared to 0 by reading SSRDR. When the RDRF bit has been set to 1 at the 8th rising edge of the transfer clock, the ORER bit in SSSR is set to 1. This indicates that an overrun error (OEI) has occurred. At this time, data reception is stopped. While the ORER bit in SSSR is set to 1, reception is not performed. To resume the reception, clear the ORER bit to 0. Rev. 5.00 Feb. 24, 2010 Page 414 of 950 REJ09B0177-0500 16. Synchronous Serial Communication Unit (SSU) (1) When 8-bit data length is selected (SSRDR0 is valid) with CPOS = 0 and CPHS = 0 1 frame SCS 1 frame SSCK Bit Bit Bit Bit Bit Bit Bit Bit 0 1 2 3 4 5 6 7 SSI Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 SSRDR0 (LSB first transmission) SSRDR0 (MSB first transmission) RDRF LSI operation RXI interrupt generated RXI interrupt generated User operation Dummy-read SSRDR0 Read SSRDR0 (2) When 16-bit data length is selected (SSRDR0 and SSRDR1 are valid) with CPOS = 0 and CPHS = 0 1 frame SCS SSCK SSI (LSB first) Bit Bit Bit Bit Bit Bit Bit Bit 0 1 2 3 4 5 6 7 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 SSRDR1 SSI (MSB first) SSRDR0 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Bit Bit Bit Bit Bit Bit Bit Bit 0 1 2 3 4 5 6 7 SSRDR0 SSRDR1 RDRF LSI operation RXI interrupt generated User operation Dummy-read SSRDR0, SSRDR1 (3) When 32-bit data length is selected (SSRDR0 and SSRDR3 are valid) with CPOS = 0 and CPHS = 0 SCS SSCK SSI (LSB first) Bit 0 to Bit Bit 7 0 SSRDR3 SSI (MSB first) Bit 7 to Bit Bit 0 7 SSRDR0 to Bit Bit 7 0 SSRDR2 to Bit 0 SSRDR1 to Bit 7 SSRDR1 Bit 7 to Bit 0 Bit Bit 0 7 SSRDR2 to Bit 7 SSRDR0 to Bit 0 SSRDR3 RDRF LSI operation User operation Dummy-read SSRDR0, SSRDR1, SSRDR2, SSRDR3 RXI interrupt generated Figure 16.7 Example of Reception Operation Rev. 5.00 Feb. 24, 2010 Page 415 of 950 REJ09B0177-0500 16. Synchronous Serial Communication Unit (SSU) Start [1] Initialization [2] Dummy-read SSRDR RDRF = 1? Yes ORER = 1? Initialization: Specify the settings such as receive data format. [2] Start reception: When SSRDR is dummy-read with RE = 1, reception is started. [3], [6] Receive error processing: When a receive error occurs execute the designated error processing after reading the ORER bit in SSSR. After that, Clear the ORER bit to 0. While the ORER bit is set to 1, transmission or reception is not resumed. Read SSSR No [3] [1] Yes [3] [4] To continue single reception: While the RDRF bit is set to 1, read received data in SSRDR after a wait for tSucyc. The next single reception starts after reading received data in SSRDR. [5] To complete reception: To complete reception, read received data after clearing the RE bit to 0. When reading SSRDR without clearing the RE bit, reception is resumed. No [4] Continous data reception? No Yes Read received data in SSRDR RDRF automatically cleared [5] RE = 0 Read received data in SSRDR End reception [6] Overrun error processing Clear ORER in SSSR End reception Note: Hatching boxes represent SSU internal operations. Figure 16.8 Example of Data Reception Flowchart * Data Transmission/Reception Figure 16.9 shows an example of simultaneous transmission/reception operation. The data transmission/reception is performed combining the data transmission and data reception as mentioned above. The data transmission/reception is started by writing transmit data to SSTDR with TE = RE = 1. Before switching transmission mode (TE = 1) or reception mode (RE = 1) to transmission/reception mode (TE = RE = 1), clear the TE and RE bits to 0. When starting the transfer, confirm that the TEND, RDRF, and ORER bits are cleared to 0 before setting the TE and RE bits to 1. Rev. 5.00 Feb. 24, 2010 Page 416 of 950 REJ09B0177-0500 16. Synchronous Serial Communication Unit (SSU) Start [1] Initialization [2] Read TDRE in SSSR. [1] Initialization: Specify the settings such as transmit/receive data format No TDRE = 1? Yes Write transmit data to SSTDR [3] Check the SSU state and read receive data: Read receive data in SSRDR after reading and confirming that the RDRF bit is 1. A change of the RDRF bit (from 0 to 1) can be notified by RXI interrupt. TDRE automatically cleared to 0 Data transferred from SSTDR to SSTRSR [4] Receive error processing: When a receive error occurs, read the ORER bit in SSSR and then execute the designated error processing. After that, clear the ORER bit to 0. While the ORER bit is set to 1, transmission or reception is not resumed. TDRE set to 1 to start transmission Read SSSR [3] No RDRF = 1? Yes ORER = 1? [2] Check the SSU state and write transmit data Write transmit data to SSTDR after reading SSSR and confirming that the TDRE bit is 1. The TDRE bit is automatically cleared to 0 by writing data to SSTDR. Data transmission or reception is started by writing data to SSTDR. Yes [4] No Read received data in SSRDR [5] Procedure for continuous data transmission/ reception: To continue setial data transmission/reception, confirm that the TDRE bit 1meaning that SSTDR is ready to be written to. After that, data can be written to SSTDR. The TDRE bit is automatically cleared to 0 by writing data to SSTDR. RDRF automatically cleared to 0 Continuous data transmission/reception Yes [5] No Read TEND in SSSR TEND = 1 ? Yes No Error processing Clear TEND in SSSR to 0 1-bit duration elapsed ? No Yes Clear TE and RE in SSER to 0 End transmission/reception Note: Hatching boxes represent SSU internal operations. Figure 16.9 Example of Simultaneous Transmission/Reception Flowchart Rev. 5.00 Feb. 24, 2010 Page 417 of 950 REJ09B0177-0500 16. Synchronous Serial Communication Unit (SSU) 16.4.6 SCS Pin Control and Conflict Errors When bits CSS1 and CSS0 in SSCRH are specified to 10 is specified to 0, the SCS pin functions as an input (high impedance) to detect conflict errors. Conflict errors are detected until a serial communication starts from the MSS bit in SSCRH is set to 1 and after the communication ends. When a low level signal is input on the SCS pin within the conflict errors detection period, a conflict error occurs. At this time, the CE bit in SSSR is set to 1 and the MSS bit is cleared to 0. Note: While the CE bit is set to 1, communication is not resumed. Clear the CE bit to 0 before resuming communication. In addition, set SRES in SSCRL to 1 to reset the internal sequencer and make the initial settings shown in figure 16.4. External input to SCS Internal-clocked SCS MSS Internal communication enable signal Data written to SSTDR CE SCS output (Hi-Z) Conflict errors detection period Worst time for SCS internal synchronization Figure 16.10 Conflict Errors Detection Timing (Before Communication) SCS (Hi-Z) MSS Internal communication enable signal CE Communication end Conflict errors detection period Figure 16.11 Conflict Errors Detection Timing (After Communication End) Rev. 5.00 Feb. 24, 2010 Page 418 of 950 REJ09B0177-0500 16. Synchronous Serial Communication Unit (SSU) 16.5 Interrupt Requests The SSU interrupt requests consist of transmit data register empty, transmit end, receive data register full, overrun error, and conflict error. Of these interrupt sources, transmit data register empty, transmit end, receive data register full can activate the DTC for data transfer. Since both the overrun error and conflict error interrupt requests are allocated to the SSERI vector address and both the transmit data empty and transmit end interrupt requests are allocated to the SSTXI vector address, flags should be checked to decide the interrupt source. Table 16.6 lists interrupt sources. When an interrupt condition shown in table 16.6 is satisfied, an interrupt requests occur. Clear the interrupt source by the CPU or a DMAC transfer. Table 16.6 Interrupt Souses Channel Abbreviation Interrupt Request Symbol Interrupt Condition DMAC Activation 0 SSERI0 Overrun error OEI0 (RIE = 1) * (ORER = 1) -- Conflict error CEI0 (CEIE = 1) * (CE = 1) -- SSRXI0 Receive data register full RXI0 (RIE = 1) * (RDRF = 1) O SSTXI0 Transmit data register empty TXI0 (TIE = 1) * (TDRE = 1) O Transmit end TEI0 (TEIE = 1) * (TEND = 1) O Overrun error OEI1 (RIE = 1) * (ORER = 1) -- Conflict error CEI1 (CEIE = 1) * (CE = 1) -- SSRXI1 Receive data register full RXI1 (RIE = 1) * (RDRF = 1) O SSTXI1 Transmit data register empty TXI1 (TIE = 1) * (TDRE = 1) O Transmit end TEI1 (TEIE = 1) * (TEND = 1) O 1 SSERI1 Legend: O: Enabled --: Disabled 16.6 Usage Note 16.6.1 Note on Using the SSU The LSI's SSU cannot be used as a slave or multi master. 16.6.2 Point to Note when Setting Pins Although each of SCS0, SCS1, and SSCK1 is assignable to multiple pins, only one pin should be assigned for use by each signal. Rev. 5.00 Feb. 24, 2010 Page 419 of 950 REJ09B0177-0500 16. Synchronous Serial Communication Unit (SSU) Rev. 5.00 Feb. 24, 2010 Page 420 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) Section 17 Controller Area Network-II (HCAN-II) 17.1 Overview The controller area network-II (HCAN-II) is a module that controls the controller area network (CAN) for realtime communication in the car and industrial device systems, etc. It serves to facilitate the hardware/software interface so that engineers involved in the CAN implementation can ensure the design is successful. The CAN data link controller function is not described in this document. The following CAN-specification documents should be referred to. The interfaces from the CAN controller are described, in so far as they pertain to the connection with the user interface. References: 1. CAN License Specification, Robert Bosch GmbH, 1992 2. CAN Specification Version 2.0, Robert Bosch GmbH, 1991 3. Implementation Guide for the CAN Protocol, CAN Specification 2.0 Addendum, CAN In Automation, Erlangen, Germany 4. OSEK Communication Specification, Version 2.1 revision 1, OSEK /VDX, 17th June 1998 17.1.1 Features * Supports CAN specification 2.0A/2.0B and ISO-11898-1 * 31 programmable mailboxes for transmission/reception and one receive-only mailbox (there is a limitation for usage only in mailbox 31) * Sleep mode for low power consumption and automatic recovery from sleep mode by detecting CAN bus activity * Programmable receive filter mask (standard and extended IDs) supported by all mailboxes * Programmable CAN data rate up to 500 kbits/s (or 1 Mbit/s with a limitation) * Transmit message queuing with an on-chip priority sorting mechanism against the problem of priority inversion for realtime applications * Flexible interrupt structure * Read section 17.8, Usage Notes carefully. Rev. 5.00 Feb. 24, 2010 Page 421 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) The following features have been added in the HCAN-II. * * * * * * * IRR0 function to notify a software reset and halt Halt mode status bit and error passive status bit added to GSR Timestamp support of all incoming messages and outgoing messages Supports various test modes Data frame and remote frame are separated (IRR2 is independent from IRR1 and RXPR from RFRR) When transmitting, the highest priority search is scanned from mailbox 31 down to mailbox 1 When receiving, the matching ID search is scanned from mailbox 31 down to mailbox 0, and one received message is only stored into one mailbox * More flexible BCR * Bus off/bus off recover interrupt (IRR6) Others: * HCAN-II connection method: Two connections are available * 32-buffer HCAN-II x 2 channels (transmit pin x 2 and receive pin x 2) 64-buffer HCAN-II (wire AND) x 1 channel (transmit pin x 1 and receive pin x 1) * DMAC can be activated by a receive message of a mailbox (only mailbox 0 in HCAN0) Rev. 5.00 Feb. 24, 2010 Page 422 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) 17.2 Architecture 17.2.1 Block Diagram The HCAN-II device offers a flexible and sophisticated way to configure and control CAN frames, supporting CAN2.0B Active and ISO-11898. The module is configured of 5 different functional blocks. These are the Microprocessor Interface (MPI), mailbox, mailbox control, timer, and CAN interface. Figure 17.1 shows a block diagram of the HCAN-II module. The bus interface timing is designed based on the SuperH peripheral bus interface (P-Bus). HRxDn HTxDn (n: 0 to 1) CAN Interface REC Data-Out[15:0] msn/readn/psize Address[10:0] Receive buffer Transmit buffer BCR Data-In[15:0] TEC Control signals Microprocessor interface Status signals TXPR0/1 TXACK0/1 MCR IRR TXCR0/1 ABACK0/1 GSR IMR RXPR0/1 RFPR0/1 MBIMR0/1 UMSR0/1 CLK TCNTR TDCR TCR LOSR TSR ICRi CCR TCMRi CCMAX TMR 16-bit bus IRQ Mailbox control Mailbox0 Mailbox1 Mailbox2 Mailbox3 Mailbox4 Mailbox5 Mailbox6 Mailbox7 Mailbox8 Mailbox9 Mailbox10 Mailbox11 Mailbox12 Mailbox13 Mailbox14 Mailbox15 Mailbox16 Mailbox24 Mailbox17 Mailbox25 Mailbox18 Mailbox26 Mailbox19 Mailbox27 Mailbox20 Mailbox28 Mailbox21 Mailbox29 Mailbox22 Mailbox30 Mailbox23 Mailbox31 Mailbox 0 to Mailbox 31 16-bit timer Figure 17.1 Block Diagram of HCAN-II (for One Channel) Note: Since the HCAN-II is designed based on a 16-bit bus system, longword (32-bit) access is prohibited. Thus, word access must be used for all the registers, and word or byte access must be used for the mailboxes. 17.2.2 Each Block Function (1) Microprocessor Interface (MPI) The MPI allows communication between the host CPU and the HCAN's registers/mailboxes to control the memory interface, and the data controller, etc. It also contains the wakeup control logic that detects the CAN bus state and notifies the MPI and the other parts of the HCAN so that the HCAN can automatically exit sleep mode. Contains registers such as MCR, IRR, GSR, and IMR. Rev. 5.00 Feb. 24, 2010 Page 423 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) (2) Mailboxes The mailboxes are message buffers which are configured of RAM. There are 32 mailboxes, and each mailbox stores the following information. * CAN message control (StdID, RTR, DLC, IDE, etc.) * CAN message data (for CAN data frames) * Local acceptance filter mask (LAFM) during reception * 3-bit mailbox configuration, automatic transmit bit for remote request, and new message control bit (3) Mailbox Control The mailbox control handles the following functions. For receive messages, compares the IDs, generates appropriate RAM addresses to store messages from the CAN interface into the mailbox, and sets/clears corresponding registers. To transmit messages, runs the internal arbitration to select the correct priority message which is event-triggered, loads the message from the mailbox into the Tx-buffer of the CAN interface, and sets/clears corresponding registers accordingly. Arbitrates mailbox accesses between the host CPU and the CAN interface or mailbox control. Contains registers such as TXPR, TXCR, TXACK, ABACK, RXPR, RFPR, and MBIMR. (4) Timer The timer is a block which transmits and receives messages at a specific time frame and records the result. The timer is a 16-bit free-running up counter which is controlled by the host CPU. It provides three 16-bit compare match registers. They can generate interrupt signals, set or clear the counter value in the local offset value, and clear messages in the transmission queue. Two 16-bit input capture registers are included to record timestamps on CAN messages and synchronize the timer value globally within a CAN system. The clock period of this timer offers a wide selection generated from the peripheral clock. Contains registers such as TCNTR, TCR, TPSR, TDCR, LOSR, ICR0_tm, ICR0_cc, ICR0_buf, ICR1, TCMR0, TCMR1, TCMR2, TMR, CCR, CCR_buf, and CMAX. [Important] The SH7059 and SH7058S do not support the timer function. (5) CAN Interface The CAN interface supports the requirements for a CAN bus data link controller defined by CAN specification 2.0A/2.0B (section 17.1, Reference 2). It fulfils all the functions of a data link layer (DLC layer) as specified by the 7 layers of the OSI model. This block provides the receive error counter, transmit error counter, and bit timing set registers, and various test modes corresponding to the CAN bus specification. This block also stores transmit/receive data for the CAN data link controller. 17.2.3 Pin Configuration Table 17.1 lists the pin configuration and functions. Table 17.1 Pin Configuration Name Input/Output Function HRxD0 Input CAN bus receive signal of channel 0 HTxD0 Output CAN bus transmit signal of channel 0 HRxD1 Input CAN bus receive signal of channel 1 HTxD1 Output CAN bus transmit signal of channel 1 Rev. 5.00 Feb. 24, 2010 Page 424 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) 17.2.4 Memory Map Figures 17.2 (1) and 17.2 (2) show the memory maps of registers which can be accessed by software. Base address: Channel 0 H'FFFFD000, channel 1 H'FFFFD800 Bit15 H'000 H'002 H'004 H'006 H'008 H'00A H'00C H'020 H'022 Bit0 Master control register_0 (MCR_0) General status register_0 (GSR_0) H'100 Mailbox 0_0 control (StdID, ExtID, RTR, IDE, DLC, ATX, DART, MBC) HCAN-II_bit configuration register 1_0 (HCAN-II_BCR1_0) HCAN-II_bit configuration register 0_0 (HCAN-II_BCR0_0) Interrupt register_0 (IRR_0) H'106 Interrupt mask register_0 (IMR_0) H'108 0 H'10A 2 H'10C 4 Transmit error counter_0 (TEC_0) Receive error counter_0 (REC_0) Transmit wait register 1_0 (TXPR1_0) H'10E Transmit wait register 0_0 (TXPR0_0) H'110 Mailbox 0_0 timestamp 1 Mailbox 0_0 data (8 bytes) 6 3 5 7 Mailbox 0_0 LAFM/Mailbox 0_0 TTT H'028 H'02A H'030 H'032 H'038 H'03A H'040 H'042 H'048 H'04A H'050 H'052 H'058 H'05A H'080 H'082 H'084 H'086 H'088 H'08A H'08C H'08E H'090 H'092 H'094 H'096 H'098 H'09A H'09C H'09E Transmit wait cancel register 1_0 (TXCR1_0) Transmit wait cancel register 0_0 (TXCR0_0) H'120 Mailbox 1_0 control/timestamp/data/LAFM Transmit acknowledge register 1_0 (TXACK1_0) Transmit acknowledge register 0_0 (TXACK0_0) Abort acknowledge register 1_0 (ABACK1_0) H'140 H'160 Mailbox 2_0 control/timestamp/data/LAFM Mailbox 3_0 control/timestamp/data/LAFM Abort acknowledge register 0_0 (ABACK0_0) Receive complete register 1_0 (RXPR1_0) Receive complete register 0_0 (RXPR0_0) Remote request register 1_0 (RFPR1_0) Remote request register 0_0 (RFPR0_0) Mailbox interrupt mask register 1_0 (MBIMR1_0) H'2E0 H'2F3 Mailbox 15_0 control/timestamp/data/LAFM H'300 Mailbox 16_0 control/timestamp/data/LAFM H'4A0 Mailbox 29_0 control/timestamp/data/LAFM H'4C0 Mailbox 30_0 control/timestamp/data/LAFM Mailbox interrupt mask register 0_0 (MBIMR0_0) Unread message status register 1_0 (UMSR1_0) Unread message status register 0_0 (UMSR0_0) Timer counter register 0 (TCNTR0) Timer control register_0 (TCR_0) Timer status register_0 (TSR_0) Timer drift correction register 0 (TDCR0) Local offset register 0 (LOSR0) CCR input capture register 0 (ICR0_cc_0) H'4E0 TCNTR input capture register 0 (ICR0_tm_0) H'4F3 Mailbox 31_0 control/timestamp/data/LAFM Input capture register 1_0 (ICR1_0) Timer compare match register 0_0 (TCMR0_0) Timer compare match register 1_0 (TCMR1_0) Timer compare match register 2_0 (TCMR2_0) Cycle counter register 0 (CCR0) Cycle maximum register 0 (CMAX0) Timer mode register_0 (TMR_0) Cycle counter register double buffer 0 (CCR_buf0) Input capture register double buffer 0 (ICR0_buf0) Figure 17.2 (1) HCAN-II Memory Map for Channel 0 (HCAN0) Rev. 5.00 Feb. 24, 2010 Page 425 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) Bit15 H'800 H'802 H'804 H'806 H'808 H'80A H'80C H'820 H'822 Bit0 Master control register_1 (MCR_1) General status register_1 (GSR_1) H'900 Mailbox 0_1 control (StdID, ExtID, RTR, IDE, DLC, ATX, DART, MBC) HCAN-II_bit configuration register 1_1 (HCAN-II_BCR1_1) HCAN-II_bit configuration register 0_1 (HCAN-II_BCR0_1) Interrupt register_1 (IRR_1) H'906 Interrupt mask register_1 (IMR_1) H'908 0 H'90A 2 Transmit error counter_1 (TEC_1) Receive error counter_1 (REC_1) H'90C Transmit wait register 1_1 (TXPR1_1) H'90E Transmit wait register 0_1 (TXPR0_1) H'910 Mailbox 0_1 timestamp 4 1 Mailbox 0_1 data (8 bytes) 6 3 5 7 Mailbox 0_1 LAFM/Mailbox 0_1 TTT H'828 H'82A H'830 H'832 H'838 H'83A H'840 H'842 H'848 H'84A H'850 H'852 H'858 H'85A H'880 H'882 H'884 H'886 H'888 H'88A H'88C H'88E H'890 H'892 H'894 H'896 H'898 H'89A H'89C H'89E Transmit wait cancel register 1_1 (TXCR1_1) Transmit wait cancel register 0_1 (TXCR0_1) H'920 Mailbox 1_1 control/timestamp/data/LAFM Transmit acknowledge register 1_1 (TXACK1_1) Transmit acknowledge register 0_1 (TXACK0_1) Abort acknowledge register 1_1 (ABACK1_1) H'940 H'960 Mailbox 2_1 control/timestamp/data/LAFM Mailbox 3_1 control/timestamp/data/LAFM Abort acknowledge register 0_1 (ABACK0_1) Receive complete register 1_1 (RXPR1_1) Receive complete register 0_1 (RXPR0_1) Remote request register 1_1 (RFPR1_1) Remote request register 0_1 (RFPR0_1) H'AE0 Mailbox 15_1 control/timestamp/data/LAFM H'AF3 Mailbox interrupt mask register 1_1 (MBIMR1_1) H'B00 Mailbox 16_1 control/timestamp/data/LAFM H'CA0 Mailbox 29_1 control/timestamp/data/LAFM H'CC0 Mailbox 30_1 control/timestamp/data/LAFM Mailbox interrupt mask register 0_1 (MBIMR0_1) Unread message status register 1_1 (UMSR1_1) Unread message status register 0_1 (UMSR0_1) Timer counter register 1 (TCNTR1) Timer control register_1 (TCR_1) Timer status register_1 (TSR_1) Timer drift correction register 1 (TDCR1) Local offset register 1 (LOSR1) CCR input capture register 1 (ICR1_cc_1) H'CE0 TCNTR input capture register 1 (ICR1_tm_1) H'CF3 Mailbox 31_1 control/timestamp/data/LAFM Input capture register 1_1 (ICR1_1) Timer compare match register 0_1 (TCMR1_1) Timer compare match register 1_1 (TCMR1_1) Timer compare match register 2_1 (TCMR2_1) Cycle counter register 1 (CCR1) Cycle maximum register 1 (CMAX1) Timer mode register_1 (TMR_1) Cycle counter register double buffer 1 (CCR_buf1) Input capture register double buffer 1 (ICR0_buf1) Figure 17.2 (2) HCAN-II Memory Map for Channel 1 (HCAN1) 17.3 Mailboxes 17.3.1 Mailbox Configuration Mailboxes play a role as message buffers to transmit/receive CAN frames. Each mailbox is comprised of 4 identical storage fields that are 1): Message control, 2): Message data, 3): Timestamp, and 4): Local acceptance filter mask (LAFM)/Transmission trigger time. Table 17.2 shows the memory map for each mailbox. Rev. 5.00 Feb. 24, 2010 Page 426 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) Note: The message control (STDID/EXTID/RTR/IDE), timestamp, and LAFM/transmission trigger time fields can only be accessed in word size (16 bits), whereas the message control (NMC/ATX/MBC/DLC) and the message data area can be accessed in word (16-bit) or byte (8-bit) size. As unused mailboxes affect the RAM configuration, bits of other than the MBC bit must be initialized to 0 while the MBC setting is inactive. When the LAFM is not used to receive messages, it must be cleared (it must be set to 0). Table 17.2 Mailbox Configuration Address Control Timestamp Data LAFM/Trigger Time Mailbox 6 Bytes 2 Bytes 8 Bytes 4 Bytes 0 (Receive only) 100 - 105 106 - 107 108 - 10F 110 - 113 1 120 - 125 126 - 127 128 - 12F 130 - 133 2 140 - 145 146 - 147 148 - 14F 150 - 153 3 160 - 165 166 - 167 168 - 16F 170 - 173 4 180 - 185 186 - 187 188 - 18F 190 - 193 5 1A0 - 1A5 1A6 - 1A7 1A8 - 1AF 1B0 - 1B3 6 1C0 - 1C5 1C6 - 1C7 1C8 - 1CF 1D0 - 1D3 7 1E0 - IE5 1E6 - 1E7 1E8 - 1EF 1F0 - 1F3 8 200 - 205 206 - 207 208 - 20F 210 - 213 9 220 - 225 226 - 227 228 - 22F 230 - 233 10 240 - 245 246 - 247 248 - 24F 250 - 253 11 260 - 265 266 - 267 268 - 26F 270 - 273 12 280 - 285 286 - 287 288 - 28F 290 - 293 13 2A0 - 2A5 2A6 - 2A7 2A8 - 2AF 2B0 - 2B3 14 2C0 - 2C5 2C6 - 2C7 2C8 - 2CF 2D0 - 2D3 15 2E0 - 2E5 2E6 - 2E7 2E8 - 2EF 2F0 - 2F3 16 300 - 305 306 - 307 308 - 30F 310 - 313 17 320 - 325 326 - 327 328 - 32F 330 - 333 18 340 - 345 346 - 347 348 - 34F 350 - 353 19 360 - 365 366 - 367 368 - 36F 370 - 373 20 380 - 385 386 - 387 388 - 38F 390 - 393 21 3A0 - 3A5 3A6 - 3A7 3A8 - 3AF 3B0 - 3B3 22 3C0 - 3C5 3C6 - 3C7 3C8 - 3CF 3D0 - 3D3 23 3E0 - 3E5 3E6 - 3E7 3E8 - 3EF 3F0 - 3F3 24 400 - 405 406 - 407 408 - 40F 410 - 413 25 420 - 425 426 - 427 428 - 42F 430 - 433 26 440 - 445 446 - 447 448 - 44F 450 - 453 27 460 - 465 466 - 467 468 - 46F 470 - 473 28 480 - 485 486 - 487 488 - 48F 490 - 493 29 4A0 - 4A5 4A6 - 4A7 4A8 - 4AF 4B0 - 4B3 30 4C0 - 4C5 4C6 - 4C7 4C8 - 4CF 4D0 - 4D3 31 4E0 - 4E5 4E6 - 4E7 4E8 - 4EF 4F0 - 4F3 Mailbox 0 is a receive-only mailbox, and all the rest of mailbox 1 to mailbox 31 can operate as both receive and transmit mailboxes according to the MBC (Mailbox Configuration) bits in the message control. Figure 17.3 shows the configuration of a mailbox in detail. Rev. 5.00 Feb. 24, 2010 Page 427 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) Important: If mailbox 31 is used as a transmit buffer, there is a usage limitation. For details, see section 17.8, Usage Notes. Address Register Name HCAN0 Data Bus HCAN1 15 14 13 12 11 MBx[0] to [1] H'100+N*32 H'900+N*32 MBx[2] to [3] H'102+N*32 MBx[4] to [5] H'104+N*32 H'904+N*32 CCM TTE NMC ATX DART 10 9 MBx[6] H'106+N*32 H'906+N*32 H'108+N*32 H'908+N*32 7 6 5 4 STDID[10:0] 0 H'902+N*32 MBx[7] to [8] 8 3 RTR 2 1 IDE EXIDT[17:16] EXTID[15:0] MBC[2:0] 0 0 Access Size 16 bits TCT CBE CLE DLC[3:0] Timestamp[15:0] Field Name 16 bits Control 8/16 bits 16 bits MSG_DATA_0 (first Rx/Tx byte) MSG_DATA_1 8/16 bits MBx[9] to [10] H'10A+N*32 H'90A+N*32 MSG_DATA_2 MSG_DATA_3 8/16 bits MBx[11] to [12] H'10C+N*32 H'90C+N*32 MSG_DATA_4 MSG_DATA_5 8/16 bits MBx[13] to [14] H'10E+N*32 H'90E+N*32 MSG_DATA_6 MSG_DATA_7 8/16 bits Timestamp Data MBx[15] to [16] H'110+N*32 H'910+N*32 Local acceptance filter mask 0 (LAFM0)/Tx trigger time 0 (TTT0) 16 bits LAFM/Tx MBx[17] to [18] H'112+N*32 H'912+N*32 Local acceptance filter mask 1 (LAFM1)/Tx trigger time 1 (TTT1) 16 bits control trigger Notes: 1. All bits shadowed in gray are reserved and the write value should be 0. Values read out in the initial state are not guaranteed. 2. ATX, DART, and CLE are not supported by mailbox 0 and the MBC setting of mailbox 0 is limited. 3. If the CAN bus is configured in little endian (MCR4 = 1), transmission is started from MSG_DATA_1 instead of MSG_DATA_0 (i.e. the sequence becomes: MSG_DATA_1, MSG_DATA_0, MSG_DATA_3, MSG_DATA_2, MSG_DATA_5, MSG_DATA_4, MSG_DATA_7, and MSG_DATA_6). 4. x/N: 0 to 31 (indicates the mailbox number) Figure 17.3 Mailbox-N Configuration 17.3.2 Message Control Field Register Name Address Bit Bit Name MBx[0], MBx[1]* H'100 + N x 32 15 Description Reserved The write value should be 0. The read value is not guaranteed. 14 to 4 STDID [10:0] Standard ID Set the ID (standard ID) of data frames and remote frames. 3 RTR Remote Transmission Request Distinguishes between data frames and remote frames. This bit is overwritten by receive CAN frames depending on data frames or remote frames. Important: Note that, when the ATX bit is set with the setting MBC = 001 the RTR bit cannot be set. When a remote frame is received, the host CPU can be notified by the corresponding RFPR or IRR2 (remote frame request interrupt), however, as the HCAN needs to transmit the current message as a data frame, the RTR bit remains 0. 0: Data frame 1: Remote frame 2 IDE ID Extension Distinguishes between the standard format and extended format of CAN data frames and remote frames. 0: Standard format 1: Extended format Rev. 5.00 Feb. 24, 2010 Page 428 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) Register Name Address Bit MBx[0], MBx[1]* H'100 + N x 32 1, 0 Bit Name Description EXTID [17:16] Extended ID MBx[2], MBx[3]* H'102 + N x 32 15 to 0 EXTID [15:0] Set the ID (extended ID) of data frames and remote frames. MBx[4], MBx[5]* H'104 + N x 32 15 CCM CAN-ID Compare Match When this bit is set, message reception in the corresponding mailbox can generate two triggers. If TCR9 is set to 1, TCR14 is cleared to freeze ICR0. If TCR10 is set to 1, TCNTR (timer counter register) is automatically cleared and the LOSR (local offset register) value is set. Important: This function is not supported by this LSI. Thus the write value should be 0. Values read out in the initial state are not guaranteed. 14 TTE Time Trigger Enable When this bit is set, a mailbox in which TXPR has been already set transmits a message at a time set in the Tx trigger time field. Important: If this bit is set, a failure occurs during message transmission. Therefore setting prohibited. The write value should be 0. Values read out in the initial state are not guaranteed. 13 NMC New Message Control When this bit is cleared, a mailbox in which RXPR/RFPR has been already set does not store the new message but retains the previous one and sets the UMSR corresponding bit. When this bit is set, a mailbox in which RXPR/RFPR has been already set stores the new message and sets the UMSR corresponding bit. If a message is received in a mailbox in overwrite mode (NMC = 1), the host CPU must perform an additional check at the end of the data reading from the mailbox in order to guarantee that the mailbox data have not been corrupted during such operation by another receive message. The additional check, to be performed at the end of the mailbox access, consists in verifying that the associated bit of UMSR has not been set and so no overwrite has occurred; in case such bit is set data have been corrupted and so the message must be discarded. 12 ATX Automatic Transmission of Data Frame When this bit is set to 1 and a remote frame is received in the mailbox, a data frame is automatically transmitted from the same mailbox using the current contents of the message data. The scheduling of transmission is controlled by the CAN ID. In order to use this function, the MBC[2:0] bits should be set to 001. When transmission is performed by this function, the DLC (data length code) to be used is the one that has been received. Important: Note that, when this function is used, the RTR bit is not set even if a remote frame is received. When a remote frame is received, the host CPU will be notified by RFPR or IRR2 (remote frame request interrupt), however, as the HCAN needs to transmit the current message as a data frame, the RTR bit remains 0. Rev. 5.00 Feb. 24, 2010 Page 429 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) Register Name Address Bit MBx[4], MBx[5]* H'104 + N x 32 11 Bit Name DART Description Disable Automatic Retransmission When this bit is set, it disables the automatic retransmission of a message in the event of an error on the CAN bus or an arbitration lost on the CAN bus. When this function is used, the corresponding TXCR bit is automatically set at the start of transmission. When this bit is cleared, the HCAN tries to transmit the message as many times as required until it is successfully transmitted or it is cancelled by the TXCR. Important: This function is not supported by this LSI. Thus the write value should be 0. Values read out in the initial state are not guaranteed. 10 to 8 MBC[2:0] Mailbox Configuration Mailbox functions are set as shown in table 17.3. When MBC = 111, the mailbox is inactive, i.e., it does not receive or transmit a message regardless of TXPR or other settings. When MBC = 000 and the TTE bit is set, the Tx-trigger time field becomes available. The MBC = 110 or 011 setting is prohibited. When MBC is set to any other value, the LAFM field becomes available. Important: MB0 should be used as receive-only (MBC = 010). 7 Reserved The write value should be 0. Values read out in the initial state are not guaranteed. 6 TCT Timer Counter Transmission When this bit is set, a mailbox is set for transmission, and the DLC is set to 4, the TCNTR value, at the SOF, is embedded in the second and third bytes of the message data, instead of MSG_DATA_2 and MSG_DATA_3, and the CYCLE_COUNT in the first byte instead of MSG_DATA_0[3:0] when this mailbox starts transmission. This function will be useful when the HCAN performs a time master role to transmit the time reference message. For example, considering that two HCAN controllers are connected in the same network and that the receiver stores the message in mailbox N, the data format is shown as Figure 17.4 depending on the endian setting for the CAN bus (MCR4). Important: This function is not supported by this LSI. Thus the write value should be 0. The read value is not guaranteed. Rev. 5.00 Feb. 24, 2010 Page 430 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) Register Name Address Bit MBx[4], MBx[5]* H'104 + N x 32 5 Bit Name CBE Description CAN Bus Error An external fault-tolerant CAN transceiver can be used together with the HCAN module. If the error output pin of the transceiver (normally active low) is connected to the CAN_NERR pin of this LSI, the value of the CAN_NERR pin is stored into this bit at the end of each transmission/reception (if the message is stored). The inverted value of the CAN_NERR pin is set to this bit. If the error output pin is active high, the setting value is not inverted. When this bit is set, it indicates a potential physical error with the CAN bus. As the CAN_NERR value is updated after the transmission or reception in the corresponding mailbox, noninterrupt is dedicated to this function but instead the normal transmit end interrupt (IRR6) and normal receive end interrupt (IRR2) should be considered. Important: This function is not supported by this LSI. Thus the write value should be 0. Values read out in the initial state are not guaranteed. 4 CLE Transmit Clear Enable When this bit is set, message reception in the corresponding mailbox cancels the wait messages in the transmission queue. This action is notified by IRR8 and ABACK. Important: This function is not supported by this LSI. Thus the write value should be 0. Values read out in the initial state are not guaranteed. 3 to 0 DLC[3:0] Data Length Code Indicate the number of data bytes to be transmitted in a data frame. DLC[3:0] Data Length 0000 0 bytes 0001 1 byte 0010 2 bytes 0011 3 bytes 0100 4 bytes 0101 5 bytes 0110 6 bytes 0111 7 bytes 1xxx 8 bytes Legend: x: Don't care Note: * x/N: 0 to 31 (Indicates the mailbox number) Rev. 5.00 Feb. 24, 2010 Page 431 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) Table 17.3 Mailbox Configuration (Setting of MBC[2:0] Bits) MBC[2] MBC[1] MBC[0] Data Frame Remote Frame Data Frame Remote Frame Transmission Transmission Reception Reception Description 0 0 0 Yes Yes No No * Not allowed for mailbox 0 0 0 1 Yes Yes No Yes * Can be used with ATX * Not allowed for mailbox 0 * LAFM can be used * Allowed for mailbox 0 * LAFM can be used * Not allowed for mailbox 0 * LAFM can be used * Not allowed for mailbox 0 * LAFM can be used 0 1 0 No No Yes Yes 0 1 1 1 0 0 No Yes Yes Yes 1 0 1 No Yes Yes No Setting prohibited 1 1 0 Setting prohibited 1 1 1 Mailbox inactive Important: If mailbox 31 is used as a transmit buffer, there is a usage limitation. For details, see section 17.8, Usage Notes. Message Data Field when TCT = 1: Register Name Data Bus Address HCAN0 HCAN1 MBx[7] to [8] H'108+N*32 H'908+N*32 MBx[9] to [10] 15 14 13 12 11 10 9 8 Cycle_Counter (first Rx/Tx byte) 7 6 5 4 3 2 1 0 Access Size MSG_DATA_1 8/16 bits H'10A+N*32 H'90A+N*32 TCNTR[7:0] TCNTR[15:8] 8/16 bits MBx[11] to [12] H'10C+N*32 H'90C+N*32 MSG_DATA_4 MSG_DATA_5 8/16 bits MBx[13] to [14] H'10E+N*32 H'90E+N*32 MSG_DATA_6 MSG_DATA_7 8/16 bits Field Name Data Big endian MBx[7] to [8] H'108+N*32 H'908+N*32 MSG_DATA_1 Cycle_Counter (first Rx/Tx byte) 8/16 bits MBx[9] to [10] H'10A+N*32 H'90A+N*32 TCNTR[15:8] TCNTR[7:0] 8/16 bits MBx[11] to [12] H'10C+N*32 H'90C+N*32 MSG_DATA_5 MSG_DATA_4 8/16 bits MBx[13] to [14] H'10E+N*32 H'90E+N*32 MSG_DATA_7 MSG_DATA_6 8/16 bits Data Little endian [Legend] x/N: 0 to 31 (Indicates the mailbox number) Figure 17.4 Message Data Field Rev. 5.00 Feb. 24, 2010 Page 432 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) Timestamp Fields: Records the timestamp on messages for transmission/reception. The timestamp will be a useful function to monitor if messages are received/transmitted within expected schedule or if messages for transmission are scheduled in the appropriate order. Register Name Address Bit Bit Name MBx[6]* H'106 + N x 32 15 to 0 TimeStamp [15:0] Description Message Reception: During message reception, when the SOF or EOF is detected, ICR1 (input capture register 1) always captures the TCNTR (timer counter register) value or the value of Cycle_Counter + TCNTR[15:4], depending on the value of bit 3 in TMR (Timer mode register), at either SOF or EOF depending on the value in TCR13 (timer control register), and the ICR1 value is stored into the timestamp field of the corresponding mailbox. Important: Capturing at the SOF is not supported by the SH7059. Thus TCR13 should be set to EOF detection mode. Message Transmission: During message transmission, the TCNTR (timer counter register) value or the value of Cycle_Counter + TCNTR[15:4], depending on the value of bit 3 in TMR (timer mode register) is captured when either the TXPR bit or TXACK bit is set depending on the value in TCR12, and the captured value is stored into the timestamp field of the corresponding mailbox. Important: Capturing when the TXPR bit is set is not supported by this LSI. In this LSI, activating TCNTR (the timer counter) may cause problems (the timer is not to be used). Therefore, the time-stamp function is not supported. The write value should be 0. Values read out in the initial state are not guaranteed. Note: * 17.3.3 x/N: 0 to 31 (Indicates the mailbox number) Message Data Fields Register Name Address Bit Bit Name MBx[7], MBx[8]* H'108 + N' x 32 15 to 8, MSG_DATA_0, 7 to 0 MSG_DATA_1 MBx[9], MBx[10]* H'10A + N x 32 15 to 8, MSG_DATA_2, 7 to 0 MSG_DATA_3 MBx[11], MBx[12]* H'10C + N x 32 15 to 8, MSG_DATA_4, 7 to 0 MSG_DATA_5 MBx[13], MBx[14]* H'10E + N x 32 15 to 8, MSG_DATA_6, 7 to 0 MSG_DATA_7 Note: * Description Store the CAN message data that is transmitted or received. MSG_DATA_0 corresponds to the first data byte that is transmitted or received. x/N: 0 to 31 (Indicates the mailbox number) Rev. 5.00 Feb. 24, 2010 Page 433 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) 17.3.4 Local Acceptance Filter Mask (LAFM)/Tx-Trigger Time (TTT) This area is used as the local acceptance filter mask (LAFM) for receive boxes or as the Tx-trigger time (TTT) for transmit boxes. LAFM: When the MBC bits are set to 001, 010, 011, 100, and 101, this field becomes the LAFM field. The LAFM is comprised of two 16-bit readable/writable areas. It allows a mailbox to accept more than one receive IDs. Data Bus Address Register Name HCAN0 HCAN1 15 MBx[15], MBx[16] H'110 + N x 32 H'910 + N x 32 0 MBx[17], MBx[18] H'112 + N x 32 H'912 + N x 32 14 13 12 11 10 9 8 7 6 STDID[10:0] EXTID[15:0] 5 4 3 2 0 0 1 0 EXTID[17:16] Access Size Field Name 16 bits LAFM field 16 bits [Legend] x/N: 0 to 31 (Indicates the mailbox number) Figure 17.5 Acceptance Filter If a bit is set in the LAFM, the corresponding bit of a received CAN ID is ignored when the HCAN searches a mailbox with the matching CAN ID. If the bit is cleared, the corresponding bit of a received CAN ID must match the STD_ID/EXT_ID set in the mailbox to be stored. The configuration of the LAFM is same as the message control in a mailbox. If this function is not required, it must be filled with 0. Notes: 1. When the LAFM is used, the HCAN starts to find a matching ID from mailbox 31 down to mailbox 0. As soon as the HCAN finds one, it stops the search and stores the message into the mailbox. This means that a received message can only be stored into one mailbox. 2. When a message is received and a matching mailbox is found, the whole message is stored into the mailbox. This means that, if the LAFM is used, the STD_ID, RTR, IDE, and EXT_ID differ to the ones originally set as they are updated with the STD_ID, RTR, IDE, and EXT_ID of the received message. 3. If the setting of the LAFM register that has already been set is changed, the HCAN should be set to halt mode before changing the setting. Do not access the LAFM during operation. 4. Do not access the undefined addresses. Correct operation cannot be guaranteed. LAFM Field: Register Name Address Bit MBx[15], MBx[16] H'110 + N x 32 15 Bit Name Description Reserved The write value should be 0. Values read out in the initial state are not guaranteed. 14 to 4 STDID_LAFM Filter Mask Bits[10:0] for CAN Base ID[10:0] [10:0] 0: Corresponding bit to CAN base ID set in mailbox 0 is valid 1: Corresponding bit to CAN base ID set in mailbox 0 is invalid 3, 2 Reserved The write value should be 0. Values read out in the initial state are not guaranteed. 1, 0 EXTID_LAFM Filter Mask Bits[17:16] for CAN Extended ID[17:16] [17:16] 0: Corresponding bit to extended CAN base ID is valid 1: Corresponding bit to extended CAN base ID is invalid MBx[17], MBx[18] H'112 + N x 32 15 to 0 EXTID_LAFM Filter Mask Bits[15:0] for CAN Extended ID[15:0] [15:0] 0: Corresponding bit to extended CAN base ID is valid 1: Corresponding bit to extended CAN base ID is invalid Note: * x/N: 0 to 31 (Indicates the mailbox number) Rev. 5.00 Feb. 24, 2010 Page 434 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) TTT: When the MBC bits are set to 000, this field becomes a Tx-trigger time (TTT) field. The TTT is comprised of two 16-bit readable/writable areas. Data Bus Address Register Name HCAN0 Access Size Field Name HCAN1 MBx[15], MBx[16] H'110 + N x 32 H'910 + N x 32 MBx[17], MBx[18] H'112 + N x 32 H'912 + N x 32 15 14 13 12 0 0 0 0 11 10 9 8 7 6 5 4 0 0 3 2 1 Tx-trigger time (absolute value) Offset[3:0] 0 0 0 16 bits Rep_Count[3:0] Tx-trigger control field 16 bits [Legend] x/N: 0 to 31 (Indicates the mailbox number) Figure 17.6 Tx-Trigger Control Field Tx-Trigger Time Field: Register Name Address Bit Bit Name MBx[15], MBx[16]* H'110 + N x 32 15 to 0 TTT MBx[17], MBx[18]* H'112 + N x 32 15 to 12 Description Tx-Trigger Time Set the time that triggers message transmission using the absolute value. Reserved The write value should be 0. Values read out in the initial state are not guaranteed. 11 to 8 Offset 7 to 4 Offset Reserved The write value should be 0. Values read out in the initial state are not guaranteed. 3 to 0 Note: * Rep_Count [3:0] Repeat Counter Set the transmit cycle. x/N: 0 to 31 (Indicates the mailbox number) The first 16-bit area sets the time that triggers message transmission using the absolute value. The second 16-bit area sets the basic cycle in the system matrix where the transmission must start (offset) and in the system matrix of the frequency for periodic transmission. When TXPR is set, the corresponding Tx-trigger time (TTT), repeat counter, and offset are downloaded into an internal register. When the internal TTT register matches the TCNTR value and the internal offset matches the CCR (cycle counter register) value, the corresponding mailbox automatically starts transmission. In order to enable this function, the TTE (time trigger enable) bit must be enabled (set to 1) and the timer (TCNTR) must be running (TCR15 = 1). When the TTE is cleared to 0 and the corresponding TXPR bit is set, it joins the queue for transmission immediately. If the repeat counter is not 0, transmission occurs periodically every Rep_Count's basic cycle from CCR = offset to CCR = MAX_CYCLE. In such case once TXPR is set by software, the HCAN does not clear the corresponding TXPR bit to carry on performing the periodic transmission. In order to stop the periodic transmission, TXPR must be cleared by TXCR or the Rep_Count field must be cleared. If the repeat counter is 0, transmission occurs only once at the programmed basic cycle (i.e. CCR = offset and TCNTR = TTT). The Tx-trigger time must not be set outside the TCNTR cycle if the compare-match timer clear/set function is used (by TCMR0 or CCM). During a time triggered transmission, only another one time triggered transmission can be triggered and a minimum difference of 200 peripheral clock cycles between them is allowed. Rev. 5.00 Feb. 24, 2010 Page 435 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) 17.4 HCAN Control Registers The following sections describe the HCAN control registers. Table 17.4 shows the address map. Note: These registers can only be accessed in word size (16 bits). Table 17.4 HCAN Control Registers Channel Address Register Name Abbreviation Access Size (Bits) 0 H'FFFFD000 Master control register_0 MCR_0 16 H'FFFFD002 General status register_0 GSR_0 16 H'FFFFD004 HCAN-II_bit configuration register 1_0 HCAN-II_BCR1_0 16 1 17.4.1 H'FFFFD006 HCAN-II_bit configuration register 0_0 HCAN-II_BCR0_0 16 H'FFFFD008 Interrupt register_0 IRR_0 16 H'FFFFD00A Interrupt mask register_0 IMR_0 16 H'FFFFD00C Transmit error counter_0/ Receive error counter_0 TEC_0/REC_0 16 H'FFFFD800 Master control register_1 MCR_1 16 H'FFFFD802 General status register_1 GSR_1 16 H'FFFFD804 HCAN-II_bit configuration register 1_1 HCAN-II_BCR1_1 16 H'FFFFD806 HCAN-II_bit configuration register 0_1 HCAN-II_BCR0_1 16 H'FFFFD808 Interrupt register_1 IRR_1 16 H'FFFFD80A Interrupt mask register_1 IMR_1 16 H'FFFFD80C Transmit error counter_1/ Receive error counter_1 TEC_1/REC_1 16 Register Descriptions Legends for register descriptions are as follows: Initial Value -- R/W R R/WC0 R/WC1 W --/W 17.4.2 : Register value after a reset : Undefined value : Readable/writable bit. The write value can be read. : Read-only bit. The write value should always be 0. : Readable/writable bit. If 0 is written to this bit, the bit is initialized; if 1 is written to this bit, it is ignored. : Readable/writable bit. If 1 is written to this bit, the bit is initialized; if 0 is written to this bit, it is ignored. : Write-only bit. Reading prohibited. If reserved, the write value should always be 0. : Write-only bit. The read value is undefined. Master Control Register_n (MCR_n) (n = 0, 1) The master control register (MCR) is a 16-bit readable/writable register that controls the HCAN. Bit: 15 14 13 12 11 10 9 8 7 6 TST7 TST6 TST5 TST4 TST3 TST2 TST1 TST0 MCR7 Initial Value: 0 R/W R/W 5 4 3 MCR5 MCR4 2 1 0 MCR2 MCR1 MCR0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. 5.00 Feb. 24, 2010 Page 436 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) Bit Bit Name Initial Value R/W Description 15 TST7 0 R/W Test Mode Enables/disables the test modes settable by TST[6:0]. When this bit is set, the following TST[6:0] are enabled. 0: HCAN is in normal mode 1: HCAN is in test mode 14 TST6 0 R/W Write CAN Error Counters Enables the TEC (transmit error counter) and REC (receive error counter) to be writable. The same value is written to TEC and REC at the same time. The maximum value that can be written to TEC and REC is D'255 (H'FF). This means that the HCAN cannot be forced into the bus off state. Before writing to TEC and REC, the HCAN needs to enter halt mode, and when writing to TEC and REC, the TST7 bit (MCR15) should be set to 1. The value written to TEC is used to write REC. 0: TEC/REC is not writable but read-only 1: TEC/REC is writable with the same value at the same time 13 TST5 0 R/W Forced Error Passive Forces the HCAN to behave as an error passive node, regardless of the error counters. 0: State of HCAN depends on error counters 1: HCAN behaves as an error passive node, regardless of error counters 12 TST4 0 R/W Automatic Acknowledge Mode Allows the HCAN to generate its own acknowledge bit in order to enable the self test. In order to enter self-test mode, the message transmitted needs to be read back, and there are 2 settings for this. One is to set (Enable Internal Loop = 1, Disable Tx Output = 1, and Disable Rx Input = 1), so that the Tx value is internally provided to the Rx. The other way is to set (Enable Internal Loop = 0, Disable Tx Output = 0, and Disable Rx Input = 0) and connect the Tx and Rx onto the CAN bus so that the transmitted data can be received via the CAN bus. 0: HCAN does not generate its own acknowledge bit 1: HCAN generates its own acknowledge bit 11 TST3 0 R/W Disable Error Counters Enables/disables the error counters (TEC/REC). When this bit is disabled, the error counters (TEC/REC) remain unchanged and retain the current value. When this bit is enabled, the error counters (TEC/REC) operate according to the CAN specification. 0: Error counters (TEC/REC) operate according to the CAN specification 1: Error counters (TEC/REC) remain unchanged and retain the current value 10 TST2 0 R/W Disable Rx Input Controls the Rx to be supplied to the CAN Interface block. When this bit is enabled, the Rx pin value is supplied to the CAN interface block. When this bit is disabled, the Rx value for the CAN block is always retained or the Tx value internally connected if Enable Internal Loop = 1. 0: Value of external Rx pin is supplied to the CAN interface block 1: Enable Internal Loop = 0: Rx value is retained for the CAN interface block Enable Internal Loop = 1: Tx value is internally supplied to the CAN interface block Rev. 5.00 Feb. 24, 2010 Page 437 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) Bit Bit Name Initial Value R/W Description 9 TST1 0 R/W Disable Tx Output Controls the Tx to output transmit data or retain data. When this bit is enabled, the value of the internal transmit output pin appears on the Tx pin. When this bit is disabled, the Tx pin always retains the value. 0: Value of external Tx pin is supplied from the CAN interface block 1: Enable Internal Loop = 0: Tx value is retained 8 TST0 0 R/W Enable Internal Loop = 1: Tx is supplied to the internal Rx Enable Internal Loop Enables/disables the internal Tx looped back to the internal Rx. For details, see section 17.7.1 Test Mode settings. 0: Rx is supplied from the Rx Pin 1: Rx is supplied from the internal Tx signal 7 MCR7 0 R/W Cancel HCAN-II Sleep Mode Enables or disables auto-wake mode. When this bit is set, the HCAN automatically cancels sleep mode (MCR5) by detecting CAN bus activity (dominant bit). When this bit is not set, the HCAN does not automatically cancel sleep mode. 0: Auto-wake by CAN bus activity disabled 1: Auto-wake by CAN bus activity enabled 6 -- 0 R Reserved The write value should always be 0. The read value is not guaranteed. 5 MCR5 0 R/W HCAN-II Sleep Mode Enables or disables sleep mode transition. When this bit is set, sleep mode is enabled. The HCAN waits for the completion of the current bus access before entering sleep mode. Until this mode is terminated the HCAN will ignore CAN bus operation. The two error counters (REC, TEC) will retain the same value during and after sleep mode. This mode will be exited in two ways: * Write 0 to this bit * If MCR7 is enabled, after detecting a dominant bit on the CAN bus When exiting this mode, the HCAN will synchronize with the CAN bus (by checking for 11 recessive bits) before restart. This means that, when the second way is used, the HCAN cannot receive the first message, however, CAN transceivers have the same feature, and software needs to be designed in this manner. Note: This mode is same as setting the module to halt mode and stopping the clock. This means that, the interrupt is generated from IRR0 when entering sleep mode. During sleep mode, only the MPI block is accessible, i.e., MCR/GSR/IRR/IMR are accessible. However, IRR1 cannot be cleared during sleep mode as it is an ORed signal of RXPR that cannot be cleared during sleep mode, therefore, set halt mode first and then make a transition to sleep mode. 0: HCAN sleep mode is exited 1: Transition to HCAN sleep mode enabled Note: Do not access to MB during sleep mode. Certain restrictions apply when using sleep mode. Be sure to read section 17.8, Usage Notes. Rev. 5.00 Feb. 24, 2010 Page 438 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) Bit Bit Name Initial Value R/W Description 4 MCR4 0 R/W CAN Endian Mode Controls whether the HCAN should transmit the messages in little endian mode or big endian mode. By using this bit, in other words, it is possible to set different endian mode to the HCAN and the external network. Note that this bit is only valid when data field is transmitted/received. 0: Data field transmitted/received in big endian mode 1: Data field transmitted/received in little endian mode 3 -- 0 R/W Reserved The initial value should be retained. 2 MCR2 0 R/W Message Transmission Priority Selects the order of transmission for pending transmit data. When this bit is set, pending transmit data are sent in order of the bit position in the transmit wait register (TXPR). The order of transmission starts from mailbox 31 as the highest priority, and then down to mailbox 1 (if those mailboxes are configured for transmission). Important: This function cannot be used for timer triggered transmission. When this bit is cleared, all messages for transmission are queued with respect to their priority (by running internal arbitration). The highest priority message has the arbitration field with the lowest digital value and is transmitted first. The internal arbitration includes the RTR bit and the IDE bit. 0: Transmission order determined by message ID priority 1: Transmission order determined by mailbox number priority (mailbox 31 mailbox 1) 1 MCR1 0 R/W Halt Request Setting this bit causes the CAN controller to complete its current operation and then to cut off the CAN bus. The HCAN remains in halt mode until this bit is cleared. During halt mode, the CAN interface does not join the CAN bus activity or does not store messages nor transmit messages. All of the registers and mailbox contents are retained. The HCAN will complete the current operation if it is a transmitter or a receiver, and then enter halt mode. If the CAN bus is in the idle or intermission state, the HCAN will enter halt mode immediately. Entering halt mode is notified by IRR0 and GSR4. If a halt request is made during bus off, the HCAN-II remains bus off even after 128 x 11 recessive bits. In order to exit this state, the halt state needs to be canceled by software. In halt mode, the HCAN configuration can be modified as it does not join the bus activity. This bit has to be cleared to 0 to re-join the CAN bus. After this bit is cleared, the CAN interface waits until it detects 11 recessive bits, and then joins the CAN bus. 0: Normal operating mode 1: Halt mode transition request Rev. 5.00 Feb. 24, 2010 Page 439 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) Bit Bit Name Initial Value R/W Description 0 MCR0 1 R/W Reset Request Controls resetting of the HCAN module. After detecting a reset request, the HCAN controller enters its reset routine, re-initializes the internal logic, and then set GSR3 and IRR0 to notify reset mode. Then the HCAN enters reset mode. During re-initialization, all the registers are cleared. This bit has to be cleared by writing a 0 to join the CAN bus. After this bit is cleared, the HCAN needs to be re-configured, waits until it detects 11 recessive bits, and then joins the CAN bus. After a power-on reset, this bit and GSR3 are always set. This means that a reset request has been made and the HCAN is in re-configuration mode. 0: CAN interface normal operating mode (MCR0 = 0 and GSR3 = 0) Setting condition: When 0 is written after an HCAN reset 1: Reset mode transition request of CAN interface 17.4.3 General Status Register_n (GSR_n) (n = 0, 1) The general status register (GSR) is a 16-bit read-only register that indicates the status of the HCAN. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GSR5 GSR4 GSR3 GSR2 GSR1 GSR0 Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 R/W: R R R R R R Bit Bit Name Initial Value R/W Description 15 to 6 -- All 0 Reserved The write value should be 0. The read value is not guaranteed. 5 GSR5 0 R Error Passive Status Indicates whether the CAN interface is error passive or not. This bit is set as soon as the HCAN enters the error passive state and is cleared when the module enters again the error active state. This means that this bit will remain high during error passive and during bus off. Thus to find out the correct state, both GSR5 and GRS0 must be considered. 0: HCAN is not error passive Setting condition: HCAN is in error active state 1: HCAN is error passive (if GSR0 = 0) Setting condition: When TEC 128 or REC 128 4 GSR4 0 R Halt/Sleep Status Indicates whether the CAN interface is in the halt/sleep state or not. 0: HCAN is not in the halt state nor sleep state 1: Halt mode (if MCR1 = 1) or sleep mode (if MCR5 = 1) Setting condition: If MCR1 is set and the CAN bus is either in intermission or idle state Rev. 5.00 Feb. 24, 2010 Page 440 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) Bit Bit Name Initial Value R/W 3 GSR3 1 R Description Reset Status Indicates whether the CAN interface is in the reset state (configuration mode) or not. 0: Normal operating state Setting condition: After an HCAN internal reset 1: Reset state (configuration mode) 2 GSR2 1 R Message Transmission Complete Flag Indicates to the host CPU if the HCAN is processing transmission requests or if a transmission is completed. This bit is an ORed signal of all the TXPR bits. Note that the IRR8 (slot empty) is an ORed signal of all the TXACK/ABACK bits. 0: Transmission in progress 1: There is no message requested for transmission 1 GSR1 0 R Transmit/Receive Warning Flag Indicates an error warning. 0: Reset condition: When TEC < 96, or REC < 96, or TEC 256 1: When 96 TEC < 256 or 96 REC 0 GSR0 0 R Bus Off Flag Indicates that the HCAN is in the bus off state. 0: Reset condition: Recovery from bus off state 1: When TEC 256 (bus off state) Rev. 5.00 Feb. 24, 2010 Page 441 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) 17.4.4 HCAN-II_Bit Configuration Register n (HCAN-II_BCR0_n, HCAN-II_BCR1_n) (n = 0, 1) The bit configuration registers (BCR0 and BCR1) are 16-bit readable/writable registers that set CAN bit timing parameters and the baud rate prescaler for the CAN interface. For the following description the following definition is used: BRP fclk Timequanta = Where: BRP (baud rate predivider) is stored in BCR0 and fclk is P (peripheral clock). * BCR1 For details on TSEG1 and TSEG2 settings, see table 17.5. Bit: 15 14 13 12 11 10 TSEG1[3:0] Initial Value: 0 R/W: R/W 9 8 7 6 TSEG2[2:0] 5 4 3 2 SJW[1:0] 1 0 EG BSP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 15 TSEG1[3] 0 R/W Time Segment 1 (TSEG1[3:0] = BCR1[15:12]) 14 TSEG1[2] 0 R/W 13 TSEG1[1] 0 R/W Set the segment for absorbing output buffer, CAN bus, and input buffer delay. A value from 4 to 16 time quanta can be set. 12 TSEG1[0] 0 R/W 11 -- 0 -- 0000: Setting prohibited 0001: Setting prohibited 0010: Setting prohibited 0011: PRSEG + PHSEG1 = 4 time quanta 0100: PRSEG + PHSEG1 = 5 time quanta : 1111: PRSEG + PHSEG1 = 16 time quanta Reserved The write value should be 0. The read value is not guaranteed. 10 TSEG2[2] 0 R/W Time Segment 2 (TSEG2[2:0] = BCR1[10:8]) 9 TSEG2[1] 0 R/W 8 TSEG2[0] 0 R/W Set the segment for correcting 1-bit time error. A value from 2 to 8 time quanta can be set. 000: Setting prohibited 001: PHSEG2 = 2 time quanta (setting prohibited depending on the condition so see table 16.5) 010: PHSEG2 = 3 time quanta 011: PHSEG2 = 4 time quanta 100: PHSEG2 = 5 time quanta 101: PHSEG2 = 6 time quanta 110: PHSEG2 = 7 time quanta 111: PHSEG2 = 8 time quanta 7, 6 -- 0 -- Reserved The write value should be 0. The read value is not guaranteed. Rev. 5.00 Feb. 24, 2010 Page 442 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) Bit Bit Name Initial Value R/W Description 5 SJW[1] 0 R/W Re-Synchronization Jump Width (SJW[1:0] = BCR0[5:4]) 4 SJW[0] 0 R/W Set the synchronization jump width. 00: 1 time quantum 01: 2 time quanta 10: 3 time quanta 11: 4 time quanta 3, 2 -- All 0 -- Reserved The write value should be 0. The read value is not guaranteed. 1 EG 0 R/W Edge Select (EG = BCR1[1]) Selects at which edge is to be used for re-synchronization. In order to comply with the standard CAN, 0 should be set. 0: Re-synchronization is performed at falling edge of Rx 1: Re-synchronization is performed at both rising and falling edges of Rx 0 BSP 0 R/W Bit Sample Point (BSP = BCR1[0]) Sets the point at which data is sampled. Important: Sampling at three points is only available when the BRP[7:0] is programmed to be less than 4. 0: Bit sampling at one point (end of time segment 1) 1: Bit sampling at three points (end of time segment 1, and 1 time quantum before and after) * BCR0 Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BRP7 BRP6 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 15 to 8 -- All 0 -- Reserved 7 BRP[7] 0 R/W Baud Rate Prescale (BRP[7:0] = BCR0 [7:0]) 6 BRP[6] 0 R/W Set the clock used for 1 time quantum. 5 BRP[5] 0 R/W 4 BRP[4] 0 R/W 3 BRP[3] 0 R/W 2 BRP[2] 0 R/W 1 BRP[1] 0 R/W 00000000: 1 x P (peripheral clock) 00000001: 2 x P (peripheral clock) 00000010: 3 x P (peripheral clock) : (BRP + 1) x P (peripheral clock) 11111111: 256 x P (peripheral clock) 0 BRP[0] 0 R/W The write value should be 0. The read value is not guaranteed. Rev. 5.00 Feb. 24, 2010 Page 443 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) About Bit Configuration Register: 1-bit time (9-25 quanta) SYNC_SEG PRSEG 1 PHSEG1 PHSEG2 TSEG1 TSEG2 4-16 2-8 Quantum SYNC_SEG: Segment for establishing synchronization of nodes on the CAN bus. (Normal bit edge transitions occur in this segment.) PRSEG: Segment for adjusting physical delay between networks. PHSEG1: Buffer segment for correcting phase drift (positive). (This segment is extended when synchronization (resynchronization) is established.) PHSEG2: Buffer segment for correcting phase drift (negative). (This segment is shortened when synchronization (resynchronization) is established.) The CAN-bus bit rate is calculate as follows: Bit rate = fclk /{(BRP[7:0]+1) x ( (TSEG1[3:0]+1)+(TSEG2[2:0]+1)+SYNC_SEG )} The SYNC_SEG is fixed to 1 time quantum. fclk = P (peripheral clock) BCR setting constraints TSEG1 > TSEG2 SJW (SJW = 1 to 4) TSEG1 + TSEG2 + 3 = 8 to 25 time quantum These constraints allow the setting range shown in table 17.5 for TSEG1 and TSEG2 in the bit configuration register. Table 17.5 TSEG1 and TSEG2 Settings TSEG2 (BCR[10:8]) TSEG1(BCR[15:12]) Note: * 001* 010 011 100 101 110 111 2 3 4 5 6 7 8 0011 4 No Yes No No No No No 0100 5 Yes Yes Yes No No No No 0101 6 Yes Yes Yes Yes No No No 0110 7 Yes Yes Yes Yes Yes No No 0111 8 Yes Yes Yes Yes Yes Yes No 1000 9 Yes Yes Yes Yes Yes Yes Yes 1001 10 Yes Yes Yes Yes Yes Yes Yes 1010 11 Yes Yes Yes Yes Yes Yes Yes 1011 12 Yes Yes Yes Yes Yes Yes Yes 1100 13 Yes Yes Yes Yes Yes Yes Yes 1101 14 Yes Yes Yes Yes Yes Yes Yes 1110 15 Yes Yes Yes Yes Yes Yes Yes 1111 16 Yes Yes Yes Yes Yes Yes Yes When BPR [7:0] = H'00000000, TSEG [2:0] H'001. Rev. 5.00 Feb. 24, 2010 Page 444 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) Examples: 1. To have a bit rate of 1 Mbps with a P (peripheral clock) frequency of fclk = 20 MHz, it is possible to set: BRP[7:0] = 1, TSEG1[3:0] = 5, and TSEG2[2:0] = 2. Then BCR1 should be written to H'5200 and BCR0 to H'0001. 2. To have a bit rate of 500 kbps with a P (peripheral clock) frequency of fclk = 16 MHz, it is possible to set: BPR[7:0] = 1, TSEG1[3:0] = 9, TSEG2[2:0] = 4. Then BCR1 should be written to H'9400 and BCR0 to H'0001. 17.4.5 Interrupt Register_n (IRR_n) (n = 0, 1) The interrupt register (IRR) is a 16-bit readable/writable register that contains status flags for the various interrupt sources. * IRR Bit: 15 14 13 12 11 10 IRR 15 IRR 14 IRR 13 IRR 12 IRR 11 IRR 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R R R/W Initial Value: R/W: R/W 9 8 7 6 5 4 3 2 1 0 IRR9 IRR8 IRR7 IRR6 IRR5 IRR4 IRR3 IRR2 IRR1 IRR0 Bit Bit Name Initial Value R/W Description 15 IRR15 0 R/W Timer Compare Match Interrupt Flag 1 Indicates that a compare-match condition occurred to the timer compare match register 1 (TCMR1). When the value set in TCMR1 matches the timer value (TCMR1 = TCNTR), this bit is set. This bit is not set if the TCMR1 value is H'0000. 0: Timer compare match has not occurred to TCMR1 Clearing condition: Writing 1 1: Timer compare match has occurred to TCMR1 Setting condition: TCMR1 matches the timer value (TCMR1 = TCNTR) if TMR1 = 0 or matches Cycle_Count + TCNTR[15:4] if TMR1 = 1 14 IRR14 0 R/W Timer Compare Match Interrupt Flag 0 Indicates that a compare-match condition occurred to the timer compare match register 0 (TCMR0). When the value set in TCMR0 matches the timer value (TCMR0 = TCNTR), this bit is set. This bit is not set if the TCMR0 value is H'0000. 0: Timer compare match has not occurred to the TCMR0 Clearing condition: Writing 1 1: Timer compare match has occurred to the TCMR0 Setting condition: TCMR0 matches the timer value (TCMR0 = TCNTR) 13 IRR13 0 R/W Timer Overrun Interrupt Flag Indicates that the timer has overrun and is reset to the LOSR (local offset register) value. This bit is set even when TCMR0 is enabled to clear/set the timer value and its value is set to H'FFFF. 0: Timer has not overrun Clearing condition: Writing 1 1: Timer has overrun Setting condition: When the timer (TCNTR) changes from H'FFFF to H'0000 Rev. 5.00 Feb. 24, 2010 Page 445 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) Bit Bit Name Initial Value R/W Description 12 IRR12 0 R/W Bus Activity Interrupt Flag Indicates that a CAN bus activity is present. While the HCAN is in sleep mode and a recessive to dominant bit transition takes place on the CAN bus, this bit is set. The operation of this interrupt is set in the master control register (MCR7: Auto-wake mode). This interrupt is cleared by writing a 1 to this bit. Writing a 0 is ignored. 0: Bus idle state Clearing condition: Writing 1 1: CAN bus activity detected in HCAN sleep mode Setting condition: Recessive dominant bit transition detection while in sleep mode 11 IRR11 0 R/W Timer Compare Match Interrupt Flag 2 Indicates that a compare-match condition occurred to the timer compare match register 2 (TCMR2). When the value set in TCMR2 matches the timer value (TCMR2 = TCNTR) or matches Cycle_Count + TCNTR[15:4] depending on the TMR2 (timer mode register) setting, this bit is set. This bit is not set if the TCMR2 value is H'0000. 0: Timer compare match has not occurred to TCMR2 Clearing condition: Writing 1 1: Timer compare match has occurred to TCMR2 Setting condition: TCMR2 matches the timer value (TCMR2 = TCNTR) if TMR2 = 0 or matches Cycle_Count + TCNTR[15:4] if TMR2 = 1 10 IRR10 0 R/W Cycle Counter Overrun Interrupt Flag Indicates that the Cycle_Counter has reached the maximum value (CMAX). When the CCR counter matches the CMAX value (CCR = CMAX), this bit is set and CCR is cleared. Note that setting CMAX = 0 disables the Cycle_Counter and no interrupt is generated. 0: Cycle counter has not reached CMAX or CMAX = 0 Clearing condition: Writing 1 1: Cycle counter has reached CMAX and CMAX 0 Setting condition: CCR matches the CMAX value (CCR = CMAX) 9 IRR9 0 R Message Overrun/Overwrite Interrupt Flag Status flag indicating that new message has been received but the existing message in the mailbox has not been read due to the corresponding RXPR or RFPR set to 1. The received message is either abandoned (overrun) or overwritten dependant upon the NMC (new message control) bit. This bit is cleared by writing 1 to the correspondent bit in UMSR (unread message status register). Writing 0 is ignored. 0: No message overrun/overwrite Clearing condition: Clearing of all bits in UMSR 1: Receive message overrun and its storage has been rejected or message overwrite Setting condition: Message is received while the corresponding RXPR or RFPR = 1 and MBIMR = 0 Rev. 5.00 Feb. 24, 2010 Page 446 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) Bit Bit Name Initial Value R/W 8 IRR8 0 R Description Mailbox Empty Interrupt Flag Indicates that message transmission or transmission cancellation has been successfully made and this mailbox is now ready to accept a new message data for the next transmission. This bit is set when at least one TXPR bit is cleared. This bit is also set by an ORed signal of the TXACK and ABACK bits, therefore, this bit is automatically cleared when all the TXACK and ABACK bits are cleared. Writing 0 is ignored. Note that this bit does not represent that all TXPR bits are reset, whereas GSR2 does. 0: Messages set for transmission or transmission cancellation not processed Clearing condition: All the TXACK and ABACK bits are cleared 1: Message has been transmitted or canceled, and new message can be stored Setting condition: When one of the TXPR bits is cleared by completion of transmission or completion of transmission cancellation, i.e., when a TXACK or ABACK bit is set (if MBIMR = 0) 7 IRR7 0 R/W Overload Frame Interrupt Flag Indicates that the HCAN has transmitted an overload frame. It remains latched until a reset by writing 1 to this bit. Writing 0 is ignored. 0: Clearing condition: Writing 1 1: Setting condition: Overload frame transmitted 6 IRR6 0 R/W Bus Off/Bus Off Recover Interrupt Flag This bit is set when the HCAN enters the bus-off state or when the HCAN leaves bus-off and returns to error-active. This is because the existing condition that 11 recessive bits have received 128 times when TEC 256 at the node or in the bus-off state. This bit remains latched even when the HCAN node cancels the bus-off state, and needs to be cleared by software. GSR0 should be read to determine whether the HCAN has become bus-off or error active. This bit is cleared by writing 1 even if the HCAN is still in the bus-off state. Writing 0 is ignored. 0: Clearing condition: Writing 1 1: Bus off state caused by transmit error or error active state returning from bus-off Setting condition: When 11 recessive bits have received 128 times when TEC 256 at the node or in the bus-off state 5 IRR5 0 R/W Error Passive Interrupt Flag Indicates that the error passive state caused by the transmit or receive error counter. This bit is cleared by writing 1. Writing 0 is ignored. If this bit is cleared, the node may still be error passive. 0: Clearing condition: Writing 1 1: Error passive state caused by transmit/receive error Setting condition: When TEC 128 or REC 128 4 IRR4 0 R/W Receive Warning Interrupt Flag This bit is set and latched if the receive error counter (REC) reaches a value greater than 96. This bit is cleared by writing 1. Writing 0 is ignored. When the interrupt is cleared, REC still holds its value greater than 96. 0: Clearing condition: Writing 1 1: Error warning state caused by receive error Setting condition: When REC 96 Rev. 5.00 Feb. 24, 2010 Page 447 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) Bit Bit Name Initial Value R/W 3 IRR3 0 R/W Description Transmit Warning Interrupt Flag This bit is set and latched if the transmit error counter (TEC) reaches a value greater than 96. This bit is cleared by writing 1. Writing 0 is ignored. When the interrupt is cleared, TEC still holds its value greater than 96. 0: Clearing condition: Writing 1 1: Error warning state caused by transmit error Setting condition: When TEC 96 2 IRR2 0 R Remote Frame Request Interrupt Flag Indicates that a remote frame has been received in a mailbox. This bit is set if at least one receive mailbox contains a remote frame transmission request. This bit is cleared by ensuring all bits in the remote request wait register (RFPR) are cleared. Writing to this bit is ignored. 0: Clearing condition: Clearing of all bits in RFPR 1: At least one remote request is waiting Setting condition: When a remote frame is received and the corresponding MBIMR = 0 1 IRR1 0 R Receive Message Interrupt Flag Indicates that there are waiting data frames received. If at least one receive mailbox contains a waiting message, this bit is set. This bit is cleared when all bits in the receive message waiting register (RXPR) are cleared, i.e. there is no waiting message in any receive mailbox. A logical OR from each set receive mailbox. Writing to this bit is ignored. 0: Clearing condition: Clearing of all bits in RXPR 1: Data frame received and stored in mailbox Setting condition: When data is received and the corresponding MBIMR = 0 0 IRR0 1 R/W Reset/Halt/Sleep Interrupt Flag Indicates that the CAN interface has been reset or halted and the HCAN is now in configuration mode or in sleep mode. An interrupt signal will be generated through this bit to notify the change of the HCAN's state to the host CPU if an MCR0 (software reset), MCR1 (halt), or MCR5 (sleep) request occurs. GSR can be read after this bit is set to figure out which state the HCAN is in. Important: When a sleep mode request needs to be made, halt mode should be used beforehand. For details, see the MCR5 description. 0: Clearing condition: Writing 1 1: Transition to software reset mode, transition to halt mode, or transition to sleep mode without halt mode Setting condition: When reset/halt processing is completed after an MCR0 (software reset), MCR1 (halt), or MCR5 (sleep) is requested Rev. 5.00 Feb. 24, 2010 Page 448 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) 17.4.6 Interrupt Mask Register_n (IMR_n) (n = 0, 1) The interrupt mask register (IMR) is a 16-bit register that masks output of corresponding interrupt requests in the interrupt register (IRR). An interrupt request is masked if the corresponding bit is set to 1. This register can be read or written to at any time. IMR directly controls the generation of an interrupt request, but does not control the setting of the corresponding bit in IRR. * IMR Bit: 15 14 13 12 11 10 9 IMR15 IMR14 IMR13 IMR12 IMR11 IMR10 IMR9 Initial Value: 1 R/W: R/W 8 7 6 5 4 3 2 1 0 IMR8 IMR7 IMR6 IMR5 IMR4 IMR3 IMR2 IMR1 IMR0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 15 IMR15 1 R/W 14 IMR14 1 R/W Mask the corresponding IRR[15:0] interrupts. When this bit is set, the interrupt signal is masked, although the IRR setting is retained. 13 IMR13 1 R/W 12 IMR12 1 R/W 11 IMR11 1 R/W 10 IMR10 1 R/W 9 IMR9 1 R/W 8 IMR8 1 R/W 7 IMR7 1 R/W 6 IMR6 1 R/W 5 IMR5 1 R/W 4 IMR4 1 R/W 3 IMR3 1 R/W 2 IMR2 1 R/W 1 IMR1 1 R/W 0 IMR0 1 R/W 17.4.7 Transmit Error Counter_n (TEC_n) (n = 0, 1)/ Receive Error Counter_n (REC_n) (n = 0, 1) 0: Corresponding IRR is not masked (an interrupt request is generated for interrupt conditions) 1: Corresponding IRR interrupt is masked The transmit error counter (TEC)/receive error counter (REC) is a 16-bit readable/(writable) register that functions as a counter indicating the number of transmit/receive message errors on the CAN interface. The count value is stipulated in the CAN protocol specification (References 2 and 3). In normal mode, this register is read-only, and can only be modified by the CAN interface. This register can be cleared by a reset request (MCR0) or bus off. In test mode (i.e. MCR[15] = MCR[14] = 1), it is possible to write to this register. A same value can only be written to TEC and REC, and the value set in TEC is written to TEC and REC. When writing to this register, the HCAN needs to be in halt mode. This function is only intended for test purposes. [Important] While the HCAN-II is in the bus-off status, the TEC and REC values are undefined. Rev. 5.00 Feb. 24, 2010 Page 449 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) * TEC/REC Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Bit Bit Name Initial Value R/W Description 15 TEC7 0 R/W* Transmit Error Counter 14 TEC6 0 R/W* 13 TEC5 0 R/W* This register is incremented if an error is detected during transmission as specified on the CAN specification (see CAN specification document). 12 TEC4 0 R/W* 11 TEC3 0 R/W* 10 TEC2 0 R/W* 9 TEC1 0 R/W* 8 TEC0 0 R/W* 7 REC7 0 R/W* Receive Error Counter 6 REC6 0 R/W* 5 REC5 0 R/W* This register is incremented if an error is detected during reception as specified on the CAN specification (see CAN specification document). 4 REC4 0 R/W* 3 REC3 0 R/W* 2 REC2 0 R/W* 1 REC1 0 R/W* 0 REC0 0 R/W* Note: * It is only possible to write the value in test mode when MCR15 = MCR14 = 1. Rev. 5.00 Feb. 24, 2010 Page 450 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) 17.5 HCAN Mailbox Registers The HCAN mailbox registers control individual mailboxes. The address is mapped as follows. Note: These registers can only be accessed in word size (16 bits). Table 17.6 HCAN Mailbox Registers Channel Address (Bytes) Register Name Abbreviation R/W Access Size (Bits) 0 H'D020 Transmit wait register 1_0 TXPR1_0 R/W 16 H'D022 Transmit wait register 0_0 TXPR0_0 R/W H'D028 Transmit wait cancel register 1_0 TXCR1_0 R/W H'D02A Transmit wait cancel register 0_0 TXCR0_0 R/W H'D030 Transmit acknowledge register 1_0 TXACK1_0 R/W H'D032 Transmit acknowledge register 0_0 TXACK0_0 R/W H'D024 H'D026 16 H'D02C H'D02E 16 H'D034 H'D036 H'D038 Abort acknowledge register 1_0 ABACK1_0 R/W H'D03A Abort acknowledge register 0_0 ABACK0_0 R/W H'D040 Received complete register 1_0 RXPR1_0 R/W H'D042 Received complete register 0_0 RXPR0_0 R/W H'D048 Remote request register 1_0 RFPR1_0 R/W H'D04A Remote request register 0_0 RFPR0_0 R/W H'D050 Mailbox interrupt mask register 1_0 MBIMR1_0 R/W H'D052 Mailbox interrupt mask register 0_0 MBIMR0_0 R/W H'D058 Unread message status register 1_0 UMSR1_0 R/W H'D05A Unread message status register 0_0 UMSR0_0 R/W 16 H'D03C H'D03E 16 H'D044 H'D046 16 H'D04C H'D04E 16 H'D054 H'D056 16 H'D05C H'D05E Rev. 5.00 Feb. 24, 2010 Page 451 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) Channel Address (Bytes) Register Name Abbreviation R/W Access Size (Bits) 1 H'D820 Transmit wait register 1_1 TXPR1_1 R/W 16 H'D822 Transmit wait register 0_1 TXPR0_1 R/W H'D828 Transmit wait cancel register 1_1 TXCR1_1 R/W H'D82A Transmit wait cancel register 0_1 TXCR0_1 R/W H'D830 Transmit acknowledge register 1_1 TXACK1_1 R/W H'D832 Transmit acknowledge register 0_1 TXACK0_1 R/W H'D838 Abort acknowledge register 1_1 ABACK1_1 R/W H'D83A Abort acknowledge register 0_1 ABACK0_1 R/W H'D840 Receive complete register 1_1 RXPR1_1 R/W H'D842 Receive complete register 0_1 RXPR0_1 R/W H'D848 Remote request register 1_1 RFPR1_1 R/W H'D84A Remote request register 0_1 RFPR0_1 R/W H'D850 Mailbox interrupt mask register 1_1 MBIMR1_1 R/W H'D852 Mailbox interrupt mask register 0_1 MBIMR0_1 R/W H'D858 Unread message status register 1_1 UMSR1_1 R/W H'D85A Unread message status register 0_1 UMSR0_1 R/W H'D824 H'D826 16 H'D82C H'D82E 16 H'D834 H'D836 16 H'D83C H'D83E 16 H'D844 H'D846 16 H'D84C H'D84E 16 H'D854 H'D856 H'D85C H'D85E Rev. 5.00 Feb. 24, 2010 Page 452 of 950 REJ09B0177-0500 16 17. Controller Area Network-II (HCAN-II) 17.5.1 Transmit Wait Register n (TXPR0n, TXPR1n) (n = 0, 1) TXPR1 and TXPR0 are 16-bit readable/conditionally-writable registers that contain any transmit wait flags for the CAN module. TXPR1 controls mailbox 31 to mailbox 16, and TXPR0 controls mailbox 15 to mailbox 1. The host CPU makes a transmit message stored in a mailbox be in a transmit wait state by writing 1 to the corresponding bit. Writing 0 is ignored, and TXPR cannot be cleared by writing 0 and must be cleared by setting the corresponding TXCR bits. TXPR may be read by the host CPU to determine which, if any, transmissions are waiting. There is a transmit wait bit for all mailboxes except for mailbox 0. Writing 1 to a bit when the mailbox is set for reception is ignored, and TXPR is automatically cleared when an internal arbitration for transmission runs. The HCAN will clear a transmit wait flag after successful transmission of its corresponding message or when a transmission wait cancellation is requested successfully from TXCR. TXPR is not cleared if the message is not transmitted due to the CAN node losing the arbitration processing or due to errors on the CAN bus, and the HCAN automatically tries to transmit it again unless its DART bit (disable automatic re-transmission) is set in the message control of the corresponding mailbox. In such case (DART set) the transmission wait is cleared and notified through mailbox empty interrupt flag (IRR8) and the correspondent bit in the abort acknowledgement register (ABACK). If the status of TXPR changes, the HCAN shall ensure that in the ID priority scheme (MCR[2] = 0), the highest priority message is always presented for transmission in an intelligent way even under circumstances such as bus arbitration losses or errors on the CAN bus. For details, see section 17.7, Operation. When the HCAN changes the state of any TXPR bit to 0, a mailbox empty interrupt (IRR8) may be generated. This indicates that either a successful or an aborted mailbox transmission has just been made. If a message transmission is successful, it is indicated in TXACK, and if a message transmission abortion is successful, it is indicated in ABACK. By checking these registers, the contents of the message data of the corresponding mailbox is modified to prepare for the next transmission. Important: If mailbox 31 is used as a transmit buffer, there is a usage limitation. For details, see section 17.8, Usage Notes. * TXPR1n (n = 0, 1) Bit: 15 14 13 11 12 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 TXPR1[15:0] Initial Value: 0 0 0 0 0 0 0 0 0 R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Bit Bit Name Initial Value 15 to 0 TXPR1[15:0] 0 R/W Description R/W* Request the corresponding mailbox to transmit a CAN frame. Bits 15 to 0 correspond to mailboxes 31 to 16 respectively. When multiple bits are set, the order of the transmissions is determined by MCR2 (CAN-ID or mailbox number). 0: Corresponding mailbox is in transmit message idle state Clearing condition: Completion of message transmission or message transmission wait abortion (automatically cleared) 1: Transmission request made for corresponding mailbox Note: * Only 1 can be written to set a mailbox for transmission. Rev. 5.00 Feb. 24, 2010 Page 453 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) * TXPR0n (n = 0, 1) Bit: 15 14 13 12 11 10 9 0 0 0 0 0 0 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 TXPR0[15:1] Initial Value: 0 0 0 R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Bit Bit Name Initial Value 15 to 1 TXPR0[15:1] 0 R R/W Description R/W* Request the corresponding mailbox to transmit a CAN frame. Bits 15 to 1 correspond to mailboxes 15 to 1 respectively. When multiple bits are set, the order of the transmissions is determined by MCR2 (CAN-ID or mailbox number). 0: Corresponding mailbox is in transmit message idle state Clearing condition: Completion of message transmission or message transmission wait abortion (automatically cleared) 1: Transmission request made for corresponding mailbox 0 0 R Reserved This bit is always 0 as this is a receive-only mailbox. Writing 1 to this bit is ignored. The read value is not guaranteed. Note: * 17.5.2 Only 1 can be written to set a mailbox for transmission. Transmit Wait Cancel Register n (TXCR1n, TXCR0n) (n = 0, 1) TXCR1 and TXCR0 are 16-bit readable/conditionally-writable registers. TXCR1 controls mailbox 31 to mailbox 16, and TXCR0 controls mailbox 15 to mailbox 1. This register is used by the host CPU to request the transmission wait messages in TXPR to be cancelled. To clear the corresponding bit in TXPR, the host CPU must write 1 to the bit in TXCR. Writing 0 is ignored. When transmission cancellation has succeeded, the CAN controller clears the corresponding TXPR and TXCR bits, and sets the corresponding ABACK bit. However, once a mailbox has started a transmission, it cannot be cancelled by this bit. In such a case, if the transmission finishes in success, the CAN controller clears the corresponding TXPR and TXCR bits, and sets the corresponding TXACK bit, however, if the transmission fails due to a bus arbitration loss or an error on the bus, the CAN controller clears the corresponding TXPR and TXCR bits, and sets the corresponding ABACK bit. If an attempt is made by the host CPU to cancel a mailbox transmission that is not transmit-waiting, it shall have no effect, and will be automatically cleared when an internal arbitration for transmission runs. Important: For details on the method of canceling a transmit wait, see section 17.7, Operation. Important: If mailbox 31 is used as a transmit buffer, there is a usage limitation. For details, see section 17.8, Usage Notes. * TXCR1n (n = 0, 1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 TXCR1[15:0] Initial Value: 0 0 0 0 0 0 0 0 0 R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Rev. 5.00 Feb. 24, 2010 Page 454 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) Bit Bit Name Initial Value 15 to 0 TXCR1[15:0] 0 R/W Description R/W* Request the corresponding mailbox, that is in the queue for transmission, to cancel its transmission wait. Bits 15 to 0 correspond to mailboxes 31 to 16 and TXPR1[15:0] respectively. 0: Corresponding mailbox is in transmit message cancellation idle state Clearing condition: Completion of transmit wait cancellation (automatically cleared) 1: Transmit wait cancellation request made for corresponding mailbox Note: * 1 can be written only to a mailbox that is requested for transmission or set for transmission. * TXCR0n (n = 0, 1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 TXCR0[15:1] Initial Value: 0 0 0 0 0 0 0 0 0 R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Bit Bit Name Initial Value 15 to 1 TXCR0[15:1] 0 R R/W Description R/W* Request the corresponding mailbox, that is in the queue for transmission, to cancel its transmission wait. Bits 15 to 1 correspond to mailboxes 15 to 1 and TXPR0[15:1] respectively. 0: Corresponding mailbox is in transmit message cancellation idle state Clearing condition: Completion of transmit wait cancellation (automatically cleared) 1: Transmit wait cancellation request made for corresponding mailbox 0 0 R Reserved This bit is always 0 as this is a receive-only mailbox. Writing 1 to this bit is ignored. The read value is always 0. Note: 17.5.3 * 1 can be written only to a mailbox that is requested for transmission or set for transmission. Transmit Acknowledge Register n (TXACK1n, TXACK0n) (n = 0, 1) TXACK1 and TXACK0 are 16-bit readable/conditionally-writable registers. These registers notify the host CPU that a mailbox transmission has been successfully made. When a transmission has succeeded, the HCAN sets the corresponding bit in TXACK. The host CPU can clear a TXACK bit by writing 1 to the corresponding bit. Writing 0 is ignored. * TXACK1n (n = 0, 1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXACK1[15:0] Initial Value: 0 R/W: R / 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 Rev. 5.00 Feb. 24, 2010 Page 455 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) Bit Bit Name Initial Value R/W Description 15 to 0 TXACK1 [15:0] 0 R/WC1 Notify that the requested transmission of the corresponding mailbox has been finished successfully. Bits 15 to 0 correspond to mailboxes 31 to 16 respectively. 0: Clearing condition: Writing 1 1: Corresponding mailbox has successfully transmitted message (data or remote frame) Setting condition: Completion of message transmission for corresponding mailbox * TXACK0n (n = 0, 1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXACK0[15:1] Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 Bit Bit Name Initial Value 15 to 1 TXACK0[15: 0 1] R/W Description R/WC1 Notify that the requested transmission of the corresponding mailbox has been finished successfully. Bits 15 to 1 correspond to mailboxes 15 to 1 respectively. 0: Clearing condition: Writing 1 1: Corresponding mailbox has successfully transmitted message (data or remote frame) Setting condition: Completion of message transmission for corresponding mailbox 0 TXACK0[0] 0 R Reserved This bit is always 0 as this is a receive-only mailbox. Writing 1 to this bit is ignored. The read value is always 0. 17.5.4 Abort Acknowledge Register n (ABACK1n, ABACK0n) (n = 0, 1) ABACK1 and ABACK0 are 16-bit readable/conditionally-writable registers. These registers notify the host CPU that a mailbox transmission has been aborted as per its request. When an abort has succeeded, the HCAN sets the corresponding bit in ABACK. The host CPU can clear the ABACK bit by writing 1 to the corresponding bit. Writing 0 is ignored. An ABACK bit is used by the HCAN to acknowledge that a TXPR bit has been cleared by the corresponding TXCR bit. * ABACK1n (n = 0, 1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ABACK1[15:0] Initial Value: R/W: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 Rev. 5.00 Feb. 24, 2010 Page 456 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) Bit Bit Name Initial Value 15 to 0 ABACK1[15: 0 0] R/W Description R/WC1 Notify that the requested transmit wait cancellation of the corresponding mailbox has been finished successfully. Bits 15 to 0 correspond to mailboxes 31 to 16 respectively. 0: Clearing condition: Writing 1 1: Corresponding mailbox has cancelled transmission of message (data or remote frame) Setting condition: Completion of transmit wait cancellation for corresponding mailbox * ABACK0n (n = 0, 1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ABACK0[15:1] Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 Bit Bit Name Initial Value R/W Description 15 to 1 ABACK0 [15:1] 0 R/WC1 Notify that the requested transmit wait cancellation of the corresponding mailbox has been finished successfully. Bits 15 to 1 correspond to mailboxes 15 to 1 respectively. 0: Clearing condition: Writing 1 1: Corresponding mailbox has cancelled transmission of message (data or remote frame) Setting condition: Completion of transmit wait cancellation for corresponding mailbox 0 0 0 R Reserved This bit is always 0 as this is a receive-only mailbox. Writing 1 to this bit is ignored. The read value is always 0. 17.5.5 Receive Complete Register n (RXPR1n, RXPR0n) (n = 0, 1) RXPR1 and RXPR0 are 16-bit readable/conditionally-writable registers. RXPR is a register that contains the data frame receive complete flags associated with receive mailboxes. When a CAN data frame is successfully stored in a receive mailbox, the corresponding bit is set in RXPR. The corresponding bit is cleared by writing 1. Writing 0 is ignored. However, the bit may only be set if the mailbox is set by its MBC (mailbox configuration) to receive data frames. When an RXPR bit is set, IRR1 (data frame receive interrupt flag) is also set if its MBIMR (mailbox interrupt mask register) is not set, and the interrupt signal is generated if IMR1 is not set. These bits are only set by receiving data frames and not by receiving remote frames. If a data frame is overwritten/overrun with a remote frame or vice versa, UMSR, RXPR, and RFPR will be set for the same mailbox. In this case the application needs to check the RTR bit within the mailbox control field to understand the nature of the message on the mailbox. Consequently when UMSR is set, both RXPR and RFPR should be checked and, if necessary, cleared. Rev. 5.00 Feb. 24, 2010 Page 457 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) * RXPR1n (n = 0, 1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXPR1[15:0] Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 Bit Bit Name Initial Value 15 to 0 RXPR1[15:0] 0 R/W Description R/WC1 Set receive mailboxes corresponding to mailboxes 31 to 16 respectively. 0: Clearing condition: Writing 1 1: Corresponding mailbox has received a CAN data frame Setting condition: Completion of data frame reception in corresponding mailbox * RXPR0n (n = 0, 1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXPR0[15:0] Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 Bit Bit Name Initial Value 15 to 0 RXPR0[15:0] 0 R/W Description R/WC1 Set receive mailboxes corresponding to mailboxes 15 to 0 respectively. 0: Clearing condition: Writing 1 1: Corresponding mailbox has received a CAN data frame Setting condition: Completion of data frame reception in corresponding mailbox 17.5.6 Remote Request Register n (RFPR1n, RFPR0n) (n = 0, 1) RFPR1 and RFPR0 are 16-bit readable/conditionally-writable registers. RFPR is a register that contains the remote request flags associated with the receive mailboxes. When a CAN remote frame is successfully stored in a receive mailbox, the corresponding bit is set in RFPR. The corresponding bit is cleared by writing 1. Writing 0 is ignored. There is a bit for all mailboxes. However, the bit is only set if the mailbox is set by its MBC (mailbox configuration) to receive remote frames. When an RFPR bit is set, IRR2 (remote frame request interrupt flag) is also set if its MBIMR (mailbox interrupt mask register) is not set, and the interrupt signal is generated if IMR2 is not set. These bits are only set by receiving remote frames and not by receiving data frames. If a data frame is overwritten/overrun with a remote frame or vice versa, UMSR, RXPR, and RFPR will be set for the same mailbox. In this case the application needs to check the RTR bit within the mailbox control field to understand the nature of the message on the mailbox. Consequently when UMSR is set, both RXPR and RFPR should be checked and, if necessary, cleared. Rev. 5.00 Feb. 24, 2010 Page 458 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) * RFPR1n (n = 0, 1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RFPR1[15:0] Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 Bit Bit Name Initial Value 15 to 0 RFPR1[15:0] 0 R/W Description R/WC1 Remote request wait flags for receive mailboxes 31 to 16. 0: Clearing condition: Writing 1 1: Corresponding mailbox has received a remote frame Setting condition: Completion of remote frame reception in corresponding mailbox * RFPR0n (n = 0, 1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RFPR0[15:0] Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 Bit Bit Name Initial Value 15 to 0 RFPR0[15:0] 0 R/W Description R/WC1 Remote request wait flags for receive mailboxes 15 to 0. 0: Clearing condition: Writing 1 1: Corresponding mailbox has received a remote frame Setting condition: Completion of remote frame reception in corresponding mailbox 17.5.7 Mailbox Interrupt Mask Register n (MBIMR1n, MBIMR0n) (n = 0, 1) MBIMR1 and MBIMR0 are 16-bit readable/writable registers. MBIMR only masks IRR (IRR1: data frame receive interrupt, IRR2: remote frame request interrupt, IRR8: mailbox empty interrupt, and IRR9: message overflow interrupt) related to the mailbox activities. If a mailbox is set for reception, the generation of a receive interrupt (IRR1, IRR2, and IRR9) is masked but the setting of the corresponding bit in RXPR, RFPR, or UMSR is not modified. Similarly when a mailbox is set for transmission, the generation of an interrupt signal and setting of an mailbox empty interrupt due to successful transmission or abortion of transmission (IRR8) are masked, however, clearing the corresponding TXPR/TXCR bit and setting the TXACK bit for successful transmission are not masked, or clearing the corresponding TXPR/TXCR bit and setting the ABACK bit for abortion of the transmission are not masked. A mask is set by writing 1 to the corresponding bit for the mailbox activity to be masked. At a reset all mailbox interrupts are masked. Rev. 5.00 Feb. 24, 2010 Page 459 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) * MBIMR1n (n = 0, 1) Bit: 15 14 13 12 11 10 9 8 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W MBIMR1[15:0] Initial Value: 1 R/W: R/W Bit Bit Name Initial Value 15 to 0 MBIMR1[15: 1 0] R/W Description R/W Enable or disable interrupts requests from individual mailbox 31 to mailbox 16 respectively. 0: Interrupt request from IRR1/IRR2/IRR8/ IRR9 enabled 1: Interrupt request from IRR1/IRR2/IRR8/ IRR9 disabled * MBIMR0n (n = 0, 1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MBIMR0[15:0] Initial Value: 1 R/W: R/W 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value 15 to 0 MBIMR0[15: 1 0] R/W Description R/W Enable or disable interrupt requests from individual mailbox 15 to mailbox 0 respectively. 0: Interrupt request from IRR1/IRR2/IRR8/ IRR9 enabled 1: Interrupt request from IRR1/IRR2/IRR8/ IRR9 disabled 17.5.8 Unread Message Status Register n (UMSR1n, UMSR0n) (n = 0, 1) UMSR1 and UMSR0 are 16-bit readable/writable registers that record the receive mailboxes whose contents have not been accessed by the host CPU prior to a new message being received. If the host CPU has not cleared the corresponding bit in RXPR/RFPR when a new message for a mailbox is received, the corresponding UMSR bit is set. This bit is cleared by writing 1. Writing 0 is ignored. If a mailbox is set for transmission, the corresponding UMSR bit cannot be set. * UMSR1n (n = 0, 1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UMSR1[15:0] Initial Value: R/W: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ R/ WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 WC1 Rev. 5.00 Feb. 24, 2010 Page 460 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) Bit Bit Name Initial Value 15 to 0 UMSR1[15:0] 0 R/W Description R/WC1 Indicate that an unread message has been overwritten or overrun for mailboxes 31 to 16. 0: Clearing condition: Writing 1 1: Unread message is overwritten by a new message or overrun Setting Condition: When a new message is received before RXPR/RFPR is cleared. * UMSR0n (n = 0, 1) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UMSR0[15:0] Initial Value: R/W: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/ WC1 R/ WC1 R/ WC1 R/ WC1 R/ WC1 R/ WC1 R/ WC1 R/ WC1 R/ WC1 R/ WC1 R/ WC1 R/ WC1 R/ WC1 R/ WC1 R/ WC1 R/ WC1 Bit Bit Name Initial Value 15 to 0 UMSR0[15:0] 0 R/W Description R/WC1 Indicate that an unread message has been overwritten or overrun for mailboxes 15 to 0. 0: Clearing condition: Writing 1 1: Unread message is overwritten by a new message Setting Condition: When a new message is received before RXPR/RFPR is cleared. Rev. 5.00 Feb. 24, 2010 Page 461 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) 17.6 Timer Registers The timer is a new function for the HCAN-II. The timer is 16 bits and supports several clock sources. It is divided by a prescale counter to reduce the clock speed. It also supports two input capture registers (ICR1 and ICR0) and three compare match registers (TCMR2, TCMR1, and TCMR0). The address map is as follows. Note: These registers can only be accessed in word size (16 bits). Table 17.7 HCAN Timer Registers Channel Address (Bytes) Register Name Abbreviation Access Size (Bits) 0 H'D080 Timer counter register 0 TCNTR0 16 H'D082 Timer control register_0 TCR_0 16 H'D084 Timer status register_0 TSR_0 16 H'D086 Timer drift correction register 0 TDCR0 16 H'D088 Local offset register 0 LOSR0 16 H'D08A Input capture register for cycle counter 0 ICR0-cc0 16 H'D08C Input capture register for timer counter 0 ICR0-tm0 16 H'D08E Input capture register 1_0 ICR1_0 16 H'D090 Timer compare match register 0_0 TCMR0_0 16 H'D092 Timer compare match register 1_0 TCMR1_0 16 H'D094 Timer compare match register 2_0 TCMR2_0 16 H'D096 Cycle counter register 0 CCR0 16 H'D098 Cycle maximum register 0 CMAX0 16 H'D09A Timer mode register_0 TMR_0 16 H'D09C Cycle counter double buffer 0 CCR_buf0 16 H'D09E Input capture double buffer 0 ICR0_buf0 16 H'D880 Timer counter register 1 TCNTR1 16 H'D882 Timer control register_1 TCR_1 16 H'D884 Timer status register_1 TSR_1 16 H'D886 Timer drift correction register 1 TDCR1 16 H'D8D8 Local offset register 1 LOSR1 16 H'D88A Input capture register for cycle counter 1 ICR0-cc1 16 H'D88C Input capture register for timer counter 1 ICR0-tm1 16 H'D88E Input capture register 1_1 ICR1_1 16 H'D890 Timer compare match register 0_1 TCMR0_1 16 H'D892 Timer compare match register 1_1 TCMR1_1 16 H'D894 Timer compare match register 2_1 TCMR2_1 16 H'D896 Cycle counter register 1 CCR1 16 H'D898 Cycle maximum register 1 CMAX1 16 H'D89A Timer mode register_1 TMR_1 16 H'D89C Cycle counter double buffer 1 CCR_buf1 16 H'D89E Input capture double buffer 1 ICR0_buf1 16 1 Note: It is recommended that the timer should be disabled (TCR15 = 0) to change the setting of the registers related to the timer. Rev. 5.00 Feb. 24, 2010 Page 462 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) 17.6.1 Timer Counter Register n (TCNTRn) (n = 0, 1) The timer counter register (TCNTR) is a 16-bit readable/writable register that allows the CPU to monitor and modify the value of the free-running timer counter. When the timer matches TCMR0 (timer compare match register 0) and TCR11 is set to 1, TCNTR is set to LOSR (local offset register) and counting starts again. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 TCNTR[15:0] Initial Value: 0 0 0 0 0 0 0 0 0 R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Bit Bit Name 15 to 0 TCNTR[15:0] 0 Note: * 17.6.2 Initial Value R/W Description R/W* Indicate the value of the free-running timer. This register is cleared by the compare match condition. Timer Control Register_n (TCR_n) (n = 0, 1) The timer control register (TCR) is a 16-bit readable/writable register that controls the operation of the timer. This register should be set before each periodical transmission or the deadline monitor register is set and the timer operation starts. Bit: 15 Initial Value: 14 13 12 11 10 9 TCR 15 TCR 14 TCR 13 TCR 12 TCR 11 TCR 10 TCR9 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W: R/W 8 7 6 5 4 3 2 1 0 TCR5 TCR4 TCR3 TCR2 TCR1 TCR0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W TCR7 Bit Bit Name Initial Value R/W Description 15 TCR15 0 R/W Enable Timer When this bit is set, the timer runs. When this bit is cleared, the timer completes the current cycle (notified by timer overrun or a compare match condition on TCMR0) and is cleared to 0. 0: Timer stops running and is cleared at the end of current cycle 1: Timer is running Important: There is a failure on the timer function in the SH7059. This bit must be written to 0 not to activate the timer. 14 TCR14 0 R/W Disable ICR0 Enables or disables the input capture register 0 (ICR0). When this bit is enabled, the timer value is always captured every time a start of frame (SOF) is output to the CAN bus, whether the HCAN is a transmitter or receiver. When this bit is disabled, the value of ICR0 remains latched. 0: ICR0 is disabled and holds the current value Clearing condition:TCR9 = 1 when CAN-ID of receive message is equal to the ID of a mailbox with CCM set 1: ICR0 is enabled and captures the timer value at every SOF Rev. 5.00 Feb. 24, 2010 Page 463 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) Bit Bit Name Initial Value R/W 13 TCR13 0 R/W Description Timestamp Control for Reception Specifies whether the timestamp in the message control of each mailbox is recorded at the start of frame (SOF) or end of frame (EOF) when a message is received. This bit selects the trigger for the input capture register 1 (ICR1) that is used to timestamp for transmit mailboxes. 0: Timestamp is recorded at the SOF of every message received 1: Timestamp is recorded at the EOF of every message received Important: The timestamp recorded at the SOF of every message received is not supported by the SH7059. When a receive timestamp is used, this bit should be set to 1. 12 TCR12 0 R/W Timestamp Control for Transmission Specifies whether the timestamp of each transmit mailbox is recorded at the point that the corresponding TXPR bit is set or the corresponding TXACK bit is set when a transmit request is made. This bit selects the trigger for the input capture register 1 (ICR1) that is used for timestamp of receive mailboxes. The input capture register 1 (ICR1) is used for timestamp, regardless of whether ICR0 is enabled or disabled. 0: Timestamp is recorded at the point that the TXPR bit is set for message transmission 1: Timestamp is recorded at the point that the TXACK bit is set for message transmission 11 TCR11 0 R/W Timer Clear/Set Control by TCMR0 Specifies whether the timer is to be cleared and set to LOSR when TCMR0 matches TCNTR. TCMR0 is also capable of generating an interrupt signal to the host CPU via IRR15. 0: Timer is not cleared by TCMR0 1: Timer is cleared by TCMR0 10 TCR10 0 R/W Timer Clear/Set Control by CCM Specifies whether the timer is to be cleared and set to LOSR by the CAN-ID compare match for receive mailboxes. When a mailbox stores a receive message, the timer counter (TCNTR) is automatically cleared and set to LOSR, if the CCM bit of the corresponding mailbox and this bit are set. CCM is not capable of generating an interrupt signal since this is performed by the message receive interrupt (IRR1) or remote frame request interrupt (IRR2). 0: Timer is not cleared/set by CCM 1: Timer is cleared and set to LOSR by CCM 9 TCR9 0 R/W ICR0 Automatic Disable by CCM Specifies whether ICR0 is to be disabled by the CAN-ID compare match (CCM) for receive mailboxes. When a mailbox stores a receive message, bit 14 of this register (TCR14) is automatically cleared and the value of ICR0 is retained, if the CCM bit of the corresponding mailbox and this bit are set. 0: TCR14 is not cleared by CCM 1: TCR14 is automatically cleared by CCM 8 -- 0 Reserved Writing 0 to this bit is ignored. The read value is not guaranteed. Rev. 5.00 Feb. 24, 2010 Page 464 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) Bit Bit Name Initial Value R/W Description 7 TCR7 0 R/W Drift Correction Control Specifies whether TCNTR is to be incremented by 2 or 0 every time TCNTR reaches the cycle specified by TDCR. If this function is not required, TDCR must be set to H'0000. 0: Timer is incremented by 0 (i.e. retains the same value for one clock cycle) every cycle specified by TDCR. 1: Timer is incremented by 2 every cycle specified by TDCR (see TDCR description). 6 -- 0 Reserved Writing 0 to this bit is ignored. The read value is not guaranteed. 5 TCR5 0 R/W HCAN-II Timer Prescaler 4 TCR4 0 R/W 3 TCR3 0 R/W Divide the source clock (2 x P) before it is used for the timer. The following relationship exists between source clocks and the timer 2 TCR2 0 R/W 1 TCR1 0 R/W 0 TCR0 0 R/W 17.6.3 Timer Status Register_n (TSR_n) (n = 0, 1) 000000: 1 x source clock 000001: 2 x source clock 000010: 4 x source clock 000011: 6 x source clock 000100: 8 x source clock : 111111: 126 x source clock The timer status register (TSR) is a 16-bit read-only register that allows the host CPU to monitor the timer compare match status and the timer overrun status. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TSR4 TSR3 TSR2 TSR1 TSR0 Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R Bit Bit Name Initial Value R/W Description 15 to 5 -- All 0 Reserved Writing 0 to this bit is ignored. The read value is not guaranteed. 4 to 0 TSR[4:0] 0 R These bits are read-only that allow the CPU to monitor the status of the cycle counter, the timer, and the compare match registers. Writing to these bits is ignored. Rev. 5.00 Feb. 24, 2010 Page 465 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) Bit Bit Name Initial Value R/W Description 4 TSR4 0 R Cycle Counter Overflow Flag Indicates that the cycle counter has reached its maximum value and is reset to H'0. Setting CMAX = 0 makes the cycle counter be disabled and TSR4 be always cleared to 0. 0: Cycle counter has not overflow Clearing condition: Writing 1 to IRR10 (cycle counter overflow interrupt) 1: Cycle counter has overflow Setting condition: When the cycle counter value changes from the maximum value (CMAX) to H'0 3 TSR3 0 R Timer Compare Match Flag 2 Indicates that a compare-match condition occurred to the timer compare match register 2 (TCMR2). When the value set in TCMR2 matches the timer value (TCMR2 = TCNTR), this bit is set. This bit is not set if the TCMR2 value is H'0000. Also, this bit is read-only and is cleared when IRR11 (timer compare match interrupt 2) is cleared. 0: Timer compare match has not occurred to TCMR2 Clearing condition: Writing 1 to IRR11 (timer compare match interrupt 2) 1: Timer compare match has occurred to TCMR2 Setting condition: TCMR2 matches the timer value (TCMR2 = TCNTR) 2 TSR2 0 R Timer Compare Match Flag 1 Indicates that a compare-match condition occurred to the timer compare match register 1 (TCMR1). When the value set in TCMR1 matches the timer value (TCMR1 = TCNTR), this bit is set. This bit is not set if the TCMR1 value is H'0000. Also, this bit is read-only and is cleared when IRR15 (timer compare match interrupt 1) is cleared. 0: Timer compare match has not occurred to TCMR1 Clearing condition: Writing 1 to IRR15 (timer compare match interrupt 1) 1: Timer compare match has occurred to TCMR1 Setting condition: TCMR1 matches the timer value (TCMR1 = TCNTR) 1 TSR1 0 R Timer Compare Match Flag 0 Indicates that a compare-match condition occurred to the timer compare match register 0 (TCMR0). When the value set in TCMR0 matches the timer value (TCMR0 = TCNTR), this bit is set. This bit is not set if the TCMR0 value is H'0000. Also, this bit is read-only and is cleared when IRR14 (timer compare match interrupt 0) is cleared. 0: Timer compare match has not occurred to TCMR0 Clearing condition: Writing 1 to IRR14 (timer compare match interrupt 0) 1: Timer compare match has occurred to TCMR0 Setting condition: TCMR0 matches the timer value (TCMR0 = TCNTR) 0 TSR0 0 R Timer Overrun Flag Indicates that the timer has overrun and is reset to H'0000. This bit is set even when TCMR0 is set to H'FFFF and is enabled to clear the timer value. 0: Timer has not overrun Clearing condition: Writing 1 to IRR13 (timer overrun interrupt) 1: Timer has overrun Setting condition: When the timer value changes the value from H'FFFF to H'0000 Rev. 5.00 Feb. 24, 2010 Page 466 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) 17.6.4 Timer Mode Register_n (TMR_n) (n = 0, 1) The timer mode register (TMR) is a 16-bit readable/writable register that specifies the value to be used for the timer functions. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TMR3 TMR2 TMR1 Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W Bit Bit Name Initial Value R/W Description 15 to 4 -- All 0 -- Reserved Writing 0 to this bit is ignored. The read value is not guaranteed. 3 TMR3 0 R/W Timestamp Value Specifies whether the timestamp for transmission and reception contains the timer value (TCNTR) or the value of Cycle_Counter + TCNTR[15:4]. This function is very useful for time triggered transmission. 0: TCNTR[15:0] is used for the timestamp 1: Cycle_Counter + TCNTR[15:4] is used for the timestamp 2 TMR2 0 R/W TCMR2 Control Specifies whether the timer compare match 2 is compared with the timer value (TCNTR) or with Cycle_Counter + TCNTR[15:4]. 0: TCNTR[15:0] is used for a compare match 1: Cycle_Counter + TCNTR[15:4] is used for a compare match 1 TMR1 0 R/W TCMR1 Control Specifies whether the timer compare match 1 is compared with the timer value (TCNTR) or with Cycle_Counter + TCNTR[15:4]. 0: TCNTR[15:0] is used for a compare match 1: Cycle_Counter + TCNTR[15:4] is used for a compare match 0 -- 0 -- Reserved Writing 0 to this bit is ignored. The read value is not guaranteed. 17.6.5 Timer Drift Correction Register n (TDCRn) (n = 0, 1) The timer drift correction register (TDCR) is a 16-bit readable/writable register. The purpose of this register is to adjust the drift of the timer caused by a different clock running at other CAN nodes on the same system. When TCNTR reaches to the cycle specified by this register, the timer value is incremented by 2 or 0 (i.e. retains the same value). This register does not point at a specific time nor a specific cycle. This means, if TCNTR/2 > TDCR, the drift correction will be performed more than twice (unless TCMR0 is used to clear TCNTR before it reaches the second cycle). When TDCR is set to H'0000, the drift correction will not be performed at all. Bit: 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W TDCR[15:0] Initial Value: 0 R/W: R/W Rev. 5.00 Feb. 24, 2010 Page 467 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) Bit Bit Name Initial Value 15 to 0 TDCR[15:0] All 0 R/W Description R/W Timer Drift Correction Register Set the value of the cycle to adjust the drift of the timer. Important: For a proper operation of the timer, the maximum value must be TDCR <= 8000 (hexadecimal). 17.6.6 Local Offset Register n (LOSRn) (n = 0, 1) The local offset register (LOSR) is a 16-bit readable/writable register that sets a local offset value to TCNTR. When TCNTR is cleared by an overflow, timer compare match, or CAN-ID compare match, TCNTR starts running at the value set in this register. Bit: 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W LOSR[15:0] Initial Value: 0 R/W: R/W Bit Bit Name Initial Value 15 to 0 LOSR[15:0] All 0 R/W Description R/W Local Offset Register Indicate the value of the local offset for TCNTR to start with. 17.6.7 Cycle Counter Register n (CCRn) (n = 0, 1) The cycle counter register (CCR) is a 4-bit readable/writable register that stores the number of the basic cycles for time triggered transmission. Its value is incremented by one every time the free-running counter (TCNTR) is cleared to 0 by a compare match condition on TCMR0. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CCR[3:0] Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 15 to 4 -- All 0 R Reserved 3 to 0 CCR[3:0] All 0 R/W Cycle Counter Indicate the number of the current basic cycles of the matrix cycle for timer triggered transmission. Rev. 5.00 Feb. 24, 2010 Page 468 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) 17.6.8 Cycle Counter Double-Buffer Register n (CCR_buf n) (n = 0, 1) The cycle counter double-buffer register (CCR_buf) is a 4-bit readable/writable register that is used when the cycle counter (CCR) and timer counter (TCNTR) are read from or written to simultaneously to refer the same basic cycle constantly. (This register is used as a temporary retain register to prevent the 20-bit counter value from being updated in CPU access.) Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CCR_buf[3:0] Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 15 to 4 -- All 0 R Reserved 3 to 0 CCR_buf [3:0] All 0 R/W Cycle Counter Double-Buffer A temporary retain buffer when accessing the basic cycle of the matrix cycle for timer triggered transmission (CCR) and timer counter (TCNTR) simultaneously. The CCR_buf value indicates the same value as write/read data to/from CCR. The procedure for accessing the cycle counter (CCR) and timer counter (TCNTR) using the cycle counter double-buffer (CCR_buf) is described below. * Read operation Read the timer counter (TCNTR). (The value of the cycle counter (CCR) is written to the cycle counter double-buffer (CCR_buf) simultaneously.) Then read the cycle counter double-buffer (CCR_buf). Peripheral data bus Peripheral data bus Step 1 Step 2 CCR- buf CCR- buf CCR TCNT R CCR TCNT R * Write operation Write data to the cycle counter double-buffer (CCR_buf). Then write data to the timer counter (TCNTR). (The value of the cycle counter double-buffer (CCR_buf) is written to the cycle counter (CCR) simultaneously.) Peripheral data bus Peripheral data bus Step 1 Step 2 CCR- buf CCR CCR- buf TCNT R CCR TCNT R Rev. 5.00 Feb. 24, 2010 Page 469 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) 17.6.9 Cycle Maximum Register n (CMAXn) (n = 0, 1) The cycle maximum register (CMAX) is a 4-bit readable/writable register that stores the maximum value for the cycle counter (CCR) for timer triggered transmission to set the number of basic cycles in the matrix system. When the cycle counter reaches the maximum value (CCR = CMAX), the cycle counter is cleared to 0 and an interrupt is generated on IRR10. Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CMAX[3:0] Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 15 to 4 -- All 0 R Reserved 3 to 0 CMAX[3:0] All 0 R/W Cycle Maximum Value Store the maximum value of CCR. The initial value of CMAX is 0 making the cycle counter be disabled. During the time trigger setting, the requested value must be programmed. 17.6.10 Input Capture Registers n (ICR0_cc n, ICR0_buf, ICR0_tm n, ICR1 n) (n = 0, 1) The input capture registers are composed of one 4-bit readable/writable register (ICR0_cc) and two 16-bit readable/writable registers (ICR0_tm and ICR1). * ICR0_cc n (n = 0, 1) ICR0_cc can be used for global synchronization, when used with ICR0_tm. The current basic cycle value (Cycle_Counter) is captured at the SOF if ICR0_cc is enabled by bit 14 in TCR, regardless whether the receive message matches the ID set in the receive mailboxes or not. If ICR0_cc is disabled by bit 14 in TCR, it retains the current value. * ICR0_buf n (n = 0, 1): Input Capture Double-Buffer Register A temporary retain buffer that accesses ICR0_cc and ICR0_tm simultaneously. The ICR0_buf value is same as the ICR0_cc value. * ICR0_tm n (n = 0, 1) ICR0_tm can be used for global synchronization, when used with ICR0_cc. The timer value is captured at the SOF if ICR0_tm is enabled by bit 14 in TCR, regardless whether the receive message matches the ID set in the receive mailboxes or not. If ICR0_tm is disabled by bit 14 in TCR, it retains the current value. * Read operation for ICR0_cc, ICR0_buf, and ICR0_tm Read the input capture register (ICR0_tm). (The value of ICR0_cc is written to the input capture double-buffer register (ICR0_buf) simultaneously.) Then read the input capture double-buffer (ICR0_buf). Rev. 5.00 Feb. 24, 2010 Page 470 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) Peripheral data bus Peripheral data bus Step 1 ICR0-buf ICR0-buf ICR0_cc ICR0_tm Step 2 ICR0_cc ICR0_tm * Write operation for ICR0_cc, ICR0_buf, and ICR0_tm Write data to the input capture double-buffer (ICR0_buf). Then write data to the input capture register (ICR0_tm). (The value of the input capture double-buffer (ICR0_buf) is written to ICR0_cc simultaneously.) Peripheral data bus Peripheral data bus Step 1 ICR0-buf ICR0-buf ICR0_cc ICR0_tm Step 2 ICR0_cc ICR0_tm * ICR1 n (n = 0, 1) ICR1 records the timestamp for messages to be transmitted and received. Bit 13 (for reception) and bit 12 (for transmission) in TCR control at which point the timestamp should be recorded. The difference to ICR0 is that ICR1 cannot be disabled so that the timestamps recorded on messages are always correct. * ICR0_cc/ICR0_buf Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ICR0_cc[3:0]/ ICR0_buf[3:0] Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R R R R R R R R R R R R Bit Bit Name Initial Value R/W 15 to 4 -- All 0 R 0 0 0 0 R/W* R/W* R/W* R/W* Description Reserved The write value should be 0. The read value is not guaranteed. 3 2 1 0 Note: * ICR0_cc [3:0]/ ICR0_buf [3:0] 0 R/W* 0 R/W* 0 R/W* 0 R/W* This register samples the value of the cycle counter register (CCR) at every SOF on the CAN bus when enabled by TCR[14]. This register can be written to, however, the written value is ignored. Rev. 5.00 Feb. 24, 2010 Page 471 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) * ICR0_tm/ICR1 Bit: 15 14 13 12 11 10 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 ICR0_tm[15:0], ICR1[15:0] Initial Value: 0 0 0 0 0 R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Bit Bit Name 15 to 0 ICR0_tm[15: All 0 0] Note: * Initial Value R/W Description R/W* This register samples the value of the timer (TCNTR) at every SOF on the CAN bus when enabled by TCR[14]. This register can be written to, however, the written value is ignored. Bit Bit Name Initial Value R/W Description 15 to 0 ICR1[15:0] All 0 R/W* This register samples the value of the timer (TCNTR) at the condition specified by bit 13 (for reception) and bit 12 (for transmission) in TCR. Note: * This register can be written to, however, the written value is ignored. 17.6.11 Timer Compare Match Registers n (TCMR0n, TCMR1n, TCMR2n) (n = 0, 1) * TCMR0, TCMR1, and TCMR Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TCMR0[15:0], TCMR1[15:0], TCMR2[15:0] Initial Value: 0 R/W: R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W 15 to 0 TCMR0[15:0] , All 0 TCMR1[15:0], TCMR2[15:0] R/W Description The timer compare match registers (TCMR0, TCMR1, and TCMR2) are 16bit readable/writable registers that generate interrupt signals, clear/set the timer value (only supported by TCMR0), or clear the transmit messages in the queue (only supported by TCMR2). (These registers offer exactly the same function except for the clear of the timer and the clear of the transmission.) The value used for the compare can be set independently for each register, using bits 1, 2, and 3 in TMR (timer mode register), to be the timer value (TCNTR[15:0]) or the value of Cycle_Count + TCNTR[15:4]. Interrupts are flagged by bits 15, 14, and 11 in IRR when a compare match occurs, and these bits cannot be prevented from being set in IRR except when the TCMR value is H'0000. The generation of interrupt signals can be masked by bits 15, 14, and 11 in IMR. When a compare match occurs and IRR15 (or IRR14 or IRR11) is set, bits 2, 1, and 3 in TSR (HCAN timer status register) are also set. Clearing the IRR bit also clears the corresponding bit in TSR. The timer value is cleared and LOSR is set when a compare match occurs to TCMR0 if bit 11 in TCR is enabled (timer clear/set function). TCMR1 and TCMR2 do not have this function. The messages in the transmit queue are cleared only when a compare match occurs to TCMR2 (cancellation of the messages in the transmit queue). TCMR1 and TCMR0 do not have this function. Important: TCMR0 and TCMR2 are not supported by this LSI. The setting must be H'0000. Rev. 5.00 Feb. 24, 2010 Page 472 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) 17.7 Operation 17.7.1 Test Mode Settings The HCAN has various test modes. Bits TST[7:0] (bits 15 to 8 in MCR) are used to select the HCAN-II test mode. The initial settings allow the HCAN to operate in normal mode. The following table is examples for test modes. Table 17.8 Test Modes Bit15: TST7 Bit14: TST6 Bit13: TST5 Bit12: TST4 Bit11: TST3 Bit10: TST2 Bit9: TST1 Bit8: TST0 Description 0 0 0 0 0 0 0 0 Normal mode (initial value) 1 0 0 0 1 0 1 0 Listen-only mode (receive-only) 1 0 0 1 0 0 0 0 Self test mode 1 (external) 1 0 0 1 0 1 1 1 Self test mode 2 (internal) 1 1 0 0 0 0 0 0 Error passive mode 1 1 0 1 0 0 0 0 0 Error passive mode 2 Normal Mode: The HCAN operates normally. Listen-Only Mode: The ISO-11898 requires this mode for baud rate detection etc. The error counters are disabled so that TEC/REC does not increment the values, and the Tx output is disabled so that the HCAN does not generate error frames. Self Test Mode 1: The HCAN generates its own acknowledge bit. The Rx and Tx pins must be connected to the CAN bus. Self Test Mode 2: The HCAN generates its own acknowledge bit. The Rx and Tx pins do not need to be connected to the CAN bus or any external devices, as the internal Tx is looped back to be connected to the internal Rx. Important: In self test modes 1 and 2, the transmitted data is not received in the internal mailbox. Error Passive Mode 1: The HCAN can be forced to become an error passive node by writing a value (greater than 127) to the error counter. (MCR1 must be 1 when writing to the error counter). The value written to TEC is used to write to REC, so only the same value can be set to these registers. Also, the HCAN needs to be in halt mode when writing to TEC/REC. Error Passive Mode 2: The HCAN can be forced to become an error passive node by setting TST5. Rev. 5.00 Feb. 24, 2010 Page 473 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) 17.7.2 HCAN Settings * Reset Sequence The following sequence is an example to set the HCAN after a software or hardware reset. After a reset, all the registers are initialized, therefore, the HCAN needs to be set before joining the CAN bus activity. Please read the notes carefully. Reset Sequence Configuration Mode Power-on/software reset*1 Clear MCR[0] Setting of the endian for use in transmission No GSR3 = 0? Yes Clear all mailboxes*2 (MSG-control, data, timestamp, LAFM, Txtrigger) Clear IRR[0] HCAN-II is in normal mode Set TXPR to start transmission or stay idle to receive Clear required IMR bits Set LAFM Normal Mode Mailbox setting (STD-ID, EXT-ID, DLC, RTR, IDE, MBC, MBIMR, ATX, NMC, LAFM, message data) Set bit configuration register (BCR) Notes: 1. 2. 3. Detect 11 recessive bits and join the CAN bus activity Receive*3 Transmit*3 A software reset can be performed at any time by setting MCR [0] = 1. Mailboxes are comprised of RAMs, therefore, initialize all the mailboxes first even if some of them are not used. If TXPR is not set, the HCAN-II starts the message reception. If TXPR is set, the HCAN-II starts transmission of the message and is arbitrated by the CAN bus. If an arbitration loss occurs, reception starts. Figure 17.7 Reset Sequence Rev. 5.00 Feb. 24, 2010 Page 474 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) 17.7.3 Message Transmission Sequence (1) Event Triggered Transmission * Message Transmission Request Figure 17.8 is an example to transmit a CAN frame onto the bus. As described in Register Description, note that IRR8 is set when the TXACK or ABACK bit is set. This means that one of the mailboxes has completed its transmission or transmission abortion and is now ready to be updated for the next transmission, whereas, GSR2 means that there is currently no transmission request made (TXPR = H'0000). HCAN is in normal mode (MBC[x]=0x000 or 0x001, TTT=0) Mailbox[x] is ready to be updated for next transmission Update message data of Mailbox[x] Clear TXACK[x] Write 1 to the TXPR[x] bit at any desired timing TXACK[x] =1? No Reinterrupt monitoring No Reinterrupt monitoring Yes Internal arbitration highest priority? No IRR8 =1? Yes Transmission start End of Frame CAN bus arbitration CAN bus Figure 17.8 Transmission Request Rev. 5.00 Feb. 24, 2010 Page 475 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) * Internal Arbitration for Transmission Figure 17.9 explains how the HCAN manages to schedule transmit-requested messages in the correct order based on the CAN ID. "Internal arbitration" picks up the highest priority message among transmit-requested messages. Frame-1 CAN bus state HCAN scheduler state Bus idle SOF Frame-3 Frame-2 Message Tx=arbitation for Tx=arbitation for frame-1 frame-2 EOF Interm SOF Rx matching Message Tx=arbitation for frame-3 EOF Interm SOF Tx=arbitation for Rx matching frame-4 Scheduler start point TXPR/TXCR/ Error/Arbitation-lost set point 1-1 2-1 2-2 3-1 3-2 3-3 3-4 Interm: Intermission Field SOF: Start Of Frame EOF: End Of Frame Message: Arbitration + control + data + CRC + Ack field Figure 17.9 Internal Arbitration for Transmission The HCAN scheduler, which runs internal arbitration, has 2 states - Tx arbitration state and Rx matching state. The HCAN scheduler is in the Rx matching state if the CAN bus is in the EOF or intermission cycles, or otherwise is in the Tx arbitration state. When a transmit request or transmit abort request is made in the Tx arbitration state, the internal arbitration starts running immediately. When a transmit request or transmit abort request is made in the Rx matching state, the internal arbitration waits until the Rx matching state (i.e. intermission field) is finished, and then starts running as soon as the HCAN scheduler state becomes the Tx arbitration. There are 5 sources that can run internal arbitration, which are: * TXPR is set * TXCR is set (if TXCR is set for the message currently under transmission, the HCAN does not stop the transmission but completes. If the message loses the bus arbitration or causes an error on the bus, the HCAN will cancel the transmit request.) * Error occurs on the CAN bus * Message under transmission loses the arbitration on the CAN bus * Mailbox with the setting MBC = 001 receives a remote frame When these sources occur, the internal arbitration starts running to ensure that the highest priority message is always transmitted first. The followings are examples set in Figure 17.9. 1-1: When a TXPR bit is set while the CAN bus is idle, the internal arbitration starts running immediately and the transmission is started. 2-1, 2-2: During this period (Tx-arbitration for frame-2), when any of the above 5 sources occurs, the internal arbitration starts running and the next frame (Frame-2) to be transmitted is scheduled. 3-1, 3-2: During this period (Rx matching), any internal arbitration is not allowed to run, but scheduling is performed at the SOF of the next frame (Frame-2). If the transmit-requested message has the highest priority, the transmission will be set for the Frame-3. 3-3, 3-4: This is the same case as 2-1, 2-2. Rev. 5.00 Feb. 24, 2010 Page 476 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) 17.7.4 Message Transmission Cancellation Sequence Figure 17.10 shows the sequence for canceling a message transmit request set by TXPR. TXPR transmission cancellation sequence : Processing by hardware : Setting by user Set TXCR[N]*1 Read TXPR (1)*1 Read TXCR (2)*1 Write value of (2) and (NOT (value of (1)) to TXPR*1 Transmission of MB[N] in progress? Yes Transmission of MB[N] completed No Set ABACK[N] Set ABACK[N]*2 End of TXPR transmission cancellation sequence End of TXPR transmission cancellation sequence Notes: 1. This setting must be made when transmission is canceled regardless of whether the mailbox is transmitting the message or no message is being transmitted. 2. For a message being transmitted, canceling operation of this transmission near EOF may also set ABACK in some case, though TXACK is normally set. (Flag invalid) In this case, clear ABACK. Figure 17.10 Transmission Cancellation Sequence Rev. 5.00 Feb. 24, 2010 Page 477 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) 17.7.5 Message Receive Sequence Figure 17.11 shows the message receive sequence. CAN bus End of arbitration field End of frame HCAN Idle Valid CAN-ID received Read IRR1(IRR2)=0 Valid CAN frame received N=N-1 Loop (N=31; N>0; N=N-1) Read RXPR[N] (RFPR[N])=0 Compare ID with mailbox[n] + LAFM[N] (if MBC is set for reception) Incorrect Check MBC/ LAFM/CAN-ID Yes No ID matched? No N=0? Yes Write 1 to RXPR[N] (RFPR[N]) Correct Yes Read mailbox[N] RXPR[N] (RFPR[N]) =1? Store mailbox-number[N] and go back to idle state No Yes Yes: OverWrite NMC[N] =1? No: OverRun * Store message by overwriting * Set UMSR * Set IRR9 (if MBIMR[N]=0) * Generate interrupt signal (if IMR9=0) Interrupt signal * Reject message * Set UMSR * Set IRR9 (if MBIMR[N]=0) * Generate interrupt signal (if IMR9=0) Interrupt signal * Store message * Set RXPR[N] (RFPR[N]) * Set IRR1(IRR2) (if MBIMR[N]=0) * Generate interrupt signal (if IMR1(IMR2)=0) Read RXPR[N] (RFPR[N])=1 Yes IRR1(IRR2) =1? No Reinterrupt monitoring Read IRR Interrupt signal CPU receive interrupt Figure 17.11 Message Receive Sequence When the HCAN recognizes the end of the arbitration field during receiving of a message, it starts comparing the received ID to the IDs set in the mailboxes, starting from mailbox 31 down to mailbox 0. It first checks the MBC if it is configured as a receive box, and reads LAFM, and reads the CAN-ID of mailbox 31 to finally compare them to the received ID. If it does not match, the same check takes place at mailbox 30 (if configured as a receive box). Once the HCAN finds a matching ID, it stores the number of mailbox n into an internal buffer, stops the search, and goes back to the idle state, waiting for the end of frame (EOF) to come. When an EOF is notified by the CAN interface logic, the HCAN reads the MBC, LAFM, and CAN-ID of mailbox n to confirm the matching condition again (i.e., there has been no modification to the configuration of mailbox n). This re-confirmation guarantees the data consistency even when a mailbox is reconfigured during receiving a message. If it still matches, then the message is written to or abandoned, depending on the setting of the NMC bit. If it is written to the corresponding mailbox, including the CAN-ID, i.e., there is a possibility that the CAN-ID is overwritten by a different CAN-ID of the received message due to the LAFM used. This also implies that, if the ID of a received message matches the ID + LAFM of 2 or more mailboxes, the higher numbered mailbox will always store the relevant messages and the lower numbered mailbox will never receive messages. Therefore, the settings of the IDs and LAFMs need to be carefully made. Rev. 5.00 Feb. 24, 2010 Page 478 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) 17.7.6 Reconfiguration of Mailboxes When reconfiguration of mailboxes is required, the following procedures should be taken. Change ID of Transmit Box or Change Transmit Box to Receive Box: Confirm that the corresponding TXPR is not set. The ID or corresponding MBC bit can be changed at any time. When both need to be changed, change the ID first and then change the corresponding MBC bit. Change ID of Receive Box or Change Receive Box to Transmit Box: Method-1: Using Halt Mode The advantage of this method is that the HCAN will not lose a message even if the message is on the CAN bus and the HCAN is a receiver. The HCAN-II will be in halt mode after completing the reception. The disadvantage is that it might take long if the HCAN is receiving a message (as the transition to halt mode is delayed until the end of the reception), and also the HCAN will not be able to receive/transmit messages during halt mode. Method-2: Without Using Halt Mode The advantage of this method is that the reconfiguration is done immediately, and the software overhead will be less as there is no interrupt. RXPR needs to be read before and after the reconfiguration. This is because to check if a message is received or not during this period. Note that MBIMR does not prevent the IRR1 from being set but simply prevents the interrupt signal from being generated. If a message is received, it is unknown if the received message is for the previous ID or for the new ID. Therefore, if a message is received during this period, it is better to abandon this message, and this is the disadvantage of this method. Rev. 5.00 Feb. 24, 2010 Page 479 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) Reconfiguration of Mailboxes Method-1 (Using Halt Mode) Method-2 (Without Using Halt Mode) HCAN is in normal mode HCAN is in normal mode Set MCR[1] (halt mode) Set corresponding MBIMR Is HCAN transmitter, receiver, or bus off? Yes No No Generate interrupt (IRR0) Read IRR0 and GSR4 as 1 HCAN is in halt Yes Read corresponding RXPR(RFPR) bit as 0 Change ID or MBC of mailbox Read corresponding RXPR(RFPR) bit 0 1 Abandon received message Change ID or MBC of mailbox Clear corresponding MBIMR bit Clear MCR1 HCAN is in normal mode HCAN is in normal mode and ready for action : Processing by hardware : Setting by user Figure 17.12 Change ID of Receive Box or Change Receive Box to Transmit Box Rev. 5.00 Feb. 24, 2010 Page 480 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) 17.7.7 List of Registers Table 17.9 List of Registers Symbol Register Name Description MCR Master control register General configurations for HCAN and test mode setting GSR General status register Status register for HCAN HCAN_BCR0/1 Bit configuration register Timing configurations for baud rate setting IRR Interrupt register Interrupt request status IMR Interrupt mask register Mask for interrupt request TXPR0/1 Transmission wait register Transmission request TXCR0/1 Transmission wait cancel register Abort transmission request TXACK0/1 Transmission acknowledge register Transmission successful flag ABACK0/1 Abort acknowledge register Transmission abort flag RXPR0/1 Receive complete register Data frame receive flag RFPR0/1 Remote request register Remote frame receive flag MBIMR0/1 Mailbox interrupt mask register Mask for mailbox related interrupt UMSR0/1 Unread message status register Overwrite message flag TCNTR Timer counter register Current timer value TCR Timer control register General timer setting TSR Timer status register Status flag for timer TMR Timer mode register Value to be used for timestamp and TCMR TDCR Timer drift correction register Timer adjustment for synchronization with network LOSR Local offset register Offset for timer CCR Cycle counter register Current cycle counter value for time triggered transmission CMAX Cycle maximum register Number of basic cycles ICR0/1 Input capture register Input capture value TCMR0-2 Timer compare match register Compare value for timer MB Mailbox Mailbox setting Rev. 5.00 Feb. 24, 2010 Page 481 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) 17.7.8 Interrupt Sources Table 17.10 lists the HCAN-II interrupt sources. These sources can be masked using the mailbox interrupt mask register (MBIMR) and interrupt mask register (IMR). For details on the interrupt vector of each interrupt source, see section 7, Interrupt Controller (INTC) . Table 17.10 Interrupt Sources Interrupt Vector DMAC Activation HCAN0 HCAN1 Description ERS0 ERS1 Error passive interrupt (TEC 128 or REC 128) Interrupt Flag (IRR Bit) HCAN0 HCAN1 IRR5 Not Not possible possible Bus off interrupt (TEC 256)/bus off recovery (receives IRR6 11 recessive bits 128 times) OVR0 OVR1 Error warning interrupt (TEC 96) IRR3 Error warning interrupt (REC 96) IRR4 Reset processing interrupt by power-on reset IRR0 Overload frame transmission IRR7 Unread message overwrite/overrun IRR9 Cycle counter overflow IRR10 TCMR2 compare match IRR11 Detection of CAN bus operation in HCAN-II sleep mode IRR12 RM0 SLE0 RM1 SLE1 Timer overrun IRR13 TCMR0 compare match IRR14 TCMR1 compare match IRR15 Data frame reception IRR1 Remote frame reception IRR2 Mailbox empty IRR8 Rev. 5.00 Feb. 24, 2010 Page 482 of 950 REJ09B0177-0500 Possible Not possible 17. Controller Area Network-II (HCAN-II) 17.7.9 DMAC Interface The HCAN-II can activate the DMAC when a message is received at mailbox 0 in channel 0. When an interrupt occurs by mailbox 0 and the DMAC transfer ends after settings of the DMAC activation has been made, the RXPR0 and RFPR0 flags are cleared automatically. An interrupt request due to a receive interrupt from the HCAN-II cannot be sent to the CPU in this case. Figure 17.13 shows a DMAC transfer flowchart. For details on the settings of the DMAC activation, see section 10, Direct Memory Access Controller (DMAC). : Processing by hardware Initial setting of DMAC Set activation source Set source and destination addresses Set number of transmissions and interrupts : Setting by user Receive a message at mailbox 0 in channel 0 Activate DMAC DMAC transfer ended? No Yes Set DMAC transfer end bit Clear RXPR and RFPR Enable DMAC interrupt No Yes Interrupt to CPU Clear DMAC interrupt flag End Figure 17.13 DMAC Transfer Flowchart Rev. 5.00 Feb. 24, 2010 Page 483 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) 17.7.10 HCAN-II Port Settings The HCAN-II port settings must be made in configuration mode or before entering the mode. For details on port settings, see section 22, Pin Function Controller(PFC). This LSI has the HCAN-II with two channels and there are two methods of using the HCAN-II. * 32-buffer HCAN-II with two channels * 64-buffer HCAN-II with one channel* Note: * If you set up the HCAN-II interface as a single channel with 64 buffers, be sure to read section 17.8, Usage Notes. Following figures show examples of the 32-buffer HCAN-II with two channels and 64-buffer HCAN-II with one channel. HTxD0 HCAN0 (32 buffers) HRxD0 HTxD1 HCAN1 (32 buffers) HRxD1 PB10 PB11 PL10 PL11 Figure 17.14 32-Buffer HCAN-II with Two Channels HTxD0 HCAN0 (32 buffers) HCAN1 (32 buffers) HRxD0 HTxD1 PL10 HRxD1 PL11 Figure 17.15 64-Buffer HCAN-II with One Channel 64 buffer HCAN-II with one channel is carried out, following should be taken notice. 1. When message is transmitted to the CAN bus without connecting to other node, ACK error will not be occurred. For example, when message is transmitted from HCAN0 in above diagram, HCAN1 transmits ACK in ACK field. HCAN1 which already receive the message on CAN bus transmits ACK in ACK field according to the CAN protocol and HCAN0 receives the ACK. Rev. 5.00 Feb. 24, 2010 Page 484 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) For a countermeasure, please set the channel that will not transmit the message to reset state (MCR0=1). 2. Internal arbitration which determines transmittion order is independently carried out by HCAN0 and HCAN1, respectively. HCAN-II has 31-transmission buffers per channel. However, internal arbitration can not be carry out in the range of the 62-transmission buffers. 3. Please do not the same transmission message ID to HCAN0 and HCAN1. The same ID message will be transmitted from two channels after arbitration on CAN bus. 17.7.11 CAN Bus Interface A bus transceiver is required to connect this LSI to a CAN bus. The PCA82C250 from NXP Semiconductors is recommended. If any other product is used, confirm that it is equivalent to the PCA82C250. Figure 17.16 shows an example of a connection. 124 This LSI Vcc PCA82C250 RS Vcc HRxD1 RxD CANH HTxD1 TxD CANL NC Vref CAN bus GND Note: NC: No Connection 124 Figure 17.16 Using the PCA82C250 in a High-Speed Interface 17.8 Usage Notes 17.8.1 TXPR Setting during Reception When the HCAN-II is used with the baud rate set to 1 Mbps and the transmission setting is made during message reception, there are following limitations on the number of transmit mailboxes (MB) and the number of accesses to mailboxes. Note that there is no limitation when 500 kbps of baud rate is used. Important: Limitations on setting TXPR during reception There are limitations on the number of mailboxes set by TXPR and the number of accesses to mailboxes. Rev. 5.00 Feb. 24, 2010 Page 485 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) Table 17.11 Limitations on Setting TXPR during Reception P Baud Rate Number of Transmit MB to be Set Simultaneously Upper-Limit Number of Accesses to MB in Words 20 MHz 1.0 Mbps 25 36 30 30 31 29 16 MHz 0.5 Mbps 31 No limitation 1.0 Mbps 10 34 20 24 25 18 30 12 31 11 31 No limitation 0.5 Mbps 17.8.2 Transmit Cancellation Setting immediately after Transmission Setting in Bus Idle When the transmission setting is made and then the transmit cancellation (TXCR) setting is made while the HCAN-II is in the bus idle state, there are following limitations. Important: Limitation on transmit cancellation setting immediately after transmission setting in bus idle CAN bus Bus idele A ID SOF t1 t2 Transmit cancellation prohibited period When the transmission setting (TXPR) is made to a mailbox at the point A shown in the above figure and then transmit cancellation setting (TXCR) is made at the timing between t1 and t2, transmission may be performed to the CAN bus regardless of the fact that a flag is set in the abort acknowledge register. (The transmit acknowledge (TXACK) of the transmitted mailbox is set.) The t1 and t2 timings are as follows after the transmission setting (TXPR) has been made. Table 17.12 Transmit Cancellation Prohibited Period P Baud Rate 20 MHz 1 Mbps MB order ID order 5.05 s 13.55 s 20 MHz 0.5 Mbps MB order 2.55 s 7.65 s ID order 5.45 s 13.55 s Rev. 5.00 Feb. 24, 2010 Page 486 of 950 REJ09B0177-0500 t1 t2 1.90 s 6.30 s 17. Controller Area Network-II (HCAN-II) 17.8.3 Failure on Transmit Cancellation at Mailbox 31 When mailbox 31 is used as a transmit buffer and the transmit cancellation setting is made by TXCR, the following failures may occur. Note that these failures do not occur in the bus-off state. * When the transmit cancellation setting is made by TXCR for mailbox 31 during message transmission (except for mailbox 31), a message may be transmitted and the transmit acknowledge register (TXACK) may be set regardless of the fact that the abort acknowledge register (ABACK) is set. * When the transmit cancellation setting is made by TXCR for mailbox 31 during message transmission of mailbox 31, TXPR may not be cleared even if transmission is completed at mailbox 31 and retransmission may be performed according to the internal arbitration sequence. 17.8.4 TXPR Setting during Transmission When the HCAN-II is used with the baud rate set to 1 Mbps, over the period from the TXPR setting during transmission to the completion of transmission, there are following limitations on the number of transmit mailboxes (MB) and the number of accesses to mailboxes. Note that there is no limitation when 500 kbps of baud rate is used. [Important] Limitations on transmission settings during transmission Rev. 5.00 Feb. 24, 2010 Page 487 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) Important: Limitations on transmission setting during transmission Table 17.13 Limitations on Accesses during Transmission Setting Number of Transmit MB to be Set Simultaneously Upper-Limit Number of Accesses to MB in Words 1 36 2 34 3 34 4 32 5 32 6 30 7 30 8 28 9 28 10 26 11 26 12 24 13 24 14 22 15 22 16 22 17 22 18 20 19 20 20 20 21 18 22 18 23 16 24 16 25 14 26 12 27 12 28 10 29 8 30 8 17.8.5 Time Triggered Transmission Setting/Timer Operation Disabled * The TTE (time trigger enable) bit for setting mailboxes must be written to 0. A failure may occur during event triggered transmission. * The timer must not be operated during event triggered transmission (TCR15 bit = 0). A failure may occur during event triggered transmission. Rev. 5.00 Feb. 24, 2010 Page 488 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) 17.8.6 Mailbox Access during HCAN Sleep Mode Do not access to Mailbox during the HCAN sleep mode. If Mailbox is accessed during HCAN sleep mode, the CPU may stop. The CPU does not stop when the register is accessed during the sleep mode or when Mailbox is accessed except during the HCAN sleep mode. MCR1 = 1 No GSR4 = 1 ? User monitor Yes MCR1 = 0 & MCR5 = 0 Accesses to mailbox are prohibited during this period. CLK stop No Bus operation? Yes IRRl2 = 1 No IMRl2 = 1 ? Yes MCR7 = 0 ? No Yes Sleep mode cancellation Automatic cancellation Manual cancellation MCR5 = 0 No Yes MCR5 = 0 Figure 17.17 HCAN Sleep Mode Flowchart Rev. 5.00 Feb. 24, 2010 Page 489 of 950 REJ09B0177-0500 17. Controller Area Network-II (HCAN-II) 17.8.7 Notes on Port Settings for 64-Buffer HCAN-II with One Channel This LSI has the HCAN-II with two channels. When using the HCAN-II as a 64-buffer with one channel, the following notice should be taken at port settings. HTxD0 HCAN0 (HCAN-II: 32 buffers) HCAN1 (HCAN-II: 32 buffers) HRxD0 HTxD1 PL10 HRxD1 PL11 1. When a message is transmitted to the CAN bus without connecting to other nodes, an ACK error will not occur. For example, when a message is transmitted from HCAN0 in the above figure, HCAN1 transmits ACK in the ACK field. HCAN1 which already received the message on the CAN bus transmits ACK in the ACK field according to the CAN protocol and HCAN0 receives the ACK. For a countermeasure, please set the channel that will not transmit the message to the reset state (MCR0 = 1). Accordingly, a channel that will not transmit the message does not transmit ACK. 2. Internal arbitration which determines the transmission order is independently carried out by HCAN0 and HCAN1, respectively. The HCAN-II has 31 transmission buffers per channel. However, internal arbitration cannot be carried out in the range of the 62 transmission buffers. 3. Please do not set the same transmit message ID to HCAN0 and HCAN1. Otherwise, the same message will be transmitted from the two channels after arbitration on the CAN bus. Rev. 5.00 Feb. 24, 2010 Page 490 of 950 REJ09B0177-0500 18. A/D Converter Section 18 A/D Converter 18.1 Overview This LSI includes a 10-bit successive-approximation A/D converter, with software selection of up to 32 analog input channels. The A/D converter is composed of three independent modules, A/D0, A/D1, and A/D2. A/D0 and A/D1 each comprise three groups, while A/D2 comprises two groups. Module Analog Groups Channels A/D0 Analog group 0 AN0-AN3 Analog group 1 AN4-AN7 Analog group 2 AN8-AN11 Analog group 3 AN12-AN15 Analog group 4 AN16-AN19 Analog group 5 AN20-AN23 Analog group 6 AN24-AN27 Analog group 7 AN28-AN31 A/D1 A/D2 18.1.1 Features The features of the A/D converter are summarized below. * 10-bit resolution 32 input channels (A/D0: 12 channels, A/D1: 12 channels, A/D2: 8 channels) * High-speed conversion Conversion time: minimum 13.3 s per channel (when fop = 20 MHz) * Two conversion modes Single mode: A/D conversion on one channel Scan mode: cotinuous scan mode, single-cycle scan mode (AN0-AN3, AN4-AN7, AN8-AN11, AN12-AN15, AN16-AN19, AN20-AN23, AN24-AN27, AN28-AN31) Continuous conversion on 1 to 12 channels (A/D0) Continuous conversion on 1 to 12 channels (A/D1) Continuous conversion on 1 to 8 channels (A/D2) * Thirty-two 10-bit A/D data registers A/D conversion results are transferred for storage into data registers corresponding to the channels. * Three sample-and-hold circuits A sample-and-hold circuit is built into each A/D converter module (AD/0, AD/1, and AD/2), simplifying the configuration of external analog input circuitry. * A/D conversion interrupts and DMA function supported An A/D conversion interrupt request (ADI) can be sent to the CPU at the end of A/D conversion (ADI0: A/D0 interrupt request; ADI1: A/D1 interrupt request; ADI2: A/D2 interrupt request). Also, the DMAC can be activated by an ADI interrupt request. Rev. 5.00 Feb. 24, 2010 Page 491 of 950 REJ09B0177-0500 18. A/D Converter * Two kinds of conversion activation Software or external trigger (ADTER0, ATU-II (ITVRR2A)) can be selected (A/D0) Software or external trigger (ADTGR0, ATU-II (ITVRR2B)) can be selected (A/D1) Software or external trigger (ADTGR1, ATU-II (ITVRR1)) can be selected (A/D2) * ADEND output Conversion timing can be monitored with the ADEND output pin when using channel 31 in scan mode. 18.1.2 Block Diagram Figure 18.1 shows a block diagram of the A/D converter. Rev. 5.00 Feb. 24, 2010 Page 492 of 950 REJ09B0177-0500 18. A/D Converter Analog multiplexer AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 Sample-andhold circuit + ADCR0 ADDR0-ADDR11 ADTRGR0 10-bit D/A AVss ADCSR0 AVcc AVref Successiveapproximation register Module data bus Bus interface A/D0 Internal data bus A/D conversion control circuit - Comparator ADI0 interrupt signal ATU0 ADTRG0 Analog multiplexer AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 Sample-andhold circuit + - Comparator ADTRGR1 ADDR12-ADDR23 ADCR1 10-bit D/A ADCSR1 Successiveapproximation register Module data bus Bus interface A/D1 Internal data bus A/D conversion control circuit ADI1 interrupt signal ATU0 ADTRGR2 ADCR2 ADDR24- ADDR31 ADCSR2 10-bit D/A Successiveapproximation register Module data bus Bus interface A/D2 Internal data bus AN26 AN27 AN28 AN29 AN30 AN31 Analog multiplexer ADEND AN24 AN25 Sample-andhold circuit + - Comparator A/D conversion control circuit ATU0 ADI2 interrupt signal ADTRG1 Legend: ADCR0, ADCR1, ADCR2: A/D control registers 0 to 2 ADCSR0, ADCSR1, ADCSR2: A/D control/status registers 0 to 2 ADDR0 to ADDR31: A/D data registers 0 to 31 ADTRGR0, ADTRGR1, ADTRGR2: A/D trigger registers 0 to 2 Figure 18.1 A/D Converter Block Diagram Rev. 5.00 Feb. 24, 2010 Page 493 of 950 REJ09B0177-0500 18. A/D Converter 18.1.3 Pin Configuration Table 18.1 summarizes the A/D converter's input pins. There are 32 analog input pins, AN0 to AN31. The 12 pins AN0 to AN11 are A/D0 analog inputs, divided into three groups: AN0 to AN3 (group 0), AN4 to AN7 (group 1), and AN8 to AN11 (group 2). The 12 pins AN12 to AN23 are A/D1 analog inputs, divided into three groups: AN12 to AN15 (group 3), AN16 to AN19 (group 4), and AN20 to AN23 (group 5). The 8 pins AN24 to AN31 are A/D2 analog inputs, divided into two groups: AN24 to AN27 (group 6), and AN28 to AN31 (group 7). The ADTRG0 and ADTRG1 pins are used to provide A/D conversion start timing from off-chip. When the low level of a pulse is applied to one of these pins, A/D0, A/D1, or A/D2 starts conversion. The ADEND pin is an output used to monitor conversion timing when channel 31 is used in scan mode. The AVCC and AVSS pins are power supply voltage pins for the analog section in A/D converter modules A/D0 to A/D2. The AVref pin is the A/D converter module A/D0 to A/D2 reference voltage pin. To maintain chip reliability, ensure that AVCC = 5 V 0.5 V and AVSS = VSS during normal operation, and never leave the AVCC and AVSS pins open, even when the A/D converter is not being used. The voltage applied to the analog input pins should be in the range AVSS ANn AVref. Rev. 5.00 Feb. 24, 2010 Page 494 of 950 REJ09B0177-0500 18. A/D Converter Table 18.1 A/D Converter Pins Pin Name Abbreviation I/O Function Analog power supply pin AVCC Input A/D0-A/D2 analog section power supply Analog ground pin AVSS Input A/D0-A/D2 analog section ground and referencevoltage Analog reference power supply pin AVref Input A/D0-A/D2 analog section reference voltage Analog input pin 0 AN0 Input A/D0 analog inputs 0 to 3 (analog group 0) Analog input pin 1 AN1 Input Analog input pin 2 AN2 Input Analog input pin 3 AN3 Input Analog input pin 4 AN4 Input Analog input pin 5 AN5 Input Analog input pin 6 AN6 Input Analog input pin 7 AN7 Input Analog input pin 8 AN8 Input Analog input pin 9 AN9 Input Analog input pin 10 AN10 Input Analog input pin 11 AN11 Input Analog input pin 12 AN12 Input Analog input pin 13 AN13 Input Analog input pin 14 AN14 Input Analog input pin 15 AN15 Input Analog input pin 16 AN16 Input Analog input pin 17 AN17 Input Analog input pin 18 AN18 Input Analog input pin 19 AN19 Input Analog input pin 20 AN20 Input Analog input pin 21 AN21 Input Analog input pin 22 AN22 Input Analog input pin 23 AN23 Input Analog input pin 24 AN24 Input Analog input pin 25 AN25 Input Analog input pin 26 AN26 Input Analog input pin 27 AN27 Input Analog input pin 28 AN28 Input Analog input pin 29 AN29 Input Analog input pin 30 AN30 Input Analog input pin 31 AN31 Input A/D conversion trigger input pin 0 ADTRG0 Input A/D0 and A/D1 A/D conversion trigger input A/D conversion trigger input pin 1 ADTRG1 Input A/D2 A/D conversion trigger input ADEND output pin ADEND Output A/D2 channel 31 conversion timing monitor output A/D0 analog inputs 4 to 7 (analog group 1) A/D0 analog inputs 8 to 11 (analog group 2) A/D1 analog inputs 12 to 15 (analog group 3) A/D1 analog inputs 16 to 19 (analog group 4) A/D1 analog inputs 20 to 23 (analog group 5) A/D2 analog inputs 24 to 27 (analog group 6) A/D2 analog inputs 28 to 31 (analog group 7) Rev. 5.00 Feb. 24, 2010 Page 495 of 950 REJ09B0177-0500 18. A/D Converter 18.1.4 Register Configuration Table 18.2 summarizes the A/D converter's registers. Table 18.2 A/D Converter Registers Name Abbreviation R/W Initial Value Address Access Size*1 A/D data register 0 (H/L) ADDR0 (H/L) R H'0000 H'FFFFF800 8, 16 A/D data register 1 (H/L) ADDR1 (H/L) R H'0000 H'FFFFF802 8, 16 A/D data register 2 (H/L) ADDR2 (H/L) R H'0000 H'FFFFF804 8, 16 A/D data register 3 (H/L) ADDR3 (H/L) R H'0000 H'FFFFF806 8, 16 A/D data register 4 (H/L) ADDR4 (H/L) R H'0000 H'FFFFF808 8, 16 A/D data register 5 (H/L) ADDR5 (H/L) R H'0000 H'FFFFF80A 8, 16 A/D data register 6 (H/L) ADDR6 (H/L) R H'0000 H'FFFFF80C 8, 16 A/D data register 7 (H/L) ADDR7 (H/L) R H'0000 H'FFFFF80E 8, 16 A/D data register 8 (H/L) ADDR8 (H/L) R H'0000 H'FFFFF810 8, 16 A/D data register 9 (H/L) ADDR9 (H/L) R H'0000 H'FFFFF812 8, 16 A/D data register 10 (H/L) ADDR10 (H/L) R H'0000 H'FFFFF814 8, 16 A/D data register 11 (H/L) ADDR11 (H/L) R H'0000 H'FFFFF816 8, 16 A/D data register 12 (H/L) ADDR12 (H/L) R H'0000 H'FFFFF820 8, 16 A/D data register 13 (H/L) ADDR13 (H/L) R H'0000 H'FFFFF822 8, 16 A/D data register 14 (H/L) ADDR14 (H/L) R H'0000 H'FFFFF824 8, 16 A/D data register 15 (H/L) ADDR15 (H/L) R H'0000 H'FFFFF826 8, 16 A/D data register 16 (H/L) ADDR16 (H/L) R H'0000 H'FFFFF828 8, 16 A/D data register 17 (H/L) ADDR17 (H/L) R H'0000 H'FFFFF82A 8, 16 A/D data register 18 (H/L) ADDR18 (H/L) R H'0000 H'FFFFF82C 8, 16 A/D data register 19 (H/L) ADDR19 (H/L) R H'0000 H'FFFFF82E 8, 16 A/D data register 20 (H/L) ADDR20 (H/L) R H'0000 H'FFFFF830 8, 16 A/D data register 21 (H/L) ADDR21 (H/L) R H'0000 H'FFFFF832 8, 16 A/D data register 22 (H/L) ADDR22 (H/L) R H'0000 H'FFFFF834 8, 16 A/D data register 23 (H/L) ADDR23 (H/L) R H'0000 H'FFFFF836 8, 16 A/D data register 24 (H/L) ADDR24 (H/L) R H'0000 H'FFFFF840 8, 16 A/D data register 25 (H/L) ADDR25 (H/L) R H'0000 H'FFFFF842 8, 16 A/D data register 26 (H/L) ADDR26 (H/L) R H'0000 H'FFFFF844 8, 16 A/D data register 27 (H/L) ADDR27 (H/L) R H'0000 H'FFFFF846 8, 16 A/D data register 28 (H/L) ADDR28 (H/L) R H'0000 H'FFFFF848 8, 16 A/D data register 29 (H/L) ADDR29 (H/L) R H'0000 H'FFFFF84A 8, 16 A/D data register 30 (H/L) ADDR30 (H/L) R H'0000 H'FFFFF84C 8, 16 A/D data register 31 (H/L) ADDR31 (H/L) R H'0000 H'FFFFF84E 8, 16 H'00 H'FFFFF818 8, 16 H'0F H'FFFFF819 8, 16 H'FF H'FFFFF76E 8 H'00 H'FFFFF838 8, 16 A/D control/status register 0 ADCSR0 R/(W)* A/D control register 0 ADCR0 R/W A/D trigger register 0 ADTRGR0 R/W A/D control/status register 1 ADCSR1 Rev. 5.00 Feb. 24, 2010 Page 496 of 950 REJ09B0177-0500 R/(W)* 2 2 18. A/D Converter Name Abbreviation R/W Initial Value Address Access Size*1 A/D control register 1 ADCR1 R/W H'0F H'FFFFF839 8, 16 A/D trigger register 1 ADTRGR1 R/W H'FF H'FFFFF72E 8 H'08 H'FFFFF858 8, 16 2 A/D control/status register 2 ADCSR2 R/(W)* A/D control register 2 ADCR2 R/W H'0F H'FFFFF859 8, 16 A/D trigger register 2 ADTRGR2 R/W H'FF H'FFFFF72F 8 Notes: 1. A 16-bit access must be made on a word boundary. 2. Only 0 can be written to bit 7 to clear the flag. 18.2 Register Descriptions 18.2.1 A/D Data Registers 0 to 31 (ADDR0 to ADDR31) A/D data registers 0 to 31 (ADDR0 to ADDR31) are 16-bit read-only registers that store the results of A/D conversion. There are 32 registers, corresponding to analog inputs 0 to 31 (AN0 to AN31). The ADDR registers are initialized to H'0000 by a power-on reset, and in hardware standby mode and software standby mode. Bit: 7 6 5 4 3 2 1 0 ADDRnH (upper byte) AD9 AD8 AD7 AD6 AD5 ADR AD3 AD2 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 ADDRnL (lower byte) AD1 AD0 -- -- -- -- -- -- Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Note: n = 0 to 31 The A/D converter converts analog input to a 10-bit digital value. The upper 8 bits of this data are stored in the upper byte of the ADDR corresponding to the selected channel, and the lower 2 bits in the lower byte of that ADDR. Only the most significant 2 bits of the ADDR lower byte data are valid. Table 18.3 shows correspondence between the analog input channels and A/D data registers. Rev. 5.00 Feb. 24, 2010 Page 497 of 950 REJ09B0177-0500 18. A/D Converter Table 18.3 Analog Input Channels and A/D Data Registers Analog Input A/D Data Channel Register Analog Input A/D Data Channel Register Analog Input A/D Data Channel Register Analog Input A/D Data Channel Register AN0 ADDR0 AN8 ADDR8 AN16 ADDR16 AN24 ADDR24 AN1 ADDR1 AN9 ADDR9 AN17 ADDR17 AN25 ADDR25 AN2 ADDR2 AN10 ADDR10 AN18 ADDR18 AN26 ADDR26 AN3 ADDR3 AN11 ADDR11 AN19 ADDR19 AN27 ADDR27 AN4 ADDR4 AN12 ADDR12 AN20 ADDR20 AN28 ADDR28 AN5 ADDR5 AN13 ADDR13 AN21 ADDR21 AN29 ADDR29 AN6 ADDR6 AN14 ADDR14 AN22 ADDR22 AN30 ADDR30 AN7 ADDR7 AN15 ADDR15 AN23 ADDR23 AN31 ADDR31 18.2.2 A/D Control/Status Registers 0 and 1 (ADCSR0, ADCSR1) A/D control/status registers 0 and 1 (ADCSR0, ADCSR1) are 8-bit readable/writable registers whose functions include selection of the A/D conversion mode for A/D0 and A/D1. ADCSR0 and ADCSR1 are initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. Bit: Initial value: R/W: Note: * 7 6 5 4 3 2 1 0 ADF ADIE ADM1 ADM0 CH3 CH2 CH1 CH0 0 0 0 0 0 0 0 0 R/(W)* R/W R/W R/W R/W R/W R/W R/W Only 0 can be written to clear the flag. * Bit 7--A/D End Flag (ADF): Indicates the end of A/D conversion. Bit 7:ADF Description 0 Indicates that A/D0 or A/D1 is performing A/D conversion, or is in the idle state (Initial value) [Clearing conditions] 1 * When ADF is read while set to 1, then 0 is written to ADF * When the DMAC is activated by ADI0 or ADI1 Indicates that A/D0 or A/D1 has finished A/D conversion, and the digital value has been transferred to ADDR [Setting conditions] * Single mode: When A/D conversion ends * Scan mode: When all set A/D conversions end The operation of the A/D converter after ADF is set to 1 differs between single mode and scan mode. In single mode, after the A/D converter transfers the digit value to ADDR, ADF is set to 1 and the A/D converter enters the idle state. In scan mode, ADF is set to 1 after all the set conversions end. For example, in the case of 12channel scanning, ADF is set to 1 immediately after the end of conversion for AN8 to AN11 (group 2) or AN20 to AN23 (group 5). After ADF is set to 1, conversion continues in the case of continuous scanning, and ends in the case of single-cycle scanning. Note that 1 cannot be written to ADF. Rev. 5.00 Feb. 24, 2010 Page 498 of 950 REJ09B0177-0500 18. A/D Converter * Bit 6--A/D Interrupt Enable (ADIE): Enables or disables the A/D interrupt (ADI). To prevent incorrect operation, ensure that the ADST bit in A/D control registers 0 and 1 (ADCR0, ADCR1) is cleared to 0 before switching the operating mode. Bit 6:ADIE Description 0 A/D interrupt (ADI0, ADI1) is disabled 1 A/D interrupt (ADI0, ADI1) is enabled (Initial value) When A/D conversion ends and the ADF bit is set to 1, an A/D0 or A/D1 A/D interrupt (ADI0, ADI1) will be generated If the ADIE bit is 1. ADI0 and ADI1 are cleared by clearing ADF or ADIE to 0. * Bits 5 and 4: A/D Mode 1 and 0 (ADM1, ADM0): These bits select the A/D conversion mode from single mode, 4channel scan mode, 8-channel scan mode, and 12-channel scan mode. To prevent incorrect operation, ensure that the ADST bit in A/D control registers 1 and 0 (ADCR1, ADCR0) is cleared to 0 before switching the operating mode. Bit 5:ADM1 Bit 4:ADM0 Description 0 0 Single mode 1 4-channel scan mode (analog groups 0, 1, 2, 3, 4, 5) 0 8-channel scan mode (analog groups 0, 1, 3, 4) 1 12-channel scan mode (analog groups 0, 1, 2, 3, 4, 5) 1 (Initial value) When ADM1 and ADM0 are set to 00, single mode is set. In single mode, operation ends after A/D conversion has been performed once on the analog channels selected with bits CH3 to CH0 in ADCSR. When ADM1 and ADM0 are set to 01, 4-channel scan mode is set. In scan mode, A/D conversion is performed continuously on a number of channels. The channels on which A/D conversion is to be performed in scan mode are set with bits CH3 to CH0 in ADCSR1 and ADCSR0. In 4-channel scan mode, conversion is performed continuously on the channels in one of analog groups 0 (AN0 to AN3), 1 (AN4 to AN7), 2 (AN8 to AN11), 3 (AN12 to AN15, 4 (AN16 to AN19), or 5 (AN20 to AN23). When the ADCS bit is cleared to 0, selecting scanning of all channels within the group (AN0 to AN3, AN4 to AN7, AN8 to AN11, or AN12 to AN15, AN16 to AN19, AN20 to AN23), conversion is performed continuously, once only for each channel within the group, and operation stops on completion of conversion for the last (highest-numbered) channel. When ADM1 and ADM0 are set to 10, 8-channel scan mode is set. In 8-channel scan mode, conversion is performed continuously on the 8 channels in analog groups 0 (AN0 to AN3) and 1 (AN4 to AN7) or analog groups 3 (AN12 to AN15) and 4 (AN16 to AN19). When the ADCS bit is cleared to 0, selecting scanning of all channels within the groups (AN0 to AN7 or AN12 to AN19), conversion is performed continuously, once only for each channel within the groups, and operation stops on completion of conversion for the last (highest-numbered) channel. When ADM1 and ADM0 are set to 11, 12-channel scan mode is set. In 12-channel scan mode, conversion is performed continuously on the 12 channels in analog groups 0 (AN0 to AN3), 1 (AN4 to AN7), and 2 (AN8 to AN11) or analog groups 3 (AN12 to AN15), 4 (AN16 to AN19), and 5 (AN20 to AN23). When the ADCS bit is cleared to 0, selecting scanning of all channels within the groups (AN0 to AN11 or AN12 to AN19), conversion is performed continuously, once only for each channel within the groups, and operation stops on completion of conversion for the last (highest-numbered) channel. For details of the operation in single mode and scan mode, see section 18.4, Operation. * Bits 3 to 0--Channel Select 3 to 0 (CH3 to CH0): These bits, together with the ADM1 and ADM0 bits, select the analog input channels. To prevent incorrect operation, ensure that the ADST bit in A/D control registers 1 and 0 (ADCR1, ADCR0) is cleared to 0 before changing the analog input channel selection. Rev. 5.00 Feb. 24, 2010 Page 499 of 950 REJ09B0177-0500 18. A/D Converter Analog Input Channels Single Mode Bit 3: CH3 Bit 2: CH2 Bit 1: CH1 Bit 0: CH0 A/D0 0 0 0 0 1 1 0 1 1 0* 0 1 Note: 4-Channel Scan Mode A/D1 A/D0 A/D1 AN0 (Initial value) AN12(Initial value) AN0 AN12 1 AN1 AN13 AN0, AN1 AN12, AN13 0 AN2 AN14 AN0-AN2 AN12-AN14 1 AN3 AN15 AN0-AN3 AN12-AN15 0 AN4 AN16 AN4 AN16 1 AN5 AN17 AN4, AN5 AN16, AN17 0 AN6 AN18 AN4-AN6 AN16-AN18 1 AN7 AN19 AN4-AN7 AN16-AN19 0 AN8 AN20 AN8 AN20 1 AN9 AN21 AN8, AN9 AN20, AN21 0 AN10 AN22 AN8-AN10 AN20-AN22 1 AN11 AN23 AN8-AN11 AN20-AN23 Should be cleared to 0. * Analog Input Channels Bit 3: Bit 2: Bit 1: Bit 0: CH3 CH2 CH1 CH0 A/D0 0 0 0 1 0 1 1 1 1 0* 0 1 8-Channel Scan Mode 12-Channel Scan Mode A/D1 A/D0 A/D1 0 AN0, AN4 AN12, AN16 AN0, AN4, AN8 ANAN12, AN16, AN20 1 AN0, AN1, AN4, AN5 AN12, AN13, AN16, AN17 AN0, AN1, AN4, AN5, AN8, AN9 AN12, AN13, AN16, AN17, AN20, AN21 0 AN0-AN2, AN4- AN6 AN12-AN14, AN16- AN18 AN0-AN2, AN4-AN6, AN8-AN10 AN12-AN14, AN16-AN18, AN20-AN22 1 AN0-AN7 AN12-AN19 AN0-AN11 AN12-AN23 0 AN0, AN4 AN12, AN16 AN0, AN4, AN8 AN12, AN16, AN20 1 AN0, AN1, AN4, AN5 AN12, AN13, AN16, AN17 AN0, AN1, AN4, AN5, AN8, AN9 AN12, AN13, AN16, AN17, AN20, AN21 0 AN0-AN2, AN4- AN6 AN12-AN14, AN16- AN18 AN0-AN2, AN4-AN6, AN8-AN10 AN12-AN14, AN16-AN18, AN20-AN22 1 AN0-AN7 AN12-AN19 AN0-AN11 AN12-AN23 AN0, AN4, AN8 AN12, AN16, AN20 1 AN0, AN1, AN4, AN5, AN8, AN9 AN12, AN13, AN16, AN17, AN20, AN21 0 AN0-AN2, AN4-AN6, AN8-AN10 AN12-AN14, AN16-AN18, AN20-AN22 1 AN0-AN11 AN12-AN23 0 2 Reserved* 2 Reserved* Notes: 1. Should be cleared to 0. 2. These modes are provided for future expansion, and cannot be used at present. Rev. 5.00 Feb. 24, 2010 Page 500 of 950 REJ09B0177-0500 18. A/D Converter 18.2.3 A/D Control Registers 0 to 2 (ADCR0 to ADCR2) A/D control registers 0 to 2 (ADCR0 to ADCR2) are 8-bit readable/writable registers that control the start of A/D conversion and selects the operating clock for A/D0 to A/D2. ADCR0 to ADCR2 are initialized to H'0F by a power-on reset, and in hardware standby mode and software standby mode. Bits 3 to 0 of ADCR0 to ADCR2 are reserved. These bits cannot be modified. These bits are always read as 1. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 TRGE CKS ADST ADCS -- -- -- -- 0 0 0 0 1 1 1 1 R/W R/W R/W R/W R R R R * Bit 7--Trigger Enable (TRGE): Enables or disables triggering of A/D conversion by external input or the ATU-II. Bit 7:TRGE Description 0 A/D conversion triggering by external input or ATU-II is disabled 1 A/D conversion triggering by external input or ATU-II is enabled (Initial value) For details of external or ATU-II trigger selection, see section 18.2.5, A/D Trigger Registers 0 to 2 (ADTRGR0 to ADTRGR2). When ATU triggering is selected, clear bit 7 of registers ADTRGR0 to ADTRGR2 to 0. When external triggering is selected, upon input of the low level of a pulse to the ADTRG0 or ADTRG1 pin after TRGE has been set to 1, the A/D converter detects the falling edge of a pulse and sets the ADST bit to 1 in ADCR. The same operation is subsequently performed when 1 is written in the ADST bit by software. External triggering of A/D conversion is only enabled when the ADST bit is cleared to 0. When external triggering is used, the low level width of a pulse input to the ADTRG0 or ADTRG1 pin must be at least 1.5 P clock cycles in width. * Bit 6--Clock Select (CKS): Selects the A/D conversion time. A/D conversion is executed in a maximum of 266 states when CKS is 0, and a maximum of 134 states when 1. To prevent incorrect operation, ensure that the ADST bit A/D control registers 0 to 2 (ADCR0 to ADCR2) is cleared to 0 before changing the A/D conversion time. For details, see section 18.4.3, Analog Input Sampling and A/D Conversion Time. Bit 6:CKS Description 0 Conversion time = 266 states (maximum) 1 Conversion time = 134 states (maximum) (Initial value) * Bit 5--A/D Start (ADST): Starts or stops A/D conversion. A/D conversion is started when ADST is set to 1, and stopped when ADST is cleared to 0. Bit 5:ADST Description 0 A/D conversion is stopped 1 A/D conversion is being executed (Initial value) [Clearing conditions] * Single mode: Automatically cleared to 0 when A/D conversion ends * Scan mode: Automatically cleared to 0 on completion of one round of conversion on all set channels (single-cycle scan) Rev. 5.00 Feb. 24, 2010 Page 501 of 950 REJ09B0177-0500 18. A/D Converter Note that the operation of the ADST bit differs between single mode and scan mode. In single mode, ADST is automatically cleared to 0 when A/D conversion ends on one channel. In scan mode (continuous scan), when all conversions have ended for the selected analog inputs, ADST remains set to 1 in order to start A/D conversion again for all the channels. Therefore, in scan mode (continuous scan), the ADST bit must be cleared to 0, stopping A/D conversion, before changing the conversion time or the analog input channel selection. However, in scan mode (single-cycle scan), the ADST bit is automatically cleared to 0, stopping A/D conversion, when one round of conversion ends on all the set channels. Ensure that the ADST bit in ADCR0 to ADCR2 is cleared to 0 before switching the operating mode. Also, make sure that A/D conversion is stopped (ADST is cleared to 0) before changing A/D interrupt enabling (bit ADIE in ADCSR0 to ADCSR2), the A/D conversion time (bit CKS in ADCR0 to ADCR2), the operating mode (bits ADM1 and ADM0 in ADSCR0 to ADCSR2), or the analog input channel selection (bits CH3 to CH0 in ADCSR0 to ADCSR2). The A/D data register contents will not be guaranteed if these changes are made while the A/D converter is operating (ADST is set to 1). * Bit 4--A/D Continuous Scan (ADCS): Selects either single-cycle scan or continuous scan in scan mode. This bit is valid only when scan mode is selected. See section 18.4.2, Scan Mode, for details. Bit 4: ADCS Description 0 Single-cycle scan 1 Continuous scan (Initial value) * Bits 3 to 0--Reserved: These bits are always read as 1. The write value should always be 1. 18.2.4 A/D Control/Status Register 2 (ADCSR2) A/D control/status register 2 (ADCSR2) is an 8-bit readable/writable register whose functions include selection of the A/D conversion mode for A/D2. ADCSR2 is initialized to H'08 by a power-on reset, and in hardware standby mode and software standby mode. Bit: Initial value: R/W: Note: * 7 6 5 4 3 2 1 0 ADF ADIE ADM1 ADM0 -- CH2 CH1 CH0 0 0 0 0 1 0 0 0 R/(W)* R/W R/W R/W R R/W R/W R/W Only 0 can be written to clear the flag. * Bit 7--A/D End Flag (ADF): Indicates the end of A/D conversion. Bit 7:ADF 0 Description Indicates that A/D2 is performing A/D conversion, or is in the idle state (Initial value) [Clearing conditions] 1 * When ADF is read while set to 1, then 0 is written to ADF * When the DMAC is activated by ADI2 Indicates that A/D2 has finished A/D conversion, and the digital value has been transferred to ADDR [Setting conditions] * Single mode: When A/D conversion ends * Scan mode: When all set A/D conversions end Rev. 5.00 Feb. 24, 2010 Page 502 of 950 REJ09B0177-0500 18. A/D Converter The operation of the A/D converter after ADF is set to 1 differs between single mode and scan mode. In single mode, after the A/D converter transfers the digit value to ADDR, ADF is set to 1 and the A/D converter enters the idle state. In scan mode, ADF is set to 1 after all the set conversions end. For example, in the case of 8channel scanning, ADF is set to 1 immediately after the end of conversion for AN28 to AN31 (group 7). After ADF is set to 1, conversion continues in the case of continuous scanning, and ends in the case of single-cycle scanning. Note that 1 cannot be written to ADF. * Bit 6--A/D Interrupt Enable (ADIE): Enables or disables the A/D interrupt (ADI). To prevent incorrect operation, ensure that the ADST bit in A/D control register 2 (ADCR2) is cleared to 0 before switching the operating mode. Bit 6:ADIE Description 0 A/D interrupt (ADI2) is disabled 1 A/D interrupt (ADI2) is enabled (Initial value) When A/D conversion ends and the ADF bit in ADCSR2 is set to 1, an A/D2 A/D interrupt (ADI2) will be generated If the ADIE bit is 1. ADI2 is cleared by clearing ADF or ADIE to 0. * Bits 5 and 4--A/D Mode 1 and 0 (ADM1, ADM0): These bits select the A/D conversion mode from single mode, 4channel scan mode,and 8-channel scan mode. To prevent incorrect operation, ensure that the ADST bit in A/D control register 2 (ADCR2) is cleared to 0 before switching the operating mode. Bit 5:ADM1 Bit 4:ADM0 Description 0 0 Single mode 1 4-channel scan mode (analog groups 6 and 7) 0 8-channel scan mode (analog groups 6 and 7) 1 Reserved 1 (Initial value) When ADM1 and ADM0 are set to 00, single mode is set. In single mode, operation ends after A/D conversion has been performed once on the analog channels selected with bits CH2 to CH0 in ADCSR. When ADM1 and ADM0 are set to 01, 4-channel scan mode is set. In scan mode, A/D conversion is performed continuously on a number of channels. The channels on which A/D conversion is to be performed in scan mode are set with bits CH2 to CH0 in ADCSR2. In 4-channel scan mode, conversion is performed continuously on the channels in one of analog groups 6 (AN24 to AN27) or 7 (AN28 to AN31). When the ADCS bit is cleared to 0, selecting scanning of all channels within the group (AN24 to AN27, AN28 to AN31), conversion is performed continuously, once only for each channel within the group, and operation stops on completion of conversion for the last (highest-numbered) channel. When ADM1 and ADM0 are set to 10, 8-channel scan mode is set. In 8-channel scan mode, conversion is performed continuously on the 8 channels in analog groups 6 (AN24 to AN27) and 7 (AN28 to AN31). When the ADCS bit is cleared to 0, selecting scanning of all channels within the groups (AN24 to AN31), conversion is performed continuously, once only for each channel within the groups, and operation stops on completion of conversion for the last (highest-numbered) channel. For details of the operation in single mode and scan mode, see section 18.4, Operation. * Bit 3--Reserved: This bit is always read as 1. The write value should always be 0. * Bits 2 to 0--Channel Select 2 to 0 (CH2 to CH0): These bits, together with the ADM1 and ADM0 bits, select the analog input channels. To prevent incorrect operation, ensure that the ADST bit in A/D control register 2 (ADCR2) is cleared to 0 before changing the analog input channel selection. Rev. 5.00 Feb. 24, 2010 Page 503 of 950 REJ09B0177-0500 18. A/D Converter Analog Input Channels Bit:CH2 Bit:CH1 Bit:CH0 Single Mode 4-Channel Scan Mode 8-Channel Scan Mode 0 0 0 AN24 (Initial value) AN24 AN24, AN28 1 AN25 AN24, AN25 AN24, AN25, AN28, AN29 0 AN26 AN24-AN26 AN24-AN26, AN28-AN30 1 AN27 AN24-AN27 AN24-AN31 0 AN28 AN28 AN24, AN28 1 AN29 AN28, AN29 AN24, AN25, AN28, AN29 0 AN30 AN28-AN30 AN24-AN26, AN28-AN30 1 AN31 AN28-AN31 AN24-AN31 1 1 0 1 18.2.5 A/D Trigger Registers 0 to 2 (ADTRGR0 to ADTRGR2) The A/D trigger registers (ADTRGR0 to ADTRGR2) are 8-bit readable/writable registers that select the A/D0, A/D1, and A/D2 triggers. Either external pin (ADTRG0, ADTRG1) or ATU-II (ATU-II interval timer A/D conversion request) triggering can be selected. ADTRGR0 to ADTRGR2 are initialized to H'FF by a power-on reset, in hardware standby mode and software standby mode. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 EXTRG -- -- -- -- -- -- -- 1 1 1 1 1 1 1 1 R/W R R R R R R R * Bit 7--Trigger Enable (EXTRG): Selects external pin input (ADTRG0, ADTRG1) or the ATU-II interval timer A/D conversion request. Bit 7:EXTRG Description 0 A/D conversion is triggered by the ATU-II channel 0 interval timer A/D conversion request 1 A/D conversion is triggered by external pin input (ADTRG) (Initial value) In order to select external triggering or ATU-II triggering, the TGRE bit in ADCR0 to ADCR2 must be set to 1. For details, see section 18.2.3, A/D Control Registers 0 to 2 (ADCR0 to ADCR2). * Bits 6 to 0--Reserved: These bits are always read as 1. The write value should always be 1. Rev. 5.00 Feb. 24, 2010 Page 504 of 950 REJ09B0177-0500 18. A/D Converter 18.3 CPU Interface A/D data registers 0 to 31 (ADDR0 to ADDR31) are 16-bit registers, but they are connected to the CPU by an 8-bit data bus. Therefore, the upper and lower bytes must be read separately. To prevent the data being changed between the reads of the upper and lower bytes of an A/D data register, the lower byte is read via a temporary register (TEMP). The upper byte can be read directly. Data is read from an A/D data register as follows. When the upper byte is read, the upper-byte value is transferred directly to the CPU and the lower-byte value is transferred into TEMP. Next, when the lower byte is read, the TEMP contents are transferred to the CPU. When performing byte-size reads on an A/D data register, always read the upper byte before the lower byte. It is possible to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained. If a word-size read is performed on an A/D data register, reading is performed in upper byte, lower byte order automatically. Figure 18.2 shows the data flow for access to an A/D data register. Upper-byte read CPU (H'AA) Bus interface Module data bus TEMP (H'40) ADDRnH (H'AA) ADDRnL (H'40) Lower-byte read CPU (H'40) Bus interface Module data bus TEMP (H'40) ADDRnH (H'AA) ADDRnL (H'40) Figure 18.2 A/D Data Register Access Operation (Reading H'AA40) Rev. 5.00 Feb. 24, 2010 Page 505 of 950 REJ09B0177-0500 18. A/D Converter 18.4 Operation The A/D converter operates by successive approximations with 10-bit resolution. It has two operating modes: single mode and scan mode. There are two kinds of scan mode: continuous and single-cycle. In single mode, conversion is performed once on one specified channel, then ends. In continuous scan mode, A/D conversion continues on one or more specified channels until the ADST bit is cleared to 0. In single-cycle scan mode, A/D conversion ends after being performed once on one or more channels. 18.4.1 Single Mode Single mode, should be selected when only one A/D conversion on one channel is required. Single mode is selected by setting the ADM1 and ADM0 bits in the A/D control/status register (ADSCR) to 00. When the ADST bit in the A/D control register (ADCR) is set to 1, A/D conversion is started in single mode. The ADST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when conversion ends. When conversion ends, the ADF flag in ADCSR is set to 1. If the ADIE bit in ADCSR is also 1, an ADI interrupt is requested. To clear the ADF flag, first read ADF when set to 1, then write 0 to ADF. If the DMAC is activated by the ADI interrupt, ADF is cleared automatically. An example of the operation when analog input channel 1 (AN1) is selected and A/D conversion is performed in single mode is described next. Figure 18.3 shows a timing diagram for this example. 1. Single mode is selected (ADM1 = ADM0 = 0), input channel AN1 is selected (CH3 = CH2 = CH1 = 0, CH0 = 1), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started (ADST = 1). 2. When A/D conversion is completed, the result is transferred to ADDR1. At the same time the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle. 3. Since ADF = 1 and ADIE = 1, an ADI interrupt is requested. 4. The A/D interrupt handling routine is started. 5. The routine reads ADF set to 1, then writes 0 to ADF. 6. The routine reads and processes the conversion result (ADDR1). 7. Execution of the A/D interrupt handling routine ends. After this, if the ADST bit is set to 1, A/D conversion starts again and steps 2 to 7 are repeated. Rev. 5.00 Feb. 24, 2010 Page 506 of 950 REJ09B0177-0500 18. A/D Converter Set* ADIE A/D conver- Set* sion starts Set* ADST Clear* Clear* ADF State of channel 0 (AN0) Idle State of channel 1 (AN1) Idle State of channel 2 (AN2) Idle State of channel 3 (AN3) Idle A/D conversion (1) Idle A/D conversion (2) Idle ADDR0 Read conversion result ADDR1 Read conversion result A/D conversion result (1) A/D conversion result (2) ADDR2 ADDR3 Note: * Vertical arrows ( ) indicate instructions executed by software. Figure 18.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) 18.4.2 Scan Mode Scan mode is useful for monitoring analog inputs in a group of one or more channels. Scan mode is selected for A/D0 or A/D1 by setting the ADM1 and ADM0 bits in A/D control/status register 0 or 1 (ADSCR0 or ADSCR1) to 01 (4-channel scan mode), 10 (8-channel scan mode), or 11 (12-channel scan mode). For A/D2, scan mode is selected by setting the ADM1 and ADM0 bits in A/D control/status register 2 (ADCSR2) to 01 (4-channel scan mode) or 10 (8-channel scan mode). When the ADCS bit is cleared to 0 and the ADST bit is set to 1 in the A/D control register (ADCR), single-cycle scanning is performed. When the ADCS bit is set to 1 and the ADST bit is set to 1, continuous scanning is performed. In scan mode, A/D conversion is performed in low-to-high analog input channel number order (AN0, AN1 ... AN11, AN12, AN13 ... AN23, AN24, AN25 ... AN31). In single-cycle scanning, the ADF bit in ADCSR is set to 1 when conversion has been performed once on all the set channels, and the ADST bit is automatically cleared to 0. Rev. 5.00 Feb. 24, 2010 Page 507 of 950 REJ09B0177-0500 18. A/D Converter In continuous scanning, the ADF bit in ADCSR is set to 1 when conversion ends on all the set channels. To stop A/D conversion, write 0 to the ADST bit. If the ADIE bit in ADCSR is set to 1 when ADF is set to 1, an ADI interrupt (ADI0, ADI1, or ADI2) is requested. To clear the ADF flag, first read ADF when set to 1, then write 0 to ADF. If the DMAC is activated by the ADI interrupt, ADF is cleared to 0 automatically. An example of the operation when analog inputs 0 to 11 (AN0 to AN11) are selected and A/D conversion is performed in single-cycle scan mode is described below. Figure 18.4 shows the operation timing for this example. 1. 12-channel scan mode is selected (ADM1 = 1, ADM0 = 1), single-cycle scan mode is selected (ADCS = 0), analog input channels AN0 to AN11 are selected (CH3 = 0, CH2 = 0, CH1 = 1, CH0 = 1), and A/D conversion is started. 2. When conversion of the first channel (AN0) is completed, the result is transferred to ADDR0. Next, conversion of the second channel (AN1) starts automatically. 3. Conversion proceeds in the same way through the 12th channel (AN11). 4. When conversion is completed for all the selected channels (AN0 to AN11), the ADF flag is set to 1, the ADST bit is cleared to 0 automatically, and A/D conversion stops. If the ADIE bit is 1, an ADI interrupt is requested after A/D conversion ends. An example of the operation when analog inputs 0 to 2 and 4 to 6 (AN0 to AN2 and AN4 to AN6) are selected and A/D conversion is performed in 8-channel scan mode is described below. Figure 18.5 shows the operation timing. 1. 8-channel scan mode is selected (ADM1 = 1, ADM0 = 0) continuous scan mode is selected (ADCS = 1), analog input channels AN0 to AN2 and AN4 to AN6 are selected (CH3 = 0, CH2 = 0, CH1 = 1, CH0 = 0), and A/D conversion is started. 2. When conversion of the first channel (AN0) is completed, the result is transferred to ADDR0. Next, conversion of the second channel (AN1) starts automatically. 3. Conversion proceeds in the same way through the third channel (AN2). 4. Conversion of the fifth channel (AN4) starts automatically. 5. Conversion proceeds in the same way through the seventh channel (AN6) 6. When conversion is completed for all the selected channels (AN0 to AN2 and AN4 to AN6), the ADF flag is set to 1. If the ADIE bit is also 1, an ADI interrupt is requested. 7. Steps 2 to 6 are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops. After this, if the ADST bit is set to 1, A/D conversion starts again from the first channel (AN0). Rev. 5.00 Feb. 24, 2010 Page 508 of 950 REJ09B0177-0500 18. A/D Converter Continuous A/D conversion Set* Clear ADST Clear* ADF State of channel 0 (AN0) State of channel 1 (AN1) Idle Idle A/D conversion (1) Idle A/D conversion (2) State of channel 2 (AN2) Idle State of channel 9 (AN9) Idle State of channel 10 (AN10) Idle State of channel 11 (AN11) Idle Idle Idle A/D conversion (3) Idle A/D conversion (9) Idle A/D conversion (10) Idle A/D conversion (11) ADDR0 A/D conversion result (0) ADDO1 A/D conversion result (1) ADDR2 A/D conversion result (2) ADDR9 A/D conversion result (9) ADDR10 A/D conversion result (10) ADDR11 A/D conversion result (11) Note: * Vertical arrows ( ) indicate instructions executed by software. Figure 18.4 Example of A/D Converter Operation (Scan Mode (Single-Cycle Scan), Channels AN0 to AN11 Selected) Rev. 5.00 Feb. 24, 2010 Page 509 of 950 REJ09B0177-0500 18. A/D Converter Continuous A/D conversion Set*1 Clear*1 ADST Clear*1 ADF State of channel 0 (AN0) State of channel 1 (AN1) Idle Idle A/D conversion (1) Idle Idle A/D conversion (2) State of channel 2 (AN2) Idle State of channel 3 (AN3) Idle State of channel 4 (AN4) Idle State of channel 5 (AN5) Idle State of channel 6 (AN6) Idle State of channel 7 (AN7) Idle ADDR0 ADDR1 ADDR2 Idle A/D conversion (7) Idle A/D conversion (3) Idle A/D conversion (8) Idle A/D conversion (9) Idle A/D conversion (4) A/D conversion (10) Idle A/D conversion (6) A/D conversion result (1) *2 Idle A/D conversion (11) Idle A/D conversion (5) Idle A/D conversion result (7) A/D conversion result (2) A/D conversion result (8) A/D conversion result (3) A/D conversion result (9) ADDR3 ADDR4 A/D conversion result (4) ADDR5 ADDR6 A/D conversion result (10) A/D conversion result (5) A/D conversion result (6) ADDR7 Notes: 1. Vertical arrows ( ) indicate instructions executed by software. 2. Data currently being converted is ignored. Figure 18.5 Example of A/D Converter Operation (Scan Mode (Continuous Scan), Channels AN0 to AN2 and AN4 to AN6 Selected) 18.4.3 Analog Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit in A/D0, A/D1, and A/D2. The A/D converter samples the analog input at time tD (A/D conversion start delay time) after the ADST bit is set to 1, then starts conversion. Figure 18.6 shows the A/D conversion timing. The A/D conversion time (tCONV) includes tD and the analog input sampling time (tSPL). The length of tD is not fixed, since it includes the time required for synchronization of the A/D conversion operation. The total conversion time therefore varies within the ranges shown in table 18.4. Rev. 5.00 Feb. 24, 2010 Page 510 of 950 REJ09B0177-0500 18. A/D Converter In scan mode, the tCONV values given in table 18.4 apply to the first conversion. In the second and subsequent conversions, tCONV is fixed at 256 states when CKS = 0 or 128 states when CKS = 1. Table 18.4 A/D Conversion Time (Single Mode) CKS = 0: fop = 10 to 20 MHz CKS = 1: fop = 10 MHz Item Symbol Min Typ Max Min Typ Max Unit A/D conversion start delay time tD 10 -- 17 6 -- 9 States(CK base) Input sampling time tSPL -- 64 -- -- 32 -- A/D conversion time tCONV 259 -- 266 131 -- 134 A/D conversion time (tCONV) A/D conversion start delay time (tD) Analog input sampling time (tSPL) Write cycle A/D synchronization time (3 states) (up to 14 states) CK Address Internal write signal ADST write timing Analog input sampling signal A/D converter Idle Sample-and-hold A/D conversion ADF End of A/D conversion Figure 18.6 A/D Conversion Timing 18.4.4 External Triggering of A/D Conversion A/D conversion can be externally triggered. To activate the A/D converter with an external trigger, first set the pin functions with the PFC (pin function controller) and the TRGE bit to 1 in the A/D control register (ADCR), and set the EXTRG bit to 1 in the A/D trigger register (ADTRGR). When a low level is input to the ADTRG pin after these settings have been made, the A/D converter detects the falling edge of a pulse and sets the ADST bit to 1. Figure 18.7 shows the timing for external trigger input. The ADST bit is set to 1 two states after the A/D converter samples the falling edge on the ADTRG pin. The timing from setting of the ADST bit until the start of A/D conversion is the same as when 1 is written into the ADST bit by software. Rev. 5.00 Feb. 24, 2010 Page 511 of 950 REJ09B0177-0500 18. A/D Converter pin sampled CK input ADST bit ADST = 1 Figure 18.7 External Trigger Input Timing 18.4.5 A/D Converter Activation by ATU-II The A/D0, A/D1, and A/D2 converter modules can be activated by an A/D conversion request from the ATU-II's channel 0 interval timer. To activate the A/D converter by means of the ATU-II, set the TRGE bit to 1 in the A/D control register (ADCR) and clear the EXTRG bit to 0 in the A/D trigger register (ADTRGR). When an ATU-II channel 0 interval timer A/D conversion request is generated after these settings have been made, the ADST bit set to 1. The timing from setting of the ADST bit until the start of A/D conversion is the same as when 1 is written into the ADST bit by software. 18.4.6 ADEND Output Pin When channel 31 is used in scan mode, the conversion timing can be monitored with the ADEND output pin. After the channel 31 analog voltage has been latched in scan mode, and conversion has started, the ADEND pin goes high. The ADEND pin subsequently goes low when channel 31 conversion ends. ADEND State of channel 28 (AN28) Idle State of channel 29 (AN29) Idle A/D conversion A/D conversion State of channel 30 (AN30) Idle Idle A/D conversion Figure 18.8 ADEND Output Timing Rev. 5.00 Feb. 24, 2010 Page 512 of 950 REJ09B0177-0500 Idle A/D conversion Idle A/D conversion Idle State of channel 31 A/D (AN31) conversion A/D conversion Idle Idle 18. A/D Converter 18.5 Interrupt Sources and DMA Transfer Requests The A/D converter can generate an A/D conversion end interrupt request (ADI0, ADI1, or ADI2) upon completion of A/D conversions. The ADI interrupt can be enabled by setting the ADIE bit in the A/D control/status register (ADCSR) to 1, or disabled by clearing the ADIE bit to 0. The DMAC can be activated by an ADI interrupt. In this case an interrupt request is not sent to the CPU. When the DMAC is activated by an ADI interrupt, the ADF bit in ADCSR is automatically cleared when data is transferred by the DMAC. See section 10.4.2, Example of DMA Transfer between A/D Converter and On-Chip Memory (Address Reload On), for an example of this operation. 18.6 Usage Notes The following points should be noted when using the A/D converter. 1. Analog input voltage range The voltage applied to analog input pins during A/D conversion should be in the range AVSS ANn AVref. 2. Relation between, AVSS, AVCC and VSS, VCC When using the A/D converter, set AVCC = 5.0 V 0.5 V, and AVSS = VSS. When the A/D converter is not used, set AVSS = VSS, and the setting range is AVSS AVCC 5.5 V. 3. AVref input range Set AVref = 4.5 V to AVCC when the A/D converter is used, and AVCC - 1.0 V AVref AVCC and AVSS AVref when not used. If conditions above are not met, the reliability of the device may be adversely affected. 4. Notes on board design In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values. Also, digital circuitry must be isolated from the analog input signals (ANn), analog reference voltage (AVref), and analog power supply (AVCC) by the analog ground (AVSS). AVSS should be connected at one point to a stable digital ground (VSS) on the board. 5. Notes on noise countermeasures A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (ANn) and analog reference voltage (AVref) should be connected between AVCC and AVSS as shown in figure 18.9. Also, the bypass capacitors connected to AVCC and AVref and the filter capacitor connected to ANn must be connected to AVSS. If a filter capacitor is connected as shown in figure 18.9, the input currents at the analog input pins (ANn) are averaged, and so an error may arise. Careful consideration is therefore required when deciding the circuit constants. Rev. 5.00 Feb. 24, 2010 Page 513 of 950 REJ09B0177-0500 18. A/D Converter AVCC AVref Rin*2 *1 This LSI 100 AN0-AN31 *1 0.1 F AVSS Notes: *1 10 F 0.01 F *2 Rin: Input impedance Figure 18.9 Example of Analog Input Pin Protection Circuit Table 18.5 Analog Pin Specifications Item Min Max Analog input capacitance -- 20 pF Permissible signal source impedance -- 3 k 18.6.1 Unit A/D conversion accuracy definitions A/D conversion accuracy definitions are given below. 1. Resolution The number of A/D converter digital conversion output codes 2. Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value 0000000000 to 0000000001 (does not include quantization error) (see figure 18.10). 3. Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from 1111111110 to 111111111 (does not include quantization error) (see figure 18.10). 4. Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 18.10). 5. Nonlinearity error The error with respect to the ideal A/D conversion characteristic between the zero voltage and the full-scale voltage. Does not include the offset error, full-scale error, or quantization error. 6. Absolute accuracy The deviation between the digital value and the analog input value. Includes the offset error, full-scale error, quantization error, and nonlinearity error. Rev. 5.00 Feb. 24, 2010 Page 514 of 950 REJ09B0177-0500 18. A/D Converter Digital output 111 Digital output Ideal A/D conversion characteristic Full-scale error Ideal A/D conversion characteristic 110 101 100 Nonlinearity error 011 010 Quantization error Actual A/D conversion characteristic 001 000 1/8 2/8 3/8 4/8 5/8 6/8 7/8 FS Analog input voltage Offset error FS Analog input voltage Figure 18.10 A/D Conversion Accuracy Definitions Rev. 5.00 Feb. 24, 2010 Page 515 of 950 REJ09B0177-0500 18. A/D Converter Rev. 5.00 Feb. 24, 2010 Page 516 of 950 REJ09B0177-0500 19. Multi-Trigger A/D Converter (MTAD) Section 19 Multi-Trigger A/D Converter (MTAD) 19.1 Overview The multi-trigger A/D converter (MTAD) is composed of two independent modules A/D0 and A/D1, as listed below. Module Analog Group Channels A/D0 Analog group 2 AN8 to AN11 A/D1 Analog group 5 AN20 to AN23 19.1.1 Feature The feature of the multi-trigger A/D conversion is shown below. * Multi-trigger A/D conversion mode While performing conversion on the specified channels in scan mode, A/D conversion on the channels for which conversion has been requested can be performed prior to the other channels when a compare match occurs with respect to the timer in the A/D converter. Rev. 5.00 Feb. 24, 2010 Page 517 of 950 REJ09B0177-0500 19. Multi-Trigger A/D Converter (MTAD) 19.1.2 Block Diagram Figure 19.1 shows a block diagram of the multi-trigger A/D converter. Timer control logic Module data bus Bus interface ADTRGR0 ADCR0 ADCSR0 Internal data bus A/D conversion control circuit + - Channel A interrupt A/D Priority ATU0 ADTRG0 Interrupt A/D end Sample-andhold circuit Channel B interrupt A/D AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 ADDR 0 to 11 10-bit D/A Successiveapproximation register Avcc Avref Avss Analog multiplexer A/D conversion part ADI0 ADT00A ADT00B Timer control logic ADT0 Bus interface ADTSR0 ADTIER0 ADDR0B ADDR0A ADCYLR0 ADGR0B ADGR0A ADCNT0 Clock select A/D timer part Module data bus ADTRGR1 ADCR1 ADCSR1 - Channel A interrupt A/D Priority ATU1 ADTRG1 Interrupt A/D end Analog multiplexer Internal data bus A/D conversion control circuit + Channel B interrupt A/D AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 ADDR 12 to 23 10-bit D/A Successiveapproximation register Avcc Avref Avss Bus interface Module data bus A/D conversion part ADI1 ADT01A ADT01B ADT1 Timer control logic Bus interface ADTSR1 ADTIER1 ADDR1B ADDR1A ADCYLR1 ADGR1B ADGR1A ADCNT1 Clock select A/D timer part Module data bus Figure 19.1 Simplified Block Diagram of Multi-Trigger A/D Converter Rev. 5.00 Feb. 24, 2010 Page 518 of 950 REJ09B0177-0500 19. Multi-Trigger A/D Converter (MTAD) 19.1.3 Input/Output Pins Table 19.1 summarizes the multi-trigger A/D converter output pins. When using these external pins, the pin function controller (PFC) should also be set in accordance with the A/D conversion settings. Table 19.1 Pin Configuration Channel Pin Name Abbreviation I/O Function 0 A/D timer output 0A ADTO0A Output PWM output 0 A/D timer output 0B ADTO0B Output PWM output 1 A/D timer output 1A ADTO1A Output PWM output 1 A/D timer output 1B ADTO1B Output PWM output 19.1.4 Register Configuration Channel Register Name Abbreviation R/W Initial Value 0 A/D free-running counter ADCNT0 R/W H'0001 H'FFFFF860 (upper byte) H'FFFFF861 (lower byte) 16 0 A/D cycle register 0 ADCYLR0 R/W H'FFFF H'FFFFF862 (upper byte) H'FFFFF863 (lower byte) 16 0 A/D duty register 0A ADDR0A R/W H'FFFF H'FFFFF864 (upper byte) H'FFFFF865 (lower byte) 16 0 A/D duty register 0B ADDR0B R/W H'FFFF H'FFFFF866 (upper byte) H'FFFFF867 (lower byte) 16 0 A/D general register 0A ADGR0A R/W H'FFFF H'FFFFF868 (upper byte) H'FFFFF869 (lower byte) 16 0 A/D general register 0B ADGR0B R/W H'FFFF H'FFFFF86A (upper byte) H'FFFFF86B (lower byte) 16 0 A/D trigger control register 0 ADTCR0 R/W H'00 H'FFFFF86C 8 0 A/D trigger status register 0 ADTSR0 R/(W)* H'00 H'FFFFF86D 8 0 A/D trigger interrupt enable register 0 ADTIER0 R/W H'00 H'FFFFF86E 8 1 A/D free-running counter 1 ADCNT1 R/W H'0001 H'FFFFF870 (upper byte) H'FFFFF871 (lower byte) 16 1 A/D cycle register 1 ADCYLR1 R/W H'FFFF H'FFFFF872 (upper byte) H'FFFFF873 (lower byte) 16 1 A/D duty register 1A ADDR1A R/W H'FFFF H'FFFFF874 (upper byte) H'FFFFF875 (lower byte) 16 1 A/D duty register 1B ADDR1B R/W H'FFFF H'FFFFF876 (upper byte) H'FFFFF877 (lower byte) 16 1 A/D general register 1A ADGR1A R/W H'FFFF H'FFFFF878 (upper byte) H'FFFFF879 (lower byte) 16 1 A/D general register 1B ADGR1B R/W H'FFFF H'FFFFF87A (upper byte) H'FFFFF87B (lower byte) 16 1 A/D trigger control register ADTCR1 R/W H'00 H'FFFFF87C 8 1 A/D trigger status register 1 ADTSR1 1 A/D trigger interrupt enable register 1 ADTIER1 Note: * Address Access Size R/(W)* H'00 H'FFFFF87D 8 R/W H'FFFFF87E 8 H'00 Only 0 can be written. Rev. 5.00 Feb. 24, 2010 Page 519 of 950 REJ09B0177-0500 19. Multi-Trigger A/D Converter (MTAD) 19.2 Register Descriptions 19.2.1 A/D Trigger Control Registers 0 and 1 (ADTCR0 and ADTCR1) A/D trigger control registers 0 and 1 (ADTCR0 and ADTCR1) are 8-bit readable/writable registers whose functions include selection of the prescaler. ADTCR0 and ADTCR1 are initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 CKSEL1x CKSEL0x -- -- DTSELxB DTSELxA ADSELxB ADSELxA 0 0 0 0 0 0 0 0 R/W R/W R R R/W R/W R/W R/W * Bits 7 and 6--Clock Select 1 and 0 (CKSEL1x and CKSEL0x): Halt the counter or select internal clock " from among P/2, P/5, and P/10, which are obtained by dividing clock P. Bit 7: CKSEL1x Bit 6: CKSEL0x Description 0 0 Counter is halted 1 Counter is incremented with internal clock " = P/2 0 Counter is incremented with internal clock " = P/5 1 Counter is incremented with internal clock " = P/10 1 * Bits 5 and 4--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 3--Duty Select 1B or 0B (DTSEL1B or DTSEL0B): Selects either on-duty or off-duty for the PWM output from ADTOxB of channel xB. Bit 3: DTSELxB Description 0 On-duty for the PWM output from ADTOxB 1 Off-duty for the PWM output from ADTOxB (Initial value) Note: x = 0 or 1. * Bit 2--Duty Select 1A or 0A (DTSEL1A or DTSEL0A): Selects either on-duty or off-duty for the PWM output from ADTOxA of channel xA. Bit 2: DTSELxA Description 0 On-duty for the PWM output from ADTOxA 1 Off-duty for the PWM output from ADTOxA (Initial value) Note: x = 0 or 1. * Bit 1--A/D Data Select 1B (ADSEL1B): Selects the register to which the result of multi-trigger A/D conversion is transferred. This bit is inverted when the ADDR register is updated by the multi-trigger A/D conversion. Switching settings during the multi-trigger A/D conversion operation should be carried out when TADF1B (ADTSR1 register) is 1. Rev. 5.00 Feb. 24, 2010 Page 520 of 950 REJ09B0177-0500 19. Multi-Trigger A/D Converter (MTAD) Bit 1: ADSEL1B Description 0 Conversion result is transferred to ADDR22 1 Conversion result is transferred to ADDR23 (Initial value) * Bit 1--A/D Data Select 0B (ADSEL0B): Selects the register to which the result of multi-trigger A/D conversion is transferred. This bit is inverted when the ADDR register is updated by the multi-trigger A/D conversion. Switching settings during the multi-trigger A/D conversion operation should be carried out when TADF0B (ADTSR0 register) is set to 1. Bit 1: ADSEL0B Description 0 Conversion result is transferred to ADDR10 1 Conversion result is transferred to ADDR11 (Initial value) * Bit 0--A/D Data Select 1A (ADSEL1A): Selects the register to which the result of multi-trigger A/D conversion is transferred. This bit is inverted when the ADDR register is updated by the multi-trigger A/D conversion. Switching settings during the multi-trigger A/D conversion operation should be carried out when TADF1A (ADTSR1 register) is set to 1. Bit 0: ADSEL1A Description 0 Conversion result is transferred into ADDR20 1 Conversion result is transferred into ADDR21 (Initial value) * Bit 0--A/D Data Select 0A (ADSEL0A): Selects the register to which the result of multi-trigger A/D conversion is transferred. This bit is inverted when the ADDR register is updated by the multi-trigger A/D conversion. Switching settings during the multi-trigger A/D conversion operation should be carried out when TADF0A (ADTSR0 register) is set to 1. Bit 0: ADSEL0A Description 0 Conversion result is transferred to ADDR8 1 Conversion result is transferred to ADDR9 (Initial value) Rev. 5.00 Feb. 24, 2010 Page 521 of 950 REJ09B0177-0500 19. Multi-Trigger A/D Converter (MTAD) 19.2.2 A/D Trigger Status Registers 0 and 1 (ADTSR0 and ADTSR1) A/D trigger status registers 0 and 1 (ADTSR0 and ADTSR1) indicate the compare match generation and the multi-trigger A/D conversion status in channels 0 and 1. ADTSR0 and ADTSR1 are initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. Bit: 7 6 5 4 3 2 -- TADFxB TADFxA ADDFxB ADDFxA ADCYLFx 1 0 ADCMFxB ADCMFxA Initial value: 0 0 0 0 0 0 0 0 R/W: -- R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: x = 0 or 1. * Only 0 can be written, to clear the flag. * Bit 7--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 6--Trigger A/D Flag B (TADFxB): Indicates the end of multi-trigger A/D conversion B. Bit 6: TADFxB Description 0 Indicates that the multi-trigger A/D converter is performing A/D conversion B, or the converter is in the idle state (Initial value) [Clearing condition] When TADFxB is read while set to 1, then 0 is written to TADFxB 1 Indicates that the multi-trigger A/D converter has finished A/D conversion B, and the digital value has been transferred to ADDR [Setting condition] When multi-trigger A/D conversion B ends Note: x = 0 or 1. * Bit 5--Trigger A/D Flag A (TADFxA): Indicates the end of multi-trigger A/D conversion A. Bit 5: TADFxA Description 0 Indicates that the multi-trigger A/D converter is performing A/D conversion A, or the converter is in the idle state (Initial value) [Clearing condition] When TADFxA is read while set to 1, then 0 is written to TADFxA 1 Indicates that the multi-trigger A/D converter has finished A/D conversion A, and the digital value has been transferred to ADDR [Setting condition] When multi-trigger A/D conversion A ends Note: x = 0 or 1. Rev. 5.00 Feb. 24, 2010 Page 522 of 950 REJ09B0177-0500 19. Multi-Trigger A/D Converter (MTAD) * Bit 4--A/D Duty Flag B (ADDFxB): Indicates whether or not the ADDRxB and ADCNT values have matched. Bit 4: ADDFxB Description 0 [Clearing condition] When ADDFxB is read while set to 1, then 0 is written to ADDFxB 1 [Setting condition] When ADCNTx and ADDRxB values have matched (Initial value) Note: x = 0 or 1. * Bit 3--A/D Duty Flag A (ADDFxA): Indicates whether or not the ADDRxA and ADCNT values have matched. Bit 3: ADDFxA Description 0 [Clearing condition] When ADDFxA is read while set to 1, then 0 is written to ADDFxA 1 [Setting condition] When ADCNTx and ADDRxA values have matched (Initial value) Note: x = 0 or 1. * Bit 2--A/D Cycle Compare Match Flow Flag (ADCYLFx): Indicates whether or not the ADCYLRx and ADCNT values have matched. Bit 2: ADCYLFx Description 0 [Clearing condition] When ADCYLFx is read while set to 1, then 0 is written to ADCYLFx 1 [Setting condition] When ADCNTx and ADCYLRx values have matched (Initial value) Note: x = 0 or 1. * Bit 1--A/D Compare Match Flag (ADCMFxB): Indicates whether or not the ADGRxB and ADCNT values have matched. Bit 1: ADCMFxB Description 0 [Clearing condition] When ADCMFxB is read while set to 1, then 0 is written to ADCMFxB 1 [Setting condition] When ADCNTx and ADGRxB values have matched (Initial value) Note: x = 0 or 1. * Bit 0--A/D Compare Match Flag (ADCMFxA): Indicates whether or not the ADGRxA and ADCNT values have matched. Bit 0: ADCMFxA Description 0 [Clearing condition] When ADCMFxA is read while set to 1, then 0 is written to ADCMFxA 1 [Setting condition] When ADCNTx and ADGRxA values have matched (Initial value) Note: x = 0 or 1. Rev. 5.00 Feb. 24, 2010 Page 523 of 950 REJ09B0177-0500 19. Multi-Trigger A/D Converter (MTAD) 19.2.3 A/D Trigger Interrupt Enable Registers 0 and 1 (ADTIER0 and ADTIER1) A/D trigger interrupt enable registers 0 and 1 (ADTIER0 and ADTIER1) enable or disable interrupt request triggered by the compare match generation and multi-trigger A/D conversion end in channels 0 and 1. ADTIER0 and ADTIER1 are initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 ADTRGx TADExB TADExA ADDExB ADDExA ADCYLFx 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W ADCMExB ADCMExA Note: x = 0 or 1. * Bit 7--ADT Trigger (ADTRGx): Enables or disables triggering of multi-trigger A/D conversion by a compare match between ADCNTx and ADGRxA or ADGRxB. To prevent incorrect operation, ensure that the ADST bit in A/D control register (ADCR) is 0 before switching this setting. Bit 7: ADTRGx Description 0 Triggering of multi-trigger A/D conversion by a compare match between ADCNTx and ADGRxA or ADGRxB is disabled (Initial value) 1 Triggering of multi-trigger A/D conversion by a compare match between ADCNTx and ADGRxA or ADGRxB is enabled Notes: 1. x = 0 or 1. 2. Value 1 can be set to ADTRGx only for the cases below; 0 should always be set for the other cases. Conversion mode (ADCR): continuous scan Channels for conversion (ADCSRx): Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Analog Input Channels ADM1 ADM0 CH3 CH2 CH1 CH0 A/D0 A/D1 0 1 0 0 1 1 AN0 to AN3 AN12 to AN15 1 0 0 0 1 1 AN0 to AN7 AN12 to AN19 0 1 0 1 1 1 AN4 to AN7 AN16 to AN19 Notes: 1. x = 0 or 1. 2. For the ADCR and ADCSRx settings, refer to section 18, A/D Converter. * Bit 6--Trigger A/D Interrupt Enable B (TADExB): Enables or disables the interrupt request by TADFxB when the trigger A/D flag xB (TADFxB) in ADTSR is set to 1. To prevent incorrect operation, ensure that the ADTRG bit in A/D trigger interrupt enable register (ADTIER0 or ADTIER1) is 0 before switching this setting. Bit 6: TADExB Description 0 The interrupt request (TADIxB) by TADFxB is disabled 1 The interrupt request (TADIxB) by TADFxB is enabled Rev. 5.00 Feb. 24, 2010 Page 524 of 950 REJ09B0177-0500 (Initial value) 19. Multi-Trigger A/D Converter (MTAD) When multi-trigger A/D conversion B ends, setting TADFxB to 1, a trigger A/D interrupt for A/D0 or A/D1 (TADIxB) is requested if TADExB is 1. TADIxB can be cleared to 0 by clearing TADFxB or TADExB to 0. * Bit 5--Trigger A/D Interrupt Enable A (TADExA): Enables or disables the interrupt request by TADFxA when the trigger A/D flag xA (TADFxA) in ADTSR is set to 1. To prevent incorrect operation, ensure that the ADTRG bit in A/D trigger interrupt enable register (ADTIER0 or ADTIER1) is 0 before switching this setting. Bit 5: TADExA Description 0 The interrupt request (TADIxA) by TADFxA is disabled 1 The interrupt request (TADIxA) by TADFxA is enabled (Initial value) When multi-trigger A/D conversion A ends setting TADFxA to 1, a trigger A/D interrupt for A/D0 or A/D1 (TADIxA) is requested if TADExA is 1. TADIxA can be cleared to 0 by clearing TADFxA or TADExA to 0. * Bit 4--A/D Duty Interrupt Enable B (ADDExB): Enables or disables the interrupt request by ADDFxB when the ADDRxB compare match flag (ADDFxB) in ADTSR is set to 1. Bit 4: ADDExB Description 0 The interrupt request (ADDIxB) by ADDFxB is disabled 1 The interrupt request (ADDIxB) by ADDFxB is enabled (Initial value) Note: x = 0 or 1. * Bit 3--A/D Duty Interrupt Enable A (ADDExA): Enables or disables the interrupt request by ADDFxA when the ADDRxA compare match flag (ADDFxA) in ADTSR is set to 1. Bit 3: ADDExA Description 0 The interrupt request (ADDIxA) by ADDFxA is disabled 1 The interrupt request (ADDIxA) by ADDFxA is enabled (Initial value) Note: x = 0 or 1. * Bit 2--A/D Cycle Interrupt Enable (ADCYLEx): Enables or disables the interrupt request by ADCYLFx when the A/D cycle compare match flow flag (ADCYLFx) in ADTSRx is set to 1. Bit 2: ADCYLEx Description 0 The interrupt request (ADCYIx) by ADCYLFx is disabled 1 The interrupt request (ADCYIx) by ADCYLFx is enabled (Initial value) Note: x = 0 or 1. * Bit 1--A/D Compare Match Interrupt Enable B (ADCMExB): Enables or disables the interrupt request by ADCMFxB when the ADDRxB compare match flag (ADCMFxB) in ADTSR is set to 1. Bit 1: ADCMExB Description 0 The interrupt request (ADDIxB) by ADCMFxB is disabled 1 The interrupt request (ADDIxB) by ADCMFxB is enabled (Initial value) Note: x = 0 or 1. Rev. 5.00 Feb. 24, 2010 Page 525 of 950 REJ09B0177-0500 19. Multi-Trigger A/D Converter (MTAD) * Bit 0--A/D Compare Match Interrupt Enable A (ADCMExA): Enables or disables the interrupt request by ADCMFxA when the ADDRxA compare match flag (ADCMFxA) in ADTSR is set to 1. Bit 0: ADCMExA Description 0 The interrupt request (ADDIxA) by ADCMFxA is disabled 1 The interrupt request (ADDIxA) by ADCMFxA is enabled (Initial value) Note: x = 0 or 1. 19.2.4 A/D Free-Running Counters (ADCNT0 and ADCNT1) A/D free-running counters 0 and 1 (ADCNT0 and ADCNT1) are 16-bit readable/writable registers that start incrementing according to the setting of the A/D trigger control registers (ADTCR0 and ADTCR1). The clock selected by the prescaler (ADTCR0 and ADTCR1) is input to the corresponding counters. ADCNT0 and ADCNT1 are initialized to H'0001 by a power-on reset, and in hardware standby mode and software standby mode. ADCNT0 and ADCNT1 can only be read from or written to in words. Bit: 15 Initial Value: 0 R/W: R/W 19.2.5 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W A/D General Registers A and B (ADGR0A, ADGR0B, ADGR1A, and ADGR1B) A/D general registers (ADGR0A, ADGR0B, ADGR1A, and ADGR1B) are 16-bit readable/writable registers. Two registers are provided for each of channels 0 and 1. The ADGR value is constantly compared with the corresponding free-running counter (ADCNT0 or ADCNT1) value. When the two values match, the ADCMFxA and ADCMFxB bits in the corresponding A/D trigger status register (ADTSR) are set to 1, which requests initiation of the multi-trigger A/D conversion. ADGR0A, ADGR0B, ADGR1A, and ADGR1B can only be read from or written to in words. ADGR0A, ADGR0B, ADGR1A, and ADGR1B are initialized to H'FFFF by a power-on reset, and in hardware standby mode and software standby mode. Bit: 15 Initial Value: 1 R/W: R/W 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. 5.00 Feb. 24, 2010 Page 526 of 950 REJ09B0177-0500 19. Multi-Trigger A/D Converter (MTAD) 19.2.6 A/D Cycle Registers 0 and 1 (ADCYLR0 and ADCYLR1) A/D cycle registers (ADCYLR0 and ADCYLR1) are 16-bit readable/writable registers. One register is provided for each of channels 0 and 1. The ADCYLR value is constantly compared with the corresponding free-running counter (ADCNT0 or ADCNT1) value. When the two values match, the ADCYLFx bit in the corresponding A/D trigger status register (ADTSR) is set to 1, which clears ADCNT0 and ADCNT1 to H'0001. ADCYLR0 and ADCYLR1 can only be read from or written to in words. ADCYLR0 and ADCYLR1 are initialized to H'FFFF by a power-on reset, and in hardware standby mode and software standby mode. Bit: 15 Initial Value: 1 R/W: R/W 19.2.7 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W A/D Duty Registers A and B (ADDR0A, ADDR0B, ADDR1A, and ADDR1B) A/D duty registers (ADDR0A, ADDR0B, ADDR1A, and ADDR1B) are 16-bit readable/writable registers. Two registers are provided for each of channels 0 and 1. The ADDR value is constantly compared with the corresponding free-running counter (ADCNT0 or ADCNT1) value. When the two values match, the ADDFxA and ADDFxB bits in the corresponding A/D trigger status register (ADTSR) are set to 1. ADDR0A, ADDR0B, ADDR1A, and ADDR1B can only be read from or written to in words. ADDR0A, ADDR0B, ADDR1A, and ADDR1B are initialized to H'FFFF by a power-on reset, and in hardware standby mode and software standby mode. Bit: 15 Initial Value: 1 R/W: R/W 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. 5.00 Feb. 24, 2010 Page 527 of 950 REJ09B0177-0500 19. Multi-Trigger A/D Converter (MTAD) 19.3 Operation 19.3.1 Overview The multi-trigger A/D converter is divided into the timer parts and A/D conversion parts. The timer parts include two channels 0 and 1, each of which includes the prescaler that can generate or provide the selection of an input clock having the desired frequency. The following are general descriptions of the operations of the channels and prescalers. (1) Channels 0 and 1 Channels 0 and 1 include 16-bit free running counters (ADCNT0 and ADCNT1), 16-bit cycle registers (ADCYLR0 and ADCYLR1), 16-bit duty registers (ADDR0A, ADDR0B, ADDR1A, and ADDR1B), and 16-bit general registers (ADGR0A, ADGR0B, ADGR1A, and ADGR1B), respectively. They also have external output pins of their own (ADTO0A, ADTO0B, ADTO1A, and ADTO1B), thus allowing the channels to be used as PWM timers. ADCNT0 and ADCNT1, which are the incrementing counters, output 0 (1)* to the external output pins when the counter value matches the ADDR value (when ADDR ADCYLR). When the counter value matches the ADCYLR value (when ADDR H'0000), ADCNT0 and ADCNT1 output 1 (0)* to the external output pins, simultaneously clearing the ADCNT value to H'0001. Due to these operations, channels 0 and 1 can output a waveform having the cycle specified by the ADCYLR value and the duty specified by the ADDR value. When ADDR = ADCYLR, ADCNT0 and ADCNT1 output 1 (0)* continuously to the external output pins, thus providing a 100%-duty waveform, and when ADDR = H'0000, these counters output 0 (1)* continuously to the external output pins, thus providing a 0%-duty waveform. Note that the ADDR value should never be greater than the ADCYLR value. Channels 0 and 1 also perform the compare match operation when the ADCNT value matches the ADGR0A, ADGR0B, ADGR1A, or ADGR1B value that has been set in ADGR previously. However, no output pins are provided. The channels can also trigger multi-trigger A/D conversion using the compare matches. Neither ADCNT0 nor ADCNT1 is cleared when the value matches the ADGR0A, ADGR0B, ADGR1A, or ADGR1B value. Note: * Selected by the A/D trigger control register (ADTCR). (2) Prescalers Each channel has a dedicated prescaler that can halt the clock signal or divide its frequency by 2, 5, or 10, according to the setting of the A/D trigger control registers (ADTCR0 and ADTCR1) for the corresponding channel. 19.3.2 PWM Operation Channels 0 and 1 can be unconditionally used as PWM timers using external output pins (ADTO0A, ADTO0B, ADTO1A, and ADTO1B). When the prescaler is set using the A/D trigger control register (ADTCR) thus starting the free-running counter (ADCNT) in channels 0 and 1, the counters increment the count value until the value matches the value in the corresponding cycle register (ADCYLR). When the ADCNT value matches the ADCYLR value, the ADCNT value is cleared to H'0001, thus incrementing again from H'0001. Here, the corresponding pins output 1 (0)*. When the appropriate value is set in the duty register (ADDR) and the ADCNT matches the ADDR value, the corresponding pins output 0 (1)*. When the ADDR value is H'0000, the output does not change (0% duty). To obtain the 100% duty output, set the same values to the ADDR and ADCYLR. Note that the ADDR value should not be greater than the ADCYLR value. Note: * Selected by the DTSEL0A, DTSEL0B, DTSEL1A, and DTSEL1B bits in the A/D trigger control register (ADTCR). Rev. 5.00 Feb. 24, 2010 Page 528 of 950 REJ09B0177-0500 19. Multi-Trigger A/D Converter (MTAD) 19.3.3 Compare Match Operation The A/D general registers (ADGR0A, ADGR0B, ADGR1A, and ADGR1B) in channels 0 and 1 can trigger the corresponding multi-trigger A/D converters. When the A/D trigger control register (ADTCR) is set appropriately, the free-running counter (ADCNT) starts incrementing the count value. When the ADCNT value matches the ADGR value that has been set previously, the compare match is generated, requesting the corresponding multi-trigger A/D converter to start. However, no output pins are provided. 19.3.4 Multi-Trigger A/D Conversion Operation The multi-trigger A/D conversion is the special conversion mode, in which A/D conversion on the special cha956els is performed prior to the other channels during continuous scan mode. When using the multi-trigger A/D conversion operation, only the settings shown below are possible for continuous scan mode; other settings are prohibited. Channels for Conversion (ADCSRx) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Analog Input Channels ADM1 ADM0 CH3 CH2 CH1 CH0 A/D0 A/D1 0 1 0 0 1 1 AN0 to AN3 AN12 to AN15 1 0 0 0 1 1 AN0 to AN7 AN12 to AN19 0 1 0 1 1 1 AN4 to AN7 AN16 to AN19 Note: x = 0 or 1. Be sure to start multi-trigger A/D conversion only while the ADCMFxB and ADCMFxA bits in the A/D trigger status registers 0 and 1 (ADTSR0 and ADTSR1) are 0. When the multi-trigger A/D conversion is complete, clear these bits. Multi-trigger A/D conversion can be enabled by setting the ADTRG in the A/D trigger interrupt enable registers 0 and 1 (ADTIER0 and ADTIER1) to 1. Multi-trigger A/D conversion starts when the A/D counter (ADCNT) value matches the A/D general register (ADGR) value during scan mode on the specified channels while the ADTRG bit in the A/D trigger interrupt enable register (ADTIER) is 1. When the A/D conversion on the current channel in continuous scan mode is complete, the multi-trigger A/D conversion on the channels for which the conversion has been requested is performed prior to the other channels. When the multi-trigger A/D conversion on the channels for which the conversion has been requested is complete, the A/D conversion starts again on the channel that has been halted. When the multi-trigger A/D conversion A (AN8, AN9, AN20, and AN21) and B (AN10, AN11, AN22, and AN23) on the channel for which the conversion has been requested is complete, the results are transferred to the appropriate ADDR in accordance with the setting of the A/D select bits (ADSEL) in the A/D trigger control register (ADTCR) at the start of the multi-trigger A/D conversion, thus setting the TADFxA and TADFxB bits in ADTSR to 1. Here, if the TADExA and TADExB bits in ADTIER are 1, the TADIxA and TADIxB interrupts are requested. To clear the TADFxA and TADFxB bits to 0, read these bits while they are 1, and write 0 to them. An example of the operation when analog inputs 0 to 7 (AN0 to AN7) are selected; A/D conversion is performed in 8channel scan mode; and A/D interrupt conversion is performed is described below. Figure 19.4 shows the operation flowchart for the example. 1. 8-channel scan mode is selected (ADM1 = 1 and ADM0 = 0), continuous scan mode is selected (ADCS = 1), analog input channels AN0 to AN7 are selected (CH3 = 0, CH2 = 0, CH1 = 1, and CH0 = 1), the A/D0 module is enabled for triggering of multi-trigger A/D conversion (ADTRG = 1), multi-trigger A/D conversion end interrupt is enabled (TADExA and TADExB = 1), and A/D conversion is started. Rev. 5.00 Feb. 24, 2010 Page 529 of 950 REJ09B0177-0500 19. Multi-Trigger A/D Converter (MTAD) 2. When conversion of the first channel (AN0) is completed, the result is transferred to ADDR0. 3. Conversion proceeds in the same way through the eighth channel (AN7). 4. When conversion is completed for all the selected channels (AN0 to AN7), the ADF flag is set to 1. If the ADIE bit is 1 at the completion of conversion, an ADI interrupt is requested after A/D conversion ends. 5. If the A/D counter (ADCNT) and A/D general register (ADGR) values match during conversion of AN0 to AN7, the multi-trigger A/D conversion on the channels for which the conversion has been requested is started after A/D conversion of the current channel ends. 6. When the multi-trigger A/D conversion on the channels for which the conversion has been requested is completed, the result is transferred to ADDRx and the A/D data select (ADSELx) is inverted. If the TADIExA or TADIExB is 1 at the completion of multi-trigger A/D conversion, a TADIA or TADIB interrupt of the completed channel is requested. 7. After step 6, the A/D conversion starts again on the channel that has been halted. While ADST is 1, steps 2 to 7 are repeated. Note: When multi-trigger A/D conversion is requested simultaneously from two sources, conversion is performed according to the priority. Priority high CMFxA Priority low > CMFxB Rev. 5.00 Feb. 24, 2010 Page 530 of 950 REJ09B0177-0500 19. Multi-Trigger A/D Converter (MTAD) ADST ADF Clear* ADCMFxA Clear* ADCMFxB Clear* TADFxA Clear* TADFxB Idle A/D conversion (1) Channel 0 (AN0) Idle Channel 1 (AN1) Idle Channel 8 (AN8) Channel 2 (AN2) Channel 10 (AN10) Channel 3 (AN3) ADDR0 Idle A/D conversion (2) A/D conversion (3) Idle A/D conversion (4) Idle Idle Idle A/D conversion (5) Idle Idle A/D conversion (6) A/D conversion result (1) A/D conversion result (2) ADDR1 ADDR2 A/D conversion result (4) ADDR3 A/D conversion result (3) ADDR8 A/D conversion result (5) ADDR10 Note: * Instructions executed by software are indicated. Figure 19.2 Example of Multi-Trigger A/D Converter Operation Rev. 5.00 Feb. 24, 2010 Page 531 of 950 REJ09B0177-0500 19. Multi-Trigger A/D Converter (MTAD) Multi-trigger A/D conversion mode A/D conversion and multi-trigger A/D conversion are set TADFxB, TADFxA, ADCMFxB, and ADCMFxA flags are cleared Continuous scan starts A/D conversion on ANx is performed Data is transferred to ADDRx ADST=1? Are ADCMFxB and ADCMFxA 0? Yes No Yes No A/D conversion ends Is multi-trigger A/D conversion requested? Yes A/D conversion on the ANx for which the conversion has been requested is performed Data is transferred to ADDRx TADFx is set to 1 Figure 19.3 Flowchart of Multi-Trigger A/D Converter Operation Rev. 5.00 Feb. 24, 2010 Page 532 of 950 REJ09B0177-0500 No 19. Multi-Trigger A/D Converter (MTAD) 19.3.5 Interrupts Each of channels 0 and 1 generate interrupts from seven sources, that is, a total of 14 sources listed below. Module IPR Bit Vector Vector Number ADT0 IPRJ (11 to 8) ADI0 189 Conditions of Interrupt Generation Multi-trigger A/D conversion ends when the interrupt is enabled by TADE0A Multi-trigger A/D conversion ends when the interrupt is enabled by TADE0B ADCNT0 matches ADCYLR0 when the interrupt is enabled by CYE0 ADCNT0 matches ADDR0A when the interrupt is enabled by ADDE0A ADCNT0 matches ADDR0B when the interrupt is enabled by ADDE0B ADCNT0 matches ADGR0A when the interrupt is enabled by ADCME0A ADCNT0 matches ADGR0B when the interrupt is enabled by ADCME0B Module IPR Bit Vector Vector Number ADT1 IPRJ (7 to 4) ADI1 193 Conditions of Interrupt Generation Multi-trigger A/D conversion ends when the interrupt is enabled by TADE1A Multi-trigger A/D conversion ends when the interrupt is enabled by TADE1B ADCNT1 matches ADCYLR1 when the interrupt is enabled by CYE1 ADCNT1 matches ADDR1A when the interrupt is enabled by ADDE1A ADCNT1 matches ADDR1B when the interrupt is enabled by ADDE1B ADCNT1 matches ADGR1A when the interrupt is enabled by ADCME1A ADCNT1 matches ADGR1B when the interrupt is enabled by ADCME1B 19.3.6 Usage Notes 1. When a conflict occurs between a write to ADCNT and clearing of the counter by a compare match When a compare match occurs during T2 state of a CPU cycle for writing to ADCNT, ADCNT is not cleared but is written to. However, a compare match remains effective, thus allowing a write of 1 to the interrupt status flag and external waveform output, similar to regular compare matches. 2. When a conflict occurs between a write to ADCNT and incrementing of the counter The counter is not incremented but is written to. 3. When a conflict occurs between clearing of the interrupt status flag and setting of the flag by interrupt generation When any event, such as a compare match and overflow, occurs during T2 state of a CPU cycle for writing 0 to the interrupt status flag, the compare match takes priority thus allowing the interrupt status flag to be set. 4. When reading the continuous scan A/D conversion data during the multi-trigger A/D conversion is performed Reading is performed by the DMA. Following errors are generated according to the interrupt timing. When reading ADDR of the first channel by the continuous scan interrupt, if MTAD is executed on the last channel in the previous scan, the data may be overwritten again in this scan because the first channel is converted. Rev. 5.00 Feb. 24, 2010 Page 533 of 950 REJ09B0177-0500 19. Multi-Trigger A/D Converter (MTAD) 19.3.7 Operation Waveform Examples (A) Hardware Operation 1. A compare match occurs, setting the status flag to the corresponding source. 2. Multi-trigger A/D conversion that is enabled by A/D trigger (ADTRG) in the A/D trigger interrupt enable register (ADTIER) starts. After Multi-trigger A/D conversion is Over 3. Multi-trigger A/D conversion result is transferred to the register that is specified by A/D select (ADSEL) in the A/D trigger control register (ADTCR) at the start of the conversion. 4. An interrupt is generated if the multi-trigger A/D conversion end interrupt is enabled. Software Operation 1. A compare match flag is cleared. 2. The value in the A/D general register (ADGR) is changed. 3. A/D select (ADSEL) in the A/D trigger control register (ADTCR) is changed. After Multi-trigger A/D conversion is Over 4. The multi-trigger A/D conversion end flag is cleared. 5. The conversion result is read out. (B) Hardware Operation 1. A compare match occurs, setting the status flag to the corresponding source. 2. An interrupt is generated if the A/D duty enable bit (ADDE) in the A/D trigger interrupt enable register (ADTIER) is set. 3. The level of the external output pin is changed. Software Operation 1. The duty compare match flag is cleared. (C) Hardware Operation 1. A compare match occurs, setting the status flag to the corresponding source. 2. An interrupt is generated if the A/D cycle enable bit (ADCYLR) in the A/D trigger interrupt enable register (ADTIER) is set. 3. The level of the external output pin is changed. 4. Clear ADCNT to H'0001 Software Operation 1. The cycle compare match flag is cleared. 2. The values in the A/D duty register (ADDR) and the A/D cycle register (ADCYLR) are changed. Rev. 5.00 Feb. 24, 2010 Page 534 of 950 REJ09B0177-0500 19. Multi-Trigger A/D Converter (MTAD) ADCYLRx ADGRxA ADGRxB ADDRxA ADDRxB ADGRxA ADGRxB ADTOxA ADTOxB (A) Note: x = 0, 1 (A) (B) (B) (A) (A) (C) (A) (A) DTSELxA, xB=0 (On-duty output is selected for PWM.) Figure 19.4 Example of Output Waveform from MTAD PWM Rev. 5.00 Feb. 24, 2010 Page 535 of 950 REJ09B0177-0500 19. Multi-Trigger A/D Converter (MTAD) Rev. 5.00 Feb. 24, 2010 Page 536 of 950 REJ09B0177-0500 20. High-performance User Debug Interface (H-UDI) Section 20 High-performance User Debug Interface (H-UDI) 20.1 Overview The High-performance user debug interface (H-UDI) provides data transfer, interrupt request, and boundary scan functions. The H-UDI performs serial transfer by means of external signal control. 20.1.1 Features The H-UDI has the following features conforming to the IEEE 1149.1 standard. * * * * * * Five test signals (TCK, TDI, TDO, TMS, and TRST) TAP controller Instruction register Data register Bypass register Boundary scan register The H-UDI has seven instructions. * BYPASS mode Test mode conforming to IEEE 1149.1 * EXTEST mode Test mode conforming to IEEE1149.1. * SAMPLE/PRELOAD mode Test mode conforming to IEEE1149.1. * CLAMP mode Test mode conforming to IEEE1149.1. * HIGHZ mode Test mode conforming to IEEE1149.1. * IDCODE mode Test mode conforming to IEEE1149.1. * H-UDI interrupt H-UDI interrupt request to INTC Rev. 5.00 Feb. 24, 2010 Page 537 of 950 REJ09B0177-0500 20. High-performance User Debug Interface (H-UDI) 20.1.2 H-UDI Block Diagram Figure 20.1 shows a block diagram of the H-UDI. TCK TMS TAP controller Internal bus controller H-UDI interrupt signal TRST TDI Decoder SDDRH 16 SDDRL SDIDR TDO Mux Legend: SDIR: SDSR: SDDRH: SDDRL: SDBPR: SDBSR: Instruction register Status register Data register H Data register L Bypass register Boundary scan register TCK: TMS: TRST: TDI: TDO: SDIDR: Test clock Test mode select Test reset Test data input Test data output ID code register Figure 20.1 H-UDI Block Diagram Rev. 5.00 Feb. 24, 2010 Page 538 of 950 REJ09B0177-0500 Peripheral bus SDSR Shift register SDBSR SDBPR SDIR 20. High-performance User Debug Interface (H-UDI) 20.1.3 Pin Configuration Table 20.1 shows the H-UDI pin configuration. Table 20.1 Pin Configuration Pin Name Abbreviation I/O Function Test clock TCK Input Test clock input Test mode select TMS Input Test mode select input signal Test data input TDI Input Serial data input Test data output TDO Output Serial data output Test reset TRST Input Test reset input signal 20.1.4 Register Configuration Table 20.2 shows the H-UDI registers. Table 20.2 Register Configuration Register Abbreviation R/W*1 Initial Value*2 Address Access Size (Bits) Instruction register SDIR R H'E000 H'FFFFF7C0 8/16/32 Status register SDSR R/W H'5001 (SH7058SF) H'FFFFF7C2 8/16/32 H'0F01 (SH7059F) Data register H SDDRH R/W Undefined H'FFFFF7C4 8/16/32 Data register L SDDRL R/W Undefined H'FFFFF7C6 8/16/32 Bypass register SDBPR -- -- -- -- Boundary scan register SDBSR -- -- -- -- ID code register SDIDR -- H'08016447 (SH7058SF) -- -- H'0800B447 (SH7059F) Notes: 1. Indicates whether the register can be read from/written to by the CPU. 2. Initial value when the TRST signal is input. Registers are not initialized by a reset (power-on or manual). Instructions and data can be input to the instruction register (SDIR) and data register (SDDR) by serial transfer from the test data input pin (TDI). Data from SDIR, the status register (SDSR), and SDDR can be output via the test data output pin (TDO). The bypass register (SDBPR) is a 1-bit register to which TDI and TDO are connected in BYPASS, CLAMP, or HIGHZ mode. The boundary scan register (SDBSR) is a 474-bit register, and is connected to TDI and TDO in the SAMPLE/PRELOAD or EXTEST mode. The ID code register (SDIDR) is a 32-bit register; a fixed code can be output via TDO in the IDCODE mode. All registers, except SDBPR, SDBSR, and SDIDR, can be accessed from the CPU. Rev. 5.00 Feb. 24, 2010 Page 539 of 950 REJ09B0177-0500 20. High-performance User Debug Interface (H-UDI) Table 20.3 shows the kinds of serial transfer possible with each register. Table 20.3 H-UDI Register Serial Transfer Register Serial Input Serial Output SDIR Possible Possible SDSR Impossible Possible SDDRH Possible Possible SDDRL Possible Possible SDBPR Possible Possible SDBSR Possible Possible SDIDR Impossible Possible 20.2 External Signals 20.2.1 Test Clock (TCK) The test clock pin (TCK) provides an independent clock supply to the H-UDI. As the clock input to TCK is supplied directly to the H-UDI, a clock waveform with a duty cycle close to 50% should be input (for details, see section 29, Electrical Characteristics). If no signal is input, TCK is fixed at 1 by internal pull-up. 20.2.2 Test Mode Select (TMS) The test mode select pin (TMS) is sampled at the rise of TCK. TMS controls the internal state of the TAP controller. If no signal is input, TMS is fixed at 1 by internal pull-up. 20.2.3 Test Data Input (TDI) The test data input pin (TDI) performs serial input of instructions and data for H-UDI registers. TDI is sampled at the rise of TCK. If no signal is input, TDI is fixed at 1 by internal pull-up. 20.2.4 Test Data Output (TDO) The test data output pin (TDO) performs serial output of instructions and data from H-UDI registers. Transfer is performed in synchronization with TCK. If there is no output, TDO goes to the high-impedance state. 20.2.5 Test Reset (TRST) The test reset pin (TRST) initializes the H-UDI asynchronously. If no signal is input, TRST is fixed at 1 by internal pullup. Rev. 5.00 Feb. 24, 2010 Page 540 of 950 REJ09B0177-0500 20. High-performance User Debug Interface (H-UDI) 20.3 Register Descriptions 20.3.1 Instruction Register (SDIR) Bit: 15 14 13 12 11 10 9 8 TS3 TS2 TS1 TS0 -- -- -- -- Initial value: 1 1 1 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 -- -- -- -- -- -- -- -- Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R The instruction register (SDIR) is a 16-bit register that can only be read by the CPU. H-UDI instructions can be transferred to SDIR by serial input from TDI. SDIR can be initialized by the TRST signal or in software standby mode, but is not initialized by a reset. SDIR defines four valid bits for instruction. If an instruction exceeding four bits is input, the last four bits of the serial data will be stored in SDIR. Operation is not guaranteed if a reserved instruction is set in this register. Bits 15 to 12--Test Set Bits (TS3-TS0): Table 20.4 shows the instruction configuration. Table 20.4 Instruction Configuration Bit 15: TS3 Bit 14: TS2 Bit 13: TS1 Bit 12: TS0 Description 0 0 0 0 EXTEST mode 1 Reserved 0 CLAMP mode 1 HIGHZ mode 0 SAMPLE/PRELOAD mode 1 Reserved 0 Reserved 1 Reserved 0 Reserved 1 Reserved 0 H-UDI interrupt 1 Reserved 0 Reserved 1 Reserved 0 IDCODE mode 1 BYPASS mode 1 1 0 1 1 0 0 1 1 0 1 (Initial value) Bits 11 to 0--Reserved: These bits are always read as 0. The write value should always be 0. Rev. 5.00 Feb. 24, 2010 Page 541 of 950 REJ09B0177-0500 20. High-performance User Debug Interface (H-UDI) 20.3.2 Status Register (SDSR) (SH7058SF) Bit: 15 14 13 12 11 10 9 8 -- -- -- -- -- -- -- -- Initial value: 0 1 0 1 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 -- -- -- -- -- -- -- SDTRF Initial value: 0 0 0 0 0 0 0 1 R/W: R R R R R R R R/W Bit: 15 14 13 12 11 10 9 8 (SH7059F) -- -- -- -- -- -- -- -- Initial value: 0 0 0 0 1 1 1 1 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 -- -- -- -- -- -- -- SDTRF Initial value: 0 0 0 0 0 0 0 1 R/W: R R R R R R R R/W The status register (SDSR) is a 16-bit register that can be read from and written to by the CPU. SDSR output from TDO is possible, but serial data cannot be written to SDSR via TDI. The SDTRF bit is output by means of a 1-bit shift. In the case of a 2-bit shift, the SDTRF bit is first output, followed by a reserved bit. SDSR is initialized by TRST signal input or in software standby mode, but is not initialized by a reset. (SH7058SF) Bits 15, 13, and 11 to 1 are always read as 0, and the write value should always be 0. Bits 14 and 12 are always read as 1, and the write value should always be 1. (SH7059F) Bits 15 to 1--Reserved: Bits 15 to 12 and 7 to 1 are always read as 0, and the write value should always be 0. Bits 11 to 8 are always read as 1, and the write value should always be 1. Bit 0--Serial Data Transfer Control Flag (SDTRF): Indicates whether H-UDI registers can be accessed by the CPU. The SDTRF bit is reset by the TRST signal , but is not initialized by a reset. Bit 0: SDTRF Description 0 Serial transfer to SDDR has ended, and SDDR can be accessed 1 Serial transfer to SDDR in progress Rev. 5.00 Feb. 24, 2010 Page 542 of 950 REJ09B0177-0500 (Initial value) 20. High-performance User Debug Interface (H-UDI) 20.3.3 Data Register (SDDR) The data register (SDDR) comprises data register H (SDDRH) and data register L (SDDRL), each of which has the following configuration. Bit: 15 14 13 12 11 10 9 8 Initial value: -- -- -- -- -- -- -- -- R/W R/W R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 Initial value: -- -- -- -- -- -- -- -- R/W R/W R/W R/W R/W R/W R/W R/W R/W: R/W: SDDRH and SDDRL are 16-bit registers that can be read from and written to by the CPU. SDDR is connected to TDO and TDI for serial data transfer to and from an external device. 32-bit data is input and output in serial data transfer. If data exceeding 32 bits is input, only the last 32 bits will be stored in SDDR. Serial data is input starting from the MSB of SDDR (bit 15 of SDDRH), and output starting from the LSB (bit 0 of SDDRL). This register is not initialized by a reset, or by the TRST signal. 20.3.4 Bypass Register (SDBPR) The bypass register (SDBPR) is a 1-bit shift register. In BYPASS, CLAMP, or HIGHZ mode, SDBPR is connected between TDI and TDO. SDBPR cannot be read or written to by the CPU. 20.3.5 Boundary scan register (SDBSR) The boundary scan register (SDBSR), a shift register that controls the I/O pins of this LSI, is provided on the PAD. Using the EXTEST mode or the SAMPLE/PRELOAD mode, a boundary scan test conforming to the IEEE1149.1 standard can be performed. For SDBSR, read/write by the CPU cannot be performed. Table 20.5 shows the relationship between the pins of the LSI and the boundary scan register. Rev. 5.00 Feb. 24, 2010 Page 543 of 950 REJ09B0177-0500 20. High-performance User Debug Interface (H-UDI) Table 20.5 Correspondence between Pins and Boundary Scan Register Bits Pin No. Pin Name Input/Output Bit No. 238 AUDRST Input 473 240 AUDMD Input 472 241 AUDATA0 Input 471 Output 470 from TDI 242 243 244 245 246 248 250 251 252 253 254 AUDATA1 AUDATA2 AUDATA3 AUDCK AUDSYNC PD0/TOP1A PD1/TIO1B PD2/TIO1C PD3/TIO1D PD4/TIO1E PD5/TIO1F Rev. 5.00 Feb. 24, 2010 Page 544 of 950 REJ09B0177-0500 Output enable 469 Input 468 Output 467 Output enable 466 Input 465 Output 464 Output enable 463 Input 462 Output 461 Output enable 460 Input 459 Output 458 Output enable 457 Input 456 Output 455 Output enable 454 Input 453 Output 452 Output enable 451 Input 450 Output 449 Output enable 448 Input 447 Output 446 Output enable 445 Input 444 Output 443 Output enable 442 Input 441 Output 440 Output enable 439 Input 438 Output 437 Output enable 436 20. High-performance User Debug Interface (H-UDI) Pin No. Pin Name Input/Output Bit No. 255 PD6/TIO1G Input 435 Output 434 Output enable 433 256 1 2 3 4 5 6 7 8 9 10 12 14 PD4/TIO1H PD8/PULS0 PD9/PULS1 Input 432 Output 431 Output enable 430 Input 429 Output 428 Output enable 427 Input 426 Output 425 Output enable 424 Input 423 Output 422 Output enable 421 Input 420 Output 419 Output enable 418 Input 417 Output 416 Output enable 415 PD13/PULS6/ Input 414 HTxD0/HTxD1 Output 413 Output enable 412 Input 411 Output 410 Output enable 409 PD10/PULS2 PD11/PULS3 PD12/PULS4 PE0/A0 PE1/A1 PE2/A2 PE3/A3 PE4/A4 PE5/A5 Input 408 Output 407 Output enable 406 Input 405 Output 404 Output enable 403 Input 402 Output 401 Output enable 400 Input 399 Output 398 Output enable 397 Input 396 Output 395 Output enable 394 Rev. 5.00 Feb. 24, 2010 Page 545 of 950 REJ09B0177-0500 20. High-performance User Debug Interface (H-UDI) Pin No. Pin Name Input/Output Bit No. 15 PE6/A6 Input 393 Output 392 Output enable 391 16 17 18 19 21 23 24 25 26 27 28 29 31 PE4/A7 PE8/A8 PE9/A9 PE10/A10 PE11/A11 PE12/A12 PE13/A13 PE14/A14 PE15/A15 PF0/A16 PF1/A17 PF2/A18 PF3/A19 Rev. 5.00 Feb. 24, 2010 Page 546 of 950 REJ09B0177-0500 Input 390 Output 389 Output enable 388 Input 387 Output 386 Output enable 385 Input 384 Output 383 Output enable 382 Input 381 Output 380 Output enable 379 Input 378 Output 377 Output enable 376 Input 375 Output 374 Output enable 373 Input 372 Output 371 Output enable 370 Input 369 Output 368 Output enable 367 Input 366 Output 365 Output enable 364 Input 363 Output 362 Output enable 361 Input 360 Output 359 Output enable 358 Input 357 Output 356 Output enable 355 Input 354 Output 353 Output enable 352 20. High-performance User Debug Interface (H-UDI) Pin No. Pin Name Input/Output Bit No. 33 PF4/A20 Input 351 Output 350 Output enable 349 34 35 36 37 38 40 42 43 44 45 46 PF5/A21/POD PF6/WRL PF7/WRH PF8/WAIT PF9/RD PF10/CS0 PF1/CS1 PF12/CS2 PF13/CS3 PF14/BACK/SCS0 PF15/BREQ/SCS1 Input 348 Output 347 Output enable 346 Input 345 Output 344 Output enable 343 Input 342 Output 341 Output enable 340 Input 339 Output 338 Output enable 337 Input 336 Output 335 Output enable 334 Input 333 Output 332 Output enable 331 Input 330 Output 329 Output enable 328 Input 327 Output 326 Output enable 325 Input 324 Output 323 Output enable 322 Input 321 Output 320 Output enable 319 Input 318 Output 317 Output enable 316 50 MD2 Input 315 55 MD1 Input 314 56 FWE Input 313 59 MD0 Input 312 Rev. 5.00 Feb. 24, 2010 Page 547 of 950 REJ09B0177-0500 20. High-performance User Debug Interface (H-UDI) Pin No. Pin Name Input/Output Bit No. 63 PH0/D0 Input 311 Output 310 Output enable 309 64 65 66 67 68 69 71 73 74 76 78 79 80 PH1/D1 PH2/D2 PH3/D3 PH4/D4 PH5/D5 PH6/D6 PH7/D7 PH8/D8 PH9/D9 PH10/D10 PH11/D11 PH12/D12 PH13/D13 Rev. 5.00 Feb. 24, 2010 Page 548 of 950 REJ09B0177-0500 Input 308 Output 307 Output enable 306 Input 305 Output 304 Output enable 303 Input 302 Output 301 Output enable 300 Input 299 Output 298 Output enable 297 Input 296 Output 295 Output enable 294 Input 293 Output 292 Output enable 291 Input 290 Output 289 Output enable 288 Input 287 Output2 286 Output enable 285 Input 284 Output 283 Output enable 282 Input 281 Output 280 Output enable 279 Input 278 Output 277 Output enable 276 Input 275 Output 274 Output enable 273 Input 272 Output 271 Output enable 270 20. High-performance User Debug Interface (H-UDI) Pin No. Pin Name Input/Output Bit No. 81 PH14/D14 Input 269 Output 268 Output enable 267 82 PH15/D15 Input 266 Output 265 Output enable 264 84 NMI Input 263 124 WDTOVF Output 262 Output enable 261 Input 260 Output 259 125 127 129 130 131 132 133 134 135 136 PA0/TI0A PA1/TI0B PA2/TI0C PA3/TI0D PA4/TIO3A PA5/TIO3B PA6/TIO3C Output enable 258 Input 257 Output 256 Output enable 255 Input 254 Output 253 Output enable 252 Input 251 Output 250 Output enable 249 Input 248 Output 247 Output enable 246 Input 245 Output 244 Output enable 243 Input 242 Output 241 Output enable 240 Input 239 Output 238 Output enable 237 PA8/TIIO4A Input 236 /ADTO0A Output 235 Output enable 234 PA9/TIO4B Input 233 /ADTO0B Output 232 Output enable 231 PA7/TIO3D Rev. 5.00 Feb. 24, 2010 Page 549 of 950 REJ09B0177-0500 20. High-performance User Debug Interface (H-UDI) Pin No. 137 138 140 142 143 144 145 146 147 149 151 152 153 154 Pin Name Input/Output Bit No. PA10/TIO4C Input 230 /ADTO1A Output 229 Output enable 228 PA11/TIO4D Input 227 /ADTO1B Output 226 Output enable 225 Input 224 Output 223 Output enable 222 Input 221 Output 220 PA12/TIO5A PA13/TIO5B Output enable 219 PA14/TxD0 Input 218 /SSO0 Output 217 Output enable 216 PA15/RxD0 Input 215 /SSI0 Output 214 Output enable 213 Input 212 PB0/TO6A PB1/TO6B PB2/TO6C PB3/TO6D PB4/TO7A/TO8A PB5/TO7B/TO8B PB6/TO7C/TO8C PB7/TO7D/TO8D Rev. 5.00 Feb. 24, 2010 Page 550 of 950 REJ09B0177-0500 Output 211 Output enable 210 Input 209 Output 208 Output enable 207 Input 206 Output 205 Output enable 204 Input 203 Output 202 Output enable 201 Input 200 Output 199 Output enable 198 Input 197 Output 196 Output enable 195 Input 194 Output 193 Output enable 192 Input 191 Output 190 Output enable 189 20. High-performance User Debug Interface (H-UDI) Pin No. Pin Name Input/Output Bit No. 155 PD8/TxD3/TO8E Input 188 Output 187 Output enable 186 156 157 158 159 160 162 164 165 166 167 168 169 170 PB9/RxD3/TO8F Input 185 Output 184 Output enable 183 PB10/TxD4/HTxD0 Input 182 /TO8G Output 181 Output enable 180 PB11/RxD4/HRxD0 Input 179 /TO8H Output 178 Output enable 177 PB12/TCLKA Input 176 /UBCTRG Output 175 Output enable 174 PB13/SCK0 Input 173 /SSCK0 Output 172 Output enable 171 PB14/SCK1/ Input 170 TCLKB/TI10 Output 169 Output enable 168 PB15/PULS5/ Input 167 SCK2/SSCK1 Output 166 Output enable 165 Input 164 Output 163 Output enable 162 PC0/TxD1 PC1/RxD1 PC2/TxD2/SSO1 PC3/RxD2/SSI1 Input 161 Output 160 Output enable 159 Input 158 Output 157 Output enable 156 Input 155 Output 154 Output enable 153 Input 152 Output 151 Output enable 150 PG0/PULS7/ Input 149 HRxD0/HRxD1 Output 148 Output enable 147 PC4/IRQ0 Rev. 5.00 Feb. 24, 2010 Page 551 of 950 REJ09B0177-0500 20. High-performance User Debug Interface (H-UDI) Pin No. Pin Name Input/Output Bit No. 171 PG1/IRQ1 Input 146 Output 145 Output enable 144 173 175 176 177 178 179 180 181 182 183 184 186 188 PG2/IRQ2/ADEND Input 143 Output 142 Output enable 141 PG3/IRQ3/ Input 140 ADTRG0 Output 139 Output enable 138 Input 137 Output 136 PJ0/TIO2A PJ1/TIO2B PJ2/TIO2C PJ3/TIO2D PJ4/TIO2E PJ5/TIO2F PJ6/TIO2G PJ7/TIO2H PJ8/TIO5C PJ9/TIO5D PJ10/TI9A Rev. 5.00 Feb. 24, 2010 Page 552 of 950 REJ09B0177-0500 Output enable 135 Input 134 Output 133 Output enable 132 Input 131 Output 130 Output enable 129 Input 128 Output 127 Output enable 126 Input 125 Output 124 Output enable 123 Input 122 Output 121 Output enable 120 Input 119 Output 118 Output enable 117 Input 116 Output 115 Output enable 114 Input 113 Output 112 Output enable 111 Input 110 Output 109 Output enable 108 Input 107 Output 106 Output enable 105 20. High-performance User Debug Interface (H-UDI) Pin No. Pin Name Input/Output Bit No. 189 PJ11/TI9B Input 104 Output 103 Output enable 102 190 191 192 193 195 197 198 199 200 201 202 204 206 PJ12/TI9C PJ13/TI9D PJ14/TI9E PJ15/TI9F PK0/TO8A PK1/TO8B PK2/TO8C PK3/TO8D PK4/TO8E PK5/TO8F PK6/TO8G PK7/TO8H PK8/TO8I Input 101 Output 100 Output enable 99 Input 98 Output 97 Output enable 96 Input 95 Output 94 Output enable 93 Input 92 Output 91 Output enable 90 Input 89 Output 88 Output enable 87 Input 86 Output 85 Output enable 84 Input 83 Output 82 Output enable 81 Input 80 Output 79 Output enable 78 Input 77 Output 76 Output enable 75 Input 74 Output 73 Output enable 72 Input 71 Output 70 Output enable 69 Input 68 Output 67 Output enable 66 Input 65 Output 64 Output enable 63 Rev. 5.00 Feb. 24, 2010 Page 553 of 950 REJ09B0177-0500 20. High-performance User Debug Interface (H-UDI) Pin No. Pin Name Input/Output Bit No. 207 PK9/TO8J Input 62 Output 61 Output enable 60 208 209 210 211 213 215 216 217 218 219 220 221 222 PK10/TO8K PK11/TO8L PK12/TO8M PK13/TO8N PK14/TO8O PK15/TO8P PL0/TI10 PL1/TIO11A/IRQ6 PL2/TIO11B/IRQ7 PL3/TCLKB PL4/ADTRG0 PL5/ADTRG1 PL6/ADEND Rev. 5.00 Feb. 24, 2010 Page 554 of 950 REJ09B0177-0500 Input 59 Output 58 Output enable 57 Input 56 Output 55 Output enable 54 Input 53 Output 52 Output enable 51 Input 50 Output 49 Output enable 48 Input 47 Output 46 Output enable 45 Input 44 Output 43 Output enable 42 Input 41 Output 40 Output enable 39 Input 38 Output 37 Output enable 36 Input 35 Output 34 Output enable 33 Input 32 Output 31 Output enable 30 Input 29 Output 28 Output enable 27 Input 26 Output 25 Output enable 24 Input 23 Output 22 Output enable 21 20. High-performance User Debug Interface (H-UDI) Pin No. Pin Name Input/Output Bit No. 223 PL7/SCK2/SSCK1 Input 20 Output 19 Output enable 18 224 PL8/SCK3 226 Input 17 Output 16 Output enable 15 Input 14 Output 13 Output enable 12 PL10/HTxD0/ Input 11 HTxD1/HTxD0& Output 10 PL9/SCL4/IRQ5 228 229 230 231 HTxD1 Output enable 9 PL11/HRxD0/ Input 8 HRxD1/HRxD0& Output 7 HRxD1 Output enable 6 PL12/IRQ4/SCS0 Input 5 Output 4 Output enable 3 Input 2 Output 1 Output enable 0 PL13/IRQOUT/SCS1 to TDO 20.3.6 ID code register (SDIDR) The ID code register (SDIDR) is a 32-bit register. In the IDCODE mode, SDIDR outputs a fixed code via TDO. The codes are H'08016447 for the SH7058SF and H'0800B447 for the SH7059F. Serial data cannot be written to SDIDR via TDI. For SDIDR, read/write by the CPU cannot be performed. (SH7058SF) 31 28 0000 27 1000 Version (4 bits) 12 0000 0001 0110 Part Number (16 bits) 11 0100 1 0100 011 Manufacture Identify (11 bits) 0 1 Fixed Code (1 bit) (SH7059F) 31 28 0000 Version (4 bits) 27 1000 12 0000 0000 Part Number (16 bits) 1011 11 0100 1 0100 011 Manufacture Identify (11 bits) 0 1 Fixed Code (1 bit) Rev. 5.00 Feb. 24, 2010 Page 555 of 950 REJ09B0177-0500 20. High-performance User Debug Interface (H-UDI) 20.4 Operation 20.4.1 TAP Controller Figure 20.2 shows the internal states of the TAP controller. State transitions basically conform with the IEEE1149.1 standard. 1 Test-logic-reset 0 Run-test/idle 0 1 1 1 Select-DR-scan Select-IR-scan 0 1 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Capture-IR 0 0 Shift-IR 1 1 Exit1-IR 0 0 Pause-IR 1 0 1 0 0 Exit2-DR 1 Exit2-IR 1 Update-DR 1 0 Update-IR 1 0 Figure 20.2 TAP Controller State Transitions 20.4.2 H-UDI Interrupt and Serial Transfer When an H-UDI interrupt instruction is transferred to SDIR via TDI, an interrupt is generated. Data transfer can be controlled by means of the H-UDI interrupt service routine. Transfer can be performed by means of SDDR. Control of data input/output between an external device and the H-UDI is performed by monitoring the SDTRF bit in SDSR externally and internally. Internal SDTRF bit monitoring is carried out by having SDSR read by the CPU. The H-UDI interrupt and serial transfer procedure is as follows. 1. An instruction is input to SDIR by serial transfer, and an H-UDI interrupt request is generated. 2. After the H-UDI interrupt request is issued, the SDTRF bit in SDSR is monitored externally. After output of SDTRF = 1 from TDO is observed, serial data is transferred to SDDR. 3. On completion of the serial transfer to SDDR, the SDTRF bit is cleared to 0, and SDDR can be accessed by the CPU. After SDDR has been accessed, SDDR serial transfer is enabled by setting the SDTRF bit to 1 in SDSR. 4. Serial data transfer between an external device and the H-UDI can be carried out by constantly monitoring the SDTRF bit in SDSR externally and internally. Rev. 5.00 Feb. 24, 2010 Page 556 of 950 REJ09B0177-0500 20. High-performance User Debug Interface (H-UDI) Figures 20.3, 20.4, and 20.5 show the timing of data transfer between an external device and the H-UDI. Instruction SDTRF 1 Serial data Input/ output Input 0 1 H-UDI interrupt request Shift disabled SDTRF (in SDSR)*1 Shift enabled Shift enabled SDSR and SDDR MUX*2 SDDR access state SDSR Shift SDDR SDDR SDSR CPU Shift CPU SDSR serial transfer (monitoring) Notes: 1. SDTRF flag (in SDSR): Indicates whether SDDR access by the CPU or serial transfer data input/output to SDDR is possible. 1 SDDR is shift-disabled. SDDR access by the CPU is enabled. 2 SDDR is shift-enabled. Do not access SDDR until SDTRF = 0. Conditions: * SDTRF = 1 -- When TRST = 0 -- When the CPU writes 1 -- In BYPASS mode * SDTRF = 0 -- End of SDDR shift access in serial transfer 2. SDSR/SDDR (Update-DR state) internal MUX switchover timing * Switchover from SDSR to SDDR: On completion of serial transfer in which SDTRF = 1 is output from TDO * Switchover from SDDR to SDSR: On completion of serial transfer to SDDR Figure 20.3 Data Input/Output Timing Chart (1) Rev. 5.00 Feb. 24, 2010 Page 557 of 950 REJ09B0177-0500 20. High-performance User Debug Interface (H-UDI) Test-Logic-Reset Update-DR Run-Test/Idle Exit1-DR Shift-DR Capture-DR Select-DR Update-IR Exit1-IR Shift-IR Select-IR Capture-IR Select-DR Test-Logic-Reset Run-Test/Idle TCK TMS TS0 TS3 TDI TDO SDTRF Figure 20.4 Data Input/Output Timing Chart (2) Exit1-DR Update-DR Shift-DR Capture-DR Select-DR Update-DR Exit1-DR Shift-DR Capture-DR Select-DR Exit1-DR Update-DR Shift-DR Select-DR Capture-DR Update-DR Shift-DR Exit1-DR Select-DR Capture-DR TCK TMS Bit 31 Bit 0 Bit 31 Bit 0 TDI Bit 0 TDO SDTRF Bit 31 Bit 0 Bit 31 SDTRF Figure 20.5 Data Input/Output Timing Chart (3) 20.4.3 H-UDI Reset The H-UDI can be reset in the following cases. * * * * * When the TRST signal is held at 0. When TRST = 1 and at least five TCK clock cycles are input while TMS = 1. When the MSTOP2 bit in SYSCR2 is set to 1 (see section 27.2.3 System Control Register 2 (SYSCR2)). In hardware standby mode. In software standby mode. Rev. 5.00 Feb. 24, 2010 Page 558 of 950 REJ09B0177-0500 20. High-performance User Debug Interface (H-UDI) 20.5 Boundary Scan The H-UDI pins can be placed in the boundary scan mode stipulated by IEEE1149.1 by setting a command in SDIR. 20.5.1 Supported Instructions This LSI supports the three essential instructions defined in IEEE1149.1 (BYPASS, SAMPLE/PRELOAD, and EXTEST) and optional instructions (CLAMP, HIGHZ, and IDCODE). BYPASS: The BYPASS instruction is an essential standard instruction that operates the bypass register. This instruction shortens the shift path to speed up serial data transfer involving other chips on the printed circuit board. While this instruction is executing, the test circuit has no effect on the system circuits. The instruction code is 1111. SAMPLE/PRELOAD: The SAMPLE/PRELOAD instruction inputs values from this LSI's internal circuitry to the boundary scan register, outputs values from the scan path, and loads data onto the scan path. When this instruction is executing, this LSI's input pin signals are transmitted directly to the internal circuitry, and internal circuit values are directly output externally from the output pins. This LSI's system circuits are not affected by execution of this instruction. The instruction code is 0100. In a SAMPLE operation, a snapshot of a value to be transferred from an input pin to the internal circuitry, or a value to be transferred from the internal circuitry to an output pin, is latched into the boundary scan register and read from the scan path. Snapshot latching does not affect normal operation of this LSI. In a PRELOAD operation, an initial value is set in the parallel output latch of the boundary scan register from the scan path prior to the EXTEST instruction. Without a PRELOAD operation, when the EXTEST instruction was executed an undefined value would be output from the output pin until completion of the initial scan sequence (transfer to the output latch) (with the EXTEST instruction, the parallel output latch value is constantly output to the output pin). EXTEST: This instruction is provided to test external circuitry when this LSI is mounted on a printed circuit board. When this instruction is executed, output pins are used to output test data (previously set by the SAMPLE/PRELOAD instruction) from the boundary scan register to the printed circuit board, and input pins are used to latch test results into the boundary scan register from the printed circuit board. If testing is carried out by using the EXTEST instruction N times, the Nth test data is scanned-in when test data (N-1) is scanned out. Data loaded into the output pin boundary scan register in the Capture-DR state is not used for external circuit testing (it is replaced by a shift operation). The instruction code is 0000. CLAMP: When the CLAMP instruction is enabled, the output pin outputs the value of the boundary scan register that has been set by the SAMPLE/PRELOAD instruction. While the CLAMP instruction is enabled, the state of the boundary scan register maintains the previous state regardless of the state of the TAP controller. A bypass register is connected between TDI and TDO. The related circuit operates in the same way when the BYPASS instruction is enabled. The instruction code is 0010. HIGHZ: When the HIGHZ instruction is enabled, all output pins enter a high-impedance state. While the HIGHZ instruction is enabled, the state of the boundary scan register maintains the previous state regardless of the state of the TAP controller. A bypass register is connected between TDI and TDO. The related circuit operates in the same way when the BYPASS instruction is enabled. Rev. 5.00 Feb. 24, 2010 Page 559 of 950 REJ09B0177-0500 20. High-performance User Debug Interface (H-UDI) The instruction code is 0011. IDCODE: When the IDCODE instruction is enabled, the value of the ID code register is output from TDO with LSB first when the TAP controller is in the Shift-DR state. While this instruction is being executed, the test circuit does not affect the system circuit. When the TAP controller is in the Test-Logic-Reset state, the instruction register is initialized to the IDCODE instruction. The instruction code is 1110. 20.5.2 Notes on Use 1. 2. 3. 4. 5. Boundary scan mode does not cover clock-related signals (EXTAL, XTAL, CK, PLLCAP). Boundary scan mode does not cover reset-related signals (RES, HSTBY). Boundary scan mode does not cover H-UDI-related signals (TCK, TDI, TDO, TMS, TRST). Boundary scan mode does not cover A/D-converter-related signals (AD0 to AN31). While the HIGHZ instruction is being executed, the pull-up/pull-down settings of the AUD-related pins (AUDATA3 to ADUATA0, AUDCK, and AUDSYNC) are valid. 6. While the SAMPLE/PRELOAD instruction is being executed during the AUD reset (while AUDRST = low), the latched input values of the AUDSYNC and AUDATA0 to AUDATA3 pins are fixed high. 7. While the SAMPLE/PRELOAD instruction is being executed during the reset state (while RES = low), the following restrictions are put on I/O port pins. The output values of PF6, PF7, PF9, and PF10 pins are fixed high in MCU extended mode. Other port F pins and the port E and port H pins can latch input signals. The input values of other pins are fixed high. 8. While the EXTEST instruction is being executed during the reset state (while RES = low), the following restrictions are put on I/O port pins. PE0 to PE15, PF0 to PF7, PF9, and PF10 pins can be output. Port E, port F, and port H pins can be input. However, the output values of PF6, PF7, PF9, and PF10 pins are fixed high in MCU extended mode. The output settings for other pins are invalid, and their input values are fixed high. 9. While the CLAMP instruction is beign executed during the reset state (while RES = low), the following restrictions are put on I/O port pins. Only PE0 to PE15, PF0 to PF7, PF9, and PF10 pins can be output. However, the output values of PF6, PF7, PF9, and PF10 pins are fixed high in MCU extended mode. The output settings for other pins are invalid, and their input values are fixed high. 10. While the HIGHZ instruction is being executed during the reset state (while RES = low), the following restrictions are put on I/O port pins. The output values of PF6, PF7, PF9, and PF10 pins are fixed high, and the HIGHZ instruction is invalid. Rev. 5.00 Feb. 24, 2010 Page 560 of 950 REJ09B0177-0500 20. High-performance User Debug Interface (H-UDI) 20.6 Usage Notes * A reset must always be executed by driving the TRST signal to 0, regardless of whether or not the H-UDI is to be activated. TRST must be held low for 20 TCK clock cycles. For details, see section 29, Electrical Characteristics. * The registers are not initialized in software standby mode. If TRST is set to 0 in software standby mode, IDCODE mode will be entered. * The frequency of TCK must be lower than that of the peripheral module clock (P). For details, see section 29, Electrical Characteristics. * In serial data transfer, data input/output starts with the LSB. Figure 20.6 shows serial data input/output. * When data that exceeds the number of bits of the register connected between TDI and TDO is serially transferred, the serial data that exceeds the number of register bits and output from TDO is the same as that input from TDI. * If the H-UDI serial transfer sequence is disrupted, a TRST reset must be executed. Transfer should then be retried, regardless of the transfer operation. * TDO is output at the falling edge of TCK when one of six instructions defined in IEEE1149.1 is selected. Otherwise, it is output at the rising edge of TCK. * SDIR and SDSR serial data input/output In Capture-IR, SDIR and SDSR are captured into the shift register, and in Shift-IR bits 0 to 15 of SDSR and bits 0 to 15 of SDIR are output in that order from TDO. In Update-IR, data input from TDI is written to SDIR, but not to SDSR. TDI TDI Bit 31 Shift register SDIR Bit 0 Bit 15 Bit 15 . . . Bit 0 Bit 31 Shift register Bit 15 . . . SDIR Bit 16 SDSR TDO Bit 15 . . . TDI input data Bit 16 SDIR Bit 0 Bit 15 SDSR SDSR Bit 0 Bit 0 Capture-IR TDO Update-IR Figure 20.6 Serial Data Input/Output (1) Rev. 5.00 Feb. 24, 2010 Page 561 of 950 REJ09B0177-0500 20. High-performance User Debug Interface (H-UDI) * SDDRH and SDDRL serial data input/output (1) In H-UDI interrupt mode, before SDTRF = 1 is read from TDO when an H-UDI interrupt is generated, SDSR and SDIR are captured into the shift register in Capture-DR, and in Shift-DR bits 0 to 15 of SDSR and bits 0 to 15 of SDIR are output in that order from TDO. In Update-DR, TDI input data is not written to any register. TDI Bit 31 Shift register Bit 15 . . . SDIR Bit 16 Bit 15 Bit 15 . . . SDSR Bit 0 TDO SDIR Bit 0 SDSR Bit 0 Capture-DR (2) In H-UDI interrupt mode, after SDTRF = 1 is read from TDO when an H-UDI interrupt is generated, SDDRH and SDDRL are captured into the shift register in Capture-DR, and in Shift-DR bits 0 to 15 of SDDRL and bits 0 to 15 of SDDRH are output in that order from TDO. Data input from TDI is written to SDDRH and SDDRL in Update-DR. TDI TDI Bit 31 Shift register SDDRH Bit 0 Bit 15 Bit 15 . . . Bit 0 Bit 31 Shift register TDI input data Bit 0 Figure 20.6 Serial Data Input/Output (2) Rev. 5.00 Feb. 24, 2010 Page 562 of 950 REJ09B0177-0500 Bit 16 Bit 0 Bit 15 . . . Bit 0 TDO SDDRH Bit 15 SDDRL Capture-DR Bit 15 . . . SDDRH Bit 16 SDDRL TDO Bit 15 . . . SDDRL Bit 0 Update-DR 20. High-performance User Debug Interface (H-UDI) * SDIDR serial data input/output In IDCODE mode, SDIDR is captured into the shift register in Capture-DR, and in Shift-DR bits 0 to 31 of SDIDR are output in that order from TDO. In Update-DR, data input from TDI is not written to any register. TDI Bit 31 Shift register . . . . SDIDR Bit 0 TDO Bit 31 SDIDR Bit 0 Capture-DR Figure 20.6 Serial Data Input/Output (3) Rev. 5.00 Feb. 24, 2010 Page 563 of 950 REJ09B0177-0500 20. High-performance User Debug Interface (H-UDI) Rev. 5.00 Feb. 24, 2010 Page 564 of 950 REJ09B0177-0500 21. Advanced User Debugger (AUD) Section 21 Advanced User Debugger (AUD) 21.1 Overview This LSI has an on-chip advanced user debugger (AUD). Use of the AUD simplifies the construction of a simple emulator, with functions such as acquisition of branch trace data and monitoring/tuning of on-chip RAM data. 21.1.1 Features The AUD has the following features: * Eight input/output pins Data bus (AUDATA3-AUDATA0) AUD reset (AUDRST) AUD sync signal (AUDSYNC) AUD clock (AUDCK) AUD mode (AUDMD) * Two modes Branch trace mode or RAM monitor mode can be selected by switching AUDMD. Branch trace mode When the PC branches on execution of a branch instruction or generation of an interrupt in the user program, the branch is detected by the AUD and the branch destination address is output from AUDATA. The address is compared with the previously output address, and 4-, 8-, 16-, or 32-bit output is selected automatically according to the upper address matching status. RAM monitor mode When an address is written to AUDATA from off-chip, the data corresponding to that address is output. If an address and data are written to AUDATA, the data is transferred to that address. 21.1.2 Block Diagram Figure 21.1 shows a block diagram of the AUD. Internal bus AUDATA0 PC output circuit On-chip memory AUDATA1 AUDATA2 Address buffer AUDATA3 Peripheral module bus Bus controller Data buffer AUDMD AUDCK On-chip peripheral module Mode control CPU Figure 21.1 AUD Block Diagram Rev. 5.00 Feb. 24, 2010 Page 565 of 950 REJ09B0177-0500 21. Advanced User Debugger (AUD) 21.2 Pin Configuration Table 21.1 shows the AUD's input/output pins. Table 21.1 AUD Pins Function Name Abbreviation AUD data AUDATA3-AUDATA0 Branch destination address output Monitor address/data input/output AUD reset AUDRST AUD reset input AUD reset input AUD mode AUDMD Mode select input (L) Mode select input (H) AUD clock AUDCK Serial clock (P) output Serial clock input AUD sync signal AUDSYNC Data start position identification signal output Data start position identification signal input 21.2.1 Branch Trace Mode RAM Monitor Mode Pin Descriptions Pins Used in Both Modes Pin Description AUDMD The mode is selected by changing the input level at this pin. Low: Branch trace mode High: RAM monitor mode The input at this pin should be changed when AUDRST is low. When no connection is made, this pin is pulled up internally. AUDRST The AUD's internal buffers and logic are initialized by inputting a low level to this pin. When this signal goes low, the AUD enters the reset state and the AUD's internal buffers and logic are reset. When AUDRST goes high again after the AUDMD level settles, the AUD starts operating in the selected mode. When no connection is made, this pin is pulled down internally. Rev. 5.00 Feb. 24, 2010 Page 566 of 950 REJ09B0177-0500 21. Advanced User Debugger (AUD) Pin Functions in Branch Trace Mode Pin Description AUDCK This pin outputs the peripheral module operating frequency (P). This is the clock for AUDATA synchronization. AUDSYNC This pin indicates whether output from AUDATA is valid. High: Valid data is not being output Low: An address is being output AUDATA3 to AUDATA0 1. When AUDSYNC is low When a program branch or interrupt branch occurs, the AUD asserts AUDSYNC and outputs the branch destination address. The output order is A3-A0, A7-A4, A11-A8, A15-A12, A19-A16, A23-A20, A27-A24, A31-A28. 2. When AUDSYNC is high When waiting for branch destination address output, these pins constantly output 0011. When an branch occurs, AUDATA3-AUDATA2 output 10, and AUDATA1-AUDATA0 indicate whether a 4-, 8-, 16-, or 32-bit address is to be output by comparing the previous fully output address with the address output this time (see table below). AUDATA1, AUDATA0 00 Address bits A31-A4 match; 4 address bits A3-A0 are to be output (i.e. output is performed once). 01 Address bits A31-A8 match; 8 address bits A3-A0 and A7-A4 are to be output (i.e. output is performed twice). 10 Address bits A31-A16 match; 16 address bits A3-A0, A7-A4, A11- A8, and A15-A12 are to be output (i.e. output is performed four times). 11 None of the above cases applies; 32 address bits A3-A0, A7-A4, A11-A8, and A15-A12, A19-A16, A23-A20, A27-A24, and A31-A28 are to be output (i.e. output is performed eight times). Pin Functions in RAM Monitor Mode Pin Description AUDCK The external clock input pin. Input the clock to be used for debugging to this pin. The input frequency must not exceed 1/8 of the internal operating frequency (). When no connection is made, this pin is pulled up internally. AUDSYNC Do not assert this pin until a command is input to AUDATA from off-chip and the necessary data can be prepared. See the protocol description for details. When no connection is made, this pin is pulled up internally. AUDATA3 to AUDATA0 When a command is input from off-chip, data is output after Ready reception. Output starts when AUDSYNC is negated. See the protocol description for details. When no connections are made, these pins are pulled up internally. Rev. 5.00 Feb. 24, 2010 Page 567 of 950 REJ09B0177-0500 21. Advanced User Debugger (AUD) 21.3 Branch Trace Mode 21.3.1 Overview In this mode, the branch destination address is output when a branch occurs in the user program. Branches may be caused by branch instruction execution or interrupt/exception processing, but no distinction is made between the two in this mode. 21.3.2 Operation Operation starts in branch trace mode when AUDRST is asserted, AUDMD is driven low, then AUDRST is negated*. Figure 21.2 shows an example of data output. While the user program is being executed without branches, the AUDATA pins constantly output 0011 in synchronization with AUDCK. When a branch occurs, after execution starts at the branch destination address in the PC, the previous fully output address (i.e. for which output was not interrupted by the occurrence of another branch) is compared with the current branch address, and depending on the result, AUDSYNC is asserted and the branch destination address is output after AUDCKbased 1-clock output of 1000 (in the case of 4-bit output), 1001 (8-bit output), 1010 (16-bit output), or 1011 (32-bit output) from the AUDATA pins. On completion of the cycle in which the address is output, AUDSYNC is negated and 0011 is output from the AUDATA pins. If another branch occurs during branch destination address output, the later branch has priority for output. In this case, AUDSYNC is negated and the AUDATA pins output the address after outputting 10xx again (figure 21.3 shows an example of the output when consecutive branches occur). Note that the compared address is the previous fully output address, and not an interrupted address (since the upper address of an interrupted address will be unknown). The interval from the start of execution at the branch destination address in the PC until the AUDATA pins output 10xx is 1.5 or 2 AUDCK cycles. Start of execution at branch destination address in PC AUDCK AUDATA [3:0] 0011 0011 1011 A3-A0 A7-A4 A11-A8 A15-A12 A19-A16 A23-A20 A27-A24 A31-A28 Figure 21.2 Example of Data Output (32-Bit Output)* Rev. 5.00 Feb. 24, 2010 Page 568 of 950 REJ09B0177-0500 0011 21. Advanced User Debugger (AUD) Start of execution at branch destination address in PC (1) Start of execution at branch destination address in PC (2) AUDCK AUDATA [3:0] 0011 0011 1011 A3-A0 A7-A4 1010 A3-A0 A7-A4 A11-A8 A15-A12 0011 0011 Figure 21.3 Example of Output in Case of Successive Branches* Note: * For details on the AUD reset timing and the timing in branch trace mode, refer to section 29.3.13, AUD Timing. 21.4 RAM Monitor Mode 21.4.1 Overview In this mode, all the modules connected to this LSI's internal or external bus can be read and written to, allowing RAM monitoring and tuning to be carried out. 21.4.2 Communication Protocol The AUD latches the AUDATA input when AUDSYNC is asserted. The following AUDATA input format should be used. Input format 0000 DIR A3-A0 Command . . . . . . A31-A28 D3-D0 Address Bit 3 Bit 2 Fixed at 1 0: Read 1: Write . . . . . . Dn-Dn-3 Data (in case of write only) B write: n = 7 W write: n = 15 L write: n = 31 Bit 1 Bit 0 00: Byte 01: Word 10: Longword Spare bits (4 bits): b'0000 Figure 21.4 AUDATA Input Format Rev. 5.00 Feb. 24, 2010 Page 569 of 950 REJ09B0177-0500 21. Advanced User Debugger (AUD) 21.4.3 Operation Operation starts in RAM monitor mode when AUDMD is driven high after AUDRST has been asserted, then AUDRST is negated*. Figure 21.5 shows an example of a read operation, and figure 21.6 an example of a write operation. When AUDSYNC is asserted, input from the AUDATA pins begins. When a command, address, or data (writing only) is input in the format shown in figure 21.2, execution of read/write access to the specified address is started. During internal execution, the AUD returns Not Ready (0000). When execution is completed, the Ready flag (0001) is returned (figures 21.5 and 21.6). Table 21.2 shows the Ready flag format. In a read, data of the specified size is output when AUDSYNC is negated following detection of this flag (figure 21.7). If a command other than the above is input in DIR, the AUD treats this as a command error, disables processing, and sets bit 1 in the Ready flag to 1. If a read/write operation initiated by the command specified in DIR causes a bus error, the AUD disables processing and sets bit 2 in the Ready flag to 1 (figure 21.7). Table 21.2 Ready Flag Format Bit 3 Fixed at 0 Bit 2 Bit 1 Bit 0 0: Normal status 0: Normal status 0: Not ready 1: Bus error 1: Bus error 1: Ready Bus error conditions are shown below. 1. 2. 3. 4. Word access to address 4n+1 or 4n+3 Longword access to address 4n+1, 4n+2, or 4n+3 Longword access to on-chip I/O 8-bit space Access to external space in single-chip mode AUDCK Input/output switchover AUDATAn 0000 1000 A3-A0 A31-A28 DIR 0000 0001 Not ready Ready 0001 Input 0001 D3-D0 D7-D4 Ready Ready Output Figure 21.5 Example of Read Operation (Byte Read)* AUDCK Input/output switchover AUDATAn 0000 1110 A3-A0 A31-A28 DIR Input D3-D0 D31-D28 0000 0001 Not ready Ready Output Figure 21.6 Example of Write Operation (Longword Write)* Rev. 5.00 Feb. 24, 2010 Page 570 of 950 REJ09B0177-0500 0001 0001 Ready Ready 21. Advanced User Debugger (AUD) AUDCK Input/output switchover AUDATAn 0000 1010 A3-A0 DIR A31-A28 0000 0101 Not ready Ready (Bus error) Input 0101 Ready 0101 Ready (Bus error) (Bus error) Output Figure 21.7 Example of Error Occurrence (Longword Read)* Note: * For details on the AUD reset timing and the timing in branch trace mode, refer to section 29.3.13, AUD Timing. 21.5 Usage Notes 21.5.1 Initialization The debugger's internal buffers and processing states are initialized in the following cases: 1. 2. 3. 4. 5. 6. In a power-on reset In hardware standby mode In software standby mode When AUDRST is driven low When the AUDSRST bit is set to 1 in the SYSCR1 register (see section 27.2.2 System Control Register 1 (SYSCR1)) When the MSTOP3 bit is set to 1 in the SYSCR2 register (see section 27.2.3 System Control Register 2 (SYSCR2)) Rev. 5.00 Feb. 24, 2010 Page 571 of 950 REJ09B0177-0500 21. Advanced User Debugger (AUD) Rev. 5.00 Feb. 24, 2010 Page 572 of 950 REJ09B0177-0500 22. Pin Function Controller (PFC) Section 22 Pin Function Controller (PFC) 22.1 Overview The pin function controller (PFC) consists of registers for selecting multiplex pin functions and their input/output direction. Table 22.1 shows this LSI's multiplex pins. Table 22.1 Multiplex Pins Port Function 1 (Related Module) Function 2 (Related Module) A PA0 input/output (port) TI0A input (ATU-II) A PA1 input/output (port) TI0B input (ATU-II) A PA2 input/output (port) TI0C input (ATU-II) Function 3 (Related Module) Function 4 (Related Module) A PA3 input/output (port) TI0D input (ATU-II) A PA4 input/output (port) TIO3A input/output (ATU-II) A PA5 input/output (port) TIO3B input/output (ATU-II) A PA6 input/output (port) TIO3C input/output (ATU-II) A PA7 input/output (port) TIO3D input/output (ATU-II) A PA8 input/output (port) TIO4A input/output (ATU-II) A PA9 input/output (port) TIO4B input/output (ATU-II) ADTO0B output (MTAD) A PA10 input/output (port) TIO4C input/output (ATU-II) ADTO1A output (MTAD) ADTO1B output (MTAD) ADTO0A output (MTAD) A PA11 input/output (port) TIO4D input/output (ATU-II) A PA12 input/output (port) TIO5A input/output (ATU-II) A PA13 input/output (port) TIO5B input/output (ATU-II) A PA14 input/output (port) TxD0 output (SCI) SSO0 output (SSU*) A PA15 input/output (port) RxD0 input (SCI) SSI0 input (SSU*) B PB0 input/output (port) TO6A output (ATU-II) B PB1 input/output (port) TO6B output (ATU-II) B PB2 input/output (port) TO6C output (ATU-II) B PB3 input/output (port) TO6D output (ATU-II) B PB4 input/output (port) TO7A output (ATU-II) TO8A output (ATU-II) B PB5 input/output (port) TO7B output (ATU-II) TO8B output (ATU-II) B PB6 input/output (port) TO7C output (ATU-II) TO8C output (ATU-II) B PB7 input/output (port) TO7D output (ATU-II) TO8D output (ATU-II) B PB8 input/output (port) TxD3 output (SCI) TO8E output (ATU-II) B PB9 input/output (port) RxD3 input (SCI) TO8F output (ATU-II) B PB10 input/output (port) TxD4 output (SCI) HTxD0 output (HCAN-II) TO8G output (ATU-II) TO8H output (ATU-II) B PB11 input/output (port) RxD4 input (SCI) HRxD0 input (HCAN-II) B PB12 input/output (port) TCLKA input (ATU-II) UBCTRG output (UBC) B PB13 input/output (port) SCK0 input/output (SCI) SSCK0 output (SSU*) B PB14 input/output (port) SCK1 input/output (SCI) TCLKB input (ATU-II) TI10 input (ATU-II) B PB15 input/output (port) PULS5 output (APC) SCK2 input/output (SCI) SSCK1 output (SSU*) C PC0 input/output (port) TxD1 output (SCI) C PC1 input/output (port) RxD1 input (SCI) C PC2 input/output (port) TxD2 output (SCI) SSO1 output (SSU*) C PC3 input/output (port) RxD2 input (SCI) SSI1 input (SSU*) Rev. 5.00 Feb. 24, 2010 Page 573 of 950 REJ09B0177-0500 22. Pin Function Controller (PFC) Port Function 1 (Related Module) Function 2 (Related Module) C PC4 input/output (port) IRQ0 input (INTC) D PD0 input/output (port) TIO1A input/output (ATU-II) D PD1 input/output (port) TIO1B input/output (ATU-II) D PD2 input/output (port) TIO1C input/output (ATU-II) D PD3 input/output (port) TIO1D input/output (ATU-II) D PD4 input/output (port) TIO1E input/output (ATU-II) D PD5 input/output (port) TIO1F input/output (ATU-II) D PD6 input/output (port) TIO1G input/output (ATU-II) D PD7 input/output (port) TIO1H input/output (ATU-II) D PD8 input/output (port) PULS0 output (APC) D PD9 input/output (port) PULS1 output (APC) D PD10 input/output (port) PULS2 output (APC) D PD11 input/output (port) PULS3 output (APC) D PD12 input/output (port) PULS4 output (APC) D PD13 input/output (port) PULS6 output (APC) E PE0 input/output (port) A0 output (BSC) E PE1 input/output (port) A1 output (BSC) E PE2 input/output (port) A2 output (BSC) E PE3 input/output (port) A3 output (BSC) E PE4 input/output (port) A4 output (BSC) E PE5 input/output (port) A5 output (BSC) E PE6 input/output (port) A6 output (BSC) E PE7 input/output (port) A7 output (BSC) E PE8 input/output (port) A8 output (BSC) E PE9 input/output (port) A9 output (BSC) E PE10 input/output (port) A10 output (BSC) E PE11 input/output (port) A11 output (BSC) E PE12 input/output (port) A12 output (BSC) E PE13 input/output (port) A13 output (BSC) E PE14 input/output (port) A14 output (BSC) E PE15 input/output (port) A15 output (BSC) F PF0 input/output (port) A16 output (BSC) F PF1 input/output (port) A17 output (BSC) F PF2 input/output (port) A18 output (BSC) F PF3 input/output (port) A19 output (BSC) F PF4 input/output (port) A20 output (BSC) F PF5 input/output (port) A21 output (BSC) F PF6 input/output (port) WRL output (BSC) F PF7 input/output (port) WRH output (BSC) F PF8 input/output (port) WAIT input (BSC) F PF9 input/output (port) RD output (BSC) F PF10 input/output (port) CS0 output (BSC) F PF11 input/output (port) CS1 output (BSC) F PF12 input/output (port) CS2 output (BSC) Rev. 5.00 Feb. 24, 2010 Page 574 of 950 REJ09B0177-0500 Function 3 (Related Module) Function 4 (Related Module) HTxD0 output (HCAN-II) HTxD1 output (HCAN-II) POD input (port) 22. Pin Function Controller (PFC) Port Function 1 (Related Module) Function 2 (Related Module) F PF13 input/output (port) CS3 output (BSC) F PF14 input/output (port) BACK output (BSC) F PF15 input/output (port) BREQ input (BSC) SCS1 input/output (SSU*) G PG0 input/output (port) PULS7 output (APC) HRxD0 input (HCAN-II) G PG1 input/output (port) IRQ1 input (INTC) G PG2 input/output (port) IRQ2 input (INTC) ADEND output (A/D) G PG3 input/output (port) IRQ3 input (INTC) ADTRG0 input (A/D) H PH0 input/output (port) D0 input/output (BSC) H PH1 input/output (port) D1 input/output (BSC) H PH2 input/output (port) D2 input/output (BSC) H PH3 input/output (port) D3 input/output (BSC) H PH4 input/output (port) D4 input/output (BSC) H PH5 input/output (port) D5 input/output (BSC) H PH6 input/output (port) D6 input/output (BSC) H PH7 input/output (port) D7 input/output (BSC) H PH8 input/output (port) D8 input/output (BSC) H PH9 input/output (port) D9 input/output (BSC) H PH10 input/output (port) D10 input/output (BSC) H PH11 input/output (port) D11 input/output (BSC) H PH12 input/output (port) D12 input/output (BSC) H PH13 input/output (port) D13 input/output (BSC) H PH14 input/output (port) D14 input/output (BSC) H PH15 input/output (port) D15 input/output (BSC) J PJ0 input/output (port) TIO2A input/output (ATU-II) J PJ1 input/output (port) TIO2B input/output (ATU-II) J PJ2 input/output (port) TIO2C input/output (ATU-II) J PJ3 input/output (port) TIO2D input/output (ATU-II) J PJ4 input/output (port) TIO2E input/output (ATU-II) J PJ5 input/output (port) TIO2F input/output (ATU-II) J PJ6 input/output (port) TIO2G input/output (ATU-II) J PJ7 input/output (port) TIO2H input/output (ATU-II) J PJ8 input/output (port) TIO5C input/output (ATU-II) J PJ9 input/output (port) TIO5D input/output (ATU-II) J PJ10 input/output (port) TI9A input (ATU-II) J PJ11 input/output (port) TI9B input (ATU-II) J PJ12 input/output (port) TI9C input (ATU-II) J PJ13 input/output (port) TI9D input (ATU-II) J PJ14 input/output (port) TI9E input (ATU-II) J PJ15 input/output (port) TI9F input (ATU-II) K PK0 input/output (port) TO8A output (ATU-II) K PK1 input/output (port) TO8B output (ATU-II) K PK2 input/output (port) TO8C output (ATU-II) K PK3 input/output (port) TO8D output (ATU-II) Function 3 (Related Module) Function 4 (Related Module) SCS0 input/output (SSU*) HRxD1 input (HCAN-II) Rev. 5.00 Feb. 24, 2010 Page 575 of 950 REJ09B0177-0500 22. Pin Function Controller (PFC) Port Function 1 (Related Module) Function 2 (Related Module) Function 3 (Related Module) K PK4 input/output (port) TO8E output (ATU-II) K PK5 input/output (port) TO8F output (ATU-II) K PK6 input/output (port) TO8G output (ATU-II) K PK7 input/output (port) TO8H output (ATU-II) K PK8 input/output (port) TO8I output (ATU-II) K PK9 input/output (port) TO8J output (ATU-II) K PK10 input/output (port) TO8K output (ATU-II) K PK11 input/output (port) TO8L output (ATU-II) K PK12 input/output (port) TO8M output (ATU-II) K PK13 input/output (port) TO8N output (ATU-II) K PK14 input/output (port) TO8O output (ATU-II) K PK15 input/output (port) TO8P output (ATU-II) L PL0 input/output (port) TI10 input (ATU-II) L PL1 input/output (port) TIO11A input/output (ATU-II) IRQ6 input (INTC) L PL2 input/output (port) TIO11B input/output (ATU-II) IRQ7 input (INTC) L PL3 input/output (port) TCLKB input (ATU-II) L PL4 input/output (port) ADTRG0 input (A/D) L PL5 input/output (port) ADTRG1 input (A/D) L PL6 input/output (port) ADEND output (A/D) L PL7 input/output (port) SCK2 input/output (SCI) L PL8 input/output (port) SCK3 input/output (SCI) Function 4 (Related Module) SSCK1 output (SSU*) L PL9 input/output (port) SCK4 input/output (SCI) IRQ5 input (INTC) L PL10 input/output (port) HTxD0 output (HCAN-II) HTxD1 output (HCAN-II) HTxD0 & HTxD1 (HCAN-II) L PL11 input/output (port) HRxD0 input (HCAN-II) HRxD1 input (HCAN-II) HRxD0 & HRxD1 (HCAN-II) L PL12 input/output (port) IRQ4 input (INTC) SCS0 input/output (SSU*) PL13 input/output (port) IRQOUT output (INTC) IRQOUT output (INTC) L Note: * SSU: Synchronous Serial Communication Unit Rev. 5.00 Feb. 24, 2010 Page 576 of 950 REJ09B0177-0500 SCS1 input/output (SSU*) 22. Pin Function Controller (PFC) 22.2 Register Configuration PFC registers are listed in table 22.2. Table 22.2 PFC Registers Name Abbreviation R/W Initial Value Address Access Size Port A IO register PAIOR R/W H'0000 H'FFFFF720 8, 16 Port A control register H PACRH R/W H'0000 H'FFFFF722 8, 16 Port A control register L PACRL R/W H'0000 H'FFFFF724 8, 16 Port B IO register PBIOR R/W H'0000 H'FFFFF730 8, 16 Port B control register H PBCRH R/W H'0000 H'FFFFF732 8, 16 Port B control register L PBCRL R/W H'0000 H'FFFFF734 8, 16 Port B invert register PBIR R/W H'0000 H'FFFFF736 8, 16 Port C IO register PCIOR R/W H'0000 H'FFFFF73A 8, 16 Port C control register PCCR R/W H'0000 H'FFFFF73C 8, 16 Port D IO register PDIOR R/W H'0000 H'FFFFF740 8, 16 Port D control register H PDCRH R/W H'0000 H'FFFFF742 8, 16 Port D control register L PDCRL R/W H'0000 H'FFFFF744 8, 16 Port E IO register PEIOR R/W H'0000 H'FFFFF750 8, 16 Port E control register PECR R/W H'0000 H'FFFFF752 8, 16 Port F IO register PFIOR R/W H'0000 H'FFFFF748 8, 16 Port F control register H PFCRH R/W H'0015 H'FFFFF74A 8, 16 Port F control register L PFCRL R/W H'5000 H'FFFFF74C 8, 16 Port G IO register PGIOR R/W H'0000 H'FFFFF760 8, 16 Port G control register PGCR R/W H'0000 H'FFFFF762 8, 16 Port H IO register PHIOR R/W H'0000 H'FFFFF728 8, 16 Port H control register PHCR R/W H'0000 H'FFFFF72A 8, 16 Port J IO register PJIOR R/W H'0000 H'FFFFF766 8, 16 Port J control register H PJCRH R/W H'0000 H'FFFFF768 8, 16 Port J control register L PJCRL R/W H'0000 H'FFFFF76A 8, 16 Port K IO register PKIOR R/W H'0000 H'FFFFF770 8, 16 Port K control register H PKCRH R/W H'0000 H'FFFFF772 8, 16 Port K control register L PKCRL R/W H'0000 H'FFFFF774 8, 16 Port K invert register PKIR R/W H'0000 H'FFFFF776 8, 16 Port L IO register PLIOR R/W H'0000 H'FFFFF756 8, 16 Port L control register H PLCRH R/W H'0000 H'FFFFF758 8, 16 Port L control register L PLCRL R/W H'0000 H'FFFFF75A 8, 16 Port L invert register PLIR R/W H'0000 H'FFFFF75C 8, 16 Rev. 5.00 Feb. 24, 2010 Page 577 of 950 REJ09B0177-0500 22. Pin Function Controller (PFC) 22.3 Register Descriptions 22.3.1 Port A IO Register (PAIOR) Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 PA15 IOR PA14 IOR PA13 IOR PA12 IOR PA11 IOR PA10 IOR PA9 IOR PA8 IOR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PA7 IOR PA6 IOR PA5 IOR PA4 IOR PA3 IOR PA2 IOR PA1 IOR PA0 IOR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The port A IO register (PAIOR) is a 16-bit readable/writable register that selects the input/output direction of the 16 pins in port A. Bits PA15IOR to PA0IOR correspond to pins PA15/RxD0/SSI0 to PA0/TI0A. PAIOR is enabled when port A pins function as general input/output pins (PA15 to PA0), ATU-II input/output pins or transmit/receive input/output for the SSU* (SSI0 and SSO0), and disabled otherwise. For bits 3 to 0, when ATU-II input capture input is selected, the PAIOR bits should be cleared to 0. When port A pins function as PA15 to PA0, ATU-II input/output pins or transmit/receive input/output for the SSU* (SSI0 and SSO0), a pin becomes an output when the corresponding bit in PAIOR is set to 1, and an input when the bit is cleared to 0. PAIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. Note: * SSU: Synchronous Serial Communication Unit 22.3.2 Port A Control Registers H and L (PACRH, PACRL) Port A control registers H and L (PACRH, PACRL) are 16-bit readable/writable registers that select the functions of the 16 multiplex pins in port A. PACRH selects the functions of the pins for the upper 8 bits of port A, and PACRL selects the functions of the pins for the lower 8 bits. PACRH and PACRL are initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. They are not initialized in sleep mode. Rev. 5.00 Feb. 24, 2010 Page 578 of 950 REJ09B0177-0500 22. Pin Function Controller (PFC) Port A Control Register H (PACRH) Bit: 15 14 13 12 PA15MD1 PA15MD0 PA14MD1 PA14MD0 Initial value: R/W: Bit: R/W: 10 9 8 -- PA13MD -- PA12MD 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R R/W R R/W 7 6 5 4 3 2 1 0 PA11MD1 PA11MD0 PA10MD1 PA10MD0 Initial value: 11 PA9MD1 PA9MD0 PA8MD1 PA8MD0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W * Bits 15 and 14--PA15 Mode Bit 1, 0 (PA15MD1, PA15MD0): Selects the function of pin PA15/RxD0/SSI0. Bit 15: PA15MD1 Bit 14: PA15MD0 Description 0 0 General input/output (PA15) 1 Receive data input (RxD0) 0 Receive data input (SSI0) 1 Received (Do not set) 1 (Initial value) * Bits 13 and 12--PA14 Mode Bit 1, 0 (PA14MD1, PA14MD0): Selects the function of pin PA14/TxD0/SSO0. Bit 13: PA14MD1 0 1 Bit 12: PA14MD0 Description 0 General input/output (PA14) 1 Transmit data output (TxD0) 0 Transmit data output (SSO0) 1 Received (Do not set) (Initial value) * Bit 11--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 10--PA13 Mode Bit (PA13MD): Selects the function of pin PA13/TIO5B. Bit 10: PA13MD Description 0 General input/output (PA13) 1 ATU-II input capture input/output compare output (TIO5B) (Initial value) * Bit 9--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 8--PA12 Mode Bit (PA12MD): Selects the function of pin PA12/TIO5A. Bit 8: PA12MD Description 0 General input/output (PA12) 1 ATU-II input capture input/output compare output (TIO5A) (Initial value) Rev. 5.00 Feb. 24, 2010 Page 579 of 950 REJ09B0177-0500 22. Pin Function Controller (PFC) * Bits 7 and 6--PA11 Mode Bit 1 and 0 (PA11MD1, PA11MD0): Select the function of pin PA11/TIO4D/ADTO1B. Bit 7: PA11MD1 Bit 6: PA11MD0 Description 0 0 General input/output (PA11) 1 ATU-II input capture input/output compare output (TIO4D) 0 Setting prohibited 1 Output compare 1B output (ADTO1B) 1 (Initial value) * Bits 5 and 4--PA10 Mode Bit 1 and 0 (PA10MD1, PA10MD0): Select the function of pin PA10/TIO4C/ADTO1A. Bit 5: PA10MD1 Bit 4: PA10MD0 Description 0 0 General input/output (PA10) 1 ATU-II input capture input/output compare output (TIO4C) 1 (Initial value) 0 Setting prohibited 1 Output compare 1A output (ADTO1A) * Bits 3 and 2--PA9 Mode Bit 1 and 0 (PA9MD1, PA9MD0): Select the function of pin PA9/TIO4B/ADTO0B. Bit 3: PA9MD1 Bit 2: PA9MD0 Description 0 0 General input/output (PA9) 1 ATU-II input capture input/output compare output (TIO4B) 0 Setting prohibited 1 Output compare 0B output (ADTO0B) 1 (Initial value) * Bits 1 and 0--PA8 Mode Bit 1 and 0 (PA8MD1, PA8MD0): Select the function of pin PA8/TIO4A/ADTO0A. Bit 1: PA8MD1 Bit 0: PA8MD0 Description 0 0 General input/output (PA8) 1 ATU-II input capture input/output compare output (TIO4A) 0 Setting prohibited 1 Output compare 0A output (ADTO0A) 1 (Initial value) Port A Control Register L (PACRL) Bit: 15 14 13 12 11 10 9 8 -- PA7MD -- PA6MD -- PA5MD -- PA4MD Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R R/W R R/W R R/W Bit: 7 6 5 4 3 2 1 0 -- PA3MD -- PA2MD -- PA1MD -- PA0MD Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R R/W R R/W R R/W Rev. 5.00 Feb. 24, 2010 Page 580 of 950 REJ09B0177-0500 22. Pin Function Controller (PFC) * Bit 15--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 14--PA7 Mode Bit (PA7MD): Selects the function of pin PA7/TIO3D. Bit 14: PA7MD Description 0 General input/output (PA7) 1 ATU-II input capture input/output compare output (TIO3D) (Initial value) * Bit 13--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 12--PA6 Mode Bit (PA6MD): Selects the function of pin PA6/TIO3C. Bit 12: PA6MD Description 0 General input/output (PA6) 1 ATU-II input capture input/output compare output (TIO3C) (Initial value) * Bit 11--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 10--PA5 Mode Bit (PA5MD): Selects the function of pin PA5/TIO3B. Bit 10: PA5MD Description 0 General input/output (PA5) 1 ATU-II input capture input/output compare output (TIO3B) (Initial value) * Bit 9--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 8--PA4 Mode Bit (PA4MD): Selects the function of pin PA4/TIO3A. Bit 8: PA4MD Description 0 General input/output (PA4) 1 ATU-II input capture input/output compare output (TIO3A) (Initial value) * Bit 7--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 6--PA3 Mode Bit (PA3MD): Selects the function of pin PA3/TI0D. Bit 6: PA3MD Description 0 General input/output (PA3) 1 ATU-II input capture input (TI0D) (Initial value) * Bit 5--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 4--PA2 Mode Bit (PA2MD): Selects the function of pin PA2/TI0C. Bit 4: PA2MD Description 0 General input/output (PA2) 1 ATU-II input capture input (TI0C) (Initial value) Rev. 5.00 Feb. 24, 2010 Page 581 of 950 REJ09B0177-0500 22. Pin Function Controller (PFC) * Bit 3--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 2--PA1 Mode Bit (PA1MD): Selects the function of pin PA1/TI0B. Bit 2: PA1MD Description 0 General input/output (PA1) 1 ATU-II input capture input (TI0B) (Initial value) * Bit 1--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 0--PA0 Mode Bit (PA0MD): Selects the function of pin PA0/TI0A. Bit 0: PA0MD Description 0 General input/output (PA0) 1 ATU-II input capture input (TI0A) 22.3.3 (Initial value) Port B IO Register (PBIOR) Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 PB15 IOR PB14 IOR PB13 IOR PB12 IOR PB11 IOR PB10 IOR PB9 IOR PB8 IOR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PB7 IOR PB6 IOR PB5 IOR PB4 IOR PB3 IOR PB2 IOR PB1 IOR PB0 IOR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The port B IO register (PBIOR) is a 16-bit readable/writable register that selects the input/output direction of the 16 pins in port B. Bits PB15IOR to PB0IOR correspond to pins PB15/PULS5/SCK2/SSCK1 to PB0/TO6A. PBIOR is enabled when port B pins function as general input/output pins (PB15 to PB0) or serial clock pins (SCK0, SCK1, SCK2, SSCK0, SSCK1), and disabled otherwise. When port B pins function as PB15 to PB0 or SCK0, SCK1, and SCK2, SSCK0, SSCK1, a pin becomes an output when the corresponding bit in PBIOR is set to 1, and an input when the bit is cleared to 0. PBIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. 22.3.4 Port B Control Registers H and L (PBCRH, PBCRL) Port B control registers H and L (PBCRH, PBCRL) are 16-bit readable/writable registers that select the functions of the 16 multiplex pins in port B. PBCRH selects the functions of the pins for the upper 8 bits of port B, and PBCRL selects the functions of the pins for the lower 8 bits. PBCRH and PBCRL are initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode and in software standby mode. They are not initialized in sleep mode. Rev. 5.00 Feb. 24, 2010 Page 582 of 950 REJ09B0177-0500 22. Pin Function Controller (PFC) Port B Control Register H (PBCRH) Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 PB15 MD1 PB15 MD0 PB14 MD1 PB14 MD0 PB13 MD1 PB13 MD0 PB12 MD1 PB12 MD0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PB11 MD1 PB11 MD0 PB10 MD1 PB10 MD0 PB9 MD1 PB9 MD0 PB8 MD1 PB8 MD0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W * Bits 15 and 14--PB15 Mode Bits 1 and 0 (PB15MD1, PB15MD0): These bits select the function of pin PB15/PULS5/SCK2/SSCK1. Bit 15: PB15MD1 Bit 14: PB15MD0 Description 0 0 General input/output (PB15) 1 APC pulse output (PULS5) 0 Serial clock input/output (SCK2) 1 Serial clock output (SSCK1) 1 (Initial value) * Bits 13 and 12--PB14 Mode Bits 1 and 0 (PB14MD1, PB14MD0): These bits select the function of pin PB14/SCK1/TCLKB/T110. Bit 13: PB14MD1 Bit 12: PB14MD0 Description 0 0 General input/output (PB14) 1 Serial clock input/output (SCK1) 0 ATU-II clock input (TCLKB) 1 ATU-II edge input (TI10) 1 (Initial value) * Bits 11 and 10--PB13 Mode Bit 1, 0 (PB13MD1, PB13MD0): Selects the function of pin PB13/SCK0/SSCK0. Bit 11: PB13MD1 Bit 10: PB13MD0 Description 0 0 General input/output (PB13) 1 Serial clock input/output (SCK0) 0 Serial clock output (SSCK0) 1 Reserved (Do not set) 1 (Initial value) Rev. 5.00 Feb. 24, 2010 Page 583 of 950 REJ09B0177-0500 22. Pin Function Controller (PFC) * Bits 9 and 8--PB12 Mode Bits 1 and 0 (PB12MD1, PB12MD0): These bits select the function of pin PB12/TCLKA/UBCTRG. Bit 9: PB12MD1 Bit 8: PB12MD0 Description 0 0 General input/output (PB12) 1 ATU-II clock input (TCLKA) 0 Trigger pulse output (UBCTRG) 1 Reserved (Do not set) 1 (Initial value) * Bits 7 and 6--PB11 Mode Bits 1 and 0 (PB11MD1, PB11MD0): These bits select the function of pin PB11/RxD4/HRxD0/TO8H. Bit 7: PB11MD1 Bit 6: PB11MD0 Description 0 0 General input/output (PB11) 1 Receive data input (RxD4) 0 HCAN-II receive data input (HRxD0) 1 ATU-II one-shot pulse output (TO8H) 1 (Initial value) * Bits 5 and 4--PB10 Mode Bits 1 and 0 (PB10MD1, PB10MD0): These bits select the function of pin PB10/TxD4/HTxD0/TO8G. Bit 5: PB10MD1 Bit 4: PB10MD0 Description 0 0 General input/output (PB10) 1 Transmit data output (TxD4) 1 0 HCAN-II transmit data output (HTxD0) 1 ATU-II one-shot pulse output (TO8G) (Initial value) * Bits 3 and 2--PB9 Mode Bits 1 and 0 (PB9MD1, PB9MD0): These bits select the function of pin PB9/RxD3/TO8F. Bit 3: PB9MD1 Bit 2: PB9MD0 Description 0 0 General input/output (PB9) 1 Receive data input (RxD3) 1 0 ATU-II one-shot pulse output (TO8F) 1 Reserved (Do not set) (Initial value) * Bits 1 and 0--PB8 Mode Bits 1 and 0 (PB8MD1, PB8MD0): These bits select the function of pin PB8/TxD3/TO8E. Bit 1: PB8MD1 Bit 0: PB8MD0 Description 0 0 General input/output (PB8) 1 Transmit data output (TxD3) 0 ATU-II one-shot pulse output (TO8E) 1 Reserved (Do not set) 1 Rev. 5.00 Feb. 24, 2010 Page 584 of 950 REJ09B0177-0500 (Initial value) 22. Pin Function Controller (PFC) Port B Control Register L (PBCRL) Bit: 15 14 13 12 11 10 9 8 PB7MD1 PB7MD0 PB6MD1 PB6MD0 PB5MD1 PB5MD0 PB4MD1 PB4MD0 Initial value: R/W: Bit: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 -- PB3MD -- PB2MD -- PB1MD -- PB0MD Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R R/W R R/W R R/W * Bits 15 and 14--PB7 Mode Bits 1 and 0 (PB7MD1, PB7MD0): These bits select the function of pin PB7/TO7D/TO8D. Bit 15: PB7MD1 Bit 14: PB7MD0 Description 0 0 General input/output (PB7) 1 ATU-II PWM output (TO7D) 1 0 ATU-II one-shot pulse output (TO8D) 1 Reserved (Do not set) (Initial value) * Bits 13 and 12--PB6 Mode Bits 1 and 0 (PB6MD1, PB6MD0): These bits select the function of pin PB6/TO7C/TO8C. Bit 13: PB6MD1 Bit 12: PB6MD0 Description 0 0 General input/output (PB6) 1 ATU-II PWM output (TO7C) 0 ATU-II one-shot pulse output (TO8C) 1 Reserved (Do not set) 1 (Initial value) * Bits 11 and 10--PB5 Mode Bits 1 and 0 (PB5MD1, PB5MD0): These bits select the function of pin PB5/TO7B/TO8B. Bit 11: PB5MD1 Bit 10: PB5MD0 Description 0 0 General input/output (PB5) 1 ATU-II PWM output (TO7B) 0 ATU-II one-shot pulse output (TO8B) 1 Reserved (Do not set) 1 (Initial value) * Bits 9 and 8--PB4 Mode Bits 1 and 0 (PB4MD1, PB4MD0): These bits select the function of pin PB4/TO7A/TO8A. Bit 9: PB4MD1 Bit 8: PB4MD0 Description 0 0 General input/output (PB4) 1 ATU-II PWM output (TO7A) 0 ATU-II one-shot pulse output (TO8A) 1 Reserved (Do not set) 1 (Initial value) Rev. 5.00 Feb. 24, 2010 Page 585 of 950 REJ09B0177-0500 22. Pin Function Controller (PFC) * Bit 7--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 6--PB3 Mode Bit (PB3MD): Selects the function of pin PB3/TO6D. Bit 6: PB3MD Description 0 General input/output (PB3) 1 ATU-II PWM output (TO6D) (Initial value) * Bit 5--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 4--PB2 Mode Bit (PB2MD): Selects the function of pin PB2/TO6C. Bit 4: PB2MD Description 0 General input/output (PB2) 1 ATU-II PWM output (TO6C) (Initial value) * Bit 3--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 2--PB1 Mode Bit (PB1MD): Selects the function of pin PB1/TO6B. Bit 2: PB1MD Description 0 General input/output (PB1) 1 ATU-II PWM output (TO6B) (Initial value) * Bit 1--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 0--PB0 Mode Bit (PB0MD): Selects the function of pin PB0/TO6A. Bit 0: PB0MD Description 0 General input/output (PB0) 1 ATU-II PWM output (TO6A) 22.3.5 (Initial value) Port B Invert Register (PBIR) Bit: 15 14 13 PB15IR PB14IR PB13IR Initial value: R/W: Bit: Initial value: R/W: 12 -- 11 10 PB11IR PB10IR 9 8 PB9IR PB8IR 0 0 0 0 0 0 0 0 R/W R/W R/W R R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PB7IR PB6IR PB5IR PB4IR PB3IR PB2IR PB1IR PB0IR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The port B invert register (PBIR) is a 16-bit readable/writable register that sets the port B inversion function. Bits PB15IR to PB13IR and PB11IR to PB0IR correspond to pins PB15/PULS5/SCK2/SSCK1 to PB13/SCK0/SSCK0 and PB11/RxD4/HRxD0/TO8H to PB0/TO6A. PBIR is enabled when port B pins function as ATU-II outputs or serial clock pins, and disabled otherwise. When port B pins function as ATU-II outputs or serial clock pins, the value of a pin is inverted when the corresponding bit in PBIR is set to 1. Rev. 5.00 Feb. 24, 2010 Page 586 of 950 REJ09B0177-0500 22. Pin Function Controller (PFC) PBIR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. PBnIR Description 0 Value is not inverted 1 Value is inverted (Initial value) Note: n = 15 to 13, 11 to 0 22.3.6 Port C IO Register (PCIOR) Bit: 15 14 13 12 11 10 9 8 -- -- -- -- -- -- -- -- Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R 4 3 2 1 0 Bit: 7 6 5 -- -- -- Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R/W R/W R/W R/W R/W PC4IOR PC3IOR PC2IOR PC1IOR PC0IOR The port C IO register (PCIOR) is a 16-bit readable/writable register that selects the input/output direction of the five pins in port C. Bits PC4IOR to PC0IOR correspond to pins PC4/IRQ0 to PC0/TxD1. PCIOR is enabled when port C pins function as general input/output pins (PC4 to PC0 or transmit/receive input/output for the SSU* (SSI1 and SSO1)), and disabled otherwise. When port C pins function as PC4 to PC0 or transmit/receive input/output for the SSU* (SSI1 and SSO1), a pin becomes an output when the corresponding bit in PCIOR is set to 1, and an input when the bit is cleared to 0. PCIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. Note: * SSU: Synchronous Serial Communication Unit 22.3.7 Port C Control Register (PCCR) Bit: 15 14 13 12 11 10 9 8 -- -- -- -- -- -- -- PC4MD Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R/W Bit: 7 6 5 4 3 2 1 0 -- PC1MD -- PC0MD PC3MD1 PC3MD0 PC2MD1 PC2MD0 Initial value: R/W: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R R/W R R/W The port C control register (PCCR) is a 16-bit readable/writable register that selects the functions of the five multiplex pins in port C. PCCR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. Rev. 5.00 Feb. 24, 2010 Page 587 of 950 REJ09B0177-0500 22. Pin Function Controller (PFC) * Bits 15 to 9--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 8--PC4 Mode Bit (PC4MD): Selects the function of pin PC4/IRQ0. Bit 8: PC4MD Description 0 General input/output (PC4) 1 Interrupt request input (IRQ0) (Initial value) * Bits 7 and 6--PC3 Mode Bit 1, 0 (PC3MD1, PC3MD0): Selects the function of pin PC3/RxD2/SSI1. Bit 7: PC3MD1 Bit 6: PC3MD0 Description 0 0 General input/output (PC3) 1 Receive data input (RxD2) 1 0 Receive data input (SSI1) 1 Reserved (Do not set) (Initial value) * Bits 5 and 4--PC2 Mode Bit 1, 0 (PC2MD1, PC2MD0): Selects the function of pin PC2/TxD2/SSO1. Bit 5: PC2MD1 Bit 4: PC2MD0 Description 0 0 General input/output (PC2) 1 Transmit data output (TxD2) 0 Transmit data output (SSO1) 1 Reserved (Do not set) 1 (Initial value) * Bit 3--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 2--PC1 Mode Bit (PC1MD): Selects the function of pin PC1/RxD1. Bit 2: PC1MD Description 0 General input/output (PC1) 1 Receive data input (RxD1) (Initial value) * Bit 1--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 0--PC0 Mode Bit (PC0MD): Selects the function of pin PC0/TxD1. Bit 0: PC0MD Description 0 General input/output (PC0) 1 Transmit data output (TxD1) Rev. 5.00 Feb. 24, 2010 Page 588 of 950 REJ09B0177-0500 (Initial value) 22. Pin Function Controller (PFC) 22.3.8 Port D IO Register (PDIOR) Bit: 15 14 13 12 11 10 9 8 -- -- PD13 IOR PD12 IOR PD11 IOR PD10 IOR PD9 IOR PD8 IOR Initial value: 0 0 0 0 0 0 0 0 R/W: R R R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 PD7 IOR PD6 IOR PD5 IOR PD4 IOR PD3 IOR PD2 IOR PD1 IOR PD0 IOR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: R/W: The port D IO register (PDIOR) is a 16-bit readable/writable register that selects the input/output direction of the 14 pins in port D. Bits PD13IOR to PD0IOR correspond to pins PD13/PULS6/HTxD0/HTxD1 to PD0/TIO1A. PDIOR is enabled when port D pins function as general input/output pins (PD13 to PD0) or timer input/output pins, and disabled otherwise. When port D pins function as PD13 to PD0 or timer input/output pins, a pin becomes an output when the corresponding bit in PDIOR is set to 1, and an input when the bit is cleared to 0. PDIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. 22.3.9 Port D Control Registers H and L (PDCRH, PDCRL) Port D control registers H and L (PDCRH, PDCRL) are 16-bit readable/writable registers that select the functions of the 14 multiplex pins in port D. PDCRH selects the functions of the pins for the upper 6 bits of port D, and PDCRL selects the functions of the pins for the lower 8 bits. PDCRH and PDCRL are initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. They are not initialized in sleep mode. Port D Control Register H (PDCRH) Bit: 15 14 13 12 11 10 9 8 -- -- -- -- PD13 MD1 PD13 MD0 -- PD12 MD Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R/W R/W R R/W Bit: 7 6 5 4 3 2 1 0 -- PD11 MD -- PD10 MD -- PD9 MD -- PD8 MD Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R R/W R R/W R R/W * Bits 15 to 12--Reserved: These bits are always read as 0. The write value should always be 0. * Bits 11 and 10--PD13 Mode Bits 1 and 0 (PD13MD1, PD13MD0): These bits select the function of pin PD13/PULS6/HTxD0/HTxD1. Rev. 5.00 Feb. 24, 2010 Page 589 of 950 REJ09B0177-0500 22. Pin Function Controller (PFC) Bit 11: PD13MD1 Bit 10: PD13MD0 Description 0 0 General input/output (PD13) 1 APC pulse output (PULS6) 0 HCAN-II transmit data output (HTxD0) 1 HCAN-II transmit data output (HTxD1) 1 (Initial value) * Bit 9--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 8--PD12 Mode Bit (PD12MD): Selects the function of pin PD12/PULS4. Bit 8: PD12MD Description 0 General input/output (PD12) 1 APC pulse output (PULS4) (Initial value) * Bit 7--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 6--PD11 Mode Bit (PD11MD): Selects the function of pin PD11/PULS3. Bit 6: PD11MD Description 0 General input/output (PD11) 1 APC pulse output (PULS3) (Initial value) * Bit 5--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 4--PD10 Mode Bit (PD10MD): Selects the function of pin PD10/PULS2. Bit 4: PD10MD Description 0 General input/output (PD10) 1 APC pulse output (PULS2) (Initial value) * Bit 3--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 2--PD9 Mode Bit (PD9MD): Selects the function of pin PD9/PULS1. Bit 2: PD9MD Description 0 General input/output (PD9) 1 APC pulse output (PULS1) (Initial value) * Bit 1--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 0--PD8 Mode Bit (PD8MD): Selects the function of pin PD8/PULS0. Bit 0: PD8MD Description 0 General input/output (PD8) 1 APC pulse output (PULS0) Rev. 5.00 Feb. 24, 2010 Page 590 of 950 REJ09B0177-0500 (Initial value) 22. Pin Function Controller (PFC) Port D Control Register L (PDCRL) Bit: 15 14 13 12 11 10 9 8 -- PD7MD -- PD6MD -- PD5MD -- PD4MD Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R R/W R R/W R R/W Bit: 7 6 5 4 3 2 1 0 -- PD3MD -- PD2MD -- PD1MD -- PD0MD Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R R/W R R/W R R/W * Bit 15--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 14--PD7 Mode Bit (PD7MD): Selects the function of pin PD7/TIO1H. Bit 14: PD7MD Description 0 General input/output (PD7) 1 ATU-II input capture input/output compare output (TIO1H) (Initial value) * Bit 13--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 12--PD6 Mode Bit (PD6MD): Selects the function of pin PD6/TIO1G. Bit 12: PD6MD Description 0 General input/output (PD6) 1 ATU-II input capture input/output compare output (TIO1G) (Initial value) * Bit 11--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 10--PD5 Mode Bit (PD5MD): Selects the function of pin PD5/TIO1F. Bit 10: PD5MD Description 0 General input/output (PD5) 1 ATU-II input capture input/output compare output (TIO1F) (Initial value) * Bit 9--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 8--PD4 Mode Bit (PD4MD): Selects the function of pin PD4/TIO1E. Bit 8: PD4MD Description 0 General input/output (PD4) 1 ATU-II input capture input/output compare output (TIO1E) (Initial value) * Bit 7--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 6--PD3 Mode Bit (PD3MD): Selects the function of pin PD3/TIO1D. Bit 6: PD3MD Description 0 General input/output (PD3) 1 ATU-II input capture input/output compare output (TIO1D) (Initial value) Rev. 5.00 Feb. 24, 2010 Page 591 of 950 REJ09B0177-0500 22. Pin Function Controller (PFC) * Bit 5--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 4--PD2 Mode Bit (PD2MD): Selects the function of pin PD2/TIO1C. Bit 4: PD2MD Description 0 General input/output (PD2) 1 ATU-II input capture input/output compare output (TIO1C) (Initial value) * Bit 3--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 2--PD1 Mode Bit (PD1MD): Selects the function of pin PD1/TIO1B. Bit 2: PD1MD Description 0 General input/output (PD1) 1 ATU-II input capture input/output compare output (TIO1B) (Initial value) * Bit 1--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 0--PD0 Mode Bit (PD0MD): Selects the function of pin PD0/TIO1A. Bit 0: PD0MD Description 0 General input/output (PD0) 1 ATU-II input capture input/output compare output (TIO1A) (Initial value) 22.3.10 Port E IO Register (PEIOR) Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 PE15 IOR PE14 IOR PE13 IOR PE12 IOR PE11 IOR PE10 IOR PE9 IOR PE8 IOR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PE7 IOR PE6 IOR PE5 IOR PE4 IOR PE3 IOR PE2 IOR PE1 IOR PE0 IOR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The port E IO register (PEIOR) is a 16-bit readable/writable register that selects the input/output direction of the 16 pins in port E. Bits PE15IOR to PE0IOR correspond to pins PE15/A15 to PE0/A0. PEIOR is enabled when port E pins function as general input/output pins (PE15 to PE0), and disabled otherwise. When port E pins function as PE15 to PE0, a pin becomes an output when the corresponding bit in PEIOR is set to 1, and an input when the bit is cleared to 0. PEIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. Rev. 5.00 Feb. 24, 2010 Page 592 of 950 REJ09B0177-0500 22. Pin Function Controller (PFC) 22.3.11 Port E Control Register (PECR) Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 PE15 MD PE14 MD PE13 MD PE12 MD PE11 MD PE10 MD PE9 MD PE8 MD 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PE7 MD PE6 MD PE5 MD PE4 MD PE3 MD PE2 MD PE1 MD PE0 MD 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The port E control register (PECR) is a 16-bit readable/writable register that selects the functions of the 16 multiplex pins in port E. PECR settings are not valid in all operating modes. 1. Expanded mode with on-chip ROM disabled Port E pins function as address output pins, and PECR settings are invalid. 2. Expanded mode with on-chip ROM enabled Port E pins are multiplexed as address output pins and general input/output pins. PECR settings are valid. 3. Single-chip mode Port E pins function as general input/output pins, and PECR settings are invalid. PECR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. * Bit 15--PE15 Mode Bit (PE15MD): Selects the function of pin PE15/A15. Description Bit 15: PE15MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Address output (A15) (Initial value) General input/output (PE15) (Initial value) General input/output (PE15) (Initial value) 1 Address output (A15) Address output (A15) General input/output (PE15) * Bit 14--PE14 Mode Bit (PE14MD): Selects the function of pin PE14/A14. Description Bit 14: PE14MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Address output (A14) (Initial value) General input/output (PE14) (Initial value) General input/output (PE14) (Initial value) 1 Address output (A14) Address output (A14) General input/output (PE14) * Bit 13--PE13 Mode Bit (PE13MD): Selects the function of pin PE13/A13. Rev. 5.00 Feb. 24, 2010 Page 593 of 950 REJ09B0177-0500 22. Pin Function Controller (PFC) Description Bit 13: PE13MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Address output (A13) (Initial value) General input/output (PE13) (Initial value) General input/output (PE13) (Initial value) 1 Address output (A13) Address output (A13) General input/output (PE13) * Bit 12--PE12 Mode Bit (PE12MD): Selects the function of pin PE12/A12. Description Bit 12: PE12MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Address output (A12) (Initial value) General input/output (PE12) (Initial value) General input/output (PE12) (Initial value) 1 Address output (A12) Address output (A12) General input/output (PE12) * Bit 11--PE11 Mode Bit (PE11MD): Selects the function of pin PE11/A11. Description Bit 11: PE11MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Address output (A11) (Initial value) General input/output (PE11) (Initial value) General input/output (PE11) (Initial value) 1 Address output (A11) Address output (A11) General input/output (PE11) * Bit 10--PE10 Mode Bit (PE10MD): Selects the function of pin PE10/A10. Description Bit 10: PE10MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Address output (A10) (Initial value) General input/output (PE10) (Initial value) General input/output (PE10) (Initial value) 1 Address output (A10) Address output (A10) General input/output (PE10) * Bit 9--PE9 Mode Bit (PE9MD): Selects the function of pin PE9/A9. Description Bit 9: PE9MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Address output (A9) (Initial value) General input/output (PE9) (Initial value) General input/output (PE9) (Initial value) 1 Address output (A9) Address output (A9) General input/output (PE9) * Bit 8--PE8 Mode Bit (PE8MD): Selects the function of pin PE8/A8. Rev. 5.00 Feb. 24, 2010 Page 594 of 950 REJ09B0177-0500 22. Pin Function Controller (PFC) Description Bit 8: PE8MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Address output (A8) (Initial value) General input/output (PE8) (Initial value) General input/output (PE8) (Initial value) 1 Address output (A8) Address output (A8) General input/output (PE8) * Bit 7--PE7 Mode Bit (PE7MD): Selects the function of pin PE7/A7. Description Bit 7: PE7MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Address output (A7) (Initial value) General input/output (PE7) (Initial value) General input/output (PE7) (Initial value) 1 Address output (A7) Address output (A7) General input/output (PE7) * Bit 6--PE6 Mode Bit (PE6MD): Selects the function of pin PE6/A6. Description Bit 6: PE6MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Address output (A6) (Initial value) General input/output (PE6) (Initial value) General input/output (PE6) (Initial value) 1 Address output (A6) Address output (A6) General input/output (PE6) * Bit 5--PE5 Mode Bit (PE5MD): Selects the function of pin PE5/A5. Description Bit 5: PE5MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Address output (A5) (Initial value) General input/output (PE5) (Initial value) General input/output (PE5) (Initial value) 1 Address output (A5) Address output (A5) General input/output (PE5) * Bit 4--PE4 Mode Bit (PE4MD): Selects the function of pin PE4/A4. Description Bit 4: PE4MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Address output (A4) (Initial value) General input/output (PE4) (Initial value) General input/output (PE4) (Initial value) 1 Address output (A4) Address output (A4) General input/output (PE4) * Bit 3--PE3 Mode Bit (PE3MD): Selects the function of pin PE3/A3. Rev. 5.00 Feb. 24, 2010 Page 595 of 950 REJ09B0177-0500 22. Pin Function Controller (PFC) Description Bit 3: PE3MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Address output (A3) (Initial value) General input/output (PE3) (Initial value) General input/output (PE3) (Initial value) 1 Address output (A3) Address output (A3) General input/output (PE3) * Bit 2--PE2 Mode Bit (PE2MD): Selects the function of pin PE2/A2. Description Bit 2: PE2MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Address output (A2) (Initial value) General input/output (PE2) (Initial value) General input/output (PE2) (Initial value) 1 Address output (A2) Address output (A2) General input/output (PE2) * Bit 1--PE1 Mode Bit (PE1MD): Selects the function of pin PE1/A1. Description Bit 1: PE1MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Address output (A1) (Initial value) General input/output (PE1) (Initial value) General input/output (PE1) (Initial value) 1 Address output (A1) Address output (A1) General input/output (PE1) * Bit 0--PE0 Mode Bit (PE0MD): Selects the function of pin PE0/A0. Description Bit 0: PE0MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Address output (A0) (Initial value) General input/output (PE0) (Initial value) General input/output (PE0) (Initial value) 1 Address output (A0) Address output (A0) General input/output (PE0) 22.3.12 Port F IO Register (PFIOR) Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 PF15 IOR PF14 IOR PF13 IOR PF12 IOR PF11 IOR PF10 IOR PF9 IOR PF8 IOR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PF7 IOR PF6 IOR PF5 IOR PF4 IOR PF3 IOR PF2 IOR PF1 IOR PF0 IOR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Rev. 5.00 Feb. 24, 2010 Page 596 of 950 REJ09B0177-0500 22. Pin Function Controller (PFC) The port F IO register (PFIOR) is a 16-bit readable/writable register that selects the input/output direction of the 16 pins in port F. Bits PF15IOR to PF0IOR correspond to pins PF15/BREQ/SCS1 to PF0/A16. PFIOR is enabled when port F pins function as general input/output pins (PF15 to PF0), and disabled otherwise. When port F pins function as PF15 to PF0, a pin becomes an output when the corresponding bit in PFIOR is set to 1, and an input when the bit is cleared to 0. PFIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. It is not initialized by a WDT power-on reset. 22.3.13 Port F Control Registers H and L (PFCRH, PFCRL) Port F control registers H and L (PFCRH, PFCRL) are 16-bit readable/writable registers that select the functions of the 16 multiplex pins in port F and the function of the CK pin. PFCRH selects the functions of the pins for the upper 8 bits of port F, and PFCRL selects the functions of the pins for the lower 8 bits. PFCRH and PFCRL are initialized to H'0015 and H'5000, respectively, by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. They are not initialized in sleep mode. Port F Control Register H (PFCRH) Bit: 15 14 13 12 11 10 CKHIZ PF15MD PF15MD PF14MD PF14MD PF13MD 0 1 0 1 Initial value: 9 8 -- PF12MD 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R R/W 7 6 5 4 3 2 1 0 -- PF11MD -- PF10MD -- PF9MD -- PF8MD Initial value: 0 0 0 1 0 1 0 1 R/W: R R/W R R/W R R/W R R/W R/W: Bit: * Bit 15--CKHIZ Bit: Selects the function of pin CK. Bit: CKHIZ Description 0 CK pin output 1 CK pin Hi-Z (Initial value) * Bits 14 and 13--PF15 Mode Bit 0, 1 (PF15MD0, PF15MD1): Selects the function of pin PF15/BREQ/SCS1. Description Bit 14: PF15MD0 Bit 13: PF15MD1 Expanded Mode Single-Chip Mode 0 0 General input/output (PF15) (Initial value) General input/output (PF15) (Initial value) 1 Reserved (Do not set) Chip select input/output (SCS1) 0 Bus request input (BREQ) General input/output (PF15) 1 Reserved (Do not set) 1 Rev. 5.00 Feb. 24, 2010 Page 597 of 950 REJ09B0177-0500 22. Pin Function Controller (PFC) * Bits 12 and 11--PF14 Mode Bit 0, 1 (PF14MD0, PF14MD1): Selects the function of pin PF14/BACK/SCS0. Description Bit 12: PF14MD0 Bit 11: PF14MD1 Expanded Mode Single-Chip Mode 0 0 General input/output (PF14) (Initial value) General input/output (PF14) (Initial value) 1 Reserved (Do not set) Chip select input/output (SCS0) 0 Bus acknowledge output (BACK) General input/output (PF14) 1 Reserved (Do not set) 1 * Bit 10--PF13 Mode Bit (PF13MD): Selects the function of pin PF13/CS3. Description Bit 10: PF13MD Expanded Mode Single-Chip Mode 0 General input/output (PF13) (Initial value) General input/output (PF13) (Initial value) 1 Chip select output (CS3) General input/output (PF13) * Bit 9--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 8--PF12 Mode Bit (PF12MD): Selects the function of pin PF12/CS2. Description Bit 8: PF12MD Expanded Mode Single-Chip Mode 0 General input/output (PF12) (Initial value) General input/output (PF12) (Initial value) 1 Chip select output (CS2) General input/output (PF12) * Bit 7--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 6--PF11 Mode Bit (PF11MD): Selects the function of pin PF11/CS1. Description Bit 6: PF11MD Expanded Mode Single-Chip Mode 0 General input/output (PF11) (Initial value) General input/output (PF11) (Initial value) 1 Chip select output (CS1) General input/output (PF11) * Bit 5--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 4--PF10 Mode Bit (PF10MD): Selects the function of pin PF10/CS0. Description Bit 4: PF10MD Expanded Mode Single-Chip Mode 0 General input/output (PF10) General input/output (PF10) 1 Chip select output (CS0) (Initial value) General input/output (PF10) (Initial value) * Bit 3--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 2--PF9 Mode Bit (PF9MD): Selects the function of pin PF9/RD. Rev. 5.00 Feb. 24, 2010 Page 598 of 950 REJ09B0177-0500 22. Pin Function Controller (PFC) Description Bit 2: PF9MD Expanded Mode Single-Chip Mode 0 General input/output (PF9) General input/output (PF9) 1 Read output (RD) (Initial value) General input/output (PF9) (Initial value) * Bit 1--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 0--PF8 Mode Bit (PF8MD): Selects the function of pin PF8/WAIT. Description Bit 0: PF8MD Expanded Mode Single-Chip Mode 0 General input/output (PF8) General input/output (PF8) 1 Wait state input (WAIT) (Initial value) General input/output (PF8) (Initial value) Port F Control Register L (PFCRL) Bit: 15 14 13 -- PF7MD -- 12 11 10 PF6MD PF5MD1 PF5MD0 9 8 -- PF4MD Initial value: 0 1 0 1 0 0 0 0 R/W: R R/W R R/W R/W R/W R R/W Bit: 7 6 5 4 3 2 1 0 -- PF3MD -- PF2MD -- PF1MD -- PF0MD Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R R/W R R/W R R/W * Bit 15--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 14--PF7 Mode Bit (PF7MD): Selects the function of pin PF7/WRH. Description Bit 14: PF7MD Expanded Mode Single-Chip Mode 0 General input/output (PF7) General input/output (PF7) 1 Upper write (WRH) (Initial value) General input/output (PF7) (Initial value) * Bit 13--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 12--PF6 Mode Bit (PF6MD): Selects the function of pin PF6/WRL. Description Bit 12: PF6MD Expanded Mode Single-Chip Mode 0 General input/output (PF6) General input/output (PF6) 1 Lower write (WRL) (Initial value) General input/output (PF6) (Initial value) Rev. 5.00 Feb. 24, 2010 Page 599 of 950 REJ09B0177-0500 22. Pin Function Controller (PFC) * Bits 11 and 10--PF5 Mode Bits 1 and 0 (PF5MD1, PF5MD0): These bits select the function of pin PF5/A21/POD. Description Bit 11: PF5MD1 Bit 10: PF5MD0 Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 1 0 Address output (A21) (Initial value) General input/output (PF5) (Initial value) General input/output (PF5) (Initial value) 1 Address output (A21) Address output (A21) General input/output (PF5) 0 Address output (A21) Port output disable input (POD) Port output disable input (POD) 1 Reserved (Do not set) Reserved (Do not set) Reserved (Do not set) * Bit 9--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 8--PF4 Mode Bit (PF4MD): Selects the function of pin PF4/A20. Description Bit 8: PF4MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Address output (A20) (Initial value) General input/output (PF4) (Initial value) General input/output (PF4) (Initial value) 1 Address output (A20) Address output (A20) General input/output (PF4) * Bit 7--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 6--PF3 Mode Bit (PF3MD): Selects the function of pin PF3/A19. Description Bit 6: PF3MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Address output (A19) (Initial value) General input/output (PF3) (Initial value) General input/output (PF3) (Initial value) 1 Address output (A19) Address output (A19) General input/output (PF3) * Bit 5--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 4--PF2 Mode Bit (PF2MD): Selects the function of pin PF2/A18. Description Bit 4: PF2MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Address output (A18) (Initial value) General input/output (PF2) (Initial value) General input/output (PF2) (Initial value) 1 Address output (A18) Address output (A18) General input/output (PF2) * Bit 3--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 2--PF1 Mode Bit (PF1MD): Selects the function of pin PF1/A17. Rev. 5.00 Feb. 24, 2010 Page 600 of 950 REJ09B0177-0500 22. Pin Function Controller (PFC) Description Bit 2: PF1MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Address output (A17) (Initial value) General input/output (PF1) (Initial value) General input/output (PF1) (Initial value) 1 Address output (A17) Address output (A17) General input/output (PF1) * Bit 1--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 0--PF0 Mode Bit (PF0MD): Selects the function of pin PF0/A16. Description Bit 0: PF0MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Address output (A16) (Initial value) General input/output (PF0) (Initial value) General input/output (PF0) (Initial value) 1 Address output (A16) Address output (A16) General input/output (PF0) 22.3.14 Port G IO Register (PGIOR) Bit: 15 14 13 12 11 10 9 8 -- -- -- -- -- -- -- -- Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 -- -- -- -- Initial value: 0 0 0 0 PG3IOR PG2IOR PG1IOR PG0IOR 0 0 0 0 R/W: R R R R R/W R/W R/W R/W The port G IO register (PGIOR) is a 16-bit readable/writable register that selects the input/output direction of the four pins in port G. Bits PG3IOR to PG0IOR correspond to pins PG3/IRQ3/ADTRG0 to PG0/PULS7/HRxD0/HRxD1. When port G pins function as PG3 to PG0, a pin becomes an output when the corresponding bit in PGIOR is set to 1, and an input when the bit is cleared to 0. PGIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. Rev. 5.00 Feb. 24, 2010 Page 601 of 950 REJ09B0177-0500 22. Pin Function Controller (PFC) 22.3.15 Port G Control Register (PGCR) The port G control register (PGCR) is a 16-bit readable/writable register that selects the functions of the four multiplex pins in port G. PGCR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. Bit: 15 14 13 12 11 10 9 8 -- -- -- -- -- -- -- -- Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 PG3MD1 PG3MD0 PG2MD1 PG2MD0 Initial value: R/W: -- PG1MD PG0MD1 PG0MD0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R R/W R/W R/W * Bits 15 to 8--Reserved: These bits are always read as 0. The write value should always be 0. * Bits 7 and 6--PG3 Mode Bits 1 and 0 (PG3MD1, PG3MD0): These bits select the function of pin PG3/IRQ3/ADTRG0. Bit 7: PG3MD1 Bit 6: PG3MD0 Description 0 0 General input/output (PG3) 1 Interrupt request input (IRQ3) 0 A/D conversion trigger input (ADTRG0) 1 Reserved (Do not set) 1 (Initial value) * Bits 5 and 4--PG2 Mode Bits 1 and 0 (PG2MD1, PG2MD0): These bits select the function of pin PG2/IRQ2/ADEND. Bit 5: PG2MD1 Bit 4: PG2MD0 Description 0 0 General input/output (PG2) 1 Interrupt request input (IRQ2) 0 A/D conversion end output (ADEND) 1 Reserved (Do not set) 1 (Initial value) * Bit 3--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 2--PG1 Mode Bit (PG1MD): Selects the function of pin PG1/IRQ1. Bit 2: PG1MD Description 0 General input/output (PG1) 1 Interrupt request input (IRQ1) * Bits 1 and 0--PG0 Mode Bits 1 and 0 (PG0MD1, PG2MD0): These bits select the function of pin PG0/PULS7/HRxD0/HRxD1. Rev. 5.00 Feb. 24, 2010 Page 602 of 950 REJ09B0177-0500 (Initial value) 22. Pin Function Controller (PFC) Bit 1: PG0MD1 Bit 0: PG0MD0 Description 0 0 General input/output (PG0) 1 APC pulse output (PULS7) 0 HCAN-II receive data input (HRxD0) 1 HCAN-II receive data input (HRxD1) 1 (Initial value) 22.3.16 Port H IO Register (PHIOR) Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 PH15 IOR PH14 IOR PH13 IOR PH12 IOR PH11 IOR PH10 IOR PH9 IOR PH8 IOR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PH7 IOR PH6 IOR PH5 IOR PH4 IOR PH3 IOR PH2 IOR PH1 IOR PH0 IOR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The port H IO register (PHIOR) is a 16-bit readable/writable register that selects the input/output direction of the 16 pins in port H. Bits PH15IOR to PH0IOR correspond to pins PH15/D15 to PH0/D0. PHIOR is enabled when port H pins function as general input/output pins (PH15 to PH0), and disabled otherwise. When port H pins function as PH15 to PH0, a pin becomes an output when the corresponding bit in PHIOR is set to 1, and an input when the bit is cleared to 0. PHIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. 22.3.17 Port H Control Register (PHCR) Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 PH15 MD PH14 MD PH13 MD PH12 MD PH11 MD PH10 MD PH9 MD PH8 MD 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PH7 MD PH6 MD PH5 MD PH4 MD PH3 MD PH2 MD PH1 MD PH0 MD 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The port H control register (PHCR) is a 16-bit readable/writable register that selects the functions of the 16 multiplex pins in port H. PHCR settings are not valid in all operating modes. 1. Expanded mode with on-chip ROM disabled (area 0: 8-bit bus) Port H pins D0 to D7 function as data input/output pins, and PHCR settings are invalid. Rev. 5.00 Feb. 24, 2010 Page 603 of 950 REJ09B0177-0500 22. Pin Function Controller (PFC) 2. Expanded mode with on-chip ROM disabled (area 0: 16-bit bus) Port H pins function as data input/output pins, and PHCR settings are invalid. 3. Expanded mode with on-chip ROM enabled Port H pins are multiplexed as data input/output pins and general input/output pins. PHCR settings are valid. 4. Single-chip mode Port H pins function as general input/output pins, and PHCR settings are invalid. PHCR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. * Bit 15--PH15 Mode Bit (PH15MD): Selects the function of pin PH15/D15. Description Expanded Mode with Bit 15: PH15MD ROM Disabled Area 0: 8 Bits Expanded Mode with ROM Disabled Area 0: 16 Bits 0 General input/output (PH15) (Initial value) 1 Data input/output (D15) Expanded Mode with ROM Enabled Single-Chip Mode Data input/output (D15) (Initial value) General input/output (PH15) (Initial value) General input/output (PH15) (Initial value) Data input/output (D15) Data input/output (D15) General input/output (PH15) * Bit 14--PH14 Mode Bit (PH14MD): Selects the function of pin PH14/D14. Description Expanded Mode with Bit 14: PH14MD ROM Disabled Area 0: 8 Bits Expanded Mode with ROM Disabled Area 0: 16 Bits 0 General input/output (PH14) (Initial value) 1 Data input/output (D14) Expanded Mode with ROM Enabled Single-Chip Mode Data input/output (D14) (Initial value) General input/output (PH14) (Initial value) General input/output (PH14) (Initial value) Data input/output (D14) Data input/output (D14) General input/output (PH14) * Bit 13--PH13 Mode Bit (PH13MD): Selects the function of pin PH13/D13. Description Expanded Mode with Bit 13: PH13MD ROM Disabled Area 0: 8 Bits Expanded Mode with ROM Disabled Area 0: 16 Bits 0 General input/output (PH13) (Initial value) 1 Data input/output (D13) Rev. 5.00 Feb. 24, 2010 Page 604 of 950 REJ09B0177-0500 Expanded Mode with ROM Enabled Single-Chip Mode Data input/output (D13) (Initial value) General input/output (PH13) (Initial value) General input/output (PH13) (Initial value) Data input/output (D13) Data input/output (D13) General input/output (PH13) 22. Pin Function Controller (PFC) * Bit 12--PH12 Mode Bit (PH12MD): Selects the function of pin PH12/D12. Description Expanded Mode with Bit 12: PH12MD ROM Disabled Area 0: 8 Bits Expanded Mode with ROM Disabled Area 0: 16 Bits 0 General input/output (PH12) (Initial value) 1 Data input/output (D12) Expanded Mode with ROM Enabled Single-Chip Mode Data input/output (D12) (Initial value) General input/output (PH12) (Initial value) General input/output (PH12) (Initial value) Data input/output (D12) Data input/output (D12) General input/output (PH12) * Bit 11--PH11 Mode Bit (PH11MD): Selects the function of pin PH11/D11. Description Expanded Mode with Bit 11: PH11MD ROM Disabled Area 0: 8 Bits Expanded Mode with ROM Disabled Area 0: 16 Bits 0 General input/output (PH11) (Initial value) 1 Data input/output (D11) Expanded Mode with ROM Enabled Single-Chip Mode Data input/output (D11) (Initial value) General input/output (PH11) (Initial value) General input/output (PH11) (Initial value) Data input/output (D11) Data input/output (D11) General input/output (PH11) * Bit 10--PH10 Mode Bit (PH10MD): Selects the function of pin PH10/D10. Description Expanded Mode with Bit 10: PH10MD ROM Disabled Area 0: 8 Bits Expanded Mode with ROM Disabled Area 0: 16 Bits 0 General input/output (PH10) (Initial value) 1 Data input/output (D10) Expanded Mode with ROM Enabled Single-Chip Mode Data input/output (D10) (Initial value) General input/output (PH10) (Initial value) General input/output (PH10) (Initial value) Data input/output (D10) Data input/output (D10) General input/output (PH10) * Bit 9--PH9 Mode Bit (PH9MD): Selects the function of pin PH9/D9. Description Expanded Mode with ROM Disabled Area 0: 8 Bits Expanded Mode with ROM Disabled Area 0: 16 Bits 0 General input/output (PH9) (Initial value) 1 Data input/output (D9) Bit 9: PH9MD Expanded Mode with ROM Enabled Single-Chip Mode Data input/output (D9) (Initial value) General input/output (PH9) (Initial value) General input/output (PH9) (Initial value) Data input/output (D9) Data input/output (D9) General input/output (PH9) * Bit 8--PH8 Mode Bit (PH8MD): Selects the function of pin PH8/D8. Rev. 5.00 Feb. 24, 2010 Page 605 of 950 REJ09B0177-0500 22. Pin Function Controller (PFC) Description Expanded Mode with ROM Disabled Area 0: 8 Bits Expanded Mode with ROM Disabled Area 0: 16 Bits 0 General input/output (PH8) (Initial value) 1 Data input/output (D8) Bit 8: PH8MD Expanded Mode with ROM Enabled Single-Chip Mode Data input/output (D8) (Initial value) General input/output (PH8) (Initial value) General input/output (PH8) (Initial value) Data input/output (D8) Data input/output (D8) General input/output (PH8) * Bit 7--PH7 Mode Bit (PH7MD): Selects the function of pin PH7/D7. Description Bit 7: PH7MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Data input/output (D7) (Initial value) General input/output (PH7) (Initial value) General input/output (PH7) (Initial value) 1 Data input/output (D7) Data input/output (D7) General input/output (PH7) * Bit 6--PH6 Mode Bit (PH6MD): Selects the function of pin PH6/D6. Description Bit 6: PH6MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Data input/output (D6) (Initial value) General input/output (PH6) (Initial value) General input/output (PH6) (Initial value) 1 Data input/output (D6) Data input/output (D6) General input/output (PH6) * Bit 5--PH5 Mode Bit (PH5MD): Selects the function of pin PH5/D5. Description Bit 5: PH5MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Data input/output (D5) (Initial value) General input/output (PH5) (Initial value) General input/output (PH5) (Initial value) 1 Data input/output (D5) Data input/output (D5) General input/output (PH5) * Bit 4--PH4 Mode Bit (PH4MD): Selects the function of pin PH4/D4. Description Bit 4: PH4MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Data input/output (D4) (Initial value) General input/output (PH4) (Initial value) General input/output (PH4) (Initial value) 1 Data input/output (D4) Data input/output (D4) General input/output (PH4) Rev. 5.00 Feb. 24, 2010 Page 606 of 950 REJ09B0177-0500 22. Pin Function Controller (PFC) * Bit 3--PH3 Mode Bit (PH3MD): Selects the function of pin PH3/D3. Description Bit 3: PH3MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Data input/output (D3) (Initial value) General input/output (PH3) (Initial value) General input/output (PH3) (Initial value) 1 Data input/output (D3) Data input/output (D3) General input/output (PH3) * Bit 2--PH2 Mode Bit (PH2MD): Selects the function of pin PH2/D2. Description Bit 2: PH2MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Data input/output (D2) (Initial value) General input/output (PH2) (Initial value) General input/output (PH2) (Initial value) 1 Data input/output (D2) Data input/output (D2) General input/output (PH2) * Bit 1--PH1 Mode Bit (PH1MD): Selects the function of pin PH1/D1. Description Bit 1: PH1MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Data input/output (D1) (Initial value) General input/output (PH1) (Initial value) General input/output (PH1) (Initial value) 1 Data input/output (D1) Data input/output (D1) General input/output (PH1) * Bit 0--PH0 Mode Bit (PH0MD): Selects the function of pin PH0/D0. Description Bit 0: PH0MD Expanded Mode with ROM Disabled Expanded Mode with ROM Enabled Single-Chip Mode 0 Data input/output (D0) (Initial value) General input/output (PH0) (Initial value) General input/output (PH0) (Initial value) 1 Data input/output (D0) Data input/output (D0) General input/output (PH0) Rev. 5.00 Feb. 24, 2010 Page 607 of 950 REJ09B0177-0500 22. Pin Function Controller (PFC) 22.3.18 Port J IO Register (PJIOR) Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 PJ15 IOR PJ14 IOR PJ13 IOR PJ12 IOR PJ11 IOR PJ10 IOR PJ9 IOR PJ8 IOR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PJ7 IOR PJ6 IOR PJ5 IOR PJ4 IOR PJ3 IOR PJ2 IOR PJ1 IOR PJ0 IOR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The port J IO register (PJIOR) is a 16-bit readable/writable register that selects the input/output direction of the 16 pins in port J. Bits PJ15IOR to PJ0IOR correspond to pins PJ15/TI9F to PJ0/TIO2A. PJIOR is enabled when port J pins function as general input/output pins (PJ15 to PJ0) or ATU-II input/output pins, and disabled otherwise. When ATU-II event counter input is selected, however, the bits 10 to 15 of the PJIOR should be cleared to 0. When port J pins function as PJ15 to PJ0 or ATU-II input/output pins, a pin becomes an output when the corresponding bit in PJIOR is set to 1, and an input when the bit is cleared to 0. PJIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. 22.3.19 Port J Control Registers H and L (PJCRH, PJCRL) Port J control registers H and L (PJCRH, PJCRL) are 16-bit readable/writable registers that select the functions of the 16 multiplex pins in port J. PJCRH selects the functions of the pins for the upper 8 bits of port J, and PJCRL selects the functions of the pins for the lower 8 bits. PJCRH and PJCRL are initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. They are not initialized in sleep mode. Port J Control Register H (PJCRH) Bit: 15 14 13 12 11 10 9 8 -- PJ15MD -- PJ14MD -- PJ13MD -- PJ12MD Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R R/W R R/W R R/W Bit: 7 6 5 4 3 2 1 0 -- PJ11MD -- PJ10MD -- PJ9MD -- PJ8MD Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R R/W R R/W R R/W * Bit 15--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 14--PJ15 Mode Bit (PJ15MD): Selects the function of pin PJ15/TI9F. Rev. 5.00 Feb. 24, 2010 Page 608 of 950 REJ09B0177-0500 22. Pin Function Controller (PFC) Bit 14: PJ15MD Description 0 General input/output (PJ15) 1 ATU-II event counter input (TI9F) (Initial value) * Bit 13--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 12--PJ14 Mode Bit (PJ14MD): Selects the function of pin PJ14/TI9E. Bit 12: PJ14MD Description 0 General input/output (PJ14) 1 ATU-II event counter input (TI9E) (Initial value) * Bit 11--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 10--PJ13 Mode Bit (PJ13MD): Selects the function of pin PJ13/TI9D. Bit 10: PJ13MD Description 0 General input/output (PJ13) 1 ATU-II event counter input (TI9D) (Initial value) * Bit 9--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 8--PJ12 Mode Bit (PJ12MD): Selects the function of pin PJ12/TI9C. Bit 8: PJ12MD Description 0 General input/output (PJ12) 1 ATU-II event counter input (TI9C) (Initial value) * Bit 7--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 6--PJ11 Mode Bit (PJ11MD): Selects the function of pin PJ11/TI9B. Bit 6: PJ11MD Description 0 General input/output (PJ11) 1 ATU-II event counter input (TI9B) (Initial value) * Bit 5--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 4--PJ10 Mode Bit (PJ10MD): Selects the function of pin PJ10/TI9A. Bit 4: PJ10MD Description 0 General input/output (PJ10) 1 ATU-II event counter input (TI9A) (Initial value) * Bit 3--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 2--PJ9 Mode Bit (PJ9MD): Selects the function of pin PJ9/TIO5D. Bit 2: PJ9MD Description 0 General input/output (PJ9) 1 ATU-II input capture input/output compare output (TIO5D) (Initial value) * Bit 1--Reserved: This bit is always read as 0. The write value should always be 0. Rev. 5.00 Feb. 24, 2010 Page 609 of 950 REJ09B0177-0500 22. Pin Function Controller (PFC) * Bit 0--PJ8 Mode Bit (PJ8MD): Selects the function of pin PJ8/TIO5C. Bit 0: PJ8MD Description 0 General input/output (PJ8) 1 ATU-II input capture input/output compare output (TIO5C) (Initial value) Port J Control Register L (PJCRL) Bit: 15 14 13 12 11 10 9 8 -- PJ7MD -- PJ6MD -- PJ5MD -- PJ4MD Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R R/W R R/W R R/W Bit: 7 6 5 4 3 2 1 0 -- PJ3MD -- PJ2MD -- PJ1MD -- PJ0MD Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R R/W R R/W R R/W * Bit 15--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 14--PJ7 Mode Bit (PJ7MD): Selects the function of pin PJ7/TIO2H. Bit 14: PJ7MD Description 0 General input/output (PJ7) 1 ATU-II input capture input/output compare output (TIO2H) (Initial value) * Bit 13--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 12--PJ6 Mode Bit (PJ6MD): Selects the function of pin PJ6/TIO2G. Bit 12: PJ6MD Description 0 General input/output (PJ6) 1 ATU-II input capture input/output compare output (TIO2G) (Initial value) * Bit 11--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 10--PJ5 Mode Bit (PJ5MD): Selects the function of pin PJ5/TIO2F. Bit 10: PJ5MD Description 0 General input/output (PJ5) 1 ATU-II input capture input/output compare output (TIO2F) (Initial value) * Bit 9--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 8--PJ4 Mode Bit (PJ4MD): Selects the function of pin PJ4/TIO2E. Bit 8: PJ4MD Description 0 General input/output (PJ4) 1 ATU-II input capture input/output compare output (TIO2E) * Bit 7--Reserved: This bit is always read as 0. The write value should always be 0. Rev. 5.00 Feb. 24, 2010 Page 610 of 950 REJ09B0177-0500 (Initial value) 22. Pin Function Controller (PFC) * Bit 6--PJ3 Mode Bit (PJ3MD): Selects the function of pin PJ3/TIO2D. Bit 6: PJ3MD Description 0 General input/output (PJ3) 1 ATU-II input capture input/output compare output (TIO2D) (Initial value) * Bit 5--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 4--PJ2 Mode Bit (PJ2MD): Selects the function of pin PJ2/TIO2C. Bit 4: PJ2MD Description 0 General input/output (PJ2) 1 ATU-II input capture input/output compare output (TIO2C) (Initial value) * Bit 3--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 2--PJ1 Mode Bit (PJ1MD): Selects the function of pin PJ1/TIO2B. Bit 2: PJ1MD Description 0 General input/output (PJ1) 1 ATU-II input capture input/output compare output (TIO2B) (Initial value) * Bit 1--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 0--PJ0 Mode Bit (PJ0MD): Selects the function of pin PJ0/TIO2A. Bit 0: PJ0MD Description 0 General input/output (PJ0) 1 ATU-II input capture input/output compare output (TIO2A) (Initial value) Rev. 5.00 Feb. 24, 2010 Page 611 of 950 REJ09B0177-0500 22. Pin Function Controller (PFC) 22.3.20 Port K IO Register (PKIOR) Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 PK15 IOR PK14 IOR PK13 IOR PK12 IOR PK11 IOR PK10 IOR PK9 IOR PK8 IOR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PK7 IOR PK6 IOR PK5 IOR PK4 IOR PK3 IOR PK2 IOR PK1 IOR PK0 IOR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The port K IO register (PKIOR) is a 16-bit readable/writable register that selects the input/output direction of the 16 pins in port K. Bits PK15IOR to PK0IOR correspond to pins PK15/TO8P to PK0/TO8A. PKIOR is enabled when port K pins function as general input/output pins (PK15 to PK0), and disabled otherwise. When port K pins function as PK15 to PK0, a pin becomes an output when the corresponding bit in PKIOR is set to 1, and an input when the bit is cleared to 0. PKIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. 22.3.21 Port K Control Registers H and L (PKCRH, PKCRL) Port K control registers H and L (PKCRH, PKCRL) are 16-bit readable/writable registers that select the functions of the 16 multiplex pins in port K. PKCRH selects the functions of the pins for the upper 8 bits of port K, and PKCRL selects the functions of the pins for the lower 8 bits. PKCRH and PKCRL are initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. They are not initialized in sleep mode. Port K Control Register H (PKCRH) Bit: 15 14 13 12 11 10 9 8 -- PK15 MD -- PK14 MD -- PK13 MD -- PK12 MD Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R R/W R R/W R R/W 7 6 5 4 3 2 1 0 -- PK11 MD -- PK10 MD -- PK9 MD -- PK8 MD Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R R/W R R/W R R/W Bit: * Bit 15--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 14--PK15 Mode Bit (PK15MD): Selects the function of pin PK15/TO8P. Rev. 5.00 Feb. 24, 2010 Page 612 of 950 REJ09B0177-0500 22. Pin Function Controller (PFC) Bit 14: PK15MD Description 0 General input/output (PK15) 1 ATU-II one-shot pulse output (TO8P) (Initial value) * Bit 13--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 12--PK14 Mode Bit (PK14MD): Selects the function of pin PK14/TO8O. Bit 12: PK14MD Description 0 General input/output (PK14) 1 ATU-II one-shot pulse output (TO8O) (Initial value) * Bit 11--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 10--PK13 Mode Bit (PK13MD): Selects the function of pin PK13/TO8N. Bit 10: PK13MD Description 0 General input/output (PK13) 1 ATU-II one-shot pulse output (TO8N) (Initial value) * Bit 9--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 8--PK12 Mode Bit (PK12MD): Selects the function of pin PK12/TO8M. Bit 8: PK12MD Description 0 General input/output (PK12) 1 ATU-II one-shot pulse output (TO8M) (Initial value) * Bit 7--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 6--PK11 Mode Bit (PK11MD): Selects the function of pin PK11/TO8L. Bit 6: PK11MD Description 0 General input/output (PK11) 1 ATU-II one-shot pulse output (TO8L) (Initial value) * Bit 5--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 4--PK10 Mode Bit (PK10MD): Selects the function of pin PK10/TO8K. Bit 4: PK10MD Description 0 General input/output (PK10) 1 ATU-II one-shot pulse output (TO8K) (Initial value) * Bit 3--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 2--PK9 Mode Bit (PK9MD): Selects the function of pin PK9/TO8J. Bit 2: PK9MD Description 0 General input/output (PK9) 1 ATU-II one-shot pulse output (TO8J) (Initial value) * Bit 1--Reserved: This bit is always read as 0. The write value should always be 0. Rev. 5.00 Feb. 24, 2010 Page 613 of 950 REJ09B0177-0500 22. Pin Function Controller (PFC) * Bit 0--PK8 Mode Bit (PK8MD): Selects the function of pin PK8/TO8I. Bit 0: PK8MD Description 0 General input/output (PK8) 1 ATU-II one-shot pulse output (TO8I) (Initial value) Port K Control Register L (PKCRL) Bit: 15 14 13 12 11 10 9 8 -- PK7MD -- PK6MD -- PK5MD -- PK4MD Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R R/W R R/W R R/W Bit: 7 6 5 4 3 2 1 0 -- PK3MD -- PK2MD -- PK1MD -- PK0MD Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R R/W R R/W R R/W * Bit 15--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 14--PK7 Mode Bit (PK7MD): Selects the function of pin PK7/TO8H. Bit 14: PK7MD Description 0 General input/output (PK7) 1 ATU-II one-shot pulse output (TO8H) (Initial value) * Bit 13--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 12--PK6 Mode Bit (PK6MD): Selects the function of pin PK6/TO8G. Bit 12: PK6MD Description 0 General input/output (PK6) 1 ATU-II one-shot pulse output (TO8G) (Initial value) * Bit 11--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 10--PK5 Mode Bit (PK5MD): Selects the function of pin PK5/TO8F. Bit 10: PK5MD Description 0 General input/output (PK5) 1 ATU-II one-shot pulse output (TO8F) (Initial value) * Bit 9--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 8--PK4 Mode Bit (PK4MD): Selects the function of pin PK4/TO8E. Bit 8: PK4MD Description 0 General input/output (PK4) 1 ATU-II one-shot pulse output (TO8E) * Bit 7--Reserved: This bit is always read as 0. The write value should always be 0. Rev. 5.00 Feb. 24, 2010 Page 614 of 950 REJ09B0177-0500 (Initial value) 22. Pin Function Controller (PFC) * Bit 6--PK3 Mode Bit (PK3MD): Selects the function of pin PK3/TO8D. Bit 6: PK3MD Description 0 General input/output (PK3) 1 ATU-II one-shot pulse output (TO8D) (Initial value) * Bit 5--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 4--PK2 Mode Bit (PK2MD): Selects the function of pin PK2/TO8C. Bit 4: PK2MD Description 0 General input/output (PK2) 1 ATU-II one-shot pulse output (TO8C) (Initial value) * Bit 3--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 2--PK1 Mode Bit (PK1MD): Selects the function of pin PK1/TO8B. Bit 2: PK1MD Description 0 General input/output (PK1) 1 ATU-II one-shot pulse output (TO8B) (Initial value) * Bit 1--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 0--PK0 Mode Bit (PK0MD): Selects the function of pin PK0/TO8A. Bit 0: PK0MD Description 0 General input/output (PK0) 1 ATU-II one-shot pulse output (TO8A) (Initial value) 22.3.22 Port K Invert Register (PKIR) Bit: 15 14 13 12 11 10 PK15IR PK14IR PK13IR PK12IR PK11IR PK10IR Initial value: R/W: Bit: Initial value: R/W: 9 8 PK9IR PK8IR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PK7IR PK6IR PK5IR PK4IR PK3IR PK2IR PK1IR PK0IR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The port K invert register (PKIR) is a 16-bit readable/writable register that sets the port K inversion function. Bits PK15IR to PK0IR correspond to pins PK15/TO8P to PK0/TO8A. PKIR is enabled when port K pins function as ATU-II outputs, and disabled otherwise. When port K pins function as ATU-II outputs, the value of a pin is inverted when the corresponding bit in PKIR is set to 1. PKIR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. Rev. 5.00 Feb. 24, 2010 Page 615 of 950 REJ09B0177-0500 22. Pin Function Controller (PFC) PKnIR Description 0 Value is not inverted 1 Value is inverted (Initial value) Note: n = 15 to 0 22.3.23 Port L IO Register (PLIOR) Bit: 15 14 13 12 11 10 9 8 -- -- PL13 IOR PL12 IOR PL11 IOR PL10 IOR PL9 IOR PL8 IOR Initial value: 0 0 0 0 0 0 0 0 R/W: R R R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 PL7 IOR PL6 IOR PL5 IOR PL4 IOR PL3 IOR PL2 IOR PL1 IOR PL0 IOR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: R/W: The port L IO register (PLIOR) is a 16-bit readable/writable register that selects the input/output direction of the 14 pins in port L. Bits PL13IOR to PL0IOR correspond to pins PL13/IRQOUT/SCS1 to PL0/TI10. PLIOR is enabled when port L pins function as general input/output pins (PL13 to PL0), timer input/output pins (TIO11A, TIO11B), or serial clock pins (SCK2, SCK3, SCK4, SSCK1), and disabled otherwise. When port L pins function as PL13 to PL0, TIO11A and TIO11B, or SCK2, SCK3, SCK4, and SSCK1, a pin becomes an output when the corresponding bit in PLIOR is set to 1, and an input when the bit is cleared to 0. PLIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. 22.3.24 Port L Control Registers H and L (PLCRH, PLCRL) Port L control registers H and L (PLCRH, PLCRL) are 16-bit readable/writable registers that select the functions of the 14 multiplex pins in port L. PLCRH selects the functions of the pins for the upper 6 bits of port L, and PLCRL selects the functions of the pins for the lower 8 bits. PLCRH and PLCRL are initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. They are not initialized in sleep mode. Rev. 5.00 Feb. 24, 2010 Page 616 of 950 REJ09B0177-0500 22. Pin Function Controller (PFC) Port L Control Register H (PLCRH) Bit: 15 14 13 12 11 10 9 8 -- -- -- -- PL13 MD1 PL13 MD0 PL12 MD1 PL12 MD0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 PL11 MD1 PL11 MD0 PL10 MD1 PL10 MD0 PL9 MD1 PL9 MD0 -- PL8 MD 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R R/W Initial value: R/W: * Bits 15 to 12--Reserved: These bits are always read as 0. The write value should always be 0. * Bits 11 and 10--PL13 Mode Bits 1 and 0 (PL13MD1, PL13MD0): These bits select the function of pin PL13/IRQOUT/SCS1. Bit 11: PL13MD1 Bit 10: PL13MD0 Description 0 0 General input/output (PL13) 1 IRQOUT is fixed high (IRQOUT) 0 IRQOUT is output by INTC interrupt request (IRQOUT) 1 Chip select input/output (SCS1) 1 (Initial value) * Bits 9 and 8--PL12 Mode Bit 1, 0 (PL12MD1, PL12MD0): Selects the function of pin PL12/IRQ4/SCS0. Bit 9: PL12MD1 Bit 8: PL12MD0 Description 0 0 General input/output (PL12) 1 Interrupt request input (IRQ4) 0 Chip select input/output (SCS0) 1 Reserved (Do not set) 1 (Initial value) * Bits 7 and 6--PL11 Mode Bits 1 and 0 (PL11MD1, PL11MD0): These bits select the function of pin PL11/HRxD0/HRxD1. Bit 7: PL11MD1 Bit 6: PL11MD0 Description 0 0 General input/output (PL11) 1 HCAN-II receive data input (HRxD0) 0 HCAN-II receive data input (HRxD1) 1 HCAN-II receive data input (both HRxD0 and HRxD1 input) 1 (Initial value) Rev. 5.00 Feb. 24, 2010 Page 617 of 950 REJ09B0177-0500 22. Pin Function Controller (PFC) * Bits 5 and 4--PL10 Mode Bits 1 and 0 (PL10MD1, PL10MD0): These bits select the function of pin PL10/HTxD0/HTxD1. Bit 5: PL10MD1 Bit 4: PL10MD0 Description 0 0 General input/output (PL10) 1 HCAN-II transmit data output (HTxD0) 0 HCAN-II transmit data output (HTxD1) 1 HCAN-II transmit data output (AND of HTxD0 and HTxD1) 1 (Initial value) * Bits 3 and 2--PL9 Mode Bits 1 and 0 (PL9MD1, PL9MD0): These bits select the function of pin PL9/SCK4/IRQ5. Bit 3: PL9MD1 Bit 2: PL9MD0 Description 0 0 General input/output (PL9) 1 Serial clock input/output (SCK4) 0 Interrupt request input (IRQ5) 1 Reserved (Do not set) 1 (Initial value) * Bit 1--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 0--PL8 Mode Bit (PL8MD): Selects the function of pin PL8/SCK3. Bit 0: PL8MD Description 0 General input/output (PL8) 1 Serial clock input/output (SCK3) (Initial value) Port L Control Register L (PLCRL) Bit: 15 14 PL7MD1 PL7MD0 Initial value: R/W: Bit: 13 12 11 10 9 8 -- PL6MD -- PL5MD -- PL4MD 0 0 0 0 0 0 0 0 R/W R/W R R/W R R/W R R/W 7 6 5 4 3 2 1 0 -- PL0MD -- PL3MD PL2MD1 PL2MD0 PL1MD1 PL1MD0 Initial value: 0 0 0 0 0 0 0 0 R/W: R R/W R/W R/W R/W R/W R R/W * Bits 15 and 14--PL7 Mode Bit 1, 0 (PL7MD1, PL7MD0): Selects the function of pin PL7/SCK2/SSCK1. Bit 15: PL7MD1 Bit 14: PL7MD0 Description 0 0 General input/output (PL7) 1 Serial clock input/output (SCK2) 0 Serial clock output (SSCK1) 1 Reserved (Do not set) 1 Rev. 5.00 Feb. 24, 2010 Page 618 of 950 REJ09B0177-0500 (Initial value) 22. Pin Function Controller (PFC) * Bit 13--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 12--PL6 Mode Bit (PL6MD): Selects the function of pin PL6/ADEND. Bit 12: PL6MD Description 0 General input/output (PL6) 1 A/D conversion end output (ADEND) (Initial value) * Bit 11--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 10--PL5 Mode Bit (PL5MD): Selects the function of pin PL5/ADTRG1. Bit 10: PL5MD Description 0 General input/output (PL5) 1 A/D conversion trigger input (ADTRG1) (Initial value) * Bit 9--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 8--PL4 Mode Bit (PL4MD): Selects the function of pin PL4/ADTRG0. Bit 8: PL4MD Description 0 General input/output (PL4) 1 A/D conversion trigger input (ADTRG0) (Initial value) * Bit 7--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 6--PL3 Mode Bit (PL3MD): Selects the function of pin PL3/TCLKB. Bit 6: PL3MD Description 0 General input/output (PL3) 1 ATU-II clock input (TCLKB) (Initial value) * Bits 5 and 4--PL2 Mode Bits 1 and 0 (PL2MD1, PL2MD0): These bits select the function of pin PL2/TIO11B/IRQ7. Bit 5: PL2MD1 Bit 4: PL2MD0 Description 0 0 General input/output (PL2) 1 ATU-II input capture input/output compare output (TIO11B) 0 Interrupt request input (IRQ7) 1 Reserved (Do not set) 1 (Initial value) * Bits 3 and 2--PL1 Mode Bits 1 and 0 (PL1MD1, PL1MD0): These bits select the function of pin PL1/TIO11A/IRQ6. Bit 3: PL1MD1 Bit 2: PL1MD0 Description 0 0 General input/output (PL1) 1 ATU-II input capture input/output compare output (TIO11A) 0 Interrupt request input (IRQ6) 1 Reserved (Do not set) 1 (Initial value) Rev. 5.00 Feb. 24, 2010 Page 619 of 950 REJ09B0177-0500 22. Pin Function Controller (PFC) * Bit 1--Reserved: This bit is always read as 0. The write value should always be 0. * Bit 0--PL0 Mode Bit (PL0MD): Selects the function of pin PL0/TI10. Bit 0: PL0MD Description 0 General input/output (PL0) 1 ATU-II edge input (TI10) (Initial value) 22.3.25 Port L Invert Register (PLIR) Bit: 15 14 13 12 11 10 9 8 -- -- -- -- -- -- PL9IR PL8IR Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R/W R/W Bit: 7 6 5 4 3 2 1 0 PL7IR -- -- -- -- -- -- -- 0 0 0 0 0 0 0 0 R/W R R R R R R R Initial value: R/W: The port L invert register (PLIR) is a 16-bit readable/writable register that sets the port L inversion function. Bits PL9IR to PL7IR correspond to pins PL9/SCK4/IRQ5 to PL7/SCK2/SSCK1. PLIR is enabled when port L pins function as serial clock pins, and disabled otherwise. When port L pins function as serial clock pins, the value of a pin is inverted when the corresponding bit in PLIR is set to 1. PLIR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. PLnIR Description 0 Value is not inverted 1 Value is inverted Note: n = 9 to 7 Rev. 5.00 Feb. 24, 2010 Page 620 of 950 REJ09B0177-0500 (Initial value) 23. I/O Ports (I/O) Section 23 I/O Ports (I/O) 23.1 Overview This LSI has 11 ports: A, B, C, D, E, F, G, H, J, K, and L, all supporting both input and output. Ports A B, E, F, H, J, and K are 16-bit ports, port C is a 5-bit port, ports D and L are 14-bit ports, and port G is a 4-bit port. All the port pins are multiplexed as general input/output pins and special function pins. The functions of the multiplex pins are selected by means of the pin function controller (PFC). Each port is provided with a data register for storing the pin data. Each of the ports A, B, D, J, and L is provided with a port register to read the pin values. 23.2 Port A Port A is an input/output port with the 16 pins shown in figure 23.1. PA15 (I/O) /RxD0 (input) /SSI0 (input) PA14 (I/O) /TxD0 (output) /SSO0 (output) PA13 (I/O) /TIO5B (I/O) PA12 (I/O) /TIO5A (I/O) PA11 (I/O) /TIO4D (I/O) /ADTO1B (output) PA10 (I/O) /TIO4C (I/O) /ADTO1A (output) PA9 (I/O) /TIO4B (I/O) /ADTO0B (output) PA8 (I/O) /TIO4A (I/O) /ADTO0A (output) Port A PA7 (I/O) /TIO3D (I/O) PA6 (I/O) /TIO3C (I/O) PA5 (I/O) /TIO3B (I/O) PA4 (I/O) /TIO3A (I/O) PA3 (I/O) /TIOD (input) PA2 (I/O) /TIOC (input) PA1 (I/O) /TIOB (input) PA0 (I/O) /TIOA (input) Figure 23.1 Port A 23.2.1 Register Configuration The port A register configuration is shown in table 23.1. Table 23.1 Register Configuration Name Abbreviation R/W Initial Value Address Access Size Port A data register PADR R/W H'0000 H'FFFFF726 8, 16 Port A port register PAPR R Port A pin values H'FFFFF780 8, 16 Rev. 5.00 Feb. 24, 2010 Page 621 of 950 REJ09B0177-0500 23. I/O Ports (I/O) 23.2.2 Port A Data Register (PADR) Bit: 15 14 13 12 11 10 9 8 PA15 DR PA14 DR PA13 DR PA12 DR PA11 DR PA10 DR PA9 DR PA8 DR Initial value: R/W: Bit: Initial value: R/W: 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PA7 DR PA6 DR PA5 DR PA4 DR PA3 DR PA2 DR PA1 DR PA0 DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The port A data register (PADR) is a 16-bit readable/writable register that stores port A data. Bits PA15DR to PA0DR correspond to pins PA15/RxD0/SSI0 to PA0/TI0A. When a pin functions as a general output, if a value is written to PADR, that value is output directly from the pin, and if PADR is read, the register value is returned directly regardless of the pin state. When a pin functions as a general input, if PADR is read, the pin state, not the register value, is returned directly. If a value is written to PADR, although that value is written into PADR, it does not affect the pin state. Table 23.2 summarizes port A data register read/write operations. PADR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. Table 23.2 Port A Data Register (PADR) Read/Write Operations Bits 15 to 0: PAIOR Pin Function Read Write 0 General input Pin state Value is written to PADR, but does not affect pin state Other than general input Pin state Value is written to PADR, but does not affect pin state General output PADR value Write value is output from pin Other than general output PADR value Value is written to PADR, but does not affect pin state 1 23.2.3 Port A Port Register (PAPR) Bit: 15 14 13 12 11 10 9 PA15PR PA14PR PA13PR PA12PR PA11PR PA10PR PA9PR Initial value: 8 PA8PR PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 PA7PR PA6PR PA5PR PA4PR PA3PR PA2PR PA1PR PA0PR PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 R R R R R R R R Initial value: R/W: Rev. 5.00 Feb. 24, 2010 Page 622 of 950 REJ09B0177-0500 23. I/O Ports (I/O) The port A port register (PAPR) is a 16-bit read-only register that always stores the value of the port A pins. The CPU cannot write data to this register. Bits PA15PR to PA0PR correspond to pins PA15/RxD0/SSI0 to PA0/TI0A. If PAPR is read, the corresponding pin values are returned. 23.3 Port B Port B is an input/output port with the 16 pins shown in figure 23.2. PB15 (I/O) /PULS5 (output) /SCK2 (I/O) /SSCK1 (output) PB14 (I/O) /SCK1 (I/O) /TCLKB (input) /TI10 (input) PB13 (I/O) /SCK0 (I/O) /SSCK0 (output) PB12 (I/O) /TCLKA (input) /UBCTRG (output) PB11 (I/O) /RxD4 (input) /HRxD0 (input) /TO8H (output) PB10 (I/O) /TxD4 (output) /HTxD0 (output) /TO8G (output) PB9 (I/O) /RxD3 (input) /TO8F (output) PB8 (I/O) /TxD3 (output) /TO8E (output) Port B PB7 (I/O) /TO7D (output) /TO8D (output) PB6 (I/O) /TO7C (output) /TO8C (output) PB5 (I/O) /TO7B (output) /TO8B (output) PB4 (I/O) /TO7A (output) /TO8A (output) PB3 (I/O) /TO6D (output) PB2 (I/O) /TO6C (output) PB1 (I/O) /TO6B (output) PB0 (I/O) /TO6A (output) Figure 23.2 Port B 23.3.1 Register Configuration The port B register configuration is shown in table 23.3. Table 23.3 Register Configuration Name Abbreviation R/W Initial Value Address Access Size Port B data register PBDR R/W H'0000 H'FFFFF738 8, 16 Port B port register PBPR R Port B pin values H'FFFFF782 8, 16 Rev. 5.00 Feb. 24, 2010 Page 623 of 950 REJ09B0177-0500 23. I/O Ports (I/O) 23.3.2 Port B Data Register (PBDR) Bit: 15 14 13 12 11 10 9 8 PB15 DR PB14 DR PB13 DR PB12 DR PB11 DR PB10 DR PB9 DR PB8 DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PB7 DR PB6 DR PB5 DR PB4 DR PB3 DR PB2 DR PB1 DR PB0 DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: R/W: Bit: Initial value: R/W: The port B data register (PBDR) is a 16-bit readable/writable register that stores port B data. Bits PB15DR to PB0DR correspond to pins PB15/PULS5/SCK2/SSCK1 to PB0/TO6A. When a pin functions as a general output, if a value is written to PBDR, that value is output directly from the pin, and if PBDR is read, the register value is returned directly regardless of the pin state. When a pin functions as a general input, if PBDR is read, the pin state, not the register value, is returned directly. If a value is written to PBDR, although that value is written into PBDR, it does not affect the pin state. Table 23.4 summarizes port B data register read/write operations. PBDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. Table 23.4 Port B Data Register (PBDR) Read/Write Operations Bits 15 to 0: PBIOR Pin Function Read Write 0 General input Pin state Value is written to PBDR, but does not affect pin state Other than general input Pin state Value is written to PBDR, but does not affect pin state 1 General output PBDR value Write value is output from pin Other than general output PBDR value Value is written to PBDR, but does not affect pin state 23.3.3 Port B Port Register (PBPR) Bit: 15 14 13 12 11 10 9 PB15PR PB14PR PB13PR PB12PR PB11PR PB10PR PB9PR Initial value: 8 PB8PR PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 PB7PR PB6PR PB5PR PB4PR PB3PR PB2PR PB1PR PB0PR PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 R R R R R R R R Initial value: R/W: Rev. 5.00 Feb. 24, 2010 Page 624 of 950 REJ09B0177-0500 23. I/O Ports (I/O) The port B port register (PBPR) is a 16-bit read-only register that always stores the value of the port B pins. The CPU cannot write data to this register. Bits PB15PR to PB0PR correspond to pins PB15/PULS5/SCK2/SSCK1 to PB0/TO6A. If PBPR is read, the corresponding pin values are returned. 23.4 Port C Port C is an input/output port with the five pins shown in figure 23.3. PC4 (I/O) /IRQ0 (input) PC3 (I/O) /RxD2 (input) /SSI1 (input) Port C PC2 (I/O) /TxD2 (output) /SSO1 (output) PC1 (I/O) /RxD1 (input) PC0 (I/O) /TxD1 (output) Figure 23.3 Port C 23.4.1 Register Configuration The port C register configuration is shown in table 23.5. Table 23.5 Register Configuration Name Abbreviation R/W Initial Value Address Access Size Port C data register PCDR R/W H'0000 H'FFFFF73E 8, 16 Rev. 5.00 Feb. 24, 2010 Page 625 of 950 REJ09B0177-0500 23. I/O Ports (I/O) 23.4.2 Port C Data Register (PCDR) Bit: 15 14 13 12 11 10 9 8 -- -- -- -- -- -- -- -- Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 -- -- -- PC4 DR PC3 DR PC2 DR PC1 DR PC0 DR Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R/W R/W R/W R/W R/W The port C data register (PCDR) is a 16-bit readable/writable register that stores port C data. Bits PC4DR to PC0DR correspond to pins PC4/IRQ0 to PC0/TxD1. When a pin functions as a general output, if a value is written to PCDR, that value is output directly from the pin, and if PCDR is read, the register value is returned directly regardless of the pin state. When a pin functions as a general input, if PCDR is read, the pin state, not the register value, is returned directly. If a value is written to PCDR, although that value is written into PCDR, it does not affect the pin state. Table 23.6 summarizes port C data register read/write operations. PCDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. * Bits 15 to 5--Reserved: These bits are always read as 0. The write value should always be 0. Table 23.6 Port C Data Register (PCDR) Read/Write Operations Bits 4 to 0: PCIOR Pin Function Read Write 0 General input Pin state Value is written to PCDR, but does not affect pin state Other than general input Pin state Value is written to PCDR, but does not affect pin state 1 General output PCDR value Write value is output from pin Other than general output PCDR value Value is written to PCDR, but does not affect pin state Rev. 5.00 Feb. 24, 2010 Page 626 of 950 REJ09B0177-0500 23. I/O Ports (I/O) 23.5 Port D Port D is an input/output port with the 14 pins shown in figure 23.4. PD13 (I/O) /PULS6 (output) / HTxD0 (output) /HTxD1 (output) PD12 (I/O) /PULS4 (output) PD11 (I/O) /PULS3 (output) PD10 (I/O) /PULS2 (output) PD9 (I/O) /PULS1 (output) PD8 (I/O) /PULS0 (output) PD7 (I/O) /TIO1H (I/O) Port D PD6 (I/O) /TIO1G (I/O) PD5 (I/O) /TIO1F (I/O) PD4 (I/O) /TIO1E (I/O) PD3 (I/O) /TIO1D (I/O) PD2 (I/O) /TIO1C (I/O) PD1 (I/O) /TIO1B (I/O) PD0 (I/O) /TIO1A (I/O) Figure 23.4 Port D 23.5.1 Register Configuration The port D register configuration is shown in table 23.7. Table 23.7 Register Configuration Name Abbreviation R/W Initial Value Port D data register PDDR R/W H'0000 H'FFFFF746 8, 16 Port D port register PDPR R Port D pin values H'FFFFF784 8, 16 23.5.2 Address Access Size Port D Data Register (PDDR) Bit: 15 14 13 12 11 10 9 8 -- -- PD13 DR PD12 DR PD11 DR PD10 DR PD9 DR PD8 DR Initial value: 0 0 0 0 0 0 0 0 R/W: R R R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 PD7 DR PD6 DR PD5 DR PD4 DR PD3 DR PD2 DR PD1 DR PD0 DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: R/W: The port D data register (PDDR) is a 16-bit readable/writable register that stores port D data. Bits PD13DR to PD0DR correspond to pins PD13/PULS6/HTxD0/HTxD1 to PD0/TIO1A. Rev. 5.00 Feb. 24, 2010 Page 627 of 950 REJ09B0177-0500 23. I/O Ports (I/O) When a pin functions as a general output, if a value is written to PDDR, that value is output directly from the pin, and if PDDR is read, the register value is returned directly regardless of the pin state. When a pin functions as a general input, if PDDR is read, the pin state, not the register value, is returned directly. If a value is written to PDDR, although that value is written into PDDR, it does not affect the pin state. Table 23.8 summarizes port D data register read/write operations. PDDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. * Bits 15 and 14-- Reserved: These bits are always read as 0. The write value should always be 0. Table 23.8 Port D Data Register (PDDR) Read/Write Operations Bits 13 to 0: PDIOR Pin Function Read Write 0 General input Pin state Value is written to PDDR, but does not affect pin state Other than general input Pin state Value is written to PDDR, but does not affect pin state General output PDDR value Write value is output from pin Other than general output PDDR value Value is written to PDDR, but does not affect pin state 1 23.5.3 Port D Port Register (PDPR) Bit: 15 14 -- -- Initial value: 0 0 PD13 PD12 PD11 PD10 PD9 PD8 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 PD7PR PD6PR PD5PR PD4PR PD3PR PD2PR PD1PR PD0PR PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 R R R R R R R R Initial value: R/W: 13 12 11 10 9 PD13PR PD12PR PD11PR PD10PR PD9PR 8 PD8PR The port D port register (PDPR) is a 16-bit read-only register that always stores the value of the port D pins. The CPU cannot write data to this register. Bits PD13PR to PD0PR correspond to pins PD13/PULS6/HTxD0/HTxD1 to PD0/TIO1A. If PDPR is read, the corresponding pin values are returned. Rev. 5.00 Feb. 24, 2010 Page 628 of 950 REJ09B0177-0500 23. I/O Ports (I/O) 23.6 Port E Port E is an input/output port with the 16 pins shown in figure 23.5. ROM disabled ROM enabled expansion mode expansion mode Port E Singlechip mode A15 (output) PE15 (I/O) /A15 (output) PE15 (I/O) A14 (output) PE14 (I/O) /A14 (output) PE14 (I/O) A13 (output) PE13 (I/O) /A13 (output) PE13 (I/O) A12 (output) PE12 (I/O) /A12 (output) PE12 (I/O) A11 (output) PE11 (I/O) /A11 (output) PE11 (I/O) A10 (output) PE10 (I/O) /A10 (output) PE10 (I/O) A9 (output) PE9 (I/O) /A9 (output) PE9 (I/O) A8 (output) PE8 (I/O) /A8 (output) PE8 (I/O) A7 (output) PE7 (I/O) /A7 (output) PE7 (I/O) A6 (output) PE6 (I/O) /A6 (output) PE6 (I/O) A5 (output) PE5 (I/O) /A5 (output) PE5 (I/O) A4 (output) PE4 (I/O) /A4 (output) PE4 (I/O) A3 (output) PE3 (I/O) /A3 (output) PE3 (I/O) A2 (output) PE2 (I/O) /A2 (output) PE2 (I/O) A1 (output) PE1 (I/O) /A1 (output) PE1 (I/O) A0 (output) PE0 (I/O) /A0 (output) PE0 (I/O) Figure 23.5 Port E 23.6.1 Register Configuration The port E register configuration is shown in table 23.9. Table 23.9 Register Configuration Name Abbreviation R/W Initial Value Address Access Size Port E data register PEDR R/W H'0000 H'FFFFF754 8, 16 Rev. 5.00 Feb. 24, 2010 Page 629 of 950 REJ09B0177-0500 23. I/O Ports (I/O) 23.6.2 Port E Data Register (PEDR) Bit: 15 14 13 12 11 10 9 8 PE15 DR PE14 DR PE13 DR PE12 DR PE11 DR PE10 DR PE9 DR PE8 DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PE7 DR PE6 DR PE5 DR PE4 DR PE3 DR PE2 DR PE1 DR PE0 DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: R/W: Bit: Initial value: R/W: The port E data register (PEDR) is a 16-bit readable/writable register that stores port E data. Bits PE15DR to PE0DR correspond to pins PE15/A15 to PE0/A0. When a pin functions as a general output, if a value is written to PEDR, that value is output directly from the pin, and if PEDR is read, the register value is returned directly regardless of the pin state. When the POD pin is driven low, general outputs go to the high-impedance state regardless of the PEDR value. When the POD pin is driven high, the written value is output from the pin. When a pin functions as a general input, if PEDR is read, the pin state, not the register value, is returned directly. If a value is written to PEDR, although that value is written into PEDR, it does not affect the pin state. Table 23.10 summarizes port E data register read/write operations. PEDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. Table 23.10 Port E Data Register (PEDR) Read/Write Operations Bits 15 to 0: PEIOR Pin Function Read Write 0 General input Pin state Value is written to PEDR, but does not affect pin state Other than general input Pin state Value is written to PEDR, but does not affect pin state General output Write value is output from pin (POD pin = high) 1 PEDR value High impedance regardless of PEDR value (POD pin = low) Other than general output Rev. 5.00 Feb. 24, 2010 Page 630 of 950 REJ09B0177-0500 PEDR value Value is written to PEDR, but does not affect pin state 23. I/O Ports (I/O) 23.7 Port F Port F is an input/output port with the 16 pins shown in figure 23.6. ROM disabled ROM enabled expansion mode expansion mode Port F Single-chip mode PF15 (I/O) /BREQ (input) PF15 (I/O)/SCS1 (I/O) PF14 (I/O) /BACK (output) PF14 (I/O)/SCS0 (I/O) PF13 (I/O) /CS3 (output) PF13 (I/O) PF12 (I/O) /CS2 (output) PF12 (I/O) PF11 (I/O) /CS1 (output) PF11 (I/O) PF10 (I/O) /CS0 (output) PF10 (I/O) PF9 (I/O) /RD (output) PF9 (I/O) PF8 (I/O) /WAIT (input) PF8 (I/O) PF7 (I/O) /WRH (output) PF7 (I/O) PF6 (I/O) /WRL (output) PF6 (I/O) A21 (output) PF5 (I/O) /POD (input) A20 (output) PF5 (I/O) /A21 (output) / POD (input) PF4 (I/O) /A20 (output) A19 (output) PF3 (I/O) /A19 (output) PF3 (I/O) A18 (output) PF2 (I/O) /A18 (output) PF2 (I/O) A17 (output) PF1 (I/O) /A17 (output) PF1 (I/O) A16 (output) PF0 (I/O) /A16 (output) PF0 (I/O) PF4 (I/O) Figure 23.6 Port F 23.7.1 Register Configuration The port F register configuration is shown in table 23.11. Table 23.11 Register Configuration Name Abbreviation R/W Initial Value Address Access Size Port F data register PFDR R/W H'0000 H'FFFFF74E 8, 16 Rev. 5.00 Feb. 24, 2010 Page 631 of 950 REJ09B0177-0500 23. I/O Ports (I/O) 23.7.2 Port F Data Register (PFDR) Bit: 15 14 13 12 11 10 9 8 PF15 DR PF14 DR PF13 DR PF12 DR PF11 DR PF10 DR PF9 DR PF8 DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PF7 DR PF6 DR PF5 DR PF4 DR PF3 DR PF2 DR PF1 DR PF0 DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: R/W: Bit: Initial value: R/W: The port F data register (PFDR) is a 16-bit readable/writable register that stores port F data. Bits PF15DR to PF0DR correspond to pins PF15/BREQ/SCS1 to PF0/A16. When a pin functions as a general output, if a value is written to PFDR, that value is output directly from the pin, and if PFDR is read, the register value is returned directly regardless of the pin state. For pins PF0 to PF4, when the POD pin is driven low, general outputs go to the high-impedance state regardless of the PFDR value. When the POD pin is driven high, the written value is output from the pin. When a pin functions as a general input, if PFDR is read, the pin state, not the register value, is returned directly. If a value is written to PFDR, although that value is written into PFDR, it does not affect the pin state. Table 23.12 summarizes port F data register read/write operations. PFDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. Table 23.12 Port F Data Register (PFDR) Read/Write Operations Bits 15 to 5: PFIOR Pin Function Read Write 0 General input Pin state Value is written to PFDR, but does not affect pin state Other than general input Pin state Value is written to PFDR, but does not affect pin state General output PFDR value Write value is output from pin Other than general output PFDR value Value is written to PFDR, but does not affect pin state PFIOR Pin Function Read Write 0 General input Pin state Value is written to PFDR, but does not affect pin state Other than general input Pin state Value is written to PFDR, but does not affect pin state General output Write value is output from pin (POD pin = high) 1 Bits 4 to 0: 1 PFDR value High impedance regardless of PFDR value (POD pin = low) Other than general output Rev. 5.00 Feb. 24, 2010 Page 632 of 950 REJ09B0177-0500 PFDR value Value is written to PFDR, but does not affect pin state 23. I/O Ports (I/O) 23.8 Port G Port G is an input/output port with the four pins shown in figure 23.7. PG3 (I/O) /IRQ3 (input) /ADTRG0 (input) PG2 (I/O) /IRQ2 (input) /ADEND (output) Port G PG1 (I/O) /IRQ1 (input) PG0 (I/O) /PULS7 (output) /HRxD0 (input) /HRxD1 (input) Figure 23.7 Port G 23.8.1 Register Configuration The port G register configuration is shown in table 23.13. Table 23.13 Register Configuration Name Abbreviation R/W Initial Value Address Access Size Port G data register PGDR R/W H'0000 H'FFFFF764 8, 16 23.8.2 Port G Data Register (PGDR) Bit: 15 14 13 12 11 10 9 8 -- -- -- -- -- -- -- -- Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 -- -- -- -- PG3 DR PG2 DR PG1 DR PG0 DR Initial value: 0 0 0 0 0 0 0 0 R/W: R R R R R/W R/W R/W R/W The port G data register (PGDR) is a 16-bit readable/writable register that stores port G data. Bits PG3DR to PG0DR correspond to pins PG3/IRQ3/ADTRG0 to PG0/PULS7/HRxD0/HRxD1. When a pin functions as a general output, if a value is written to PGDR, that value is output directly from the pin, and if PGDR is read, the register value is returned directly regardless of the pin state. When a pin functions as a general input, if PGDR is read, the pin state, not the register value, is returned directly. If a value is written to PGDR, although that value is written into PGDR, it does not affect the pin state. Table 23.14 summarizes port G data register read/write operations. PGDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. * Bits 15 to 4--Reserved: These its are always read as 0. The write value should always be 0. Rev. 5.00 Feb. 24, 2010 Page 633 of 950 REJ09B0177-0500 23. I/O Ports (I/O) Table 23.14 Port G Data Register (PGDR) Read/Write Operations Bits 3 to 0: PGIOR Pin Function Read Write 0 General input Pin state Value is written to PGDR, but does not affect pin state Other than general input Pin state Value is written to PGDR, but does not affect pin state General output PGDR value Write value is output from pin Other than general output PGDR value Value is written to PGDR, but does not affect pin state 1 23.9 Port H Port H is an input/output port with the 16 pins shown in figure 23.8. ROM enabled expansion (Area 0: 8 bits) (Area 0: 16 bits) mode ROM disabled expansion mode Port H PH15 (I/O) / D15 (I/O) D15 (I/O) PH15 (I/O) / PH15 (I/O) D15 (I/O) PH14 (I/O) / D14 (I/O) D14 (I/O) PH14 (I/O) / PH14 (I/O) D14 (I/O) PH13 (I/O) / D13 (I/O) D13 (I/O) PH13 (I/O) / PH13 (I/O) D13 (I/O) PH12 (I/O) / D12 (I/O) D12 (I/O) PH12 (I/O) / PH12 (I/O) D12 (I/O) PH11 (I/O) / D11 (I/O) D11 (I/O) PH11 (I/O) / PH11 (I/O) D11 (I/O) PH10 (I/O) / D10 (I/O) D10 (I/O) PH10 (I/O) / PH10 (I/O) D10 (I/O) PH9 (I/O) / D9 (I/O) D9 (I/O) PH9 (I/O) / D9 (I/O) PH9 (I/O) PH8 (I/O) / D8 (I/O) D8 (I/O) PH8 (I/O) / D8 (I/O) PH8 (I/O) D7 (I/O) PH7 (I/O) / D7 (I/O) PH7 (I/O) D6 (I/O) PH6 (I/O) / D6 (I/O) PH6 (I/O) D5 (I/O) PH5 (I/O) / D5 (I/O) PH5 (I/O) D4 (I/O) PH4 (I/O) / D4 (I/O) PH4 (I/O) D3 (I/O) PH3 (I/O) / D3 (I/O) PH3 (I/O) D2 (I/O) PH2 (I/O) / D2 (I/O) PH2 (I/O) D1 (I/O) PH1 (I/O) / D1 (I/O) PH1 (I/O) D0 (I/O) PH0 (I/O) / D0 (I/O) PH0 (I/O) Figure 23.8 Port H Rev. 5.00 Feb. 24, 2010 Page 634 of 950 REJ09B0177-0500 Singlechip mode 23. I/O Ports (I/O) 23.9.1 Register Configuration The port H register configuration is shown in table 23.15. Table 23.15 Register Configuration Name Abbreviation R/W Initial Value Address Access Size Port H data register PHDR R/W H'0000 H'FFFFF72C 8, 16 23.9.2 Port H Data Register (PHDR) Bit: 15 14 13 12 11 10 9 8 PH15 DR PH14 DR PH13 DR PH12 DR PH11 DR PH10 DR PH9 DR PH8 DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PH7 DR PH6 DR PH5 DR PH4 DR PH3 DR PH2 DR PH1 DR PH0 DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: R/W: Bit: Initial value: R/W: The port H data register (PHDR) is a 16-bit readable/writable register that stores port H data. Bits PH15DR to PH0DR correspond to pins PH15/D15 to PH0/D0. When a pin functions as a general output, if a value is written to PHDR, that value is output directly from the pin, and if PHDR is read, the register value is returned directly regardless of the pin state. When the POD pin is driven low, general outputs go to the high-impedance state regardless of the PHDR value. When the POD pin is driven high, the written value is output from the pin. When a pin functions as a general input, if PHDR is read, the pin state, not the register value, is returned directly. If a value is written to PHDR, although that value is written into PHDR, it does not affect the pin state. Table 23.16 summarizes port H data register read/write operations. PHDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. Table 23.16 Port H Data Register (PHDR) Read/Write Operations Bits 15 to 0: PHIOR Pin Function Read Write 0 General input Pin state Value is written to PHDR, but does not affect pin state Other than general input Pin state Value is written to PHDR, but does not affect pin state General output Write value is output from pin (POD pin = high) 1 PHDR value High impedance regardless of PHDR value (POD pin = low) Other than general output PHDR value Value is written to PHDR, but does not affect pin state Rev. 5.00 Feb. 24, 2010 Page 635 of 950 REJ09B0177-0500 23. I/O Ports (I/O) 23.10 Port J Port J is an input/output port with the 16 pins shown in figure 23.9. PJ15 (I/O) /TI9F (input) PJ14 (I/O) /TI9E (input) PJ13 (I/O) /TI9D (input) PJ12 (I/O) /TI9C (input) PJ11 (I/O) /TI9B (input) PJ10 (I/O) /TI9A (input) PJ9 (I/O) /TIO5D (I/O) PJ8 (I/O) /TIO5C (I/O) Port J PJ7 (I/O) /TIO2H (I/O) PJ6 (I/O) /TIO2G (I/O) PJ5 (I/O) /TIO2F (I/O) PJ4 (I/O) /TIO2E (I/O) PJ3 (I/O) /TIO2D (I/O) PJ2 (I/O) /TIO2C (I/O) PJ1 (I/O) /TIO2B (I/O) PJ0 (I/O) /TIO2A (I/O) Figure 23.9 Port J 23.10.1 Register Configuration The port J register configuration is shown in table 23.17. Table 23.17 Register Configuration Name Abbreviation R/W Initial Value Port J data register PJDR R/W H'0000 H'FFFFF76C 8, 16 Port J port register PJPR R Port J pin values H'FFFFF786 8, 16 Rev. 5.00 Feb. 24, 2010 Page 636 of 950 REJ09B0177-0500 Address Access Size 23. I/O Ports (I/O) 23.10.2 Port J Data Register (PJDR) Bit: 15 14 13 12 11 10 9 8 PJ15 DR PJ14 DR PJ13 DR PJ12 DR PJ11 DR PJ10 DR PJ9 DR PJ8 DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PJ7 DR PJ6 DR PJ5 DR PJ4 DR PJ3 DR PJ2 DR PJ1 DR PJ0 DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: R/W: Bit: Initial value: R/W: The port J data register (PJDR) is a 16-bit readable/writable register that stores port J data. Bits PJ15DR to PJ0DR correspond to pins PJ15/TI9F to PJ0/TIO2A. When a pin functions as a general output, if a value is written to PJDR, that value is output directly from the pin, and if PJDR is read, the register value is returned directly regardless of the pin state. When a pin functions as a general input, if PJDR is read, the pin state, not the register value, is returned directly. If a value is written to PJDR, although that value is written into PJDR, it does not affect the pin state. Table 23.18 summarizes port J data register read/write operations. PJDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. Table 23.18 Port J Data Register (PJDR) Read/Write Operations Bits 15 to 0: PJIOR Pin Function Read Write 0 General input Pin state Value is written to PJDR, but does not affect pin state Other than general input Pin state Value is written to PJDR, but does not affect pin state 1 General output PJDR value Write value is output from pin Other than general output PJDR value Value is written to PJDR, but does not affect pin state Rev. 5.00 Feb. 24, 2010 Page 637 of 950 REJ09B0177-0500 23. I/O Ports (I/O) 23.10.3 Port J Port Register (PJPR) Bit: 15 14 13 12 11 10 PJ15PR PJ14PR PJ13PR PJ12PR PJ11PR PJ10PR Initial value: 9 8 PJ9PR PJ8PR PJ15 PJ14 PJ13 PJ12 PJ11 PJ10 PJ9 PJ8 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 PJ7PR PJ6PR PJ5PR PJ4PR PJ3PR PJ2PR PJ1PR PJ0PR PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 R R R R R R R R Initial value: R/W: The port J port register (PJPR) is a 16-bit read-only register that always stores the value of the port J pins. The CPU cannot write data to this register. Bits PJ15PR to PJ0PR correspond to pins PJ15/TI9F to PJ0/TIO2A. If PJPR is read, the corresponding pin values are returned. 23.11 Port K Port K is an input/output port with the 16 pins shown in figure 23.10. PK15 (I/O) /TO8P (output) PK14 (I/O) /TO8O (output) PK13 (I/O) /TO8N (output) PK12 (I/O) /TO8M (output) PK11 (I/O) /TO8L (output) PK10 (I/O) /TO8K (output) PK9 (I/O) /TO8J (output) Port K PK8 (I/O) /TO8I (output) PK7 (I/O) /TO8H (output) PK6 (I/O) /TO8G (output) PK5 (I/O) /TO8F (output) PK4 (I/O) /TO8E (output) PK3 (I/O) /TO8D (output) PK2 (I/O) /TO8C (output) PK1 (I/O) /TO8B (output) PK0 (I/O) /TO8A (output) Figure 23.10 Port K Rev. 5.00 Feb. 24, 2010 Page 638 of 950 REJ09B0177-0500 23. I/O Ports (I/O) 23.11.1 Register Configuration The port K register configuration is shown in table 23.19. Table 23.19 Register Configuration Name Abbreviation R/W Initial Value Address Access Size Port K data register PKDR R/W H'0000 H'FFFFF778 8, 16 23.11.2 Port K Data Register (PKDR) Bit: 15 14 13 12 11 10 9 8 PK15 DR PK14 DR PK13 DR PK12 DR PK11 DR PK10 DR PK9 DR PK8 DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PK7 DR PK6 DR PK5 DR PK4 DR PK3 DR PK2 DR PK1 DR PK0 DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: R/W: Bit: Initial value: R/W: The port K data register (PKDR) is a 16-bit readable/writable register that stores port K data. Bits PK15DR to PK0DR correspond to pins PK15/TO8P to PK0/TO8A. When a pin functions as a general output, if a value is written to PKDR, that value is output directly from the pin, and if PKDR is read, the register value is returned directly regardless of the pin state. When a pin functions as a general input, if PKDR is read, the pin state, not the register value, is returned directly. If a value is written to PKDR, although that value is written into PKDR, it does not affect the pin state. Table 23.20 summarizes port K data register read/write operations. PKDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. Table 23.20 Port K Data Register (PKDR) Read/Write Operations Bits 15 to 0: PKIOR Pin Function Read Write 0 General input Pin state Value is written to PKDR, but does not affect pin state Other than general input Pin state Value is written to PKDR, but does not affect pin state 1 General output PKDR value Write value is output from pin Other than general output PKDR value Value is written to PKDR, but does not affect pin state Rev. 5.00 Feb. 24, 2010 Page 639 of 950 REJ09B0177-0500 23. I/O Ports (I/O) 23.12 Port L Port L is an input/output port with the 14 pins shown in figure 23.11. PL13 (I/O) /IRQOUT (output) /SCS1 (I/O) PL12 (I/O) /IRQ4 (input) /SCS0 (I/O) PL11 (I/O) /HRxD0 (input) /HRxD1 (input) PL10 (I/O) /HTxD0 (output) /HTxD1 (output) PL9 (I/O) /SCK4 (I/O) /IRQ5 (input) PL8 (I/O) /SCK3 (I/O) PL7 (I/O) /SCK2 (I/O) /SSCK1 (output) Port L PL6 (I/O) /ADEND (output) PL5 (I/O) /ADTRG1 (input) PL4 (I/O) /ADTRG0 (input) PL3 (I/O) /TCLKB (I/O) PL2 (I/O) /TIO11B (I/O) /IRQ7 (input) PL1 (I/O) /TIO11A (I/O) /IRQ6 (input) PL0 (I/O) /TI10 (input) Figure 23.11 Port L 23.12.1 Register Configuration The port L register configuration is shown in table 23.21. Table 23.21 Register Configuration Name Abbreviation R/W Initial Value Address Access Size Port L data register PLDR R/W H'0000 H'FFFFF75E 8, 16 Port L port register PLPR R Port L pin values H'FFFFF788 8, 16 23.12.2 Port L Data Register (PLDR) Bit: 15 14 13 12 11 10 9 8 -- -- PL13 DR PL12 DR PL11 DR PL10 DR PL9 DR PL8 DR Initial value: 0 0 0 0 0 0 0 0 R/W: R R R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 PL7 DR PL6 DR PL5 DR PL4 DR PL3 DR PL2 DR PL1 DR PL0 DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: R/W: Rev. 5.00 Feb. 24, 2010 Page 640 of 950 REJ09B0177-0500 23. I/O Ports (I/O) The port L data register (PLDR) is a 16-bit readable/writable register that stores port L data. Bits PL13DR to PL0DR correspond to pins PL13/IRQOUT/SCS1 to PL0/TI10. When a pin functions as a general output, if a value is written to PLDR, that value is output directly from the pin, and if PLDR is read, the register value is returned directly regardless of the pin state. When a pin functions as a general input, if PLDR is read, the pin state, not the register value, is returned directly. If a value is written to PLDR, although that value is written into PLDR, it does not affect the pin state. Table 23.22 summarizes port L data register read/write operations. PLDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), in hardware standby mode, and in software standby mode. It is not initialized in sleep mode. * Bits 15 and 14--Reserved: These bits are always read as 0. The write value should always be 0. Table 23.22 Port L Data Register (PLDR) Read/Write Operations Bits 13 to 0: PLIOR Pin Function Read Write 0 General input Pin state Value is written to PLDR, but does not affect pin state Other than general input Pin state Value is written to PLDR, but does not affect pin state General output PLDR value Write value is output from pin Other than general output PLDR value Value is written to PLDR, but does not affect pin state 1 23.12.3 Port L Port Register (PLPR) Bit: 15 14 -- -- Initial value: 0 0 PL13 PL12 PL11 PL10 PL9 PL8 R/W: R R R R R R R R Bit: 7 6 5 4 3 2 1 0 PL7PR PL6PR PL5PR PL4PR PL3PR PL2PR PL1PR PL0PR PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 R R R R R R R R Initial value: R/W: 13 12 11 10 9 PL13PR PL12PR PL11PR PL10PR PL9PR 8 PL8PR The port L port register (PLPR) is a 16-bit read-only register that always stores the value of the port L pins. The CPU cannot write data to this register. Bits PL13PR to PL0PR correspond to pins PL13/IRQOUT/SCS1 to PL0/TI10. If PLPR is read, the corresponding pin values are returned. Rev. 5.00 Feb. 24, 2010 Page 641 of 950 REJ09B0177-0500 23. I/O Ports (I/O) 23.13 POD (Port Output Disable) Control The output port drive buffers for the address bus pins (A20 to A0) and data bus pins (D15 to D0) can be controlled by the POD (port output disable) pin input level. However, this function is enabled only when the address bus pins (A20 to A0) and data bus pins (D15 to D0) are designated as general output ports. Output buffer control by means of POD is performed asynchronously from bus cycles. POD Address Bus Pins (A20 to A0) and Data Bus Pins (D15 to D0) (when designated as output ports) 0 Enabled (high-impedance) 1 Disabled (general output) Rev. 5.00 Feb. 24, 2010 Page 642 of 950 REJ09B0177-0500 24. ROM (SH7058S) Section 24 ROM (SH7058S) 24.1 Features This LSI has 1-Mbyte on-chip flash memory. The flash memory has the following features. * Two flash-memory MATs according to LSI initiation mode The on-chip flash memory has two memory spaces in the same address space (hereafter referred to as memory MATs). The mode setting in the initiation determines which memory MAT is initiated first. The MAT can be switched by using the bank-switching method after initiation. The user MAT is initiated at a power-on reset in user mode: 1 Mbyte The user boot MAT is initiated at a power-on reset in user boot mode: 12 Kbytes * Three on-board programming modes and one off-board programming mode On-board programming modes Boot Mode: This mode is a program mode that uses an on-chip SCI interface. The user MAT and user boot MAT can be programmed. This mode can automatically adjust the bit rate between the host and this LSI. User Program Mode: The user MAT can be programmed by using the optional interface. User Boot Mode: The user boot program of the optional interface can be made and the user MAT can be programmed. Off-board programming mode Programmer Mode: This mode uses the PROM programmer. The user MAT and user boot MAT can be programmed. * Programming/erasing interface by the download of on-chip program This LSI has a dedicated programming/erasing program. After downloading this program to the on-chip RAM, programming/erasing can be performed by setting the argument parameter. The user branch is also supported. User branch The program processing is performed in 128-byte units. It consists the program pulse application, verify read, and several other steps. Erasing is performed in one divided-block units and consists of several steps. The user processing routine can be executed between the steps, this setting for which is called the user branch addition. * Emulation function of flash memory by using the on-chip RAM As flash memory is overlapped with part of the on-chip RAM, the flash memory programming can be emulated in real time. * Protection modes There are two protection modes. Software protection by the register setting and hardware protection by the FWE pin. The protection state for flash memory programming/erasing can be set. When abnormalities, such as runaway of programming/erasing are detected, these modes enter the error protection state and the programming/erasing processing is suspended. * Programming/erasing time The flash memory programming time is tP ms (typ) in 128-byte simultaneous programming and tP/128 ms per byte. The erasing time is tE s (typ) per block. * Number of programming The number of flash memory programming can be up to NWEC times. * Operating frequency at programming/erasing The operating frequency at programming/erasing is a maximum of 80 MHz. Rev. 5.00 Feb. 24, 2010 Page 643 of 950 REJ09B0177-0500 24. ROM (SH7058S) 24.2 Overview 24.2.1 Block Diagram Internal address bus Internal data bus (32 bits) FCCS FPCS Module bus FECS FKEY Memory MAT unit Control unit FMATS User MAT: 1 Mbyte User boot MAT: 12 Kbytes FTDAR RAMER Flash memory FWE pin Mode pins Legend: FCCS: FPCS: FECS: FKEY: FMATS: FTDAR: RAMER: Operating mode Flash code control and status register Flash program code select register Flash erase code select register Flash key code register Flash MAT select register Flash transfer destination address register RAM emulation register Figure 24.1 Block Diagram of Flash Memory Rev. 5.00 Feb. 24, 2010 Page 644 of 950 REJ09B0177-0500 24. ROM (SH7058S) 24.2.2 Operating Mode When each mode pin and the FWE pin are set in the reset state and the reset signal is released, the microcomputer enters each operating mode as shown in figure 24.2. For the setting of each mode pin and the FWE pin, see table 24.1. * Flash memory cannot be read, programmed, or erased in ROM invalid mode. The programming/erasing interface registers cannot be written to. When these registers are read, H'00 is always read. * Flash memory can be read in user mode, but cannot be programmed or erased. * Flash memory can be read, programmed, or erased on the board only in user program mode, user boot mode, and boot mode. * Flash memory can be read, programmed, or erased by means of the PROM programmer in programmer mode. RES=0 RES=0 ROM invalid mode ROM invalid mode setting Us mo er p de rog se ram ttin g S= 0 ot S= 0 mo de se ttin g 0 Us RE Bo S= er d mo RE es RE ing ett ot g bo tin er set Us de mo =0 S RE PROM mode Programmer mode setting Reset state FWE=0 User mode User boot mode User program mode FWE=1 Boot mode RAM emulation is enabled On-board programming mode Figure 24.2 Mode Transition of Flash Memory Table 24.1 Relationship between FWE and MD Pins and Operating Modes Mode Reset State ROM Invalid Mode ROM Valid Mode Pin User Program Mode User Boot Mode Boot Mode Programmer Mode RES 0 1 1 1 1 1 1 FWE 0/1 0 0 1 1 1 0/1 MD0 0/1 0/1*1 0/1*2 0/1*2 0/1*2 0/1*2 1 MD1 0/1 0 1 1 0 0 1 MD2 0/1 1 1 1 0 1 0 Notes: 1. MD0 = 0: 8-bit external bus, MD0 = 1: 16-bit external bus 2. MD0 = 0: External bus can be used, MD0 = 1: Single-chip mode (external bus cannot be used) Rev. 5.00 Feb. 24, 2010 Page 645 of 950 REJ09B0177-0500 24. ROM (SH7058S) 24.2.3 Mode Comparison The comparison table of programming and erasing related items about boot mode, user program mode, user boot mode, and programmer mode is shown in table 24.2. Table 24.2 Comparison of Programming Modes Boot Mode User Program Mode User Boot Mode Programmer Mode Programming/ erasing environment On-board programming On-board programming On-board programming Off-board programming Programming/ erasing enable MAT User MAT User boot MAT User MAT User MAT User MAT User boot MAT Programming/ erasing control Command method Programming/ erasing interface Programming/ erasing interface Command method All erasure O (Automatic) O O O (Automatic) 1 Block division erasure O* O O X Program data transfer From host via SCI From optional device via RAM From optional device via RAM Via programmer User branch function X O O X RAM emulation X O X X Reset initiation MAT Embedded program storage MAT User MAT User boot MAT*2 Embedded program storage MAT Transition to user mode Mode setting change and reset FWE setting change Mode setting change and reset -- Notes: 1. All-erasure is performed. After that, the specified block can be erased. 2. Initiation starts from the embedded program storage MAT. After checking the flash-memory related registers, initiation starts from the reset vector of the user MAT. * The user boot MAT can be programmed or erased only in boot mode and programmer mode. * The user MAT and user boot MAT are all erased in boot mode. Then, the user MAT and user boot MAT can be programmed by means of the command method. However, the contents of the MAT cannot be read until this state. Only user boot MAT is programmed and the user MAT is programmed in user boot mode or only user MAT is programmed because user boot mode is not used. * In user boot mode, the boot operation of the optional interface can be performed by a mode pin setting different from user program mode. 24.2.4 Flash Memory Configuration This LSI's flash memory is configured by the 1-Mbyte user MAT and 12-Kbyte user boot MAT. The start address is allocated to the same address in the user MAT and user boot MAT. Therefore, when the program execution or data access is performed between the two MATs, the MAT must be switched by using FMATS. The user MAT is divided into two 512-Kbyte banks (bank 0 and bank 1). The user MAT or user boot MAT can be read in all modes if it is in ROM valid mode. However, the user boot MAT can be programmed only in boot mode and programmer mode. Rev. 5.00 Feb. 24, 2010 Page 646 of 950 REJ09B0177-0500 24. ROM (SH7058S) <User MAT> <User Boot MAT> Address H'00,0000 Address H'00,0000 12 Kbytes Address H'00,2FFF Bank 0 512 Kbytes Bank 1 512 Kbytes Address H'07,FFFF Address H'08,0000 Address H'0F,FFFF Figure 24.3 Flash Memory Configuration The user MAT and user boot MAT have different memory sizes. Do not access a user boot MAT that is 12 Kbytes or more. When a user boot MAT exceeding 12 Kbytes is read from, an undefined value is read. 24.2.5 Block Division The user MAT is divided into 128 Kbytes (seven blocks), 96 Kbytes (one block), and 4 Kbytes (eight blocks) as shown in figure 24.4. The user MAT can be erased in this divided-block units and the erase-block number of EB0 to EB15 is specified when erasing. The RAM emulation can be performed in the eight blocks of 4 Kbytes. 4 Kbytes x 8 512 Kbytes 96 Kbytes Address H'07,FFFF Erase block EB0 to EB7 <User MAT: Bank 1> Address H'08,0000 * EB8 128 Kbytes EB9 128 Kbytes EB10 128 Kbytes EB11 512 Kbytes <User MAT: Bank 0> Address H'00,0000 Erase block 128 Kbytes EB12 128 Kbytes EB13 128 Kbytes EB14 128 Kbytes EB15 Address H'0F,FFFF Note: *RAM emulation can be performed in the eight blocks of 4 Kbytes. Figure 24.4 Block Division of User MAT Rev. 5.00 Feb. 24, 2010 Page 647 of 950 REJ09B0177-0500 24. ROM (SH7058S) 24.2.6 Programming/Erasing Interface Programming/erasing is executed by downloading the on-chip program to the on-chip RAM and specifying the program address/data and erase block by using the interface registers/parameters. The procedure program is made by the user in user program mode and user boot mode. The overview of the procedure is as follows. For details, see section 24.5.2, User Program Mode. Start user procedure program for programming/erasing. Select on-chip program to be downloaded and set download destination Download on-chip program by setting VBR, FKEY, and SCO bits. Initialization execution (on-chip program execution) Programming (in 128-byte units) or erasing (in one-block units) (on-chip program execution) No Programming/ erasing completed? Yes End user procedure program Figure 24.5 Overview of User Procedure Program (1) Selection of On-Chip Program to be Downloaded and Setting of Download Destination This LSI has programming/erasing programs and they can be downloaded to the on-chip RAM. The on-chip program to be downloaded is selected by setting the corresponding bits in the programming/erasing interface registers. The download destination can be specified by FTDAR. (2) Download of On-Chip Program The on-chip program is automatically downloaded by clearing VBR of the CPU to H'00000000 and then setting the SCO bit in the flash key code register (FKEY) and the flash code control and status register (FCCS), which are programming/erasing interface registers. The user MAT is replaced to the embedded program storage area when downloading. Since the flash memory cannot be read when programming/erasing, the procedure program, which is working from download to completion of programming/erasing, must be executed in a space other than the flash memory to be programmed/erased (for example, on-chip RAM). Since the result of download is returned to the programming/erasing interface parameters, whether the normal download is executed or not can be confirmed. Note that VBR can be changed after download is completed. Rev. 5.00 Feb. 24, 2010 Page 648 of 950 REJ09B0177-0500 24. ROM (SH7058S) (3) Initialization of Programming/Erasing The operating frequency and user branch are set before execution of programming/erasing. The user branch destination must be in an area other than the user MAT area which is in the middle of programming and the area where the on-chip program is downloaded. These settings are performed by using the programming/erasing interface parameters. (4) Programming/Erasing Execution To program or erase, the FWE pin must be brought high and user program mode must be entered. The program data/programming destination address is specified in 128-byte units when programming. The block to be erased is specified in erase-block units when erasing. These specifications are set by using the programming/erasing interface parameters and the on-chip program is initiated. The on-chip program is executed by using the JSR or BSR instruction to perform the subroutine call of the specified address in the on-chip RAM. The execution result is returned to the programming/erasing interface parameters. The area to be programmed must be erased in advance when programming flash memory. There are limitations and notes on the interrupt processing during programming/erasing. For details, see section 24.8.2, Interrupts during Programming/Erasing. (5) When Programming/Erasing is Executed Consecutively When the processing is not ended by the 128-byte programming or one-block erasure, the program address/data and erase-block number must be updated and consecutive programming/erasing is required. Since the downloaded on-chip program is left in the on-chip RAM after the processing, download and initialization are not required when the same processing is executed consecutively. 24.3 Pin Configuration Flash memory is controlled by the pins as shown in table 24.3. Table 24.3 Pin Configuration Pin Name Abbreviation Input/Output Function Power-on reset RES Input Reset Flash programming enable FWE Input Hardware protection when programming flash memory Mode 2 MD2 Input Sets operating mode of this LSI Mode 1 MD1 Input Sets operating mode of this LSI Mode 0 MD0 Input Sets operating mode of this LSI Transmit data TxD1 Output Serial transmit data output (used in boot mode) Receive data RxD1 Input Serial receive data input (used in boot mode) Note: For the pin configuration in PROM mode, see section 24.9, Programmer Mode. Rev. 5.00 Feb. 24, 2010 Page 649 of 950 REJ09B0177-0500 24. ROM (SH7058S) 24.4 Register Configuration 24.4.1 Registers The registers/parameters which control flash memory when the on-chip flash memory is valid are shown in table 24.4. There are several operating modes for accessing flash memory, for example, read mode/program mode. There are two memory MATs: user MAT and user boot MAT. The dedicated registers/parameters are allocated for each operating mode and MAT selection. The correspondence of operating modes and registers/parameters for use is shown in table 24.5. Table 24.4 (1) Register Configuration Name Abbreviation*4 R/W Initial Value Address Access Size Flash code control status register FCCS R, W*1 H'00*2 H'80*2 H'FFFFE800 8 Flash program code select register FPCS R/W H'00 H'FFFFE801 8 Flash erase code select register FECS R/W H'00 H'FFFFE802 8 Flash key code register FKEY R/W H'00 H'FFFFE804 8 3 Flash MAT select register FMATS R/W H'00* H'AA*3 H'FFFFE805 8 Flash transfer destination address register FTDAR R/W H'00 H'FFFFE806 8 RAM emulation register RAMER R/W H'0000 H'FFFFEC26 8, 16, 32 Notes: 1. 2. 3. 4. All registers except for RAMER can be accessed only in bytes, and the access requires three cycles. RAMER can be accessed in bytes or words, and the access requires three cycles. The bits except the SCO bit are read-only bits. The SCO bit is a programming-only bit. (The value which can be read is always 0.) The initial value is H'00 when the FWE pin goes low. The initial value is H'80 when the FWE pin goes high. The initial value at initiation in user mode or user program mode is H'00. The initial value at initiation in user boot mode is H'AA. The registers except RAMER can be accessed only in bytes, and the access requires four cycles. Since the RAMER register is in BSC, when it is accessed in bytes, the access requires four cycles, and when it is accessed in longwords, the access requires eight cycles. Rev. 5.00 Feb. 24, 2010 Page 650 of 950 REJ09B0177-0500 24. ROM (SH7058S) Table 24.4 (2) Parameter Configuration Name Abbreviation R/W Initial Value Address Access Size Download pass/fail result DPFR R/W Undefined On-chip RAM* 8, 16, 32 Flash pass/fail result FPFR R/W Undefined R0 of CPU 8, 16, 32 Flash multipurpose address area FMPAR R/W Undefined R5 of CPU 8, 16, 32 Flash multipurpose data destination area FMPDR R/W Undefined R4 of CPU 8, 16, 32 Flash erase block select FEBS R/W Undefined R4 of CPU 8, 16, 32 Flash program and erase frequency control FPEFEQ R/W Undefined R4 of CPU 8, 16, 32 Flash user branch address set parameter FUBRA R/W Undefined R5 of CPU 8, 16, 32 Note: * One byte of the start address in the on-chip RAM area specified by FTDAR is valid. Table 24.5 Register/Parameter and Target Mode Download Initialization Programming Erasure Read RAM Emulation Programming/ FCCS O -- -- -- -- -- erasing FPCS O -- -- -- -- -- interface PECS O -- -- -- -- -- registers FKEY O -- O O -- -- FMATS -- -- O*1 O*1 O*2 -- FTDAR O -- -- -- -- -- Programming/ DPFR O -- -- -- -- -- erasing FPFR O O O O -- -- interface FPEFEQ -- O -- -- -- -- FUBRA -- O -- -- -- -- FMPAR -- -- O -- -- -- parameters RAM emulation FMPDR -- -- O -- -- -- FEBS -- -- -- O -- -- RAMER -- -- -- -- -- O Notes: 1. The setting is required when programming or erasing user MAT in user boot mode. 2. The setting may be required according to the combination of initiation mode and read target MAT. Rev. 5.00 Feb. 24, 2010 Page 651 of 950 REJ09B0177-0500 24. ROM (SH7058S) 24.4.2 Programming/Erasing Interface Registers The programming/erasing interface registers are as described below. They are all 8-bit registers that can be accessed in bytes. These registers are initialized at a power-on reset, in hardware standby mode, or in software standby mode. (1) Flash Code Control and Status Register (FCCS) FCCS is configured by bits which request the monitor of the FWE pin state and error occurrence during programming or erasing flash memory and the download of the on-chip program. Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 FWE -- -- FLER -- -- -- SCO 1/0 0 0 0 0 0 0 R R R R R R R 0 (R)W * Bit 7--Flash Programming Enable (FWE): Monitors the level which is input to the FWE pin that performs hardware protection of the flash memory programming or erasing. The initial value is 0 or 1 according to the FWE pin state. Bit 7 FWE Description 0 When the FWE pin goes low (in hardware protection state) 1 When the FWE pin goes high * Bits 6 and 5--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 4--Flash Memory Error (FLER): Indicates an error occurs during programming and erasing flash memory. When FLER is set to 1, flash memory enters the error protection state. This bit is initialized at a power-on reset or in hardware standby mode. When FLER is set to 1, high voltage is applied to the internal flash memory. To reduce the damage to flash memory, the reset signal must be released after the reset period of 100 s which is longer than normal. Bit 4 FLER Description 0 Flash memory operates normally Programming/erasing protection for flash memory (error protection) is invalid. [Clearing condition] At a power-on reset or in hardware standby mode 1 Indicates an error occurs during programming/erasing flash memory. Programming/erasing protection for flash memory (error protection) is valid. [Setting condition] See section 24.6.3, Error Protection. (Initial value) * Bits 3 to 1--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 0--Source Program Copy Operation (SCO): Requests the on-chip programming/erasing program to be downloaded to the on-chip RAM. When this bit is set to 1, the on-chip program which is selected by FPCS/FECS is automatically downloaded in the onchip RAM area specified by FTDAR. In order to set this bit to 1, RAM emulation state must be canceled, H'A5 must be written to FKEY, and this operation must be in the on-chip RAM. Eight NOP instructions must be executed immediately after setting this bit to 1. Rev. 5.00 Feb. 24, 2010 Page 652 of 950 REJ09B0177-0500 24. ROM (SH7058S) For interrupts during download, see section 24.8.2, Interrupts during Programming/Erasing. For the download time, see section 24.8.3, Other Notes. Since this bit is cleared to 0 when download is completed, this bit cannot be read as 1. Download by setting the SCO bit to 1 requires a special interrupt processing that performs bank switching to the on-chip program storage area. Therefore, before issuing a download request (SCO = 1), set VBR to H'00000000. Otherwise, the CPU gets out of control. Once download end is confirmed, VBR can be changed to any other value. Bit 0 SCO Description 0 Download of the on-chip programming/erasing program to the on-chip RAM is not executed (Initial value) [Clearing condition] When download is completed 1 Request that the on-chip programming/erasing program is downloaded to the on-chip RAM is generated [Clearing conditions] When all of the following conditions are satisfied and 1 is written to this bit * FKEY is written to H'A5 * During execution in the on-chip RAM * Not in RAM emulation mode (RAMS in RAMCR = 0) (2) Flash Program Code Select Register (FPCS) FPCS selects the on-chip programming program to be downloaded. Bit : 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 -- 0 PPVS Initial value : 0 0 0 0 0 0 0 0 R/W : R R R R R R R R/W * Bits 7 to 1--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 0--Program Pulse Single (PPVS): Selects the programming program. Bit 0 PPVS Description 0 On-chip programming program is not selected (Initial value) [Clearing condition] When transfer is completed 1 On-chip programming program is selected (3) Flash Erase Code Select Register (FECS) FECS selects download of the on-chip erasing program. Bit : 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 -- 0 EPVB Initial value : 0 0 0 0 0 0 0 0 R/W : R R R R R R R R/W * Bits 7 to 1--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 0--Erase Pulse Verify Block (EPVB): Selects the erasing program. Rev. 5.00 Feb. 24, 2010 Page 653 of 950 REJ09B0177-0500 24. ROM (SH7058S) Bit 0 EPVB Description 0 On-chip erasing program is not selected (Initial value) [Clearing condition] When transfer is completed 1 On-chip erasing program is selected (4) Flash Key Code Register (FKEY) FKEY is a register for software protection that enables download of the on-chip program and programming/erasing of flash memory. Before setting the SCO bit to 1 in order to download the on-chip program or executing the downloaded programming/erasing program, these processings cannot be executed if the key code is not written. Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 K7 K6 K5 K4 K3 K2 K1 K0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W * Bits 7 to 0--Key Code (K7 to K0): Only when H'A5 is written, writing to the SCO bit is valid. When a value other than H'A5 is written to FKEY, 1 cannot be written to the SCO bit. Therefore downloading to the on-chip RAM cannot be executed. Only when H'5A is written, programming/erasing of flash memory can be executed. Even if the on-chip programming/erasing program is executed, flash memory cannot be programmed or erased when a value other than H'5A is written to FKEY. Bits 7 to 0 K7 to K0 Description H'A5 Writing to the SCO bit is enabled (The SCO bit cannot be set by a value other than H'A5.) H'5A Programming/erasing is enabled (A value other than H'A5 enables software protection state.) H'00 Initial value (5) Flash MAT Select Register (FMATS) FMATS specifies whether user MAT or user boot MAT is selected. Bit : Initial value : Initial value : R/W : 7 MS7 0 1 R/W 6 MS6 0 0 R/W 5 MS5 0 1 R/W 4 MS4 0 0 R/W 3 MS3 0 1 R/W 2 MS2 0 0 R/W 1 MS1 0 1 R/W 0 MS0 0 0 R/W (When not in user boot mode) (When in user boot mode) * Bits 7 to 0--MAT Select (MS7 to MS0): These bits are in user-MAT selection state when a value other than H'AA is written and in user-boot-MAT selection state when H'AA is written. The MAT is switched by writing a value in FMATS. When the MAT is switched, follow section 24.8.1, Switching between User MAT and User Boot MAT. (The user boot MAT cannot be programmed in user programming mode if user boot MAT is selected by FMATS. The user boot MAT must be programmed in boot mode or in programmer mode.) Rev. 5.00 Feb. 24, 2010 Page 654 of 950 REJ09B0177-0500 24. ROM (SH7058S) Bits 7 to 0 MS7 to MS0 Description H'AA The user boot MAT is selected (in user-MAT selection state when the value of these bits are other than H'AA) Initial value when these bits are initiated in user boot mode. H'00 Initial value when these bits are initiated in a mode except for user boot mode (in user-MAT selection state) [Programmable condition] These bits are in the execution state in the on-chip RAM. (6) Flash Transfer Destination Address Register (FTDAR) FTDAR specifies the on-chip RAM address to which the on-chip program is downloaded. Make settings for FTDAR before writing 1 to the SCO bit in FCCS. The initial value is H'00 which points to the start address (H'FFFF0000) in on-chip RAM. Bit : Initial value : R/W : 7 TDER 0 6 TDA6 0 5 TDA5 0 4 TDA4 0 3 TDA3 0 2 TDA2 0 1 TDA1 0 0 TDA0 0 R/W R/W R/W R/W R/W R/W R/W R/W * Bit 7--Transfer Destination Address Setting Error: This bit is set to 1 when there is an error in the download start address set by bits 6 to 0 (TDA6 to TDA0). Whether the address setting is erroneous or not is judged by checking whether the setting of TDA6 to TDA0 is between the range of H'00 and H'05 after setting the SCO bit in FCCS to 1 and performing download. Before setting the SCO bit to 1 be sure to set the FTDAR value between H'00 to H'05 as well as clearing this bit to 0. Bit 7 TDER Description (Return Value after Download) 0 Setting of TDA6 to TDA0 is normal 1 Setting of TDER and TDA6 to TDA0 is H'06 to H'FF and download has been aborted (Initial value) * Bits 6 to 0--Transfer Destination Address (TDA6 to TDA0): These bits specify the download start address. A value from H'00 to H'05 can be set to specify the download start address in on-chip RAM in 2-Kbyte units. A value from H'06 to H'FF cannot be set. If such a value is set, the TDER bit (bit 7) in this register is set to 1 to prevent download from being executed. Bits 6 to 0 TDA6 to TDA0 Description H'00 Download start address is set to H'FFFF0000 H'01 Download start address is set to H'FFFF0800 H'02 Download start address is set to H'FFFF1000 H'03 Download start address is set to H'FFFF1800 H'04 Download start address is set to H'FFFF2000 H'05 Download start address is set to H'FFFF2800 H'06 to H'FF Setting prohibited. If this value is set, the TDER bit (bit 7) is set to 1 to abort the download processing. Rev. 5.00 Feb. 24, 2010 Page 655 of 950 REJ09B0177-0500 24. ROM (SH7058S) 24.4.3 Programming/Erasing Interface Parameters The programming/erasing interface parameters specify the operating frequency, user branch destination address, storage place for program data, programming destination address, and erase block and exchanges the processing result for the downloaded on-chip program. This parameter uses the general registers of the CPU (R4, R5, and R0) or the on-chip RAM area. The initial value is undefined at a power-on reset, in hardware standby mode, or in software standby mode. At download all CPU registers are stored, and at initialization or when the on-chip program is executed, CPU registers except for R0 are stored. The return value of the processing result is written in R0. Since the stack area is used for storing the registers or as a work area, the stack area must be saved at the processing start. (The maximum size of a stack area to be used is 128 bytes.) The programming/erasing interface parameters are used in the following four items. (1) Download control (2) Initialization before programming or erasing (3) Programming (4) Erasing These items use different parameters. The correspondence table is shown in table 24.6. The processing results of initialization, programming, and erasing are returned, but the bit contents have different meanings according to the processing program. See the description of FPFR for each processing. Table 24.6 Usable Parameters and Target Modes Name of Parameter Abbreviation Down-load Initialization Programming Erasure R/W Initial Value Allocation Download DPFR pass/fail result O -- -- -- R/W Undefined On-chip RAM* Flash pass/fail FPFR result -- O O O R/W Undefined R0 of CPU Flash FPEFEQ programming/ erasing frequency control -- O -- -- R/W Undefined R4 of CPU Flash user branch address set parameter FUBRA -- O -- -- R/W Undefined R5 of CPU Flash multipurpose address area FMPAR -- -- O -- R/W Undefined R5 of CPU Flash multipurpose data destination area FMPDR -- -- O -- R/W Undefined R4 of CPU Flash erase block select FEBS -- -- -- O R/W Undefined R4 of CPU Note: * One byte of start address of download destination specified by FTDAR Rev. 5.00 Feb. 24, 2010 Page 656 of 950 REJ09B0177-0500 24. ROM (SH7058S) (1) Download Control The on-chip program is automatically downloaded by setting the SCO bit to 1. The on-chip RAM area to be downloaded is the area as much as 3 Kbytes starting from the start address specified by FTDAR. For the address map of the on-chip RAM, see figure 24.10. The download control is set by using the programming/erasing interface registers. The return value is given by the DPFR parameter. (a) Download pass/fail result parameter (DPFR: one byte of start address of on-chip RAM specified by FTDAR) This parameter indicates the return value of the download result. The value of this parameter can be used to determine if downloading is executed or not. Since the confirmation whether the SCO bit is set to 1 is difficult, the certain determination must be performed by setting one byte of the start address of the on-chip RAM area specified by FTDAR to a value other than the return value of download (for example, H'FF) before the download start (before setting the SCO bit to 1). For the checking method of download results, see section 24.5.2, User Program Mode. Bit : 7 6 5 4 3 2 1 0 0 0 0 0 0 SS FK SF * Bits 7 to 3--Unused: Return 0. * Bit 2--Source Select Error Detect (SS): The on-chip program which can be downloaded can be specified as only one type. When more than two types of the program are selected, the program is not selected, or the program is selected without mapping, an error occurs. Bit 2 SS Description 0 Download program can be selected normally 1 Download error occurs (Multi-selection or program which is not mapped is selected) * Bit 1--Flash Key Register Error Detect (FK): Returns the check result whether the value of FKEY is set to H'A5. Bit 1 FK Description 0 FKEY setting is normal (FKEY = H'A5) 1 FKEY setting is abnormal (FKEY = value other than H'A5) * Bit 0--Success/Fail (SF): Returns the result whether download has ended normally or not. Bit 0 SF Description 0 Downloading on-chip program has ended normally (no error) 1 Downloading on-chip program has ended abnormally (error occurs) (2) Programming/Erasing Initialization The on-chip programming/erasing program to be downloaded includes the initialization program. The specified period pulse must be applied when programming or erasing. The specified pulse width is made by the method in which wait loop is configured by the CPU instruction. The operating frequency of the CPU must be set. Since the user branch function is supported, the user branch destination address must be set. The initial program is set as a parameter of the programming/erasing program which has downloaded these settings. Rev. 5.00 Feb. 24, 2010 Page 657 of 950 REJ09B0177-0500 24. ROM (SH7058S) (2.1) Flash programming/erasing frequency parameter (FPEFEQ: general register R4 of CPU) This parameter sets the operating frequency of the CPU. For the range of the operating frequency of this LSI, see section 29.3.2, Clock Timing. Bit : Bit : Bit : Bit : 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 F15 F14 F13 F12 F11 F10 F9 F8 7 6 5 4 3 2 1 0 F7 F6 F5 F4 F3 F2 F1 F0 * Bits 31 to 16--Unused: Return 0. * Bits 15 to 0--Frequency Set (F15 to F0): Set the operating frequency of the CPU. The setting value must be calculated as the following methods. 1. The operating frequency which is shown in MHz units must be rounded in a number to three decimal places and be shown in a number of two decimal places. 2. The centuplicated value is converted to the binary digit and is written to the FPEFEQ parameter (general register R4). For example, when the operating frequency of the CPU is 28.882 MHz, the value is as follows. 1. The number to three decimal places of 28.882 is rounded and the value is thus 28.88. 2. The formula that 28.88 x 100 = 2888 is converted to the binary digit and b'0000, 1011, 0100, 1000 (H'0B48) is set to R4. (2.2) Flash user branch address setting parameter (FUBRA: general register R5 of CPU) This parameter sets the user branch destination address. The user program which has been set can be executed in specified processing units when programming and erasing. Bit : 31 UA31 30 UA30 29 UA29 28 UA28 27 UA27 26 UA26 25 UA25 24 UA24 Bit : 23 UA23 22 UA22 21 UA21 20 UA20 19 UA19 18 UA18 17 UA17 16 UA16 Bit : 15 UA15 14 UA14 13 UA13 12 UA12 11 UA11 10 UA10 9 UA9 8 UA8 Bit : 7 UA7 6 UA6 5 UA5 4 UA4 3 UA3 2 UA2 1 UA1 0 UA0 * Bits 31 to 0--User Branch Destination Address (UA31 to UA0): When the user branch is not required, address 0 (H'00000000) must be set. The user branch destination must be an area other than the flash memory, an area other than the RAM area in which onchip program has been transferred, or the external bus space. Note that the CPU must not branch to an area without the execution code and get out of control. The on-chip program download area and stack area must not be overwritten. If CPU runaway occurs or the download area or stack area is overwritten, the value of flash memory cannot be guaranteed. Rev. 5.00 Feb. 24, 2010 Page 658 of 950 REJ09B0177-0500 24. ROM (SH7058S) The download of the on-chip program, initialization, initiation of the programming/erasing program must not be executed in the processing of the user branch destination. Programming or erasing cannot be guaranteed when returning from the user branch destination. The program data which has already been prepared must not be programmed. Store general registers R8 to R15 and the control register (GBR). General registers R0 to R7 are available without storing them. Moreover, the programming/erasing interface registers must not be written to or RAM emulation mode must not be entered in the processing of the user branch destination. After the processing of the user branch has ended, the programming/erasing program must be returned to by using the RTS instruction. For the execution intervals of the user branch processing, see note 2 (User branch processing intervals) in section 24.8.3, Other Notes. (2.3) Flash pass/fail result parameter (FPFR: general register R0 of CPU) This parameter indicates the return value of the initialization result. Bit : Bit : Bit : Bit : 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 BR FQ SF * Bits 31 to 3--Unused: Return 0. * Bit 2--User Branch Error Detect (BR): Returns the check result whether the specified user branch destination address is in the area other than the storage area of the programming/erasing program which has been downloaded . Bit 2 BR Description 0 User branch address setting is normal 1 User branch address setting is abnormal * Bit 1--Frequency Error Detect (FQ): Returns the check result whether the specified operating frequency of the CPU is in the range of the supported operating frequency. Bit 1 FQ Description 0 Setting of operating frequency is normal 1 Setting of operating frequency is abnormal * Bit 0--Success/Fail (SF): Indicates whether initialization is completed normally. Rev. 5.00 Feb. 24, 2010 Page 659 of 950 REJ09B0177-0500 24. ROM (SH7058S) Bit 0 SF Description 0 Initialization has ended normally (no error) 1 Initialization has ended abnormally (error occurs) (3) Programming Execution When flash memory is programmed, the programming destination address on the user MAT must be passed to the programming program in which the program data is downloaded. 1. The start address of the programming destination on the user MAT is set in general register R5 of the CPU. This parameter is called FMPAR (flash multipurpose address area parameter). Since the program data is always in 128-byte units, the lower eight bits (MOA7 to MOA0) must be H'00 or H'80 as the boundary of the programming start address on the user MAT. 2. The program data for the user MAT must be prepared in the consecutive area. The program data must be in the consecutive space which can be accessed by using the MOV.B instruction of the CPU and is not the flash memory space. When data to be programmed does not satisfy 128 bytes, the 128-byte program data must be prepared by embedding the dummy code (H'FF). The start address of the area in which the prepared program data is stored must be set in general register R4. This parameter is called FMPDR (flash multipurpose data destination area parameter). For details on the programming procedure, see section 24.5.2, User Program Mode. (3.1) Flash multipurpose address area parameter (FMPAR: general register R5 of CPU) This parameter indicates the start address of the programming destination on the user MAT. When an address in an area other than the flash memory space is set, an error occurs. The start address of the programming destination must be at the 128-byte boundary. If this boundary condition is not satisfied, an error occurs. The error occurrence is indicated by the WA bit (bit 1) in FPFR. Bit : 31 MOA31 30 MOA30 29 MOA29 28 MOA28 27 MOA27 26 MOA26 25 MOA25 24 MOA24 Bit : 23 MOA23 22 MOA22 21 MOA21 20 MOA20 19 MOA19 18 MOA18 17 MOA17 16 MOA16 Bit : 15 MOA15 14 MOA14 13 MOA13 12 MOA12 11 MOA11 10 MOA10 9 MOA9 8 MOA8 Bit : 7 MOA7 6 MOA6 5 MOA5 4 MOA4 3 MOA3 2 MOA2 1 MOA1 0 MOA0 * Bits 31 to 0--MOA31 to MOA0: Store the start address of the programming destination on the user MAT. The consecutive 128-byte programming is executed starting from the specified start address of the user MAT. The MOA6 to MOA0 bits are always 0 because the start address of the programming destination is at the 128-byte boundary. (3.2) Flash multipurpose data destination parameter (FMPDR: general register R4 of CPU) This parameter indicates the start address in the area which stores the data to be programmed in the user MAT. When the storage destination of the program data is in flash memory, an error occurs. The error occurrence is indicated by the WD bit (bit 2) in FPFR. Rev. 5.00 Feb. 24, 2010 Page 660 of 950 REJ09B0177-0500 24. ROM (SH7058S) Bit : 31 MOD31 30 MOD30 29 MOD29 28 MOD28 27 MOD27 26 MOD26 25 MOD25 24 MOD24 Bit : 23 MOD23 22 MOD22 21 MOD21 20 MOD20 19 MOD19 18 MOD18 17 MOD17 16 MOD16 Bit : 15 MOD15 14 MOD14 13 MOD13 12 MOD12 11 MOD11 10 MOD10 9 MOD9 8 MOD8 Bit : 7 MOD7 6 MOD6 5 MOD5 4 MOD4 3 MOD3 2 MOD2 1 MOD1 0 MOD0 * Bits 31 to 0--MOD31 to MOD0: Store the start address of the area which stores the program data for the user MAT. The consecutive 128-byte data is programmed to the user MAT starting from the specified start address. (3.3) Flash pass/fail parameter (FPFR: general register R0 of CPU) This parameter indicates the return value of the program processing result. Bit : Bit : Bit : Bit : 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 MD EE FK 0 WD WA SF * Bits 31 to 7--Unused: Return 0. * Bit 6--Programming Mode Related Setting Error Detect (MD): Returns the check result of whether the signal input to the FWE pin is high and whether the error protection state is entered. When a low-level signal is input to the FWE pin or the error protection state is entered, 1 is written to this bit. The input level to the FWE pin and the error protection state can be confirmed with the FWE bit (bit 7) and the FLER bit (bit 4) in FCCS, respectively. For conditions to enter the error protection state, see section 24.6.3, Error Protection. Bit 6 MD Description 0 FWE and FLER settings are normal (FWE = 1, FLER = 0) 1 FWE = 0 or FLER = 1, and programming cannot be performed * Bit 5--Programming Execution Error Detect (EE): 1 is returned to this bit when the specified data could not be written because the user MAT was not erased or when flash-memory related register settings are partially changed on returning from the user branch processing. If this bit is set to 1, there is a high possibility that the user MAT is partially rewritten. In this case, after removing the error factor, erase the user MAT. If FMATS is set to H'AA and the user boot MAT is selected, an error occurs when programming is performed. In this case, both the user MAT and user boot MAT are not rewritten. Programming of the user boot MAT must be executed in boot mode or programmer mode. Rev. 5.00 Feb. 24, 2010 Page 661 of 950 REJ09B0177-0500 24. ROM (SH7058S) Bit 5 EE Description 0 Programming has ended normally 1 Programming has ended abnormally (programming result is not guaranteed) * Bit 4--Flash Key Register Error Detect (FK): Returns the check result of the value of FKEY before the start of the programming processing. Bit 4 FK Description 0 FKEY setting is normal (FKEY = H'A5) 1 FKEY setting is error (FKEY = value other than H'A5) * Bit 3--Unused: Returns 0. * Bit 2--Write Data Address Detect (WD): When an address in the flash memory area is specified as the start address of the storage destination of the program data, an error occurs. Bit 2 WD Description 0 Setting of write data address is normal 1 Setting of write data address is abnormal * Bit 1--Write Address Error Detect (WA): When the following items are specified as the start address of the programming destination, an error occurs. 1. The programming destination address is an area other than flash memory 2. The specified address is not at the 128-byte boundary (A6 to A0 are not 0) Bit 1 WA Description 0 Setting of programming destination address is normal 1 Setting of programming destination address is abnormal * Bit 0--Success/Fail (SF): Indicates whether the program processing has ended normally or not. Bit 0 SF Description 0 Programming has ended normally (no error) 1 Programming has ended abnormally (error occurs) (4) Erasure Execution When flash memory is erased, the erase-block number on the user MAT must be passed to the erasing program which is downloaded. This is set to the FEBS parameter (general register R4). One block is specified from the block number 0 to 15. For details on the erasing procedure, see section 24.5.2, User Program Mode. Rev. 5.00 Feb. 24, 2010 Page 662 of 950 REJ09B0177-0500 24. ROM (SH7058S) (4.1) Flash erase block select parameter (FEBS: general register R4 of CPU) This parameter specifies the erase-block number. Several block numbers cannot be specified. Bit : Bit : Bit : Bit : 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 EBS7 EBS6 EBS5 EBS4 EBS3 EBS2 EBS1 EBS0 * Bits 31 to 8--Unused: Return 0. * Bits 7 to 0--Erase Block (EB7 to EB0): Set the erase-block number in the range from 0 to 15. 0 corresponds to the EB0 block and 15 corresponds to the EB15 block. An error occurs when a number other than 0 to 15 (H'00 to H'0F) is set. (4.2) Flash pass/fail result parameter (FPFR: general register R0 of CPU) This parameter returns the value of the erasing processing result. Bit : Bit : Bit : Bit : 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 MD EE FK EB 0 0 SF * Bits 31 to 7--Unused: Return 0. * Bit 6--Erasure Mode Related Setting Error Detect (MD): Returns the check result of whether the signal input to the FWE pin is high and whether the error protection state is entered. When a low-level signal is input to the FWE pin or the error protection state is entered, 1 is written to this bit. The input level to the FWE pin and the error protection state can be confirmed with the FWE bit (bit 7) and the FLER bit (bit 4) in FCCS, respectively. For conditions to enter the error protection state, see section 24.6.3, Error Protection. Bit 6 MD Description 0 FWE and FLER settings are normal (FWE = 1, FLER = 0) 1 FWE = 0 or FLER = 1, and erasure cannot be performed * Bit 5--Erasure Execution Error Detect (EE): 1 is returned to this bit when the user MAT could not be erased or when flash-memory related register settings are partially changed on returning from the user branch processing. If this bit is set to 1, there is a high possibility that the user MAT is partially erased. In this case, after removing the error factor, erase the user MAT. Rev. 5.00 Feb. 24, 2010 Page 663 of 950 REJ09B0177-0500 24. ROM (SH7058S) If FMATS is set to H'AA and the user boot MAT is selected, an error occurs when erasure is performed. In this case, both the user MAT and user boot MAT are not erased. Erasure of the user boot MAT must be executed in boot mode or programmer mode. Bit 5 EE Description 0 Erasure has ended normally 1 Erasure has ended abnormally (erasure result is not guaranteed) * Bit 4--Flash Key Register Error Detect (FK): Returns the check result of FKEY value before start of the erasing processing. Bit 4 FK Description 0 FKEY setting is normal (FKEY = H'5A) 1 FKEY setting is error (FKEY = value other than H'5A) * Bit 3--Erase Block Select Error Detect (EB): Returns the check result whether the specified erase-block number is in the block range of the user MAT. Bit 3 EB Description 0 Setting of erase-block number is normal 1 Setting of erase-block number is abnormal * Bits 2 and 1--Unused: Return 0. * Bit 0--Success/Fail (SF): Indicates whether the erasing processing has ended normally or not. Bit 0 SF Description 0 Erasure has ended normally (no error) 1 Erasure has ended abnormally (error occurs) 24.4.4 RAM Emulation Register (RAMER) When the realtime programming of the user MAT is emulated, RAMER sets the area of the user MAT which is overlapped with a part of the on-chip RAM. RAMER is initialized to H'0000 at a power-on reset or in hardware standby mode, or in software standby mode. The RAMER setting must be executed in user mode or in user program mode. For the division method of the user-MAT area, see table 24.7. In order to operate the emulation function certainly, the target MAT of the RAM emulation must not be accessed immediately after RAMER is programmed. If it is accessed, the normal access is not guaranteed. Rev. 5.00 Feb. 24, 2010 Page 664 of 950 REJ09B0177-0500 24. ROM (SH7058S) Bit : 15 14 13 12 11 10 9 8 Initial value : R/W : 0 0 0 0 0 0 0 0 R R R R R R R R Bit : 7 6 5 4 3 2 1 0 RAMS RAM2 RAM1 RAM0 Initial value : R/W : 0 0 0 0 0 0 0 0 R R R R R/W R/W R/W R/W * Bits 15 to 4--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 3--RAM Select (RAMS): Sets whether the user MAT is emulated or not. When RAMS = 1, all blocks of the user MAT are in the programming/erasing protection state. Bit 3 RAMS Description 0 Emulation is not selected Programming/erasing protection of all user-MAT blocks is invalid 1 Emulation is selected Programming/erasing protection of all user-MAT blocks is valid (Initial value) * Bits 2 to 0--User MAT Area Select: These bits are used with bit 3 to select the user-MAT area to be overlapped with the on-chip RAM. (See table 24.7.) Table 24.7 Overlapping of RAM Area and User MAT Area RAM Area Block Name RAMS H'FFFF0000 to H'FFFF0FFF RAM area (4 Kbytes) 0 H'00000000 to H'00000FFF EB0 (4 Kbytes) 1 H'00001000 to H'00001FFF EB1 (4 Kbytes) 1 H'00002000 to H'00002FFF EB2 (4 Kbytes) H'00003000 to H'00003FFF RAM2 RAM1 RAM0 * * * 0 0 0 0 0 1 1 0 1 0 EB3 (4 Kbytes) 1 0 1 1 H'00004000 to H'00004FFF EB4 (4 Kbytes) 1 1 0 0 H'00005000 to H'00005FFF EB5 (4 Kbytes) 1 1 0 1 H'00006000 to H'00006FFF EB6 (4 Kbytes) 1 1 1 0 H'00007000 to H'00007FFF EB7 (4 Kbytes) 1 1 1 1 Legend: * Don't care. Rev. 5.00 Feb. 24, 2010 Page 665 of 950 REJ09B0177-0500 24. ROM (SH7058S) 24.5 On-Board Programming Mode When the pin is set in on-board programming mode and the reset start is executed, the on-board programming state that can program/erase the on-chip flash memory is entered. On-board programming mode has three operating modes: user programming mode, user boot mode, and boot mode. For details on the pin setting for entering each mode, see table 24.1. For details on the state transition of each mode for flash memory, see figure 24.2. 24.5.1 Boot Mode Boot mode executes programming/erasing user MAT and user boot MAT by means of the control command and program data transmitted from the host using the on-chip SCI. The tool for transmitting the control command and program data must be prepared in the host. The SCI communication mode is set to asynchronous mode. When reset start is executed after this LSI's pin is set in boot mode, the boot program in the microcomputer is initiated. After the SCI bit rate is automatically adjusted, the communication with the host is executed by means of the control command method. The RAM areas used by boot mode are 3 Kbytes starting at address H'FFFF0000, 4 Kbytes starting at address H'FFFFB000, and 128 bytes from H'FFFFBF80 to H'FFFFBFFF, which are used as the stack. The system configuration diagram in boot mode is shown in figure 24.6. For details on the pin setting in boot mode, see table 24.1. Interrupts are ignored in boot mode, so do not generate them. Note that the AUD cannot be used during boot mode operation. This LSI Host Boot Control command, program data programming tool and program data Reply response Control command, analysis execution software (on-chip) Flash memory RxD1 On-chip SCI1 TxD1 On-chip RAM Figure 24.6 System Configuration in Boot Mode (1) SCI Interface Setting by Host When boot mode is initiated, this LSI measures the low period of asynchronous SCI-communication data (H'00), which is transmitted consecutively by the host. The SCI transmit/receive format is set to 8-bit data, 1 stop bit, and no parity. This LSI calculates the bit rate of transmission by the host by means of the measured low period and transmits the bit adjustment end sign (1 byte of H'00) to the host. The host must confirm that this bit adjustment end sign (H'00) has been received normally and transmits 1 byte of H'55 to this LSI. When reception is not executed normally, boot mode is initiated again (reset) and the operation described above must be executed. The bit rate between the host and this LSI is not matched because of the bit rate of transmission by the host and system clock frequency of this LSI. To operate the SCI normally, the transfer bit rate of the host must be set to 9,600 bps or 19,200 bps. The system clock frequency which can automatically adjust the transfer bit rate of the host and the bit rate of this LSI is shown in table 24.8. Boot mode must be initiated in the range of this system clock. Rev. 5.00 Feb. 24, 2010 Page 666 of 950 REJ09B0177-0500 24. ROM (SH7058S) Start bit D0 D1 D2 D3 D4 D5 Measure low period (9 bits) (data is H'00) D6 D7 Stop bit High period of at least 1 bit Figure 24.7 Automatic Adjustment Operation of SCI Bit Rate Table 24.8 System Clock Frequency that Can Automatically Adjust Bit Rate of This LSI Host Bit Rate System Clock Frequency Which Can Automatically Adjust LSI's Bit Rate 9,600 bps 40 to 80 MHz (input frequency of 5 to 10 MHz) 19,200 bps 40 to 80 MHz (input frequency of 5 to 10 MHz) (2) State Transition The overview of the state transition after boot mode is initiated is shown in figure 24.8. For details on boot mode, see section 24.10.1, Serial Communications Interface Specification for Boot Mode. 1. Bit rate adjustment After boot mode is initiated, the bit rate of the SCI interface is adjusted with that of the host. 2. Waiting for inquiry set command For inquiries about the user-MAT size and configuration, MAT start address, and support state, the required information is transmitted to the host. 3. Automatic erasure of all user MAT and user boot MAT After inquiries have finished, all of the user MAT and user boot MAT are automatically erased if a programming/erasing status transition command is sent. 4. Waiting for programming/erasing command * When the program selection command is received, the state for waiting program data is entered. The programming start address and program data must be transmitted following the programming command. When programming is finished, the programming start address must be set to H'FFFFFFFF and transmitted. Then the state for waiting program data is returned to the state of programming/erasing command wait. * When the erasure selection command is received, the state for waiting erase-block data is entered. The eraseblock number must be transmitted following the erasing command. When the erasure is finished, the eraseblock number must be set to H'FF and transmitted. Then the state for waiting erase-block data is returned to the state for waiting programming/erasing command. The erasure must be executed when reset start is not executed and the specified block is programmed after programming is executed in boot mode. When programming can be executed by only one operation, all blocks are erased before the state for waiting programming/erasing/other command is entered. The erasing operation is not required. * There are many commands other than programming/erasing. Examples are checksum, blank check (erasure check), and memory read of the user MAT/user boot MAT and acquisition of current status information. Note that memory read of the user MAT/user boot MAT can only read the program data after all user MAT/user boot MAT has automatically been erased. Rev. 5.00 Feb. 24, 2010 Page 667 of 950 REJ09B0177-0500 24. ROM (SH7058S) (Bit rate adjustment) H'00 to H'00 reception Boot mode initiation (reset by boot mode) Bit rate adjustment H'55 rece Inquiry command reception 2 Wait for inquiry setting command Inquiry command response Processing of inquiry setting command All user MAT and user boot MAT erasure 3 4 1 ption Wait for programming/erasing command Read/check command reception Processing of read/check command Command response Erasure selection command reception Erasure end notice Program end notice Program selection command reception Program data transmission Erase-block specification Wait for erase-block data Wait for program data Figure 24.8 Overview of Boot Mode State Transition Rev. 5.00 Feb. 24, 2010 Page 668 of 950 REJ09B0177-0500 24. ROM (SH7058S) 24.5.2 User Program Mode The user MAT can be programmed/erased in user program mode. (The user boot MAT cannot be programmed/erased.) Programming/erasing is executed by downloading the program in the microcomputer. The overview flow is shown in figure 24.9. High voltage is applied to internal flash memory during the programming/erasing processing. Therefore, transition to reset or hardware standby mode must not be executed. Doing so may cause damage or destroy flash memory. If reset is executed accidentally, the reset signal must be released after the reset input period, which is longer than the normal 100 s. For details on the programming procedure, see the description in 24.5.2 (2) Programming Procedure in User Program Mode. For details on the erasing procedure, see the description in 24.5.2 (3) Erasing Procedure in User Program Mode. For the overview of a processing that repeats erasing and programming by downloading the programming program and the erasing program in separate on-chip ROM areas using FTDAR, see the description in 24.5.2 (4) Erasing and Programming Procedure in User Program Mode. Programming/erasing start 1. RAM emulation mode must be canceled in advance. Download cannot be executed in emulation mode. When programming, program data is prepared FWE=1 ? Yes Programming/erasing procedure program is transferred to the on-chip RAM and executed Programming/erasing end No 2. When the program data is made by means of emulation, the download destination must be changed by FTDAR. With the initial setting of FTDAR (H'00), the download area is overlapped with the emulation area. 3. Inputting high level to the FWE pin sets the FWE bit to 1. 4. Programming/erasing is executed only in the on-chip RAM. However, if the program data is in a consecutive area and can be accessed by the MOV.B instruction of the CPU like SRAM/ROM, the program data can be in an external space. 5. After programming/erasing is finished, low level must be input to the FWE pin for protection. Figure 24.9 Programming/Erasing Overview Flow (1) On-Chip RAM Address Map when Programming/Erasing is Executed Parts of the procedure program that are made by the user, like download request, programming/erasing procedure, and judgement of the result, must be executed in the on-chip RAM. All of the on-chip program that is to be downloaded is in on-chip RAM. Note that on-chip RAM must be controlled so that these parts do not overlap. Figure 24.10 shows the program area to be downloaded. Rev. 5.00 Feb. 24, 2010 Page 669 of 950 REJ09B0177-0500 24. ROM (SH7058S) Area to be downloaded (Size: 3 Kbytes) Unusable area in programming/erasing processing period <On-chip RAM> RAM emulation area or area that can be used by user DPFR (Return value: 1 byte) System use area (15 bytes) Programming/ erasing entry Address RAMTOP (H'FFFF0000) FTDAR setting FTDAR setting+16 FTDAR setting+32 Initialization process entry Initialization + programming program or Initialization + erasing program Area that can be used by user FTDAR setting+3072 RAMEND (H'FFFFBFFF) Figure 24.10 RAM Map after Download (2) Programming Procedure in User Program Mode The procedures for download, initialization, and programming are shown in figure 24.11. Start programming procedure program 1 Download Set FKEY to H'A5 (2.2) Set parameter to R4 and R5 (FMPAR and FMPDR) (2.10) Programming JSR FTDAR setting+16 (2.11) (2.3) Clear FKEY to 0 (2.4) Yes FPFR=0? Yes (2.5) No No Download error processing Set the FPEFEQ and FUBRA parameters Initialization Set FKEY to H'5A After clearing VBR, set SCO to 1 and execute download DPFR=0? Required data programming is completed? Clear FKEY to 0 FPFR=0? Yes (2.7) (2.8) End programming procedure program No Initialization error processing 1 Figure 24.11 Programming Procedure Rev. 5.00 Feb. 24, 2010 Page 670 of 950 REJ09B0177-0500 (2.12) No Clear FKEY and programming error processing (2.13) Yes (2.6) Initialization JSR FTDAR setting+32 (2.9) (2.1) Programming Select on-chip program to be downloaded and set download destination by FTDAR (2.14) 24. ROM (SH7058S) The details of the programming procedure are described below. The procedure program must be executed in an area other than the flash memory to be programmed. Especially the part where the SCO bit in FCCS is set to 1 for downloading must be executed in the on-chip RAM. The area that can be executed in the steps of the user procedure program (on-chip RAM, user MAT, and external space) is shown in section 24.10.3, Storable Area for Procedure Program and Programming Data. The following description assumes the area to be programmed on the user MAT is erased and program data is prepared in the consecutive area. When erasing has not been executed, carry out erasing before writing. 128-byte programming is performed in one program processing. When more than 128-byte programming is performed, programming destination address/program data parameter is updated in 128-byte units and programming is repeated. When less than 128-byte programming is performed, data must total 128 bytes by adding the invalid data. If the invalid data to be added is H'FF, the program processing period can be shortened. (2.1) Select the on-chip program to be downloaded When the PPVS bit of FPCS is set to 1, the programming program is selected. Several programming/erasing programs cannot be selected at one time. If several programs are set, download is not performed and a download error is returned to the source select error detect (SS) bit in the DPFR parameter. Specify the start address of the download destination by FTDAR. (2.2) Write H'A5 in FKEY If H'A5 is not written to FKEY for protection, 1 cannot be written to the SCO bit for a download request. (2.3) VBR is cleared to 0 and 1 is written to the SCO bit of FCCS, and then download is executed. VBR must always be cleared to H'00000000 before setting the SCO bit to 1. To write 1 to the SCO bit, the following conditions must be satisfied. * RAM emulation mode is canceled. * H'A5 is written to FKEY. * The SCO bit writing is executed in the on-chip RAM. When the SCO bit is set to 1, download is started automatically. When execution returns to the user procedure program, the SCO bit is cleared to 0. Therefore, the SCO bit cannot be confirmed to be 1 in the user procedure program. The download result can be confirmed only by the return value of the DPFR parameter. Before the SCO bit is set to 1, incorrect judgement must be prevented by setting the DPFR parameter, that is one byte of the start address of the onchip RAM area specified by FTDAR, to a value other than the return value (H'FF). When download is executed, particular interrupt processing, which is accompanied by the bank switch as described below, is performed as an internal microcomputer processing, so VBR need to be cleared to 0. Eight NOP instructions are executed immediately after the instructions that set the SCO bit to 1. * The user MAT space is switched to the on-chip program storage area. * After the selection condition of the download program and the address set in FTDAR are checked, the transfer processing is executed starting from the on-chip RAM address specified by FTDAR. * The SCO bits in FPCS, FECS, and FCCS are cleared to 0. * The return value is set to the DPFR parameter. * After the on-chip program storage area is returned to the user MAT space, execution returns to the user procedure program. After download is completed and the user procedure program is running, the VBR setting can be changed. The notes on download are as follows. In the download processing, the values of the general registers of the CPU are retained. During the download processing, the interrupt processing cannot be executed. However, the NMI, UBC, and H-UDI interrupt requests are retained, so that on returning to the user procedure program, the interrupt processing starts. For details on the relationship between download and interrupts, see section 24.8.2, Interrupts during Programming/Erasing. Rev. 5.00 Feb. 24, 2010 Page 671 of 950 REJ09B0177-0500 24. ROM (SH7058S) Since a stack area of maximum 128 bytes is used, an area of at least 128 bytes must be saved before setting the SCO bit to 1. If an access by the DMAC or AUD occurs during download, operation cannot be guaranteed. Therefore, access by the DMAC or AUD must not be executed. (2.4) FKEY is cleared to H'00 for protection. (2.5) The value of the DPFR parameter must be checked to confirm the download result. A recommended procedure for confirming the download result is shown below. * Check the value of the DPFR parameter (one byte of start address of the download destination specified by FTDAR). If the value is H'00, download has been performed normally. If the value is not H'00, the source that caused download to fail can be investigated by the description below. * If the value of the DPFR parameter is the same as before downloading (e.g. H'FF), the address setting of the download destination in FTDAR may be abnormal. In this case, confirm the setting of the TDER bit (bit 7) in FTDAR. * If the value of the DPFR parameter is different from before downloading, check the SS bit (bit 2) and the FK bit (bit 1) in the DPFR parameter to ensure that the download program selection and FKEY register setting were normal, respectively. (2.6) The operating frequency is set to the FPEFEQ parameter and the user branch destination is set to the FUBRA parameter for initialization. * The current frequency of the CPU clock is set to the FPEFEQ parameter (general register R4). For the settable range of the FPEFEQ parameter, see section 29.3.2, Clock Timing. For the settable range of the FPEFEQ parameter, see section 29.3.2, Clock Timing. When the frequency is set out of this range, an error is returned to the FPFR parameter of the initialization program and initialization is not performed. For details on the frequency setting, see the description in 24.4.3 (2.1) Flash programming/erasing frequency parameter (FPEFEQ). * The start address in the user branch destination is set to the FUBRA parameter (general register R5). When the user branch processing is not required, 0 must be set to FUBRA. When the user branch is executed, the branch destination is executed in flash memory other than the one that is to be programmed. The area of the on-chip program that is downloaded cannot be set. The program processing must be returned from the user branch processing by the RTS instruction. See the description in 24.4.3 (2.2) Flash user branch address setting parameter (FUBRA). (2.7) Initialization When a programming program is downloaded, the initialization program is also downloaded to on-chip RAM. There is an entry point of the initialization program in the area from (download start address set by FTDAR) + 32 bytes. The subroutine is called and initialization is executed by using the following steps. MOV.L #DLTOP+32,R1 ; Set entry address to R1 JSR @R1 ; Call initialization routine NOP * The general registers other than R0 are saved in the initialization program. * R0 is a return value of the FPFR parameter. * Since the stack area is used in the initialization program, a stack area of maximum 128 bytes must be reserved in RAM. * Interrupts can be accepted during the execution of the initialization program. However, the program storage area and stack area in on-chip RAM and register values must not be destroyed. (2.8) The return value of the initialization program, FPFR (general register R0) is judged. (2.9) FKEY must be set to H'5A and the user MAT must be prepared for programming. (2.10) The parameter which is required for programming is set. Rev. 5.00 Feb. 24, 2010 Page 672 of 950 REJ09B0177-0500 24. ROM (SH7058S) The start address of the programming destination of the user MAT (FMPAR) is set to general register R5. The start address of the program data storage area (FMPDR) is set to general register R4. * FMPAR setting FMPAR specifies the programming destination start address. When an address other than one in the user MAT area is specified, even if the programming program is executed, programming is not executed and an error is returned to the return value parameter FPFR. Since the unit is 128 bytes, the lower eight bits (MOA7 to MOA0) must be in the 128-byte boundary of H'00 or H'80. * FMPDR setting If the storage destination of the program data is flash memory, even when the program execution routine is executed, programming is not executed and an error is returned to the FPFR parameter. In this case, the program data must be transferred to on-chip RAM and then programming must be executed. (2.11) Programming There is an entry point of the programming program in the area from (download start address set by FTDAR) + 16 bytes of on-chip RAM. The subroutine is called and programming is executed by using the following steps. MOV.L #DLTOP+16,R1 ; Set entry address to R1 JSR @R1 ; Call programming routine NOP The general registers other than R0 are saved in the programming program. R0 is a return value of the FPFR parameter. Since the stack area is used in the programming program, a stack area of maximum 128 bytes must be reserved in RAM. (2.12) The return value in the programming program, FPFR (general register R0) is judged. (2.13) Determine whether programming of the necessary data has finished. If more than 128 bytes of data are to be programmed, specify FMPAR and FMPDR in 128-byte units, and repeat steps (2.10) to (2.13). Increment the programming destination address by 128 bytes and update the programming data pointer correctly. If an address which has already been programmed is written to again, not only will a programming error occur, but also flash memory will be damaged. (2.14) After programming finishes, clear FKEY and specify software protection. If this LSI is restarted by a power-on reset immediately after user MAT programming has finished, secure a reset period (period of RES = 0) that is at least as long as the normal 100 s. Rev. 5.00 Feb. 24, 2010 Page 673 of 950 REJ09B0177-0500 24. ROM (SH7058S) (3) Erasing Procedure in User Program Mode The procedures for download, initialization, and erasing are shown in figure 24.12. Start erasing procedure program 1 Set FKEY to H'5A (3.1) Set FKEY to H'A5 Set FEBS parameter (3.2) After clearing VBR, set SCO to 1 and execute download Erasing JSR FTDAR setting+16 (3.3) Erasing Download Select on-chip program to be downloaded and set download destination by FTDAR Clear FKEY to 0 Yes DPFR = 0? Yes No No Download error processing No Clear FKEY and erasing error processing Required block erasing is completed? Set the FPEFEQ and FUBRA parameters Initialization (3.4) FPFR=0 ? (3.5) Yes Clear FKEY to 0 Initialization JSR FTDAR setting+32 (3.6) End erasing procedure program FPFR=0 ? No Yes Initialization error processing 1 Figure 24.12 Erasing Procedure The details of the erasing procedure are described below. The procedure program must be executed in an area other than the user MAT to be erased. Especially the part where the SCO bit in FCCS is set to 1 for downloading must be executed in on-chip RAM. The area that can be executed in the steps of the user procedure program (on-chip RAM, user MAT, and external space) is shown in section 24.10.3, Storable Area for Procedure Program and Programming Data. For the downloaded on-chip program area, see the RAM map for programming/erasing in figure 24.10. A single divided block is erased by one erasing processing. For block divisions, see figure 24.4. To erase two or more blocks, update the erase block number and perform the erasing processing for each block. (3.1) Select the on-chip program to be downloaded Set the EPVB bit in FECS to 1. Several programming/erasing programs cannot be selected at one time. If several programs are set, download is not performed and a download error is returned to the source select error detect (SS) bit in the DPFR parameter. Specify the start address of the download destination by FTDAR. The procedures to be carried out after setting FKEY, e.g. download and initialization, are the same as those in the programming procedure. For details, see the description in 24.5.2 (2) Programming Procedure in User Program Mode. (3.2) Set the FEBS parameter necessary for erasure Set the erase block number of the user MAT in the flash erase block select parameter (FEBS: general register R4). If a value other than an erase block number of the user MAT is set, no block is erased even though the erasing program is executed, and an error is returned to the return value parameter FPFR. Rev. 5.00 Feb. 24, 2010 Page 674 of 950 REJ09B0177-0500 24. ROM (SH7058S) (3.3) Erasure Similar to as in programming, there is an entry point of the erasing program in the area from (download start address set by FTDAR) + 16 bytes of on-chip RAM. The subroutine is called and erasing is executed by using the following steps. MOV.L #DLTOP+16,R1 ; Set entry address to R1 JSR @R1 ; Call erasing routine NOP The general registers other than R0L are saved in the erasing program. R0 is a return value of the FPFR parameter. Since the stack area is used in the erasing program, a stack area of maximum 128 bytes must be reserved in RAM. (3.4) The return value in the erasing program, FPFR (general register R0) is judged. (3.5) Determine whether erasure of the necessary blocks has finished. If more than one block is to be erased, update the FEBS parameter and repeat steps (3.2) to (3.5). Blocks that have already been erased can be erased again. (3.6) After erasure finishes, clear FKEY and specify software protection. If this LSI is restarted by a power-on reset immediately after user MAT programming has finished, secure a reset period (period of RES = 0) that is at least as long as the normal 100 s. (4) Erasing and Programming Procedure in User Program Mode By changing the on-chip RAM address of the download destination in FTDAR, the erasing program and programming program can be downloaded to separate on-chip RAM areas. Figure 24.13 shows an example of repetitively executing RAM emulation, erasing, and programming. 1 Set FTDAR to H'02 (Specify H'FFFF1000 as download destination) Download erasing program Programming program download Initialize erasing program Set FTDAR to H'04 (Specify H'FFFF2000 as download destination) Enter RAM emulation mode and tune data in on-chip RAM Emulation/Erasing/Programming Erasing program download Start procedure program Cancel RAM emulation mode Erase relevant block (execute erasing program) Set FMPDR to H'FFFF0000 to program relevant block (execute programming program) Download programming program Confirm operation Initialize programming program End? No Yes 1 End procedure program Figure 24.13 Sample Procedure of Repeating RAM Emulation, Erasing, and Programming (Overview) Rev. 5.00 Feb. 24, 2010 Page 675 of 950 REJ09B0177-0500 24. ROM (SH7058S) In the above example, the erasing program and programming program are downloaded to areas excluding the 4 Kbytes (H'FFFF0000 to H'FFFF0FFF) from the start of on-chip ROM. Download and initialization are performed only once at the beginning. In this kind of operation, note the following: * Be careful not to damage on-chip RAM with overlapped settings. In addition to the RAM emulation area, erasing program area, and programming program area, areas for the user procedure programs, work area, and stack area are reserved in on-chip RAM. Do not make settings that will overwrite data in these areas. * Be sure to initialize both the erasing program and programming program. Initialization by setting the FPEFEQ and FUBRA parameters must be performed for both the erasing program and the programming program. Initialization must be executed for both entry addresses: (download start address for erasing program) + 32 bytes (H'FFFF1020 in this example) and (download start address for programming program) + 32 bytes (H'FFFF2020 in this example). 24.5.3 User Boot Mode This LSI has user boot mode which is initiated with different mode pin settings than those in user program mode or boot mode. User boot mode is a user-arbitrary boot mode, unlike boot mode that uses the on-chip SCI. Only the user MAT can be programmed/erased in user boot mode. Programming/erasing of the user boot MAT is only enabled in boot mode or programmer mode. (1) User Boot Mode Initiation For the mode pin settings to start up user boot mode, see table 24.1, Relationship between FWE and MD pins and Operating Modes. When the reset start is executed in user boot mode, the check routine for flash-memory related registers runs. The RAM area about 3 Kbytes from H'FFFFB000 and 128 bytes from H'FFFFBF80 to H'FFFFBFFF (a stack area) is used by the routine. While the check routine is running, NMI and all other interrupts cannot be accepted. Neither can the AUD be used in this period. This period is 100 s while operating at an internal frequency of 80 MHz. Next, processing starts from the execution start address of the reset vector in the user boot MAT. At this point, H'AA is set to the flash MAT select register (FMATS) because the execution MAT is the user boot MAT. (2) User MAT Programming in User Boot Mode For programming the user MAT in user boot mode, additional processings made by setting FMATS are required: switching from user-boot-MAT selection state to user-MAT selection state, and switching back to user-boot-MAT selection state after programming completes. Figure 24.14 shows the procedure for programming the user MAT in user boot mode. Rev. 5.00 Feb. 24, 2010 Page 676 of 950 REJ09B0177-0500 24. ROM (SH7058S) Start programming procedure program 1 Select on-chip program to be downloaded and set download destination by FTDAR Set FMATS to value other than H'AA to select user MAT No Download error processing Set the FPEFEQ and FUBRA parameters Initialization JSR FTDAR setting+32 FPFR=0 ? Set parameter to R4 and R5 (FMPAR and FMPDR) Programming JSR FTDAR setting+16 Programming Clear FKEY to 0 Yes MAT switchover Set FKEY to H'A5 User-MAT selection state Download After clearing VBR, set SCO to 1 and execute download DPFR=0 ? Initialization User-boot-MAT selection state Set FKEY to H'A5 FPFR=0 ? No Yes Clear FKEY and programming error processing* No Required data programming is completed? Yes No Clear FKEY to 0 Yes Initialization error processing Set FMATS to H'AA to select user boot MAT 1 User-boot-MAT selection state MAT switchover End programming procedure program Note: * The MAT must be switched by FMATS to perform the programming error processing in the user boot MAT. Figure 24.14 Procedure for Programming User MAT in User Boot Mode The difference between the programming procedures in user program mode and user boot mode is whether the MAT is switched or not as shown in figure 24.14. In user boot mode, the user boot MAT can be seen in the flash memory space with the user MAT hidden in the background. The user MAT and user boot MAT are switched only while the user MAT is being programmed. Because the user boot MAT is hidden while the user MAT is being programmed, the procedure program must be located in an area other than flash memory. After programming finishes, switch the MATs again to return to the first state. MAT switchover is enabled by writing a specific value to FMATS. However note that while the MATs are being switched, the LSI is in an unstable state, e.g. access to a MAT is not allowed until MAT switching is completely finished, and if an interrupt occurs, from which MAT the interrupt vector is read from is undetermined. Perform MAT switching in accordance with the description in section 24.8.1, Switching between User MAT and User Boot MAT. Except for MAT switching, the programming procedure is the same as that in user program mode. The area that can be executed in the steps of the user procedure program (on-chip RAM, user MAT, and external space) is shown in section 24.10.3, Storable Area for Procedure Program and Programming Data. (3) User MAT Erasing in User Boot Mode For erasing the user MAT in user boot mode, additional processings made by setting FMATS are required: switching from user-boot-MAT selection state to user-MAT selection state, and switching back to user-boot-MAT selection state after erasing completes. Figure 24.15 shows the procedure for erasing the user MAT in user boot mode. Rev. 5.00 Feb. 24, 2010 Page 677 of 950 REJ09B0177-0500 24. ROM (SH7058S) Start erasing procedure program 1 Select on-chip program to be downloaded and set download destination by FTDAR Set FMATS to value other than H'AA to select user MAT Set FKEY to H'5A Yes No Download error processing Set the FPEFEQ and FUBRA parameters Initialization JSR FTDAR setting+32 FPFR=0 ? Set FEBS parameter Programming JSR FTDAR setting+16 Erasing Clear FKEY to 0 User-MAT selection state Download After clearing VBR, set SCO to 1 and execute download DPFR=0 ? Initialization User-boot-MAT selection state Set FKEY to H'A5 MAT switchover FPFR=0 ? No No Yes Clear FKEY and erasing error processing* Required block erasing is completed? Yes No Clear FKEY to 0 Yes Initialization error processing 1 Set FMATS to H'AA to select user boot MAT User-boot-MAT selection state MAT switchover End erasing procedure program Note: * The MAT must be switched by FMATS to perform the erasing error processing in the user boot MAT. Figure 24.15 Procedure for Erasing User MAT in User Boot Mode The difference between the erasing procedures in user program mode and user boot mode depends on whether the MAT is switched or not as shown in figure 24.15. MAT switching is enabled by writing a specific value to FMATS. However note that while the MATs are being switched, the LSI is in an unstable state, e.g. access to a MAT is not allowed until MAT switching is completed finished, and if an interrupt occurs, from which MAT the interrupt vector is read from is undetermined. Perform MAT switching in accordance with the description in section 24.8.1, Switching between User MAT and User Boot MAT. Except for MAT switching, the erasing procedure is the same as that in user program mode. The area that can be executed in the steps of the user procedure program (on-chip RAM, user MAT, and external space) is shown in section 24.10.3, Storable Area for Procedure Program and Programming Data. Rev. 5.00 Feb. 24, 2010 Page 678 of 950 REJ09B0177-0500 24. ROM (SH7058S) 24.6 Protection There are three kinds of flash memory program/erase protection: hardware, software, and error protection. 24.6.1 Hardware Protection Programming and erasing of flash memory is forcibly disabled or suspended by hardware protection. In this state by the FWE pin, the downloading of an on-chip program and initialization of the flash memory are possible. However, an activated program for programming or erasure cannot program or erase locations in a user MAT, and the error in programming/erasing is reported in the FPFR parameter. Table 24.9 Hardware Protection Function to be Protected Item Description Download Programming/ Erasure FWE-pin protection The input of a low-level signal on the FWE pin clears the FWE bit of FCCS and the LSI enters a programming/erasing-protected state. -- O Reset/standby protection * A power-on reset (including a power-on reset by the WDT) and entry to standby mode initializes the programming/erasing interface registers and the LSI enters a programming/erasing-protected state. O O * Resetting by means of the RES pin after power is initially supplied will not make the LSI enter the reset state unless the RES pin is held low until oscillation has stabilized. In the case of a reset during operation, hold the RES pin low for the RES pulse width that is specified in the section on AC characteristics. If the LSI is reset during programming or erasure, data in the flash memory is not guaranteed. In this case, execute erasure and then execute programming again. 24.6.2 Software Protection Software protection is set up in any of three ways: by disabling the downloading of on-chip programs for programming and erasing, by means of a key code, and by the RAM emulation register (RAMER). Rev. 5.00 Feb. 24, 2010 Page 679 of 950 REJ09B0177-0500 24. ROM (SH7058S) Table 24.10 Software Protection Function to be Protected Item Description Download Programming/ Erasure Protection by the SCO bit Clearing the SCO bit in FCCS disables downloading of the programming/erasing program, thus making the LSI enter a programming/erasing-protected state. O O Protection by FKEY Downloading and programming/erasing are disabled unless the required key code is written in FKEY. Different key codes are used for downloading and for programming/erasing. O O Emulation protection Setting the RAMS bit in RAMER to 1 makes the LSI enter a programming/erasingprotected state. O O 24.6.3 Error Protection Error protection is a mechanism for aborting programming or erasure when an error occurs, in the form of the microcomputer getting out of control during programming/erasing of the flash memory or operations that are not in accordance with the established procedures for programming/erasing. Aborting programming or erasure in such cases prevents damage to the flash memory due to excessive programming or erasing. If the microcomputer malfunctions during programming/erasing of the flash memory, the FLER bit in FCCS is set to 1 and the LSI enters the error protection state, thus aborting programming or erasure. The FLER bit is set to 1 in the following conditions: * Flash memory is read during programming/erasing (including a vector read or an instruction fetch) * When a SLEEP instruction is executed during programming/erasing Error protection is cancelled (FLER bit is cleared) by a power-on reset, in software standby mode, or in hardware-standby mode. Note that the reset signal should only be released after providing a reset input over a period longer than the normal 100 s. Since high voltages are applied during programming/erasing of the flash memory, some voltage may still remain even after the error protection state has been entered. For this reason, it is necessary to reduce the risk of damage to the flash memory by extending the reset period so that the charge is released. The state-transition diagram in figure 24.16 shows transitions to and from the error protection state. Rev. 5.00 Feb. 24, 2010 Page 680 of 950 REJ09B0177-0500 24. ROM (SH7058S) Program mode Erase mode Read disabled Programming/erasing enabled FLER=0 = 0 or =0 Er Error occurred ror =0 oc (S curr oft e wa d re sta nd Error protection mode Read enabled Programming/erasing disabled FLER=1 or by ) Software standby mode Reset or standby (Hardware protection) Read enabled Programming/erasing disabled FLER=0 =0 Programming/erasing interface register is in its initial state. =0 , =0 or software standby mode cancellation (Software standby) Read disabled Programming/erasing disabled FLER=undefined The power is not supplied in this LSI. Figure 24.16 Transitions to and from Error Protection State Rev. 5.00 Feb. 24, 2010 Page 681 of 950 REJ09B0177-0500 24. ROM (SH7058S) 24.7 Flash Memory Emulation in RAM To provide real-time emulation in RAM of data that is to be written to the flash memory, a part of the RAM can be overlaid on an area of flash memory (user MAT) that has been specified by the RAM emulation register (RAMER). After the RAMER setting is made, the RAM is accessible in both the user MAT area and as the RAM area that has been overlaid on the user MAT area. Such emulation is possible in user mode and user program mode. Figure 24.17 shows an example of the emulation of realtime programming of the user MAT area. Start of emulation program Set RAMER Write the data for tuning to the overlapped RAM area Execute application program No Tuning OK? Yes Cancel RAMER setting Program the emulation block in the user MAT End of emulation program Figure 24.17 Emulation of Flash Memory in RAM Rev. 5.00 Feb. 24, 2010 Page 682 of 950 REJ09B0177-0500 24. ROM (SH7058S) This area is accessible as both a RAM area and as a flash memory area. H'000000 EB0 H'001000 EB1 H'002000 EB2 H'003000 EB3 H'004000 EB4 H'005000 EB5 H'006000 EB6 H'007000 EB7 H'FFFF0000 H'FFFF0FFF H'008000 Flash memory (user MAT) On-chip RAM EB8 to EB15 H'0FFFFF H'FFFFBFFF Figure 24.18 Example of Overlapped RAM Operation Figure 24.18 shows an example of an overlap on block area EB0 of the flash memory. Emulation is possible for a single area selected from among the eight areas, from EB0 to EB7, of the user MAT. The area is selected by the setting of the RAM2 to RAM0 bits in RAMER. (1) To overlap a part of the RAM on area EB0, to allow realtime programming of the data for this area, set the RAMS bit in RAMER to 1, and each of the RAM2 to RAM0 bits to 0. (2) Realtime programming is carried out using the overlaid area of RAM. In programming or erasing the user MAT, it is necessary to run a program that implements a series of procedural steps, including the downloading of an on-chip program. In this process, set the download area with FTDAR so that the overlaid RAM area and the area where the on-chip program is to be downloaded do not overlap. The initial setting (H'00) of FTDAR causes the tuned data area to overlap with the download area. When using the initial setting of FTDAR, the data that is to be programmed must be saved beforehand in an area that is not used by the system. Figure 24.19 shows an example of programming data that has been emulated to the EB0 area in the user MAT. Rev. 5.00 Feb. 24, 2010 Page 683 of 950 REJ09B0177-0500 24. ROM (SH7058S) H'000000 H'001000 H'002000 EB0 EB1 EB2 H'003000 EB3 H'004000 EB4 H'005000 H'006000 H'007000 (1) Cancel the emulation mode. (2) Transfer the user programming/erasing procedure program. (3) Download the on-chip programming/ erasing program to the destination set by FTDAR without overlapping the tuned data area. (4) Execute programming after erasing. EB5 EB6 EB7 H'008000 <On-chip RAM> Tuned data area Flash memory (user MAT) H'FFFF0000 H'FFFF0FFF FTDAR setting Download area EB8 to EB15 Programming/erasing procedure program area H'FFFFBFFF H'0FFFFF Figure 24.19 Programming of Tuned Data 1. After the data to be programmed has fixed values, clear the RAMS bit to 0 to cancel the overlap of RAM. Emulation mode is canceled and emulation protection is also cleared. 2. Transfer the user programming/erasing procedure program to RAM. 3. Run the programming/erasing procedure program in RAM and download the on-chip programming/erasing program. Specify the download start address with FTDAR so that the tuned data area does not overlap with the download area. 4. When the EB0 area of the user MAT has not been erased, erasing must be performed before programming. Set the parameters FMPAR and FMPDR so that the tuned data is designated, and execute programming. Note: Setting the RAMS bit to 1 puts all the blocks in flash memory in the programming/erasing-protected state regardless of the values of the RAM2 to RAM0 bits (emulation protection). Clear the RAMS bit to 0 before actual programming or erasure. Though RAM emulation can also be carried out with the user boot MAT selected, the user boot MAT can be erased or programmed only in boot mode or programmer mode. Rev. 5.00 Feb. 24, 2010 Page 684 of 950 REJ09B0177-0500 24. ROM (SH7058S) 24.8 Usage Notes 24.8.1 Switching between User MAT and User Boot MAT It is possible to switch between the user MAT and user boot MAT. However, the following procedure is required because these MATs are allocated to address 0. (Switching to the user boot MAT disables programming and erasing. Programming of the user boot MAT must take place in boot mode or programmer mode.) (1) MAT switching by FMATS should always be executed from the on-chip RAM. The SH microcomputer prefetches execution instructions. Therefore, a switchover during program execution in the user MAT causes an instruction code in the user MAT to be prefetched or an instruction in the newly selected user boot MAT to be prefetched, thus resulting in unstable operation. (2) To ensure that the MAT that has been switched to is accessible, execute eight NOP instructions in on-chip RAM immediately after writing to FMATS of on-chip RAM (this prevents access to the flash memory during MAT switching). (3) If an interrupt occurs during switching, there is no guarantee of which memory MAT is being accessed. Always mask the maskable interrupts before switching MATs. In addition, configuring the system so that NMI interrupts do not occur during MAT switching is recommended. (4) After the MATs have been switched, take care because the interrupt vector table will also have been switched. If the same interrupt processings are to be executed before and after MAT switching or interrupt requests cannot be disabled, transfer the interrupt processing routine to on-chip RAM, and use the VBR setting to place the interrupt vector table in on chip RAM. In this case, make sure the VBR setting change does not conflict with the interrupt occurrence. (5) Memory sizes of the user MAT and user boot MAT are different. When accessing the user boot MAT, do not access addresses exceeding the 12-Kbyte memory space. If access goes beyond the 12-Kbyte space, the values read are undefined. <User MAT> <On-chip RAM> <User boot MAT> Procedure for switching to the user boot MAT Procedure for switching to the user MAT Procedure for switching to the user boot MAT (1) Mask interrupts. (2) Write H'AA to FMATS. (3) Execute eight NOP instructions before accessing the user boot MAT. Procedure for switching to the user MAT (1) Mask interrupts. (2) Write a value other than H'AA to FMATS. (3) Execute eight NOP instructions before accessing the user MAT. Figure 24.20 Switching between User MAT and User Boot MAT Rev. 5.00 Feb. 24, 2010 Page 685 of 950 REJ09B0177-0500 24. ROM (SH7058S) 24.8.2 Interrupts during Programming/Erasing (1) Download of On-Chip Program (1.1) VBR setting change Before downloading the on-chip program, VBR must be set to H'00000000 (initial value). If VBR is set to a value other than the initial value, the interrupt vector table is placed in the user MAT (FMATS is not H'AA) or the user boot MAT (FMATS is H'AA) on initialization of VBR. When VBR setting change conflicts with interrupt occurrence, whether the vector table before or after VBR is changed is referenced may cause an error. Therefore, for cases where VBR setting change may conflict with interrupt occurrence, prepare a vector table to be referenced when VBR is H'00000000 at the start of the user MAT or user boot MAT. (1.2) SCO download request and interrupt request Download of the on-chip programming/erasing program that is initiated by setting the SCO bit in FCCS to 1 generates a particular interrupt processing accompanied by MAT switchover. Operation when the SCO download request and interrupt request conflicts is described below. 1. Contention between SCO download request and interrupt request Figure 24.21 shows the timing of contention between execution of the instruction that sets the SCO bit in FCCS to 1 and interrupt acceptance. CPU cycle CPU operation for instruction that sets SCO bit to 1 Interrupt acceptance n n+1 n+2 n+3 n+4 Fetch Decoding Execution Execution Execution (a) (b) (c) (a) When the interrupt is accepted at or before the (n + 1) cycle After the interrupt processing completes, the SCO bit is set to 1 and download is executed. (b) When the interrupt is accepted at the (n + 2) cycle The interrupt conflicts with the SCO download request. For details on operation in this case, see 2. Operation when contention occurs. (c) When the interrupt is accepted at or after the (N + 3) cycle The SCO download request occurs prior to the interrupt request, and download is executed. During download, no other interrupt processing can be handled. If an interrupt is still being requested after download completes, the interrupt processing starts. For details on interrupt requests during download, see 3. Interrupt requests generated during download. Figure 24.21 Timing of Contention between SCO Download Request and Interrupt Request 2. Operation when contention occurs Operation differs according to the type of interrupt with which the SCO download request has conflicted. NMI, UBC, and H-UDI interrupt requests Operation for when these interrupts conflict with the SCO download request is described below. Rev. 5.00 Feb. 24, 2010 Page 686 of 950 REJ09B0177-0500 24. ROM (SH7058S) Main processing SCO download processing Contention between SCO and interrupt Interrupt processing, e.g. NMI Figure 24.22 Contention between Interrupts (e.g. NMI) * The NMI, UBC, or H-UDI interrupt processing is started. Processing proceeds up to the point where SR and PC are saved, the vector is fetched, and the start instruction of the interrupt processing routine is fetched. * At this point, the SCO download request with a higher priority occurs. The SCO download processing is started. * After the download processing has ended, the interrupt processing routine (e.g. NMI) that was in the middle of execution resumes from the point of fetching the start instruction of the interrupt processing routine. * The interrupt processing routine is ended, and execution returns to the main processing. IRQ and on-chip peripheral module interrupt requests Operation for when these interrupts conflict with the SCO download request is described below. Main processing SCO download processing Contention between SCO and interrupt Interrupt processing, e.g. IRQ Figure 24.23 Contention between Interrupts (e.g. IRQ) * An IRQ interrupt or interrupt from an on-chip peripheral module is replaced with the SCO download request and download is executed. * If the IRQ or on-chip peripheral module interrupt is still being requested when the download processing has ended, the interrupt processing is executed. If these interrupt requests have been canceled, execution returns to the main processing. * An interrupt request is canceled when the IRQ signal, for which low-level detection is set, has been driven high before download ends. Also refer to the description below (3. Interrupt requests generated during download). 3. Interrupt requests generated during download Rev. 5.00 Feb. 24, 2010 Page 687 of 950 REJ09B0177-0500 24. ROM (SH7058S) Even though an interrupt is requested during SCO download, the interrupt processing is not executed until download ends. Note that interrupt requests are basically retained, so that on completion of download, the interrupt processing starts. When more than one type of interrupts are requested, their priorities are judged by the interrupt controller (INTC), and execution starts from the interrupt processing with higher priority. NMI, UBC, and H-UDI interrupt requests When these interrupt requests occur during SCO download, their interrupt sources are retained. IRQ interrupt request Falling-edge detection or low-level detection can be specified for an IRQ interrupt. * Falling-edge detection is selected: When the falling-edge of IRQ is detected during SCO download, the interrupt source is retained. * Low-level detection is selected: When the low-level of IRQ is detected during SCO download, if the IRQ remains low when download ends, the interrupt processing starts. If the IRQ is high when download ends, the interrupt source will be canceled. On-chip peripheral module interrupt request An interrupt from an on-chip peripheral module is requested by input of the specified level. Since the interrupt signal continues to be output unless the interrupt flag is cleared, the interrupt source is retained. (2) Interrupts during programming/erasing Though an interrupt processing can be executed at realtime during programming/erasing of the downloaded on-chip program, the following limitations and notes are applied. 1. When flash memory is being programmed or erased, both the user MAT and user boot MAT cannot be accessed. Prepare the interrupt vector table and interrupt processing routine in on-chip RAM or external memory. Make sure the flash memory being programmed or erased is not accessed by the interrupt processing routine. If flash memory is read, the read values are not guaranteed. If flash memory that is being programmed or erased is accessed, the error protect state is entered, and programming or erasing is aborted. 2. Do not rewrite the program data specified by the FMPDR parameter. If new program data is to provided by the interrupt processing, temporarily save the new program data in another area. After confirming the completion of programming, save the new program data in the area specified by FMPDR or change the setting in FMPDR to indicated the other area in which the new program data was temporarily saved. 3. Make sure the interrupt processing routine does not rewrite the contents of the flash-memory related registers or data in the downloaded on-chip program area. During the interrupt processing, do not simultaneously perform RAM emulation, download of the on-chip program by an SCO request, or programming/erasing. 4. At the beginning of the interrupt processing routine, save the CPU register contents. Before returning from the interrupt processing, write the saved contents in the CPU registers again. 5. When a transition is made to sleep mode in the interrupt processing routine, the error protection state is entered and programming/erasing is aborted. If a transition is made to the reset state, the reset signal should only be released after providing a reset input over a period longer than the normal 100 s to reduce the damage to flash memory. 24.8.3 Other Notes 1. Download time of on-chip program The programming program that includes the initialization routine and the erasing program that includes the initialization routine are each 3 Kbytes or less. Accordingly, when the CPU clock frequency is 80 MHz, the download for each program takes approximately 305 s at maximum. 2. User branch processing intervals The intervals for executing the user branch processing differs in programming and erasing. The processing phase also differs. Table 24.11 lists the minimum and maximum user branch processing intervals when the CPU clock frequency is 80 MHz. Rev. 5.00 Feb. 24, 2010 Page 688 of 950 REJ09B0177-0500 24. ROM (SH7058S) Table 24.11 User Branch Processing Intervals Processing Name Maximum Interval Minimum Interval Programming Approximately 1 ms Approximately 19 s Erasing Approximately 5 ms Approximately 19 s However, when operation is done with CPU clock of 80 MHz, maximum and minimum values of the time until initial user branch processing are as shown in table 24.12. Table 24.12 Intervals Until Start of User Branch Processing Processing Name Max. Min. Programming Approximately 500 s Approximately 500 s Erasing Approximately 2300 s Approximately 1000 s 3. Write to flash-memory related registers by AUD or DMAC While an instruction in on-chip RAM is being executed, the AUD or DMAC can write to the SCO bit in FCCS that is used for a download request or FMATS that is used for MAT switching. Make sure that these registers are not accidentally written to, otherwise an on-chip program may be downloaded and damage RAM or a MAT switchover may occur and the CPU get out of control. 4. State in which AUD operation is disabled and interrupts are ignored In the following modes or period, the AUD is in module standby mode and cannot operate. The NMI or maskable interrupt requests are ignored; they are not executed and the interrupt sources are not retained. Boot mode Programmer mode Checking the flash-memory related registers immediately after user boot mode is initiated (Approximately 100 s if operation is done at an internal frequency of 80 MHz after the reset signal is released) 5. Compatibility with programming/erasing program of conventional F-ZTAT SH microcomputer A programming/erasing program for flash memory used in the conventional F-ZTAT SH microcomputer which does not support download of the on-chip program by a SCO transfer request cannot run in this LSI. Be sure to download the on-chip program to execute programming/erasing of flash memory in this LSI. 6. Monitoring runaway by WDT Unlike the conventional F-ZTAT SH microcomputer, no countermeasures are available for a runaway by WDT during programming/erasing by the downloaded on-chip program. Prepare countermeasures (e.g. use of the user branch routine and periodic timer interrupts) for WDT while taking the programming/erasing time into consideration as required. 7. FWE pin state Make sure not to change the state of the FWE pin during the flash memory reprogramming. Make sure not to drive the FWE pin low instantaneously even if the noise occurs. Programming/erasing results are not guaranteed if the FWE state is changed during the flash memory reprogramming. Rev. 5.00 Feb. 24, 2010 Page 689 of 950 REJ09B0177-0500 24. ROM (SH7058S) 24.9 Programmer Mode Along with its on-board programming mode, this LSI also has programmer mode as another mode for writing and erasing of programs and data. Programmer mode supports memory-read mode, auto-program mode, auto-erase mode, and statusread mode. Programming/erasing is possible on the user MAT and user boot MAT. A status-polling system is adopted for operation in auto-program mode, auto-erase mode, and status-read mode. In statusread mode, details of the system's internal state are output after execution of automatic programming or automatic erasure. In programmer mode, set the mode pins as shown in table 24.13, and provide a 6-MHz input-clock signal. This enables this LSI to operate at 48 MHz. Table 24.13 Programmer Mode Pin Settings Pin Name Settings Mode pins: MD2, MD1, and MD0 0, 1, 1 FWE High-level input (automatic programming and automatic erasure) RES Power-on reset circuit EXTAL, XTAL, PLLVCC, PLLVSS, PLLCAP Oscillation circuit and PLL circuit VCL Internal stepdown stabilization capacitor 24.9.1 Pin Arrangement of Socket Adapter Attach the socket adapter to the LSI in the way shown in figure 24.25. This allows conversion to 40 pins. Figure 24.24 shows the memory mapping of on-chip ROM, and figure 24.25 shows the arrangement of the socket adapter's pins. Address in MCU mode H'0000,0000 Address in PROM mode Address in MCU mode H'00,0000 H'0000,0000 Address in PROM mode H'0,0000 On-chip ROM space (user boot MAT) 12 Kbytes H'0000,2FFF H'0,2FFF On-chip ROM space (user MAT) 1 Mbyte H'0F,FFFF H'000F,FFFF Figure 24.24 Mapping of On-Chip Flash Memory Rev. 5.00 Feb. 24, 2010 Page 690 of 950 REJ09B0177-0500 24. ROM (SH7058S) SH7058SF Pin No. Pin Name Socket Adapter (40-Pin Conversion) HN27C4096HG (40 pins) BP-272 FP-256H Pin No. Pin Name B3 7 A0 21 A0 D4 8 A1 22 A1 C4 9 A2 23 A2 A3 10 A3 24 A3 B4 12 A4 25 A4 A4 14 A5 26 A5 C5 15 A6 27 A6 B5 16 A7 28 A7 A5 17 A8 29 A8 D6 18 A9 31 A9 B6 19 A10 32 A10 A6 21 A11 33 A11 C7 23 A12 34 A12 B7 24 A13 35 A13 A7 25 A14 36 A14 D8 26 A15 37 A15 C8 27 A16 38 A16 B8 28 A17 39 A17 A8 29 A18 10 A18*1 D9 31 A19 9 A19*1 C9 33 A20 8 A20*1 D15 63 D0 19 I/00 B18 64 D1 18 I/01 A19 65 D2 17 I/02 C18 66 D3 16 I/03 B19 67 D4 15 I/04 B20 68 D5 14 I/05 C17 69 D6 13 I/06 C19 71 D7 12 I/07 P1 218 CE 2 CE K2 230 OE 20 OE L3 226 WE 3 WE D14 56 FWE 4 FWE 1,40 Vcc Vcc 11,30 Vss 5,6,7 NC D5,C6,A10,C11,A12,C12,C13, D13,B14,C15,A16,C16,D16,F17, F18,K19,K20,T20,T19,U19,U16, V15,V9,U6,V5,U4,P3,J3,H4 A9,B13,B15,D7,B12,D11,C14,F19, G3,G17,E20,J4,J20,U20,J9 to 12, K9 to 12,L9 to 12,M1,M9 to 12,P4, T18,U5,U9,V6,V16,W11 C10 11,20,37,39,42,43,46,49,52,55, 57,59,70,75,83,100,101,119, 120,128,139,148,172,187,194, 203,212,237,247 13,22,32,41,44,47,50,54,72,77, 84,85,99,121,126,141,150,163, 174,185,196,205,214,227,239, 249 34 Vss A21 B16 58 A15 53 RES XTAL A14 51 EXTAL A17 60 PLLVcc B17 61 PLLCAP A18 62 PLLVss B9,Y11,M2 30,161,225 VCL Other Other NC (OPEN) Power-on reset circuit Oscillator circuit PLL circuit Capacitor Legend: : Flash-write enable FWE I/07 to 0 : Data I/O A21 to 0 : Address input : Chip enable CE : Output enable OE : Write enable WE Note: *With using the HN27C4096HG as the base, unused I/O pins are adopted to make up for the shortage of address pins. Figure 24.25 Pin Arrangement of Socket Adapter Rev. 5.00 Feb. 24, 2010 Page 691 of 950 REJ09B0177-0500 24. ROM (SH7058S) 24.9.2 Programmer Mode Operation Table 24.14 shows the settings for the operating modes of programmer mode, and table 24.15 lists the commands used in programmer mode. The following sections provide detailed information on each mode. * Memory-read mode Supports reading from the user MAT or user boot MAT in bytes. * Auto-program mode Supports the simultaneous programming of the user MAT and user boot MAT in 128-byte units. Status polling is used to confirm the end of automatic programming. * Auto-erase mode Supports only automatic erasure of the entire user MAT or user boot MAT. Status polling is used to confirm the end of automatic erasure. * Status-read mode Status polling is used with automatic programming and automatic erasure. Normal completion can be detected by reading the signal on the I/O6 pin. In status-read mode, error information is output when an error has occurred. Table 24.14 Settings for Each Operating Mode of Programmer Mode Pin Name Mode FWE CE OE WE I/O7 to I/O0 A20 to A0 Read H or L L L H Data output Ain Output disable H or L L H H Hi-Z X Command write H or L L H L Data input Ain* Chip disable H or L H X X Hi-Z X Notes: 1. The chip-disable mode is not a standby state; internally, it is an operational state. 2. To write commands when making a transition to auto-program or auto-erase mode, input a high-level signal on the FWE pin. * Ain indicates that there is also an address input in auto-program mode. Rev. 5.00 Feb. 24, 2010 Page 692 of 950 REJ09B0177-0500 24. ROM (SH7058S) Table 24.15 Commands in Programmer Mode 1st Cycle Numberof Cycles Memory MAT to be Accessed Mode Memory-read mode 1+n User MAT Write User boot MAT Auto-program mode 129 Auto-erase mode 2 Command Status-read mode 2 Address 2nd Cycle Data Mode Address Data X H'00 Read RA Dout Write X H'05 User MAT Write X H'40 Write WA Din User boot MAT Write X H'45 User MAT Write X H'20 Write X H'20 User boot MAT Write X H'25 Common to both MATs Write X H'71 H'25 Write X H'71 Notes 1. In auto-program mode, 129 cycles are required in command writing because of the simultaneous 128-byte write. 2. In memory read mode, the number of cycles varies with the number of address writing cycles (n). 3. In an automatic erasure command, input the same command code for the 1st and 2nd cycles (for erasing of the user boot MAT, input H'25 for the 1st and 2nd cycles). 24.9.3 Memory-Read Mode (1) On completion of automatic programming, automatic erasure, or status read, the LSI enters a command input wait state. So, to read the contents of memory after these operations, issue the command to transit to memory-read mode before reading from the memory. (2) In memory-read mode, the writing of commands is possible in the same way as in command input wait state. (3) After entering memory-read mode, continuous reading is possible. (4) After power has first been supplied, the LSI enters memory-read mode. For the AC characteristics in memory read mode, see section 24.10.2, AC Characteristics and Timing in Programmer Mode. Rev. 5.00 Feb. 24, 2010 Page 693 of 950 REJ09B0177-0500 24. ROM (SH7058S) 24.9.4 Auto-Program Mode (1) In auto-program mode, programming is in 128-byte units. That is, 128 bytes of data are transferred in succession. (2) Even in the programming of less than 128 bytes, 128 bytes of data must be transferred. H'FF should be written to those addresses that are unnecessarily written to. (3) Set the lower seven bits of the address to be transferred to low level. Inputting an invalid address will result in a programming error, although processing will proceed to the memory-programming operation. (4) The memory address is transferred in the 2nd cycle. Do not transfer addresses in the 3rd or later cycles. (5) Do not issue commands while programming is in progress. (6) When programming, execute automatic programming once for each 128-byte block of addresses. Programming the block at an address where programming has already been performed is not possible. (7) To confirm the end of automatic programming, check the signal on the I/O6 pin. Confirmation in status-read mode is also possible (status polling of the I/O7 pin is used to check the end status of automatic programming). (8) Status-polling information on the I/O6 and I/O7 pins is retained until the next command is written. As long as no command is written, the information is made readable by enabling CE and OE. For the AC characteristics in auto-program mode, see section 24.10.2, AC Characteristics and Timing in Programmer Mode. 24.9.5 Auto-Erase Mode (1) Auto-erase mode only supports erasing of the entire memory. (2) Do not perform command writing while auto erasing is in progress. (3) To confirm the end of automatic erasure, check the signal on the I/O6 pin. Confirmation in the status-read mode is also possible (status polling of the I/O7 pin is used to check the end status of automatic erasure). (4) Status polling information on the I/O6 and I/O7 pins is retained until the next command writing. As long as no command is written, the information is made readable by enabling CE and OE. For the AC characteristics in auto-erase mode, see section 24.10.2, AC Characteristics and Timing in Programmer Mode. Rev. 5.00 Feb. 24, 2010 Page 694 of 950 REJ09B0177-0500 24. ROM (SH7058S) 24.9.6 Status-Read Mode (1) Status-read mode is used to determine the type of an abnormal termination. Use this mode when automatic programming or automatic erasure ends abnormally. (2) The return code is retained until writing of a command that selects a mode other than status-read mode. Table 24.16 lists the return codes of status-read mode. For the AC characteristics in status-read mode, see section 24.10.2, AC Characteristics and Timing in Programmer Mode. Table 24.16 Return Codes of Status-Read Mode Pin Name I/O7 Attribute I/O6 Normal end Command indicator error Initial value 0 Indication 0 I/O5 I/O4 Programming error 0 Normal end: Command Programming 0 error: 1 error: 1 Abnormal Otherwise: 0 Otherwise: 0 end: 1 I/O3 I/O2 I/O1 I/O0 Erasure error -- -- Programming or erase count exceeded Invalid address error 0 0 0 0 -- Count exceeded: 1 Otherwise: 0 Invalid address error: 1 Otherwise: 0 0 Erasure -- error:1 Otherwise: 0 Note: I/O2 and I/O3 are undefined pins. 24.9.7 Status Polling (1) The I/O7 status-polling output is a flag that indicates the operating status in auto-program or auto-erase mode. (2) The I/O6 status-polling output is a flag that indicates normal/abnormal end of auto-program or auto-erase mode. Table 24.17 Truth Table of Status-Polling Output Pin Name In Progress Abnormal End -- Normal End I/O7 0 1 0 1 I/O6 0 0 1 1 I/O0 to I/O5 0 0 0 0 24.9.8 Time Taken in Transition to Programmer Mode Until oscillation has stabilized and while programmer mode is being set up, the LSI is unable to accept commands. After the programmer-mode setup time has elapsed, the LSI enters memory-read mode. For details, see section 24.10.2, AC Characteristics and Timing in Programmer Mode. 24.9.9 Notes on Programming in Programmer Mode (1) When programming addresses which have previously been programmed, apply auto-erasing before auto-programming. (2) When using programmer mode to program a chip that has been programmed/erased in an on-board programming mode, auto-erasing before auto-programming is recommended. (3) Do not take the chip out of the PROM programmer or reset the chip during programming or erasure. Flash memory is susceptible to permanent damage since a high voltage is being applied during the programming/erasing. When the reset signal is accidentally input to the chip, the period in the reset state until the reset signal is released should be longer than the normal 100 s. Rev. 5.00 Feb. 24, 2010 Page 695 of 950 REJ09B0177-0500 24. ROM (SH7058S) Notes: 1. The flash memory is initially in the erased state when the device is shipped by Renesas Technology. For other chips for which the history of erasure is unknown, auto-erasing as a check and supplement for the initialization (erase) level is recommended. 2. Automatic programming to a single address block can only be performed once. Additional programming to an address block that has already been programmed is not allowed. 24.10 Further Information 24.10.1 Serial Communication Interface Specification for Boot Mode Initiating boot mode enables the boot program to communicate with the host by using the on-chip SCI. The serial communication interface specifications are shown below. * Status The boot program has three states. (1) Bit-rate-adjustment state In this state, the boot program adjusts the bit rate to communicate with the host. Initiating boot mode enables starting of the boot program and entry to the bit-rate-adjustment state. The program receives the command from the host to adjust the bit rate. After adjusting the bit rate, the program enters the inquiry/selection state. (2) Inquiry/Selection state In this state, the boot program responds to inquiry commands from the host. The device name, clock mode, and bit rate are selected. After selection of these settings, the program is made to enter the programming/erasing state by the command for a transition to the programming/erasing state. The boot program transfers the erasure program to RAM and erases the user MATs and user boot MATs before the transition. (3) Programming/erasing state Programming and erasure by the boot program take place in this state. The boot program is made to transfer the programming/erasing program to RAM by commands from the host. Checksums and blank checks are executed by sending these commands from the host. These boot program states are shown in figure 24.26. Rev. 5.00 Feb. 24, 2010 Page 696 of 950 REJ09B0177-0500 24. ROM (SH7058S) Reset Bit-rate-adjustment state Bit rate adjustment Inquiry/Selection state Inquiry/Selection wait Selection Inquiry Selection processing Inquiry processing Transition to programming/ erasing state Programming/Erasing state User MAT/User boot MAT erasing processing Programming/Erasing selection wait Programming Programming processing Erasing Erasing processing Check Check processing Figure 24.26 Boot Program Processing Flow * Bit-rate-adjustment state The bit rate is calculated by measuring the period of transfer of a low-level byte (H'00) from the host. The bit rate can be changed by the command for a new bit rate selection. After the bit rate has been adjusted, the boot program enters the inquiry/selection state. The bit-rate-adjustment sequence is shown in figure 24.27. Rev. 5.00 Feb. 24, 2010 Page 697 of 950 REJ09B0177-0500 24. ROM (SH7058S) Host Boot Program H'00 (30 times maximum) Measuring the 1-bit length H'00 (Completion of adjustment) H'55 H'E6 (Response to boot) H'FF (Error) Figure 24.27 Bit-Rate-Adjustment Sequence * Communications protocol After adjustment of the bit rate, the protocol for serial communications between the host and the boot program is as shown below. (1) One-byte commands and one-byte responses These commands and responses are comprised of a single byte. These consists of the inquiries and ACK for successful completion. (2) n-byte commands or n-byte responses These commands and responses are comprised of n bytes of data. These are selections and responses to inquiries. The amount of programming data is not included under this heading because it is determined in another command. (3) Error response The error response is a response to inquiries. It consists of an error response and an error code and which take up two bytes. (4) Programming of 128 bytes The size is not specified in commands. The data size is indicated in response to the programming unit inquiry. (5) Memory read response This response consists of four bytes of data. Rev. 5.00 Feb. 24, 2010 Page 698 of 950 REJ09B0177-0500 24. ROM (SH7058S) 1-byte command or 1-byte response n-byte command or n-byte response Command or response Data Data size Checksum Command or response Error response Error code Error response 128-byte programming Address Data (n bytes) Checksum Command Memory read response Data size Data Response Checksum Figure 24.28 Communications Protocol Format Command (one byte): Commands including inquiries, selection, programming, erasing, and checking Response (one byte): Response to an inquiry Size (one or two bytes): The amount of data for transmission excluding the command, amount of data, and checksum Data (n bytes): Detailed data of a command or response Checksum (one byte): The checksum is calculated so that the total of all values from the command byte to the SUM byte becomes H'00. Error Response (one byte): Error response to a command Error Code (one byte): Type of the error Address (four bytes): Address for programming Data (n bytes): Data to be programmed. n is indicated in the response to the programming unit inquiry. Data Size (four bytes): Four-byte response to a memory read * Inquiry/Selection State The boot program returns information from the flash memory in response to the host's inquiry commands and sets the device code, clock mode, and bit rate in response to the host's selection command. Table 24.18 lists the inquiry and selection commands. Rev. 5.00 Feb. 24, 2010 Page 699 of 950 REJ09B0177-0500 24. ROM (SH7058S) Table 24.18 Inquiry and Selection Commands Command Command Name Description H'20 Supported Device Inquiry Inquiry regarding device codes and product names of F-ZTAT H'10 Device Selection Selection of device code H'21 Clock Mode Inquiry Inquiry regarding numbers of clock modes and values of each mode H'11 Clock Mode Selection Indication of the selected clock mode H'22 Multiplication Ratio Inquiry Inquiry regarding the number of clock types, the number of multiplication/division ratios, and the multiplication/division ratios H'23 Operating Clock Frequency Inquiry Inquiry regarding the maximum and minimum values of the main clock and peripheral clocks H'24 User Boot MAT Information Inquiry Inquiry regarding the number of user boot MATs and the start and last addresses of each MAT H'25 User MAT Information Inquiry Inquiry regarding the a number of user MATs and the start and last addresses of each MAT H'26 Block for Erasing Information Inquiry Inquiry regarding the number of blocks and the start and last addresses of each block H'27 Programming Unit Inquiry Inquiry regarding the unit of programming data H'3F New Bit Rate Selection Selection of new bit rate H'40 Transition to Programming/Erasing State Erasing of user MAT and user boot MAT, and entry to programming/erasing state H'4F Boot Program Status Inquiry Inquiry into the operation status of the boot program The selection commands, which are device selection (H'10), clock mode selection (H'11), and new bit rate selection (H'3F), should be sent from the host in this order. These commands are certainly required. When two or more selection commands are sent at once, the last command will be valid. All of these commands, except for the boot program status inquiry command (H'4F), will be valid until the boot program receives the programming/erasing transition (H'40). The host can choose the needed commands out of the commands and inquiries listed above. The boot program status inquiry command (H'4F) is valid after the boot program has received the programming/erasing transition command (H'40). (1) Supported device inquiry The boot program will return the device codes of supported devices in response to the supported device inquiry. Command H'20 Command: H'20 (one byte): Inquiry regarding supported devices Response H'30 Size Number of devices Number of characters Device code Product name ... SUM Response: H'30 (one byte): Response to the supported device inquiry Size (one byte): Number of bytes to be transmitted, excluding the command, amount of data, and checksum, that is, the amount of data consists of the product names, the number of devices, characters, and device codes Number of devices (one byte): Number of device types supported by the boot program Number of characters (one byte): Number of characters in the device code and boot program's name Rev. 5.00 Feb. 24, 2010 Page 700 of 950 REJ09B0177-0500 24. ROM (SH7058S) Device code (four bytes): Supporting product (ASCII code) Product name (n bytes): Type name of the boot program (ASCII code) SUM (one byte): Checksum The checksum is calculated so that the total number of all values from the command byte to the SUM byte becomes H'00. (2) Device Selection The boot program will set the supported device to the specified device code. The program will return the selected device code in response to the inquiry after this setting has been made. Command H'10 Size Device code SUM Command: H'10 (one byte): Device selection Size (one byte): Number of characters in the device code (fixed at 2) Device code (four bytes): Device code returned in response to the supported device inquiry (ASCII code) SUM (one byte): Checksum Response H'06 Response: H'06, (one byte): Response to the device selection command ACK will be returned when the device code matches. Error response H'90 ERROR Error response: H'90 (one byte): Error response to the device selection command ERROR: (one byte): Error code H'11: Checksum error H'21: Device code mismatch error (3) Clock Mode Inquiry The boot program will return the supported clock modes in response to the clock mode inquiry. Command H'21 Command: H'21 (one byte): Inquiry regarding clock mode Response H'31 Size Number of modes Mode SUM Response: H'31 (one byte): Response to the clock-mode inquiry Size (one byte): Amount of data that represents the number of modes and modes Number of modes (one byte): Number of supported clock modes H'00 indicates no clock mode or the device allows the clock mode to be read. Mode (one byte): Supported clock modes (i.e. H'01 means clock mode 1.) SUM (one byte): Checksum (4) Clock Mode Selection The boot program will set the specified clock mode. The program will return the selected clock-mode information after this setting has been made. The clock-mode selection command should be sent after the device selection command. Command H'11 Size Mode SUM Command: H'11 (one byte): Selection of clock mode Size (one byte): Number of characters that represents the mode (fixed at 1) Mode (one byte): Clock mode returned in reply to the supported clock mode inquiry. SUM (one byte): Checksum Response H'06 Response: H'06 (one byte): Response to the clock-mode selection command ACK will be returned when the clock mode matches. Rev. 5.00 Feb. 24, 2010 Page 701 of 950 REJ09B0177-0500 24. ROM (SH7058S) Error response H'91 ERROR Error response: H'91 (one byte): Error response to the clock-mode selection command ERROR (one byte): Error code H'11: Checksum error H'22: Clock mode mismatch error (5) Multiplication Ratio Inquiry The boot program will return the supported multiplication/division ratios. Command H'22 Command: H'22 (one byte): Inquiry regarding multiplication ratio Response H'32 Size Number of clock types Number of multiplication ratios Multiplication ratio ... ... SUM Response: H'32 (one byte): Response to the multiplication ratio inquiry Size (one byte): Amount of data that represents the number of clock types, the number of multiplication ratios, and the multiplication ratios Number of clock types (one byte): Number of supported multiplied clock types (e.g. when there are two multiplied clock types, which are the main operating frequency and the peripheral module operating frequency, the number of types will be H'02) Number of multiplication ratios (one byte): Number of multiplication ratios for each operating frequency (e.g. the number of multiplication ratios to which the main operating frequency can be set and the peripheral module operating frequency can be set) Multiplication ratio (one byte) Multiplication ratio : Value of the multiplication ratio (e.g. when the clock-frequency multiplier is four, the value of multiplication ratio will be H'04) Division ratio: Value of the division ratio, inverted to be a negative number (e.g. when the clock is divided by two, the value of division ratio will be H'FE. H'FE = -2) The number of multiplication ratios returned is the same as the number of multiplication ratios and as many groups of data are returned as there are types. SUM (one byte): Checksum (6) Operating Clock Frequency Inquiry The boot program will return the number of operating clock frequencies, and the maximum and minimum values. Command H'23 Command: H'23, (one byte): Inquiry regarding operating clock frequencies Response H'33 Size Minimum value of operating clock frequency Number of operating clock frequencies Maximum value of operating clock frequency ... SUM Response: H'33 (one byte): Response to operating clock frequency inquiry Size (one byte): Number of bytes that represents the number of types, minimum values, and maximum values of operating clock frequencies. Number of types (one byte): Number of supported operating clock frequency types (e.g. when there are two operating clock frequency types, which are the main and peripheral clocks, the number of types will be H'02) Rev. 5.00 Feb. 24, 2010 Page 702 of 950 REJ09B0177-0500 24. ROM (SH7058S) Minimum value of operating clock frequency (two bytes): Minimum value for each multiplied or divided clock frequency. The minimum and maximum values represent the values in MHz, valid to the hundredths place of MHz, and multiplied by 100. (e.g. when the value is 20.00 MHz, it will be multiplied by 100 to be 2000 which is H'07D0) Maximum value of operating clock frequency (two bytes): Maximum value for each multiplied or divided clock frequency. There are as many pairs of minimum and maximum values as there are operating clock frequencies. SUM (one byte): Checksum (7) User Boot MAT Information Inquiry The boot program will return the number of user boot MATs and their addresses. Command H'24 Command: H'24 (one byte): Inquiry regarding user boot MAT information Response H'34 Size Number of areas Start address of area Last address of area ... SUM Response: H'34 (one byte): Response to user boot MAT information inquiry Size (one byte): Amount of data that represents the number of areas, the start address of each area, and the last address of each area Number of areas (one byte): Number of non-consecutive user boot MAT areas When user boot MAT areas are consecutive, the number of areas returned is H'01. Start address of area (four bytes): Start address of the area Last address of area (four bytes): Last address of the area There are as many groups of data representing the start and last addresses as there are areas. SUM (one byte): Checksum (8) User MAT Information Inquiry The boot program will return the number of user MATs and their addresses. Command H'25 Command: H'25 (one byte): Inquiry regarding user MAT information Response H'35 Size Number of areas Start address of area Last address of area ... SUM Response: H'35 (one byte): Response to the user MAT information inquiry Size (one byte): Amount of data that represents the number of areas, the start address of each area, and the last address of each area Number of areas (one byte): Number of non-consecutive user MAT areas When user MAT areas are consecutive, the number of areas returned is H'01. Start address of area (four bytes): Start address of the area -- Last address of area (four bytes): Last address of the area There are as many groups of data representing the start and last addresses as there are areas. -- SUM (one byte): Checksum (9) Erased Block Information Inquiry The boot program will return the number of erased blocks and their addresses. Command H'26 Command: H'26 (one byte): Inquiry regarding erased block information Rev. 5.00 Feb. 24, 2010 Page 703 of 950 REJ09B0177-0500 24. ROM (SH7058S) Response H'36 Size Number of blocks Start address of block Last address of block ... SUM Response: H'36 (one byte): Response to the number of erased blocks and addresses Size (two bytes): Amount of data that represents the number of blocks, the start address of each block, and the last address of each block Number of blocks (one byte): Number of erased blocks in flash memory Start address of block (four bytes): Start address of the block Last address of block (four bytes): Last address of the block There are as many groups of data representing the start and last addresses as there are blocks. SUM: Checksum (10) Programming Unit Inquiry The boot program will return the programming unit used to program data. Command H'27 Command: H'27 (one byte): Inquiry regarding programming unit Response H'37 Size Programming unit SUM Response: H'37 (one byte): Response to programming unit inquiry Size (one byte): Number of characters that indicate the programming unit (fixed at 2) Programming unit (two bytes): Unit for programming This is the unit for reception of program data. SUM (one byte): Checksum (11) Inquiry of Two-MAT Simultaneous Programming For an inquiry of two-MAT simultaneous programming, the boot program returns the response whether two-MAT simultaneous programming is possible or not, and the start address. Command H'28 Command: H'28 (one byte): Inquiry of two-MAT simultaneous programming Response H'38 Size Programming method First MAT start address Second MAT start address SUM Response: H'38 (one byte): Response to the inquiry of two-MAT simultaneous programming Size (one byte): Total amount of programming method and MAT start address 5 bytes when programming to one MAT, 9 bytes when programming to two MATs simultaneously Programming method (one byte): H'01 = One-MAT programming H'02 = Two-MAT simultaneous programming First MAT start address (four bytes): First MAT start address Second side MAT start address four bytes): Second MAT start address Data on second MAT start address is available only when two-MAT simultaneous programming is possible. SUM (one byte): Checksum (12) New Bit Rate Selection The boot program will set a new bit rate and return the new bit rate. This selection should be sent after sending the clock-mode selection command. Rev. 5.00 Feb. 24, 2010 Page 704 of 950 REJ09B0177-0500 24. ROM (SH7058S) Command H'3F Size Bit rate Number of multiplication ratios Multiplication ratio 1 Multiplication ratio 2 Input frequency SUM Command: H'3F (one byte): Selection of new bit rate Size (one byte): Amount of data that represents the bit rate, input frequency, number of multiplication ratios, and multiplication ratios Bit rate (two bytes): New bit rate One hundredth of the value (e.g. when the value is 19200 bps, the bit rate is 192, which is H'00C0) Input frequency (two bytes): Frequency of the clock input to the boot program This value is valid to the hundredths place and represents the value in MHz multiplied by 100. (e.g. when the value is 28.88 MHz, it will be multiplied by 100 to be 2888 which is H'0B48. Number of multiplication ratios (one byte): Number of multiplication ratios to which the device can be set. Multiplication ratio 1 (one byte): Value of the multiplication or division ratio for the main operating frequency Multiplication ratio: Value of the multiplication ratio (e.g. when the clock frequency is multiplied by four, the multiplication ratio will be H'04.) Division ratio: Value of the division ratio, inverted to be a negative number (e.g. when the clock is divided by two, the value of division ratio will be H'FE. H'FE = -2) Multiplication ratio 2 (one byte): Value of the multiplication or division ratio for the peripheral operating frequency Multiplication ratio: Value of the multiplication ratio (e.g. when the clock frequency is multiplied by four, the multiplication ratio will be H'04.) Division ratio: Value of the division ratio, inverted to be a negative number (e.g. when the clock is divided by two, the value of division ratio will be H'FE. H'FE = -2) SUM (one byte): Checksum Response H'06 Response: H'06 (one byte): Response to selection of a new bit rate When it is possible to set the bit rate, the response will be ACK. Error response H'BF ERROR Error response: H'BF (one byte): Error response to selection of new bit rate ERROR: (one byte): Error code H'11: Checksum error H'24: Bit-rate selection error This bit rate is not available. H'25: Input frequency error This input frequency is not within the range set by the minimum and maximum values. H'26: Multiplication ratio error This ratio does not match an available ratio. H'27: Operating frequency error This operating frequency is not within the range set by the minimum and maximum values. The methods for checking of received data are listed below. * Input frequency The received value of the input frequency is checked to ensure that it is within the range of minimum to maximum frequencies which matches the clock modes of the specified device. When the value is out of this range, an input frequency error is generated. * Multiplication ratio The received value of the multiplication ratio or division ratio is checked to ensure that it matches the clock modes of the specified device. When the value is out of this range, a multiplication error is generated. Rev. 5.00 Feb. 24, 2010 Page 705 of 950 REJ09B0177-0500 24. ROM (SH7058S) * Operating frequency error The operating frequency is calculated from the received value of the input frequency and the multiplication or division ratio. The input frequency is input to the LSI and the LSI is actually operated at the operating frequency. The expression is given below. Operating frequency = Input frequency*Multiplication ratio, or Operating frequency = Input frequency/Division ratio The calculated operating frequency should be checked to ensure that it is within the range of minimum to maximum frequencies which are available with the clock modes of the specified device. When it is out of this range, an operating frequency error is generated. * Bit rate From peripheral operating clock () and bit rate (B), the clock select (CKS) value (n) in the serial mode register (SMR) and the bit rate register (BRR) value (N) are obtained. The error between n and N that is calculated by the method below is checked to ensure that it is less than 4%. When it is 4% or more, a bit-rate selection error is generated. Error (%) = {[ x 106 ] -1} x 100 (N+1) x B x 64 x 2(2n-1) When the new bit rate is selectable, the new bit rate will be set in the register after sending ACK in response. The host will send ACK with the new bit rate for confirmation and the boot program will response with that rate. Confirmation H'06 Confirmation: H'06 (one byte): Confirmation of a new bit rate Response H'06 Response: H'06 (one byte): Response to confirmation of a new bit rate The sequence of new bit-rate selection is shown in figure 24.29. Boot program Host Setting a new bit rate Waiting for one-bit period at the specified bit rate H'06 (ACK) Setting a new bit rate Setting a new bit rate H'06 (ACK) with the new bit rate H'06 (ACK) with the new bit rate Figure 24.29 New Bit-Rate Selection Sequence Transition to Programming/Erasing State: To enter the programming/erasing state, the boot program will transfer the erasing program, and erase the user MATs and user boot MATs in that order. On completion of this erasure, ACK will be returned and a transition is made to the programming/erasing state. The host should select the device code, clock mode, and new bit rate with device selection, clock-mode selection, and new bit-rate selection commands, and then send the command for the transition to programming/erasing state. This procedure should be carried out before transferring the programming selection command or program data. Command H'40 Command: H'40 (one byte): Transition to programming/erasing state Rev. 5.00 Feb. 24, 2010 Page 706 of 950 REJ09B0177-0500 24. ROM (SH7058S) Response H'06 Response: H'06 (one byte): Response to transition to programming/erasing state The boot program will send ACK when the user MATs and user boot MATs have been erased by the transferred erasing program. Error response H'C0 H'51 Error response: H'C0 (one byte): Error response to transition to programming/erasing state Error code: H'51 (one byte): Erasing error An error occurred and erasure was not completed. Command Error: A command error will occur when a command is undefined, the order of commands is incorrect, or a command is unacceptable. Issuing a clock-mode selection command before a device selection or issuing an inquiry command after the command for transition to the programming/erasing state, are examples. Error response H'80 H'xx Error response: H'80 (one byte): Command error Command: H'xx (one byte): Received command Command Order: The order for commands in the inquiry selection state is shown below. (1) A supported device inquiry (H'20) should be made to inquire about the supported devices. (2) The device should be selected from among those described by the returned information and set with a device selection (H'10) command. (3) A clock-mode inquiry (H'21) should be made to inquire about the supported clock modes. (4) The clock mode should be selected from among those described by the returned information and set with a clock-mode selection (H'11) command. (5) After selection of the device and clock mode, inquiries for other required information should be made, such as the multiplication ratio inquiry (H'22) or operating frequency inquiry (H'23). (6) A new bit rate should be selected with the new bit-rate selection (H'3F) command, according to the returned information on multiplication ratios and operating frequencies. (7) After selection of the device and clock mode, the information of the user boot MAT and user MAT should be made to inquire about the user boot MAT information inquiry (H'24), user MAT information inquiry (H'25), erased block information inquiry (H'26), programming unit inquiry (H'27), and two-MAT simultaneous programming information inquiry (H'28). (8) After making inquiries and selecting a new bit rate, issue the command for transition to the programming/erasing state (H'40). The boot program will then enter the programming/erasing state. Programming/Erasing State: In the programming/erasing state, a programming selection command makes the boot program select the programming method, a 128-byte programming command makes it program the memory with data, and an erasing selection command and block erasing command make it erase the block. Table 24.19 lists the programming/erasing commands. Rev. 5.00 Feb. 24, 2010 Page 707 of 950 REJ09B0177-0500 24. ROM (SH7058S) Table 24.19 Programming/Erasing Commands Command Command Name Description H'42 User boot MAT programming selection Transfers the user boot MAT programming program H'43 User MAT programming selection Transfers the user MAT programming program H'50 128-byte programming Programs 128 bytes of data H'48 Erasing selection Transfers the erasing program H'58 Block erasing Erases a block of data H'52 Memory read Reads the contents of memory H'4A User boot MAT checksum Checks the checksum of the user boot MAT H'4B User MAT checksum Checks the checksum of the user MAT H'4C User boot MAT blank check Checks whether the contents of the user boot MAT are blank H'4D User MAT blank check Checks whether the contents of the user MAT are blank H'4F Boot program status inquiry Inquires into the boot program's state Programming: Programming is executed by a programming selection command and a 128-byte programming command. First, the host should send the programming selection command and select the programming method and programming MATs. There are three programming selection commands used according to the area and method for programming. (1) User boot MAT programming selection (2) User MAT programming selection After issuing the programming selection command, the host should send the 128-byte programming command. The 128byte programming command that follows the selection command represents the data programmed according to the method specified by the selection command. When more than 128-byte data is programmed, 128-byte commands should repeatedly be executed. Sending a 128-byte programming command with H'FFFFFFFF as the address will stop the programming. On completion of programming, the boot program will wait for selection of programming or erasing. To continue programming with another method or of another MAT, the procedure must be repeated from the programming selection command. The programming selection command and sequence for the 128-byte programming commands are shown in figure 24.30. Rev. 5.00 Feb. 24, 2010 Page 708 of 950 REJ09B0177-0500 24. ROM (SH7058S) Host Boot program Programming selection (H'42, H'43) Transfer of the programming program ACK 128-byte programming (address, data) Repeat Programming ACK 128-byte programming (H'FFFFFFFF) ACK Figure 24.30 Programming Sequence (1) User boot MAT programming selection The boot program will transfer a programming program. The data is programmed to the user boot MATs by the transferred programming program. Command H'42 Command: H'42 (one byte): User boot MAT programming selection Response H'06 Response: H'06 (one byte): Response to user boot MAT programming selection When the programming program has been transferred, the boot program will return ACK. Error response H'C2 ERROR Error response: H'C2 (one byte): Error response to user boot MAT programming selection -- ERROR: (one byte): Error code H'54: Selection processing error (transfer error occurs and processing is not completed) (2) User MAT programming selection The boot program will transfer a programming program. The data is programmed to the user MATs by the transferred programming program. Command H'43 Command: H'43 (one byte): User MAT programming selection Response H'06 Response: H'06 (one byte): Response to user MAT programming selection When the programming program has been transferred, the boot program will return ACK. Error response H'C3 ERROR Error response: H'C3 (one byte): Error response to user MAT programming selection ERROR: (one byte): Error code H'54: Selection processing error (transfer error occurs and processing is not completed) (3) 128-byte programming The boot program will use the programming program transferred by the programming selection command for programming the user boot MATs or user MATs. When two-user-MAT simultaneous programming command is selected, programming will start after the boot program has received data for both MATs. Rev. 5.00 Feb. 24, 2010 Page 709 of 950 REJ09B0177-0500 24. ROM (SH7058S) Command H'50 Programming address Data ... ... SUM Command: H'50 (one byte): 128-byte programming Programming address (four bytes): Start address for programming Multiple of the size specified in response to the programming unit inquiry; a 128-byte boundary (e.g. H'00, H'01, H'00, H'00: H'01000000) Data (n bytes): Data to be programmed The size is specified in response to the programming unit inquiry. SUM (one byte): Checksum Response H'06 Response: H'06 (one byte): Response to 128-byte programming On completion of programming, the boot program will return ACK. In two-MAT programming, when all data for the first MAT has been received, the boot program will return ACK. Error response H'D0 ERROR Error response: H'D0 (one byte): Error response to 128-byte programming ERROR: (one byte): Error code H'11: Checksum error H'2A: Address error (address is not within the specified range) H'53: Programming error (a programming error has occurred and programming cannot be continued) The specified address should match the unit for programming of data. For example, when the programming is in 128-byte units, the lower byte of the address should be H'00 or H'80. When there are less than 128 bytes of data to be programmed, the host should fill the rest with H'FF. In two-user-MAT simultaneous programming, the host should alternately send the data for each MAT address. Sending the 128-byte programming command with the address of H'FFFFFFFF will stop the programming operation. The boot program will interpret this as the end of programming and wait for selection of programming or erasing. When the most recently received data has not been programmed in two-user-MAT simultaneous programming, the most recent data is programmed before programming is stopped. Command H'50 Programming address SUM Command: H'50 (one byte): 128-byte programming Programming address (four bytes): End code is H'FF, H'FF, H'FF, H'FF. SUM (one byte): Checksum Error response H'D0 ERROR Error response: H'D0 (one byte): Error response to 128-byte programming ERROR: (one byte): Error code H'11: Checksum error H'53: Programming error An error has occurred in programming, and programming cannot be continued (in two-user-MAT simultaneous programming, when programming to the last MAT has not been completed.) Erasure: Erasure is performed with the erasing selection and block erasing command. First, erasure is selected by the erasing selection command and the boot program then erases the block specified by the block erasing command. The command should be repeatedly executed if two or more blocks are to be erased. Sending a Rev. 5.00 Feb. 24, 2010 Page 710 of 950 REJ09B0177-0500 24. ROM (SH7058S) block erasing command from the host with the block number H'FF will stop erasure. On completion of erasing, the boot program will wait for selection of programming or erasing. The erasing selection command and sequence for erasing data are shown in figure 24.31. Host Boot program Preparation for erasure (H'48) Transfer of erasure program ACK Erasure (Erased block number) Repeat Erasure ACK Erasure (H'FF) ACK Figure 24.31 Erasing Sequence (1) Erasing selection The boot program will transfer the erasing program. User MAT data is erased by the transferred erasing program. Command H'48 Command: H'48 (one byte): Erasing selection Response H'06 Response: H'06 (one byte): Response to erasing selection After the erasing program has been transferred, the boot program will return ACK. Error response H'C8 ERROR Error response: H'C8 (one byte): Error response to erasing selection ERROR: (one byte): Error code H'54: Selection processing error (transfer error occurs and processing is not completed) (2) Block erasing The boot program will erase the contents of the specified block. Command H'58 Size Block number SUM Command: H'58 (one byte): Erasing Size (one byte): Number of characters that represents the erasure block number (fixed at 1) Block number (one byte): Number of the block whose data is to be erased SUM (one byte): Checksum Response H'06 Response: H'06 (one byte): Response to erasing After erasure has been completed, the boot program will return ACK. Rev. 5.00 Feb. 24, 2010 Page 711 of 950 REJ09B0177-0500 24. ROM (SH7058S) Error response H'D8 ERROR Error response: H'D8 (one byte): Error response to erasing H'11: Checksum error H'29: Block number error Block number is incorrect. H'51: Erasure error An error has occurred during erasure. On receiving block number H'FF, the boot program will stop erasure and wait for a selection command. Command H'58 Size Block number SUM Command: H'58 (one byte): Erasure Size (one byte): Number of characters that represents the block number (fixed at 1) Block number (one byte): H'FF (stop code for erasure) SUM (one byte): Checksum Response H'06 Response: H'06 (one byte): Response to end of erasure (ACK) When erasure is to be performed again after the block number H'FF has been sent, the procedure should be executed from the erasure selection command. Rev. 5.00 Feb. 24, 2010 Page 712 of 950 REJ09B0177-0500 24. ROM (SH7058S) Memory Read: The boot program will return the data in the specified address. Command H'52 Size Area Read start address Read size SUM Command: H'52 (one byte): Memory read Size (one byte): Amount of data that represents the area, read address, and read size (fixed at 9) Area (one byte) H'11: User boot MAT H'01: User MAT An address error occurs when the area setting is incorrect. Read start address (four bytes): Start address to be read from Read size (four bytes): Size of data to be read SUM (one byte): Checksum Response H'52 Read size Data ... SUM Response: H'52 (one byte): Response to memory read Read size (four bytes): Size of data to be read Data (n bytes): Data for the read size from the read address SUM (one byte): Checksum Error response H'D2 ERROR Error response: H'D2 (one byte): Error response to memory read ERROR: (one byte): Error code H'11: Checksum error H'2A: Address error The read address is not in the MAT. H'2B: Size error The read size exceeds the MAT. Or, the read end address calculated from the read start address and read size is out of the MAT range, or the read size is 0. User Boot MAT Checksum: The boot program will add the amount of data in user boot MATs and return the result. The user boot MAT checksum value is calculated as a 16-Kbyte area. The checksum value is the sum of 12 Kbytes of user boot MAT data and 4 Kbytes of H'FF data. Command H'4A Command: H'4A (one byte): Checksum of user boot MATs Response H'5A Size MAT checksum SUM Response: H'5A (one byte): Response to checksum of user boot MATs Size (one byte): Number of characters in checksum data (fixed at 4) MAT checksum (4 bytes): The user boot MAT checksum value calculated by adding byte units, with a further 4 Kbytes of H'FF data added SUM (one byte): Checksum (for transmit data) Rev. 5.00 Feb. 24, 2010 Page 713 of 950 REJ09B0177-0500 24. ROM (SH7058S) User MAT Checksum: The boot program will add the amount of data in user MATs and return the result. Command H'4B Command: H'4B (one byte): Checksum of user MATs Response H'5B Size MAT checksum SUM Response: H'5B (one byte): Response to checksum of user MATs Size (one byte): Number of characters in checksum data (fixed at 4) MAT checksum (four bytes): Checksum of user MATs The total amount of data is obtained in byte units. SUM (one byte): Checksum (for transmit data) User Boot MAT Blank Check: The boot program will check whether or not all user boot MATs are blank and return the result. Command H'4C Command: H'4C (one byte): Blank check of user boot MATs Response H'06 Response: H'06 (one byte): Response to blank check of user boot MATs If all user boot MATs are blank (H'FF), the boot program will return ACK. Error response H'CC H'52 Error response: H'CC (one byte): Error response to blank check of user boot MATs Error code: H'52 (one byte): Erasure has not been completed User MAT Blank Check: The boot program will check whether or not all user MATs are blank and return the result. Command H'4D Command: H'4D (one byte): Blank check of user MATs Response H'06 Response: H'06 (one byte): Response to blank check of user MATs If all user MATs are blank (H'FF), the boot program will return ACK. Error response H'CD H'52 Error response: H'CD (one byte): Error response to blank check of user MATs Error code: H'52 (one byte): Erasure has not been completed. Boot Program Status Inquiry: The boot program will return indications of its present state and error condition. This inquiry can be made in the inquiry/selection state or the programming/erasing state. Command H'4F Command: H'4F (one byte): Inquiry regarding boot program status Response H'5F Size STATUS ERROR SUM Response: H'5F (one byte): Response to inquiry regarding boot program status Size (one byte): Number of characters in data (fixed at 2) STATUS (one byte): Standard boot program status For details, see table 24.20. ERROR (one byte): Error state ERROR = 0 indicates normal operation. ERROR = 1 indicates error has occurred For details, see table 24.21. SUM (one byte): Checksum Rev. 5.00 Feb. 24, 2010 Page 714 of 950 REJ09B0177-0500 24. ROM (SH7058S) Table 24.20 Status Code Code Description H'01 Device Selection Wait H'02 Clock Mode Selection Wait H'03 Bit Rate Selection Wait H'0F Programming/Erasing State Transition Wait (bit rate selection is completed) H'31 Programming State for Erasing User MAT and User Boot MAT H'3F Programming/Erasing Selection Wait (Erasure is completed) H'4F Programming Data Receive Wait H'5F Erasure Block Specification Wait (erasure is completed) Table 24.21 Error Code Code Description H'00 No Error H'11 Checksum Error H'21 Device Code Mismatch Error H'22 Clock Mode Mismatch Error H'24 Bit Rate Selection Error H'25 Input Frequency Error H'26 Multiplication Ratio Error H'27 Operating Frequency Error H'29 Block Number Error H'2A Address Error H'2B Data Length Error H'51 Erasure Error H'52 Erasure Incompletion Error H'53 Programming Error H'54 Selection Error H'80 Command Error H'FF Bit-Rate-Adjustment Confirmation Error Rev. 5.00 Feb. 24, 2010 Page 715 of 950 REJ09B0177-0500 24. ROM (SH7058S) 24.10.2 AC Characteristics and Timing in Programmer Mode Table 24.22 AC Characteristics in Memory Read Mode Condition: VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C Code Symbol Min Max Unit Command write cycle tnxtc 20 s CE hold time tceh 0 ns CE setup time tces 0 ns Data hold time tdh 50 ns Data setup time tds 50 ns Programming pulse width twep 70 ns WE rise time tr 30 ns WE fall time tf 30 ns Command write Note Memory read mode Address stable A21-A0 tces tceh tnxtc CE OE twep tf tr WE tds tdh I/O7-I/O0 Note : Data is latched at the rising edge of WE. Figure 24.32 Memory Read Timing after Command Write Table 24.23 AC Characteristics in Transition from Memory Read Mode to Others Condition: VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C Code Symbol Min Command write cycle tnxtc 20 s CE hold time tceh 0 ns CE setup time tces 0 ns Data hold time tdh 50 ns Data setup time tds 50 ns Programming pulse width twep 70 WE rise time tr 30 ns WE fall time tf 30 ns Rev. 5.00 Feb. 24, 2010 Page 716 of 950 REJ09B0177-0500 Max Unit ns Note 24. ROM (SH7058S) Command write in another mode Memory read mode A21-A0 Address stable tnxtc tces tceh CE OE twep tf tr WE tds tdh I/O7-I/O0 Note : WE and OE should not be enabled simultaneously. Figure 24.33 Timing at Transition from Memory Read Mode to Other Modes Table 24.24 AC Characteristics in Memory Read Mode Condition: VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C Code Symbol Access time Max Unit tacc 20 s CE output delay time tce 150 ns OE output delay time toe 150 ns Output disable delay time tdf 100 ns Data output hold time toh 5 CE VIL OE VIL VIH Note ns Address stable A21-A0 WE Min Address stable tacc tacc toh toh I/O7-I/O0 Figure 24.34 CE/OE Enable State Read Rev. 5.00 Feb. 24, 2010 Page 717 of 950 REJ09B0177-0500 24. ROM (SH7058S) Address stable A21-A0 Address stable tce tce CE WE toe toe OE tacc tacc VIH toh toh tdf tdf I/O7-I/O0 Figure 24.35 CE/OE Clock Read Table 24.25 AC Characteristics in Auto-Program Mode Condition: VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C Code Symbol Min Command write cycle tnxtc 20 s CE hold time tceh 0 ns CE setup time tces 0 ns Data hold time tdh 50 ns Data setup time tds 50 ns Programming pulse width twep 70 ns Status polling start time twsts 1 Status polling access time tspa Address setup time tas 0 ns Address hold time tah 60 ns Memory programming time twrite -- Programming setup time tpns 100 Programming end setup time tpnh 100 WE rise time tr 30 ns WE fall time tf 30 ns Rev. 5.00 Feb. 24, 2010 Page 718 of 950 REJ09B0177-0500 Max Unit Note ms 150 tP ns ms ns ns tP: Refer to section 29.5, Flash Memory Characteristics 24. ROM (SH7058S) tpnh FWE Address stable A21-A0 tpns tces tnxtc tceh tnxtc CE OE tf twep tas tr WE tds tdh tah twsts Data transfer 1 byte to 128 bytes tspa twrite I/O7 Programming end identification signal I/O6 Programming normal end confirmation signal I/O5-I/O0 H'00 H'40 or H'45 1st-byte Din 128th-byte Din Figure 24.36 Timing in Auto-Program Mode Rev. 5.00 Feb. 24, 2010 Page 719 of 950 REJ09B0177-0500 24. ROM (SH7058S) Table 24.26 AC Characteristics in Auto-Erase Mode Condition: VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C Code Symbol Min Max Unit Command write cycle tnxtc 20 s CE hold time tceh 0 ns CE setup time tces 0 ns Data hold time tdh 50 ns Data setup time tds 50 ns Programming pulse width twep 70 ns Status polling start time tests 1 ms Status polling access time tspa Memory erase time terase -- Erase setup time tens 100 ns Erase end setup time tenh 100 ns WE rise time tr 30 ns WE fall time tf 30 ns 150 ns 8 x tE s tE: Refer to section 29.5, Flash Memory Characteristics tenh FWE A21-A0 tens tces tnxtc tceh tnxtc CE OE tf twep tests tr tspa WE tds terase tdh I/O7 Erase end identification signal I/O6 Erase normal end confirmation signal I/O5-I/O0 H'00 H'20 or H'25 H'20 or H'25 Figure 24.37 Timing in Auto-Erase Mode Rev. 5.00 Feb. 24, 2010 Page 720 of 950 REJ09B0177-0500 Note 24. ROM (SH7058S) Table 24.27 AC Characteristics Status Read Mode Condition: VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C Code Symbol Min Max Unit Command write cycle tnxtc 20 s CE hold time tceh 0 ns CE setup time tces 0 ns Data hold time tdh 50 ns Data setup time tds 50 ns Programming pulse width twep 70 ns OE output delay time toe 150 ns Disable delay time tdf 100 ns CE output delay time tce 150 ns WE rise time tr 30 ns WE fall time tf 30 ns Note A21-A0 tces tnxtc tceh tces tnxtc tceh tnxtc CE tce OE tf twep tr tf twep toe tr WE tds tdh tds H'71 I/O7-I/O0 tdf tdh H'71 Note: I/O3 and I/O2 are undefined. Figure 24.38 Timing in Status Read Mode Table 24.28 Stipulated Transition Times to Command Wait State Condition: VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C Code Symbol Min Max Unit Standby release (oscillation stabilization time) tosc1 30 ms Programmer mode setup time tbmv 10 ms VCC hold time tdwn 0 ms Note Rev. 5.00 Feb. 24, 2010 Page 721 of 950 REJ09B0177-0500 24. ROM (SH7058S) tosc1 tbmv Memory read mode Command wait state Auto-program mode Auto-erase mode Command wait state Normal/abnormal end identification tdwn VCC FWE Note: Set the FWE input pin to low level, except in the auto-program and auto-erase modes. Figure 24.39 Oscillation Stabilization Time, Programmer Mode Setup Time, and Power-Down Sequence 24.10.3 Storable Area for Procedure Program and Programming Data In the descriptions in the previous section, storable areas for the programming/erasing procedure programs and program data are assumed to be in on-chip RAM. However, the procedure programs and data can be stored in and executed from other areas (e.g. external address space) as long as the following conditions are satisfied. (1) The on-chip programming/erasing program is downloaded from the address set by FTDAR in on-chip RAM, therefore, this area is not available for use. (2) The on-chip programming/erasing program will use 128 bytes or more as a stack. Make sure this area is reserved. (3) Since download by setting the SCO bit to 1 will cause the MATs to be switched, it should be executed in on-chip RAM. (4) The flash memory is accessible until the start of programming or erasing, that is, until the result of downloading has been judged. When in a mode in which the external address space is not accessible, such as single-chip mode, the required procedure programs, interrupt vector table, interrupt processing routine, and user branch program should be transferred to on-chip RAM before programming/erasing of the flash memory starts. (5) The flash memory is not accessible during programming/erasing operations. Therefore, the programming/erasing program must be downloaded to on-chip RAM in advance. Areas for executing each procedure program for initiating programming/erasing, the user program at the user branch destination for programming/erasing, the interrupt vector table, and the interrupt processing routine must be located in on-chip memory other than flash memory or the external address space. (6) After programming/erasing, access to flash memory is inhibited until FKEY is cleared. A reset state (RES = 0) for more than at least 100 s must be taken when the LSI mode is changed to reset on completion of a programming/erasing operation. Transitions to the reset state or hardware standby mode during programming/erasing are inhibited. When the reset signal is accidentally input to the LSI, a longer period in the reset state than usual (100 s) is needed before the reset signal is released. (7) Switching of the MATs by FMATS is needed for programming/erasing of the user MAT in user boot mode. The program which switches the MATs should be executed from the on-chip RAM. For details, see section 24.8.1, Switching between User MAT and User Boot MAT. Please make sure you know which MAT is selected when switching the MATs. (8) When the program data storage area indicated by the FMPDR parameter in the programming processing is within the flash memory area, an error will occur. Therefore, temporarily transfer the program data to on-chip RAM to change the address set in FMPDR to an address other than flash memory. Based on these conditions, tables 24.29 and 24.30 show the areas in which the program data can be stored and executed according to the operation type and mode. Rev. 5.00 Feb. 24, 2010 Page 722 of 950 REJ09B0177-0500 24. ROM (SH7058S) Table 24.29 Executable MAT Initiated Mode Operation User Program Mode User Boot Mode* Programming Table 24.30 (1) Table 24.30 (3) Erasing Table 24.30 (2) Table 24.30 (4) Note: * Programming/Erasing is possible to user MATs. Table 24.30 (1) Usable Area for Programming in User Program Mode Storable /Executable Area Programming procedure Note: * Selected MAT Item On-Chip RAM User MAT External Space (Expanded Mode with MD0 = 0) Program data storage area O X* O -- Selecting on-chip program to be downloaded O O O O Writing H'A5 to key register O O O O Writing 1 to SCO in FCCS (download) O X X Key register clearing O O O O Judging download result O O O O Download error processing O O O O Setting initialization parameters O O O O Initialization O X X O Judging initialization result O O O O User MAT Embedded Program Storage MAT -- O Initialization error processing O O O O Interrupt processing routine O X O O Writing H'5A to key register O O O O Setting programming parameters O X O O Programming O X X O Judging programming result O X O O Programming error processing O X O O Key register clearing O X O O If the data has been transferred to on-chip RAM in advance, this area can be used. Rev. 5.00 Feb. 24, 2010 Page 723 of 950 REJ09B0177-0500 24. ROM (SH7058S) Table 24.30 (2) Usable Area for Erasure in User Program Mode Storable /Executable Area On-Chip RAM User MAT External Space (Expanded Mode with MD0 = 0) Selecting on-chip program to be downloaded O O O O Writing H'A5 to key register O O O O Writing 1 to SCO in FCCS (download) O X X Item Erasing procedure Selected MAT User MAT O Key register clearing O O O O Judging download result O O O O Download error processing O O O O Setting initialization parameters O O O O Initialization O X X O Judging initialization result O O O O Initialization error processing O O O O Interrupt processing routine O X O O Writing H'5A to key register O O O O Setting erasure parameters O X O O Erasure O X X O Judging erasure result O X O O Erasing error processing O X O O Key register clearing O X O O Rev. 5.00 Feb. 24, 2010 Page 724 of 950 REJ09B0177-0500 Embedded Program Storage MAT 24. ROM (SH7058S) Table 24.30 (3) Usable Area for Programming in User Boot Mode Storable/Executable Area On-Chip RAM User Boot MAT External Space (Expanded Mode with MD0 = 0) Program data storage area O X*1 O Selecting on-chip program to be downloaded O O O O Writing H'A5 to key register O O O O Writing 1 to SCO in FCCS (download) O X X Key register clearing O O O O Judging download result O O O O Download error processing O O O O Setting initialization parameters O O O O Initialization O X X O Judging initialization result O O O O Initialization error processing O O O O Interrupt processing routine O X O O Switching MATs by FMATS O X X O Writing H'5A to Key Register O X O O Setting programming parameters O X O O Programming O X X O Judging programming result O X O O Programming error processing O X*2 O O Key register clearing O X O O Switching MATs by FMATS O X X Item Programming procedure Selected MAT User MAT User Boot Mat Embedded Program Storage Area -- -- -- O O Notes 1. If the data has been transferred to on-chip RAM in advance, this area can be used. 2. If the MATs have been switched by FMATS in on-chip RAM, this MAT can be used. Rev. 5.00 Feb. 24, 2010 Page 725 of 950 REJ09B0177-0500 24. ROM (SH7058S) Table 24.30 (4) Usable Area for Erasure in User Boot Mode Storable/Executable Area On-Chip RAM User Boot MAT External Space (Expanded Mode with MD0 = 0) Selecting on-chip program to be downloaded O O O O Writing H'A5 to key register O O O O Writing 1 to SCO in FCCS (download) O X X Key register clearing O O O O Judging download result O O O O Download error processing O O O O Setting initialization parameters O O O O Item Erasing procedure Note: * Selected MAT User MAT User Boot Mat O Initialization O X X O Judging initialization result O O O O Initialization error processing O O O O Interrupt processing routine O X O O Switching MATs by FMATS O X X O Writing H'5A to key register O X O O Setting erasure parameters O X O O Erasure O X X O Judging erasure result O X O O Erasing error processing O X* O O O Key register clearing O X O Switching MATs by FMATS O X X O If the MATs have been switched by FMATS in on-chip RAM, this MAT can be used. Rev. 5.00 Feb. 24, 2010 Page 726 of 950 REJ09B0177-0500 Embedded Program Storage Area 25. ROM (SH7059) Section 25 ROM (SH7059) 25.1 Features This LSI has 1.5-Mbyte on-chip flash memory. The flash memory has the following features. * Two flash-memory MATs according to LSI initiation mode The on-chip flash memory has two memory spaces in the same address space (hereafter referred to as memory MATs). The mode setting in the initiation determines which memory MAT is initiated first. The MAT can be switched by using the bank-switching method after initiation. The user MAT is initiated at a power-on reset in user mode: 1.5 Mbyte The user boot MAT is initiated at a power-on reset in user boot mode: 12 Kbytes * Three on-board programming modes and one off-board programming mode On-board programming modes Boot Mode: This mode is a program mode that uses an on-chip SCI interface. The user MAT and user boot MAT can be programmed. This mode can automatically adjust the bit rate between the host and this LSI. User Program Mode: The user MAT can be programmed by using the optional interface. User Boot Mode: The user boot program of the optional interface can be made and the user MAT can be programmed. Off-board programming mode Programmer Mode: This mode uses the PROM programmer. The user MAT and user boot MAT can be programmed. * Programming/erasing interface by the download of on-chip program This LSI has a dedicated programming/erasing program. After downloading this program to the on-chip RAM, programming/erasing can be performed by setting the argument parameter. The user branch is also supported. User branch The program processing is performed in 128-byte units. It consists the program pulse application, verify read, and several other steps. Erasing is performed in one divided-block units and consists of several steps. The user processing routine can be executed between the steps, this setting for which is called the user branch addition. * Emulation function of flash memory by using the on-chip RAM As flash memory is overlapped with part of the on-chip RAM, the flash memory programming can be emulated in real time. * Protection modes There are two protection modes. Software protection by the register setting and hardware protection by the FWE pin. The protection state for flash memory programming/erasing can be set. When abnormalities, such as runaway of programming/erasing are detected, these modes enter the error protection state and the programming/erasing processing is suspended. * Programming/erasing time The flash memory programming time is tP ms (typ) in 128-byte simultaneous programming and tP/128 ms per byte. The erasing time is tE s (typ) per block. * Number of programming The number of flash memory programming can be up to NWEC times. * Operating frequency at programming/erasing The operating frequency at programming/erasing is a maximum of 80 MHz. Rev. 5.00 Feb. 24, 2010 Page 727 of 950 REJ09B0177-0500 25. ROM (SH7059) 25.2 Overview 25.2.1 Block Diagram Internal address bus Internal data bus (32 bits) FCCS FPCS Module bus FECS FKEY Memory MAT unit Control unit FMATS User MAT: 1.5 Mbyte User boot MAT: 12 Kbytes FTDAR RAMER Flash memory FWE pin Mode pins Legend: FCCS: FPCS: FECS: FKEY: FMATS: FTDAR: RAMER: Operating mode Flash code control and status register Flash program code select register Flash erase code select register Flash key code register Flash MAT select register Flash transfer destination address register RAM emulation register Figure 25.1 Block Diagram of Flash Memory Rev. 5.00 Feb. 24, 2010 Page 728 of 950 REJ09B0177-0500 25. ROM (SH7059) 25.2.2 Operating Mode When each mode pin and the FWE pin are set in the reset state and the reset signal is released, the microcomputer enters each operating mode as shown in figure 25.2. For the setting of each mode pin and the FWE pin, see table 25.1. * Flash memory cannot be read, programmed, or erased in ROM invalid mode. The programming/erasing interface registers cannot be written to. When these registers are read, H'00 is always read. * Flash memory can be read in user mode, but cannot be programmed or erased. * Flash memory can be read, programmed, or erased on the board only in user program mode, user boot mode, and boot mode. * Flash memory can be read, programmed, or erased by means of the PROM programmer in programmer mode. RES=0 RES=0 ROM invalid mode ROM invalid mode setting Us mo er p de rog se ram ttin g S= 0 ot S= 0 mo de se ttin g 0 Us RE Bo S= er d mo RE es RE ing ett ot g bo tin er set Us de mo =0 S RE PROM mode Programmer mode setting Reset state FWE=0 User mode User boot mode User program mode FWE=1 Boot mode RAM emulation is enabled On-board programming mode Figure 25.2 Mode Transition of Flash Memory Table 25.1 Relationship between FWE and MD Pins and Operating Modes Mode Reset State ROM Invalid Mode ROM Valid Mode Pin User Program Mode User Boot Mode Boot Mode Programmer Mode RES 0 1 1 1 1 1 1 FWE 0/1 0 0 1 1 1 0/1 MD0 0/1 0/1*1 0/1*2 0/1*2 0/1*2 0/1*2 1 MD1 0/1 0 1 1 0 0 1 MD2 0/1 1 1 1 0 1 0 Notes: 1. MD0 = 0: 8-bit external bus, MD0 = 1: 16-bit external bus 2. MD0 = 0: External bus can be used, MD0 = 1: Single-chip mode (external bus cannot be used) Rev. 5.00 Feb. 24, 2010 Page 729 of 950 REJ09B0177-0500 25. ROM (SH7059) 25.2.3 Mode Comparison The comparison table of programming and erasing related items about boot mode, user program mode, user boot mode, and programmer mode is shown in table 25.2. Table 25.2 Comparison of Programming Modes Boot Mode User Program Mode User Boot Mode Programmer Mode Programming/ erasing environment On-board programming On-board programming On-board programming Off-board programming Programming/ erasing enable MAT User MAT User boot MAT User MAT User MAT User MAT User boot MAT Programming/ erasing control Command method Programming/ erasing interface Programming/ erasing interface Command method All erasure O (Automatic) O O O (Automatic) 1 Block division erasure O* O O X Program data transfer From host via SCI From optional device via RAM From optional device via RAM Via programmer User branch function X O O X RAM emulation X O X X Reset initiation MAT Embedded program storage MAT User MAT User boot MAT*2 Embedded program storage MAT Transition to user mode Mode setting change and reset FWE setting change Mode setting change and reset -- Notes: 1. All-erasure is performed. After that, the specified block can be erased. 2. Initiation starts from the embedded program storage MAT. After checking the flash-memory related registers, initiation starts from the reset vector of the user MAT. * The user boot MAT can be programmed or erased only in boot mode and programmer mode. * The user MAT and user boot MAT are all erased in boot mode. Then, the user MAT and user boot MAT can be programmed by means of the command method. However, the contents of the MAT cannot be read until this state. Only user boot MAT is programmed and the user MAT is programmed in user boot mode or only user MAT is programmed because user boot mode is not used. * In user boot mode, the boot operation of the optional interface can be performed by a mode pin setting different from user program mode. 25.2.4 Flash Memory Configuration This LSI's flash memory is configured by the 1.5-Mbyte user MAT and 12-Kbyte user boot MAT. The start address is allocated to the same address in the user MAT and user boot MAT. Therefore, when the program execution or data access is performed between the two MATs, the MAT must be switched by using FMATS. The user MAT is divided into three 512-Kbyte banks (bank 0, bank 1 and bank 2). The user MAT or user boot MAT can be read in all modes if it is in ROM valid mode. However, the user boot MAT can be programmed only in boot mode and programmer mode. Rev. 5.00 Feb. 24, 2010 Page 730 of 950 REJ09B0177-0500 25. ROM (SH7059) <User MAT> <User Boot MAT> Address H'00,0000 Address H'00,0000 12 Kbytes Address H'00,2FFF Bank 0 512 Kbytes Address H'07,FFFF Address H'08,0000 512 Kbytes Bank 1 Address H'0F,FFFF Address H'10,0000 512 Kbytes Bank 2 Address H'17,FFFF Figure 25.3 Flash Memory Configuration The user MAT and user boot MAT have different memory sizes. Do not access a user boot MAT that is 12 Kbytes or more. When a user boot MAT exceeding 12 Kbytes is read from, an undefined value is read. 25.2.5 Block Division The user MAT is divided into 256 Kbytes (four blocks), 128 Kbytes (three blocks), 96 Kbytes (one block), and 4 Kbytes (eight blocks) as shown in figure 25.4. The user MAT can be erased in this divided-block units and the erase-block number of EB0 to EB15 is specified when erasing. The RAM emulation can be performed in the eight blocks of 4 Kbytes. 512 Kbytes 96 Kbytes Address H'07,FFFF to EB7 <User MAT: Bank 1> Address H'08,0000 <User MAT: Bank 2> Erase block Address H'10,0000 Erase block * 256 Kbytes EB12 256 Kbytes EB13 256 Kbytes EB14 256 Kbytes EB15 EB8 128 Kbytes EB9 128 Kbytes EB10 128 Kbytes EB11 512 Kbytes 4 Kbytes x 8 Erase block EB0 512 Kbytes <User MAT: Bank 0> Address H'00,0000 Address H'0F,FFFF Address H'17,FFFF Note: *RAM emulation can be performed in the eight blocks of 4 Kbytes. Figure 25.4 Block Division of User MAT Rev. 5.00 Feb. 24, 2010 Page 731 of 950 REJ09B0177-0500 25. ROM (SH7059) 25.2.6 Programming/Erasing Interface Programming/erasing is executed by downloading the on-chip program to the on-chip RAM and specifying the program address/data and erase block by using the interface registers/parameters. The procedure program is made by the user in user program mode and user boot mode. The overview of the procedure is as follows. For details, see section 25.5.2, User Program Mode. Start user procedure program for programming/erasing. Select on-chip program to be downloaded and set download destination Download on-chip program by setting VBR, FKEY, and SCO bits. Initialization execution (on-chip program execution) Programming (in 128-byte units) or erasing (in one-block units) (on-chip program execution) No Programming/ erasing completed? Yes End user procedure program Figure 25.5 Overview of User Procedure Program (1) Selection of On-Chip Program to be Downloaded and Setting of Download Destination This LSI has programming/erasing programs and they can be downloaded to the on-chip RAM. The on-chip program to be downloaded is selected by setting the corresponding bits in the programming/erasing interface registers. The download destination can be specified by FTDAR. (2) Download of On-Chip Program The on-chip program is automatically downloaded by clearing VBR of the CPU to H'00000000 and then setting the SCO bit in the flash key code register (FKEY) and the flash code control and status register (FCCS), which are programming/erasing interface registers. The user MAT is replaced to the embedded program storage area when downloading. Since the flash memory cannot be read when programming/erasing, the procedure program, which is working from download to completion of programming/erasing, must be executed in a space other than the flash memory to be programmed/erased (for example, on-chip RAM). Since the result of download is returned to the programming/erasing interface parameters, whether the normal download is executed or not can be confirmed. Note that VBR can be changed after download is completed. Rev. 5.00 Feb. 24, 2010 Page 732 of 950 REJ09B0177-0500 25. ROM (SH7059) (3) Initialization of Programming/Erasing The operating frequency and user branch are set before execution of programming/erasing. The user branch destination must be in an area other than the user MAT area which is in the middle of programming and the area where the on-chip program is downloaded. These settings are performed by using the programming/erasing interface parameters. (4) Programming/Erasing Execution To program or erase, the FWE pin must be brought high and user program mode must be entered. The program data/programming destination address is specified in 128-byte units when programming. The block to be erased is specified in erase-block units when erasing. These specifications are set by using the programming/erasing interface parameters and the on-chip program is initiated. The on-chip program is executed by using the JSR or BSR instruction to perform the subroutine call of the specified address in the on-chip RAM. The execution result is returned to the programming/erasing interface parameters. The area to be programmed must be erased in advance when programming flash memory. There are limitations and notes on the interrupt processing during programming/erasing. For details, see section 25.8.2, Interrupts during Programming/Erasing. (5) When Programming/Erasing is Executed Consecutively When the processing is not ended by the 128-byte programming or one-block erasure, the program address/data and erase-block number must be updated and consecutive programming/erasing is required. Since the downloaded on-chip program is left in the on-chip RAM after the processing, download and initialization are not required when the same processing is executed consecutively. 25.3 Pin Configuration Flash memory is controlled by the pins as shown in table 25.3. Table 25.3 Pin Configuration Pin Name Abbreviation Input/Output Function Power-on reset RES Input Reset Flash programming enable FWE Input Hardware protection when programming flash memory Mode 2 MD2 Input Sets operating mode of this LSI Mode 1 MD1 Input Sets operating mode of this LSI Mode 0 MD0 Input Sets operating mode of this LSI Transmit data TxD1 Output Serial transmit data output (used in boot mode) Receive data RxD1 Input Serial receive data input (used in boot mode) Note: For the pin configuration in PROM mode, see section 25.9, Programmer Mode. Rev. 5.00 Feb. 24, 2010 Page 733 of 950 REJ09B0177-0500 25. ROM (SH7059) 25.4 Register Configuration 25.4.1 Registers The registers/parameters which control flash memory when the on-chip flash memory is valid are shown in table 25.4. There are several operating modes for accessing flash memory, for example, read mode/program mode. There are two memory MATs: user MAT and user boot MAT. The dedicated registers/parameters are allocated for each operating mode and MAT selection. The correspondence of operating modes and registers/parameters for use is shown in table 25.5. Table 25.4 (1) Register Configuration Name Abbreviation*4 R/W Initial Value Address Access Size Flash code control status register FCCS R, W*1 H'00*2 H'80*2 H'FFFFE800 8 Flash program code select register FPCS R/W H'00 H'FFFFE801 8 Flash erase code select register FECS R/W H'00 H'FFFFE802 8 Flash key code register FKEY R/W H'00 H'FFFFE804 8 3 Flash MAT select register FMATS R/W H'00* H'AA*3 H'FFFFE805 8 Flash transfer destination address register FTDAR R/W H'00 H'FFFFE806 8 RAM emulation register RAMER R/W H'0000 H'FFFFEC26 8, 16, 32 Notes: 1. 2. 3. 4. All registers except for RAMER can be accessed only in bytes, and the access requires three cycles. RAMER can be accessed in bytes or words, and the access requires three cycles. The bits except the SCO bit are read-only bits. The SCO bit is a programming-only bit. (The value which can be read is always 0.) The initial value is H'00 when the FWE pin goes low. The initial value is H'80 when the FWE pin goes high. The initial value at initiation in user mode or user program mode is H'00. The initial value at initiation in user boot mode is H'AA. The registers except RAMER can be accessed only in bytes, and the access requires four cycles. Since the RAMER register is in BSC, when it is accessed in bytes, the access requires four cycles, and when it is accessed in longwords, the access requires eight cycles. Rev. 5.00 Feb. 24, 2010 Page 734 of 950 REJ09B0177-0500 25. ROM (SH7059) Table 25.4 (2) Parameter Configuration Name Abbreviation R/W Initial Value Address Access Size Download pass/fail result DPFR R/W Undefined On-chip RAM* 8, 16, 32 Flash pass/fail result FPFR R/W Undefined R0 of CPU 8, 16, 32 Flash multipurpose address area FMPAR R/W Undefined R5 of CPU 8, 16, 32 Flash multipurpose data destination area FMPDR R/W Undefined R4 of CPU 8, 16, 32 Flash erase block select FEBS R/W Undefined R4 of CPU 8, 16, 32 Flash program and erase frequency control FPEFEQ R/W Undefined R4 of CPU 8, 16, 32 Flash user branch address set parameter FUBRA R/W Undefined R5 of CPU 8, 16, 32 Note: * One byte of the start address in the on-chip RAM area specified by FTDAR is valid. Table 25.5 Register/Parameter and Target Mode Download Initialization Programming Erasure Read RAM Emulation Programming/ FCCS O -- -- -- -- -- erasing FPCS O -- -- -- -- -- interface PECS O -- -- -- -- -- registers FKEY O -- O O -- -- FMATS -- -- O*1 O*1 O*2 -- FTDAR O -- -- -- -- -- Programming/ DPFR O -- -- -- -- -- erasing FPFR O O O O -- -- interface FPEFEQ -- O -- -- -- -- FUBRA -- O -- -- -- -- FMPAR -- -- O -- -- -- parameters RAM emulation FMPDR -- -- O -- -- -- FEBS -- -- -- O -- -- RAMER -- -- -- -- -- O Notes: 1. The setting is required when programming or erasing user MAT in user boot mode. 2. The setting may be required according to the combination of initiation mode and read target MAT. Rev. 5.00 Feb. 24, 2010 Page 735 of 950 REJ09B0177-0500 25. ROM (SH7059) 25.4.2 Programming/Erasing Interface Registers The programming/erasing interface registers are as described below. They are all 8-bit registers that can be accessed in bytes. These registers are initialized at a power-on reset, in hardware standby mode, or in software standby mode. (1) Flash Code Control and Status Register (FCCS) FCCS is configured by bits which request the monitor of the FWE pin state and error occurrence during programming or erasing flash memory and the download of the on-chip program. Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 FWE -- -- FLER -- -- -- SCO 1/0 0 0 0 0 0 0 R R R R R R R 0 (R)W * Bit 7--Flash Programming Enable (FWE): Monitors the level which is input to the FWE pin that performs hardware protection of the flash memory programming or erasing. The initial value is 0 or 1 according to the FWE pin state. Bit 7 FWE Description 0 When the FWE pin goes low (in hardware protection state) 1 When the FWE pin goes high * Bits 6 and 5--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 4--Flash Memory Error (FLER): Indicates an error occurs during programming and erasing flash memory. When FLER is set to 1, flash memory enters the error protection state. This bit is initialized at a power-on reset or in hardware standby mode. When FLER is set to 1, high voltage is applied to the internal flash memory. To reduce the damage to flash memory, the reset signal must be released after the reset period of 100 s which is longer than normal. Bit 4 FLER Description 0 Flash memory operates normally Programming/erasing protection for flash memory (error protection) is invalid. [Clearing condition] At a power-on reset or in hardware standby mode 1 Indicates an error occurs during programming/erasing flash memory. Programming/erasing protection for flash memory (error protection) is valid. [Setting condition] See section 25.6.3, Error Protection. (Initial value) * Bits 3 to 1--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 0--Source Program Copy Operation (SCO): Requests the on-chip programming/erasing program to be downloaded to the on-chip RAM. When this bit is set to 1, the on-chip program which is selected by FPCS/FECS is automatically downloaded in the onchip RAM area specified by FTDAR. In order to set this bit to 1, RAM emulation state must be canceled, H'A5 must be written to FKEY, and this operation must be in the on-chip RAM. Eight NOP instructions must be executed immediately after setting this bit to 1. Rev. 5.00 Feb. 24, 2010 Page 736 of 950 REJ09B0177-0500 25. ROM (SH7059) For interrupts during download, see section 25.8.2, Interrupts during Programming/Erasing. For the download time, see section 25.8.3, Other Notes. Since this bit is cleared to 0 when download is completed, this bit cannot be read as 1. Download by setting the SCO bit to 1 requires a special interrupt processing that performs bank switching to the on-chip program storage area. Therefore, before issuing a download request (SCO = 1), set VBR to H'00000000. Otherwise, the CPU gets out of control. Once download end is confirmed, VBR can be changed to any other value. Bit 0 SCO Description 0 Download of the on-chip programming/erasing program to the on-chip RAM is not executed (Initial value) [Clearing condition] When download is completed 1 Request that the on-chip programming/erasing program is downloaded to the on-chip RAM is generated [Clearing conditions] When all of the following conditions are satisfied and 1 is written to this bit * FKEY is written to H'A5 * During execution in the on-chip RAM * Not in RAM emulation mode (RAMS in RAMCR = 0) (2) Flash Program Code Select Register (FPCS) FPCS selects the on-chip programming program to be downloaded. Bit : 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 -- 0 PPVS Initial value : 0 0 0 0 0 0 0 0 R/W : R R R R R R R R/W * Bits 7 to 1--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 0--Program Pulse Single (PPVS): Selects the programming program. Bit 0 PPVS Description 0 On-chip programming program is not selected (Initial value) [Clearing condition] When transfer is completed 1 On-chip programming program is selected (3) Flash Erase Code Select Register (FECS) FECS selects download of the on-chip erasing program. Bit : 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 -- 0 EPVB Initial value : 0 0 0 0 0 0 0 0 R/W : R R R R R R R R/W * Bits 7 to 1--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 0--Erase Pulse Verify Block (EPVB): Selects the erasing program. Rev. 5.00 Feb. 24, 2010 Page 737 of 950 REJ09B0177-0500 25. ROM (SH7059) Bit 0 EPVB Description 0 On-chip erasing program is not selected (Initial value) [Clearing condition] When transfer is completed 1 On-chip erasing program is selected (4) Flash Key Code Register (FKEY) FKEY is a register for software protection that enables download of the on-chip program and programming/erasing of flash memory. Before setting the SCO bit to 1 in order to download the on-chip program or executing the downloaded programming/erasing program, these processings cannot be executed if the key code is not written. Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 K7 K6 K5 K4 K3 K2 K1 K0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W * Bits 7 to 0--Key Code (K7 to K0): Only when H'A5 is written, writing to the SCO bit is valid. When a value other than H'A5 is written to FKEY, 1 cannot be written to the SCO bit. Therefore downloading to the on-chip RAM cannot be executed. Only when H'5A is written, programming/erasing of flash memory can be executed. Even if the on-chip programming/erasing program is executed, flash memory cannot be programmed or erased when a value other than H'5A is written to FKEY. Bits 7 to 0 K7 to K0 Description H'A5 Writing to the SCO bit is enabled (The SCO bit cannot be set by a value other than H'A5.) H'5A Programming/erasing is enabled (A value other than H'A5 enables software protection state.) H'00 Initial value (5) Flash MAT Select Register (FMATS) FMATS specifies whether user MAT or user boot MAT is selected. Bit : Initial value : Initial value : R/W : 7 MS7 0 1 R/W 6 MS6 0 0 R/W 5 MS5 0 1 R/W 4 MS4 0 0 R/W 3 MS3 0 1 R/W 2 MS2 0 0 R/W 1 MS1 0 1 R/W 0 MS0 0 0 R/W (When not in user boot mode) (When in user boot mode) * Bits 7 to 0--MAT Select (MS7 to MS0): These bits are in user-MAT selection state when a value other than H'AA is written and in user-boot-MAT selection state when H'AA is written. The MAT is switched by writing a value in FMATS. When the MAT is switched, follow section 25.8.1, Switching between User MAT and User Boot MAT. (The user boot MAT cannot be programmed in user programming mode if user boot MAT is selected by FMATS. The user boot MAT must be programmed in boot mode or in programmer mode.) Rev. 5.00 Feb. 24, 2010 Page 738 of 950 REJ09B0177-0500 25. ROM (SH7059) Bits 7 to 0 MS7 to MS0 Description H'AA The user boot MAT is selected (in user-MAT selection state when the value of these bits are other than H'AA) Initial value when these bits are initiated in user boot mode. H'00 Initial value when these bits are initiated in a mode except for user boot mode (in user-MAT selection state) [Programmable condition] These bits are in the execution state in the on-chip RAM. (6) Flash Transfer Destination Address Register (FTDAR) FTDAR specifies the on-chip RAM address to which the on-chip program is downloaded. Make settings for FTDAR before writing 1 to the SCO bit in FCCS. The initial value is H'00 which points to the start address (H'FFFE8000) in on-chip RAM. Bit : Initial value : R/W : 7 TDER 0 6 TDA6 0 5 TDA5 0 4 TDA4 0 3 TDA3 0 2 TDA2 0 1 TDA1 0 0 TDA0 0 R/W R/W R/W R/W R/W R/W R/W R/W * Bit 7--Transfer Destination Address Setting Error: This bit is set to 1 when there is an error in the download start address set by bits 6 to 0 (TDA6 to TDA0). Whether the address setting is erroneous or not is judged by checking whether the setting of TDA6 to TDA0 is between the range of H'00 and H'05 after setting the SCO bit in FCCS to 1 and performing download. Before setting the SCO bit to 1 be sure to set the FTDAR value between H'00 to H'05 as well as clearing this bit to 0. Bit 7 TDER Description (Return Value after Download) 0 Setting of TDA6 to TDA0 is normal 1 Setting of TDER and TDA6 to TDA0 is H'06 to H'FF and download has been aborted (Initial value) * Bits 6 to 0--Transfer Destination Address (TDA6 to TDA0): These bits specify the download start address. A value from H'00 to H'05 can be set to specify the download start address in on-chip RAM in 2-Kbyte units. A value from H'06 to H'FF cannot be set. If such a value is set, the TDER bit (bit 7) in this register is set to 1 to prevent download from being executed. Bits 6 to 0 TDA6 to TDA0 Description H'00 Download start address is set to H'FFFE8000 (Initial value) H'01 Download start address is set to H'FFFE8800 H'02 Download start address is set to H'FFFE9000 H'03 Download start address is set to H'FFFE9800 H'04 Download start address is set to H'FFFEA000 H'05 Download start address is set to H'FFFEA800 H'06 to H'FF Setting prohibited. If this value is set, the TDER bit (bit 7) is set to 1 to abort the download processing. Rev. 5.00 Feb. 24, 2010 Page 739 of 950 REJ09B0177-0500 25. ROM (SH7059) 25.4.3 Programming/Erasing Interface Parameters The programming/erasing interface parameters specify the operating frequency, user branch destination address, storage place for program data, programming destination address, and erase block and exchanges the processing result for the downloaded on-chip program. This parameter uses the general registers of the CPU (R4, R5, and R0) or the on-chip RAM area. The initial value is undefined at a power-on reset, in hardware standby mode, or in software standby mode. At download all CPU registers are stored, and at initialization or when the on-chip program is executed, CPU registers except for R0 are stored. The return value of the processing result is written in R0. Since the stack area is used for storing the registers or as a work area, the stack area must be saved at the processing start. (The maximum size of a stack area to be used is 128 bytes.) The programming/erasing interface parameters are used in the following four items. (1) Download control (2) Initialization before programming or erasing (3) Programming (4) Erasing These items use different parameters. The correspondence table is shown in table 25.6. The processing results of initialization, programming, and erasing are returned, but the bit contents have different meanings according to the processing program. See the description of FPFR for each processing. Table 25.6 Usable Parameters and Target Modes Name of Parameter Abbreviation Down-load Initialization Programming Erasure R/W Initial Value Allocation Download DPFR pass/fail result O -- -- -- R/W Undefined On-chip RAM* Flash pass/fail FPFR result -- O O O R/W Undefined R0 of CPU Flash FPEFEQ programming/ erasing frequency control -- O -- -- R/W Undefined R4 of CPU Flash user branch address set parameter FUBRA -- O -- -- R/W Undefined R5 of CPU Flash multipurpose address area FMPAR -- -- O -- R/W Undefined R5 of CPU Flash multipurpose data destination area FMPDR -- -- O -- R/W Undefined R4 of CPU Flash erase block select FEBS -- -- -- O R/W Undefined R4 of CPU Note: * One byte of start address of download destination specified by FTDAR Rev. 5.00 Feb. 24, 2010 Page 740 of 950 REJ09B0177-0500 25. ROM (SH7059) (1) Download Control The on-chip program is automatically downloaded by setting the SCO bit to 1. The on-chip RAM area to be downloaded is the area as much as 3 Kbytes starting from the start address specified by FTDAR. For the address map of the on-chip RAM, see figure 25.10. The download control is set by using the programming/erasing interface registers. The return value is given by the DPFR parameter. (a) Download pass/fail result parameter (DPFR: one byte of start address of on-chip RAM specified by FTDAR) This parameter indicates the return value of the download result. The value of this parameter can be used to determine if downloading is executed or not. Since the confirmation whether the SCO bit is set to 1 is difficult, the certain determination must be performed by setting one byte of the start address of the on-chip RAM area specified by FTDAR to a value other than the return value of download (for example, H'FF) before the download start (before setting the SCO bit to 1). For the checking method of download results, see section 25.5.2, User Program Mode. Bit : 7 6 5 4 3 2 1 0 0 0 0 0 0 SS FK SF * Bits 7 to 3--Unused: Return 0. * Bit 2--Source Select Error Detect (SS): The on-chip program which can be downloaded can be specified as only one type. When more than two types of the program are selected, the program is not selected, or the program is selected without mapping, an error occurs. Bit 2 SS Description 0 Download program can be selected normally 1 Download error occurs (Multi-selection or program which is not mapped is selected) * Bit 1--Flash Key Register Error Detect (FK): Returns the check result whether the value of FKEY is set to H'A5. Bit 1 FK Description 0 FKEY setting is normal (FKEY = H'A5) 1 FKEY setting is abnormal (FKEY = value other than H'A5) * Bit 0--Success/Fail (SF): Returns the result whether download has ended normally or not. Bit 0 SF Description 0 Downloading on-chip program has ended normally (no error) 1 Downloading on-chip program has ended abnormally (error occurs) (2) Programming/Erasing Initialization The on-chip programming/erasing program to be downloaded includes the initialization program. The specified period pulse must be applied when programming or erasing. The specified pulse width is made by the method in which wait loop is configured by the CPU instruction. The operating frequency of the CPU must be set. Since the user branch function is supported, the user branch destination address must be set. The initial program is set as a parameter of the programming/erasing program which has downloaded these settings. Rev. 5.00 Feb. 24, 2010 Page 741 of 950 REJ09B0177-0500 25. ROM (SH7059) (2.1) Flash programming/erasing frequency parameter (FPEFEQ: general register R4 of CPU) This parameter sets the operating frequency of the CPU. For the range of the operating frequency of this LSI, see section 29.3.2, Clock Timing. Bit : Bit : Bit : Bit : 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 F15 F14 F13 F12 F11 F10 F9 F8 7 6 5 4 3 2 1 0 F7 F6 F5 F4 F3 F2 F1 F0 * Bits 31 to 16--Unused: Return 0. * Bits 15 to 0--Frequency Set (F15 to F0): Set the operating frequency of the CPU. The setting value must be calculated as the following methods. 1. The operating frequency which is shown in MHz units must be rounded in a number to three decimal places and be shown in a number of two decimal places. 2. The centuplicated value is converted to the binary digit and is written to the FPEFEQ parameter (general register R4). For example, when the operating frequency of the CPU is 28.882 MHz, the value is as follows. 1. The number to three decimal places of 28.882 is rounded and the value is thus 28.88. 2. The formula that 28.88 x 100 = 2888 is converted to the binary digit and b'0000, 1011, 0100, 1000 (H'0B48) is set to R4. (2.2) Flash user branch address setting parameter (FUBRA: general register R5 of CPU) This parameter sets the user branch destination address. The user program which has been set can be executed in specified processing units when programming and erasing. Bit : 31 UA31 30 UA30 29 UA29 28 UA28 27 UA27 26 UA26 25 UA25 24 UA24 Bit : 23 UA23 22 UA22 21 UA21 20 UA20 19 UA19 18 UA18 17 UA17 16 UA16 Bit : 15 UA15 14 UA14 13 UA13 12 UA12 11 UA11 10 UA10 9 UA9 8 UA8 Bit : 7 UA7 6 UA6 5 UA5 4 UA4 3 UA3 2 UA2 1 UA1 0 UA0 * Bits 31 to 0--User Branch Destination Address (UA31 to UA0): When the user branch is not required, address 0 (H'00000000) must be set. The user branch destination must be an area other than the flash memory, an area other than the RAM area in which onchip program has been transferred, or the external bus space. Note that the CPU must not branch to an area without the execution code and get out of control. The on-chip program download area and stack area must not be overwritten. If CPU runaway occurs or the download area or stack area is overwritten, the value of flash memory cannot be guaranteed. Rev. 5.00 Feb. 24, 2010 Page 742 of 950 REJ09B0177-0500 25. ROM (SH7059) The download of the on-chip program, initialization, initiation of the programming/erasing program must not be executed in the processing of the user branch destination. Programming or erasing cannot be guaranteed when returning from the user branch destination. The program data which has already been prepared must not be programmed. Store general registers R8 to R15 and the control register (GBR). General registers R0 to R7 are available without storing them. Moreover, the programming/erasing interface registers must not be written to or RAM emulation mode must not be entered in the processing of the user branch destination. After the processing of the user branch has ended, the programming/erasing program must be returned to by using the RTS instruction. For the execution intervals of the user branch processing, see note 2 (User branch processing intervals) in section 25.8.3, Other Notes. (2.3) Flash pass/fail result parameter (FPFR: general register R0 of CPU) This parameter indicates the return value of the initialization result. Bit : Bit : Bit : Bit : 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 BR FQ SF * Bits 31 to 3--Unused: Return 0. * Bit 2--User Branch Error Detect (BR): Returns the check result whether the specified user branch destination address is in the area other than the storage area of the programming/erasing program which has been downloaded . Bit 2 BR Description 0 User branch address setting is normal 1 User branch address setting is abnormal * Bit 1--Frequency Error Detect (FQ): Returns the check result whether the specified operating frequency of the CPU is in the range of the supported operating frequency. Bit 1 FQ Description 0 Setting of operating frequency is normal 1 Setting of operating frequency is abnormal * Bit 0--Success/Fail (SF): Indicates whether initialization is completed normally. Rev. 5.00 Feb. 24, 2010 Page 743 of 950 REJ09B0177-0500 25. ROM (SH7059) Bit 0 SF Description 0 Initialization has ended normally (no error) 1 Initialization has ended abnormally (error occurs) (3) Programming Execution When flash memory is programmed, the programming destination address on the user MAT must be passed to the programming program in which the program data is downloaded. 1. The start address of the programming destination on the user MAT is set in general register R5 of the CPU. This parameter is called FMPAR (flash multipurpose address area parameter). Since the program data is always in 128-byte units, the lower eight bits (MOA7 to MOA0) must be H'00 or H'80 as the boundary of the programming start address on the user MAT. 2. The program data for the user MAT must be prepared in the consecutive area. The program data must be in the consecutive space which can be accessed by using the MOV.B instruction of the CPU and is not the flash memory space. When data to be programmed does not satisfy 128 bytes, the 128-byte program data must be prepared by embedding the dummy code (H'FF). The start address of the area in which the prepared program data is stored must be set in general register R4. This parameter is called FMPDR (flash multipurpose data destination area parameter). For details on the programming procedure, see section 25.5.2, User Program Mode. (3.1) Flash multipurpose address area parameter (FMPAR: general register R5 of CPU) This parameter indicates the start address of the programming destination on the user MAT. When an address in an area other than the flash memory space is set, an error occurs. The start address of the programming destination must be at the 128-byte boundary. If this boundary condition is not satisfied, an error occurs. The error occurrence is indicated by the WA bit (bit 1) in FPFR. Bit : 31 MOA31 30 MOA30 29 MOA29 28 MOA28 27 MOA27 26 MOA26 25 MOA25 24 MOA24 Bit : 23 MOA23 22 MOA22 21 MOA21 20 MOA20 19 MOA19 18 MOA18 17 MOA17 16 MOA16 Bit : 15 MOA15 14 MOA14 13 MOA13 12 MOA12 11 MOA11 10 MOA10 9 MOA9 8 MOA8 Bit : 7 MOA7 6 MOA6 5 MOA5 4 MOA4 3 MOA3 2 MOA2 1 MOA1 0 MOA0 * Bits 31 to 0--MOA31 to MOA0: Store the start address of the programming destination on the user MAT. The consecutive 128-byte programming is executed starting from the specified start address of the user MAT. The MOA6 to MOA0 bits are always 0 because the start address of the programming destination is at the 128-byte boundary. (3.2) Flash multipurpose data destination parameter (FMPDR: general register R4 of CPU) This parameter indicates the start address in the area which stores the data to be programmed in the user MAT. When the storage destination of the program data is in flash memory, an error occurs. The error occurrence is indicated by the WD bit (bit 2) in FPFR. Rev. 5.00 Feb. 24, 2010 Page 744 of 950 REJ09B0177-0500 25. ROM (SH7059) Bit : 31 MOD31 30 MOD30 29 MOD29 28 MOD28 27 MOD27 26 MOD26 25 MOD25 24 MOD24 Bit : 23 MOD23 22 MOD22 21 MOD21 20 MOD20 19 MOD19 18 MOD18 17 MOD17 16 MOD16 Bit : 15 MOD15 14 MOD14 13 MOD13 12 MOD12 11 MOD11 10 MOD10 9 MOD9 8 MOD8 Bit : 7 MOD7 6 MOD6 5 MOD5 4 MOD4 3 MOD3 2 MOD2 1 MOD1 0 MOD0 * Bits 31 to 0--MOD31 to MOD0: Store the start address of the area which stores the program data for the user MAT. The consecutive 128-byte data is programmed to the user MAT starting from the specified start address. (3.3) Flash pass/fail parameter (FPFR: general register R0 of CPU) This parameter indicates the return value of the program processing result. Bit : Bit : Bit : Bit : 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 MD EE FK 0 WD WA SF * Bits 31 to 7--Unused: Return 0. * Bit 6--Programming Mode Related Setting Error Detect (MD): Returns the check result of whether the signal input to the FWE pin is high and whether the error protection state is entered. When a low-level signal is input to the FWE pin or the error protection state is entered, 1 is written to this bit. The input level to the FWE pin and the error protection state can be confirmed with the FWE bit (bit 7) and the FLER bit (bit 4) in FCCS, respectively. For conditions to enter the error protection state, see section 25.6.3, Error Protection. Bit 6 MD Description 0 FWE and FLER settings are normal (FWE = 1, FLER = 0) 1 FWE = 0 or FLER = 1, and programming cannot be performed * Bit 5--Programming Execution Error Detect (EE): 1 is returned to this bit when the specified data could not be written because the user MAT was not erased or when flash-memory related register settings are partially changed on returning from the user branch processing. If this bit is set to 1, there is a high possibility that the user MAT is partially rewritten. In this case, after removing the error factor, erase the user MAT. If FMATS is set to H'AA and the user boot MAT is selected, an error occurs when programming is performed. In this case, both the user MAT and user boot MAT are not rewritten. Programming of the user boot MAT must be executed in boot mode or programmer mode. Rev. 5.00 Feb. 24, 2010 Page 745 of 950 REJ09B0177-0500 25. ROM (SH7059) Bit 5 EE Description 0 Programming has ended normally 1 Programming has ended abnormally (programming result is not guaranteed) * Bit 4--Flash Key Register Error Detect (FK): Returns the check result of the value of FKEY before the start of the programming processing. Bit 4 FK Description 0 FKEY setting is normal (FKEY = H'A5) 1 FKEY setting is error (FKEY = value other than H'A5) * Bit 3--Unused: Returns 0. * Bit 2--Write Data Address Detect (WD): When an address in the flash memory area is specified as the start address of the storage destination of the program data, an error occurs. Bit 2 WD Description 0 Setting of write data address is normal 1 Setting of write data address is abnormal * Bit 1--Write Address Error Detect (WA): When the following items are specified as the start address of the programming destination, an error occurs. 1. The programming destination address is an area other than flash memory 2. The specified address is not at the 128-byte boundary (A6 to A0 are not 0) Bit 1 WA Description 0 Setting of programming destination address is normal 1 Setting of programming destination address is abnormal * Bit 0--Success/Fail (SF): Indicates whether the program processing has ended normally or not. Bit 0 SF Description 0 Programming has ended normally (no error) 1 Programming has ended abnormally (error occurs) (4) Erasure Execution When flash memory is erased, the erase-block number on the user MAT must be passed to the erasing program which is downloaded. This is set to the FEBS parameter (general register R4). One block is specified from the block number 0 to 15. For details on the erasing procedure, see section 25.5.2, User Program Mode. Rev. 5.00 Feb. 24, 2010 Page 746 of 950 REJ09B0177-0500 25. ROM (SH7059) (4.1) Flash erase block select parameter (FEBS: general register R4 of CPU) This parameter specifies the erase-block number. Several block numbers cannot be specified. Bit : Bit : Bit : Bit : 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 EBS7 EBS6 EBS5 EBS4 EBS3 EBS2 EBS1 EBS0 * Bits 31 to 8--Unused: Return 0. * Bits 7 to 0--Erase Block (EB7 to EB0): Set the erase-block number in the range from 0 to 15. 0 corresponds to the EB0 block and 15 corresponds to the EB15 block. An error occurs when a number other than 0 to 15 (H'00 to H'0F) is set. (4.2) Flash pass/fail result parameter (FPFR: general register R0 of CPU) This parameter returns the value of the erasing processing result. Bit : Bit : Bit : Bit : 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 MD EE FK EB 0 0 SF * Bits 31 to 7--Unused: Return 0. * Bit 6--Erasure Mode Related Setting Error Detect (MD): Returns the check result of whether the signal input to the FWE pin is high and whether the error protection state is entered. When a low-level signal is input to the FWE pin or the error protection state is entered, 1 is written to this bit. The input level to the FWE pin and the error protection state can be confirmed with the FWE bit (bit 7) and the FLER bit (bit 4) in FCCS, respectively. For conditions to enter the error protection state, see section 25.6.3, Error Protection. Bit 6 MD Description 0 FWE and FLER settings are normal (FWE = 1, FLER = 0) 1 FWE = 0 or FLER = 1, and erasure cannot be performed * Bit 5--Erasure Execution Error Detect (EE): 1 is returned to this bit when the user MAT could not be erased or when flash-memory related register settings are partially changed on returning from the user branch processing. If this bit is set to 1, there is a high possibility that the user MAT is partially erased. In this case, after removing the error factor, erase the user MAT. Rev. 5.00 Feb. 24, 2010 Page 747 of 950 REJ09B0177-0500 25. ROM (SH7059) If FMATS is set to H'AA and the user boot MAT is selected, an error occurs when erasure is performed. In this case, both the user MAT and user boot MAT are not erased. Erasure of the user boot MAT must be executed in boot mode or programmer mode. Bit 5 EE Description 0 Erasure has ended normally 1 Erasure has ended abnormally (erasure result is not guaranteed) * Bit 4--Flash Key Register Error Detect (FK): Returns the check result of FKEY value before start of the erasing processing. Bit 4 FK Description 0 FKEY setting is normal (FKEY = H'5A) 1 FKEY setting is error (FKEY = value other than H'5A) * Bit 3--Erase Block Select Error Detect (EB): Returns the check result whether the specified erase-block number is in the block range of the user MAT. Bit 3 EB Description 0 Setting of erase-block number is normal 1 Setting of erase-block number is abnormal * Bits 2 and 1--Unused: Return 0. * Bit 0--Success/Fail (SF): Indicates whether the erasing processing has ended normally or not. Bit 0 SF Description 0 Erasure has ended normally (no error) 1 Erasure has ended abnormally (error occurs) Rev. 5.00 Feb. 24, 2010 Page 748 of 950 REJ09B0177-0500 25. ROM (SH7059) 25.4.4 RAM Emulation Register (RAMER) When the realtime programming of the user MAT is emulated, RAMER sets the area of the user MAT which is overlapped with a part of the on-chip RAM. RAMER is initialized to H'0000 at a power-on reset or in hardware standby mode, or in software standby mode. The RAMER setting must be executed in user mode or in user program mode. For the division method of the user-MAT area, see table 25.7. In order to operate the emulation function certainly, the target MAT of the RAM emulation must not be accessed immediately after RAMER is programmed. If it is accessed, the normal access is not guaranteed. Bit : 15 14 13 12 11 10 9 Initial value : R/W : 0 0 0 0 0 0 0 0 R R R R R R R R Bit : 7 6 5 4 3 2 1 RAMS Initial value : R/W : 8 0 RAM0 0 0 0 0 0 0 0 0 R R R R R/W R R R/W * Bits 15 to 4, 2, 1--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 3--RAM Select (RAMS): Sets whether the user MAT is emulated or not. When RAMS = 1, all blocks of the user MAT are in the programming/erasing protection state. Bit 3 RAMS Description 0 Emulation is not selected Programming/erasing protection of all user-MAT blocks is invalid 1 Emulation is selected Programming/erasing protection of all user-MAT blocks is valid (Initial value) * Bit 0--User MAT Area Select: These bits are used with bit 3 to select the user-MAT area to be overlapped with the on-chip RAM. (See table 25.7.) Table 25.7 Overlapping of RAM Area and User MAT Area RAM Area H'FFFE8000 to H'FFFEBFFF Block Name RAMS RAM0 RAM area (16 Kbytes) 0 * 1 3 EB0 - EB3 (16 Kbytes) 1 0 2 3 EB4 - EB7 (16 Kbytes) 1 1 H'00000000 to H'00003FFF* * H'00004000 to H'00007FFF* * Legend: * Don't care. Notes: 1. Simultaneously, H'00100000 to H'00103FFF is also overlapped by the same RAM area. 2. Simultaneously, H'00104000 to H'00107FFF is also overlapped by the same RAM area. 3. To prevent overlapping use of a RAM area, either leave one of the affected address areas unused or temporarily disable the RAM emulation function by changing the setting of RAMS to 0 before accessing the address area for which overlapping use is to be avoided. Rev. 5.00 Feb. 24, 2010 Page 749 of 950 REJ09B0177-0500 25. ROM (SH7059) 25.5 On-Board Programming Mode When the pin is set in on-board programming mode and the reset start is executed, the on-board programming state that can program/erase the on-chip flash memory is entered. On-board programming mode has three operating modes: user programming mode, user boot mode, and boot mode. For details on the pin setting for entering each mode, see table 25.1. For details on the state transition of each mode for flash memory, see figure 25.2. 25.5.1 Boot Mode Boot mode executes programming/erasing user MAT and user boot MAT by means of the control command and program data transmitted from the host using the on-chip SCI. The tool for transmitting the control command and program data must be prepared in the host. The SCI communication mode is set to asynchronous mode. When reset start is executed after this LSI's pin is set in boot mode, the boot program in the microcomputer is initiated. After the SCI bit rate is automatically adjusted, the communication with the host is executed by means of the control command method. The RAM areas used by boot mode are 3 Kbytes starting at address H'FFFE8000, 4 Kbytes starting at address H'FFFFB000, and 128 bytes from H'FFFFBF80 to H'FFFFBFFF, which are used as the stack. The system configuration diagram in boot mode is shown in figure 25.6. For details on the pin setting in boot mode, see table 25.1. Interrupts are ignored in boot mode, so do not generate them. Note that the AUD cannot be used during boot mode operation. This LSI Host Boot Control command, program data programming tool and program data Reply response Control command, analysis execution software (on-chip) Flash memory RxD1 On-chip SCI1 TxD1 On-chip RAM Figure 25.6 System Configuration in Boot Mode (1) SCI Interface Setting by Host When boot mode is initiated, this LSI measures the low period of asynchronous SCI-communication data (H'00), which is transmitted consecutively by the host. The SCI transmit/receive format is set to 8-bit data, 1 stop bit, and no parity. This LSI calculates the bit rate of transmission by the host by means of the measured low period and transmits the bit adjustment end sign (1 byte of H'00) to the host. The host must confirm that this bit adjustment end sign (H'00) has been received normally and transmits 1 byte of H'55 to this LSI. When reception is not executed normally, boot mode is initiated again (reset) and the operation described above must be executed. The bit rate between the host and this LSI is not matched because of the bit rate of transmission by the host and system clock frequency of this LSI. To operate the SCI normally, the transfer bit rate of the host must be set to 9,600 bps or 19,200 bps. The system clock frequency which can automatically adjust the transfer bit rate of the host and the bit rate of this LSI is shown in table 25.8. Boot mode must be initiated in the range of this system clock. Rev. 5.00 Feb. 24, 2010 Page 750 of 950 REJ09B0177-0500 25. ROM (SH7059) Start bit D0 D1 D2 D3 D4 D5 Measure low period (9 bits) (data is H'00) D6 D7 Stop bit High period of at least 1 bit Figure 25.7 Automatic Adjustment Operation of SCI Bit Rate Table 25.8 System Clock Frequency that Can Automatically Adjust Bit Rate of This LSI Host Bit Rate System Clock Frequency Which Can Automatically Adjust LSI's Bit Rate 9,600 bps 40 to 80 MHz (input frequency of 5 to 10 MHz) 19,200 bps 40 to 80 MHz (input frequency of 5 to 10 MHz) (2) State Transition The overview of the state transition after boot mode is initiated is shown in figure 25.8. For details on boot mode, see section 25.10.1, Serial Communications Interface Specification for Boot Mode. 1. Bit rate adjustment After boot mode is initiated, the bit rate of the SCI interface is adjusted with that of the host. 2. Waiting for inquiry set command For inquiries about the user-MAT size and configuration, MAT start address, and support state, the required information is transmitted to the host. 3. Automatic erasure of all user MAT and user boot MAT After inquiries have finished, all of the user MAT and user boot MAT are automatically erased if a programming/erasing status transition command is sent. 4. Waiting for programming/erasing command * When the program selection command is received, the state for waiting program data is entered. The programming start address and program data must be transmitted following the programming command. When programming is finished, the programming start address must be set to H'FFFFFFFF and transmitted. Then the state for waiting program data is returned to the state of programming/erasing command wait. * When the erasure selection command is received, the state for waiting erase-block data is entered. The eraseblock number must be transmitted following the erasing command. When the erasure is finished, the eraseblock number must be set to H'FF and transmitted. Then the state for waiting erase-block data is returned to the state for waiting programming/erasing command. The erasure must be executed when reset start is not executed and the specified block is programmed after programming is executed in boot mode. When programming can be executed by only one operation, all blocks are erased before the state for waiting programming/erasing/other command is entered. The erasing operation is not required. * There are many commands other than programming/erasing. Examples are checksum, blank check (erasure check), and memory read of the user MAT/user boot MAT and acquisition of current status information. Note that memory read of the user MAT/user boot MAT can only read the program data after all user MAT/user boot MAT has automatically been erased. Rev. 5.00 Feb. 24, 2010 Page 751 of 950 REJ09B0177-0500 25. ROM (SH7059) (Bit rate adjustment) H'00 to H'00 reception Boot mode initiation (reset by boot mode) Bit rate adjustment H'55 rece Inquiry command reception 2 Wait for inquiry setting command Inquiry command response Processing of inquiry setting command All user MAT and user boot MAT erasure 3 4 1 ption Wait for programming/erasing command Read/check command reception Processing of read/check command Command response Erasure selection command reception Erasure end notice Program end notice Program selection command reception Program data transmission Erase-block specification Wait for erase-block data Wait for program data Figure 25.8 Overview of Boot Mode State Transition Rev. 5.00 Feb. 24, 2010 Page 752 of 950 REJ09B0177-0500 25. ROM (SH7059) 25.5.2 User Program Mode The user MAT can be programmed/erased in user program mode. (The user boot MAT cannot be programmed/erased.) Programming/erasing is executed by downloading the program in the microcomputer. The overview flow is shown in figure 25.9. High voltage is applied to internal flash memory during the programming/erasing processing. Therefore, transition to reset or hardware standby mode must not be executed. Doing so may cause damage or destroy flash memory. If reset is executed accidentally, the reset signal must be released after the reset input period, which is longer than the normal 100 s. For details on the programming procedure, see the description in 25.5.2 (2) Programming Procedure in User Program Mode. For details on the erasing procedure, see the description in 25.5.2 (3) Erasing Procedure in User Program Mode. For the overview of a processing that repeats erasing and programming by downloading the programming program and the erasing program in separate on-chip ROM areas using FTDAR, see the description in 25.5.2 (4) Erasing and Programming Procedure in User Program Mode. Programming/erasing start 1. RAM emulation mode must be canceled in advance. Download cannot be executed in emulation mode. When programming, program data is prepared FWE=1 ? Yes Programming/erasing procedure program is transferred to the on-chip RAM and executed Programming/erasing end No 2. When the program data is made by means of emulation, the download destination must be changed by FTDAR. With the initial setting of FTDAR (H'00), the download area is overlapped with the emulation area. 3. Inputting high level to the FWE pin sets the FWE bit to 1. 4. Programming/erasing is executed only in the on-chip RAM. However, if the program data is in a consecutive area and can be accessed by the MOV.B instruction of the CPU like SRAM/ROM, the program data can be in an external space. 5. After programming/erasing is finished, low level must be input to the FWE pin for protection. Figure 25.9 Programming/Erasing Overview Flow (1) On-Chip RAM Address Map when Programming/Erasing is Executed Parts of the procedure program that are made by the user, like download request, programming/erasing procedure, and judgement of the result, must be executed in the on-chip RAM. All of the on-chip program that is to be downloaded is in on-chip RAM. Note that on-chip RAM must be controlled so that these parts do not overlap. Figure 25.10 shows the program area to be downloaded. Rev. 5.00 Feb. 24, 2010 Page 753 of 950 REJ09B0177-0500 25. ROM (SH7059) Area to be downloaded (Size: 3 Kbytes) Unusable area in programming/erasing processing period <On-chip RAM> RAM emulation area or area that can be used by user DPFR (Return value: 1 byte) System use area (15 bytes) Programming/ erasing entry Address RAMTOP (H'FFFE8000) FTDAR setting FTDAR setting+16 FTDAR setting+32 Initialization process entry Initialization + programming program or Initialization + erasing program Area that can be used by user FTDAR setting+3072 RAMEND (H'FFFFBFFF) Figure 25.10 RAM Map after Download (2) Programming Procedure in User Program Mode The procedures for download, initialization, and programming are shown in figure 25.11. Start programming procedure program 1 Download Set FKEY to H'A5 (2.2) Set parameter to R4 and R5 (FMPAR and FMPDR) (2.10) Programming JSR FTDAR setting+16 (2.11) (2.3) Clear FKEY to 0 (2.4) Yes FPFR=0? Yes (2.5) No No Download error processing Set the FPEFEQ and FUBRA parameters Initialization Set FKEY to H'5A After clearing VBR, set SCO to 1 and execute download DPFR=0? Required data programming is completed? Clear FKEY to 0 FPFR=0? Yes (2.7) (2.8) End programming procedure program No Initialization error processing 1 Figure 25.11 Programming Procedure Rev. 5.00 Feb. 24, 2010 Page 754 of 950 REJ09B0177-0500 (2.12) No Clear FKEY and programming error processing (2.13) Yes (2.6) Initialization JSR FTDAR setting+32 (2.9) (2.1) Programming Select on-chip program to be downloaded and set download destination by FTDAR (2.14) 25. ROM (SH7059) The details of the programming procedure are described below. The procedure program must be executed in an area other than the flash memory to be programmed. Especially the part where the SCO bit in FCCS is set to 1 for downloading must be executed in the on-chip RAM. The area that can be executed in the steps of the user procedure program (on-chip RAM, user MAT, and external space) is shown in section 25.10.3, Storable Area for Procedure Program and Programming Data. The following description assumes the area to be programmed on the user MAT is erased and program data is prepared in the consecutive area. When erasing has not been executed, carry out erasing before writing. 128-byte programming is performed in one program processing. When more than 128-byte programming is performed, programming destination address/program data parameter is updated in 128-byte units and programming is repeated. When less than 128-byte programming is performed, data must total 128 bytes by adding the invalid data. If the invalid data to be added is H'FF, the program processing period can be shortened. (2.1) Select the on-chip program to be downloaded When the PPVS bit of FPCS is set to 1, the programming program is selected. Several programming/erasing programs cannot be selected at one time. If several programs are set, download is not performed and a download error is returned to the source select error detect (SS) bit in the DPFR parameter. Specify the start address of the download destination by FTDAR. (2.2) Write H'A5 in FKEY If H'A5 is not written to FKEY for protection, 1 cannot be written to the SCO bit for a download request. (2.3) VBR is cleared to 0 and 1 is written to the SCO bit of FCCS, and then download is executed. VBR must always be cleared to H'00000000 before setting the SCO bit to 1. To write 1 to the SCO bit, the following conditions must be satisfied. * RAM emulation mode is canceled. * H'A5 is written to FKEY. * The SCO bit writing is executed in the on-chip RAM. When the SCO bit is set to 1, download is started automatically. When execution returns to the user procedure program, the SCO bit is cleared to 0. Therefore, the SCO bit cannot be confirmed to be 1 in the user procedure program. The download result can be confirmed only by the return value of the DPFR parameter. Before the SCO bit is set to 1, incorrect judgement must be prevented by setting the DPFR parameter, that is one byte of the start address of the onchip RAM area specified by FTDAR, to a value other than the return value (H'FF). When download is executed, particular interrupt processing, which is accompanied by the bank switch as described below, is performed as an internal microcomputer processing, so VBR need to be cleared to 0. Eight NOP instructions are executed immediately after the instructions that set the SCO bit to 1. * The user MAT space is switched to the on-chip program storage area. * After the selection condition of the download program and the address set in FTDAR are checked, the transfer processing is executed starting from the on-chip RAM address specified by FTDAR. * The SCO bits in FPCS, FECS, and FCCS are cleared to 0. * The return value is set to the DPFR parameter. * After the on-chip program storage area is returned to the user MAT space, execution returns to the user procedure program. After download is completed and the user procedure program is running, the VBR setting can be changed. The notes on download are as follows. In the download processing, the values of the general registers of the CPU are retained. During the download processing, the interrupt processing cannot be executed. However, the NMI, UBC, and H-UDI interrupt requests are retained, so that on returning to the user procedure program, the interrupt processing starts. For details on the relationship between download and interrupts, see section 25.8.2, Interrupts during Programming/Erasing. Rev. 5.00 Feb. 24, 2010 Page 755 of 950 REJ09B0177-0500 25. ROM (SH7059) Since a stack area of maximum 128 bytes is used, an area of at least 128 bytes must be saved before setting the SCO bit to 1. If an access by the DMAC or AUD occurs during download, operation cannot be guaranteed. Therefore, access by the DMAC or AUD must not be executed. (2.4) FKEY is cleared to H'00 for protection. (2.5) The value of the DPFR parameter must be checked to confirm the download result. A recommended procedure for confirming the download result is shown below. * Check the value of the DPFR parameter (one byte of start address of the download destination specified by FTDAR). If the value is H'00, download has been performed normally. If the value is not H'00, the source that caused download to fail can be investigated by the description below. * If the value of the DPFR parameter is the same as before downloading (e.g. H'FF), the address setting of the download destination in FTDAR may be abnormal. In this case, confirm the setting of the TDER bit (bit 7) in FTDAR. * If the value of the DPFR parameter is different from before downloading, check the SS bit (bit 2) and the FK bit (bit 1) in the DPFR parameter to ensure that the download program selection and FKEY register setting were normal, respectively. (2.6) The operating frequency is set to the FPEFEQ parameter and the user branch destination is set to the FUBRA parameter for initialization. * The current frequency of the CPU clock is set to the FPEFEQ parameter (general register R4). For the settable range of the FPEFEQ parameter, see section 29.3.2, Clock Timing. For the settable range of the FPEFEQ parameter, see section 29.3.2, Clock Timing. When the frequency is set out of this range, an error is returned to the FPFR parameter of the initialization program and initialization is not performed. For details on the frequency setting, see the description in 25.4.3 (2.1) Flash programming/erasing frequency parameter (FPEFEQ). * The start address in the user branch destination is set to the FUBRA parameter (general register R5). When the user branch processing is not required, 0 must be set to FUBRA. When the user branch is executed, the branch destination is executed in flash memory other than the one that is to be programmed. The area of the on-chip program that is downloaded cannot be set. The program processing must be returned from the user branch processing by the RTS instruction. See the description in 25.4.3 (2.2) Flash user branch address setting parameter (FUBRA). (2.7) Initialization When a programming program is downloaded, the initialization program is also downloaded to on-chip RAM. There is an entry point of the initialization program in the area from (download start address set by FTDAR) + 32 bytes. The subroutine is called and initialization is executed by using the following steps. MOV.L #DLTOP+32,R1 ; Set entry address to R1 JSR @R1 ; Call initialization routine NOP * The general registers other than R0 are saved in the initialization program. * R0 is a return value of the FPFR parameter. * Since the stack area is used in the initialization program, a stack area of maximum 128 bytes must be reserved in RAM. * Interrupts can be accepted during the execution of the initialization program. However, the program storage area and stack area in on-chip RAM and register values must not be destroyed. (2.8) The return value of the initialization program, FPFR (general register R0) is judged. (2.9) FKEY must be set to H'5A and the user MAT must be prepared for programming. (2.10) The parameter which is required for programming is set. Rev. 5.00 Feb. 24, 2010 Page 756 of 950 REJ09B0177-0500 25. ROM (SH7059) The start address of the programming destination of the user MAT (FMPAR) is set to general register R5. The start address of the program data storage area (FMPDR) is set to general register R4. * FMPAR setting FMPAR specifies the programming destination start address. When an address other than one in the user MAT area is specified, even if the programming program is executed, programming is not executed and an error is returned to the return value parameter FPFR. Since the unit is 128 bytes, the lower eight bits (MOA7 to MOA0) must be in the 128-byte boundary of H'00 or H'80. * FMPDR setting If the storage destination of the program data is flash memory, even when the program execution routine is executed, programming is not executed and an error is returned to the FPFR parameter. In this case, the program data must be transferred to on-chip RAM and then programming must be executed. (2.11) Programming There is an entry point of the programming program in the area from (download start address set by FTDAR) + 16 bytes of on-chip RAM. The subroutine is called and programming is executed by using the following steps. MOV.L #DLTOP+16,R1 ; Set entry address to R1 JSR @R1 ; Call programming routine NOP The general registers other than R0 are saved in the programming program. R0 is a return value of the FPFR parameter. Since the stack area is used in the programming program, a stack area of maximum 128 bytes must be reserved in RAM. (2.12) The return value in the programming program, FPFR (general register R0) is judged. (2.13) Determine whether programming of the necessary data has finished. If more than 128 bytes of data are to be programmed, specify FMPAR and FMPDR in 128-byte units, and repeat steps (2.10) to (2.13). Increment the programming destination address by 128 bytes and update the programming data pointer correctly. If an address which has already been programmed is written to again, not only will a programming error occur, but also flash memory will be damaged. (2.14) After programming finishes, clear FKEY and specify software protection. If this LSI is restarted by a power-on reset immediately after user MAT programming has finished, secure a reset period (period of RES = 0) that is at least as long as the normal 100 s. Rev. 5.00 Feb. 24, 2010 Page 757 of 950 REJ09B0177-0500 25. ROM (SH7059) (3) Erasing Procedure in User Program Mode The procedures for download, initialization, and erasing are shown in figure 25.12. Start erasing procedure program 1 Set FKEY to H'5A (3.1) Set FKEY to H'A5 Set FEBS parameter (3.2) After clearing VBR, set SCO to 1 and execute download Erasing JSR FTDAR setting+16 (3.3) Erasing Download Select on-chip program to be downloaded and set download destination by FTDAR Clear FKEY to 0 Yes DPFR = 0? Yes No No Download error processing No Clear FKEY and erasing error processing Required block erasing is completed? Set the FPEFEQ and FUBRA parameters Initialization (3.4) FPFR=0 ? (3.5) Yes Clear FKEY to 0 Initialization JSR FTDAR setting+32 (3.6) End erasing procedure program FPFR=0 ? No Yes Initialization error processing 1 Figure 25.12 Erasing Procedure The details of the erasing procedure are described below. The procedure program must be executed in an area other than the user MAT to be erased. Especially the part where the SCO bit in FCCS is set to 1 for downloading must be executed in on-chip RAM. The area that can be executed in the steps of the user procedure program (on-chip RAM, user MAT, and external space) is shown in section 25.10.3, Storable Area for Procedure Program and Programming Data. For the downloaded on-chip program area, see the RAM map for programming/erasing in figure 25.10. A single divided block is erased by one erasing processing. For block divisions, see figure 25.4. To erase two or more blocks, update the erase block number and perform the erasing processing for each block. (3.1) Select the on-chip program to be downloaded Set the EPVB bit in FECS to 1. Several programming/erasing programs cannot be selected at one time. If several programs are set, download is not performed and a download error is returned to the source select error detect (SS) bit in the DPFR parameter. Specify the start address of the download destination by FTDAR. The procedures to be carried out after setting FKEY, e.g. download and initialization, are the same as those in the programming procedure. For details, see the description in 25.5.2 (2) Programming Procedure in User Program Mode. (3.2) Set the FEBS parameter necessary for erasure Set the erase block number of the user MAT in the flash erase block select parameter (FEBS: general register R4). If a value other than an erase block number of the user MAT is set, no block is erased even though the erasing program is executed, and an error is returned to the return value parameter FPFR. Rev. 5.00 Feb. 24, 2010 Page 758 of 950 REJ09B0177-0500 25. ROM (SH7059) (3.3) Erasure Similar to as in programming, there is an entry point of the erasing program in the area from (download start address set by FTDAR) + 16 bytes of on-chip RAM. The subroutine is called and erasing is executed by using the following steps. MOV.L #DLTOP+16,R1 ; Set entry address to R1 JSR @R1 ; Call erasing routine NOP The general registers other than R0L are saved in the erasing program. R0 is a return value of the FPFR parameter. Since the stack area is used in the erasing program, a stack area of maximum 128 bytes must be reserved in RAM. (3.4) The return value in the erasing program, FPFR (general register R0) is judged. (3.5) Determine whether erasure of the necessary blocks has finished. If more than one block is to be erased, update the FEBS parameter and repeat steps (3.2) to (3.5). Blocks that have already been erased can be erased again. (3.6) After erasure finishes, clear FKEY and specify software protection. If this LSI is restarted by a power-on reset immediately after user MAT programming has finished, secure a reset period (period of RES = 0) that is at least as long as the normal 100 s. (4) Erasing and Programming Procedure in User Program Mode By changing the on-chip RAM address of the download destination in FTDAR, the erasing program and programming program can be downloaded to separate on-chip RAM areas. Figure 25.13 shows an example of repetitively executing RAM emulation, erasing, and programming. 1 Set FTDAR to H'02 (Specify H'FFFE9000 as download destination) Download erasing program Programming program download Initialize erasing program Set FTDAR to H'04 (Specify H'FFFEA000 as download destination) Enter RAM emulation mode and tune data in on-chip RAM Emulation/Erasing/Programming Erasing program download Start procedure program Cancel RAM emulation mode Erase relevant block (execute erasing program) Set FMPDR to H'FFFE8000 to program relevant block (execute programming program) Download programming program Confirm operation Initialize programming program End? No Yes 1 End procedure program Figure 25.13 Sample Procedure of Repeating RAM Emulation, Erasing, and Programming (Overview) Rev. 5.00 Feb. 24, 2010 Page 759 of 950 REJ09B0177-0500 25. ROM (SH7059) In the above example, the erasing program and programming program are downloaded to areas excluding the 4 Kbytes (H'FFFE8000 to H'FFFE8FFF) from the start of on-chip ROM. Download and initialization are performed only once at the beginning. In this kind of operation, note the following: * Be careful not to damage on-chip RAM with overlapped settings. In addition to the RAM emulation area, erasing program area, and programming program area, areas for the user procedure programs, work area, and stack area are reserved in on-chip RAM. Do not make settings that will overwrite data in these areas. * Be sure to initialize both the erasing program and programming program. Initialization by setting the FPEFEQ and FUBRA parameters must be performed for both the erasing program and the programming program. Initialization must be executed for both entry addresses: (download start address for erasing program) + 32 bytes (H'FFFE9020 in this example) and (download start address for programming program) + 32 bytes (H'FFFEA020 in this example). 25.5.3 User Boot Mode This LSI has user boot mode which is initiated with different mode pin settings than those in user program mode or boot mode. User boot mode is a user-arbitrary boot mode, unlike boot mode that uses the on-chip SCI. Only the user MAT can be programmed/erased in user boot mode. Programming/erasing of the user boot MAT is only enabled in boot mode or programmer mode. (1) User Boot Mode Initiation For the mode pin settings to start up user boot mode, see table 25.1, Relationship between FWE and MD pins and Operating Modes. When the reset start is executed in user boot mode, the check routine for flash-memory related registers runs. The RAM area about 3 Kbytes from H'FFFFB000 and 128 bytes from H'FFFFBF80 to H'FFFFBFFF (a stack area) is used by the routine. While the check routine is running, NMI and all other interrupts cannot be accepted. Neither can the AUD be used in this period. This period is approximately 100 s while operating at an internal frequency of 80 MHz. Next, processing starts from the execution start address of the reset vector in the user boot MAT. At this point, H'AA is set to the flash MAT select register (FMATS) because the execution MAT is the user boot MAT. (2) User MAT Programming in User Boot Mode For programming the user MAT in user boot mode, additional processings made by setting FMATS are required: switching from user-boot-MAT selection state to user-MAT selection state, and switching back to user-boot-MAT selection state after programming completes. Figure 25.14 shows the procedure for programming the user MAT in user boot mode. Rev. 5.00 Feb. 24, 2010 Page 760 of 950 REJ09B0177-0500 25. ROM (SH7059) Start programming procedure program 1 Select on-chip program to be downloaded and set download destination by FTDAR Set FMATS to value other than H'AA to select user MAT No Download error processing Set the FPEFEQ and FUBRA parameters Initialization JSR FTDAR setting+32 FPFR=0 ? Set parameter to R4 and R5 (FMPAR and FMPDR) Programming JSR FTDAR setting+16 Programming Clear FKEY to 0 Yes MAT switchover Set FKEY to H'A5 User-MAT selection state Download After clearing VBR, set SCO to 1 and execute download DPFR=0 ? Initialization User-boot-MAT selection state Set FKEY to H'A5 FPFR=0 ? No Yes Clear FKEY and programming error processing* No Required data programming is completed? Yes No Clear FKEY to 0 Yes Initialization error processing Set FMATS to H'AA to select user boot MAT 1 User-boot-MAT selection state MAT switchover End programming procedure program Note: * The MAT must be switched by FMATS to perform the programming error processing in the user boot MAT. Figure 25.14 Procedure for Programming User MAT in User Boot Mode The difference between the programming procedures in user program mode and user boot mode is whether the MAT is switched or not as shown in figure 25.14. In user boot mode, the user boot MAT can be seen in the flash memory space with the user MAT hidden in the background. The user MAT and user boot MAT are switched only while the user MAT is being programmed. Because the user boot MAT is hidden while the user MAT is being programmed, the procedure program must be located in an area other than flash memory. After programming finishes, switch the MATs again to return to the first state. MAT switchover is enabled by writing a specific value to FMATS. However note that while the MATs are being switched, the LSI is in an unstable state, e.g. access to a MAT is not allowed until MAT switching is completely finished, and if an interrupt occurs, from which MAT the interrupt vector is read from is undetermined. Perform MAT switching in accordance with the description in section 25.8.1, Switching between User MAT and User Boot MAT. Except for MAT switching, the programming procedure is the same as that in user program mode. The area that can be executed in the steps of the user procedure program (on-chip RAM, user MAT, and external space) is shown in section 25.10.3, Storable Area for Procedure Program and Programming Data. (3) User MAT Erasing in User Boot Mode For erasing the user MAT in user boot mode, additional processings made by setting FMATS are required: switching from user-boot-MAT selection state to user-MAT selection state, and switching back to user-boot-MAT selection state after erasing completes. Figure 25.15 shows the procedure for erasing the user MAT in user boot mode. Rev. 5.00 Feb. 24, 2010 Page 761 of 950 REJ09B0177-0500 25. ROM (SH7059) Start erasing procedure program 1 Select on-chip program to be downloaded and set download destination by FTDAR Set FMATS to value other than H'AA to select user MAT Set FKEY to H'5A Yes No Download error processing Set the FPEFEQ and FUBRA parameters Initialization JSR FTDAR setting+32 FPFR=0 ? Set FEBS parameter Programming JSR FTDAR setting+16 Erasing Clear FKEY to 0 User-MAT selection state Download After clearing VBR, set SCO to 1 and execute download DPFR=0 ? Initialization User-boot-MAT selection state Set FKEY to H'A5 MAT switchover FPFR=0 ? No No Yes Clear FKEY and erasing error processing* Required block erasing is completed? Yes No Clear FKEY to 0 Yes Initialization error processing 1 Set FMATS to H'AA to select user boot MAT User-boot-MAT selection state MAT switchover End erasing procedure program Note: * The MAT must be switched by FMATS to perform the erasing error processing in the user boot MAT. Figure 25.15 Procedure for Erasing User MAT in User Boot Mode The difference between the erasing procedures in user program mode and user boot mode depends on whether the MAT is switched or not as shown in figure 25.15. MAT switching is enabled by writing a specific value to FMATS. However note that while the MATs are being switched, the LSI is in an unstable state, e.g. access to a MAT is not allowed until MAT switching is completed finished, and if an interrupt occurs, from which MAT the interrupt vector is read from is undetermined. Perform MAT switching in accordance with the description in section 25.8.1, Switching between User MAT and User Boot MAT. Except for MAT switching, the erasing procedure is the same as that in user program mode. The area that can be executed in the steps of the user procedure program (on-chip RAM, user MAT, and external space) is shown in section 25.10.3, Storable Area for Procedure Program and Programming Data. Rev. 5.00 Feb. 24, 2010 Page 762 of 950 REJ09B0177-0500 25. ROM (SH7059) 25.6 Protection There are three kinds of flash memory program/erase protection: hardware, software, and error protection. 25.6.1 Hardware Protection Programming and erasing of flash memory is forcibly disabled or suspended by hardware protection. In this state by the FWE pin, the downloading of an on-chip program and initialization of the flash memory are possible. However, an activated program for programming or erasure cannot program or erase locations in a user MAT, and the error in programming/erasing is reported in the FPFR parameter. Table 25.9 Hardware Protection Function to be Protected Item Description Download Programming/ Erasure FWE-pin protection The input of a low-level signal on the FWE pin clears the FWE bit of FCCS and the LSI enters a programming/erasing-protected state. -- O Reset/standby protection * A power-on reset (including a power-on reset by the WDT) and entry to standby mode initializes the programming/erasing interface registers and the LSI enters a programming/erasing-protected state. O O * Resetting by means of the RES pin after power is initially supplied will not make the LSI enter the reset state unless the RES pin is held low until oscillation has stabilized. In the case of a reset during operation, hold the RES pin low for the RES pulse width that is specified in the section on AC characteristics. If the LSI is reset during programming or erasure, data in the flash memory is not guaranteed. In this case, execute erasure and then execute programming again. Rev. 5.00 Feb. 24, 2010 Page 763 of 950 REJ09B0177-0500 25. ROM (SH7059) 25.6.2 Software Protection Software protection is set up in any of three ways: by disabling the downloading of on-chip programs for programming and erasing, by means of a key code, and by the RAM emulation register (RAMER). Table 25.10 Software Protection Function to be Protected Item Description Download Programming/ Erasure Protection by the SCO bit Clearing the SCO bit in FCCS disables downloading of the programming/erasing program, thus making the LSI enter a programming/erasing-protected state. O O Protection by FKEY Downloading and programming/erasing are disabled unless the required key code is written in FKEY. Different key codes are used for downloading and for programming/erasing. O O Emulation protection Setting the RAMS bit in RAMER to 1 makes the LSI enter a programming/erasingprotected state. O O 25.6.3 Error Protection Error protection is a mechanism for aborting programming or erasure when an error occurs, in the form of the microcomputer getting out of control during programming/erasing of the flash memory or operations that are not in accordance with the established procedures for programming/erasing. Aborting programming or erasure in such cases prevents damage to the flash memory due to excessive programming or erasing. If the microcomputer malfunctions during programming/erasing of the flash memory, the FLER bit in FCCS is set to 1 and the LSI enters the error protection state, thus aborting programming or erasure. The FLER bit is set to 1 in the following conditions: * Flash memory is read during programming/erasing (including a vector read or an instruction fetch) * When a SLEEP instruction is executed during programming/erasing Error protection is cancelled (FLER bit is cleared) by a power-on reset, in software standby mode, or in hardware-standby mode. Note that the reset signal should only be released after providing a reset input over a period longer than the normal 100 s. Since high voltages are applied during programming/erasing of the flash memory, some voltage may still remain even after the error protection state has been entered. For this reason, it is necessary to reduce the risk of damage to the flash memory by extending the reset period so that the charge is released. The state-transition diagram in figure 25.16 shows transitions to and from the error protection state. Rev. 5.00 Feb. 24, 2010 Page 764 of 950 REJ09B0177-0500 25. ROM (SH7059) Program mode Erase mode Read disabled Programming/erasing enabled FLER=0 = 0 or =0 Er Error occurred ror =0 oc (S curr oft e wa d re sta nd Error protection mode Read enabled Programming/erasing disabled FLER=1 or by ) Software standby mode Reset or standby (Hardware protection) Read enabled Programming/erasing disabled FLER=0 =0 Programming/erasing interface register is in its initial state. =0 , =0 or software standby mode cancellation (Software standby) Read disabled Programming/erasing disabled FLER=undefined The power is not supplied in this LSI. Figure 25.16 Transitions to and from Error Protection State Rev. 5.00 Feb. 24, 2010 Page 765 of 950 REJ09B0177-0500 25. ROM (SH7059) 25.7 Flash Memory Emulation in RAM To provide real-time emulation in RAM of data that is to be written to the flash memory, a part of the RAM can be overlaid on an area of flash memory (user MAT) that has been specified by the RAM emulation register (RAMER). After the RAMER setting is made, the RAM is accessible in both the user MAT area and as the RAM area that has been overlaid on the user MAT area. Such emulation is possible in user mode and user program mode. Figure 25.17 shows an example of the emulation of realtime programming of the user MAT area. Start of emulation program Set RAMER Write the data for tuning to the overlapped RAM area Execute application program No Tuning OK? Yes Cancel RAMER setting Program the emulation block in the user MAT End of emulation program Figure 25.17 Emulation of Flash Memory in RAM Rev. 5.00 Feb. 24, 2010 Page 766 of 950 REJ09B0177-0500 25. ROM (SH7059) This area is accessible as both a RAM area and as a flash memory area. H'000000 EB0 H'001000 EB1 H'002000 EB2 H'003000 EB3 H'004000 EB4 H'005000 EB5 H'006000 EB6 H'007000 EB7 H'FFFE8000 H'FFFEBFFF H'008000 Flash memory (user MAT) On-chip RAM EB8 to EB15 H'17FFFF H'FFFFBFFF Figure 25.18 Example of Overlapped RAM Operation Figure 25.18 shows an example of an overlap on block areas EB0 to EB3 of the flash memory. Emulation is possible for four areas selected from among the eight areas, from EB0 to EB7, of the user MAT. The area is selected by the setting of the RAM0 bit in RAMER. (1) To overlap a part of the RAM on areas EB0 to EB3, to allow realtime programming of the data for this area, set the RAMS bit in RAMER to 1, and each of the RAM0 bit to 0. (2) Realtime programming is carried out using the overlaid area of RAM. In programming or erasing the user MAT, it is necessary to run a program that implements a series of procedural steps, including the downloading of an on-chip program. In this state, note that the RAM area overlaps with the area where the on-chip program is downloaded. Prevent destruction of the data once it has been safely written to RAM by following either of the procedures below. (1) Once the tuning data has been safely written to the four areas used to emulate flash memory, secure the data in an unused area. (2) Write the tuning data to one of the four areas used to emulate flash memory. In this case, use the FTDAR register to select an area for downloading that does not overlap with the area to be tuned. Figure 25.19 shows an example in which the EB0 area is selected for tuning from among the four areas used for emulation, and the data, once safely written to RAM, is then written to the EB0 area in the user MAT. Rev. 5.00 Feb. 24, 2010 Page 767 of 950 REJ09B0177-0500 25. ROM (SH7059) H'000000 H'001000 H'002000 EB0 EB1 EB2 H'003000 EB3 H'004000 EB4 H'005000 H'006000 H'007000 (1) Cancel the emulation mode. (2) Transfer the user programming/erasing procedure program. (3) Download the on-chip programming/ erasing program to the destination set by FTDAR without overlapping the tuned data area. (4) Execute programming after erasing. EB5 EB6 <On-chip RAM> EB7 Tuned data area H'008000 H'FFFE8000 H'FFFE8FFF FTDAR setting Download area Flash memory (user MAT) H'FFFEBFFF EB8 to EB15 Programming/erasing procedure program area H'FFFFBFFF H'17FFFF Figure 25.19 Programming of Tuned Data 1. After the data to be programmed has fixed values, clear the RAMS bit to 0 to cancel the overlap of RAM. Emulation mode is canceled and emulation protection is also cleared. 2. Transfer the user programming/erasing procedure program to RAM. 3. Run the programming/erasing procedure program in RAM and download the on-chip programming/erasing program. Specify the download start address with FTDAR so that the tuned data area does not overlap with the download area. 4. When the EB0 area of the user MAT has not been erased, erasing must be performed before programming. Set the parameters FMPAR and FMPDR so that the tuned data is designated, and execute programming. Note: Setting the RAMS bit to 1 puts all the blocks in flash memory in the programming/erasing-protected state regardless of the values of the RAM0 bit (emulation protection). Clear the RAMS bit to 0 before actual programming or erasure. Though RAM emulation can also be carried out with the user boot MAT selected, the user boot MAT can be erased or programmed only in boot mode or programmer mode. Rev. 5.00 Feb. 24, 2010 Page 768 of 950 REJ09B0177-0500 25. ROM (SH7059) 25.8 Usage Notes 25.8.1 Switching between User MAT and User Boot MAT It is possible to switch between the user MAT and user boot MAT. However, the following procedure is required because these MATs are allocated to address 0. (Switching to the user boot MAT disables programming and erasing. Programming of the user boot MAT must take place in boot mode or programmer mode.) (1) MAT switching by FMATS should always be executed from the on-chip RAM. The SH microcomputer prefetches execution instructions. Therefore, a switchover during program execution in the user MAT causes an instruction code in the user MAT to be prefetched or an instruction in the newly selected user boot MAT to be prefetched, thus resulting in unstable operation. (2) To ensure that the MAT that has been switched to is accessible, execute eight NOP instructions in on-chip RAM immediately after writing to FMATS of on-chip RAM (this prevents access to the flash memory during MAT switching). (3) If an interrupt occurs during switching, there is no guarantee of which memory MAT is being accessed. Always mask the maskable interrupts before switching MATs. In addition, configuring the system so that NMI interrupts do not occur during MAT switching is recommended. (4) After the MATs have been switched, take care because the interrupt vector table will also have been switched. If the same interrupt processings are to be executed before and after MAT switching or interrupt requests cannot be disabled, transfer the interrupt processing routine to on-chip RAM, and use the VBR setting to place the interrupt vector table in on chip RAM. In this case, make sure the VBR setting change does not conflict with the interrupt occurrence. (5) Memory sizes of the user MAT and user boot MAT are different. When accessing the user boot MAT, do not access addresses exceeding the 12-Kbyte memory space. If access goes beyond the 12-Kbyte space, the values read are undefined. <User MAT> <On-chip RAM> <User boot MAT> Procedure for switching to the user boot MAT Procedure for switching to the user MAT Procedure for switching to the user boot MAT (1) Mask interrupts. (2) Write H'AA to FMATS. (3) Execute eight NOP instructions before accessing the user boot MAT. Procedure for switching to the user MAT (1) Mask interrupts. (2) Write a value other than H'AA to FMATS. (3) Execute eight NOP instructions before accessing the user MAT. Figure 25.20 Switching between User MAT and User Boot MAT Rev. 5.00 Feb. 24, 2010 Page 769 of 950 REJ09B0177-0500 25. ROM (SH7059) 25.8.2 Interrupts during Programming/Erasing (1) Download of On-Chip Program (1.1) VBR setting change Before downloading the on-chip program, VBR must be set to H'00000000 (initial value). If VBR is set to a value other than the initial value, the interrupt vector table is placed in the user MAT (FMATS is not H'AA) or the user boot MAT (FMATS is H'AA) on initialization of VBR. When VBR setting change conflicts with interrupt occurrence, whether the vector table before or after VBR is changed is referenced may cause an error. Therefore, for cases where VBR setting change may conflict with interrupt occurrence, prepare a vector table to be referenced when VBR is H'00000000 at the start of the user MAT or user boot MAT. (1.2) SCO download request and interrupt request Download of the on-chip programming/erasing program that is initiated by setting the SCO bit in FCCS to 1 generates a particular interrupt processing accompanied by MAT switchover. Operation when the SCO download request and interrupt request conflicts is described below. 1. Contention between SCO download request and interrupt request Figure 25.21 shows the timing of contention between execution of the instruction that sets the SCO bit in FCCS to 1 and interrupt acceptance. CPU cycle CPU operation for instruction that sets SCO bit to 1 Interrupt acceptance n n+1 n+2 n+3 n+4 Fetch Decoding Execution Execution Execution (a) (b) (c) (a) When the interrupt is accepted at or before the (n + 1) cycle After the interrupt processing completes, the SCO bit is set to 1 and download is executed. (b) When the interrupt is accepted at the (n + 2) cycle The interrupt conflicts with the SCO download request. For details on operation in this case, see 2. Operation when contention occurs. (c) When the interrupt is accepted at or after the (N + 3) cycle The SCO download request occurs prior to the interrupt request, and download is executed. During download, no other interrupt processing can be handled. If an interrupt is still being requested after download completes, the interrupt processing starts. For details on interrupt requests during download, see 3. Interrupt requests generated during download. Figure 25.21 Timing of Contention between SCO Download Request and Interrupt Request 2. Operation when contention occurs Operation differs according to the type of interrupt with which the SCO download request has conflicted. NMI, UBC, and H-UDI interrupt requests Operation for when these interrupts conflict with the SCO download request is described below. Rev. 5.00 Feb. 24, 2010 Page 770 of 950 REJ09B0177-0500 25. ROM (SH7059) Main processing SCO download processing Contention between SCO and interrupt Interrupt processing, e.g. NMI Figure 25.22 Contention between Interrupts (e.g. NMI) * The NMI, UBC, or H-UDI interrupt processing is started. Processing proceeds up to the point where SR and PC are saved, the vector is fetched, and the start instruction of the interrupt processing routine is fetched. * At this point, the SCO download request with a higher priority occurs. The SCO download processing is started. * After the download processing has ended, the interrupt processing routine (e.g. NMI) that was in the middle of execution resumes from the point of fetching the start instruction of the interrupt processing routine. * The interrupt processing routine is ended, and execution returns to the main processing. IRQ and on-chip peripheral module interrupt requests Operation for when these interrupts conflict with the SCO download request is described below. Main processing SCO download processing Contention between SCO and interrupt Interrupt processing, e.g. IRQ Figure 25.23 Contention between Interrupts (e.g. IRQ) * An IRQ interrupt or interrupt from an on-chip peripheral module is replaced with the SCO download request and download is executed. * If the IRQ or on-chip peripheral module interrupt is still being requested when the download processing has ended, the interrupt processing is executed. If these interrupt requests have been canceled, execution returns to the main processing. * An interrupt request is canceled when the IRQ signal, for which low-level detection is set, has been driven high before download ends. Also refer to the description below (3. Interrupt requests generated during download). Rev. 5.00 Feb. 24, 2010 Page 771 of 950 REJ09B0177-0500 25. ROM (SH7059) 3. Interrupt requests generated during download Even though an interrupt is requested during SCO download, the interrupt processing is not executed until download ends. Note that interrupt requests are basically retained, so that on completion of download, the interrupt processing starts. When more than one type of interrupts are requested, their priorities are judged by the interrupt controller (INTC), and execution starts from the interrupt processing with higher priority. NMI, UBC, and H-UDI interrupt requests When these interrupt requests occur during SCO download, their interrupt sources are retained. IRQ interrupt request Falling-edge detection or low-level detection can be specified for an IRQ interrupt. * Falling-edge detection is selected: When the falling-edge of IRQ is detected during SCO download, the interrupt source is retained. * Low-level detection is selected: When the low-level of IRQ is detected during SCO download, if the IRQ remains low when download ends, the interrupt processing starts. If the IRQ is high when download ends, the interrupt source will be canceled. On-chip peripheral module interrupt request An interrupt from an on-chip peripheral module is requested by input of the specified level. Since the interrupt signal continues to be output unless the interrupt flag is cleared, the interrupt source is retained. (2) Interrupts during programming/erasing Though an interrupt processing can be executed at realtime during programming/erasing of the downloaded on-chip program, the following limitations and notes are applied. 1. When flash memory is being programmed or erased, both the user MAT and user boot MAT cannot be accessed. Prepare the interrupt vector table and interrupt processing routine in on-chip RAM or external memory. Make sure the flash memory being programmed or erased is not accessed by the interrupt processing routine. If flash memory is read, the read values are not guaranteed. If flash memory that is being programmed or erased is accessed, the error protect state is entered, and programming or erasing is aborted. 2. Do not rewrite the program data specified by the FMPDR parameter. If new program data is to provided by the interrupt processing, temporarily save the new program data in another area. After confirming the completion of programming, save the new program data in the area specified by FMPDR or change the setting in FMPDR to indicated the other area in which the new program data was temporarily saved. 3. Make sure the interrupt processing routine does not rewrite the contents of the flash-memory related registers or data in the downloaded on-chip program area. During the interrupt processing, do not simultaneously perform RAM emulation, download of the on-chip program by an SCO request, or programming/erasing. 4. At the beginning of the interrupt processing routine, save the CPU register contents. Before returning from the interrupt processing, write the saved contents in the CPU registers again. 5. When a transition is made to sleep mode in the interrupt processing routine, the error protection state is entered and programming/erasing is aborted. If a transition is made to the reset state, the reset signal should only be released after providing a reset input over a period longer than the normal 100 s to reduce the damage to flash memory. 25.8.3 Other Notes 1. Download time of on-chip program The programming program that includes the initialization routine and the erasing program that includes the initialization routine are each 3 Kbytes or less. Accordingly, when the CPU clock frequency is 80 MHz, the download for each program takes approximately 300 s at maximum. 2. User branch processing intervals The intervals for executing the user branch processing differs in programming and erasing. The processing phase also differs. Table 25.11 lists the minimum and maximum user branch processing intervals when the CPU clock frequency is 80 MHz. Rev. 5.00 Feb. 24, 2010 Page 772 of 950 REJ09B0177-0500 25. ROM (SH7059) Table 25.11 User Branch Processing Intervals Processing Name Maximum Interval Minimum Interval Programming Approximately 1 ms Approximately 19 s Erasing Approximately 5 ms Approximately 19 s However, when operation is done with CPU clock of 80 MHz, maximum and minimum values of the time until initial user branch processing are as shown in table 25.12. Table 25.12 Intervals Until Start of User Branch Processing Processing Name Max. Min. Programming Approximately 500 s Approximately 500 s Erasing Approximately 2300 s Approximately 1000 s 3. Write to flash-memory related registers by AUD or DMAC While an instruction in on-chip RAM is being executed, the AUD or DMAC can write to the SCO bit in FCCS that is used for a download request or FMATS that is used for MAT switching. Make sure that these registers are not accidentally written to, otherwise an on-chip program may be downloaded and damage RAM or a MAT switchover may occur and the CPU get out of control. 4. State in which AUD operation is disabled and interrupts are ignored In the following modes or period, the AUD is in module standby mode and cannot operate. The NMI or maskable interrupt requests are ignored; they are not executed and the interrupt sources are not retained. Boot mode Programmer mode Checking the flash-memory related registers immediately after user boot mode is initiated (Approximately 100 s if operation is done at an internal frequency of 80 MHz after the reset signal is released) 5. Compatibility with programming/erasing program of conventional F-ZTAT SH microcomputer A programming/erasing program for flash memory used in the conventional F-ZTAT SH microcomputer which does not support download of the on-chip program by a SCO transfer request cannot run in this LSI. Be sure to download the on-chip program to execute programming/erasing of flash memory in this LSI. 6. Monitoring runaway by WDT Unlike the conventional F-ZTAT SH microcomputer, no countermeasures are available for a runaway by WDT during programming/erasing by the downloaded on-chip program. Prepare countermeasures (e.g. use of the user branch routine and periodic timer interrupts) for WDT while taking the programming/erasing time into consideration as required. 7. FWE pin state Make sure not to change the state of the FWE pin during the flash memory reprogramming. Make sure not to drive the FWE pin low instantaneously even if the noise occurs. Programming/erasing results are not guaranteed if the FWE state is changed during the flash memory reprogramming. Rev. 5.00 Feb. 24, 2010 Page 773 of 950 REJ09B0177-0500 25. ROM (SH7059) 25.9 Programmer Mode Along with its on-board programming mode, this LSI also has programmer mode as another mode for writing and erasing of programs and data. Programmer mode supports memory-read mode, auto-program mode, auto-erase mode, and statusread mode. Programming/erasing is possible on the user MAT and user boot MAT. A status-polling system is adopted for operation in auto-program mode, auto-erase mode, and status-read mode. In statusread mode, details of the system's internal state are output after execution of automatic programming or automatic erasure. In programmer mode, set the mode pins as shown in table 25.13, and provide a 6-MHz input-clock signal. This enables this LSI to operate at 48 MHz. Table 25.13 Programmer Mode Pin Settings Pin Name Settings Mode pins: MD2, MD1, and MD0 0, 1, 1 FWE High-level input (automatic programming and automatic erasure) RES Power-on reset circuit EXTAL, XTAL, PLLVCC, PLLVSS, PLLCAP Oscillation circuit and PLL circuit VCL Internal stepdown stabilization capacitor 25.9.1 Pin Arrangement of Socket Adapter Attach the socket adapter to the LSI in the way shown in figure 25.25. This allows conversion to 40 pins. Figure 25.24 shows the memory mapping of on-chip ROM, and figure 25.25 shows the arrangement of the socket adapter's pins. Address in MCU mode H'0000,0000 Address in PROM mode Address in MCU mode H'00,0000 H'0000,0000 Address in PROM mode H'0,0000 On-chip ROM space (user boot MAT) 12 Kbytes H'0000,2FFF H'0,2FFF On-chip ROM space (user MAT) 1.5 Mbytes H'17,FFFF H'0017,FFFF Figure 25.24 Mapping of On-Chip Flash Memory Rev. 5.00 Feb. 24, 2010 Page 774 of 950 REJ09B0177-0500 25. ROM (SH7059) SH7059F Pin No. Pin Name Socket Adapter (40-Pin Conversion) HN27C4096HG (40 pins) BP-272 FP-256H B3 7 A0 Pin No. 21 Pin Name A0 D4 8 A1 22 A1 C4 9 A2 23 A2 A3 10 A3 24 A3 B4 12 A4 25 A4 A4 14 A5 26 A5 C5 15 A6 27 A6 B5 16 A7 28 A7 A5 17 A8 29 A8 D6 18 A9 31 A9 B6 19 A10 32 A10 A6 21 A11 33 A11 C7 23 A12 34 A12 B7 A7 24 A13 35 A13 25 A14 36 A14 D8 26 A15 37 A15 C8 27 A16 38 A16 B8 28 A17 39 A17 A8 29 A18 10 A18* D9 31 A19 9 A19* C9 33 A20 8 A20* D15 63 D0 19 I/00 B18 64 D1 18 I/01 A19 65 D2 17 I/02 C18 66 D3 16 I/03 B19 67 D4 15 I/04 B20 68 D5 14 I/05 C17 69 D6 13 I/06 C19 71 D7 12 I/07 P1 218 CE 2 CE K2 230 OE 20 OE L3 226 WE 3 WE FWE D14 56 D5,C6,A10,C11,A12,C12,C13, D13,B14,C15,A16,C16,D16,F17 F18,K19,K20,T20,T19,U19,U16, V15,V9,U6,V5,U4,P3,J3,H4 A9,B13,B15,D7,B12,D11,C14,F19, G3,G17,E20,J4,J20,U20,J9 to 12, K9 to 12,L9 to 12,M1,M9 to 12,P4, T18,U5,U9,V6,V16,W11 C10 B16 11,20,37,39,42,43,46,49,52,55, 57,59,70,75,83,100,101,119, 120,128,139,148,172,187,194, 203,212,237,247 13,22,32,41,44,47,50,54,72,77, 84,85,99,121,126,141,150,163, 174,185,196,205,214,227,239, 249 34 A15 53 RES XTAL A14 51 EXTAL A17 60 PLLVcc B17 61 PLLCAP A18 62 PLLVss B9,Y11,M2 30,161,225 VCL Other Other NC (OPEN) 58 Vcc Vss A21 Power-on reset circuit Oscillator circuit PLL circuit Capacitor 4 FWE 1,40 Vcc 11,30 Vss 5,6,7 NC Legend: : Flash-write enable FWE I/07 to 0 : Data I/O A21 to 0 : Address input : Chip enable CE : Output enable OE : Write enable WE Note: *With using the HN27C4096HG as the base, unused I/O pins are adopted to make up for the shortage of address pins. Figure 25.25 Pin Arrangement of Socket Adapter Rev. 5.00 Feb. 24, 2010 Page 775 of 950 REJ09B0177-0500 25. ROM (SH7059) 25.9.2 Programmer Mode Operation Table 25.14 shows the settings for the operating modes of programmer mode, and table 25.15 lists the commands used in programmer mode. The following sections provide detailed information on each mode. * Memory-read mode Supports reading from the user MAT or user boot MAT in bytes. * Auto-program mode Supports the simultaneous programming of the user MAT and user boot MAT in 128-byte units. Status polling is used to confirm the end of automatic programming. * Auto-erase mode Supports only automatic erasure of the entire user MAT or user boot MAT. Status polling is used to confirm the end of automatic erasure. * Status-read mode Status polling is used with automatic programming and automatic erasure. Normal completion can be detected by reading the signal on the I/O6 pin. In status-read mode, error information is output when an error has occurred. Table 25.14 Settings for Each Operating Mode of Programmer Mode Pin Name Mode FWE CE OE WE I/O7 to I/O0 A20 to A0 Read H or L L L H Data output Ain Output disable H or L L H H Hi-Z X Command write H or L L H L Data input Ain* Chip disable H or L H X X Hi-Z X Notes: 1. The chip-disable mode is not a standby state; internally, it is an operational state. 2. To write commands when making a transition to auto-program or auto-erase mode, input a high-level signal on the FWE pin. * Ain indicates that there is also an address input in auto-program mode. Rev. 5.00 Feb. 24, 2010 Page 776 of 950 REJ09B0177-0500 25. ROM (SH7059) Table 25.15 Commands in Programmer Mode 1st Cycle Numberof Cycles Memory MAT to be Accessed Mode Memory-read mode 1+n User MAT Write User boot MAT Auto-program mode 129 Auto-erase mode 2 Command Status-read mode 2 Address 2nd Cycle Data Mode Address Data X H'00 Read RA Dout Write X H'05 User MAT Write X H'40 Write WA Din User boot MAT Write X H'45 User MAT Write X H'20 Write X H'20 User boot MAT Write X H'25 Common to both MATs Write X H'71 H'25 Write X H'71 Notes 1. In auto-program mode, 129 cycles are required in command writing because of the simultaneous 128-byte write. 2. In memory read mode, the number of cycles varies with the number of address writing cycles (n). 3. In an automatic erasure command, input the same command code for the 1st and 2nd cycles (for erasing of the user boot MAT, input H'25 for the 1st and 2nd cycles). 25.9.3 Memory-Read Mode (1) On completion of automatic programming, automatic erasure, or status read, the LSI enters a command input wait state. So, to read the contents of memory after these operations, issue the command to transit to memory-read mode before reading from the memory. (2) In memory-read mode, the writing of commands is possible in the same way as in command input wait state. (3) After entering memory-read mode, continuous reading is possible. (4) After power has first been supplied, the LSI enters memory-read mode. For the AC characteristics in memory read mode, see section 25.10.2, AC Characteristics and Timing in Programmer Mode. Rev. 5.00 Feb. 24, 2010 Page 777 of 950 REJ09B0177-0500 25. ROM (SH7059) 25.9.4 Auto-Program Mode (1) In auto-program mode, programming is in 128-byte units. That is, 128 bytes of data are transferred in succession. (2) Even in the programming of less than 128 bytes, 128 bytes of data must be transferred. H'FF should be written to those addresses that are unnecessarily written to. (3) Set the lower seven bits of the address to be transferred to low level. Inputting an invalid address will result in a programming error, although processing will proceed to the memory-programming operation. (4) The memory address is transferred in the 2nd cycle. Do not transfer addresses in the 3rd or later cycles. (5) Do not issue commands while programming is in progress. (6) When programming, execute automatic programming once for each 128-byte block of addresses. Programming the block at an address where programming has already been performed is not possible. (7) To confirm the end of automatic programming, check the signal on the I/O6 pin. Confirmation in status-read mode is also possible (status polling of the I/O7 pin is used to check the end status of automatic programming). (8) Status-polling information on the I/O6 and I/O7 pins is retained until the next command is written. As long as no command is written, the information is made readable by enabling CE and OE. For the AC characteristics in auto-program mode, see section 25.10.2, AC Characteristics and Timing in Programmer Mode. 25.9.5 Auto-Erase Mode (1) Auto-erase mode only supports erasing of the entire memory. (2) Do not perform command writing while auto erasing is in progress. (3) To confirm the end of automatic erasure, check the signal on the I/O6 pin. Confirmation in the status-read mode is also possible (status polling of the I/O7 pin is used to check the end status of automatic erasure). (4) Status polling information on the I/O6 and I/O7 pins is retained until the next command writing. As long as no command is written, the information is made readable by enabling CE and OE. For the AC characteristics in auto-erase mode, see section 25.10.2, AC Characteristics and Timing in Programmer Mode. Rev. 5.00 Feb. 24, 2010 Page 778 of 950 REJ09B0177-0500 25. ROM (SH7059) 25.9.6 Status-Read Mode (1) Status-read mode is used to determine the type of an abnormal termination. Use this mode when automatic programming or automatic erasure ends abnormally. (2) The return code is retained until writing of a command that selects a mode other than status-read mode. Table 25.16 lists the return codes of status-read mode. For the AC characteristics in status-read mode, see section 25.10.2, AC Characteristics and Timing in Programmer Mode. Table 25.16 Return Codes of Status-Read Mode Pin Name I/O7 Attribute I/O6 Normal end Command indicator error Initial value 0 Indication 0 I/O5 I/O4 Programming error 0 Normal end: Command Programming 0 error: 1 error: 1 Abnormal Otherwise: 0 Otherwise: 0 end: 1 I/O3 I/O2 I/O1 I/O0 Erasure error -- -- Programming or erase count exceeded Invalid address error 0 0 0 0 -- Count exceeded: 1 Otherwise: 0 Invalid address error: 1 Otherwise: 0 0 Erasure -- error:1 Otherwise: 0 Note: I/O2 and I/O3 are undefined pins. 25.9.7 Status Polling (1) The I/O7 status-polling output is a flag that indicates the operating status in auto-program or auto-erase mode. (2) The I/O6 status-polling output is a flag that indicates normal/abnormal end of auto-program or auto-erase mode. Table 25.17 Truth Table of Status-Polling Output Pin Name In Progress Abnormal End -- Normal End I/O7 0 1 0 1 I/O6 0 0 1 1 I/O0 to I/O5 0 0 0 0 25.9.8 Time Taken in Transition to Programmer Mode Until oscillation has stabilized and while programmer mode is being set up, the LSI is unable to accept commands. After the programmer-mode setup time has elapsed, the LSI enters memory-read mode. For details, see section 25.10.2, AC Characteristics and Timing in Programmer Mode. 25.9.9 Notes on Programming in Programmer Mode (1) When programming addresses which have previously been programmed, apply auto-erasing before auto-programming. (2) When using programmer mode to program a chip that has been programmed/erased in an on-board programming mode, auto-erasing before auto-programming is recommended. (3) Do not take the chip out of the PROM programmer or reset the chip during programming or erasure. Flash memory is susceptible to permanent damage since a high voltage is being applied during the programming/erasing. When the reset signal is accidentally input to the chip, the period in the reset state until the reset signal is released should be longer than the normal 100 s. Rev. 5.00 Feb. 24, 2010 Page 779 of 950 REJ09B0177-0500 25. ROM (SH7059) Notes: 1. The flash memory is initially in the erased state when the device is shipped by Renesas Technology. For other chips for which the history of erasure is unknown, auto-erasing as a check and supplement for the initialization (erase) level is recommended. 2. Automatic programming to a single address block can only be performed once. Additional programming to an address block that has already been programmed is not allowed. 25.10 Further Information 25.10.1 Serial Communication Interface Specification for Boot Mode Initiating boot mode enables the boot program to communicate with the host by using the on-chip SCI. The serial communication interface specifications are shown below. * Status The boot program has three states. (1) Bit-rate-adjustment state In this state, the boot program adjusts the bit rate to communicate with the host. Initiating boot mode enables starting of the boot program and entry to the bit-rate-adjustment state. The program receives the command from the host to adjust the bit rate. After adjusting the bit rate, the program enters the inquiry/selection state. (2) Inquiry/Selection state In this state, the boot program responds to inquiry commands from the host. The device name, clock mode, and bit rate are selected. After selection of these settings, the program is made to enter the programming/erasing state by the command for a transition to the programming/erasing state. The boot program transfers the erasure program to RAM and erases the user MATs and user boot MATs before the transition. (3) Programming/erasing state Programming and erasure by the boot program take place in this state. The boot program is made to transfer the programming/erasing program to RAM by commands from the host. Checksums and blank checks are executed by sending these commands from the host. These boot program states are shown in figure 25.26. Rev. 5.00 Feb. 24, 2010 Page 780 of 950 REJ09B0177-0500 25. ROM (SH7059) Reset Bit-rate-adjustment state Bit rate adjustment Inquiry/Selection state Inquiry/Selection wait Selection Inquiry Selection processing Inquiry processing Transition to programming/ erasing state Programming/Erasing state User MAT/User boot MAT erasing processing Programming/Erasing selection wait Programming Programming processing Erasing Erasing processing Check Check processing Figure 25.26 Boot Program Processing Flow * Bit-rate-adjustment state The bit rate is calculated by measuring the period of transfer of a low-level byte (H'00) from the host. The bit rate can be changed by the command for a new bit rate selection. After the bit rate has been adjusted, the boot program enters the inquiry/selection state. The bit-rate-adjustment sequence is shown in figure 25.27. Rev. 5.00 Feb. 24, 2010 Page 781 of 950 REJ09B0177-0500 25. ROM (SH7059) Host Boot Program H'00 (30 times maximum) Measuring the 1-bit length H'00 (Completion of adjustment) H'55 H'E6 (Response to boot) H'FF (Error) Figure 25.27 Bit-Rate-Adjustment Sequence * Communications protocol After adjustment of the bit rate, the protocol for serial communications between the host and the boot program is as shown below. (1) One-byte commands and one-byte responses These commands and responses are comprised of a single byte. These consists of the inquiries and ACK for successful completion. (2) n-byte commands or n-byte responses These commands and responses are comprised of n bytes of data. These are selections and responses to inquiries. The amount of programming data is not included under this heading because it is determined in another command. (3) Error response The error response is a response to inquiries. It consists of an error response and an error code and which take up two bytes. (4) Programming of 128 bytes The size is not specified in commands. The data size is indicated in response to the programming unit inquiry. (5) Memory read response This response consists of four bytes of data. Rev. 5.00 Feb. 24, 2010 Page 782 of 950 REJ09B0177-0500 25. ROM (SH7059) 1-byte command or 1-byte response n-byte command or n-byte response Command or response Data Data size Checksum Command or response Error response Error code Error response 128-byte programming Address Data (n bytes) Checksum Command Memory read response Data size Data Response Checksum Figure 25.28 Communications Protocol Format Command (one byte): Commands including inquiries, selection, programming, erasing, and checking Response (one byte): Response to an inquiry Size (one or two bytes): The amount of data for transmission excluding the command, amount of data, and checksum Data (n bytes): Detailed data of a command or response Checksum (one byte): The checksum is calculated so that the total of all values from the command byte to the SUM byte becomes H'00. Error Response (one byte): Error response to a command Error Code (one byte): Type of the error Address (four bytes): Address for programming Data (n bytes): Data to be programmed. n is indicated in the response to the programming unit inquiry. Data Size (four bytes): Four-byte response to a memory read * Inquiry/Selection State The boot program returns information from the flash memory in response to the host's inquiry commands and sets the device code, clock mode, and bit rate in response to the host's selection command. Table 25.18 lists the inquiry and selection commands. Rev. 5.00 Feb. 24, 2010 Page 783 of 950 REJ09B0177-0500 25. ROM (SH7059) Table 25.18 Inquiry and Selection Commands Command Command Name Description H'20 Supported Device Inquiry Inquiry regarding device codes and product names of F-ZTAT H'10 Device Selection Selection of device code H'21 Clock Mode Inquiry Inquiry regarding numbers of clock modes and values of each mode H'11 Clock Mode Selection Indication of the selected clock mode H'22 Multiplication Ratio Inquiry Inquiry regarding the number of clock types, the number of multiplication/division ratios, and the multiplication/division ratios H'23 Operating Clock Frequency Inquiry Inquiry regarding the maximum and minimum values of the main clock and peripheral clocks H'24 User Boot MAT Information Inquiry Inquiry regarding the number of user boot MATs and the start and last addresses of each MAT H'25 User MAT Information Inquiry Inquiry regarding the a number of user MATs and the start and last addresses of each MAT H'26 Block for Erasing Information Inquiry Inquiry regarding the number of blocks and the start and last addresses of each block H'27 Programming Unit Inquiry Inquiry regarding the unit of programming data H'3F New Bit Rate Selection Selection of new bit rate H'40 Transition to Programming/Erasing State Erasing of user MAT and user boot MAT, and entry to programming/erasing state H'4F Boot Program Status Inquiry Inquiry into the operation status of the boot program The selection commands, which are device selection (H'10), clock mode selection (H'11), and new bit rate selection (H'3F), should be sent from the host in this order. These commands are certainly required. When two or more selection commands are sent at once, the last command will be valid. All of these commands, except for the boot program status inquiry command (H'4F), will be valid until the boot program receives the programming/erasing transition (H'40). The host can choose the needed commands out of the commands and inquiries listed above. The boot program status inquiry command (H'4F) is valid after the boot program has received the programming/erasing transition command (H'40). (1) Supported device inquiry The boot program will return the device codes of supported devices in response to the supported device inquiry. Command H'20 Command: H'20 (one byte): Inquiry regarding supported devices Response H'30 Size Number of devices Number of characters Device code Product name ... SUM Response: H'30 (one byte): Response to the supported device inquiry Size (one byte): Number of bytes to be transmitted, excluding the command, amount of data, and checksum, that is, the amount of data consists of the product names, the number of devices, characters, and device codes Number of devices (one byte): Number of device types supported by the boot program Number of characters (one byte): Number of characters in the device code and boot program's name Rev. 5.00 Feb. 24, 2010 Page 784 of 950 REJ09B0177-0500 25. ROM (SH7059) Device code (four bytes): Supporting product (ASCII code) Product name (n bytes): Type name of the boot program (ASCII code) SUM (one byte): Checksum The checksum is calculated so that the total number of all values from the command byte to the SUM byte becomes H'00. (2) Device Selection The boot program will set the supported device to the specified device code. The program will return the selected device code in response to the inquiry after this setting has been made. Command H'10 Size Device code SUM Command: H'10 (one byte): Device selection Size (one byte): Number of characters in the device code (fixed at 2) Device code (four bytes): Device code returned in response to the supported device inquiry (ASCII code) SUM (one byte): Checksum Response H'06 Response: H'06, (one byte): Response to the device selection command ACK will be returned when the device code matches. Error response H'90 ERROR Error response: H'90 (one byte): Error response to the device selection command ERROR: (one byte): Error code H'11: Checksum error H'21: Device code mismatch error (3) Clock Mode Inquiry The boot program will return the supported clock modes in response to the clock mode inquiry. Command H'21 Command: H'21 (one byte): Inquiry regarding clock mode Response H'31 Size Number of modes Mode SUM Response: H'31 (one byte): Response to the clock-mode inquiry Size (one byte): Amount of data that represents the number of modes and modes Number of modes (one byte): Number of supported clock modes H'00 indicates no clock mode or the device allows the clock mode to be read. Mode (one byte): Supported clock modes (i.e. H'01 means clock mode 1.) SUM (one byte): Checksum (4) Clock Mode Selection The boot program will set the specified clock mode. The program will return the selected clock-mode information after this setting has been made. The clock-mode selection command should be sent after the device selection command. Command H'11 Size Mode SUM Command: H'11 (one byte): Selection of clock mode Size (one byte): Number of characters that represents the mode (fixed at 1) Mode (one byte): Clock mode returned in reply to the supported clock mode inquiry. SUM (one byte): Checksum Response H'06 Response: H'06 (one byte): Response to the clock-mode selection command ACK will be returned when the clock mode matches. Rev. 5.00 Feb. 24, 2010 Page 785 of 950 REJ09B0177-0500 25. ROM (SH7059) Error response H'91 ERROR Error response: H'91 (one byte): Error response to the clock-mode selection command ERROR (one byte): Error code H'11: Checksum error H'22: Clock mode mismatch error (5) Multiplication Ratio Inquiry The boot program will return the supported multiplication/division ratios. Command H'22 Command: H'22 (one byte): Inquiry regarding multiplication ratio Response H'32 Size Number of clock types Number of multiplication ratios Multiplication ratio ... ... SUM Response: H'32 (one byte): Response to the multiplication ratio inquiry Size (one byte): Amount of data that represents the number of clock types, the number of multiplication ratios, and the multiplication ratios Number of clock types (one byte): Number of supported multiplied clock types (e.g. when there are two multiplied clock types, which are the main operating frequency and the peripheral module operating frequency, the number of types will be H'02) Number of multiplication ratios (one byte): Number of multiplication ratios for each operating frequency (e.g. the number of multiplication ratios to which the main operating frequency can be set and the peripheral module operating frequency can be set) Multiplication ratio (one byte) Multiplication ratio : Value of the multiplication ratio (e.g. when the clock-frequency multiplier is four, the value of multiplication ratio will be H'04) Division ratio: Value of the division ratio, inverted to be a negative number (e.g. when the clock is divided by two, the value of division ratio will be H'FE. H'FE = -2) The number of multiplication ratios returned is the same as the number of multiplication ratios and as many groups of data are returned as there are types. SUM (one byte): Checksum (6) Operating Clock Frequency Inquiry The boot program will return the number of operating clock frequencies, and the maximum and minimum values. Command H'23 Command: H'23, (one byte): Inquiry regarding operating clock frequencies Response H'33 Size Minimum value of operating clock frequency Number of operating clock frequencies Maximum value of operating clock frequency ... SUM Response: H'33 (one byte): Response to operating clock frequency inquiry Size (one byte): Number of bytes that represents the number of types, minimum values, and maximum values of operating clock frequencies. Number of types (one byte): Number of supported operating clock frequency types (e.g. when there are two operating clock frequency types, which are the main and peripheral clocks, the number of types will be H'02) Rev. 5.00 Feb. 24, 2010 Page 786 of 950 REJ09B0177-0500 25. ROM (SH7059) Minimum value of operating clock frequency (two bytes): Minimum value for each multiplied or divided clock frequency. The minimum and maximum values represent the values in MHz, valid to the hundredths place of MHz, and multiplied by 100. (e.g. when the value is 20.00 MHz, it will be multiplied by 100 to be 2000 which is H'07D0) Maximum value of operating clock frequency (two bytes): Maximum value for each multiplied or divided clock frequency. There are as many pairs of minimum and maximum values as there are operating clock frequencies. SUM (one byte): Checksum (7) User Boot MAT Information Inquiry The boot program will return the number of user boot MATs and their addresses. Command H'24 Command: H'24 (one byte): Inquiry regarding user boot MAT information Response H'34 Size Number of areas Start address of area Last address of area ... SUM Response: H'34 (one byte): Response to user boot MAT information inquiry Size (one byte): Amount of data that represents the number of areas, the start address of each area, and the last address of each area Number of areas (one byte): Number of non-consecutive user boot MAT areas When user boot MAT areas are consecutive, the number of areas returned is H'01. Start address of area (four bytes): Start address of the area Last address of area (four bytes): Last address of the area There are as many groups of data representing the start and last addresses as there are areas. SUM (one byte): Checksum (8) User MAT Information Inquiry The boot program will return the number of user MATs and their addresses. Command H'25 Command: H'25 (one byte): Inquiry regarding user MAT information Response H'35 Size Number of areas Start address of area Last address of area ... SUM Response: H'35 (one byte): Response to the user MAT information inquiry Size (one byte): Amount of data that represents the number of areas, the start address of each area, and the last address of each area Number of areas (one byte): Number of non-consecutive user MAT areas When user MAT areas are consecutive, the number of areas returned is H'01. Start address of area (four bytes): Start address of the area -- Last address of area (four bytes): Last address of the area There are as many groups of data representing the start and last addresses as there are areas. -- SUM (one byte): Checksum (9) Erased Block Information Inquiry The boot program will return the number of erased blocks and their addresses. Command H'26 Command: H'26 (one byte): Inquiry regarding erased block information Rev. 5.00 Feb. 24, 2010 Page 787 of 950 REJ09B0177-0500 25. ROM (SH7059) Response H'36 Size Number of blocks Start address of block Last address of block ... SUM Response: H'36 (one byte): Response to the number of erased blocks and addresses Size (two bytes): Amount of data that represents the number of blocks, the start address of each block, and the last address of each block Number of blocks (one byte): Number of erased blocks in flash memory Start address of block (four bytes): Start address of the block Last address of block (four bytes): Last address of the block There are as many groups of data representing the start and last addresses as there are blocks. SUM: Checksum (10) Programming Unit Inquiry The boot program will return the programming unit used to program data. Command H'27 Command: H'27 (one byte): Inquiry regarding programming unit Response H'37 Size Programming unit SUM Response: H'37 (one byte): Response to programming unit inquiry Size (one byte): Number of characters that indicate the programming unit (fixed at 2) Programming unit (two bytes): Unit for programming This is the unit for reception of program data. SUM (one byte): Checksum (11) Inquiry of Two-MAT Simultaneous Programming For an inquiry of two-MAT simultaneous programming, the boot program returns the response whether two-MAT simultaneous programming is possible or not, and the start address. Command H'28 Command: H'28 (one byte): Inquiry of two-MAT simultaneous programming Response H'38 Size Programming method First MAT start address Second MAT start address SUM Response: H'38 (one byte): Response to the inquiry of two-MAT simultaneous programming Size (one byte): Total amount of programming method and MAT start address 5 bytes when programming to one MAT, 9 bytes when programming to two MATs simultaneously Programming method (one byte): H'01 = One-MAT programming H'02 = Two-MAT simultaneous programming First MAT start address (four bytes): First MAT start address Second side MAT start address four bytes): Second MAT start address Data on second MAT start address is available only when two-MAT simultaneous programming is possible. SUM (one byte): Checksum (12) New Bit Rate Selection The boot program will set a new bit rate and return the new bit rate. This selection should be sent after sending the clock-mode selection command. Rev. 5.00 Feb. 24, 2010 Page 788 of 950 REJ09B0177-0500 25. ROM (SH7059) Command H'3F Size Bit rate Number of multiplication ratios Multiplication ratio 1 Multiplication ratio 2 Input frequency SUM Command: H'3F (one byte): Selection of new bit rate Size (one byte): Amount of data that represents the bit rate, input frequency, number of multiplication ratios, and multiplication ratios Bit rate (two bytes): New bit rate One hundredth of the value (e.g. when the value is 19200 bps, the bit rate is 192, which is H'00C0) Input frequency (two bytes): Frequency of the clock input to the boot program This value is valid to the hundredths place and represents the value in MHz multiplied by 100. (e.g. when the value is 28.88 MHz, it will be multiplied by 100 to be 2888 which is H'0B48. Number of multiplication ratios (one byte): Number of multiplication ratios to which the device can be set. Multiplication ratio 1 (one byte): Value of the multiplication or division ratio for the main operating frequency Multiplication ratio: Value of the multiplication ratio (e.g. when the clock frequency is multiplied by four, the multiplication ratio will be H'04.) Division ratio: Value of the division ratio, inverted to be a negative number (e.g. when the clock is divided by two, the value of division ratio will be H'FE. H'FE = -2) Multiplication ratio 2 (one byte): Value of the multiplication or division ratio for the peripheral operating frequency Multiplication ratio: Value of the multiplication ratio (e.g. when the clock frequency is multiplied by four, the multiplication ratio will be H'04.) Division ratio: Value of the division ratio, inverted to be a negative number (e.g. when the clock is divided by two, the value of division ratio will be H'FE. H'FE = -2) SUM (one byte): Checksum Response H'06 Response: H'06 (one byte): Response to selection of a new bit rate When it is possible to set the bit rate, the response will be ACK. Error response H'BF ERROR Error response: H'BF (one byte): Error response to selection of new bit rate ERROR: (one byte): Error code H'11: Checksum error H'24: Bit-rate selection error This bit rate is not available. H'25: Input frequency error This input frequency is not within the range set by the minimum and maximum values. H'26: Multiplication ratio error This ratio does not match an available ratio. H'27: Operating frequency error This operating frequency is not within the range set by the minimum and maximum values. The methods for checking of received data are listed below. * Input frequency The received value of the input frequency is checked to ensure that it is within the range of minimum to maximum frequencies which matches the clock modes of the specified device. When the value is out of this range, an input frequency error is generated. * Multiplication ratio The received value of the multiplication ratio or division ratio is checked to ensure that it matches the clock modes of the specified device. When the value is out of this range, a multiplication error is generated. Rev. 5.00 Feb. 24, 2010 Page 789 of 950 REJ09B0177-0500 25. ROM (SH7059) * Operating frequency error The operating frequency is calculated from the received value of the input frequency and the multiplication or division ratio. The input frequency is input to the LSI and the LSI is actually operated at the operating frequency. The expression is given below. Operating frequency = Input frequency*Multiplication ratio, or Operating frequency = Input frequency/Division ratio The calculated operating frequency should be checked to ensure that it is within the range of minimum to maximum frequencies which are available with the clock modes of the specified device. When it is out of this range, an operating frequency error is generated. * Bit rate From peripheral operating clock () and bit rate (B), the clock select (CKS) value (n) in the serial mode register (SMR) and the bit rate register (BRR) value (N) are obtained. The error between n and N that is calculated by the method below is checked to ensure that it is less than 4%. When it is 4% or more, a bit-rate selection error is generated. Error (%) = {[ x 106 ] -1} x 100 (N+1) x B x 64 x 2(2n-1) When the new bit rate is selectable, the new bit rate will be set in the register after sending ACK in response. The host will send ACK with the new bit rate for confirmation and the boot program will response with that rate. Confirmation H'06 Confirmation: H'06 (one byte): Confirmation of a new bit rate Response H'06 Response: H'06 (one byte): Response to confirmation of a new bit rate The sequence of new bit-rate selection is shown in figure 25.29. Boot program Host Setting a new bit rate Waiting for one-bit period at the specified bit rate H'06 (ACK) Setting a new bit rate Setting a new bit rate H'06 (ACK) with the new bit rate H'06 (ACK) with the new bit rate Figure 25.29 New Bit-Rate Selection Sequence Transition to Programming/Erasing State: To enter the programming/erasing state, the boot program will transfer the erasing program, and erase the user MATs and user boot MATs in that order. On completion of this erasure, ACK will be returned and a transition is made to the programming/erasing state. The host should select the device code, clock mode, and new bit rate with device selection, clock-mode selection, and new bit-rate selection commands, and then send the command for the transition to programming/erasing state. This procedure should be carried out before transferring the programming selection command or program data. Command H'40 Command: H'40 (one byte): Transition to programming/erasing state Rev. 5.00 Feb. 24, 2010 Page 790 of 950 REJ09B0177-0500 25. ROM (SH7059) Response H'06 Response: H'06 (one byte): Response to transition to programming/erasing state The boot program will send ACK when the user MATs and user boot MATs have been erased by the transferred erasing program. Error response H'C0 H'51 Error response: H'C0 (one byte): Error response to transition to programming/erasing state Error code: H'51 (one byte): Erasing error An error occurred and erasure was not completed. Command Error: A command error will occur when a command is undefined, the order of commands is incorrect, or a command is unacceptable. Issuing a clock-mode selection command before a device selection or issuing an inquiry command after the command for transition to the programming/erasing state, are examples. Error response H'80 H'xx Error response: H'80 (one byte): Command error Command: H'xx (one byte): Received command Command Order: The order for commands in the inquiry selection state is shown below. (1) A supported device inquiry (H'20) should be made to inquire about the supported devices. (2) The device should be selected from among those described by the returned information and set with a device selection (H'10) command. (3) A clock-mode inquiry (H'21) should be made to inquire about the supported clock modes. (4) The clock mode should be selected from among those described by the returned information and set with a clock-mode selection (H'11) command. (5) After selection of the device and clock mode, inquiries for other required information should be made, such as the multiplication ratio inquiry (H'22) or operating frequency inquiry (H'23). (6) A new bit rate should be selected with the new bit-rate selection (H'3F) command, according to the returned information on multiplication ratios and operating frequencies. (7) After selection of the device and clock mode, the information of the user boot MAT and user MAT should be made to inquire about the user boot MAT information inquiry (H'24), user MAT information inquiry (H'25), erased block information inquiry (H'26), programming unit inquiry (H'27), and two-MAT simultaneous programming information inquiry (H'28). (8) After making inquiries and selecting a new bit rate, issue the command for transition to the programming/erasing state (H'40). The boot program will then enter the programming/erasing state. Programming/Erasing State: In the programming/erasing state, a programming selection command makes the boot program select the programming method, a 128-byte programming command makes it program the memory with data, and an erasing selection command and block erasing command make it erase the block. Table 25.19 lists the programming/erasing commands. Rev. 5.00 Feb. 24, 2010 Page 791 of 950 REJ09B0177-0500 25. ROM (SH7059) Table 25.19 Programming/Erasing Commands Command Command Name Description H'42 User boot MAT programming selection Transfers the user boot MAT programming program H'43 User MAT programming selection Transfers the user MAT programming program H'50 128-byte programming Programs 128 bytes of data H'48 Erasing selection Transfers the erasing program H'58 Block erasing Erases a block of data H'52 Memory read Reads the contents of memory H'4A User boot MAT checksum Checks the checksum of the user boot MAT H'4B User MAT checksum Checks the checksum of the user MAT H'4C User boot MAT blank check Checks whether the contents of the user boot MAT are blank H'4D User MAT blank check Checks whether the contents of the user MAT are blank H'4F Boot program status inquiry Inquires into the boot program's state Programming: Programming is executed by a programming selection command and a 128-byte programming command. First, the host should send the programming selection command and select the programming method and programming MATs. There are three programming selection commands used according to the area and method for programming. (1) User boot MAT programming selection (2) User MAT programming selection After issuing the programming selection command, the host should send the 128-byte programming command. The 128byte programming command that follows the selection command represents the data programmed according to the method specified by the selection command. When more than 128-byte data is programmed, 128-byte commands should repeatedly be executed. Sending a 128-byte programming command with H'FFFFFFFF as the address will stop the programming. On completion of programming, the boot program will wait for selection of programming or erasing. To continue programming with another method or of another MAT, the procedure must be repeated from the programming selection command. The programming selection command and sequence for the 128-byte programming commands are shown in figure 25.30. Rev. 5.00 Feb. 24, 2010 Page 792 of 950 REJ09B0177-0500 25. ROM (SH7059) Host Boot program Programming selection (H'42, H'43) Transfer of the programming program ACK 128-byte programming (address, data) Repeat Programming ACK 128-byte programming (H'FFFFFFFF) ACK Figure 25.30 Programming Sequence (1) User boot MAT programming selection The boot program will transfer a programming program. The data is programmed to the user boot MATs by the transferred programming program. Command H'42 Command: H'42 (one byte): User boot MAT programming selection Response H'06 Response: H'06 (one byte): Response to user boot MAT programming selection When the programming program has been transferred, the boot program will return ACK. Error response H'C2 ERROR Error response: H'C2 (one byte): Error response to user boot MAT programming selection ERROR: (one byte): Error code H'54: Selection processing error (transfer error occurs and processing is not completed) (2) User MAT programming selection The boot program will transfer a programming program. The data is programmed to the user MATs by the transferred programming program. Command H'43 Command: H'43 (one byte): User MAT programming selection Response H'06 Response: H'06 (one byte): Response to user MAT programming selection When the programming program has been transferred, the boot program will return ACK. Error response H'C3 ERROR Error response: H'C3 (one byte): Error response to user MAT programming selection ERROR: (one byte): Error code H'54: Selection processing error (transfer error occurs and processing is not completed) Rev. 5.00 Feb. 24, 2010 Page 793 of 950 REJ09B0177-0500 25. ROM (SH7059) (3) 128-byte programming The boot program will use the programming program transferred by the programming selection command for programming the user boot MATs or user MATs. When two-user-MAT simultaneous programming command is selected, programming will start after the boot program has received data for both MATs. Command H'50 Programming address Data ... ... SUM Command: H'50 (one byte): 128-byte programming Programming address (four bytes): Start address for programming Multiple of the size specified in response to the programming unit inquiry; a 128-byte boundary (e.g. H'00, H'01, H'00, H'00: H'01000000) Data (n bytes): Data to be programmed The size is specified in response to the programming unit inquiry. SUM (one byte): Checksum Response H'06 Response: H'06 (one byte): Response to 128-byte programming On completion of programming, the boot program will return ACK. In two-MAT programming, when all data for the first MAT has been received, the boot program will return ACK. Error response H'D0 ERROR Error response: H'D0 (one byte): Error response to 128-byte programming ERROR: (one byte): Error code H'11: Checksum error H'2A: Address error (address is not within the specified range) H'53: Programming error (a programming error has occurred and programming cannot be continued) The specified address should match the unit for programming of data. For example, when the programming is in 128-byte units, the lower byte of the address should be H'00 or H'80. When there are less than 128 bytes of data to be programmed, the host should fill the rest with H'FF. In two-user-MAT simultaneous programming, the host should alternately send the data for each MAT address. Sending the 128-byte programming command with the address of H'FFFFFFFF will stop the programming operation. The boot program will interpret this as the end of programming and wait for selection of programming or erasing. When the most recently received data has not been programmed in two-user-MAT simultaneous programming, the most recent data is programmed before programming is stopped. Command H'50 Programming address SUM Command: H'50 (one byte): 128-byte programming Programming address (four bytes): End code is H'FF, H'FF, H'FF, H'FF. SUM (one byte): Checksum Error response H'D0 ERROR Error response: H'D0 (one byte): Error response to 128-byte programming ERROR: (one byte): Error code H'11: Checksum error H'53: Programming error An error has occurred in programming, and programming cannot be continued (in two-user-MAT simultaneous programming, when programming to the last MAT has not been completed.) Rev. 5.00 Feb. 24, 2010 Page 794 of 950 REJ09B0177-0500 25. ROM (SH7059) Erasure: Erasure is performed with the erasing selection and block erasing command. First, erasure is selected by the erasing selection command and the boot program then erases the block specified by the block erasing command. The command should be repeatedly executed if two or more blocks are to be erased. Sending a block erasing command from the host with the block number H'FF will stop erasure. On completion of erasing, the boot program will wait for selection of programming or erasing. The erasing selection command and sequence for erasing data are shown in figure 25.31. Host Boot program Preparation for erasure (H'48) Transfer of erasure program ACK Erasure (Erased block number) Repeat Erasure ACK Erasure (H'FF) ACK Figure 25.31 Erasing Sequence (1) Erasing selection The boot program will transfer the erasing program. User MAT data is erased by the transferred erasing program. Command H'48 Command: H'48 (one byte): Erasing selection Response H'06 Response: H'06 (one byte): Response to erasing selection After the erasing program has been transferred, the boot program will return ACK. Error response H'C8 ERROR Error response: H'C8 (one byte): Error response to erasing selection ERROR: (one byte): Error code H'54: Selection processing error (transfer error occurs and processing is not completed) (2) Block erasing The boot program will erase the contents of the specified block. Command H'58 Size Block number SUM Command: H'58 (one byte): Erasing Size (one byte): Number of characters that represents the erasure block number (fixed at 1) Block number (one byte): Number of the block whose data is to be erased SUM (one byte): Checksum Response H'06 Response: H'06 (one byte): Response to erasing After erasure has been completed, the boot program will return ACK. Rev. 5.00 Feb. 24, 2010 Page 795 of 950 REJ09B0177-0500 25. ROM (SH7059) Error response H'D8 ERROR Error response: H'D8 (one byte): Error response to erasing H'11: Checksum error H'29: Block number error Block number is incorrect. H'51: Erasure error An error has occurred during erasure. On receiving block number H'FF, the boot program will stop erasure and wait for a selection command. Command H'58 Size Block number SUM Command: H'58 (one byte): Erasure Size (one byte): Number of characters that represents the block number (fixed at 1) Block number (one byte): H'FF (stop code for erasure) SUM (one byte): Checksum Response H'06 Response: H'06 (one byte): Response to end of erasure (ACK) When erasure is to be performed again after the block number H'FF has been sent, the procedure should be executed from the erasure selection command. Rev. 5.00 Feb. 24, 2010 Page 796 of 950 REJ09B0177-0500 25. ROM (SH7059) Memory Read: The boot program will return the data in the specified address. Command H'52 Size Area Read start address Read size SUM Command: H'52 (one byte): Memory read Size (one byte): Amount of data that represents the area, read address, and read size (fixed at 9) Area (one byte) H'11: User boot MAT H'01: User MAT An address error occurs when the area setting is incorrect. Read start address (four bytes): Start address to be read from Read size (four bytes): Size of data to be read SUM (one byte): Checksum Response H'52 Read size Data ... SUM Response: H'52 (one byte): Response to memory read Read size (four bytes): Size of data to be read Data (n bytes): Data for the read size from the read address SUM (one byte): Checksum Error response H'D2 ERROR Error response: H'D2 (one byte): Error response to memory read ERROR: (one byte): Error code H'11: Checksum error H'2A: Address error The read address is not in the MAT. H'2B: Size error The read size exceeds the MAT. Or, the read end address calculated from the read start address and read size is out of the MAT range, or the read size is 0. User Boot MAT Checksum: The boot program will add the amount of data in user boot MATs and return the result. The user boot MAT checksum value is calculated as a 16-Kbyte area. The checksum value is the sum of 12 Kbytes of user boot MAT data and 4 Kbytes of H'FF data. Command H'4A Command: H'4A (one byte): Checksum of user boot MATs Response H'5A Size MAT checksum SUM Response: H'5A (one byte): Response to checksum of user boot MATs Size (one byte): Number of characters in checksum data (fixed at 4) MAT checksum (4 bytes): The user boot MAT checksum value calculated by adding byte units, with a further 4 Kbytes of H'FF data added SUM (one byte): Checksum (for transmit data) User MAT Checksum: The boot program will add the amount of data in user MATs and return the result. The user MAT checksum value is calculated as a 2-Mbyte area. The checksum value is the sum of 1.5 Mbytes of user MAT data and 512 Kbytes of H'FF data. Command H'4B Command: H'4B (one byte): Checksum of user MATs Rev. 5.00 Feb. 24, 2010 Page 797 of 950 REJ09B0177-0500 25. ROM (SH7059) Response H'5B Size MAT checksum SUM Response: H'5B (one byte): Response to checksum of user MATs Size (one byte): Number of characters in checksum data (fixed at 4) MAT checksum (4 bytes): The user MAT checksum value calculated by adding byte units, with a further 512 Kbytes of H'FF data added SUM (one byte): Checksum (for transmit data) User Boot MAT Blank Check: The boot program will check whether or not all user boot MATs are blank and return the result. Command H'4C Command: H'4C (one byte): Blank check of user boot MATs Response H'06 Response: H'06 (one byte): Response to blank check of user boot MATs If all user boot MATs are blank (H'FF), the boot program will return ACK. Error response H'CC H'52 Error response: H'CC (one byte): Error response to blank check of user boot MATs Error code: H'52 (one byte): Erasure has not been completed User MAT Blank Check: The boot program will check whether or not all user MATs are blank and return the result. Command H'4D Command: H'4D (one byte): Blank check of user MATs Response H'06 Response: H'06 (one byte): Response to blank check of user MATs If all user MATs are blank (H'FF), the boot program will return ACK. Error response H'CD H'52 Error response: H'CD (one byte): Error response to blank check of user MATs Error code: H'52 (one byte): Erasure has not been completed. Boot Program Status Inquiry: The boot program will return indications of its present state and error condition. This inquiry can be made in the inquiry/selection state or the programming/erasing state. Command H'4F Command: H'4F (one byte): Inquiry regarding boot program status Response H'5F Size STATUS ERROR SUM Response: H'5F (one byte): Response to inquiry regarding boot program status Size (one byte): Number of characters in data (fixed at 2) STATUS (one byte): Standard boot program status For details, see table 25.20. ERROR (one byte): Error state ERROR = 0 indicates normal operation. ERROR = 1 indicates error has occurred For details, see table 25.21. SUM (one byte): Checksum Rev. 5.00 Feb. 24, 2010 Page 798 of 950 REJ09B0177-0500 25. ROM (SH7059) Table 25.20 Status Code Code Description H'01 Device Selection Wait H'02 Clock Mode Selection Wait H'03 Bit Rate Selection Wait H'0F Programming/Erasing State Transition Wait (bit rate selection is completed) H'31 Programming State for Erasing User MAT and User Boot MAT H'3F Programming/Erasing Selection Wait (Erasure is completed) H'4F Programming Data Receive Wait H'5F Erasure Block Specification Wait (erasure is completed) Table 25.21 Error Code Code Description H'00 No Error H'11 Checksum Error H'21 Device Code Mismatch Error H'22 Clock Mode Mismatch Error H'24 Bit Rate Selection Error H'25 Input Frequency Error H'26 Multiplication Ratio Error H'27 Operating Frequency Error H'29 Block Number Error H'2A Address Error H'2B Data Length Error H'51 Erasure Error H'52 Erasure Incompletion Error H'53 Programming Error H'54 Selection Error H'80 Command Error H'FF Bit-Rate-Adjustment Confirmation Error Rev. 5.00 Feb. 24, 2010 Page 799 of 950 REJ09B0177-0500 25. ROM (SH7059) 25.10.2 AC Characteristics and Timing in Programmer Mode Table 25.22 AC Characteristics in Memory Read Mode Condition: VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C Code Symbol Min Max Unit Command write cycle tnxtc 20 s CE hold time tceh 0 ns CE setup time tces 0 ns Data hold time tdh 50 ns Data setup time tds 50 ns Programming pulse width twep 70 ns WE rise time tr 30 ns WE fall time tf 30 ns Command write Note Memory read mode Address stable A21-A0 tces tceh tnxtc CE OE twep tf tr WE tds tdh I/O7-I/O0 Note : Data is latched at the rising edge of WE. Figure 25.32 Memory Read Timing after Command Write Table 25.23 AC Characteristics in Transition from Memory Read Mode to Others Condition: VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C Code Symbol Min Command write cycle tnxtc 20 s CE hold time tceh 0 ns CE setup time tces 0 ns Data hold time tdh 50 ns Data setup time tds 50 ns Programming pulse width twep 70 WE rise time tr 30 ns WE fall time tf 30 ns Rev. 5.00 Feb. 24, 2010 Page 800 of 950 REJ09B0177-0500 Max Unit ns Note 25. ROM (SH7059) Command write in another mode Memory read mode A21-A0 Address stable tnxtc tces tceh CE OE twep tf tr WE tds tdh I/O7-I/O0 Note : WE and OE should not be enabled simultaneously. Figure 25.33 Timing at Transition from Memory Read Mode to Other Modes Table 25.24 AC Characteristics in Memory Read Mode Condition: VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C Code Symbol Access time Max Unit tacc 20 s CE output delay time tce 150 ns OE output delay time toe 150 ns Output disable delay time tdf 100 ns Data output hold time toh 5 CE VIL OE VIL VIH Note ns Address stable A21-A0 WE Min Address stable tacc tacc toh toh I/O7-I/O0 Figure 25.34 CE/OE Enable State Read Rev. 5.00 Feb. 24, 2010 Page 801 of 950 REJ09B0177-0500 25. ROM (SH7059) Address stable A21-A0 Address stable tce tce CE WE toe toe OE tacc tacc VIH toh toh tdf tdf I/O7-I/O0 Figure 25.35 CE/OE Clock Read Table 25.25 AC Characteristics in Auto-Program Mode Condition: VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C Code Symbol Min Command write cycle tnxtc 20 s CE hold time tceh 0 ns CE setup time tces 0 ns Data hold time tdh 50 ns Data setup time tds 50 ns Programming pulse width twep 70 ns Status polling start time twsts 1 Status polling access time tspa Address setup time tas 0 ns Address hold time tah 60 ns Memory programming time twrite -- Programming setup time tpns 100 Programming end setup time tpnh 100 WE rise time tr 30 ns WE fall time tf 30 ns Rev. 5.00 Feb. 24, 2010 Page 802 of 950 REJ09B0177-0500 Max Unit Note ms 150 tP ns ms ns ns tP: Refer to section 29.5, Flash Memory Characteristics 25. ROM (SH7059) tpnh FWE Address stable A21-A0 tpns tces tnxtc tceh tnxtc CE OE tf twep tas tr WE tds tdh tah twsts Data transfer 1 byte to 128 bytes tspa twrite I/O7 Programming end identification signal I/O6 Programming normal end confirmation signal I/O5-I/O0 H'00 H'40 or H'45 1st-byte Din 128th-byte Din Figure 25.36 Timing in Auto-Program Mode Rev. 5.00 Feb. 24, 2010 Page 803 of 950 REJ09B0177-0500 25. ROM (SH7059) Table 25.26 AC Characteristics in Auto-Erase Mode Condition: VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C Code Symbol Min Max Unit Command write cycle tnxtc 20 s CE hold time tceh 0 ns CE setup time tces 0 ns Data hold time tdh 50 ns Data setup time tds 50 ns Programming pulse width twep 70 ns Status polling start time tests 1 ms Status polling access time tspa Memory erase time terase -- Erase setup time tens 100 ns Erase end setup time tenh 100 ns WE rise time tr 30 ns WE fall time tf 30 ns 150 ns 6 x tE s tE: Refer to section 29.5, Flash Memory Characteristics tenh FWE A21-A0 tens tces tnxtc tceh tnxtc CE OE tf twep tests tr tspa WE tds terase tdh I/O7 Erase end identification signal I/O6 Erase normal end confirmation signal I/O5-I/O0 H'00 H'20 or H'25 H'20 or H'25 Figure 25.37 Timing in Auto-Erase Mode Rev. 5.00 Feb. 24, 2010 Page 804 of 950 REJ09B0177-0500 Note 25. ROM (SH7059) Table 25.27 AC Characteristics Status Read Mode Condition: VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C Code Symbol Min Max Unit Command write cycle tnxtc 20 s CE hold time tceh 0 ns CE setup time tces 0 ns Data hold time tdh 50 ns Data setup time tds 50 ns Programming pulse width twep 70 ns OE output delay time toe 150 ns Disable delay time tdf 100 ns CE output delay time tce 150 ns WE rise time tr 30 ns WE fall time tf 30 ns Note A21-A0 tces tnxtc tceh tces tnxtc tceh tnxtc CE tce OE tf twep tr tf twep toe tr WE tds tdh tds H'71 I/O7-I/O0 tdf tdh H'71 Note: I/O3 and I/O2 are undefined. Figure 25.38 Timing in Status Read Mode Table 25.28 Stipulated Transition Times to Command Wait State Condition: VCC = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C 5C Code Symbol Min Max Unit Standby release (oscillation stabilization time) tosc1 30 ms Programmer mode setup time tbmv 10 ms VCC hold time tdwn 0 ms Note Rev. 5.00 Feb. 24, 2010 Page 805 of 950 REJ09B0177-0500 25. ROM (SH7059) tosc1 tbmv Memory read mode Command wait state Auto-program mode Auto-erase mode Command wait state Normal/abnormal end identification tdwn VCC FWE Note: Set the FWE input pin to low level, except in the auto-program and auto-erase modes. Figure 25.39 Oscillation Stabilization Time, Programmer Mode Setup Time, and Power-Down Sequence 25.10.3 Storable Area for Procedure Program and Programming Data In the descriptions in the previous section, storable areas for the programming/erasing procedure programs and program data are assumed to be in on-chip RAM. However, the procedure programs and data can be stored in and executed from other areas (e.g. external address space) as long as the following conditions are satisfied. (1) The on-chip programming/erasing program is downloaded from the address set by FTDAR in on-chip RAM, therefore, this area is not available for use. (2) The on-chip programming/erasing program will use 128 bytes or more as a stack. Make sure this area is reserved. (3) Since download by setting the SCO bit to 1 will cause the MATs to be switched, it should be executed in on-chip RAM. (4) The flash memory is accessible until the start of programming or erasing, that is, until the result of downloading has been judged. When in a mode in which the external address space is not accessible, such as single-chip mode, the required procedure programs, interrupt vector table, interrupt processing routine, and user branch program should be transferred to on-chip RAM before programming/erasing of the flash memory starts. (5) The flash memory is not accessible during programming/erasing operations. Therefore, the programming/erasing program must be downloaded to on-chip RAM in advance. Areas for executing each procedure program for initiating programming/erasing, the user program at the user branch destination for programming/erasing, the interrupt vector table, and the interrupt processing routine must be located in on-chip memory other than flash memory or the external address space. (6) After programming/erasing, access to flash memory is inhibited until FKEY is cleared. A reset state (RES = 0) for more than at least 100 s must be taken when the LSI mode is changed to reset on completion of a programming/erasing operation. Transitions to the reset state or hardware standby mode during programming/erasing are inhibited. When the reset signal is accidentally input to the LSI, a longer period in the reset state than usual (100 s) is needed before the reset signal is released. (7) Switching of the MATs by FMATS is needed for programming/erasing of the user MAT in user boot mode. The program which switches the MATs should be executed from the on-chip RAM. For details, see section 25.8.1, Switching between User MAT and User Boot MAT. Please make sure you know which MAT is selected when switching the MATs. (8) When the program data storage area indicated by the FMPDR parameter in the programming processing is within the flash memory area, an error will occur. Therefore, temporarily transfer the program data to on-chip RAM to change the address set in FMPDR to an address other than flash memory. Based on these conditions, tables 25.29 and 25.30 show the areas in which the program data can be stored and executed according to the operation type and mode. Rev. 5.00 Feb. 24, 2010 Page 806 of 950 REJ09B0177-0500 25. ROM (SH7059) Table 25.29 Executable MAT Initiated Mode Operation User Program Mode User Boot Mode* Programming Table 25.30 (1) Table 25.30 (3) Erasing Table 25.30 (2) Table 25.30 (4) Note: * Programming/Erasing is possible to user MATs. Table 25.30 (1) Usable Area for Programming in User Program Mode Storable /Executable Area Programming procedure Note: * Selected MAT Item On-Chip RAM User MAT External Space (Expanded Mode with MD0 = 0) Program data storage area O X* O -- Selecting on-chip program to be downloaded O O O O Writing H'A5 to key register O O O O Writing 1 to SCO in FCCS (download) O X X Key register clearing O O O O Judging download result O O O O Download error processing O O O O Setting initialization parameters O O O O Initialization O X X O Judging initialization result O O O O User MAT Embedded Program Storage MAT -- O Initialization error processing O O O O Interrupt processing routine O X O O Writing H'5A to key register O O O O Setting programming parameters O X O O Programming O X X O Judging programming result O X O O Programming error processing O X O O Key register clearing O X O O If the data has been transferred to on-chip RAM in advance, this area can be used. Rev. 5.00 Feb. 24, 2010 Page 807 of 950 REJ09B0177-0500 25. ROM (SH7059) Table 25.30 (2) Usable Area for Erasure in User Program Mode Storable /Executable Area On-Chip RAM User MAT External Space (Expanded Mode with MD0 = 0) Selecting on-chip program to be downloaded O O O O Writing H'A5 to key register O O O O Writing 1 to SCO in FCCS (download) O X X Item Erasing procedure Selected MAT User MAT O Key register clearing O O O O Judging download result O O O O Download error processing O O O O Setting initialization parameters O O O O Initialization O X X O Judging initialization result O O O O Initialization error processing O O O O Interrupt processing routine O X O O Writing H'5A to key register O O O O Setting erasure parameters O X O O Erasure O X X O Judging erasure result O X O O Erasing error processing O X O O Key register clearing O X O O Rev. 5.00 Feb. 24, 2010 Page 808 of 950 REJ09B0177-0500 Embedded Program Storage MAT 25. ROM (SH7059) Table 25.30 (3) Usable Area for Programming in User Boot Mode Storable/Executable Area On-Chip RAM User Boot MAT External Space (Expanded Mode with MD0 = 0) Program data storage area O X*1 O Selecting on-chip program to be downloaded O O O O Writing H'A5 to key register O O O O Writing 1 to SCO in FCCS (download) O X X Key register clearing O O O O Judging download result O O O O Download error processing O O O O Setting initialization parameters O O O O Initialization O X X O Judging initialization result O O O O Initialization error processing O O O O Interrupt processing routine O X O O Switching MATs by FMATS O X X O Writing H'5A to Key Register O X O O Setting programming parameters O X O O Programming O X X O Judging programming result O X O O Programming error processing O X*2 O O Key register clearing O X O O Switching MATs by FMATS O X X Item Programming procedure Selected MAT User MAT User Boot Mat Embedded Program Storage Area -- -- -- O O Notes 1. If the data has been transferred to on-chip RAM in advance, this area can be used. 2. If the MATs have been switched by FMATS in on-chip RAM, this MAT can be used. Rev. 5.00 Feb. 24, 2010 Page 809 of 950 REJ09B0177-0500 25. ROM (SH7059) Table 25.30 (4) Usable Area for Erasure in User Boot Mode Storable/Executable Area On-Chip RAM User Boot MAT External Space (Expanded Mode with MD0 = 0) Selecting on-chip program to be downloaded O O O O Writing H'A5 to key register O O O O Writing 1 to SCO in FCCS (download) O X X Key register clearing O O O O Judging download result O O O O Download error processing O O O O Setting initialization parameters O O O O Item Erasing procedure Note: * Selected MAT User MAT User Boot Mat O Initialization O X X O Judging initialization result O O O O Initialization error processing O O O O Interrupt processing routine O X O O Switching MATs by FMATS O X X O Writing H'5A to key register O X O O Setting erasure parameters O X O O Erasure O X X O Judging erasure result O X O O Erasing error processing O X* O O O Key register clearing O X O Switching MATs by FMATS O X X O If the MATs have been switched by FMATS in on-chip RAM, this MAT can be used. Rev. 5.00 Feb. 24, 2010 Page 810 of 950 REJ09B0177-0500 Embedded Program Storage Area 26. RAM Section 26 RAM 26.1 Overview The SH7058S and SH7059 have 48 and 80 Kbytes of on-chip RAM, respectively. The on-chip RAM is linked to the CPU, direct memory access controller (DMAC), and advanced user debugger (AUD) with a 32-bit data bus (figure 26.1). The CPU, DMAC, and AUD can access data in the on-chip RAM in 8, 16, or 32 bit widths. On-chip RAM data can always be accessed in one cycle for a read and two states for a write, making the RAM ideal for use as a program area, stack area, or data area, which require high-speed access. The contents of the on-chip RAM are held in both the sleep and software standby modes. When the RAME bit (see below) is cleared to 0, the on-chip RAM contents are also held in hardware standby mode. The on-chip RAM is allocated to addresses H'FFFF0000 to H'FFFFBFFF in the SH7058S and H'FFFE8000 to H'FFFFBFFF in the SH7059. SH7058S Internal data bus (32 bits) 8 bits 8 bits 8 bits 8 bits H'FFFF0000 H'FFFF0001 H'FFFF0002 H'FFFF0003 H'FFFF0004 H'FFFF0005 H'FFFF0006 H'FFFF0007 On-chip RAM H'FFFFBFFC H'FFFFBFFD H'FFFFBFFE H'FFFFBFFF SH7059 Internal data bus (32 bits) 8 bits 8 bits 8 bits 8 bits H'FFFE8000 H'FFFE8001 H'FFFE8002 H'FFFE8003 H'FFFE8004 H'FFFE8005 H'FFFE8006 H'FFFE8007 On-chip RAM H'FFFFBFFC H'FFFFBFFD H'FFFFBFFE H'FFFFBFFF Figure 26.1 Block Diagram of RAM Rev. 5.00 Feb. 24, 2010 Page 811 of 950 REJ09B0177-0500 26. RAM 26.2 Operation The on-chip RAM is controlled by means of the system control register (SYSCR). When the RAME bit in SYSCR is set to 1, the on-chip RAM is enabled. Addresses H'FFFF0000 to H'FFFFBFFF in the SH7058S or H'FFFE8000 to H'FFFFBFFF in the SH7059 then provide access to the on-chip RAM. When the RAME bit in SYSCR is cleared to 0, the on-chip RAM is not accessed. A read will return an undefined value, and a write is invalid. If a transition is made to hardware standby mode after the RAME bit in SYSCR is cleared to 0, the contents of the on-chip RAM are held. For details of SYSCR, see section 27.2.2, System Control Register1 (SYSCR1). Rev. 5.00 Feb. 24, 2010 Page 812 of 950 REJ09B0177-0500 27. Power-Down State Section 27 Power-Down State 27.1 Overview Three modes are provided as power-save modes, namely, the hardware standby, software standby and sleep modes. Also, a module standby function is available to stop some modules. These standby modes can be selected depending on applications to reduce the power consumption of this LSI. 27.1.1 Power-Down States The power-down state is effected by the following modes: 1. Hardware standby mode A transition to hardware standby mode is made according to the input level of the RES and HSTBY pins. In hardware standby mode, all this LSI functions are halted and the power supply to most circuits of this LSI is stopped. This state is exited by means of a power-on reset. 2. Software standby mode A transition to software standby mode is made by means of software (a CPU instruction). In software standby mode, all this LSI functions are halted and the power supply to most circuits of this LSI is stopped. This state is canceled by a power-on reset or a rising edge of the NMI signal. 3. Sleep mode A transition to sleep mode is made by means of a CPU instruction. In software standby mode, basically only the CPU is halted, and all on-chip peripheral modules operate. This state is exited by means of a power-on reset, a manual reset, interrupt, or DMA address error. 4. Module standby mode Operation of the on-chip peripheral modules* which can be placed in a standby mode can be stopped by stopping the clock supply. Clock supply to the individual modules can be controlled by setting bits in system control register 2 (SYSCR2). Note: * AUD, H-UDI, FPU, and UBC Rev. 5.00 Feb. 24, 2010 Page 813 of 950 REJ09B0177-0500 27. Power-Down State Table 27.1 shows the transition conditions for entering the modes from the program execution state, as well as the CPU and peripheral module status in each mode and the procedures for canceling each mode. Table 27.1 Power-Down State Conditions State Clock CPU On-Chip Peripheral Modules RAM Pins Held*1 Initialized Held High * 2 impedance* Mode Entering Procedure Hardware standby Low-level input at HSTBY Halted pin (Power supply stopped) Halted Halted (Power supply stopped) (Power supply stopped) Software standby Execute SLEEP instruction Halted with SSBY (Power bit set to 1 in SBYCR supply Halted Halted*1 (Power supply stopped) (Power supply stopped) stopped) Sleep Execute SLEEP instruction Runs with SSBY bit cleared to 0 in SBYCR Halted and Runs held in registers Runs Runs Canceling Procedure High-level input at HSTBY pin, executing poweron reset Rising edge of NMI * Power-on reset * Interrupt * DMA address error * Power-on reset * Manual reset Legend: SBYCR: Standby control register SSBY: Software standby bit Notes: 1. Clear the RAME bit in SYSCR1 to 0 in advance when changing the state from the program execution state in hardware standby mode. 2. When leaving software standby mode, the inside of this LSI is initiated in the reset state. The pin function controller and I/O port-related registers are initialized. For details on the pin state, see Appendix B, Pin States. 27.1.2 Pin Configuration Pins related to power-down modes are shown in table 27.2. Table 27.2 Pin Configuration Pin Name Abbreviation I/O Function Hardware standby input pin HSTBY Input Input level determines transition to hardware standby mode Power-on reset input pin RES Input Power-on reset signal input pin NMI input pin NMI Input Input for NMI interrupt and for canceling software standby mode Rev. 5.00 Feb. 24, 2010 Page 814 of 950 REJ09B0177-0500 27. Power-Down State 27.1.3 Related Registers Table 27.3 shows the registers used for power-down state control. Table 27.3 Related Registers Address Name Abbreviation R/W Initial Value Standby control register SBYCR R/W H'1F H'FFFFEC14 8 System control register 1 SYSCR1 R/W H'01 H'FFFFF708 8 System control register 2 SYSCR2 R/W H'01 Write Access Size Read H'FFFFF70A*1 H'FFFFF70B*2 8, 16 Notes: 1. Write data in words. Data cannot be written in bytes or longwords. 2. Read data in bytes. Values cannot be read correctly if data is read in words or longwords. 27.2 Register Descriptions 27.2.1 Standby Control Register (SBYCR) The standby control register (SBYCR) is an 8-bit readable/writable register that sets the transition to standby mode. SBYCR is initialized to H'1F by a power-on reset, and set to H'3F in software standby mode. Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 SSBY -- SSBYF -- -- -- -- -- 0 0 0 1 1 1 1 1 R/W R R R R R R R * Bit 7--Software Standby (SSBY): Specifies transition to software standby mode. The SSBY bit cannot be set to 1 while the watchdog timer is running (when the timer enable bit (TME) in the WDT timer control/status register (TCSR) is set to 1). To enter software standby mode, always halt the WDT by clearing the TME bit to 0, then set the SSBY bit. Bit 7: SSBY Description 0 Executing SLEEP instruction puts this LSI into sleep mode 1 Executing SLEEP instruction puts this LSI into standby mode (Initial value) * Bit 6-- Bit 6: Reserved This bit is always read as 0. The write value should always be 0. Rev. 5.00 Feb. 24, 2010 Page 815 of 950 REJ09B0177-0500 27. Power-Down State * Bit 5-- Software Standby Flag (SSBYF) This bit is set to 1 by a transition to software standby mode. It is cleared to 0 by a transition to hardware standby mode or a power-on reset by the RES pin. When software standby mode is cancelled by a rising edge of the NMI signal, this bit is not cleared to 0. This is a read-only bit and cannot be modified. Bit 5: SSBYF Description 0 Indicates that software standby mode has not been entered or it has been initialized by a power-on reset after a transition to software standby mode. (Initial value) 1 After a transition to software standby mode, the bit has not been initialized by a power-on reset. * Bits 4 to 0--Reserved: These bits are always read as 1. The write value should always be 1. 27.2.2 System Control Register 1 (SYSCR1) Bit: 7 6 5 4 3 2 1 0 -- -- -- -- -- -- AUDSRST RAME Initial value: 0 0 0 0 0 0 0 1 R/W: R R R R R R R/W R/W System control register 1 (SYSCR1) is an 8-bit readable/writable register that performs AUD software reset control and enables or disables access to the on-chip RAM. SYSCR1 is initialized to H'01 by a power-on reset (at the rising edge). * Bits 7 to 2--Reserved: These bits are always read as 0. The write value should always be 0. * Bit1-- AUD Software Reset (AUDSRST): This bit controls AUD reset using software. Setting AUDSRST bit to 1 places the AUD module in the power-on reset state. Bit 1: AUDSRST Description 0 AUD reset state cleared 1 AUD reset state entered (Initial value) * Bit 0--RAME Enable (RAME): Selects enabling or disabling of the on-chip RAM. When RAME is set to 1, on-chip RAM is enabled. When RAME is cleared to 0, on-chip RAM cannot be accessed. In this case, a read or instruction fetch from on-chip RAM will return an undefined value, and a write to on-chip RAM will be ignored. The initial value of RAME is 1. When on-chip RAM is disabled by clearing RAME to 0, do not place an instruction that attempts to access on-chip RAM immediately after the SYSCR1 write instruction, as normal access cannot be guaranteed in this case. When on-chip RAM is enabled by setting RAME to 1, place an SYSCR1 read instruction immediately after the SYSCR1 write instruction. Normal access cannot be guaranteed if an on-chip RAM access instruction is placed immediately after the SYSCR1 write instruction. Bit 0: RAME Description 0 On-chip RAM disabled 1 On-chip RAM enabled Rev. 5.00 Feb. 24, 2010 Page 816 of 950 REJ09B0177-0500 (Initial value) 27. Power-Down State 27.2.3 System Control Register 2 (SYSCR2) Bit: 7 6 5 4 3 2 1 0 -- -- -- -- Initial value: 0 0 0 0 0 0 0 1 R/W: R R R R R/W R/W R/W R/W MSTOP3 MSTOP2 MSTOP1 MSTOP0 System control register 2 (SYSCR2) is an 8-bit readable/writable register that controls the standby state of the AUD, HUDI, FPU, and UBC on-chip modules. SYSCR2 is initialized to H'01 by a power-on reset. Note: The method of writing to SYSCR2 is different from that of ordinary registers to prevent inadvertent rewriting. See section 27.2.4, Notes on Register Access, for more information. * Bit 7Reserved: This bit is always read as 0 and cannot be modified. * Bits 6 to 4--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 3--Module Stop 3 (MSTOP3): Specifies halting of the clock supply to the AUD on-chip peripheral module. Setting the MSTOP3 bit to 1 stops the clock supply to the AUD. To cancel halting of the clock supply to the AUD, first set the AUD software reset bit (AUDSRST) in the system control register 1 (SYSCR1) to the AUD reset state value. Use of the AUD will then be enabled by clearing the AUD reset. Bit 3: MSTOP3 Description 0 AUD operates 1 Clock supply to AUD stopped (Initial value) * Bit 2--Module Stop 2 (MSTOP2): Specifies halting of the clock supply to the H-UDI on-chip peripheral module. Setting the MSTOP2 bit to 1 stops the clock supply to the H-UDI. Bit 2: MSTOP2 Description 0 H-UDI operates 1 Clock supply to H-UDI stopped (Initial value) * Bit 1--Module Stop 1 (MSTOP1): Specifies halting of the clock supply to the FPU on-chip peripheral module. Setting the MSTOP1 bit to 1 stops the clock supply to the FPU. The MSTOP1 bit cannot be cleared by writing 0 after it has been set to 1. In other words, once the MSTOP1 bit has been set to 1 and the clock supply to the FPU has been stopped, the clock supply to the FPU cannot be resumed by clearing the MSTOP1 bit to 0. This LSI's power-on reset is necessary to restart the FPU clock supply after it has been stopped. Bit 1: MSTOP1 Description 0 FPU operates 1 Clock supply to FPU stopped (Initial value) Rev. 5.00 Feb. 24, 2010 Page 817 of 950 REJ09B0177-0500 27. Power-Down State * Bit 0--Module Stop 0 (MSTOP0): Specifies halting of the clock supply to the UBC on-chip peripheral module. Clearing the MSTOP0 bit to 0 starts the clock supply to the UBC. Stopping clock supply to the UBC will reset the internal state of the UBC including its registers. Bit 0: MSTOP0 Description 0 UBC operates 1 Clock supply to UBC stopped 27.2.4 (Initial value) Notes on Register Access The method of writing to system control register 2 (SYSCR2) is different from that of ordinary registers to prevent inadvertent rewriting. Be certain to use a word transfer instruction when writing data to SYSCR2. Data cannot be written by a byte transfer instruction. As shown in figure 27.1, set the upper byte to H'3C and transfer data using the lower byte as write data. Data can be read by the same method as for ordinary registers. SYSCR2 is allocated to address H'FFFFF70A. Always use a byte transfer instruction to read data. When writing to SYSCR2 15 Address: 8 H'FFFFF70A 7 H'3C 0 Write data Figure 27.1 Writing to SYSCR2 27.3 Hardware Standby Mode 27.3.1 Transition to Hardware Standby Mode The chip enters hardware standby mode when the HSTBY and RES pins go low. The mode pin should be set according to the pin settings described in section 4, Operating Modes. If other settings are applied to the mode pin, operation cannot be guaranteed. In hardware standby mode, power consumption is drastically reduced by halting all the functions in this LSI and stopping the internal power supply except the on-chip RAM. Since the transition to hardware standby mode is made by an external pin input, the transition is made asynchronously, regardless of the current state of this LSI, and internal power supply is stopped except the on-chip RAM. Therefore the chip state prior to the transition is not preserved. However, on-chip RAM data is retained as long as the specified voltage is supplied. To retain on-chip RAM data, clear the RAM enable bit (RAME) to 0 in the system control register 1 (SYSCR1) before driving the HSTBY pin low. Rev. 5.00 Feb. 24, 2010 Page 818 of 950 REJ09B0177-0500 27. Power-Down State 27.3.2 Canceling Hardware Standby Mode Hardware standby mode is canceled by means of the HSTBY pin and RES pin. When HSTBY is driven high while RES is low, the clock oscillator starts running. The RES pin should be held low long enough for clock oscillation to stabilize. When RES is driven high, power-on reset exception processing is started and a transition is made to the program execution state. 27.3.3 Hardware Standby Mode Timing Figure 27.2 shows sample pin timings for hardware standby mode. A transition to hardware standby mode is made by driving the HSTBY pin low after driving the RES pin low. Hardware standby mode is canceled by driving HSTBY high, waiting for clock oscillation to stabilize, then switching RES from low to high. Oscillator pulse width tRESW Oscillation settling time + pulse width Reset exception processing Figure 27.2 Hardware Standby Mode Timing 27.4 Software Standby Mode 27.4.1 Transition to Software Standby Mode To enter software standby mode, set the software standby bit (SSBY) to 1 in SBYCR, then execute the SLEEP instruction. This LSI switches from the program execution state to software standby mode. In software standby mode, power consumption is drastically reduced by halting all the functions in this LSI and stopping the internal power supply except the on-chip RAM. The contents of the on-chip RAM are held as long as the given voltages are supplied. For details on the register states of on-chip peripheral modules, see Appendix A.2, Register States in Reset and Power-Down States. For details on the pin states, see Appendix B, Pin States. 27.4.2 Canceling Software Standby Mode Software standby mode is canceled by a rising edge of the NMI pin or a power-on reset. Cancellation by a rising edge of the NMI pin: When a rising edge of the NMI pin is detected, the internal power supply and clock oscillation start, and the inside of the LSI is in the power-on reset state. The clock is supplied only to the oscillation settling counter, which counts the oscillation stabilizing time, until the oscillation settles. When the oscillation settling counter value reaches the given value, meaning that the clock has been stabilized, the clock is supplied to the entire chip and the power-on reset state in this LSI is canceled. The CPU starts the power-on reset processing. Rev. 5.00 Feb. 24, 2010 Page 819 of 950 REJ09B0177-0500 27. Power-Down State The oscillation settling counter overflows when it counts 216 = 65536 with the input clock frequency. Since the frequency of the counting clock is unstable until the PLL, multiplication circuit, is locked, the accurate time is not given. The signal output on the CK pin and duty cycle may be unstable from oscillation start to oscillation stabilization. When software standby mode is canceled by the NMI interrupt, the software standby flag (SSBYF) holds 1. Cancellation by Power-On Reset: When the RES pin is driven low, this LSI enters the power-on reset state and software standby mode is canceled. At this time, the software standby flag (SSBYF) is cleared to 0. 27.4.3 Software Standby Mode Application Example In this example, the NMI exception processing is started by the falling edge of the NMI signal; a transition to software standby mode is made; the mode is canceled by the rising edge of the NMI signal. The timing is shown in figure 27.3. When the NMI signal is driven from high to low while the NMI edge select bit (NMIE) in ICR is set to 0 (falling edge detection), the NMI interrupt is accepted. When the NMIE bit is set to 1 (rising edge detection) in the NMI exception service routine and the SLEEP instruction is executed with the software standby bit (SSBY) in SBYCR set to 1, software standby mode is entered and the internal power supply is stopped. Thereafter, software standby mode is canceled when the NMI signal is driven from low to high. After the internal power supply is provided, the clock starts oscillation, and the oscillation settling counter overflows, the power-on reset exception processing begins. Oscillator CK NMI SSBYF flag Internal power supply Internal reset state Internal LSI reset LSI state Program execution NMI exception processing Software standby mode Oscillation Settling time Figure 27.3 Software Standby Mode NMI Timing (Application Example) Rev. 5.00 Feb. 24, 2010 Page 820 of 950 REJ09B0177-0500 Reset exception processing 27. Power-Down State 27.5 Sleep Mode 27.5.1 Transition to Sleep Mode Executing the SLEEP instruction after the software standby bit (SSBY) in SBYCR has been cleared to 0 causes a transition from the program execution state to sleep mode. Although the CPU halts immediately after executing the SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip peripheral modules continue to run during sleep mode. 27.5.2 Canceling Sleep Mode Cancellation by Interrupt: When an interrupt occurs, sleep mode is canceled and interrupt exception processing is executed. The sleep mode is not canceled if the interrupt cannot be accepted because its priority level is equal to or less than the mask level set in the CPU's status register (SR) or if an interrupt by an on-chip peripheral module is disabled by the peripheral module. Cancellation by DMA Address Error: If a DMA address error occurs, sleep mode is canceled and DMA address error exception processing is executed. Cancellation by Manual Reset: When an internal manual reset is triggered by the WDT and the CPU acquires the bus during the internal manual reset period, the state of this LSI changes to the manual reset state and sleep mode will be released. Cancellation by Power-On Reset: A power-on reset of this LSI resulting from driving the RES pin low, or caused by the WDT, cancels sleep mode. Note: When performing cancellation by power-on reset, do not place RAM write instructions immediately (within eight instructions) after the sleep instruction. This will ensure that no instructions are executed before the transition to the reset. Rev. 5.00 Feb. 24, 2010 Page 821 of 950 REJ09B0177-0500 27. Power-Down State Rev. 5.00 Feb. 24, 2010 Page 822 of 950 REJ09B0177-0500 28. Reliability Section 28 Reliability 28.1 Reliability A failure rate curve represents an index of the reliability of a semiconductor device. The failure rate curve traces a bathtub shape over the course of time, as is shown in figure 28.1. The curve is divided into three periods according to the type of failure phenomena: an initial failure period, a random failure period (functional lifetime), and a wear-out failure period. Initial failures, which occur during the initial failure period, are caused by contamination with foreign matter and localized chemical pollution; these can be eliminated by screening. Wear-out failures in the final period are caused by the deterioration of materials that make up semiconductor devices during long periods of usage. Random failures, which occur during the random failure period, are thought to occur in cases where a device with a minor failure is not removed by screening, and so is shipped, and then fails during the customer's production process or in the field, and in cases where a failure which should normally not have occurred until the wear-out period occurs earlier because of variations in production. Therefore, the reliability of semiconductor device is secured by appropriate screening to reduce the presence of initial failures and high reliability design to prevent the occurrence of wear-out failures. The reliability of a product is confirmed by producing a large quantity of prototypes for checking of the initial failure rate and executing accelerated life testing to identify the wear-out failure time in a realistic environment. Initial failure period Wear-out failure period Screening Failure rate Functional lifetime Random failure period Time Figure 28.1 Failure Rate Curve (Bathtub Curve) The reliability of products is estimated on the assumption that products developed for the automotive sector are used in a tougher environment than products for the consumer and industrial sectors. The representative failure phenomena of semiconductor devices, such as the dielectric breakdown of oxide films and electromigration in wiring, constitute wear-out failures. The stress factors in such failures are the voltage, current, and temperature applied to devices while they are in use. Since the temperature range for the guaranteed operation of products for use in automobiles is conventionally -40C to 85C, their reliability in terms of the above failure phenomena has to be confirmed by accelerated life testing at all temperatures in this range. Operation at temperatures in excess of 85C leads to failure within a short time, since high temperatures induce failures in semiconductor devices. Rev. 5.00 Feb. 24, 2010 Page 823 of 950 REJ09B0177-0500 28. Reliability Figure 28.2 shows the temperature dependence of semiconductor device lifetimes. The type of failure in this figure is a wear-out failure, i.e. the dielectric breakdown of oxide film. According to figure 28.2, the life at 125C is 1/10 of life at 85C, and operation at the higher temperature leads to a correspondingly higher probability of a failure in the field. Therefore, the reliability of operation at a temperature in excess of 85C is checked on the assumption that the period of operation at the upper-limit temperature of the range for guaranteed operation is 3000 hours. 100 Activation energy 0.6eV Lifetime (log t) 10 1 0.1 0.01 125 85 50 Temperature (C) Figure 28.2 Temperature Reliability of Dielectric Breakdown of Oxide Film Rev. 5.00 Feb. 24, 2010 Page 824 of 950 REJ09B0177-0500 29. Electrical Characteristics Section 29 Electrical Characteristics 29.1 Absolute Maximum Ratings Table 29.1 shows the absolute maximum ratings. Table 29.1 Absolute Maximum Ratings Item Symbol Rating Unit Remarks VCC and PLLVCC pins VCC -0.3 to +4.3 V The EXTAL, XTAL, CK, and H-UDI pins are concerned. (VCC and PLLVCC are the same voltage) PVCC1 and PVCC2 pins PVCC -0.3 to + 6.5 V Except for the PLLCAP, EXTAL, XTAL, CK, and H-UDI pins and the analog input pin Vin -0.3 to VCC + 0.3 V Refer to table 29.2 All pins other than Vin analog input, EXTAL, PLLCAP, and H-UDI pins -0.3 to PVCC + 0.3 V PLLCAP pin Vin -0.3 to + 2.1 V AVCC -0.3 to +7.0 V Analog reference voltage AVref -0.3 to AVCC + 0.3 V Analog input voltage VAN -0.3 to AVCC + 0.3 V Operating temperature (except writing or erasing flash memory) Topr -40 to + 125 C Operating temperature (writing or TWEopr erasing flash memory) -40 to +85 C Storage temperature -55 to +125 C Power supply voltage* Input voltage EXTAL and H-UDI pins Analog supply voltage Tstg [Operating precautions] Operating the LSI in excess of the absolute maximum ratings may result in permanent damage. The two power supply voltages of PVCC of 5V and VCC of 3V may be used simultaneously with the LSI. Be sure to use the LSI in compliance with the connection of power pins, combination conditions of applicable power supply voltages, voltage applicable to each pin, and conditions of output voltage, as specified in the manual. Connecting a non-specified power supply or using the LSI at an incorrect voltage may result in permanent damage of the LSI or the system that contains the LSI. Note: * Do not apply any power supply voltage to the VCL pin. Connect to GND through an external capacitor (0.33 to 0.47 F). Rev. 5.00 Feb. 24, 2010 Page 825 of 950 REJ09B0177-0500 29. Electrical Characteristics 29.2 DC Characteristics Table 29.2 shows the correspondence between power supply names and pins. Table 29.4 shows DC characteristics. Table 29.2 Correspondence between Power Supply Names and Pins Power Supply Pin Pin No. Power Supply Name Output Circuit Input Power Voltage Supply Name Upper Limit (V) Dedicated Pin Function 1 Function 2 Function 3 Function 4 User Pin 1 PD8 PULS0 PVCC2 PVCC2+0.3 2 PD9 PULS1 PVCC2 PVCC2+0.3 3 PD10 PULS2 PVCC2 PVCC2+0.3 4 PD11 PULS3 PVCC2 PVCC2+0.3 5 PD12 PULS4 PVCC2 PVCC2+0.3 6 PD13 PULS6 PVCC2 PVCC2+0.3 7 PE0 A0 PVCC1 PVCC1+0.3 8 PE1 A1 PVCC1 PVCC1+0.3 9 PE2 A2 PVCC1 PVCC1+0.3 10 PE3 A3 PVCC1 PVCC1+0.3 PE4 A4 PVCC1 PVCC1+0.3 14 PE5 A5 PVCC1 PVCC1+0.3 15 PE6 A6 PVCC1 PVCC1+0.3 16 PE7 A7 PVCC1 PVCC1+0.3 17 PE8 A8 PVCC1 PVCC1+0.3 18 PE9 A9 PVCC1 PVCC1+0.3 19 PE10 A10 PVCC1 PVCC1+0.3 PE11 A11 PVCC1 PVCC1+0.3 23 PE12 A12 PVCC1 PVCC1+0.3 24 PE13 A13 PVCC1 PVCC1+0.3 25 PE14 A14 PVCC1 PVCC1+0.3 26 PE15 A15 PVCC1 PVCC1+0.3 27 PF0 A16 PVCC1 PVCC1+0.3 28 PF1 A17 PVCC1 PVCC1+0.3 29 PF2 A18 PVCC1 PVCC1+0.3 PF3 A19 PVCC1 PVCC1+0.3 11 20 VSS PVCC1 21 22 30 VSS VCL 31 32 HTxD1 VCC 12 13 HTxD0 VSS 33 PF4 A20 34 PF5 A21 35 PF6 36 PF7 Rev. 5.00 Feb. 24, 2010 Page 826 of 950 REJ09B0177-0500 PVCC1 PVCC1+0.3 PVCC1 PVCC1+0.3 WRL PVCC1 PVCC1+0.3 WRH PVCC1 PVCC1+0.3 POD Notes 29. Electrical Characteristics Power Supply Pin Pin No. Power Supply Name Output Circuit Input Power Voltage Supply Name Upper Limit (V) Dedicated Pin Function 1 Function 2 Function 3 Function 4 User Pin 37 PF8 WAIT PVCC1 PVCC1+0.3 38 PF9 RD PVCC1 PVCC1+0.3 PF10 CS0 PVCC1 PVCC1+0.3 42 PF11 CS1 PVCC1 PVCC1+0.3 43 PF12 CS2 PVCC1 PVCC1+0.3 44 PF13 CS3 PVCC1 PVCC1+0.3 45 PF14 BACK SCS0 PVCC1 PVCC1+0.3 46 PF15 BREQ SCS1 PVCC1 PVCC1+0.3 39 PVCC1 40 41 47 VSS VSS 48 49 CK VCC VCC 50 MD2 5.5+0.3 51 EXTAL VCC+0.3 52 VCC 53 54 XTAL VCC VSS 55 MD1 5.5+0.3 56 FWE 5.5+0.3 57 HSTBY 5.5+0.3 58 RES 5.5+0.3 59 MD0 5.5+0.3 60 PLLVCC 61 62 PLLCAP PLLVSS 63 PH0 D0 PVCC1 PVCC1+0.3 64 PH1 D1 PVCC1 PVCC1+0.3 65 PH2 D2 PVCC1 PVCC1+0.3 66 PH3 D3 PVCC1 PVCC1+0.3 67 PH4 D4 PVCC1 PVCC1+0.3 68 PH5 D5 PVCC1 PVCC1+0.3 PH6 D6 PVCC1 PVCC1+0.3 PH7 D7 PVCC1 PVCC1+0.3 PH8 D8 PVCC1 PVCC1+0.3 PH9 D9 PVCC1 PVCC1+0.3 PH10 D10 PVCC1 PVCC1+0.3 PH11 D11 PVCC1 PVCC1+0.3 69 70 PVCC1 71 72 VSS 73 74 75 VCC 76 77 78 Notes VSS Rev. 5.00 Feb. 24, 2010 Page 827 of 950 REJ09B0177-0500 29. Electrical Characteristics Power Supply Pin Pin No. Power Supply Name Output Circuit Input Power Voltage Supply Name Upper Limit (V) Dedicated Pin Function 1 Function 2 Function 3 Function 4 User Pin 79 PH12 D12 PVCC1 PVCC1+0.3 80 PH13 D13 PVCC1 PVCC1+0.3 81 PH14 D14 PVCC1 PVCC1+0.3 PH15 D15 PVCC1 PVCC1+0.3 82 83 PVCC1 84 85 NMI 5.5+0.3 VSS 86 AN0 AVCC+0.3 87 AN1 AVCC+0.3 88 AN2 AVCC+0.3 89 AN3 AVCC+0.3 90 AN4 AVCC+0.3 91 AN5 AVCC+0.3 92 AN6 AVCC+0.3 93 AN7 AVCC+0.3 94 AN8 AVCC+0.3 95 AN9 AVCC+0.3 96 AN10 AVCC+0.3 97 AN11 AVCC+0.3 AN12 AVCC+0.3 102 AN13 AVCC+0.3 103 AN14 AVCC+0.3 104 AN15 AVCC+0.3 105 AN16 AVCC+0.3 106 AN17 AVCC+0.3 107 AN18 AVCC+0.3 108 AN19 AVCC+0.3 109 AN20 AVCC+0.3 110 AN21 AVCC+0.3 111 AN22 AVCC+0.3 112 AN23 AVCC+0.3 113 AN24 AVCC+0.3 114 AN25 AVCC+0.3 115 AN26 AVCC+0.3 116 AN27 AVCC+0.3 117 AN28 AVCC+0.3 118 AN29 AVCC+0.3 98 99 AVSS 100 101 119 120 AVref AVCC AVCC AVref Rev. 5.00 Feb. 24, 2010 Page 828 of 950 REJ09B0177-0500 Notes 29. Electrical Characteristics Power Supply Pin Pin No. Power Supply Name 121 AVSS Output Circuit User Pin Input Voltage Upper Power Dedicated Pin Function 1 Function 2 Function 3 Function 4 Supply Name Limit (V) 122 AN30 AVCC+0.3 123 AN31 AVCC+0.3 WDTOVF 124 125 Notes PVCC2 PA0 TI0A PVCC2 PVCC2+0.3 Schmitt-trigger input pin PA1 TI0B PVCC2 PVCC2+0.3 Schmitt-trigger input pin 129 PA2 TI0C PVCC2 PVCC2+0.3 130 PA3 TI0D PVCC2 PVCC2+0.3 Schmitt-trigger input pin 131 PA4 TIO3A PVCC2 PVCC2+0.3 126 VSS 127 128 PVCC2 132 PA5 TIO3B PVCC2 PVCC2+0.3 133 PA6 TIO3C PVCC2 PVCC2+0.3 134 PA7 TIO3D PVCC2 PVCC2+0.3 135 PA8 TIO4A ADTO0A PVCC2 PVCC2+0.3 136 PA9 TIO4B ADTO0B PVCC2 PVCC2+0.3 137 PA10 TIO4C ADTO1A PVCC2 PVCC2+0.3 138 PA11 TIO4D ADTO1B PVCC2 PVCC2+0.3 PA12 TIO5A PVCC2 PVCC2+0.3 Schmitt-trigger input pin 142 PA13 TIO5B PVCC2 PVCC2+0.3 Schmitt-trigger input pin 143 PA14 TxD0 SSO0 PVCC2 PVCC2+0.3 144 PA15 RxD0 SSI0 PVCC2 PVCC2+0.3 145 PB0 TO6A PVCC2 PVCC2+0.3 146 PB1 TO6B PVCC2 PVCC2+0.3 147 PB2 TO6C PVCC2 PVCC2+0.3 PB3 TO6D PVCC2 PVCC2+0.3 151 PB4 TO7A TO8A PVCC2 PVCC2+0.3 152 PB5 TO7B TO8B PVCC2 PVCC2+0.3 153 PB6 TO7C TO8C PVCC2 PVCC2+0.3 154 PB7 TO7D TO8D PVCC2 PVCC2+0.3 155 PB8 TxD3 TO8E PVCC2 PVCC2+0.3 156 PB9 RxD3 TO8F PVCC2 PVCC2+0.3 157 PB10 TxD4 HTxD0 TO8G PVCC2 PVCC2+0.3 158 PB11 RxD4 HRxD0 TO8H PVCC2 PVCC2+0.3 139 VCC 140 141 148 VSS PVCC2 149 150 VSS Rev. 5.00 Feb. 24, 2010 Page 829 of 950 REJ09B0177-0500 29. Electrical Characteristics Power Supply Pin Pin No. Power Supply Name Output Circuit User Pin Input Voltage Upper Power Dedicated Pin Function 1 Function 2 Function 3 Function 4 Supply Name Limit (V) Notes 159 PB12 TCLKA UBCTRG PVCC2 PVCC2+0.3 160 PB13 SCK0 SSCK0 PVCC2 PVCC2+0.3 PB14 SCK1 TCLKB TI10 PVCC2 PVCC2+0.3 Schmitt-trigger input pin 164 PB15 PULS5 SCK2 SSCK1 PVCC2 PVCC2+0.3 Schmitt-trigger input pin 165 PC0 TxD1 PVCC2 PVCC2+0.3 166 PC1 RxD1 PVCC2 PVCC2+0.3 167 PC2 TxD2 SSO1 PVCC2 PVCC2+0.3 168 PC3 RxD2 SSI1 PVCC2 PVCC2+0.3 169 PC4 IRQ0 PVCC2 PVCC2+0.3 170 PG0 PULS7 PVCC2 PVCC2+0.3 171 PG1 IRQ1 PVCC2 PVCC2+0.3 Schmitt-trigger input pin PG2 IRQ2 ADEND PVCC2 PVCC2+0.3 Schmitt-trigger input pin 175 PG3 IRQ3 ADTRG0 PVCC2 PVCC2+0.3 176 PJ0 TIO2A PVCC2 PVCC2+0.3 Schmitt-trigger input pin 177 PJ1 TIO2B PVCC2 PVCC2+0.3 178 PJ2 TIO2C PVCC2 PVCC2+0.3 179 PJ3 TIO2D PVCC2 PVCC2+0.3 180 PJ4 TIO2E PVCC2 PVCC2+0.3 181 PJ5 TIO2F PVCC2 PVCC2+0.3 182 PJ6 TIO2G PVCC2 PVCC2+0.3 183 PJ7 TIO2H PVCC2 PVCC2+0.3 PJ8 TIO5C PVCC2 PVCC2+0.3 PJ9 TIO5D PVCC2 PVCC2+0.3 Schmitt-trigger input pin 188 PJ10 TI9A PVCC2 PVCC2+0.3 Schmitt-trigger 189 PJ11 TI9B PVCC2 PVCC2+0.3 190 PJ12 TI9C PVCC2 PVCC2+0.3 191 PJ13 TI9D PVCC2 PVCC2+0.3 161 VCL 162 163 172 VSS VSS 186 187 HRxD1 VSS 184 185 HRxD0 Schmitt-trigger input pin PVCC2 173 174 Schmitt-trigger input pin VCC input pin 192 PJ14 TI9E PVCC2 PVCC2+0.3 193 PJ15 TI9F PVCC2 PVCC2+0.3 PK0 TO8A PVCC2 PVCC2+0.3 194 195 PVCC2 Rev. 5.00 Feb. 24, 2010 Page 830 of 950 REJ09B0177-0500 Schmitt-trigger input pin 29. Electrical Characteristics Power Supply Pin Pin No. Power Supply Name 196 VSS Output Circuit User Pin Input Voltage Upper Power Dedicated Pin Function 1 Function 2 Function 3 Function 4 Supply Name Limit (V) 197 PK1 TO8B PVCC2 PVCC2+0.3 198 PK2 TO8C PVCC2 PVCC2+0.3 199 PK3 TO8D PVCC2 PVCC2+0.3 200 PK4 TO8E PVCC2 PVCC2+0.3 201 PK5 TO8F PVCC2 PVCC2+0.3 202 PK6 TO8G PVCC2 PVCC2+0.3 PK7 TO8H PVCC2 PVCC2+0.3 206 PK8 TO8I PVCC2 PVCC2+0.3 207 PK9 TO8J PVCC2 PVCC2+0.3 208 PK10 TO8K PVCC2 PVCC2+0.3 209 PK11 TO8L PVCC2 PVCC2+0.3 210 PK12 TO8M PVCC2 PVCC2+0.3 211 PK13 TO8N PVCC2 PVCC2+0.3 PK14 TO8O PVCC2 PVCC2+0.3 215 PK15 TO8P PVCC2 PVCC2+0.3 216 PL0 TI10 PVCC2 PVCC2+0.3 217 PL1 TIO11A IRQ6 PVCC2 PVCC2+0.3 218 PL2 TIO11B IRQ7 PVCC2 PVCC2+0.3 203 VCC 204 205 212 VSS PVCC2 213 214 VSS 219 PL3 TCLKB PVCC2 PVCC2+0.3 220 PL4 ADTRG0 PVCC2 PVCC2+0.3 221 PL5 ADTRG1 PVCC2 PVCC2+0.3 222 PL6 ADEND PVCC2 PVCC2+0.3 223 PL7 SCK2 PVCC2 PVCC2+0.3 PL8 SCK3 PVCC2 PVCC2+0.3 PL9 SCK4 IRQ5 PVCC2 PVCC2+0.3 228 PL10 HTxD0 HTxD1 HTxD0 and PVCC2 1 PVCC2+0.3 229 PL11 HRxD0 HRxD1 HRxD0, 1 PVCC2 PVCC2+0.3 230 PL12 IRQ4 SCS0 PVCC2 PVCC2+0.3 231 PL13 IRQOUT IRQOUT 232 TMS VCC+0.3 233 TRST VCC+0.3 234 TDI VCC+0.3 224 225 SSCK1 Schmitt-trigger input pin Schmitt-trigger input pin VCL 226 227 Notes Schmitt-trigger input pin VSS SCS1 PVCC2 Schmitt-trigger input pin PVCC2+0.3 Rev. 5.00 Feb. 24, 2010 Page 831 of 950 REJ09B0177-0500 29. Electrical Characteristics Power Supply Pin Pin No. Power Supply Name User Pin Output Circuit Input Voltage Upper Power Dedicated Pin Function 1 Function 2 Function 3 Function 4 Supply Name Limit (V) 235 TDO 236 TCK VCC+0.3 AUDRST PVCC2+0.3 237 VCC VCC 238 239 Notes VSS 240 AUDMD 241 AUDATA0 PVCC2 PVCC2+0.3 242 AUDATA1 PVCC2 PVCC2+0.3 243 AUDATA2 PVCC2 PVCC2+0.3 244 AUDATA3 PVCC2 PVCC2+0.3 245 AUDCK PVCC2 PVCC2+0.3 AUDSYNC PVCC2 PVCC2+0.3 PVCC2 PVCC2+0.3 Schmitt-trigger input pin Schmitt-trigger input pin 246 247 PVCC2 248 249 PVCC2+0.3 PD0 TIO1A VSS 250 PD1 TIO1B PVCC2 PVCC2+0.3 251 PD2 TIO1C PVCC2 PVCC2+0.3 252 PD3 TIO1D PVCC2 PVCC2+0.3 253 PD4 TIO1E PVCC2 PVCC2+0.3 254 PD5 TIO1F PVCC2 PVCC2+0.3 255 PD6 TIO1G PVCC2 PVCC2+0.3 256 PD7 TIO1H PVCC2 PVCC2+0.3 Rev. 5.00 Feb. 24, 2010 Page 832 of 950 REJ09B0177-0500 29. Electrical Characteristics [Usage Notes] Set power supply voltages during LSI operation as shown below. VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1 The PVCC1 power supply voltage depends on the operating mode as shown below. Operation cannot be guaranteed with other PVCC1 power supply voltages. Table 29.3 PVCC1 Voltage in Each Operating Mode Pin Setting Operating Mode No FWE MD2 MD1 MD0 Mode Name PVCC1 Voltage Mode 0 0 1 0 0 MCU expanded mode 3.3 V 0.3 V Mode 1 0 1 0 1 Mode 2 0 1 1 0 Mode 3 0 1 1 1 MCU Single-chip mode 5.0 V 0.5 V Mode 4 1 1 0 0 Boot mode 3.3 V 0.3 V Mode 5 1 1 0 1 Mode 6 1 1 1 0 Mode 7 1 1 1 1 Mode 8 1 0 0 0 Mode 9 1 0 0 1 5.0 V 0.5 V User program mode 3.3 V 0.3 V User boot mode 3.3 V 0.3 V 5.0 V 0.5 V 5.0 V 0.5 V Rev. 5.00 Feb. 24, 2010 Page 833 of 950 REJ09B0177-0500 29. Electrical Characteristics Table 29.4 DC Characteristics Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing flash memory, Ta = -40C to 85C. Symbol Min Typ Max Unit Measurement Conditions VIH VCC - 0.4 -- 5.8 V 2.4V VCC < 2.7V VCC - 0.5 -- 5.8 EXTAL VCC x 0.7 -- VCC + 0.3 V D15-D0, WAIT, BREQ (When in MCU expanded mode) 2.2 -- PVCC1 + 0.3 V PVCC1 = 3.3 V 0.3 V PE15-PE0, PF15-PF0, PH15-PH0 (When in MCU expanded mode) 2.2 -- PVCC1 + 0.3 V PVCC1 = 3.3 V 0.3 V TRST PVCC - 0.5 -- VCC + 0.3 V TMS, TDI, TCK 2.2 -- VCC + 0.3 V AUDRST, AUDMD PVCC - 0.5 -- PVCC2 + 0.3 V PG0, PL11 PVCC2 x 0.7 PVCC2 + 0.3 V Other input pins 2.2 -- PVcc + 0.3 V -0.3 -- 0.4 V -0.3 -- 0.5 PG0, PL11 -0.3 -- PVCC2 x 0.3 V Other input pins -0.3 -- 0.8 V Item Input high-level voltage (except Schmitt trigger input voltage) Input low-level voltage (except Schmitt trigger input voltage) RES, NMI, FWE, MD2-0, HSTBY RES, NMI, FWE, MD2-0, HSTBY, TRST, AUDRST, AUDMD Rev. 5.00 Feb. 24, 2010 Page 834 of 950 REJ09B0177-0500 VIL 2.7V VCC < 3.6V 2.4V VCC < 2.7V 2.7V VCC < 3.6V 29. Electrical Characteristics Item Schmitt trigger input voltage Input leak current TI0A-TI0D, TIO1A-TIO1H, TIO2A- TIO2H, TIO3A-TIO3D, TIO4A-TIO4D, TIO5A- TIO5D, TI9A-TI9F, TI10, TIO11A- TIO11B, TCLKA, TCLKB, ADTRG0, ADTRG1, SCK0- SCK4, IRQ0-IRQ7 and when these pins are selected as I/O ports RES, NMI, FWE, MD2-0, HSTBY Unit Min Typ Max (VIH) VT+ 4.0 -- (PVCC2 + V 0.3) (VIL) VT- (-0.3) -- 1.0 V + - VT - VT 0.4 -- -- V | lin | -- -- 3.0*1 A Vin = 0.3 V to 5.8 V A Vin = 0.3 V to VCC - 0.3 V A Vin = 0.3 V to VCC - 0.3 V A Vin = 0.3 V to PVCC2 - 0.3 V A Vin = 0.3 V to PVCC2 - 0.3 V A Vin = 0.3 V to AVCC - 0.3 V A Vin = 0.3 V to PVCC1 - 0.3 V PVCC1 = 3.3 V 0.3 V A Vin = 0.3 V to PVCC1 - 0.3 V PVCC1 = 3.3 V 0.3 V A Vin = 0.3 V to PVCC2 - 0.3 V -- -- 3.0*1 2 6.0* TMS, TRST, TDI, TCK (Standby) -- AUDMD, AUDCK, AUDSYNC, AUDATA3-0 (Standby) -- AUDRST (Standby) -- -- 3.0*1 6.0*2 -- 3.0*1 6.0*2 -- 3.0*1 2 6.0* A/D port -- -- 0.1*1 0.2*2 | lin | -- -- 3.0*1 2 6.0* PE15-PE0, PF15-PF0, PH15-PH0 (When in MCU expanded mode) -- Other input pins -- -- 3.0*1 2 6.0* -- 3.0* 1 2 6.0* Input pull-up MOS current Input pull-down MOS current Refer to table 29.2, Correspondence between Power Supply Names and Pins 6.0*2 EXTAL (Standby) D15-D0, WAIT, BREQ (When in MCU expanded mode) Measurement Conditions Symbol TMS, TRST, TDI, TCK (pull- -Ipu up characteristic) -- -- 350 A Vin = 0 V AUDMD, AUDCK, AUDSYNC, AUDATA3-0 (pull-up characteristic) -- -- 800 A Vin = 0 V Ipd -- -- 800 A Vin = PVCC2 l Its l -- -- 3.0*1 A Vin = 0.3 V to PVCC1 - 0.3 V PVCC1 = 3.3 V 0.3 V AUDRST (pull-down characteristic) Three-state leak A21-A0, D15-D0, CS3- current (while OFF) CS0, WRH, WRL, RD, BACK (When in MCU expanded mode) 6.0*2 Rev. 5.00 Feb. 24, 2010 Page 835 of 950 REJ09B0177-0500 29. Electrical Characteristics Item Symbol Output high-level voltage Output high-level voltage Typ Max Unit A21-A0, D15-D0, VOH CS3-CS0, WRH, WRL, RD, BACK (When in MCU expanded mode) PVcc1- 0.5 -- -- V IOH = 200 A PVCC1 = 3.3 V 0.3 V PE15-PE0, PF15-PF0, PH15-PH0 (When in MCU expanded mode) PVcc1- 0.5 -- -- V IOH = 200 A PVCC1 = 3.3 V 0.3 V CK, TDO VCC - 0.5 -- -- V IOH = 200 A PVCC - 0.5 -- -- V IOH = 200 A PVCC - 1.0 -- -- V IOH = 1 mA -- -- 0.4 V IOL = 1.6 mA PVCC1 = 3.3 V 0.3 V PE15-PE0, PF15-PF0, PH15-PH0 (When in MCU expanded mode) -- -- 0.4 V IOL = 1.6 mA PVCC1 = 3.3 V 0.3 V Other output pins (except XTAL) -- -- 0.4 V IOL = 1.6 mA -- -- 1.2 V IOL = 6 mA -- -- 60 pF Vin = 0 V NMI -- -- 30 pF f = 1 MHz All other input pins -- -- 20 pF Ta = 25C -- 100 150 mA f = 80 MHz (SH7058SF) -- 130 180 -- 80 130 -- 90 160 Standby -- -- 300 A Ta 50C (2.4 V Vcc 3.6 V) -- -- 750 A 50C < Ta 105C -- -- 1000 A 105C < Ta 125C -- 110 170 mA VCC = 3.3 V Other output pins A21-A0, D15-D0, CS3- CS0, WRH, WRL, RD, BACK (When in MCU expanded mode) Input capacitance Current consumption Measurement Conditions Min RES Normal operation VOH VOL Cin ICC Sleep Write operation f = 80 MHz (SH7059F) mA f = 80 MHz (SH7058SF) f = 80 MHz (SH7059F) f = 80 MHz (SH7058SF) -- 140 200 VCC = 3.3 V f = 80 MHz (SH7059F) Analog supply current During A/D conversion AlCC Awaiting A/D conversion, standby Reference power supply current During A/D conversions, awaiting A/D conversion Alref Standby RAM standby voltage Notes: 1. Ta 105C 2. Ta > 105C Rev. 5.00 Feb. 24, 2010 Page 836 of 950 REJ09B0177-0500 VRAM -- 4.5 12 mA -- 1.0 30 A -- 1.1 5 mA -- 1.1 30 A 2.4 -- -- V AVref = 5.0 V VCC 29. Electrical Characteristics [Operating precautions] 1. When the A/D converter is not used (including during standby), do not leave the AVCC, AVref, and AVSS pins open. 2. The current consumption is measured when VIHmin = VCC - 0.3 V/PVCC - 0.3 V, VIL = 0.3 V, with all output pins unloaded. 3. The guaranteed operating range of power supply PVCC1 in the MCU expanded modes is only PVCC1 = 3.3 V 0.3 V. Do not use a voltage outside this range. 4. The guaranteed operating range of power supply PVCC1 in MCU single-chip mode is only PVCC1 = 5.0 V 0.5 V. Do not use a voltage outside this range. Table 29.5 Permitted Output Current Values Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. Item Symbol Min Typ Max Unit Output low-level permissible current (per pin) IOL -- -- 6.0 mA Output low-level permissible current (total) IOL -- -- 80 mA Output high-level permissible current (per pin) IOH -- -- 2.0 mA Output high-level permissible current (total) IOL -- -- 25 mA [Operating precautions] To assure LSI reliability, do not exceed the output values listed in this table. 29.3 AC Characteristics 29.3.1 Timing for swicthing the power supply on/off Table 29.6 Timing for swicthing the power supply on/off Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. Item Symbol Min Max Unit Figures Time taken to switch VCC on tVCCS 0 -- ms Figure 29.1 VCC hold-time when PVCC is swtched off tVCCH 0 -- ms Rev. 5.00 Feb. 24, 2010 Page 837 of 950 REJ09B0177-0500 29. Electrical Characteristics VCC PLLVCC VCC min VCC min tVCCS PVCC1 PVCC2 tVCCH PVCC min PVCC min Figure 29.1 Power-On/Off Timing 29.3.2 Clock timing Table 29.7 shows the clock timing. Table 29.7 Clock Timing Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. Item Symbol Min Max Unit Figures Clock frequency fop 10 20 MHz Figure 29.2 Clock cycle time tcyc 50 100 ns Clock low-level pulse width t 12 -- ns Clock high-level pulse width t 12 -- ns CL CH Clock rise time t CR -- 10 ns Clock fall time t CF -- 10 ns EXTAL clock input frequency f 5 10 MHz EXTAL clock input cycle time t EXcyc 100 200 ns EXTAL clock input low-level pulse width t EXL 30 -- ns EXTAL clock input low-level pulse width t EXH 30 -- ns EXTAL clock input rise time t -- 8 ns EXTAL clock input fall time t EXF -- 8 ns Reset oscillation settling time tosc1 30 -- ms Standby return clock settling time tosc2 30 -- ms EX EXR Figure 29.3 Figure 29.4 The CK pin outputs the peripheral clock signal (P). [Operating precautions] The EXTAL, XTAL, and CK pins constitute a circuit requiring a power supply voltage of VCC = 3.3 V 0.3 V. Comply with the input and output voltages specified in the DC characteristics. Rev. 5.00 Feb. 24, 2010 Page 838 of 950 REJ09B0177-0500 29. Electrical Characteristics tcyc tCH 1/2VCC CK VOH tCL VOH 1/2VCC VOH VOL VOL tCF tCR Note: CK pin is VCC = 3.3 V 0.3 V power supply circuit. Figure 29.2 Peripheral Clock Timing tEXcyc tEXH VIH 1/2VCC EXTAL tEXL VIH VIL VIH 1/2VCC VIL tEXR tEXF Note: EXTAL pin is VCC = 3.3 V 0.3 V power supply circuit. Figure 29.3 EXTAL Clock Input Timing CK VCC PVCC1 PVCC2 VCC min tosc2 PVCC min VIH tosc1 tosc1 Figure 29.4 Oscillation Settling Time Rev. 5.00 Feb. 24, 2010 Page 839 of 950 REJ09B0177-0500 29. Electrical Characteristics 29.3.3 Control Signal Timing Table 29.8 shows control signal timing. Table 29.8 Control Signal Timing Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. Item Symbol Min Max Unit Figures RES pulse width tRESW 10 -- tcyc Figure 29.5 tRESS 30 -- ns MD2 to MD0 setup time 2* tMDS 10 -- tcyc NMI setup time tNMIS 30 -- ns IRQ7-IRQ0 setup time* (edge detection) tIRQES 30 -- ns IRQ7-IRQ0 setup time* (level detection) tIRQLS 30 -- ns NMI hold time tNMIH 30 -- ns IRQ7-IRQ0 hold time tIRQEH 30 -- ns IRQOUT output delay time tIRQOD -- 100 ns Figure 29.7 Bus request setup time tBRQS 30 -- ns Figure 29.8*3 Bus acknowledge delay time 1 tBACKD1 -- 30 ns Bus acknowledge delay time 2 tBACKD2 -- 30 ns Bus three-state delay time tBZD -- 30 ns RES setup time 1 2 2 Figure 29.6 [Operating precautions] 1. Mode setup time during power-on reset by the RES pin depends on the combination of signals to be input to the FWE and MD2 to MD0 pins. If a low-level signal is input to the RES pin while this LSI operates by inputting a mode specified in table 29.3 to the FWE and MD2 to MD0 pins, the mode setup time is defined by tMDS2. If a signal other than the combination of signals specified in table 29.3 (undefined mode) is input to the FWE and MD2 to MD0 pins, the mode setup time is defined by tMSD1. See section 29.6.2, Notes on Mode Pin Input. 2. The RES, NMI, and IRQ7-IRQ0 signals are asynchronous inputs, but when the setup times shown here are provided, the signals are considered to have been changed at clock fall. If the setup times are not provided, recognition is delayed until the next clock rise or fall. 3. The guaranteed operating range of power supply PVCC1 in the MCU expanded modes is only PVCC1 = 3.3 V 0.3 V. Do not use a voltage outside this range. Rev. 5.00 Feb. 24, 2010 Page 840 of 950 REJ09B0177-0500 29. Electrical Characteristics VOH CK tRESS tRESS tRESW VIH = VCC - 0.5 V VIH = VCC - 0.5 V VIL = 0.5 V VIL = 0.5 V tMD0 VIH = VCC - 0.5 V MD2-0 VIL = 0.5 V Note: pin is controlled by VIL and VIH shown above. Figure 29.5 Reset Input Timing CK VOL VOL tNMIH VIH = VCC - 0.5 V tNMIS VIH = VCC - 0.5 V NMI edge VIL = 0.5 V VIL = 0.5 V tIRQEH tIRQES VIH VIL tIRQLS level VIL Note: NMI pin is controlled by VIL and VIH shown above. Figure 29.6 Interrupt Signal Input Timing CK VOH tIRQOD tIRQOD VOH VOL Figure 29.7 Interrupt Signal Output Timing Rev. 5.00 Feb. 24, 2010 Page 841 of 950 REJ09B0177-0500 29. Electrical Characteristics VOH VOH VOH CK tBRQS VOL tBRQS VOL VIH (input) tBACKD2 tBACKD1 VOH VOL (output) tBZD , , Hi-Z , tBZD A21-A0, D15-D0 Hi-Z Figure 29.8 Bus Right Release Timing 29.3.4 Bus Timing Table 29.9 shows bus timing. Table 29.9 Bus Timing Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. Item Symbol Min Max Unit Figures Address delay time tAD -- 35 ns Figures 29.9, CS delay time 1 tCSD1 -- 30 ns 29.10 CS delay time 2 tCSD2 -- 30 ns Read strobe delay time 1 tRSD1 -- 30 ns Read strobe delay time 2 tRSD2 -- 30 ns Read data setup time tRDS 15 -- ns Read data hold time tRDH 0 -- ns Write strobe delay time 1 tWSD1 -- 30 ns Write strobe delay time 2 tWSD2 -- 30 ns Write data delay time tWDD -- 30 ns Write data hold time tWDH tcyc x m -- ns WAIT setup time tWTS 15 -- ns WAIT hold time tWTH 0 -- ns Read data access time tACC tcyc x (n+1.5)-39 -- ns Figures 29.9, Access time from read strobe tOE tcyc x (n+1.0)-39 -- ns 29.10 Write address setup time tAS 0 -- ns Write address hold time tWR 5 -- ns Legend: n: Number of waits m = 1: CS assertion extension cycle m = 0: Normal cycle (CS assertion non-extension cycle) Rev. 5.00 Feb. 24, 2010 Page 842 of 950 REJ09B0177-0500 Figure 29.11 29. Electrical Characteristics [Operating precautions] The guaranteed operating range of power supply PVCC1 in the MCU expanded modes is only PVCC1 = 3.3 V 0.3 V. Do not use a voltage outside this range. T1 T2 VOH CK VOL tAD A21-A0 tCSD2 tCSD1 tRSD1 tOE tRSD2 (read) tACC tRDS tRDH D15-D0 (read) tWSD1 (write) tWSD2 tWR tAS tWDD tWDH D15-D0 (write) Note: tRDH: Specified from the negate timing of A21-A0, , or , whichever is first. Figure 29.9 Basic Cycle (No Waits) Rev. 5.00 Feb. 24, 2010 Page 843 of 950 REJ09B0177-0500 29. Electrical Characteristics T1 TW T2 VOH CK VOL tAD A21-A0 tCSD2 tCSD1 tRSD1 tRSD2 tOE (read) tRDH tRDS tACC D15-D0 (read) tWSD2 tWSD1 (write) tWR tAS tWDD tWDH D15-D0 (write) Note: tRDH: Specified from the negate timing of A21-A0, , or , whichever is first. Figure 29.10 Basic Cycle (One Software Wait) Rev. 5.00 Feb. 24, 2010 Page 844 of 950 REJ09B0177-0500 29. Electrical Characteristics T1 TW TW TWO T2 CK A21-A0 (read) D15-D0 (read) (write) D15-D0 (write) tWTS tWTH tWTS tWTH Note: tRDH: Specified from the negate timing of A21-A0, , or , whichever is first. Figure 29.11 Basic Cycle (Two Software Waits + Waits by WAIT Signal) 29.3.5 Advanced Timer Unit Timing and Advance Pulse Controller Timing Table 29.10 shows advanced timer unit timing and advanced pulse controller timing. Table 29.10 Advanced Timer Unit Timing and Advanced Pulse Controller Timing Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. Item Symbol Min Max Unit Figures Output compare output delay time tTOCD -- 100 ns Figure 29.12 Input capture input setup time tTICS 24 -- ns PULS output delay time tPLSD - 100 ns Timer clock input setup time tTCKS 24 -- ns Timer clock pulse width (single edge specified) tTCKWH/L 1.5 -- tcyc Timer clock pulse width (both edges specified) tTCKWH/L 2.5 -- tcyc Figure 29.13 Rev. 5.00 Feb. 24, 2010 Page 845 of 950 REJ09B0177-0500 29. Electrical Characteristics VOH CK VOL VOL tTOCD Timer output tTICS Input capture input PULS output tPLSD Figure 29.12 ATU Input/Output Timing and APC Output Timing CK VOL VOL tTCKS tTCKS TCLKA, TCLKB tTCKWL tTCKWH Figure 29.13 ATU Clock Input Timing 29.3.6 I/O Port Timing Table 29.11 shows I/O port timing. Table 29.11 I/O Port Timing Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. Item Symbol Min Max Unit Figures Port output data delay time tPWD -- 100 ns Figure 29.14 Port input hold time tPRH 30 -- ns Port input setup time tPRS 30 -- ns [Operating precautions] The guaranteed operating range of power supply PVCC1 in MCU single-chip mode is only PVCC1 = 5.0 V 0.5 V. Do not use a voltage outside this range. Rev. 5.00 Feb. 24, 2010 Page 846 of 950 REJ09B0177-0500 29. Electrical Characteristics CK tPRS tPRH Port (read) tPWD Port (write) Figure 29.14 I/O Port Input/Output timing 29.3.7 Watchdog Timer Timing Table 29.12 shows watchdog timer timing. Table 29.12 Watchdog Timer Timing Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. Item Symbol Min Max Unit Figures WDTOVF delay time tWOVD -- 100 ns Figure 29.15 CK VOH VOH tWOVD tWOVD Figure 29.15 Watchdog Timer Timing Rev. 5.00 Feb. 24, 2010 Page 847 of 950 REJ09B0177-0500 29. Electrical Characteristics 29.3.8 Serial Communication Interface Timing Table 29.13 shows serial communication interface timing. Table 29.13 Serial Communication Interface Timing Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. Item Symbol Min Max Unit Figures Clock cycle tscyc 4 -- tcyc Figure 29.16 Clock cycle (clock sync) tscyc 6 -- tcyc Clock pulse width tsckw 0.4 0.6 tscyc Input clock rise time tsckr -- 1.5 tcyc Input clock fall time tsckf -- 1.5 tcyc Transmit data delay time tTxD -- 100 ns Transmit data setup time tRxS 100 -- ns Transmit data hold time tRxH 100 -- ns tsckr tsckw VIH SCK0-SCK4 VIH tsckf VIH VIL VIL VIH VIL tscyc Figure 29.16 SCI Input/Output Timing Rev. 5.00 Feb. 24, 2010 Page 848 of 950 REJ09B0177-0500 Figure 29.17 29. Electrical Characteristics tscyc SCK0 SCK4 (input/output) tTxD TxD0 TxD4 (transmit data) tRxS tRxH RxD0 RxD4 (receive data) SCI input/output timing (synchronous mode) VOH VOH CK tTxD TxD0 TxD4 (transmit data) tRxS tRxH RxD0 RxD4 (receive data) SCI input/output timing (asynchronous mode) Figure 29.17 SCI Input/Output Timing Rev. 5.00 Feb. 24, 2010 Page 849 of 950 REJ09B0177-0500 29. Electrical Characteristics 29.3.9 HCAN Timing Table 29.14 shows HCAN timing. Table 29.14 HCAN Timing Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. Item Symbol Min Max Unit Figures Transmit data delay time tHTxD -- 100 ns Figure 29.18 Transmit data setup time tHRxS 100 -- ns Transmit data hold time tHRxH 100 -- ns [Usage Note] The HCAN input signals are asynchronous, but changes in their state are considered to have occurred at the rising edge of the CK signal, as shown below. The rising edge of the CK signal is also used as the reference for changes in the HCAN output signals, as shown below. VOH VOH CK tHTxD HTxD0, HTxD1 (transmit data) tHRxS tHRxH HRxD0, HRxD1 (receive data) Figure 29.18 HCAN Input/Output Timing Rev. 5.00 Feb. 24, 2010 Page 850 of 950 REJ09B0177-0500 29. Electrical Characteristics 29.3.10 A/D Converter Timing Table 29.15 shows A/D converter timing. Table 29.15 A/D Converter Timing Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. CSK = 0: fop = 10 to 20MHz CSK = 1: fop = 10MHz Item Symbol Min Typ Max Min Typ Max Unit Figure External trigger input start delay time tTRGS 50 -- -- 50 -- -- ns Figure 29.19 A/D conversion time tCONV 259 -- 266 131 -- 134 tcyc Figure 29.20 A/D conversion start delay time tD 10 -- 17 6 -- 9 tcyc Input sampling time tSPL -- 64 -- -- 32 ADEND output delay time tADENDD -- -- 100 -- -- CK VOL tcyc 100 ns VOL input tTRGS ADCR (ADST = 1 set) Figure 29.19 External Trigger Input Timing Rev. 5.00 Feb. 24, 2010 Page 851 of 950 REJ09B0177-0500 29. Electrical Characteristics tCONV tD tSPL Write cycle A/D synchronization time (3 states) (up to 14 states) CK Address Analog input sampling signal ADF VOH VOH CK tADENDD tADENDD ADEND Figure 29.20 Analog Conversion Timing 29.3.11 MTAD Timing Table 29.16 shows MTAD timing Table 29.16 MTAD Timing Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. Item Symbol Min Max Unit Figures Delay time tLH -- 100 ns Figure 29.21 tHL -- 100 ns CK ADTO0A ADTO0B ADTO1A ADTO1B tLH tHL Figure 29.21 ADTO0A, 0B, 1A, 1B Output Timing Rev. 5.00 Feb. 24, 2010 Page 852 of 950 REJ09B0177-0500 29. Electrical Characteristics 29.3.12 H-UDI Timing Table 29.17 shows H-UDI timing. Table 29.17 H-UDI Timing Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. Item Symbol Min Max Unit Figures TCK clock cycle ttcyc 2 -- ttcyc Figure 29.22 TCK clock high-level width tTCKH 0.4 0.6 ttcyc TCK clock low-level width tTCKL 0.4 0.6 ttcyc TRST pulse width tTRSW 20 -- tcyc TRST setup time tTRSS 30 -- ns TMS setup time tTMSS 30 -- ns TMS hold time tTMSH 10 -- ns TDI setup time tTDIS 30 -- ns TDI hold time tTDIH 10 -- ns TDO delay time 1 tTDOD1 -- 30 ns TDO delay time 2 tTDOD2 -- 30 ns Figure 29.23 Figure 29.24 Figure 29.25 [Operating precautions] The H-UDI pins constitute a circuit requiring the voltage of VCC = 3.3 V 0.3 V. Comply with the input and output voltages specified in the DC characteristics, for operation. tTCKH VIH tTCKL VIH VIH TCK VIL VIL ttcyc Figure 29.22 H-UDI Clock Timing TCK VIL VIL tTRSS tTRSS TRST VIL VIL tTRSW Figure 29.23 H-UDI TRST Timing Rev. 5.00 Feb. 24, 2010 Page 853 of 950 REJ09B0177-0500 29. Electrical Characteristics VIH TCK VIH VIL tTMSS tTMSH tTDIS tTDIH TMS TDI tTDOD tTDOD TDO Figure 29.24 H-UDI Input/Output Timing VIH TCK VIL tTMSS tTMSH tTDIS tTDIH VIL VIL tTDOD2 tTDOD2 TMS TDI TDO Figure 29.25 H-UDI Input/Output Timing (Instruction Corresponding to IEEE1149.1 is Executed) Rev. 5.00 Feb. 24, 2010 Page 854 of 950 REJ09B0177-0500 29. Electrical Characteristics 29.3.13 AUD Timing Table 29.18 shows AUD timing. Table 29.18 AUD Timing Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. Item Symbol Min Max Unit Figures AUDRST pulse width (Branch trace) tAUDRSTW 10 -- tcyc Figure 29.26 AUDRST pulse width (RAM monitor) tAUDRSTW 5 -- tRMCYC AUDMD setup time (Branch trace) tAUDMDS 10 -- tcyc AUDMD setup time (RAM monitor) tAUDMDS 5 -- tRMCYC Branch trace clock cycle tBTCYC 1 1 tcyc Branch trace clock duty tBTCKW 40 60 % Branch trace data delay time tBTDD -- 40 ns Branch trace data hold time tBTDH 0 -- ns Branch trace SYNC delay time tBTSD -- 40 ns Branch trace SYNC hold time tBTSH 0 -- ns RAM monitor clock cycle tRMCYC 100 -- ns RAM monitor clock low pulse width tRMCKW 45 -- ns RAM monitor output data delay time tRMDD 7 tRMCYC - 20 ns RAM monitor output data hold time tRMDHD 5 -- ns RAM monitor input data setup time tRMDS 20 -- ns RAM monitor input data hold time tRMDH 5 -- ns RAM monitor SYNC setup time tRMSS 20 -- ns RAM monitor SYNC hold time tRMSH 5 -- ns Figure 29.27 Figure 29.28 Load conditions: AUDCK (branch trace): CL = 30 pF: otherwise CL = 100 pF AUDSYNC: CL = 100 pF AUDATA3 to AUDATA0: CL = 100 pF Rev. 5.00 Feb. 24, 2010 Page 855 of 950 REJ09B0177-0500 29. Electrical Characteristics tcyc CK (Branch trace) tRMCYC AUDCK (input) (RAM monitor) tAUDRSTW tAUDMDS AUDMD Figure 29.26 AUD Reset Timing tBTCKW tBTCYC AUDCK (output) tBTDD AUDATA3 to AUDATA0 (output) tBTDH tBTSH tBTSD (output) Figure 29.27 Branch Trace Timing tRMCYC tRMCKW AUDCK (input) tRMDD AUDATA3 to AUDATA0 (output) tRMDHD tRMDS tRMDH AUDATA3 to AUDATA0 (input) tRMSS (input) Figure 29.28 RAM Monitor Timing Rev. 5.00 Feb. 24, 2010 Page 856 of 950 REJ09B0177-0500 tRMSH 29. Electrical Characteristics 29.3.14 UBC Trigger Timing Table 29.19 shows UBC trigger timing. Table 29.19 UBC Trigger Timing Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. Item Symbol Min Max Unit Figures UBCTRG delay time tUBCTGD -- 35 ns Figure 29.29 VOH CK tUBCTGD UBCTRG Figure 29.29 UBC Trigger Timing 29.3.15 Synchronous Serial Communication Unit Timing Table 29.20 shows the synchronous serial communication unit (SSU) timing. Table 29.20 SSU Timing Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When programming or erasing the on-chip flash memory, Ta = -40C to 85C. Item Symbol Min Max Unit Figures Clock cycle tSUcyc 4 256 tcyc Figures Clock high-level pulse width tHI 0.3 -- tSUcyc 29.30 and 29.31 Clock low-level pulse width tLO 0.3 -- tSUcyc Clock rising time tRISE -- 20 ns Clock falling time tFALL -- 20 ns Data input setup time tSU 40 -- ns Data input hold time tH 10 -- ns SCS setup time tLEAD 0.3 -- tSUcyc SCS hold time tLAG 0.3 -- tSUcyc Data output delay time tOD -- 20 ns Data output hold time tOH - 30 -- ns Continuous transmission delay time tTD 0.3 -- tSUcyc Rev. 5.00 Feb. 24, 2010 Page 857 of 950 REJ09B0177-0500 29. Electrical Characteristics SCS(output) tTD tLEAD tHI SSCK(output) CPOS=1 tFALL tRISE tLAD tLO fHI SSCK(output) CPOS=0 tLO tSUcyc SSO(output) tOH tOD SSI(input) tSU tH Figure 29.30 SSU Timing (CPHS = 1) SCS(output) tTD tLEAD tHI SSCK(output) CPOS=1 tFALL tRISE tLO fHI SSCK(output) CPOS=0 tLO tSUcyc SSO(output) tOH tOD SSI(input) tSU tH Figure 29.31 SSU Timing (CPHS = 0) Rev. 5.00 Feb. 24, 2010 Page 858 of 950 REJ09B0177-0500 tLAD 29. Electrical Characteristics 29.3.16 Measuring Conditions for AC Characteristics Input reference levels Output reference level High level: VIH min. value, low level: VIL max. value High level: 2.0 V, Low level: 0.8 V IOL DUT output LSI output pin V CL VREF IOH Note: CL is a total value that includes the measuring instrument capacitance. The following CL values are used: 30 pF: 50 pF: 100 pF: 30 pF: CK, CS3-CS0, BREQ, BACK, IRQOUT, AUDCK A21-A0, D15-D0, RD, WRH, WRL, TDO AUDATA3-0, AUDSYNC All port pins other than the above, and peripheral module output pins. IOL and IOH are the condition for the IOL = 1.6 mA, IOH = 200 A. Figure 29.32 Output Test Circuit Rev. 5.00 Feb. 24, 2010 Page 859 of 950 REJ09B0177-0500 29. Electrical Characteristics 29.4 A/D Converter Characteristics Table 29.21 shows A/D converter characteristics. Table 29.21 A/D Converter Characteristics Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. CSK = 0: fop = 10 to 20 MHz CSK = 1: fop =10 MHz Item Min Typ Max Min Typ Max Unit Resolution 10 10 10 10 10 10 bit A/D conversion time -- -- 13.3 -- -- 13.4 s Analog input capacitance -- -- 20 -- -- 20 pF Permitted analog signal source -- impedance -- 3 -- -- 3 k Non-linear error -- 1.5*1 -- -- 1.5*1 -- 2.0* Offset error -- -- 1.5* 1 2 -- -- 2.0* Full-scale error -- -- 1.5* -- -- 2.0* Absolute error -- -- -- 0.5 -- 2.0* 2.5* 2 Notes: 1. Ta 105C 2. Ta > 105C Rev. 5.00 Feb. 24, 2010 Page 860 of 950 REJ09B0177-0500 1.5*1 LSB 2.0* 2 -- 1 LSB 2 2 Quantization error 1.5*1 2.0* 2 1 LSB 2.0* 2 -- -- 0.5 -- 2.0* LSB 1 2.5* 2 LSB 29. Electrical Characteristics 29.5 Flash Memory Characteristics 29.5.1 SH7058S Table 29.22 shows the flash memory characteristics. Table 29.22 Flash Memory Characteristics Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. Item Symbol Min Typ Max Unit tP -- 1 20 ms/128 bytes Erase time* * * tE -- 1.3 3.5 s/block Reprogramming count NWEC 100 -- -- Times 1 2 4 Programming time* * * 1 3 5 Notes: 1. 2. 3. 4. Use the on-chip programming/erasing routine for programming/erasure. When all 0 are programmed. 128 Kbytes of block The total reprogramming time (programming time + erasing time) is as follows. 20 s (typ), 35 s (reference value), 50 s (max) However, 90% of the values are within the reference value. 5. tE distributes focusing on near the typ. value. 29.5.2 SH7059 Table 29.23 shows the flash memory characteristics. Table 29.23 Flash Memory Characteristics Conditions: VCC = PLLVCC = 3.3 V 0.3 V, PVCC1 = 5.0 V 0.5 V/3.3 V 0.3 V, PVCC2 = 5.0 V 0.5 V, AVCC = 5.0 V 0.5 V, AVref = 4.5 V to AVCC, VSS = PLLVSS = AVSS = 0 V, Ta = -40C to 125C. When PVCC1 = 3.3 V 0.3 V, VCC = PVCC1. When writing or erasing on-chip flash memory, Ta = -40C to 85C. Item Symbol Min Typ Max Unit tP -- 1 20 ms/128 bytes Erase time* * * tE -- 2.5 7 s/block Reprogramming count NWEC 100 -- -- Times 1 2 Programming time* * * 4 1 3 5 Notes: 1. 2. 3. 4. Use the on-chip programming/erasing routine for programming/erasure. When all 0 are programmed. 256 Kbytes of block The total reprogramming time (programming time + erasing time) is as follows. 30 s (typ), 50 s (reference value), 75 s (max) However, 90% of the values are within the reference value. 5. tE distributes focusing on near the typ. value. Rev. 5.00 Feb. 24, 2010 Page 861 of 950 REJ09B0177-0500 29. Electrical Characteristics 29.6 Usage Note 29.6.1 Notes on Connecting External Capacitor for Current Stabilization This LSI includes an internal step-down circuit to automatically reduce the microprocessor power supply voltage to an appropriate level. Between this internal stepped-down power supply (VCL pin) and the VSS pin, an capacitor (0.33 to 0.47 F) for stabilizing the internal voltage. Connection of the external capacitor is shown in figure 29.33. The external capacitor should be located near the pin. Do not apply any power supply voltage to the VCL pin. External power-supply stabilizing capacitor One 0.33 to 0.47 F capacitor VCL VCL VSS VCL One 0.33 to 0.47 F capacitor One 0.33 to 0.47 F capacitor VSS VSS Note: Do not apply any power supply voltage to the VCL pin. Use multilayer ceramics capacitors (one 0.33 to 0.47 F capacitor for each VCL pin), which should be located near the pin. Figure 29.33 Connection of VCL Capacitor 29.6.2 Notes on Mode Pin Input This electrical characteristics are specified for the combination of mode pins (FWE, MD2 to MD0) specified in table 29.3. Characteristics of combinations other than those in table 29.3 cannot be guaranteed. When power is supplied and in hardware standby mode, mode setup time is determined by tMDS1. When power-on reset is performed only by the RES pin, mode setup time is differs according to the combination of input to the FWE and MD2 to MD0. When low is input to the RES pin with the pins FWE and MD2 to MD0 operated in mode specified in table 29.3, the mode setup time is determined by tMDS2. When combination which is not specified in table 29.3 is input, the mode setup time is determined by tMDS1. Table 29.24 Mode Pin Input Timing Item Symbol Min Typ Max Unit Remark Mode setup time 1 tMDS1 30 ms Figure 29.34 Mode setup time 2 tMDS2 10 tcyc Rev. 5.00 Feb. 24, 2010 Page 862 of 950 REJ09B0177-0500 29. Electrical Characteristics Vcc PLLVcc PVcc1 PVcc2 Vccmin tVCCS PVccmin HSTBY tOSC1 tOSC1 tMDS1 tMDS1 FWE, MD2 to MD0 tMDS1 or tMDS2 RES Figure 29.34 Mode Pin Input Timing Rev. 5.00 Feb. 24, 2010 Page 863 of 950 REJ09B0177-0500 29. Electrical Characteristics Rev. 5.00 Feb. 24, 2010 Page 864 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Appendix A On-chip peripheral module Registers A.1 Address On-chip peripheral module register addresses and bit names are shown in the following table. 16-bit and 32-bit registers are shown in two and four rows of 8 bits, respectively. Table A.1 Address Bit Names Register Name Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFD000 MCR -- -- -- -- -- -- -- -- HCAN0 MCR7 -- MCR5 -- -- MCR2 MCR1 MCR0 (Channel 0) GSR -- -- -- -- -- -- -- -- -- -- GSR5 GSR4 GSR3 GSR2 GSR1 GSR0 BCR1 TSEG13 TSEG12 TSEG11 TSEG10 -- TSEG22 TSEG21 TSEG20 -- -- SJW1 SJW0 -- -- -- BSP BCR0 -- -- -- -- -- -- -- -- BRP7 BRP6 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 IRR15 IRR14 IRR13 IRR12 IRR11 IRR10 IRR9 IRR8 IRR7 IRR6 IRR5 IRR4 IRR3 IRR2 IRR1 IRR0 IMR IMR15 IMR14 IMR13 IMR12 IMR11 IMR10 IMR9 IMR8 IMR7 IMR6 IMR5 IMR4 IMR3 IMR2 IMR1 IMR0 H'FFFFD00C TEC/ TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 H'FFFFD00D REC REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 H'FFFFD020 TXPR1 TXPR1[15] TXPR1[14] TXPR1[13] TXPR1[12] TXPR1[11] TXPR1[10] TXPR1[9] TXPR1[8] TXPR1[7] TXPR1[6] TXPR1[4] TXPR1[3] TXPR1[2] TXPR1[1] TXPR1[0] TXPR0 TXPR0[15] TXPR0[14] TXPR0[13] TXPR0[12] TXPR0[11] TXPR0[10] TXPR0[9] TXPR0[8] TXPR0[7] TXPR0[6] TXPR0[4] TXPR0[3] TXPR0[2] TXPR0[1] -- TXCR1 TXCR1[15] TXCR1[14] TXCR1[13] TXCR1[12] TXCR1[11] TXCR1[10] TXCR1[9] TXCR1[8] TXCR1[7] TXCR1[6] TXCR1[4] TXCR1[3] TXCR1[2] TXCR1[1] TXCR1[0] TXCR0 TXCR0[15] TXCR0[14] TXCR0[13] TXCR0[12] TXCR0[11] TXCR0[10] TXCR0[9] TXCR0[8] TXCR0[7] TXCR0[6] TXCR0[4] TXCR0[3] TXCR0[2] TXCR0[1] -- H'FFFFD001 H'FFFFD002 H'FFFFD003 H'FFFFD004 H'FFFFD005 H'FFFFD006 H'FFFFD007 H'FFFFD008 IRR H'FFFFD009 H'FFFFD00A H'FFFFD00B H'FFFFD021 H'FFFFD022 H'FFFFD023 H'FFFFD028 H'FFFFD029 H'FFFFD02A H'FFFFD02B TXPR1[5] TXPR0[5] TXCR1[5] TXCR0[5] Rev. 5.00 Feb. 24, 2010 Page 865 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 H'FFFFD030 TXACK1 TXACK1 [15] TXACK1 [14] TXACK1 [13] TXACK1 [12] TXACK1 [11] TXACK1 [10] TXACK1 [9] TXACK1 [8] TXACK1[7] TXACK1[6] TXACK1[5] TXACK1[4] TXACK1[3] TXACK1[2] TXACK1[1] TXACK1[0] TXACK0 TXACK0 TXACK0 TXACK0 TXACK0 TXACK0 TXACK0 TXACK0 [15] [14] [13] [12] [11] [10] [9] [8] TXACK0[7] TXACK0[6] TXACK0[5] TXACK0[4] TXACK0[3] TXACK0[2] TXACK0[1] TXACK0[0] ABACK1 [15] ABACK1 [14] ABACK1 [12] ABACK1 [11] H'FFFFD031 H'FFFFD032 TXACK0 H'FFFFD033 H'FFFFD038 ABACK1 H'FFFFD039 H'FFFFD03A ABACK0 ABACK0 [15] ABACK0 [14] ABACK0 [13] ABACK0 [12] ABACK0 [11] ABACK0 [10] ABACK0 [9] ABACK0 [8] RXPR1 RXPR1[15] RXPR1[7] RXPR1[6] RXPR1[4] RXPR1[3] RXPR1[1] RXPR1[0] RXPR0 RXPR0[15] RXPR0[14] RXPR0[13] RXPR0[12] RXPR0[11] RXPR0[10] RXPR0[9] RXPR0[8] RXPR0 [7] RXPR0 [6] RXPR0[4] RXPR0 [3] RXPR0 [0] H'FFFFD043 H'FFFFD048 ABACK1 [9] ABACK1 [8] ABACK0 [7] ABACK0 [6] ABACK0 [5] ABACK0 [4] ABACK0 [3] ABACK0 [2] ABACK0 [1] -- H'FFFFD041 H'FFFFD042 ABACK1 [10] ABACK1 [7] ABACK1 [6] ABACK1 [5] ABACK1 [4] ABACK1 [3] ABACK1 [2] ABACK1 [1] ABACK1 [0] H'FFFFD03B H'FFFFD040 ABACK1 [13] Bit 0 RFPR1 H'FFFFD049 RXPR1[14] RXPR1[13] RXPR1[5] RXPR0[5] RXPR1[12] RXPR1[11] RXPR1[10] RXPR1[9] RXPR1[2] RXPR0[2] RXPR0[1] RFPR1 [15] RFPR1 [14] RFPR1 [13] RFPR1 [12] RFPR1 [11] RFPR1 [10] RFPR1[9] RFPR1[0] RFPR0 [15] RFPR0 [14] RFPR0 [13] RFPR0 [12] RFPR0 [11] RFPR0 [10] RFPR0 [9] RFPR0 [8] RFPR0[7] RFPR0[6] RFPR0[5] RFPR0[4] RFPR0[3] RFPR0[2] RFPR0[1] RFPR0[0] MBIMR1 [15] MBIMR1 [14] MBIMR1 [13] MBIMR1 [12] MBIMR1 [11] MBIMR1 [10] MBIMR1 [9] MBIMR1 [8] MBIMR1[7] MBIMR1[6] MBIMR1[5] MBIMR1[4] MBIMR1[3] MBIMR1[2] MBIMR1[1] MBIMR1[0] MBIMR0 [15] MBIMR0 [14] MBIMR0 [12] MBIMR0 [11] MBIMR0[7] MBIMR0[6] MBIMR0[5] MBIMR0[4] MBIMR0[3] MBIMR0[2] MBIMR0[1] MBIMR0[0] UMSR1 UMSR1 [15] UMSR1 [14] UMSR1[7] UMSR1[6] UMSR1[1] UMSR1[0] UMSR0 UMSR0 [15] UMSR0 [14] UMSR0 [13] UMSR0 [12] UMSR0 [11] UMSR0 [10] UMSR0 [9] UMSR0 [8] H'FFFFD05B UMSR0[7] UMSR0[6] UMSR0[5] UMSR0[4] UMSR0[3] UMSR0[2] UMSR0[1] UMSR0[0] H'FFFFD05C-7F -- -- -- -- -- -- -- -- RFPR0 H'FFFFD04B H'FFFFD050 MBIMR1 H'FFFFD051 H'FFFFD052 MBIMR0 H'FFFFD053 H'FFFFD058 H'FFFFD059 H'FFFFD05A RFPR1[6] Rev. 5.00 Feb. 24, 2010 Page 866 of 950 REJ09B0177-0500 RFPR1[5] MBIMR0 [13] RFPR1[4] RFPR1[3] RFPR1[2] RFPR1[8] RFPR1[1] H'FFFFD04A RFPR1[7] RXPR1[8] MBIMR0 [10] MBIMR0 [9] MBIMR0 [8] UMSR1 [13] UMSR1 [12] UMSR1 [11] UMSR1 [10] UMSR1 [9] UMSR1[5] UMSR1[4] UMSR1[3] UMSR1[2] UMSR1 [8] Module HCAN0 (Channel 0) Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFD080 TCNTR TCNTR15 TCNTR14 TCNTR13 TCNTR12 TCNTR11 TCNTR10 TCNTR9 TCNTR8 HCAN0 TCNTR7 TCNTR6 TCNTR5 TCNTR4 TCNTR3 TCNTR2 TCNTR1 TCNTR0 (Channel 0) TCR15 TCR14 TCR13 TCR12 TCR11 TCR10 TCR9 -- TCR7 -- TCR5 TCR4 TCR3 TCR2 TCR1 TCR0 -- -- -- -- -- -- -- -- -- -- -- TSR4 TSR3 TSR2 TSR1 TSR0 TDCR15 TDCR14 TDCR13 TDCR12 TDCR11 TDCR10 TDCR9 TDCR8 TDCR7 TDCR6 TDCR5 TDCR4 TDCR3 TDCR2 TDCR1 TDCR0 LOSR15 LOSR14 LOSR13 LOSR12 LOSR11 LOSR10 LOSR9 LOSR8 LOSR7 LOSR6 LOSR5 LOSR4 LOSR3 LOSR2 LOSR1 LOSR0 -- -- -- -- -- -- -- -- -- -- -- -- ICCR0_cc3 ICCR0_cc2 ICCR0_cc1 ICCR0_cc 0 ICR0_tm ICR0_tm ICR0_tm ICR0_tm ICR0_tm ICR0_tm 15 14 13 12 11 10 H'FFFFD081 H'FFFFD082 TCR H'FFFFD083 H'FFFFD084 TSR H'FFFFD085 H'FFFFD086 TDCR H'FFFFD087 H'FFFFD088 LOSR H'FFFFD089 H'FFFFD08A ICR0_cc H'FFFFD08B H'FFFFD08C ICR0_tm H'FFFFD08D H'FFFFD08E ICR0_tm7 ICR0_tm6 ICR0_tm5 ICR0_tm4 ICR0_tm3 ICR0_tm2 ICR0_tm1 ICR0_tm0 ICR1[15] ICR1[14] ICR1[13] ICR1[12] ICR1[11] ICR1[10] ICR1[9] ICR1[8] ICR1[7] ICR1[6] ICR1[5] ICR1[4] ICR1[3] ICR1[2] ICR1[1] ICR1[0] TCMR0 TCMR0 [15] TCMR0 [14] TCMR0 [13] TCMR0 [12] TCMR0 [11] TCMR0 [10] TCMR0 [9] TCMR0 [8] TCMR0[7] TCMR0[6] TCMR0[5] TCMR0[4] TCMR0[3] TCMR0[2] TCMR0[1] TCMR0[0] TCMR1 TCMR1 [15] TCMR1 [14] TCMR1 [13] TCMR1 [12] TCMR1 [11] TCMR1 [10] TCMR1 [9] TCMR1 [8] TCMR1[7] TCMR1[6] TCMR1[5] TCMR1[4] TCMR1[3] TCMR1[2] TCMR1[1] TCMR1[0] TCMR2 TCMR2 [15] TCMR2 [14] TCMR2 [13] TCMR2 [12] TCMR2 [11] TCMR2 [10] TCMR2 [9] TCMR2 [8] TCMR2[7] TCMR2[6] TCMR2[5] TCMR2[4] TCMR2[3] TCMR2[2] TCMR2[1] TCMR2[0] CCR -- -- -- -- -- -- -- -- -- -- -- -- CCR3 CCR2 CCR1 CCR0 CMAX -- -- -- -- -- -- -- -- -- -- -- -- CMAX3 CMAX2 CMAX1 CMAX0 TMR -- -- -- -- -- -- -- -- -- -- -- -- TMR3 TMR2 TMR1 -- CCR-buf -- -- -- -- -- -- -- -- -- -- -- -- CCRbuf3 CCRbuf2 CCRbuf1 CCRbuf0 -- -- -- -- -- -- -- -- -- -- -- -- ICR0buf3 ICR0buf2 ICR0buf1 ICR0buf0 -- -- -- -- -- -- -- -- H'FFFFD091 H'FFFFD092 H'FFFFD093 H'FFFFD094 H'FFFFD095 H'FFFFD096 H'FFFFD097 H'FFFFD098 H'FFFFD099 H'FFFFD09A H'FFFFD09B H'FFFFD09C H'FFFFD09D H'FFFFD09E ICR0-buf H'FFFFD09F H'FFFFD0A0-FF ICR0_tm8 ICR1 H'FFFFD08F H'FFFFD090 ICR0_tm9 -- -- Rev. 5.00 Feb. 24, 2010 Page 867 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation H'FFFFD100 MB0[0], [1]* 1 H'FFFFD101 H'FFFFD102 MB0[2], [3] H'FFFFD103 H'FFFFD104 MB0[4], [5] H'FFFFD105 H'FFFFD106 MB0[6] H'FFFFD107 H'FFFFD108 MB0[7], [8]* 1 H'FFFFD109 H'FFFFD10A H'FFFFD120 H'FFFFD12F HCAN0 STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] (Channel 0) EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MSG_DATA_0 MSG_DATA_7 STDID_LA FM[10] STDID_LAF STDID_LA M[3] FM[2] MB0[17], [18] STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] STDID_LAF STDID_LAF -- M[1] M[0] -- EXTID_LAF EXTID_LA M[17] FM[16] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] -- -- -- -- -- -- -- STDID[10] STDID[9] STDID[8] STDID[7] STDID[6] STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE MB1[2], [3] EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] MB1[4], [5] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MB1[0], [1]* 1 MB1[6] MB1[7], [8]* 1 MSG_DATA_0 MSG_DATA_1 MB1[9], [10] MSG_DATA_2 MB1[11], [12] MSG_DATA_4 MSG_DATA_3 H'FFFFD12D H'FFFFD12E STDID[4] -- H'FFFFD12B H'FFFFD12C STDID[5] MB0[15], [16] H'FFFFD129 H'FFFFD12A STDID[6] MSG_DATA_5 H'FFFFD127 H'FFFFD128 Module STDID[7] MSG_DATA_6 H'FFFFD125 H'FFFFD126 Bit 0 STDID[8] MB0[13], [14] H'FFFFD123 H'FFFFD124 Bit 1 STDID[9] MSG_DATA_3 H'FFFFD121 H'FFFFD122 Bit 2 STDID[10] MSG_DATA_4 H'FFFFD113 H'FFFFD114-1F Bit 3 -- MB0[11], [12] H'FFFFD111 H'FFFFD112 Bit 4 MSG_DATA_1 H'FFFFD10F H'FFFFD110 Bit 5 MSG_DATA_2 H'FFFFD10D H'FFFFD10E Bit 6 MB0[9], [10] H'FFFFD10B H'FFFFD10C Bit 7 MSG_DATA_5 MB1[13], [14] MSG_DATA_6 MSG_DATA_7 Rev. 5.00 Feb. 24, 2010 Page 868 of 950 REJ09B0177-0500 -- -- -- -- STDID[5] STDID[4] HCAN0 EXTID[17] EXTID[16] (Channel 0) Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 Bit 6 Bit 5 H'FFFFD130 MB1[15], [16] -- STDID_LA FM[10] STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA HCAN0 M[9] M[8] M[7] M[6] M[5] FM[4] (Channel 0) H'FFFFD131 H'FFFFD132 STDID_LAF STDID_LA M[3] FM[2] MB1[17], [18] H'FFFFD133 -- -- -- -- -- -- STDID[8] STDID[7] STDID[6] STDID[5] STDID[4] HCAN0 STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] (Channel 0) MB2[2], [3] EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] MB2[4], [5] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MB2[6] MB2[7], [8]* 1 MSG_DATA_1 MSG_DATA_2 MB2[11], [12] MSG_DATA_4 MB2[13], [14] MSG_DATA_6 MSG_DATA_3 MSG_DATA_5 H'FFFFD14F H'FFFFD150 MSG_DATA_7 MB2[15], [16] H'FFFFD151 H'FFFFD152 MB2[17], [18] MB3[0], [1]* H'FFFFD161 MB3[2], [3] H'FFFFD163 H'FFFFD164 H'FFFFD165 STDID_LA FM[10] STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] STDID_LAF STDID_LAF -- M[1] M[0] -- EXTID_LAF EXTID_LA M[17] FM[16] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFD154-5F H'FFFFD162 -- STDID_LAF STDID_LA M[3] FM[2] H'FFFFD153 H'FFFFD160 MSG_DATA_0 MB2[9], [10] H'FFFFD14D H'FFFFD14E EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] -- H'FFFFD14B H'FFFFD14C EXTID_LAF EXTID_LA M[17] FM[16] STDID[9] H'FFFFD149 H'FFFFD14A Module -- H'FFFFD147 H'FFFFD148 Bit 0 STDID[10] H'FFFFD145 H'FFFFD146 -- Bit 1 -- 1 H'FFFFD143 H'FFFFD144 STDID_LAF STDID_LAF -- M[1] M[0] Bit 2 -- MB2[0], [1]* H'FFFFD141 H'FFFFD142 Bit 3 EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFD134-3F H'FFFFD140 Bit 4 MB3[4], [5] 1 -- -- -- -- -- -- -- -- -- STDID[10] STDID[9] STDID[8] STDID[7] STDID[6] STDID[5] STDID[4] STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] (Channel 0) EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] -- HCAN0 Rev. 5.00 Feb. 24, 2010 Page 869 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFD166 MB3[6] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] HCAN0 TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] H'FFFFD167 H'FFFFD168 MB3[7], [8]* 1 H'FFFFD16A MB3[9], [10] MSG_DATA_2 MB3[11], [12] MSG_DATA_4 H'FFFFD16B H'FFFFD16C MSG_DATA_3 H'FFFFD16D H'FFFFD16E MSG_DATA_5 MB3[13], [14] H'FFFFD16F H'FFFFD170 MB3[15], [16] MB3[17], [18] MB4[0], [1]* 1 -- -- -- -- -- -- STDID[9] STDID[8] STDID[7] STDID[6] STDID[5] STDID[4] STDID[0] RTR IDE EXTID[17] EXTID[16] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] MB4[4], [5] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MB4[6] MB4[7], [8]* 1 MSG_DATA_0 MSG_DATA_1 MB4[9], [10] MSG_DATA_2 MB4[11], [12] MSG_DATA_4 MB4[13], [14] MSG_DATA_6 MSG_DATA_3 MSG_DATA_5 H'FFFFD18F H'FFFFD191 -- STDID[10] STDID[1] H'FFFFD18D H'FFFFD190 -- -- EXTID[13] H'FFFFD18B H'FFFFD18E EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] STDID[2] H'FFFFD189 H'FFFFD18C EXTID_LAF EXTID_LA M[17] FM[16] EXTID[14] H'FFFFD187 H'FFFFD18A -- STDID[3] H'FFFFD185 H'FFFFD188 STDID_LAF STDID_LAF -- M[1] M[0] EXTID[15] H'FFFFD183 H'FFFFD186 STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] MB4[2], [3] H'FFFFD181 H'FFFFD184 STDID_LA FM[10] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFD174-7F H'FFFFD182 -- STDID_LAF STDID_LA M[3] FM[2] H'FFFFD173 H'FFFFD180 MSG_DATA_6 MSG_DATA_7 H'FFFFD171 H'FFFFD172 MSG_DATA_0 MSG_DATA_1 H'FFFFD169 MSG_DATA_7 MB4[15], [16] -- STDID_LA FM[10] STDID_LAF STDID_LA M[3] FM[2] Rev. 5.00 Feb. 24, 2010 Page 870 of 950 REJ09B0177-0500 STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] STDID_LAF STDID_LAF -- M[1] M[0] -- EXTID_LAF EXTID_LA M[17] FM[16] (Channel 0) Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 H'FFFFD192 MB4[17], [18] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA HCAN0 M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] (Channel 0) H'FFFFD193 -- STDID[10] STDID[9] STDID[8] STDID[7] STDID[6] STDID[5] STDID[4] STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] MB5[4], [5] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] MB5[6] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MB5[0], [1]* MB5[2], [3] MB5 [7], [8]* 1 MB5[13], [14] MSG_DATA_6 MSG_DATA_5 MSG_DATA_7 MB5[15], [16] MB5[17], [18] EXTID_LAF EXTID_LA M[17] FM[16] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] -- -- -- -- -- -- -- -- STDID[9] STDID[8] STDID[7] STDID[6] STDID[5] STDID[4] HCAN0 STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] (Channel 0) EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] MB6[4], [5] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] MB6[6] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MB6[2], [3] H'FFFFD1C7 H'FFFFD1C9 -- STDID[10] H'FFFFD1C5 H'FFFFD1C8 STDID_LAF STDID_LAF -- M[1] M[0] -- 1 H'FFFFD1C3 H'FFFFD1C6 STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] -- MB6[0], [1]* H'FFFFD1C1 H'FFFFD1C4 STDID_LA FM[10] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFD1B4-BF H'FFFFD1C2 -- STDID_LAF STDID_LA M[3] FM[2] H'FFFFD1B3 H'FFFFD1C0 -- MSG_DATA_2 MSG_DATA_4 H'FFFFD1B1 H'FFFFD1B2 -- MSG_DATA_0 MB5[11], [12] H'FFFFD1AF H'FFFFD1B0 -- MSG_DATA_3 H'FFFFD1AD H'FFFFD1AE Module MSG_DATA_1 MB5 [9], [10] H'FFFFD1AB H'FFFFD1AC Bit 0 -- H'FFFFD1A9 H'FFFFD1AA Bit 1 -- H'FFFFD1A7 H'FFFFD1A8 Bit 2 -- H'FFFFD1A5 H'FFFFD1A6 Bit 3 -- H'FFFFD1A3 H'FFFFD1A4 Bit 4 -- 1 H'FFFFD1A1 H'FFFFD1A2 Bit 5 EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFD194-9F H'FFFFD1A0 Bit 6 1 MB6[7], [8]* MSG_DATA_0 MSG_DATA_1 Rev. 5.00 Feb. 24, 2010 Page 871 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 H'FFFFD1CA MB6[9], [10] MSG_DATA_2 HCAN0 MSG_DATA_3 (Channel 0) H'FFFFD1CB H'FFFFD1CC MB6[11], [12] MSG_DATA_4 MB6[13], [14] MSG_DATA_6 H'FFFFD1CD H'FFFFD1CE MB6[15], [16] MB6[17], [18] EXTID_LAF EXTID_LA M[17] FM[16] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] STDID[10] STDID[9] STDID[8] STDID[7] STDID[6] STDID[2] STDID[1] STDID[0] RTR IDE MB7[2], [3] EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] MB7[4], [5] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] MB7[6] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MB7[7], [8]* 1 -- -- -- -- STDID[5] STDID[4] HCAN0 EXTID[17] EXTID[16] (Channel 0) MSG_DATA_0 MSG_DATA_1 MB7[9], [10] MSG_DATA_2 MB7[11], [12] MSG_DATA_4 MB7[13], [14] MSG_DATA_6 MB7[15], [16] -- MSG_DATA_3 MSG_DATA_5 H'FFFFD1EF MSG_DATA_7 H'FFFFD1F1 H'FFFFD1F2 -- STDID[3] H'FFFFD1ED H'FFFFD1F0 STDID_LAF STDID_LAF -- M[1] M[0] -- MB7[0], [1]* H'FFFFD1EB H'FFFFD1EE Module STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] -- H'FFFFD1E9 H'FFFFD1EC STDID_LA FM[10] -- H'FFFFD1E7 H'FFFFD1EA Bit 0 -- H'FFFFD1E5 H'FFFFD1E8 Bit 1 -- H'FFFFD1E3 H'FFFFD1E6 Bit 2 -- 1 H'FFFFD1E1 H'FFFFD1E4 Bit 3 EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFD1D4-DF H'FFFFD1E2 -- STDID_LAF STDID_LA M[3] FM[2] H'FFFFD1D3 H'FFFFD1E0 Bit 4 MSG_DATA_7 H'FFFFD1D1 H'FFFFD1D2 Bit 5 MSG_DATA_5 H'FFFFD1CF H'FFFFD1D0 Bit 6 STDID_LA FM[10] STDID_LAF STDID_LA M[3] FM[2] MB7[17], [18] STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] STDID_LAF STDID_LAF -- M[1] M[0] -- EXTID_LAF EXTID_LA M[17] FM[16] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] H'FFFFD1F3 EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFD1F4-FF -- -- Rev. 5.00 Feb. 24, 2010 Page 872 of 950 REJ09B0177-0500 -- -- -- -- -- -- -- Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation H'FFFFD200 MB8[0], [1]* 1 H'FFFFD201 H'FFFFD202 MB8[2], [3] H'FFFFD203 H'FFFFD204 MB8[4], [5] H'FFFFD205 H'FFFFD206 MB8[6] H'FFFFD207 H'FFFFD208 MB8[7], [8]* 1 H'FFFFD209 H'FFFFD20A STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] (Channel 0) EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MSG_DATA_0 STDID_LA FM[10] STDID_LAF STDID_LA M[3] FM[2] MB8[17], [18] STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] STDID_LAF STDID_LAF -- M[1] M[0] -- EXTID_LAF EXTID_LA M[17] FM[16] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] MB9[0], [1]* 1 MB9[2], [3] MB9[4], [5] MB9[6] MB9[7], [8]* 1 -- -- -- -- -- -- -- -- STDID[10] STDID[9] STDID[8] STDID[7] STDID[6] STDID[5] -- STDID[4] STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MSG_DATA_0 MSG_DATA_1 MB9[9], [10] MSG_DATA_2 MSG_DATA_3 MB9[11], [12] MSG_DATA_4 MB9[13], [14] MSG_DATA_6 H'FFFFD22D H'FFFFD22F HCAN0 MSG_DATA_7 H'FFFFD22B H'FFFFD22E STDID[4] -- H'FFFFD229 H'FFFFD22C STDID[5] MB8[15], [16] H'FFFFD227 H'FFFFD22A STDID[6] MSG_DATA_5 H'FFFFD225 H'FFFFD228 Module STDID[7] MSG_DATA_6 H'FFFFD223 H'FFFFD226 Bit 0 STDID[8] MB8[13], [14] H'FFFFD221 H'FFFFD224 Bit 1 STDID[9] MSG_DATA_3 H'FFFFD214-1F H'FFFFD222 Bit 2 STDID[10] MSG_DATA_4 H'FFFFD213 H'FFFFD220 Bit 3 -- MB8[11], [12] H'FFFFD211 H'FFFFD212 Bit 4 MSG_DATA_1 H'FFFFD20F H'FFFFD210 Bit 5 MSG_DATA_2 H'FFFFD20D H'FFFFD20E Bit 6 MB8[9], [10] H'FFFFD20B H'FFFFD20C Bit 7 MSG_DATA_5 MSG_DATA_7 Rev. 5.00 Feb. 24, 2010 Page 873 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 Bit 6 Bit 5 H'FFFFD230 MB9[15], [16] -- STDID_LA FM[10] STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA HCAN0 M[9] M[8] M[7] M[6] M[5] FM[4] (Channel 0) H'FFFFD231 H'FFFFD232 STDID_LAF STDID_LA M[3] FM[2] MB10[0], [1]* 1 H'FFFFD24E H'FFFFD24F H'FFFFD250 -- -- -- -- -- -- -- STDID[9] STDID[8] STDID[7] STDID[6] STDID[5] STDID[4] HCAN0 STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] (Channel 0) EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] MB10[4], [5] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MB10[6] MB10[7], [8]* 1 MSG_DATA_0 MSG_DATA_1 MB10[9], [10] MSG_DATA_2 MB10 [11], [12] MSG_DATA_4 MB10 [13],[14] MSG_DATA_6 MB10 [15], [16] -- MSG_DATA_3 H'FFFFD251 H'FFFFD252 -- STDID[10] EXTID[13] H'FFFFD24B H'FFFFD24D -- -- STDID[2] H'FFFFD249 H'FFFFD24C EXTID_LAF EXTID_LA M[17] FM[16] EXTID[14] H'FFFFD247 H'FFFFD24A MSG_DATA_5 MSG_DATA_7 STDID_LA FM[10] STDID_LAF STDID_LA M[3] FM[2] MB10 [17], [18] STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] STDID_LAF STDID_LAF -- M[1] M[0] -- EXTID_LAF EXTID_LA M[17] FM[16] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] H'FFFFD253 EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFD254-5F -- -- -- -- -- MB11 1 [0], [1]* -- STDID[10] STDID[9] STDID[8] STDID[7] STDID[6] STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE MB11 [2], [3] EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] MB11[4], [5] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] H'FFFFD260 H'FFFFD261 H'FFFFD262 H'FFFFD263 H'FFFFD264 H'FFFFD265 Module STDID[3] H'FFFFD245 H'FFFFD248 Bit 0 EXTID[15] H'FFFFD243 H'FFFFD246 -- Bit 1 MB10[2], [3] H'FFFFD241 H'FFFFD244 STDID_LAF STDID_LAF -- M[1] M[0] Bit 2 EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFD234-3F H'FFFFD242 Bit 3 EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] MB9[17], [18] H'FFFFD233 H'FFFFD240 Bit 4 Rev. 5.00 Feb. 24, 2010 Page 874 of 950 REJ09B0177-0500 -- -- -- -- STDID[5] STDID[4] HCAN0 EXTID[17] EXTID[16] (Channel 0) Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFD266 MB11[6] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] HCAN0 TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] H'FFFFD267 H'FFFFD268 MB11[7], [8]* 1 MB11[9], [10] MSG_DATA_2 MB11 [11], [12] MSG_DATA_4 MB11 [13], [14] MSG_DATA_6 MB11 [15], [16] -- H'FFFFD26B H'FFFFD26C H'FFFFD26D H'FFFFD26E H'FFFFD26F H'FFFFD270 MSG_DATA_3 MSG_DATA_5 MSG_DATA_7 H'FFFFD271 H'FFFFD272 MB12[0], [1]* 1 -- -- -- -- -- -- -- -- -- -- STDID[10] STDID[9] STDID[8] STDID[7] STDID[6] STDID[5] STDID[4] HCAN0 STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] (Channel 0) EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] MB12[4], [5] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MB12[6] H'FFFFD287 MB12[7], [8]* 1 MSG_DATA_0 MSG_DATA_1 H'FFFFD289 H'FFFFD28A MB12[9], H'FFFFD28B [10] MSG_DATA_3 H'FFFFD28C MB12 [11], [12] MSG_DATA_4 MB12 [13], [14] MSG_DATA_6 MB12 [15], [16] -- H'FFFFD28D H'FFFFD28E H'FFFFD28F H'FFFFD290 H'FFFFD291 EXTID_LAF EXTID_LA M[17] FM[16] EXTID[15] H'FFFFD285 H'FFFFD288 -- MB12[2], [3] H'FFFFD283 H'FFFFD286 STDID_LAF STDID_LAF -- M[1] M[0] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFD281 H'FFFFD284 STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] MB11 [17], [18] H'FFFFD274-7F H'FFFFD282 STDID_LA FM[10] STDID_LAF STDID_LA M[3] FM[2] H'FFFFD273 H'FFFFD280 MSG_DATA_0 MSG_DATA_1 H'FFFFD269 H'FFFFD26A (Channel 0) MSG_DATA_2 MSG_DATA_5 MSG_DATA_7 STDID_LA FM[10] STDID_LAF STDID_LA M[3] FM[2] STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] STDID_LAF STDID_LAF -- M[1] M[0] -- EXTID_LAF EXTID_LA M[17] FM[16] Rev. 5.00 Feb. 24, 2010 Page 875 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 H'FFFFD292 MB12 [17], [18] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA HCAN0 M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] (Channel 0) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'FFFFD293 EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFD294-9F -- -- -- -- -- MB13 1 [0], [1]* -- STDID[10] STDID[9] STDID[8] STDID[7] STDID[6] STDID[5] STDID[4] STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] MB13 [2], [3] EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] MB13[4], [5] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] MB13[6] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] H'FFFFD2A0 H'FFFFD2A1 H'FFFFD2A2 H'FFFFD2A3 H'FFFFD2A4 H'FFFFD2A5 H'FFFFD2A6 H'FFFFD2A7 H'FFFFD2A8 MB13[7], [8]* 1 H'FFFFD2A9 H'FFFFD2AA MB13[11], [12] MSG_DATA_4 MB13[13], [14] MSG_DATA_6 MSG_DATA_5 MSG_DATA_7 MB13[15], [16] H'FFFFD2B1 H'FFFFD2B2 MB13[17], [18] EXTID_LAF EXTID_LA M[17] FM[16] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] -- -- -- -- -- -- -- -- STDID[9] STDID[8] STDID[7] STDID[6] STDID[5] STDID[4] HCAN0 STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] (Channel 0) EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] MB14[4], [5] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] MB14[6] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MB14[2], [3] H'FFFFD2C7 H'FFFFD2C9 -- STDID[10] H'FFFFD2C5 H'FFFFD2C8 STDID_LAF STDID_LAF -- M[1] M[0] -- 1 H'FFFFD2C3 H'FFFFD2C6 STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] -- MB14[0], [1]* H'FFFFD2C1 H'FFFFD2C4 STDID_LA FM[10] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFD2B4-BF H'FFFFD2C2 -- STDID_LAF STDID_LA M[3] FM[2] H'FFFFD2B3 H'FFFFD2C0 MSG_DATA_0 MSG_DATA_3 H'FFFFD2AF H'FFFFD2B0 -- MSG_DATA_2 H'FFFFD2AD H'FFFFD2AE -- MSG_DATA_1 MB13[9], [10] H'FFFFD2AB H'FFFFD2AC -- Module MB14[7], [8]* 1 MSG_DATA_0 MSG_DATA_1 Rev. 5.00 Feb. 24, 2010 Page 876 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 H'FFFFD2CA MB14[9], [10] MSG_DATA_2 HCAN0 MSG_DATA_3 (Channel 0) H'FFFFD2CB H'FFFFD2CC MB14[11], [12] MSG_DATA_4 MB14[13], [14] MSG_DATA_6 H'FFFFD2CD H'FFFFD2CE MB14[15], [16] MB14[17], [18] EXTID_LAF EXTID_LA M[17] FM[16] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] STDID[10] STDID[9] STDID[8] STDID[7] STDID[6] STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE MB15[2], [3] EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] MB15[4], [5] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] MB15[6] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MB15[7], [8]* 1 -- -- -- STDID[5] STDID[4] HCAN0 EXTID[17] EXTID[16] (Channel 0) MSG_DATA_0 MSG_DATA_1 MB15[9], [10] MSG_DATA_2 MB15[11], [12] MSG_DATA_4 MB15[13], [14] MSG_DATA_6 MB15[15], [16] -- MSG_DATA_3 MSG_DATA_5 H'FFFFD2EF MSG_DATA_7 H'FFFFD2F1 H'FFFFD2F2 -- -- MB15[0], [1]* H'FFFFD2ED H'FFFFD2F0 STDID_LAF STDID_LAF -- M[1] M[0] -- H'FFFFD2EB H'FFFFD2EE Module STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] -- H'FFFFD2E9 H'FFFFD2EC STDID_LA FM[10] -- H'FFFFD2E7 H'FFFFD2EA Bit 0 -- H'FFFFD2E5 H'FFFFD2E8 Bit 1 -- H'FFFFD2E3 H'FFFFD2E6 Bit 2 -- 1 H'FFFFD2E1 H'FFFFD2E4 Bit 3 EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFD2D4-DF H'FFFFD2E2 -- STDID_LAF STDID_LA M[3] FM[2] H'FFFFD2D3 H'FFFFD2E0 Bit 4 MSG_DATA_7 H'FFFFD2D1 H'FFFFD2D2 Bit 5 MSG_DATA_5 H'FFFFD2CF H'FFFFD2D0 Bit 6 STDID_LA FM[10] STDID_LAF STDID_LA M[3] FM[2] MB15[17], [18] STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] STDID_LAF STDID_LAF -- M[1] M[0] -- EXTID_LAF EXTID_LA M[17] FM[16] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] H'FFFFD2F3 EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFD2F4-FF -- -- -- -- -- -- -- -- -- Rev. 5.00 Feb. 24, 2010 Page 877 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation H'FFFFD300 MB16[0], [1]* 1 H'FFFFD301 H'FFFFD302 MB16[2], [3] H'FFFFD303 H'FFFFD304 MB16[4], [5] H'FFFFD305 H'FFFFD306 MB16[6] H'FFFFD307 H'FFFFD308 MB16[7], [8]* 1 H'FFFFD309 H'FFFFD30A STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] (Channel 0) EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MSG_DATA_0 STDID_LA FM[10] STDID_LAF STDID_LA M[3] FM[2] MB16[17], [18] STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] STDID_LAF STDID_LAF -- M[1] M[0] -- EXTID_LAF EXTID_LA M[17] FM[16] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] MB17[0], [1]* 1 MB17[2], [3] MB17[4], [5] MB17[6] MB17[7], [8]* 1 -- -- -- -- -- -- -- -- -- -- STDID[10] STDID[9] STDID[8] STDID[7] STDID[6] STDID[5] STDID[4] HCAN0 STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] (Channel 0) EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MSG_DATA_0 MSG_DATA_1 MB17[9], [10] MSG_DATA_2 MSG_DATA_3 MB17[11], [12] MSG_DATA_4 MB17[13], [14] MSG_DATA_6 H'FFFFD32D H'FFFFD32F HCAN0 MSG_DATA_7 H'FFFFD32B H'FFFFD32E STDID[4] -- H'FFFFD329 H'FFFFD32C STDID[5] MB16[15], [16] H'FFFFD327 H'FFFFD32A STDID[6] MSG_DATA_5 H'FFFFD325 H'FFFFD328 Module STDID[7] MSG_DATA_6 H'FFFFD323 H'FFFFD326 Bit 0 STDID[8] MB16[13], [14] H'FFFFD321 H'FFFFD324 Bit 1 STDID[9] MSG_DATA_3 H'FFFFD314-1F H'FFFFD322 Bit 2 STDID[10] MSG_DATA_4 H'FFFFD313 H'FFFFD320 Bit 3 -- MB16[11], [12] H'FFFFD311 H'FFFFD312 Bit 4 MSG_DATA_1 H'FFFFD30F H'FFFFD310 Bit 5 MSG_DATA_2 H'FFFFD30D H'FFFFD30E Bit 6 MB16[9], [10] H'FFFFD30B H'FFFFD30C Bit 7 MSG_DATA_5 MSG_DATA_7 Rev. 5.00 Feb. 24, 2010 Page 878 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 Bit 6 Bit 5 H'FFFFD330 MB17[15], [16] -- STDID_LA FM[10] STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA HCAN0 M[9] M[8] M[7] M[6] M[5] FM[4] (Channel 0) H'FFFFD331 H'FFFFD332 STDID_LAF STDID_LA M[3] FM[2] MB17[17], [18] H'FFFFD333 MB18[0], [1]* 1 -- STDID[5] STDID[4] IDE EXTID[17] EXTID[16] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] MB18[4], [5] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MB18[6] MB18[7], [8]* 1 MSG_DATA_0 MSG_DATA_1 MB18[9], [10] MSG_DATA_2 MB18[11], [12] MSG_DATA_4 MB18[13], [14] MSG_DATA_6 MSG_DATA_3 MSG_DATA_5 MSG_DATA_7 MB18[15], [16] -- STDID_LA FM[10] STDID_LAF STDID_LA M[3] FM[2] MB18[17], [18] STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] STDID_LAF STDID_LAF -- M[1] M[0] -- EXTID_LAF EXTID_LA M[17] FM[16] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] -- -- -- -- -- -- -- STDID[10] STDID[9] STDID[8] STDID[7] STDID[6] STDID[5] STDID[4] STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] MB19[2], [3] EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] MB19[4], [5] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] MB19[0], [1]* H'FFFFD363 H'FFFFD365 -- STDID[6] EXTID[10] H'FFFFD361 H'FFFFD364 -- STDID[7] RTR H'FFFFD354-5F H'FFFFD362 -- EXTID[11] H'FFFFD353 H'FFFFD360 -- STDID[8] STDID[0] H'FFFFD351 H'FFFFD352 -- STDID[9] EXTID[12] H'FFFFD34F H'FFFFD350 -- STDID[10] STDID[1] H'FFFFD34D H'FFFFD34E -- -- EXTID[13] H'FFFFD34B H'FFFFD34C EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] STDID[2] H'FFFFD349 H'FFFFD34A Module EXTID_LAF EXTID_LA M[17] FM[16] EXTID[14] H'FFFFD347 H'FFFFD348 Bit 0 STDID[3] H'FFFFD345 H'FFFFD346 -- Bit 1 EXTID[15] H'FFFFD343 H'FFFFD344 STDID_LAF STDID_LAF -- M[1] M[0] Bit 2 MB18[2], [3] H'FFFFD341 H'FFFFD342 Bit 3 EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFD334-3F H'FFFFD340 Bit 4 1 -- -- Rev. 5.00 Feb. 24, 2010 Page 879 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFD366 MB19[6] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] HCAN0 TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] H'FFFFD367 H'FFFFD368 MB19[7], [8]* 1 MB19[9], [10] MSG_DATA_2 MB19[11], [12] MSG_DATA_4 H'FFFFD36B H'FFFFD36C MSG_DATA_3 H'FFFFD36D H'FFFFD36E MSG_DATA_5 MB19[13], [14] H'FFFFD36F H'FFFFD370 MB19[15], [16] MB19[17], [18] MB20[0], [1]* 1 -- -- -- -- -- -- -- STDID[9] STDID[8] STDID[7] STDID[6] STDID[5] STDID[4] HCAN0 STDID[0] RTR IDE EXTID[17] EXTID[16] (Channel 0) EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] MB20[4], [5] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MB20[6] MB20[7], [8]* 1 MSG_DATA_0 MSG_DATA_1 MB20[9], [10] MSG_DATA_2 MB20[11], [12] MSG_DATA_4 MB20[13], [14] MSG_DATA_6 MSG_DATA_3 MSG_DATA_5 H'FFFFD38F H'FFFFD391 -- STDID[10] STDID[1] H'FFFFD38D H'FFFFD390 -- -- EXTID[13] H'FFFFD38B H'FFFFD38E EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] STDID[2] H'FFFFD389 H'FFFFD38C EXTID_LAF EXTID_LA M[17] FM[16] EXTID[14] H'FFFFD387 H'FFFFD38A -- STDID[3] H'FFFFD385 H'FFFFD388 STDID_LAF STDID_LAF -- M[1] M[0] EXTID[15] H'FFFFD383 H'FFFFD386 STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] MB20[2], [3] H'FFFFD381 H'FFFFD384 STDID_LA FM[10] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFD374-7F H'FFFFD382 -- STDID_LAF STDID_LA M[3] FM[2] H'FFFFD373 H'FFFFD380 MSG_DATA_6 MSG_DATA_7 H'FFFFD371 H'FFFFD372 MSG_DATA_0 MSG_DATA_1 H'FFFFD369 H'FFFFD36A (Channel 0) MSG_DATA_7 MB20[15], [16] -- STDID_LA FM[10] STDID_LAF STDID_LA M[3] FM[2] Rev. 5.00 Feb. 24, 2010 Page 880 of 950 REJ09B0177-0500 STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] STDID_LAF STDID_LAF -- M[1] M[0] -- EXTID_LAF EXTID_LA M[17] FM[16] Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 H'FFFFD392 MB20[17], [18] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA HCAN0 M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] (Channel 0) H'FFFFD393 -- -- STDID[10] STDID[9] STDID[8] STDID[7] STDID[6] STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] MB21[4], [5] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] MB21[6] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MB21[0], [1]* MB21[2], [3] MB21[7], [8]* 1 MSG_DATA_4 MB21[13], [14] MSG_DATA_6 MB21[15], [16] MB21[17], [18] STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] STDID_LAF STDID_LAF -- M[1] M[0] -- EXTID_LAF EXTID_LA M[17] FM[16] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] -- -- -- -- -- -- -- -- -- STDID[10] STDID[9] STDID[8] STDID[7] STDID[6] STDID[5] STDID[4] HCAN0 STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] (Channel 0) EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] MB22[4], [5] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] MB22[6] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] 1 MB22[2], [3] H'FFFFD3C7 H'FFFFD3C9 STDID_LA FM[10] -- MB22[0], [1]* H'FFFFD3C5 H'FFFFD3C8 HCAN0 EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFD3C3 H'FFFFD3C6 -- STDID_LAF STDID_LA M[3] FM[2] H'FFFFD3C1 H'FFFFD3C4 STDID[4] EXTID[16] (Channel 0) MSG_DATA_7 H'FFFFD3B4-BF H'FFFFD3C2 STDID[5] EXTID[17] MSG_DATA_5 H'FFFFD3B3 H'FFFFD3C0 -- MSG_DATA_0 MB21[11], [12] H'FFFFD3B1 H'FFFFD3B2 -- MSG_DATA_3 H'FFFFD3AF H'FFFFD3B0 -- MSG_DATA_2 H'FFFFD3AD H'FFFFD3AE Module MSG_DATA_1 MB21[9], [10] H'FFFFD3AB H'FFFFD3AC Bit 0 -- H'FFFFD3A9 H'FFFFD3AA Bit 1 -- H'FFFFD3A7 H'FFFFD3A8 Bit 2 -- H'FFFFD3A5 H'FFFFD3A6 Bit 3 -- H'FFFFD3A3 H'FFFFD3A4 Bit 4 -- 1 H'FFFFD3A1 H'FFFFD3A2 Bit 5 EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFD394-9F H'FFFFD3A0 Bit 6 MB22[7], [8]* 1 MSG_DATA_0 MSG_DATA_1 Rev. 5.00 Feb. 24, 2010 Page 881 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 H'FFFFD3CA MB22[9], [10] MSG_DATA_2 HCAN0 MSG_DATA_3 (Channel 0) H'FFFFD3CB H'FFFFD3CC MB22[11], [12] MSG_DATA_4 MB22[13], [14] MSG_DATA_6 H'FFFFD3CD H'FFFFD3CE MB22[15], [16] MB22[17], [18] EXTID_LAF EXTID_LA M[17] FM[16] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] STDID[10] STDID[9] STDID[8] STDID[7] STDID[6] STDID[2] STDID[1] STDID[0] RTR IDE MB23[2], [3] EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] MB23[4], [5] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] MB23[6] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MB23[7], [8]* 1 -- -- -- -- STDID[5] STDID[4] HCAN0 EXTID[17] EXTID[16] (Channel 0) MSG_DATA_0 MSG_DATA_1 MB23[9], [10] MSG_DATA_2 MB23[11], [12] MSG_DATA_4 MB23[13], [14] MSG_DATA_6 MB23[15], [16] -- MSG_DATA_3 MSG_DATA_5 H'FFFFD3EF MSG_DATA_7 H'FFFFD3F1 H'FFFFD3F2 -- STDID[3] H'FFFFD3ED H'FFFFD3F0 STDID_LAF STDID_LAF -- M[1] M[0] -- MB23[0], [1]* H'FFFFD3EB H'FFFFD3EE Module STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] -- H'FFFFD3E9 H'FFFFD3EC STDID_LA FM[10] -- H'FFFFD3E7 H'FFFFD3EA Bit 0 -- H'FFFFD3E5 H'FFFFD3E8 Bit 1 -- H'FFFFD3E3 H'FFFFD3E6 Bit 2 -- 1 H'FFFFD3E1 H'FFFFD3E4 Bit 3 EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFD3D4-DF H'FFFFD3E2 -- STDID_LAF STDID_LA M[3] FM[2] H'FFFFD3D3 H'FFFFD3E0 Bit 4 MSG_DATA_7 H'FFFFD3D1 H'FFFFD3D2 Bit 5 MSG_DATA_5 H'FFFFD3CF H'FFFFD3D0 Bit 6 STDID_LA FM[10] STDID_LAF STDID_LA M[3] FM[2] MB23[17], [18] STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] STDID_LAF STDID_LAF -- M[1] M[0] -- EXTID_LAF EXTID_LA M[17] FM[16] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] H'FFFFD3F3 EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFD3F4-FF -- -- Rev. 5.00 Feb. 24, 2010 Page 882 of 950 REJ09B0177-0500 -- -- -- -- -- -- -- Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation H'FFFFD400 MB24[0], [1]* 1 H'FFFFD401 H'FFFFD402 MB24[2], [3] H'FFFFD403 H'FFFFD404 MB24[4], [5] H'FFFFD405 H'FFFFD406 MB24[6] H'FFFFD407 H'FFFFD408 MB24[7], [8]* 1 H'FFFFD409 H'FFFFD40A STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] (Channel 0) EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MSG_DATA_0 STDID_LA FM[10] STDID_LAF STDID_LA M[3] FM[2] MB24[17], [18] STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] STDID_LAF STDID_LAF -- M[1] M[0] -- EXTID_LAF EXTID_LA M[17] FM[16] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] MB25[0], [1]* 1 MB25[2], [3] MB25[4], [5] MB25[6] MB25[7], [8]* 1 -- -- -- -- -- -- -- -- STDID[10] STDID[9] STDID[8] STDID[7] STDID[6] STDID[5] -- STDID[4] STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MSG_DATA_0 MSG_DATA_1 MB25[9], [10] MSG_DATA_2 MSG_DATA_3 MB25[11], [12] MSG_DATA_4 MB25[13], [14] MSG_DATA_6 H'FFFFD42D H'FFFFD42F HCAN0 MSG_DATA_7 H'FFFFD42B H'FFFFD42E STDID[4] -- H'FFFFD429 H'FFFFD42C STDID[5] MB24[15], [16] H'FFFFD427 H'FFFFD42A STDID[6] MSG_DATA_5 H'FFFFD425 H'FFFFD428 Module STDID[7] MSG_DATA_6 H'FFFFD423 H'FFFFD426 Bit 0 STDID[8] MB24[13], [14] H'FFFFD421 H'FFFFD424 Bit 1 STDID[9] MSG_DATA_3 H'FFFFD414-1F H'FFFFD422 Bit 2 STDID[10] MSG_DATA_4 H'FFFFD413 H'FFFFD420 Bit 3 -- MB24[11], [12] H'FFFFD411 H'FFFFD412 Bit 4 MSG_DATA_1 H'FFFFD40F H'FFFFD410 Bit 5 MSG_DATA_2 H'FFFFD40D H'FFFFD40E Bit 6 MB24[9], [10] H'FFFFD40B H'FFFFD40C Bit 7 MSG_DATA_5 MSG_DATA_7 Rev. 5.00 Feb. 24, 2010 Page 883 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 Bit 6 Bit 5 H'FFFFD430 MB25[15], [16] -- STDID_LA FM[10] STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA HCAN0 (Channel 0) M[9] M[8] M[7] M[6] M[5] FM[4] H'FFFFD431 H'FFFFD432 STDID_LAF STDID_LA M[3] FM[2] MB25[17], [18] H'FFFFD433 MB26[0], [1]* 1 -- STDID[5] STDID[4] IDE EXTID[17] EXTID[16] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] MB26[4], [5] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MB26[6] MB26[7], [8]* 1 MSG_DATA_0 MSG_DATA_1 MB26[9], [10] MSG_DATA_2 MB26[11], [12] MSG_DATA_4 MB26[13] ,[14] MSG_DATA_6 MSG_DATA_3 MSG_DATA_5 MSG_DATA_7 MB26[15], [16] -- STDID_LA FM[10] STDID_LAF STDID_LA M[3] FM[2] MB26[17], [18] STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] STDID_LAF STDID_LAF -- M[1] M[0] -- EXTID_LAF EXTID_LA M[17] FM[16] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] -- -- -- -- -- -- STDID[10] STDID[9] STDID[8] STDID[7] STDID[6] STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE MB27[2], [3] EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] MB27[4], [5] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] MB27[0], [1]* H'FFFFD463 H'FFFFD465 -- STDID[6] EXTID[10] H'FFFFD461 H'FFFFD464 -- STDID[7] RTR H'FFFFD454-5F H'FFFFD462 -- EXTID[11] H'FFFFD453 H'FFFFD460 -- STDID[8] STDID[0] H'FFFFD451 H'FFFFD452 -- STDID[9] EXTID[12] H'FFFFD44F H'FFFFD450 -- STDID[10] STDID[1] H'FFFFD44D H'FFFFD44E -- -- EXTID[13] H'FFFFD44B H'FFFFD44C EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] STDID[2] H'FFFFD449 H'FFFFD44A Module EXTID_LAF EXTID_LA M[17] FM[16] EXTID[14] H'FFFFD447 H'FFFFD448 Bit 0 STDID[3] H'FFFFD445 H'FFFFD446 -- Bit 1 EXTID[15] H'FFFFD443 H'FFFFD444 STDID_LAF STDID_LAF -- M[1] M[0] Bit 2 MB26[2], [3] H'FFFFD441 H'FFFFD442 Bit 3 EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFD434-3F H'FFFFD440 Bit 4 1 Rev. 5.00 Feb. 24, 2010 Page 884 of 950 REJ09B0177-0500 -- -- -- -- STDID[5] STDID[4] HCAN0 EXTID[17] EXTID[16] (Channel 0) Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFD466 MB27[6] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] HCAN0 (Channel 0) TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] H'FFFFD467 H'FFFFD468 MB27[7], [8]* 1 H'FFFFD46A MB27[9],[10] MSG_DATA_2 MB27[11], [12] MSG_DATA_4 H'FFFFD46B H'FFFFD46C MSG_DATA_3 H'FFFFD46D H'FFFFD46E MSG_DATA_5 MSG_DATA_6 MB27[13],[14] H'FFFFD46F H'FFFFD470 MSG_DATA_7 MB27[15], [16] H'FFFFD471 H'FFFFD472 MB27[17], [18] MB28[0], [1]* 1 -- -- -- -- -- -- -- STDID[9] STDID[8] STDID[7] STDID[6] STDID[5] STDID[4] HCAN0 STDID[0] RTR IDE EXTID[17] EXTID[16] (Channel 0) EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] MB28[4], [5] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MB28[6] MB28 [7], [8]* 1 MSG_DATA_0 MSG_DATA_1 MB28[9], [10] MSG_DATA_2 MB28[11], [12] MSG_DATA_4 MB28[13], [14] MSG_DATA_6 MSG_DATA_3 MSG_DATA_5 H'FFFFD48F H'FFFFD491 -- STDID[10] STDID[1] H'FFFFD48D H'FFFFD490 -- -- EXTID[13] H'FFFFD48B H'FFFFD48E EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] STDID[2] H'FFFFD489 H'FFFFD48C EXTID_LAF EXTID_LA M[17] FM[16] EXTID[14] H'FFFFD487 H'FFFFD48A -- STDID[3] H'FFFFD485 H'FFFFD488 STDID_LAF STDID_LAF -- M[1] M[0] EXTID[15] H'FFFFD483 H'FFFFD486 STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] MB28[2], [3] H'FFFFD481 H'FFFFD484 STDID_LA FM[10] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFD474-7F H'FFFFD482 -- STDID_LAF STDID_LA M[3] FM[2] H'FFFFD473 H'FFFFD480 MSG_DATA_0 MSG_DATA_1 H'FFFFD469 MSG_DATA_7 MB28[15], [16] -- STDID_LA FM[10] STDID_LAF STDID_LA M[3] FM[2] STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] STDID_LAF STDID_LAF -- M[1] M[0] -- EXTID_LAF EXTID_LA M[17] FM[16] Rev. 5.00 Feb. 24, 2010 Page 885 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 H'FFFFD492 MB28[17], [18] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA HCAN0 M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] (Channel 0) H'FFFFD493 -- STDID[10] STDID[9] STDID[8] STDID[7] STDID[6] STDID[5] STDID[4] STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] MB29[4],[5] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] MB29[6] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MB29[0], [1]* MB29[2], [3] MB29[7],[8]* 1 MSG_DATA_4 MB29[13],[14] MSG_DATA_6 MSG_DATA_5 MSG_DATA_7 MB29[15], [16] MB29[17], [18] EXTID_LAF EXTID_LA M[17] FM[16] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] -- -- -- -- -- -- -- -- STDID[9] STDID[8] STDID[7] STDID[6] STDID[5] STDID[4] HCAN0 STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] (Channel 0) EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] MB30[4], [5] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] MB30[6] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MB30[2], [3] H'FFFFD4C7 H'FFFFD4C9 -- STDID[10] H'FFFFD4C5 H'FFFFD4C8 STDID_LAF STDID_LAF -- M[1] M[0] -- 1 H'FFFFD4C3 H'FFFFD4C6 STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] -- MB30[0], [1]* H'FFFFD4C1 H'FFFFD4C4 STDID_LA FM[10] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFD4B4-BF H'FFFFD4C2 -- STDID_LAF STDID_LA M[3] FM[2] H'FFFFD4B3 H'FFFFD4C0 -- MSG_DATA_0 MB29[11],[12] H'FFFFD4B1 H'FFFFD4B2 -- MSG_DATA_3 H'FFFFD4AF H'FFFFD4B0 -- MSG_DATA_2 H'FFFFD4AD H'FFFFD4AE Module MSG_DATA_1 MB29[9],[10] H'FFFFD4AB H'FFFFD4AC Bit 0 -- H'FFFFD4A9 H'FFFFD4AA Bit 1 -- H'FFFFD4A7 H'FFFFD4A8 Bit 2 -- H'FFFFD4A5 H'FFFFD4A6 Bit 3 -- H'FFFFD4A3 H'FFFFD4A4 Bit 4 -- 1 H'FFFFD4A1 H'FFFFD4A2 Bit 5 EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFD494-7F H'FFFFD4A0 Bit 6 MB30[7], [8]* 1 MSG_DATA_0 MSG_DATA_1 Rev. 5.00 Feb. 24, 2010 Page 886 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 H'FFFFD4CA MB30[9],[10] MSG_DATA_2 HCAN0 MSG_DATA_3 (Channel 0) H'FFFFD4CB H'FFFFD4CC MB30[11],[12] H'FFFFD4CD H'FFFFD4CE MSG_DATA_6 MB30[15], [16] -- MB30[17], [18] MB31[0], [1]* 1 MB31[2], [3] H'FFFFD4E3 MB31[4], [5] H'FFFFD4E5 H'FFFFD4E6 MB31[6] H'FFFFD4E7 H'FFFFD4E8 MB31[7], [8]* 1 H'FFFFD4E9 H'FFFFD4EA STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] STDID_LAF STDID_LAF -- M[1] M[0] -- EXTID_LAF EXTID_LA M[17] FM[16] -- -- -- -- -- -- -- -- -- STDID[10] STDID[9] STDID[8] STDID[7] STDID[6] STDID[5] STDID[4] HCAN0 STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] (Channel 0) EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MSG_DATA_0 MB31[11], [12] MSG_DATA_4 MB31[13], [14] MSG_DATA_6 MB31[15], [16] -- MSG_DATA_3 MSG_DATA_5 MSG_DATA_7 H'FFFFD4F1 H'FFFFD4F2 Module MSG_DATA_1 H'FFFFD4EF H'FFFFD4F0 Bit 0 -- MSG_DATA_2 H'FFFFD4ED H'FFFFD4EE Bit 1 EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] MB31[9], [10] H'FFFFD4EB H'FFFFD4EC Bit 2 EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFD4E1 H'FFFFD4E4 STDID_LA FM[10] STDID_LAF STDID_LA M[3] FM[2] H'FFFFD4D4-DF H'FFFFD4E2 Bit 3 MSG_DATA_7 H'FFFFD4D3 H'FFFFD4E0 Bit 4 MSG_DATA_4 MB30[13],[14] H'FFFFD4D1 H'FFFFD4D2 Bit 5 MSG_DATA_5 H'FFFFD4CF H'FFFFD4D0 Bit 6 STDID_LA FM[10] STDID_LAF STDID_LA M[3] FM[2] MB31[17], [18] STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] STDID_LAF STDID_LAF -- M[1] M[0] -- EXTID_LAF EXTID_LA M[17] FM[16] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] H'FFFFD4F3 EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFD4F4-7FF -- -- -- -- -- -- -- -- -- Rev. 5.00 Feb. 24, 2010 Page 887 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFD800 MCR -- -- -- -- -- -- -- -- HCAN1 MCR7 -- MCR5 -- -- MCR2 MCR1 MCR0 (Channel 1) -- -- -- -- -- -- -- -- -- -- GSR5 GSR4 GSR3 GSR2 GSR1 GSR0 BCR1 TSEG13 TSEG12 TSEG11 TSEG10 -- TSEG22 TSEG21 TSEG20 -- -- SJW1 SJW0 -- -- -- BSP BCR0 -- -- -- -- -- -- -- -- BRP7 BRP6 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 IRR IRR15 IRR14 IRR13 IRR12 IRR11 IRR10 IRR9 IRR8 IRR7 IRR6 IRR5 IRR4 IRR3 IRR2 IRR1 IRR0 IMR IMR15 IMR14 IMR13 IMR12 IMR11 IMR10 IMR9 IMR8 IMR7 IMR6 IMR5 IMR4 IMR3 IMR2 IMR1 IMR0 TEC/ REC TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 TXPR1 TXPR1[15] TXPR1[14] TXPR1[13] TXPR1[12] TXPR1[11] TXPR1[10] TXPR1[9] TXPR1[8] TXPR1[7] TXPR1[6] TXPR1[4] TXPR1[3] TXPR1[2] TXPR1[1] TXPR1[0] TXPR0[15] TXPR0[14] TXPR0[13] TXPR0[12] TXPR0[11] TXPR0[10] TXPR0[9] TXPR0[8] TXPR0[7] TXPR0[6] TXPR0[4] TXPR0[3] TXPR0[2] TXPR0[1] -- TXCR1[15] TXCR1[14] TXCR1[13] TXCR1[12] TXCR1[11] TXCR1[10] TXCR1[9] TXCR1[8] TXCR1[7] TXCR1[6] TXCR1[4] TXCR1[3] TXCR1[2] TXCR1[1] TXCR1[0] TXCR0[15] TXCR0[14] TXCR0[13] TXCR0[12] TXCR0[11] TXCR0[10] TXCR0[9] TXCR0[8] TXCR0[7] TXCR0[6] TXCR0[5] TXCR0[4] TXCR0[3] TXCR0[2] TXCR0[1] -- TXACK1 [15] TXACK1 [14] TXACK1 [13] TXACK1 [12] TXACK1 [11] TXACK1 [10] TXACK1 [9] TXACK1 TXACK1[7] TXACK1[6] TXACK1[5] TXACK1[4] TXACK1[3] TXACK1[2] TXACK1[1] TXACK1[0] TXACK0 [15] TXACK0 [14] TXACK0 [12] TXACK0 [11] TXACK0[7] TXACK0[6] TXACK0[5] TXACK0[4] TXACK0[3] TXACK0[2] TXACK0[1] TXACK0[0] ABACK1 [15] ABACK1 [14] ABACK1 [12] ABACK1 [11] H'FFFFD801 H'FFFFD802 GSR H'FFFFD803 H'FFFFD804 H'FFFFD805 H'FFFFD806 H'FFFFD807 H'FFFFD808 H'FFFFD809 H'FFFFD80A H'FFFFD80B H'FFFFD80C H'FFFFD80D H'FFFFD820 H'FFFFD821 H'FFFFD822 TXPR0 H'FFFFD823 H'FFFFD828 TXCR1 H'FFFFD829 H'FFFFD82A TXCR0 H'FFFFD82B H'FFFFD830 TXACK1 H'FFFFD831 H'FFFFD832 TXACK0 H'FFFFD833 H'FFFFD838 ABACK1 H'FFFFD839 H'FFFFD83A H'FFFFD841 TXPR0[5] TXCR1[5] TXACK0 [13] ABACK1 [13] TXACK0 [10] ABACK1 [10] [8] TXACK0 [9] TXACK0 [8] ABACK1 [9] ABACK1 [8] ABACK1 [7] ABACK1 [6] ABACK1 [5] ABACK1 [4] ABACK1 [3] ABACK1 [2] ABACK1 [1] ABACK1 [0] ABACK0 H'FFFFD83B H'FFFFD840 TXPR1[5] ABACK0 [15] ABACK0 [14] ABACK0 [13] ABACK0 [12] ABACK0 [11] ABACK0 [10] ABACK0 [9] ABACK0 [8] ABACK0 [7] ABACK0 [6] ABACK0 [5] ABACK0 [4] ABACK0 [3] ABACK0 [2] ABACK0 [1] -- RXPR1 RXPR1[15] RXPR1[14] RXPR1[13] RXPR1[12] RXPR1[11] RXPR1[10] RXPR1[9] RXPR1[8] RXPR1[7] RXPR1[6] RXPR1[4] RXPR1[3] RXPR1[0] Rev. 5.00 Feb. 24, 2010 Page 888 of 950 REJ09B0177-0500 RXPR1[5] RXPR1[2] RXPR1[1] Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 Bit 6 H'FFFFD842 RXPR0 RXPR0[15] RXPR0 [7] H'FFFFD843 Bit 5 Bit 0 Module RXPR0[11] RXPR0[10] RXPR0 [9] RXPR0[8] HCAN1 RXPR0 [3] RXPR0 [0] (Channel 1) Bit 4 Bit 3 RXPR0[14] RXPR0[13] RXPR0[12] RXPR0 [6] RXPR0[4] RXPR0[5] Bit 2 RXPR0[2] Bit 1 RXPR0[1] RFPR1 RFPR1 [15] RFPR1 [14] RFPR1 [13] RFPR1 [12] RFPR1 [11] RFPR1 [10] RFPR1 [9] RFPR1 [8] RFPR1[7] RFPR1[0] RFPR0 RFPR0 [15] RFPR0 [14] RFPR0 [13] RFPR0 [12] RFPR0 [11] RFPR0 [10] RFPR0 [9] RFPR0 [8] RFPR0[7] RFPR0[6] RFPR0[5] RFPR0[4] RFPR0[3] RFPR0[2] RFPR0[1] RFPR0[0] MBIMR1 MBIMR1 [15] MBIMR1 [14] MBIMR1 [13] MBIMR1 [12] MBIMR1 [11] MBIMR1 [10] MBIMR1 [9] MBIMR1 [8] MBIMR1[7] MBIMR1[6] MBIMR1[5] MBIMR1[4] MBIMR1[3] MBIMR1[2] MBIMR1[1] MBIMR1[0] MBIMR0 MBIMR0 [15] MBIMR0 [14] MBIMR0 [12] MBIMR0 [11] MBIMR0[7] MBIMR0[6] MBIMR0[5] MBIMR0[4] MBIMR0[3] MBIMR0[2] MBIMR0[1] MBIMR0[0] UMSR1 UMSR1 [15] UMSR1 [14] UMSR1 [12] UMSR1 [11] UMSR1[7] UMSR1[6] UMSR1[5] UMSR1[4] UMSR1[3] UMSR1[2] UMSR1[1] UMSR1[0] UMSR0 UMSR0 [15] UMSR0 [14] UMSR0 [13] UMSR0 [12] UMSR0 [11] UMSR0 [10] UMSR0 [9] UMSR0 [8] H'FFFFD85B UMSR0[7] UMSR0[6] UMSR0[5] UMSR0[4] UMSR0[3] UMSR0[2] UMSR0[1] UMSR0[0] H'FFFFD85C-7F -- -- -- -- -- -- -- -- TCNTR15 TCNTR14 TCNTR13 TCNTR12 TCNTR11 TCNTR10 TCNTR9 TCNTR8 TCNTR7 TCNTR6 TCNTR5 TCNTR4 TCNTR3 TCNTR2 TCNTR1 TCNTR0 TCR TCR15 TCR14 TCR13 TCR12 TCR11 TCR10 TCR9 -- TCR7 -- TCR5 TCR4 TCR3 TCR2 TCR1 TCR0 TSR -- -- -- -- -- -- -- -- -- -- -- TSR4 TSR3 TSR2 TSR1 TSR0 TDCR15 TDCR14 TDCR13 TDCR12 TDCR11 TDCR10 TDCR9 TDCR8 TDCR7 TDCR6 TDCR5 TDCR4 TDCR3 TDCR2 TDCR1 TDCR0 LOSR15 LOSR14 LOSR13 LOSR12 LOSR11 LOSR10 LOSR9 LOSR8 LOSR7 LOSR6 LOSR5 LOSR4 LOSR3 LOSR2 LOSR1 LOSR0 -- -- -- -- -- -- -- -- -- -- -- -- ICCR0_cc3 ICCR0_cc2 ICCR0_cc1 ICCR0_cc 0 ICR0_tm ICR0_tm 15 ICR0_tm 14 ICR0_tm 13 ICR0_tm 12 ICR0_tm 11 ICR0_tm7 ICR0_tm6 ICR0_tm5 ICR0_tm4 ICR0_tm3 ICR0_tm2 ICR0_tm1 ICR0_tm0 ICR1 ICR1[15] ICR1[14] ICR1[13] ICR1[12] ICR1[11] ICR1[10] ICR1[9] ICR1[8] ICR1[7] ICR1[6] ICR1[5] ICR1[4] ICR1[3] ICR1[2] ICR1[1] ICR1[0] H'FFFFD848 H'FFFFD849 H'FFFFD84A H'FFFFD84B H'FFFFD850 H'FFFFD851 H'FFFFD852 H'FFFFD853 H'FFFFD858 H'FFFFD859 H'FFFFD85A H'FFFFD880 TCNTR H'FFFFD881 H'FFFFD882 H'FFFFD883 H'FFFFD884 H'FFFFD885 H'FFFFD886 TDCR H'FFFFD887 H'FFFFD888 LOSR H'FFFFD889 H'FFFFD88A ICR0_cc H'FFFFD88B H'FFFFD88C H'FFFFD88D H'FFFFD88E H'FFFFD88F RFPR1[6] RFPR1[5] MBIMR0 [13] UMSR1 [13] RFPR1[4] RFPR1[3] RFPR1[2] MBIMR0 [10] UMSR1 [10] ICR0_tm 10 RFPR1[1] MBIMR0 [9] MBIMR0 [8] UMSR1 [9] ICR0_tm9 UMSR1 [8] ICR0_tm8 Rev. 5.00 Feb. 24, 2010 Page 889 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0 Module H'FFFFD890 TCMR0 TCMR0 [15] TCMR0 [14] TCMR0 [13] TCMR0 [12] TCMR0 [11] TCMR0 [10] TCMR0 [9] TCMR0 [8] HCAN1 (Channel 1) TCMR0[7] TCMR0[6] TCMR0[5] TCMR0[4] TCMR0[3] TCMR0[2] TCMR0[1] TCMR0[0] TCMR1 TCMR1 [15] TCMR1 [14] TCMR1 [13] TCMR1 [12] TCMR1 [11] TCMR1 [10] TCMR1 [9] TCMR1 [8] TCMR1[7] TCMR1[6] TCMR1[5] TCMR1[4] TCMR1[3] TCMR1[2] TCMR1[1] TCMR1[0] TCMR2 TCMR2 [15] TCMR2 [14] TCMR2 [13] TCMR2 [12] TCMR2 [11] TCMR2 [10] TCMR2 [9] TCMR2 [8] TCMR2[7] TCMR2[6] TCMR2[5] TCMR2[4] TCMR2[3] TCMR2[2] TCMR2[1] TCMR2[0] CCR -- -- -- -- -- -- -- -- -- -- -- -- CCR3 CCR2 CCR1 CCR0 CMAX -- -- -- -- -- -- -- -- -- -- -- -- CMAX3 CMAX2 CMAX1 CMAX0 TMR -- -- -- -- -- -- -- -- -- -- -- -- TMR3 TMR2 TMR1 -- CCRbuf -- -- -- -- -- -- -- -- -- -- -- -- CCRbuf3 CCRbuf2 CCRbuf1 CCRbuf0 ICR0buf -- -- -- -- -- -- -- -- -- -- -- -- ICR0buf3 ICR0buf2 ICR0buf1 ICR0buf0 H'FFFFD8A0-FF -- -- -- -- -- -- -- -- -- -- H'FFFFD900 MB0[0], [1]* -- STDID[10] STDID[9] STDID[8] STDID[7] STDID[6] STDID[5] STDID[4] HCAN1 STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] (Channel 1) EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] H'FFFFD891 H'FFFFD892 H'FFFFD893 H'FFFFD894 H'FFFFD895 H'FFFFD896 H'FFFFD897 H'FFFFD898 H'FFFFD899 H'FFFFD89A H'FFFFD89B H'FFFFD89C H'FFFFD89D H'FFFFD89E H'FFFFD89F 1 H'FFFFD901 H'FFFFD902 MB0[2], [3] H'FFFFD903 H'FFFFD904 MB0[4], [5] H'FFFFD905 H'FFFFD906 MB0[6] H'FFFFD907 H'FFFFD908 MB0[7], [8]* 1 H'FFFFD909 H'FFFFD90A MSG_DATA_1 MSG_DATA_2 MB0[11], [12] MSG_DATA_4 MB0[13], [14] MSG_DATA_6 MB0[15], [16] -- MSG_DATA_3 H'FFFFD90D H'FFFFD90E MSG_DATA_5 H'FFFFD90F H'FFFFD910 H'FFFFD911 Bit 2 MSG_DATA_0 MB0[9], [10] H'FFFFD90B H'FFFFD90C Bit 3 MSG_DATA_7 STDID_LA FM[10] STDID_LAF STDID_LA M[3] FM[2] Rev. 5.00 Feb. 24, 2010 Page 890 of 950 REJ09B0177-0500 STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] STDID_LAF STDID_LAF -- M[1] M[0] -- EXTID_LAF EXTID_LA M[17] FM[16] Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 H'FFFFD912 MB0[17], [18] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA HCAN1 (Channel 1) M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] H'FFFFD914-1F -- H'FFFFD920 MB1[0], [1]* 1 H'FFFFD921 MB1[2], [3] H'FFFFD923 H'FFFFD924 MB1[4], [5] H'FFFFD925 H'FFFFD926 MB1[6] H'FFFFD927 H'FFFFD928 MB1[7], [8]* 1 -- -- -- STDID[6] STDID[5] STDID[4] HCAN1 STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] (Channel 1) EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MSG_DATA_0 -- MSG_DATA_7 STDID_LA FM[10] STDID_LAF STDID_LA M[3] FM[2] MB1[17], [18] STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] STDID_LAF STDID_LAF -- M[1] M[0] -- EXTID_LAF EXTID_LA M[17] FM[16] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] MB2[0], [1]* 1 MB2[2], [3] MB2[4], [5] MB2[6] H'FFFFD947 H'FFFFD949 -- STDID[7] MB1[15], [16] H'FFFFD945 H'FFFFD948 -- MSG_DATA_6 H'FFFFD943 H'FFFFD946 -- STDID[8] MB1[13], [14] H'FFFFD941 H'FFFFD944 -- STDID[9] MSG_DATA_5 H'FFFFD934-3F H'FFFFD942 Module MSG_DATA_3 H'FFFFD933 H'FFFFD940 Bit 0 -- MSG_DATA_4 H'FFFFD931 H'FFFFD932 Bit 1 STDID[10] MB1[11], [12] H'FFFFD92F H'FFFFD930 Bit 2 -- MSG_DATA_2 H'FFFFD92D H'FFFFD92E Bit 3 -- MB1[9], [10] H'FFFFD92B H'FFFFD92C Bit 4 MSG_DATA_1 H'FFFFD929 H'FFFFD92A Bit 5 EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFD913 H'FFFFD922 Bit 6 MB2[7], [8]* 1 -- -- -- -- -- -- -- -- -- -- STDID[10] STDID[9] STDID[8] STDID[7] STDID[6] STDID[5] STDID[4] HCAN1 STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] (Channel 1) EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MSG_DATA_0 MSG_DATA_1 Rev. 5.00 Feb. 24, 2010 Page 891 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 H'FFFFD94A MB2[9], [10] MSG_DATA_2 HCAN1 MSG_DATA_3 (Channel 1) H'FFFFD94B H'FFFFD94C MB2[11], [12] MSG_DATA_4 MB2[13], [14] MSG_DATA_6 MB2[15], [16] -- H'FFFFD94D H'FFFFD94E MB2[17], [18] H'FFFFD966 -- -- -- -- STDID[7] STDID[6] STDID[5] STDID[4] HCAN1 STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] (Channel 1) EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] MB3[4], [5] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] MB3[6] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MB3[2], [3] MB3[7], [8]* 1 MSG_DATA_0 MSG_DATA_1 MB3[9], [10] MSG_DATA_2 MB3[11], [12] MSG_DATA_4 MSG_DATA_3 MSG_DATA_5 MB3[13], [14] MSG_DATA_6 MB3[15], [16] -- MSG_DATA_7 STDID_LA FM[10] STDID_LAF STDID_LA M[3] FM[2] MB3[17], [18] STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] STDID_LAF STDID_LAF -- M[1] M[0] -- EXTID_LAF EXTID_LA M[17] FM[16] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFD974-7F H'FFFFD981 EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] -- H'FFFFD973 H'FFFFD980 EXTID_LAF EXTID_LA M[17] FM[16] -- H'FFFFD971 H'FFFFD972 -- STDID[8] H'FFFFD96F H'FFFFD970 STDID_LAF STDID_LAF -- M[1] M[0] -- H'FFFFD96D H'FFFFD96E STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] STDID[9] H'FFFFD96B H'FFFFD96C Module -- H'FFFFD969 H'FFFFD96A Bit 0 STDID[10] H'FFFFD967 H'FFFFD968 Bit 1 -- 1 H'FFFFD963 H'FFFFD965 Bit 2 -- MB3[0], [1]* H'FFFFD961 H'FFFFD964 Bit 3 EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFD954-5F H'FFFFD962 STDID_LA FM[10] STDID_LAF STDID_LA M[3] FM[2] H'FFFFD953 H'FFFFD960 Bit 4 MSG_DATA_7 H'FFFFD951 H'FFFFD952 Bit 5 MSG_DATA_5 H'FFFFD94F H'FFFFD950 Bit 6 MB4[0], [1]* 1 -- -- -- -- -- -- -- -- -- STDID[10] STDID[9] STDID[8] STDID[7] STDID[6] STDID[5] STDID[4] STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] Rev. 5.00 Feb. 24, 2010 Page 892 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 H'FFFFD982 MB4[2], [3] EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] H'FFFFD983 H'FFFFD984 MB4[4], [5] H'FFFFD985 H'FFFFD986 MB4[6] H'FFFFD987 H'FFFFD988 MB4[7], [8]* 1 H'FFFFD989 H'FFFFD98A MSG_DATA_2 MB4[11], [12] MSG_DATA_4 MB4[13], [14] MSG_DATA_6 MB4[15], [16] -- MB4[17], [18] -- -- -- -- -- STDID[9] STDID[8] STDID[7] STDID[6] STDID[5] STDID[4] STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] MB5[2], [3] EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] MB5[4], [5] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] MB5[6] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MB5 [7], [8]* 1 MSG_DATA_0 MB5 [9], [10] MSG_DATA_2 MB5[11], [12] MSG_DATA_4 MB5[13], [14] MSG_DATA_6 MSG_DATA_3 H'FFFFD9AD H'FFFFD9AF -- MSG_DATA_1 H'FFFFD9AB H'FFFFD9AE EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] -- H'FFFFD9A9 H'FFFFD9AC EXTID_LAF EXTID_LA M[17] FM[16] STDID[10] H'FFFFD9A7 H'FFFFD9AA -- -- 1 H'FFFFD9A5 H'FFFFD9A8 STDID_LAF STDID_LAF -- M[1] M[0] -- MB5[0], [1]* H'FFFFD9A3 H'FFFFD9A6 STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFD9A1 H'FFFFD9A4 STDID_LA FM[10] STDID_LAF STDID_LA M[3] FM[2] H'FFFFD994-9F H'FFFFD9A2 (Channel 1) MSG_DATA_7 H'FFFFD993 H'FFFFD9A0 HCAN1 MSG_DATA_5 H'FFFFD991 H'FFFFD992 EXTID[8] EXTID[0] MSG_DATA_3 H'FFFFD98F H'FFFFD990 EXTID[9] EXTID[1] MSG_DATA_0 MB4[9], [10] H'FFFFD98D H'FFFFD98E Module MSG_DATA_1 H'FFFFD98B H'FFFFD98C Bit 0 Bit 1 MSG_DATA_5 MSG_DATA_7 Rev. 5.00 Feb. 24, 2010 Page 893 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 Bit 6 Bit 5 H'FFFFD9B0 MB5[15], [16] -- STDID_LA FM[10] STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA HCAN1 (Channel 1) M[9] M[8] M[7] M[6] M[5] FM[4] H'FFFFD9B1 H'FFFFD9B2 STDID_LAF STDID_LA M[3] FM[2] MB5[17], [18] H'FFFFD9B3 -- -- -- -- -- -- -- STDID[8] STDID[7] STDID[6] STDID[5] STDID[4] HCAN1 STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] (Channel 1) MB6[2], [3] EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] MB6[4], [5] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MB6[6] 1 MB6[7], [8]* MSG_DATA_1 MSG_DATA_2 MB6[11], [12] MSG_DATA_4 MB6[13], [14] MSG_DATA_6 MSG_DATA_3 MSG_DATA_5 H'FFFFD9CF H'FFFFD9D0 MSG_DATA_7 MB6[15], [16] H'FFFFD9D1 H'FFFFD9D2 MB6[17], [18] STDID_LAF STDID_LAF -- M[1] M[0] -- EXTID_LAF EXTID_LA M[17] FM[16] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] -- -- -- -- -- STDID[10] STDID[9] STDID[8] STDID[7] STDID[6] STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE MB7[2], [3] EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] MB7[4], [5] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] MB7[0], [1]* H'FFFFD9E3 H'FFFFD9E5 STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] -- H'FFFFD9E1 H'FFFFD9E4 STDID_LA FM[10] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFD9D4-DF H'FFFFD9E2 -- STDID_LAF STDID_LA M[3] FM[2] H'FFFFD9D3 H'FFFFD9E0 MSG_DATA_0 MB6[9], [10] H'FFFFD9CD H'FFFFD9CE EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] STDID[9] H'FFFFD9CB H'FFFFD9CC EXTID_LAF EXTID_LA M[17] FM[16] -- H'FFFFD9C9 H'FFFFD9CA Module STDID[10] H'FFFFD9C7 H'FFFFD9C8 Bit 0 -- H'FFFFD9C5 H'FFFFD9C6 -- Bit 1 -- H'FFFFD9C3 H'FFFFD9C4 STDID_LAF STDID_LAF -- M[1] M[0] Bit 2 MB6[0], [1]* H'FFFFD9C1 H'FFFFD9C2 Bit 3 EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFD9B4-BF H'FFFFD9C0 Bit 4 1 Rev. 5.00 Feb. 24, 2010 Page 894 of 950 REJ09B0177-0500 -- -- -- -- STDID[5] STDID[4] HCAN1 EXTID[17] EXTID[16] (Channel 1) Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFD9E6 MB7[6] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] HCAN1 TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] H'FFFFD9E7 H'FFFFD9E8 MB7[7], [8]* 1 MB7[9], [10] MSG_DATA_2 MB7[11], [12] MSG_DATA_4 H'FFFFD9EB H'FFFFD9EC MSG_DATA_3 H'FFFFD9ED H'FFFFD9EE MSG_DATA_5 MB7[13], [14] H'FFFFD9EF H'FFFFD9F0 MB7[15], [16] MB7[17], [18] MB8[0], [1]* 1 -- -- -- -- -- -- -- STDID[9] STDID[8] STDID[7] STDID[6] STDID[5] STDID[4] HCAN1 STDID[0] RTR IDE EXTID[17] EXTID[16] (Channel 1) EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] MB8[4], [5] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MB8[6] MB8[7], [8]* 1 MSG_DATA_0 MSG_DATA_1 MB8[9], [10] MSG_DATA_2 MB8[11], [12] MSG_DATA_4 MB8[13], [14] MSG_DATA_6 MSG_DATA_3 MSG_DATA_5 H'FFFFDA0F H'FFFFDA11 -- STDID[10] STDID[1] H'FFFFDA0D H'FFFFDA10 -- -- EXTID[13] H'FFFFDA0B H'FFFFDA0E EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] STDID[2] H'FFFFDA09 H'FFFFDA0C EXTID_LAF EXTID_LA M[17] FM[16] EXTID[14] H'FFFFDA07 H'FFFFDA0A -- STDID[3] H'FFFFDA05 H'FFFFDA08 STDID_LAF STDID_LAF -- M[1] M[0] EXTID[15] H'FFFFDA03 H'FFFFDA06 STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] MB8[2], [3] H'FFFFDA01 H'FFFFDA04 STDID_LA FM[10] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFD9F4-FF H'FFFFDA02 -- STDID_LAF STDID_LA M[3] FM[2] H'FFFFD9F3 H'FFFFDA00 MSG_DATA_6 MSG_DATA_7 H'FFFFD9F1 H'FFFFD9F2 MSG_DATA_0 MSG_DATA_1 H'FFFFD9E9 H'FFFFD9EA (Channel 1) MSG_DATA_7 MB8[15], [16] -- STDID_LA FM[10] STDID_LAF STDID_LA M[3] FM[2] STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] STDID_LAF STDID_LAF -- M[1] M[0] -- EXTID_LAF EXTID_LA M[17] FM[16] Rev. 5.00 Feb. 24, 2010 Page 895 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 H'FFFFDA12 MB8[17], [18] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA HCAN1 M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] (Channel 1) H'FFFFDA13 -- -- STDID[10] STDID[9] STDID[8] STDID[7] STDID[6] STDID[5] STDID[4] STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] MB9[4], [5] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] MB9[6] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MB9[0], [1]* MB9[2], [3] MB9[7], [8]* 1 MSG_DATA_3 MB9[11], [12] MSG_DATA_4 MB9[13], [14] MSG_DATA_6 MSG_DATA_5 MSG_DATA_7 -- MB9[15], [16] H'FFFFDA31 H'FFFFDA32 -- -- -- -- -- -- -- -- STDID[10] STDID[9] STDID[8] STDID[7] STDID[6] STDID[5] STDID[4] HCAN1 STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] (Channel 1) EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] MB10[4], [5] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] MB10[6] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MB10[2], [3] H'FFFFDA47 H'FFFFDA49 EXTID_LAF EXTID_LA M[17] FM[16] -- 1 H'FFFFDA45 H'FFFFDA48 -- -- MB10[0], [1]* H'FFFFDA43 H'FFFFDA46 STDID_LAF STDID_LAF -- M[1] M[0] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFDA41 H'FFFFDA44 STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] MB9[17], [18] H'FFFFDA34-3F H'FFFFDA42 STDID_LA FM[10] STDID_LAF STDID_LA M[3] FM[2] H'FFFFDA33 H'FFFFDA40 -- MSG_DATA_2 H'FFFFDA2F H'FFFFDA30 -- MSG_DATA_1 MB9[9], [10] H'FFFFDA2D H'FFFFDA2E Module MSG_DATA_0 H'FFFFDA2B H'FFFFDA2C Bit 0 -- H'FFFFDA29 H'FFFFDA2A Bit 1 -- H'FFFFDA27 H'FFFFDA28 Bit 2 -- H'FFFFDA25 H'FFFFDA26 Bit 3 -- H'FFFFDA23 H'FFFFDA24 Bit 4 -- 1 H'FFFFDA21 H'FFFFDA22 Bit 5 EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFDA14-1F H'FFFFDA20 Bit 6 MB10[7], [8]* 1 MSG_DATA_0 MSG_DATA_1 Rev. 5.00 Feb. 24, 2010 Page 896 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 H'FFFFDA4A MB10[9], [10] MSG_DATA_2 HCAN1 MSG_DATA_3 (Channel 1) H'FFFFDA4B H'FFFFDA4C MB10[11], [12] MSG_DATA_4 MB10[13],[14] MSG_DATA_6 H'FFFFDA4D H'FFFFDA4E MB10[15], [16] MB10[17], [18] EXTID_LAF EXTID_LA M[17] FM[16] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] STDID[10] STDID[9] STDID[8] STDID[7] STDID[6] STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE MB11[2], [3] EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] MB11[4], [5] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] MB11[6] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MB11[7], [8]* 1 -- -- -- STDID[5] STDID[4] HCAN1 EXTID[17] EXTID[16] (Channel 1) MSG_DATA_0 MSG_DATA_1 MB11[9], [10] MSG_DATA_2 MB11[11], [12] MSG_DATA_4 MB11[13], [14] MSG_DATA_6 MB11[15], [16] -- MSG_DATA_3 MSG_DATA_5 H'FFFFDA6F MSG_DATA_7 H'FFFFDA71 H'FFFFDA72 -- -- MB11[0], [1]* H'FFFFDA6D H'FFFFDA70 STDID_LAF STDID_LAF -- M[1] M[0] -- H'FFFFDA6B H'FFFFDA6E Module STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] -- H'FFFFDA69 H'FFFFDA6C STDID_LA FM[10] -- H'FFFFDA67 H'FFFFDA6A Bit 0 -- H'FFFFDA65 H'FFFFDA68 Bit 1 -- H'FFFFDA63 H'FFFFDA66 Bit 2 -- 1 H'FFFFDA61 H'FFFFDA64 Bit 3 EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFDA54-5F H'FFFFDA62 -- STDID_LAF STDID_LA M[3] FM[2] H'FFFFDA53 H'FFFFDA60 Bit 4 MSG_DATA_7 H'FFFFDA51 H'FFFFDA52 Bit 5 MSG_DATA_5 H'FFFFDA4F H'FFFFDA50 Bit 6 STDID_LA FM[10] STDID_LAF STDID_LA M[3] FM[2] MB11[17], [18] STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] STDID_LAF STDID_LAF -- M[1] M[0] -- EXTID_LAF EXTID_LA M[17] FM[16] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] H'FFFFDA73 EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFDA74-7F -- -- -- -- -- -- -- -- -- Rev. 5.00 Feb. 24, 2010 Page 897 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation H'FFFFDA80 MB12[0], [1]* 1 H'FFFFDA81 H'FFFFDA82 MB12[2], [3] H'FFFFDA83 H'FFFFDA84 MB12[4], [5] H'FFFFDA85 H'FFFFDA86 MB12[6] H'FFFFDA87 H'FFFFDA88 MB12[7], [8]* 1 H'FFFFDA89 H'FFFFDA8A STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] (Channel 1) EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MSG_DATA_0 STDID_LA FM[10] STDID_LAF STDID_LA M[3] FM[2] MB12[17], [18] STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] STDID_LAF STDID_LAF -- M[1] M[0] -- EXTID_LAF EXTID_LA M[17] FM[16] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] MB13[0], [1]* 1 MB13[2], [3] MB13[4], [5] MB13[6] -- -- -- -- -- -- -- -- STDID[10] STDID[9] STDID[8] STDID[7] STDID[6] STDID[5] STDID[4] STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] 1 MSG_DATA_0 MB13[9], [10] MSG_DATA_2 MB13[7], [8]* MSG_DATA_1 MSG_DATA_3 MB13[11], [12] MSG_DATA_4 MB13[13], [14] MSG_DATA_6 H'FFFFDAAD H'FFFFDAAF HCAN1 MSG_DATA_7 H'FFFFDAAB H'FFFFDAAE STDID[4] -- H'FFFFDAA9 H'FFFFDAAC STDID[5] MB12[15], [16] H'FFFFDAA7 H'FFFFDAAA STDID[6] MSG_DATA_5 H'FFFFDAA5 H'FFFFDAA8 Module STDID[7] MSG_DATA_6 H'FFFFDAA3 H'FFFFDAA6 Bit 0 STDID[8] MB12[13], [14] H'FFFFDAA1 H'FFFFDAA4 Bit 1 STDID[9] MSG_DATA_3 H'FFFFDA94-9F H'FFFFDAA2 Bit 2 STDID[10] MSG_DATA_4 H'FFFFDA93 H'FFFFDAA0 Bit 3 -- MB12[11], [12] H'FFFFDA91 H'FFFFDA92 Bit 4 MSG_DATA_1 H'FFFFDA8F H'FFFFDA90 Bit 5 MSG_DATA_2 H'FFFFDA8D H'FFFFDA8E Bit 6 MB12[9], [10] H'FFFFDA8B H'FFFFDA8C Bit 7 MSG_DATA_5 MSG_DATA_7 Rev. 5.00 Feb. 24, 2010 Page 898 of 950 REJ09B0177-0500 -- Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 Bit 6 Bit 5 H'FFFFDAB0 MB13[15], [16] -- STDID_LA FM[10] STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA HCAN1 M[9] M[8] M[7] M[6] M[5] FM[4] (Channel 1) STDID_LAF STDID_LAF -- -- EXTID_LAF EXTID_LA M[1] M[0] M[17] FM[16] H'FFFFDAB1 H'FFFFDAB2 STDID_LAF STDID_LA M[3] FM[2] MB13[17], [18] H'FFFFDAB3 MB14[0], [1]* 1 H'FFFFDAC1 H'FFFFDAC2 MB14[2], [3] H'FFFFDAC3 H'FFFFDAC4 MB14[4], [5] H'FFFFDAC5 H'FFFFDAC6 MB14[6] H'FFFFDAC7 H'FFFFDAC8 MB14[7], [8]* 1 H'FFFFDAC9 H'FFFFDACA -- -- -- -- -- -- STDID[8] STDID[7] STDID[6] STDID[5] STDID[4] HCAN1 STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] (Channel 1) EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MSG_DATA_0 MB14[15], [16] -- MSG_DATA_5 MSG_DATA_7 STDID_LA FM[10] STDID_LAF STDID_LA M[3] FM[2] MB14[17], [18] STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] STDID_LAF STDID_LAF -- M[1] M[0] -- EXTID_LAF EXTID_LA M[17] FM[16] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] MB15[0], [1]* MB15[2], [3] H'FFFFDAE3 H'FFFFDAE5 -- STDID[9] MSG_DATA_6 H'FFFFDAE1 H'FFFFDAE4 -- STDID[10] MB14[13], [14] H'FFFFDAD4-DF H'FFFFDAE2 -- -- MSG_DATA_4 H'FFFFDAD3 H'FFFFDAE0 Module EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] MB14[11], [12] H'FFFFDAD1 H'FFFFDAD2 Bit 0 MSG_DATA_3 H'FFFFDACF H'FFFFDAD0 Bit 1 MSG_DATA_1 H'FFFFDACD H'FFFFDACE Bit 2 MSG_DATA_2 MB14[9], [10] H'FFFFDACB H'FFFFDACC Bit 3 EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFDAB4-BF H'FFFFDAC0 Bit 4 MB15[4], [5] 1 -- -- -- -- -- -- -- -- -- -- STDID[10] STDID[9] STDID[8] STDID[7] STDID[6] STDID[5] STDID[4] HCAN1 STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] (Channel 1) EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] Rev. 5.00 Feb. 24, 2010 Page 899 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFDAE6 MB15[6] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] HCAN1 (Channel 1) TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] H'FFFFDAE7 H'FFFFDAE8 MB15[7], [8]* 1 H'FFFFDAE9 H'FFFFDAEA MSG_DATA_1 MB15[9], [10] MSG_DATA_2 MB15[11], [12] MSG_DATA_4 H'FFFFDAEB H'FFFFDAEC MSG_DATA_3 H'FFFFDAED H'FFFFDAEE MSG_DATA_5 MB15[13], [14] MSG_DATA_6 MB15[15], [16] -- H'FFFFDAEF H'FFFFDAF0 MSG_DATA_7 H'FFFFDAF1 H'FFFFDAF2 MB15[17], [18] -- -- -- -- -- -- -- STDID[9] STDID[8] STDID[7] STDID[6] STDID[5] STDID[4] HCAN1 STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] (Channel 1) MB16[2], [3] EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] MB16[4], [5] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] MB16[6] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MB16[7], [8]* 1 H'FFFFDB09 MB16[9], [10] MSG_DATA_2 MB16[11], [12] MSG_DATA_4 MSG_DATA_3 H'FFFFDB0D H'FFFFDB0E MSG_DATA_5 MB16[13], [14] MSG_DATA_6 MB16[15], [16] -- H'FFFFDB0F H'FFFFDB10 H'FFFFDB11 MSG_DATA_0 MSG_DATA_1 H'FFFFDB0B H'FFFFDB0C EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] -- H'FFFFDB07 H'FFFFDB0A EXTID_LAF EXTID_LA M[17] FM[16] STDID[10] H'FFFFDB05 H'FFFFDB08 -- -- 1 H'FFFFDB03 H'FFFFDB06 STDID_LAF STDID_LAF -- M[1] M[0] -- MB16[0], [1]* H'FFFFDB01 H'FFFFDB04 STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFDAF4-FF H'FFFFDB02 STDID_LA FM[10] STDID_LAF STDID_LA M[3] FM[2] H'FFFFDAF3 H'FFFFDB00 MSG_DATA_0 MSG_DATA_7 STDID_LA FM[10] STDID_LAF STDID_LA M[3] FM[2] Rev. 5.00 Feb. 24, 2010 Page 900 of 950 REJ09B0177-0500 STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] STDID_LAF STDID_LAF -- M[1] M[0] -- EXTID_LAF EXTID_LA M[17] FM[16] Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 H'FFFFDB12 MB16[17], [18] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA HCAN1 M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] (Channel 1) H'FFFFDB13 -- -- STDID[10] STDID[9] STDID[8] STDID[7] STDID[6] STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] MB17[4], [5] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] MB17[6] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MB17[0], [1]* MB17[2], [3] MB17[7], [8]* 1 MSG_DATA_4 MB17[13], [14] MSG_DATA_6 MB17[15], [16] MB17[17], [18] STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] STDID_LAF STDID_LAF -- M[1] M[0] -- EXTID_LAF EXTID_LA M[17] FM[16] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] -- -- -- -- -- -- -- -- -- STDID[10] STDID[9] STDID[8] STDID[7] STDID[6] STDID[5] STDID[4] HCAN1 STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] (Channel 1) EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] MB18[4], [5] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] MB18[6] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] 1 MB18[2], [3] H'FFFFDB47 H'FFFFDB49 STDID_LA FM[10] -- MB18[0], [1]* H'FFFFDB45 H'FFFFDB48 HCAN1 EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFDB43 H'FFFFDB46 -- STDID_LAF STDID_LA M[3] FM[2] H'FFFFDB41 H'FFFFDB44 STDID[4] EXTID[16] (Channel 1) MSG_DATA_7 H'FFFFDB34-3F H'FFFFDB42 STDID[5] EXTID[17] MSG_DATA_5 H'FFFFDB33 H'FFFFDB40 -- MSG_DATA_0 MB17[11], [12] H'FFFFDB31 H'FFFFDB32 -- MSG_DATA_3 H'FFFFDB2F H'FFFFDB30 -- MSG_DATA_2 H'FFFFDB2D H'FFFFDB2E Module MSG_DATA_1 MB17[9], [10] H'FFFFDB2B H'FFFFDB2C Bit 0 -- H'FFFFDB29 H'FFFFDB2A Bit 1 -- H'FFFFDB27 H'FFFFDB28 Bit 2 -- H'FFFFDB25 H'FFFFDB26 Bit 3 -- H'FFFFDB23 H'FFFFDB24 Bit 4 -- 1 H'FFFFDB21 H'FFFFDB22 Bit 5 EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFDB14-1F H'FFFFDB20 Bit 6 MB18[7], [8]* 1 MSG_DATA_0 MSG_DATA_1 Rev. 5.00 Feb. 24, 2010 Page 901 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 H'FFFFDB4A MB18[9], [10] MSG_DATA_2 HCAN1 MSG_DATA_3 (Channel 1) H'FFFFDB4B H'FFFFDB4C MB18[11], [12] MSG_DATA_4 MB18[13], [14] MSG_DATA_6 H'FFFFDB4D H'FFFFDB4E MB18[15], [16] MB18[17], [18] EXTID_LAF EXTID_LA M[17] FM[16] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] STDID[10] STDID[9] STDID[8] STDID[7] STDID[6] STDID[5] STDID[4] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] MB19[2], [3] EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] MB19[4], [5] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] MB19[6] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MB19[7], [8]* 1 -- -- -- MSG_DATA_0 MSG_DATA_1 MB19[9], [10] MSG_DATA_2 MB19[11], [12] MSG_DATA_4 MB19[13], [14] MSG_DATA_6 MB19[15], [16] -- MSG_DATA_3 MSG_DATA_5 H'FFFFDB6F MSG_DATA_7 H'FFFFDB71 H'FFFFDB72 -- STDID[3] H'FFFFDB6D H'FFFFDB70 STDID_LAF STDID_LAF -- M[1] M[0] -- MB19[0], [1]* H'FFFFDB6B H'FFFFDB6E Module STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] -- H'FFFFDB69 H'FFFFDB6C STDID_LA FM[10] -- H'FFFFDB67 H'FFFFDB6A Bit 0 -- H'FFFFDB65 H'FFFFDB68 Bit 1 -- H'FFFFDB63 H'FFFFDB66 Bit 2 -- 1 H'FFFFDB61 H'FFFFDB64 Bit 3 EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFDB54-5F H'FFFFDB62 -- STDID_LAF STDID_LA M[3] FM[2] H'FFFFDB53 H'FFFFDB60 Bit 4 MSG_DATA_7 H'FFFFDB51 H'FFFFDB52 Bit 5 MSG_DATA_5 H'FFFFDB4F H'FFFFDB50 Bit 6 STDID_LA FM[10] STDID_LAF STDID_LA M[3] FM[2] MB19[17], [18] STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] STDID_LAF STDID_LAF -- M[1] M[0] -- EXTID_LAF EXTID_LA M[17] FM[16] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] H'FFFFDB73 EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFDB74-7F -- -- Rev. 5.00 Feb. 24, 2010 Page 902 of 950 REJ09B0177-0500 -- -- -- -- -- -- -- Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation H'FFFFDB80 MB20[0], [1]* 1 H'FFFFDB81 H'FFFFDB82 MB20[2], [3] H'FFFFDB83 H'FFFFDB84 MB20[4], [5] H'FFFFDB85 H'FFFFDB86 MB20[6] H'FFFFDB87 H'FFFFDB88 MB20[7], [8]* 1 H'FFFFDB89 H'FFFFDB8A STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] (Channel 1) EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MSG_DATA_0 STDID_LA FM[10] STDID_LAF STDID_LA M[3] FM[2] MB20[17], [18] STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] STDID_LAF STDID_LAF -- M[1] M[0] -- EXTID_LAF EXTID_LA M[17] FM[16] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] MB21[0], [1]* 1 MB21[2], [3] MB21[4], [5] MB21[6] MB21[7], [8]* 1 -- -- -- -- -- -- -- -- -- -- STDID[10] STDID[9] STDID[8] STDID[7] STDID[6] STDID[5] STDID[4] HCAN1 STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] (Channel 1) EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MSG_DATA_0 MSG_DATA_1 MB21[9], [10] MSG_DATA_2 MSG_DATA_3 MB21[11], [12] MSG_DATA_4 MB21[13], [14] MSG_DATA_6 H'FFFFDBAD H'FFFFDBAF HCAN1 MSG_DATA_7 H'FFFFDBAB H'FFFFDBAE STDID[4] -- H'FFFFDBA9 H'FFFFDBAC STDID[5] MB20[15], [16] H'FFFFDBA7 H'FFFFDBAA STDID[6] MSG_DATA_5 H'FFFFDBA5 H'FFFFDBA8 Module STDID[7] MSG_DATA_6 H'FFFFDBA3 H'FFFFDBA6 Bit 0 STDID[8] MB20[13], [14] H'FFFFDBA1 H'FFFFDBA4 Bit 1 STDID[9] MSG_DATA_3 H'FFFFDB94-9F H'FFFFDBA2 Bit 2 STDID[10] MSG_DATA_4 H'FFFFDB93 H'FFFFDBA0 Bit 3 -- MB20[11], [12] H'FFFFDB91 H'FFFFDB92 Bit 4 MSG_DATA_1 H'FFFFDB8F H'FFFFDB90 Bit 5 MSG_DATA_2 H'FFFFDB8D H'FFFFDB8E Bit 6 MB20[9], [10] H'FFFFDB8B H'FFFFDB8C Bit 7 MSG_DATA_5 MSG_DATA_7 Rev. 5.00 Feb. 24, 2010 Page 903 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 Bit 6 Bit 5 H'FFFFDBB0 MB21[15], [16] -- STDID_LA FM[10] STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA HCAN1 M[9] M[8] M[7] M[6] M[5] FM[4] (Channel 1) STDID_LAF STDID_LAF -- -- EXTID_LAF EXTID_LA M[1] M[0] M[17] FM[16] H'FFFFDBB1 H'FFFFDBB2 STDID_LAF STDID_LA M[3] FM[2] MB21[17], [18] H'FFFFDBB3 MB22[0], [1]* 1 H'FFFFDBC1 H'FFFFDBC2 MB22[2], [3] H'FFFFDBC3 H'FFFFDBC4 MB22[4], [5] H'FFFFDBC5 H'FFFFDBC6 MB22[6] H'FFFFDBC7 H'FFFFDBC8 MB22[7], [8]* 1 H'FFFFDBC9 H'FFFFDBCA -- -- -- -- -- -- STDID[8] STDID[7] STDID[6] STDID[5] STDID[4] HCAN1 STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] (Channel 1) EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MSG_DATA_0 MB22[15], [16] -- MSG_DATA_5 MSG_DATA_7 STDID_LA FM[10] STDID_LAF STDID_LA M[3] FM[2] MB22[17], [18] STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] STDID_LAF STDID_LAF -- M[1] M[0] -- EXTID_LAF EXTID_LA M[17] FM[16] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] MB23[0], [1]* MB23[2], [3] H'FFFFDBE3 H'FFFFDBE5 -- STDID[9] MSG_DATA_6 H'FFFFDBE1 H'FFFFDBE4 -- STDID[10] MB22[13], [14] H'FFFFDBD4-DF H'FFFFDBE2 -- -- MSG_DATA_4 H'FFFFDBD3 H'FFFFDBE0 Module EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] MB22[11], [12] H'FFFFDBD1 H'FFFFDBD2 Bit 0 MSG_DATA_3 H'FFFFDBCF H'FFFFDBD0 Bit 1 MSG_DATA_1 H'FFFFDBCD H'FFFFDBCE Bit 2 MSG_DATA_2 MB22[9], [10] H'FFFFDBCB H'FFFFDBCC Bit 3 EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFDBB4-BF H'FFFFDBC0 Bit 4 MB23[4], [5] 1 -- -- -- -- -- -- -- -- -- -- STDID[10] STDID[9] STDID[8] STDID[7] STDID[6] STDID[5] STDID[4] HCAN1 STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] (Channel 1) EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] Rev. 5.00 Feb. 24, 2010 Page 904 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFDBE6 MB23[6] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] HCAN1 (Channel 1) TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] H'FFFFDBE7 H'FFFFDBE8 MB23[7], [8]* 1 H'FFFFDBE9 H'FFFFDBEA MSG_DATA_1 MB23[9], [10] MSG_DATA_2 MB23[11], [12] MSG_DATA_4 H'FFFFDBEB H'FFFFDBEC MSG_DATA_3 H'FFFFDBED H'FFFFDBEE MSG_DATA_5 MB23[13], [14] MSG_DATA_6 MB23[15], [16] -- H'FFFFDBEF H'FFFFDBF0 MSG_DATA_7 H'FFFFDBF1 H'FFFFDBF2 MB23[17], [18] -- -- -- -- -- -- -- STDID[9] STDID[8] STDID[7] STDID[6] STDID[5] STDID[4] HCAN1 STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] (Channel 1) MB24[2], [3] EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] MB24[4], [5] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MB24[6] MB24[7], [8]* 1 H'FFFFDC09 MB24[9], [10] MSG_DATA_2 MB24[11], [12] MSG_DATA_4 MSG_DATA_3 H'FFFFDC0D H'FFFFDC0E MSG_DATA_5 MB24[13], [14] MSG_DATA_6 MB24[15], [16] -- H'FFFFDC0F H'FFFFDC10 H'FFFFDC11 MSG_DATA_0 MSG_DATA_1 H'FFFFDC0B H'FFFFDC0C EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] -- H'FFFFDC07 H'FFFFDC0A EXTID_LAF EXTID_LA M[17] FM[16] STDID[10] H'FFFFDC05 H'FFFFDC08 -- -- 1 H'FFFFDC03 H'FFFFDC06 STDID_LAF STDID_LAF -- M[1] M[0] -- MB24[0], [1]* H'FFFFDC01 H'FFFFDC04 STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFDBF4-FF H'FFFFDC02 STDID_LA FM[10] STDID_LAF STDID_LA M[3] FM[2] H'FFFFDBF3 H'FFFFDC00 MSG_DATA_0 MSG_DATA_7 STDID_LA FM[10] STDID_LAF STDID_LA M[3] FM[2] STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] STDID_LAF STDID_LAF -- M[1] M[0] -- EXTID_LAF EXTID_LA M[17] FM[16] Rev. 5.00 Feb. 24, 2010 Page 905 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 H'FFFFDC12 MB24[17], [18] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA HCAN1 M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] (Channel 1) H'FFFFDC13 -- -- STDID[10] STDID[9] STDID[8] STDID[7] STDID[6] STDID[5] STDID[4] STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] MB25[4], [5] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] MB25[6] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MB25[0], [1]* MB25[2], [3] MB25[7], [8]* 1 MB25[11], [12] MSG_DATA_4 MB25[13], [14] MSG_DATA_6 MSG_DATA_5 MSG_DATA_7 MB25[15], [16] H'FFFFDC31 H'FFFFDC32 MB25[17], [18] MB26[0], [1]* 1 H'FFFFDC41 H'FFFFDC49 -- EXTID_LAF EXTID_LA M[17] FM[16] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] -- -- -- -- -- -- -- -- -- STDID[10] STDID[9] STDID[8] STDID[7] STDID[6] STDID[5] STDID[4] STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] MB26[4], [5] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] MB26[6] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] H'FFFFDC47 H'FFFFDC48 STDID_LAF STDID_LAF -- M[1] M[0] EXTID[15] H'FFFFDC45 H'FFFFDC46 STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] MB26[2], [3] H'FFFFDC43 H'FFFFDC44 STDID_LA FM[10] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFDC34-3F H'FFFFDC42 -- STDID_LAF STDID_LA M[3] FM[2] H'FFFFDC33 H'FFFFDC40 MSG_DATA_0 MSG_DATA_3 H'FFFFDC2F H'FFFFDC30 -- MSG_DATA_2 H'FFFFDC2D H'FFFFDC2E -- MSG_DATA_1 MB25[9], [10] H'FFFFDC2B H'FFFFDC2C Bit 0 -- H'FFFFDC29 H'FFFFDC2A Bit 1 -- H'FFFFDC27 H'FFFFDC28 Bit 2 -- H'FFFFDC25 H'FFFFDC26 Bit 3 -- H'FFFFDC23 H'FFFFDC24 Bit 4 -- 1 H'FFFFDC21 H'FFFFDC22 Bit 5 EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFDC14-1F H'FFFFDC20 Bit 6 MB26[7], [8]* 1 MSG_DATA_0 MSG_DATA_1 Rev. 5.00 Feb. 24, 2010 Page 906 of 950 REJ09B0177-0500 Module Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 H'FFFFDC4A MB26[9], [10] MSG_DATA_2 HCAN1 MSG_DATA_3 (Channel 1) H'FFFFDC4B H'FFFFDC4C MB26[11], [12] MSG_DATA_4 MB26[13] ,[14] MSG_DATA_6 H'FFFFDC4D H'FFFFDC4E MB26[15], [16] MB26[17], [18] EXTID_LAF EXTID_LA M[17] FM[16] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] STDID[10] STDID[9] STDID[8] STDID[7] STDID[6] STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE MB27[2], [3] EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] MB27[4], [5] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] MB27[6] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MB27[7], [8]* 1 -- -- -- STDID[5] STDID[4] HCAN1 EXTID[17] EXTID[16] (Channel 1) MSG_DATA_0 MSG_DATA_1 MB27[9],[10] MSG_DATA_2 MB27[11], [12] MSG_DATA_4 MB27[13],[14] MSG_DATA_6 MB27[15], [16] -- MSG_DATA_3 MSG_DATA_5 H'FFFFDC6F MSG_DATA_7 H'FFFFDC71 H'FFFFDC72 -- -- MB27[0], [1]* H'FFFFDC6D H'FFFFDC70 STDID_LAF STDID_LAF -- M[1] M[0] -- H'FFFFDC6B H'FFFFDC6E Module STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] -- H'FFFFDC69 H'FFFFDC6C STDID_LA FM[10] -- H'FFFFDC67 H'FFFFDC6A Bit 0 -- H'FFFFDC65 H'FFFFDC68 Bit 1 -- H'FFFFDC63 H'FFFFDC66 Bit 2 -- 1 H'FFFFDC61 H'FFFFDC64 Bit 3 EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFDC54-5F H'FFFFDC62 -- STDID_LAF STDID_LA M[3] FM[2] H'FFFFDC53 H'FFFFDC60 Bit 4 MSG_DATA_7 H'FFFFDC51 H'FFFFDC52 Bit 5 MSG_DATA_5 H'FFFFDC4F H'FFFFDC50 Bit 6 STDID_LA FM[10] STDID_LAF STDID_LA M[3] FM[2] MB27[17], [18] STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] STDID_LAF STDID_LAF -- M[1] M[0] -- EXTID_LAF EXTID_LA M[17] FM[16] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] H'FFFFDC73 EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFDC74-7F -- -- -- -- -- -- -- -- -- Rev. 5.00 Feb. 24, 2010 Page 907 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation H'FFFFDC80 MB28[0], [1]* 1 H'FFFFDC81 H'FFFFDC82 MB28[2], [3] H'FFFFDC83 H'FFFFDC84 MB28[4], [5] H'FFFFDC85 H'FFFFDC86 MB28[6] H'FFFFDC87 H'FFFFDC88 MB28 [7], [8]* 1 MB28[17], [18] STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] (Channel 1) EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MSG_DATA_0 STDID_LA FM[10] STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] STDID_LAF STDID_LAF -- M[1] M[0] -- EXTID_LAF EXTID_LA M[17] FM[16] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] MB29[0], [1]* 1 MB29[2], [3] MB29[4],[5] MB29[6] MB29[7],[8]* 1 -- -- -- -- -- -- -- -- STDID[10] STDID[9] STDID[8] STDID[7] STDID[6] STDID[5] STDID[4] STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MSG_DATA_0 MSG_DATA_1 MB29[9],[10] MSG_DATA_2 MB29[11],[12] MSG_DATA_4 MB29[13],[14] MSG_DATA_6 MSG_DATA_3 H'FFFFDCAD H'FFFFDCAF STDID[2] STDID_LAF STDID_LA M[3] FM[2] H'FFFFDCAB H'FFFFDCAE HCAN1 STDID[3] MSG_DATA_7 H'FFFFDCA9 H'FFFFDCAC STDID[4] -- H'FFFFDCA7 H'FFFFDCAA STDID[5] MB28[15], [16] H'FFFFDCA5 H'FFFFDCA8 STDID[6] MSG_DATA_5 H'FFFFDCA3 H'FFFFDCA6 Module STDID[7] MSG_DATA_6 H'FFFFDCA1 H'FFFFDCA4 Bit 0 STDID[8] MB28[13], [14] H'FFFFDC94-7F H'FFFFDCA2 Bit 1 STDID[9] MSG_DATA_3 H'FFFFDC93 H'FFFFDCA0 Bit 2 STDID[10] MSG_DATA_4 H'FFFFDC91 H'FFFFDC92 Bit 3 -- MB28[11], [12] H'FFFFDC8F H'FFFFDC90 Bit 4 MSG_DATA_2 H'FFFFDC8D H'FFFFDC8E Bit 5 MB28[9], [10] H'FFFFDC8B H'FFFFDC8C Bit 6 MSG_DATA_1 H'FFFFDC89 H'FFFFDC8A Bit 7 MSG_DATA_5 MSG_DATA_7 Rev. 5.00 Feb. 24, 2010 Page 908 of 950 REJ09B0177-0500 -- Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 Bit 6 Bit 5 H'FFFFDCB0 MB29[15], [16] -- STDID_LA FM[10] STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA HCAN1 M[9] M[8] M[7] M[6] M[5] FM[4] (Channel 1) H'FFFFDCB1 H'FFFFDCB2 STDID_LAF STDID_LA M[3] FM[2] MB29[17], [18] H'FFFFDCB3 MB30[0], [1]* 1 H'FFFFDCC1 H'FFFFDCC2 MB30[2], [3] H'FFFFDCC3 H'FFFFDCC4 MB30[4], [5] H'FFFFDCC5 H'FFFFDCC6 MB30[6] H'FFFFDCC7 H'FFFFDCC8 MB30[7], [8]* 1 -- -- -- -- -- STDID[8] STDID[7] STDID[6] STDID[5] STDID[4] HCAN1 STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] (Channel 1) EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] MSG_DATA_0 MB30[15], [16] -- MSG_DATA_5 MSG_DATA_7 STDID_LA FM[10] STDID_LAF STDID_LA M[3] FM[2] MB30[17], [18] STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] STDID_LAF STDID_LAF -- M[1] M[0] -- EXTID_LAF EXTID_LA M[17] FM[16] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] MB31[0], [1]* MB31[2], [3] H'FFFFDCE3 H'FFFFDCE5 -- MSG_DATA_6 H'FFFFDCE1 H'FFFFDCE4 -- STDID[9] MB30[13],[14] H'FFFFDCD4-DF H'FFFFDCE2 -- MSG_DATA_3 H'FFFFDCD3 H'FFFFDCE0 EXTID_LAF EXTID_LA M[17] FM[16] STDID[10] MSG_DATA_4 H'FFFFDCD1 H'FFFFDCD2 Module -- MB30[11],[12] H'FFFFDCCF H'FFFFDCD0 Bit 0 -- MSG_DATA_2 H'FFFFDCCD H'FFFFDCCE -- Bit 1 EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] MB30[9],[10] H'FFFFDCCB H'FFFFDCCC STDID_LAF STDID_LAF -- M[1] M[0] Bit 2 MSG_DATA_1 H'FFFFDCC9 H'FFFFDCCA Bit 3 EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFDCB4-BF H'FFFFDCC0 Bit 4 MB31[4], [5] 1 -- -- -- -- -- -- -- -- -- -- STDID[10] STDID[9] STDID[8] STDID[7] STDID[6] STDID[5] STDID[4] HCAN1 STDID[3] STDID[2] STDID[1] STDID[0] RTR IDE EXTID[17] EXTID[16] (Channel 1) EXTID[15] EXTID[14] EXTID[13] EXTID[12] EXTID[11] EXTID[10] EXTID[9] EXTID[8] EXTID[7] EXTID[6] EXTID[5] EXTID[4] EXTID[3] EXTID[2] EXTID[1] EXTID[0] CCM TTE NMC ATX DART MBC[2] MBC[1] MBC[0] -- TCT -- CLE DLC[3] DLC[2] DLC[1] DLC[0] Rev. 5.00 Feb. 24, 2010 Page 909 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFDCE6 MB31[6] TMSTP [15] TMSTP [14] TMSTP [13] TMSTP [12] TMSTP [11] TMSTP [10] TMSTP [9] TMSTP [8] HCAN1 (Channel 1) TMSTP[7] TMSTP[6] TMSTP[5] TMSTP[4] TMSTP[3] TMSTP[2] TMSTP[1] TMSTP[0] H'FFFFDCE7 H'FFFFDCE8 MB31[7], [8]* 1 H'FFFFDCE9 H'FFFFDCEA MSG_DATA_1 MB31[9], [10] MSG_DATA_2 MB31[11], [12] MSG_DATA_4 MB31[13], [14] MSG_DATA_6 MB31[15], [16] -- H'FFFFDCEB H'FFFFDCEC MSG_DATA_3 H'FFFFDCED H'FFFFDCEE MSG_DATA_5 H'FFFFDCEF H'FFFFDCF0 MSG_DATA_7 H'FFFFDCF1 H'FFFFDCF2 MSG_DATA_0 STDID_LA FM[10] STDID_LAF STDID_LA M[3] FM[2] MB31[17], [18] STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LAF STDID_LA M[9] M[8] M[7] M[6] M[5] FM[4] STDID_LAF STDID_LAF -- M[1] M[0] -- EXTID_LAF EXTID_LA M[17] FM[16] EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[15] M[14] M[13] M[12] M[11] M[10] M[9] FM[8] H'FFFFDCF3 EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LAF EXTID_LA M[7] M[6] M[5] M[4] M[3] M[2] M[1] FM[0] H'FFFFDCF4-7FF -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- FLASH H'FFFFE730 to H'FFFFE7FF -- H'FFFFE800 FCCS FEW -- -- FLER -- -- -- SCO H'FFFFE801 FPCS -- -- -- -- -- -- -- PPVS H'FFFFE802 FECS -- -- -- -- -- -- -- EPVB H'FFFFE803 -- H'FFFFE804 FKEY K7 K6 K5 K4 K3 K2 K1 K0 H'FFFFE805 FMATS MS7 MS6 MS5 MS4 MS3 MS2 MS1 MS0 H'FFFFE806 FTDAR TDER TDA6 TDA5 TDA4 TDA3 TDA2 TDA1 TDA0 H'FFFFE807 to H'FFFFEBFF -- H'FFFFEC00 UBARH H'FFFFEC01 H'FFFFEC02 UBARL H'FFFFEC03 H'FFFFEC04 UBAMRH H'FFFFEC05 H'FFFFEC06 H'FFFFEC07 UBAMRL System area (access prohibited) System area (access prohibited) UBA31 UBA30 UBA29 UBA28 UBA27 UBA26 UBA25 UBA24 UBA23 UBA22 UBA21 UBA20 UBA19 UBA18 UBA17 UBA16 UBA15 UBA14 UBA13 UBA12 UBA11 UBA10 UBA9 UBA8 UBA7 UBA6 UBA5 UBA4 UBA3 UBA2 UBA1 UBA0 UBM31 UBM30 UBM29 UBM28 UBM27 UBM26 UBM25 UBM24 UBM23 UBM22 UBM21 UBM20 UBM19 UBM18 UBM17 UBM16 UBM15 UBM14 UBM13 UBM12 UBM11 UBM10 UBM9 UBM8 UBM7 UBM6 UBM5 UBM4 UBM3 UBM2 UBM1 UBM0 Rev. 5.00 Feb. 24, 2010 Page 910 of 950 REJ09B0177-0500 UBC Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFEC08 UBBR -- -- -- -- -- -- -- -- UBC CP1 CP0 ID1 ID0 RW1 RW0 SZ1 SZ0 -- -- -- -- -- -- -- -- -- -- -- -- -- CKS1 CKS0 UBID -- -- -- -- -- -- -- -- -- OVF WT/IT TME -- -- CKS2 CKS1 CKS0 WDT -- -- -- -- -- -- -- -- WOVF RSTE RSTS -- -- -- -- -- H'FFFFEC09 H'FFFFEC0A UBCR H'FFFFEC0B H'FFFFEC0C to H'FFFFEC0F -- H'FFFFEC10 TCSR* 1 1 H'FFFFEC11 TCNT* H'FFFFEC12 -- H'FFFFEC13 RSTCSR* H'FFFFEC14 SBYCR SSBY -- SSBYF -- -- -- -- -- Power-Down state H'FFFFEC15 to H'FFFFEC1F -- -- -- -- -- -- -- -- -- -- H'FFFFEC20 BCR1 -- -- -- -- -- -- -- -- BSC -- -- -- -- A3SZ A2SZ A1SZ A0SZ BCR2 IW31 IW30 IW21 IW20 IW11 IW10 IW01 IW00 CW3 CW2 CW1 CW0 SW3 SW2 SW1 SW0 WCR -- W32 W31 W30 -- W22 W21 W20 H'FFFFEC21 H'FFFFEC22 H'FFFFEC23 H'FFFFEC24 H'FFFFEC25 H'FFFFEC26 RAMER* 2 RAMER* 3 H'FFFFEC27 H'FFFFEC26 H'FFFFEC27 H'FFFFEC28 to H'FFFFECAF -- 1 -- W12 W11 W10 -- W02 W01 W00 -- -- -- -- -- -- -- -- -- -- -- -- RAMS RAM2 RAM1 RAM0 -- -- -- -- -- -- -- -- -- -- -- -- RAMS -- -- RAM0 -- -- -- -- -- -- -- -- -- Rev. 5.00 Feb. 24, 2010 Page 911 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFECB0 DMAOR -- -- -- -- -- -- -- -- DMAC -- -- -- -- -- AE NMIF DME (Common) -- -- -- -- -- -- -- -- -- H'FFFFECB1 H'FFFFECB2 to H'FFFFECBF -- H'FFFFECC0 SAR0 DMAC (Channel 0) H'FFFFECC1 H'FFFFECC2 H'FFFFECC3 H'FFFFECC4 DAR0 H'FFFFECC5 H'FFFFECC6 H'FFFFECC7 H'FFFFECC8 DMATCR0 -- -- -- -- -- -- -- -- H'FFFFECC9 H'FFFFECCA H'FFFFECCB H'FFFFECCC -- -- -- DI -- -- -- RO H'FFFFECCD -- -- -- RS4 RS3 RS2 RS1 RS0 H'FFFFECCE -- -- SM1 SM0 -- -- DM1 DM0 H'FFFFECCF -- -- TS1 TS0 TM IE TE DE H'FFFFECD0 CHCR0 DMAC SAR1 (Channel 1) H'FFFFECD1 H'FFFFECD2 H'FFFFECD3 H'FFFFECD4 DAR1 H'FFFFECD5 H'FFFFECD6 H'FFFFECD7 H'FFFFECD8 DMATCR1 -- -- -- -- -- -- -- -- CHCR1 -- -- -- DI -- -- -- RO H'FFFFECDD -- -- -- RS4 RS3 RS2 RS1 RS0 H'FFFFECDE -- -- SM1 SM0 -- -- DM1 DM0 H'FFFFECDF -- -- TS1 TS0 TM IE TE DE H'FFFFECD9 H'FFFFECDA H'FFFFECDB H'FFFFECDC H'FFFFECE0 SAR2 H'FFFFECE1 H'FFFFECE2 H'FFFFECE3 Rev. 5.00 Feb. 24, 2010 Page 912 of 950 REJ09B0177-0500 DMAC (Channel 2) Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation H'FFFFECE4 DAR2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module DMAC (Channel 2) H'FFFFECE5 H'FFFFECE6 H'FFFFECE7 H'FFFFECE8 DMATCR2 -- -- -- -- -- -- -- -- H'FFFFECE9 H'FFFFECEA H'FFFFECEB H'FFFFECEC -- -- -- DI -- -- -- RO H'FFFFECED -- -- -- RS4 RS3 RS2 RS1 RS0 H'FFFFECEE -- -- SM1 SM0 -- -- DM1 DM0 H'FFFFECEF -- -- TS1 TS0 TM IE TE DE H'FFFFECF0 CHCR2 SAR3 DMAC (Channel 3) H'FFFFECF1 H'FFFFECF2 H'FFFFECF3 H'FFFFECF4 DAR3 H'FFFFECF5 H'FFFFECF6 H'FFFFECF7 H'FFFFECF8 DMATCR3 -- -- -- -- -- -- -- -- H'FFFFECF9 H'FFFFECFA H'FFFFECFB H'FFFFECFC -- -- -- DI -- -- -- RO H'FFFFECFD -- -- -- RS4 RS3 RS2 RS1 RS0 H'FFFFECFE -- -- SM1 SM0 -- -- DM1 DM0 H'FFFFECFF -- -- TS1 TS0 TM IE TE DE H'FFFFED00 CHCR3 IPRA INTC H'FFFFED01 H'FFFFED02 IPRB H'FFFFED03 H'FFFFED04 IPRC H'FFFFED05 H'FFFFED06 IPRD H'FFFFED07 H'FFFFED08 IPRE H'FFFFED09 H'FFFFED0A IPRF H'FFFFED0B H'FFFFED0C IPRG H'FFFFED0D Rev. 5.00 Feb. 24, 2010 Page 913 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation H'FFFFED0E IPRH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module INTC H'FFFFED0F H'FFFFED10 IPRI H'FFFFED11 H'FFFFED12 IPRJ H'FFFFED13 H'FFFFED14 IPRK H'FFFFED15 H'FFFFED16 IPRL H'FFFFED17 H'FFFFED18 ICR NMIL IRQ0S IRQ1S IRQ2S IRQ3S IRQ4S IRQ5S IRQ6S IRQ7S ISR -- -- -- -- -- -- -- -- IRQ0F IRQ1F IRQ2F IRQ3F IRQ4F IRQ5F IRQ6F IRQ7F H'FFFFED19 H'FFFFED1A H'FFFFED1B -- -- -- -- -- -- NMIE H'FFFFED1C to H'FFFFEFFF -- -- -- -- -- -- -- -- -- -- H'FFFFF000 SMR0 C/A CHR PE O/E STOP MP CKS1 CKS0 SCI H'FFFFF001 BRR0 H'FFFFF002 SCR0 H'FFFFF003 TDR0 H'FFFFF004 SSR0 H'FFFFF005 RDR0 H'FFFFF006 SDCR0 -- -- -- -- DIR -- -- -- H'FFFFF007 -- -- -- -- -- -- -- -- -- H'FFFFF008 SMR1 C/A CHR PE O/E STOP MP CKS1 CKS0 H'FFFFF009 BRR1 H'FFFFF00A SCR1 TIE RIE TE RE MPIE TEIE CKE1 CKE0 TDRE RDRF ORER FER PER TEND MPB MPBT (Channel 0) TIE RIE TE RE MPIE TEIE CKE1 CKE0 TDRE RDRF ORER FER PER TEND MPB MPBT SCI (Channel 1) H'FFFFF00B TDR1 H'FFFFF00C SSR1 H'FFFFF00D RDR1 H'FFFFF00E SDCR1 -- -- -- -- DIR -- -- -- H'FFFFF00F -- -- -- -- -- -- -- -- -- H'FFFFF010 SMR2 C/A CHR PE O/E STOP MP CKS1 CKS0 H'FFFFF011 BRR2 H'FFFFF012 SCR2 H'FFFFF013 TDR2 H'FFFFF014 SSR2 H'FFFFF015 RDR2 H'FFFFF016 SDCR2 -- -- -- -- DIR -- -- -- H'FFFFF017 -- -- -- -- -- -- -- -- -- SCI (Channel 2) TIE RIE TE RE MPIE TEIE CKE1 CKE0 TDRE RDRF ORER FER PER TEND MPB MPBT Rev. 5.00 Feb. 24, 2010 Page 914 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation H'FFFFF018 SMR3 H'FFFFF019 BRR3 H'FFFFF01A SCR3 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module PE O/E STOP MP CKS1 CKS0 SCI RIE TE RE MPIE TEIE CKE1 CKE0 TDRE RDRF ORER FER PER TEND MPB MPBT Bit 7 Bit 6 Bit 5 C/A CHR TIE (Channel 3) H'FFFFF01B TDR3 H'FFFFF01C SSR3 H'FFFFF01D RDR3 H'FFFFF01E SDCR3 -- -- -- -- DIR -- -- -- H'FFFFF01F -- -- -- -- -- -- -- -- -- H'FFFFF020 SMR4 C/A CHR PE O/E STOP MP CKS1 CKS0 H'FFFFF021 BRR4 H'FFFFF022 SCR4 H'FFFFF023 TDR4 H'FFFFF024 SSR4 H'FFFFF025 RDR4 H'FFFFF026 H'FFFFF027 to H'FFFFF3FF SCI (Channel 4) TIE RIE TE RE MPIE TEIE CKE1 CKE0 TDRE RDRF ORER FER PER TEND MPB MPBT SDCR4 -- -- -- -- DIR -- -- -- -- -- -- -- -- -- -- -- -- -- H'FFFFF400 TSTR2 STR7D STR7C STR7B STR7A STR6D STR6C STR6B STR6A ATU-II H'FFFFF401 TSTR1 STR10 STR5 STR4 STR3 STR1B,2B STR2A STR1A STR0 (Common) H'FFFFF402 TSTR3 -- -- -- -- -- -- -- STR11 H'FFFFF403 -- -- -- -- -- -- -- -- -- H'FFFFF404 PSCR1 -- -- -- PSC1E PSC1D PSC1C PSC1B PSC1A H'FFFFF405 -- -- -- -- -- -- -- -- -- H'FFFFF406 PSCR2 PSC2E PSC2D PSC2C PSC2B PSC2A H'FFFFF407 -- -- -- -- -- -- -- -- -- H'FFFFF408 PSCR3 -- -- -- PSC3E PSC3D PSC3C PSC3B PSC3A H'FFFFF409 -- -- -- -- -- -- -- -- -- H'FFFFF40A PSCR4 -- -- -- PSC4E PSC4D PSC4C PSC4B PSC4A H'FFFFF40B -- -- -- -- -- -- -- -- -- H'FFFFF40C to H'FFFFF41F -- -- -- -- -- -- -- -- -- H'FFFFF420 ICR0DH ATU-II (Channel 0) H'FFFFF421 H'FFFFF422 -- ICR0DL H'FFFFF423 H'FFFFF424 ITVRR1 ITVA9 ITVA8 ITVA7 ITVA6 ITVE9 ITVE8 ITVE7 ITVE6 H'FFFFF425 -- -- -- -- -- -- -- -- -- H'FFFFF426 ITVRR2A ITVA13A ITVA12A ITVA11A ITVA10A ITVE13A ITVE12A ITVE11A ITVE10A H'FFFFF427 -- -- -- -- -- -- -- -- -- H'FFFFF428 ITVRR2B ITVA13B ITVA12B ITVA11B ITVA10B ITVE13B ITVE12B ITVE11B ITVE10B H'FFFFF429 -- -- -- -- -- -- -- -- -- Rev. 5.00 Feb. 24, 2010 Page 915 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFF42A TIOR0 IO0D1 IO0D0 IO0C1 IO0C0 IO0B1 IO0B0 IO0A1 IO0A0 ATU-II H'FFFFF42B -- -- -- -- -- -- -- -- -- (Channel 0) H'FFFFF42C TSR0 -- -- -- -- -- -- -- -- IIF2B IIF2A IIF1 OVF0 ICF0D ICF0C ICF0B ICF0A TIER0 -- -- -- -- -- -- -- -- -- -- -- OVE0 ICE0D ICE0C ICE0B ICE0A H'FFFFF42D H'FFFFF42E H'FFFFF42F H'FFFFF430 TCNT0H H'FFFFF431 H'FFFFF432 TCNT0L H'FFFFF433 H'FFFFF434 ICR0AH H'FFFFF435 H'FFFFF436 ICR0AL H'FFFFF437 H'FFFFF438 ICR0BH H'FFFFF439 H'FFFFF43A ICR0BL H'FFFFF43B H'FFFFF43C ICR0CH H'FFFFF43D H'FFFFF43E ICR0CL H'FFFFF43F H'FFFFF440 TCNT1A H'FFFFF442 TCNT1B H'FFFFF443 H'FFFFF444 GR1A H'FFFFF445 H'FFFFF446 GR1B H'FFFFF447 H'FFFFF448 GR1C H'FFFFF449 H'FFFFF44A GR1D H'FFFFF44B H'FFFFF44C GR1E H'FFFFF44D H'FFFFF44E GR1F H'FFFFF44F H'FFFFF450 GR1G H'FFFFF451 H'FFFFF452 ATU-II (Channel 1) H'FFFFF441 GR1H H'FFFFF453 Rev. 5.00 Feb. 24, 2010 Page 916 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation H'FFFFF454 OCR1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ATU-II (Channel 1) H'FFFFF455 H'FFFFF456 Module OSBR1 H'FFFFF457 H'FFFFF458 TIOR1B -- IO1D2 IO1D1 IO1D0 -- IO1C2 IO1C1 H'FFFFF459 TIOR1A -- IO1B2 IO1B1 IO1B0 -- IO1A2 IO1A1 IO1A0 H'FFFFF45A TIOR1D -- IO1H2 IO1H1 IO1H0 -- IO1G2 IO1G1 IO1G0 H'FFFFF45B TIOR1C -- IO1F2 IO1F1 IO1F0 -- IO1E2 IO1E1 IO1E0 H'FFFFF45C TCR1B -- -- CKEGB1 CKEGB0 CKSELB3 CKSELB2 CKSELB1 CKSELB0 H'FFFFF45D TCR1A -- -- CKEGA1 CKEGA0 CKSELA3 CKSELA2 CKSELA1 CKSELA0 H'FFFFF45E TSR1A -- -- -- -- -- -- -- OVF1A IMF1H IMF1G IMF1F IMF1E IMF1D IMF1C IMF1B IMF1A TSR1B -- -- -- -- -- -- -- OVF1B -- -- -- -- -- -- -- CMF1 TIER1A -- -- -- -- -- -- -- OVE1A IME1H IME1G IME1F IME1E IME1D IME1C IME1B IME1A TIER1B -- -- -- -- -- -- -- OVE1B -- -- -- -- -- -- -- CME1 H'FFFFF466 TRGMDR TRGMD -- -- -- -- -- -- -- H'FFFFF467 to H'FFFFF47F -- -- -- -- -- -- -- -- -- -- H'FFFFF480 TSR3 -- OVF5 IMF5D IMF5C IMF5B IMF5A OVF4 IMF4D ATU-II IMF4C IMF4B IMF4A OVF3 IMF3D IMF3C IMF3B IMF3A (Channel 3 to 5) TIER3 -- OVE5 IME5D IME5C IME5B IME5A OVE4 IME4D IME4C IME4B IME4A OVE3 IME3D IME3C IME3B IME3A H'FFFFF484 TMDR -- -- -- -- -- T5PWM T4PWM T3PWM H'FFFFF485 to H'FFFFF49F -- -- -- -- -- -- -- -- -- H'FFFFF4A0 TCNT3 H'FFFFF45F H'FFFFF460 H'FFFFF461 H'FFFFF462 H'FFFFF463 H'FFFFF464 H'FFFFF465 H'FFFFF481 H'FFFFF482 H'FFFFF483 IO1C0 ATU-II (Channel 3) H'FFFFF4A1 H'FFFFF4A2 -- GR3A H'FFFFF4A3 H'FFFFF4A4 GR3B H'FFFFF4A5 H'FFFFF4A6 GR3C H'FFFFF4A7 H'FFFFF4A8 GR3D H'FFFFF4A9 H'FFFFF4AA TIOR3B CCI3D IO3D2 IO3D1 IO3D0 CCI3C IO3C2 IO3C1 H'FFFFF4AB TIOR3A CCI3B IO3B2 IO3B1 IO3B0 CCI3A IO3A2 IO3A1 IO3C0 IO3A0 H'FFFFF4AC TCR3 -- -- CKEG1 CKEG0 CKSEL3 CKSEL2 CKSEL1 CKSEL0 Rev. 5.00 Feb. 24, 2010 Page 917 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFF4AD to H'FFFFF4BF -- -- -- -- -- -- -- -- -- -- H'FFFFF4C0 TCNT4 ATU-II (Channel 4) H'FFFFF4C1 H'FFFFF4C2 GR4A H'FFFFF4C3 H'FFFFF4C4 GR4B H'FFFFF4C5 H'FFFFF4C6 GR4C H'FFFFF4C7 H'FFFFF4C8 GR4D H'FFFFF4C9 H'FFFFF4CA TIOR4B CCI4D IO4D2 IO4D1 IO4D0 CCI4C IO4C2 IO4C1 H'FFFFF4CB TIOR4A CCI4B IO4B2 IO4B1 IO4B0 CCI4A IO4A2 IO4A1 IO4C0 IO4A0 H'FFFFF4CC TCR4 -- -- CKEG1 CKEG0 CKSEL3 CKSEL2 CKSEL1 CKSEL0 H'FFFFF4CD to H'FFFFF4DF -- -- -- -- -- -- -- -- -- H'FFFFF4E0 TCNT5 ATU-II (Channel 5) H'FFFFF4E1 H'FFFFF4E2 -- GR5A H'FFFFF4E3 H'FFFFF4E4 GR5B H'FFFFF4E5 H'FFFFF4E6 GR5C H'FFFFF4E7 H'FFFFF4E8 GR5D H'FFFFF4E9 H'FFFFF4EA TIOR5B CCI5D IO5D2 IO5D1 IO5D0 CCI5C IO5C2 IO5C1 H'FFFFF4EB TIOR5A CCI5B IO5B2 IO5B1 IO5B0 CCI5A IO5A2 IO5A1 IO5A0 H'FFFFF4EC TCR5 -- -- CKEG1 CKEG0 CKSEL3 CKSEL2 CKSEL1 CKSEL0 H'FFFFF4ED to H'FFFFF4EF -- -- -- -- -- -- -- -- -- H'FFFFF500 TCNT6A TCNT6B H'FFFFF503 H'FFFFF504 TCNT6C H'FFFFF505 H'FFFFF506 -- ATU-II (Channel 6) H'FFFFF501 H'FFFFF502 IO5C0 TCNT6D H'FFFFF507 Rev. 5.00 Feb. 24, 2010 Page 918 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation H'FFFFF508 CYLR6A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ATU-II (Channel 6) H'FFFFF509 H'FFFFF50A Module CYLR6B H'FFFFF50B H'FFFFF50C CYLR6C H'FFFFF50D H'FFFFF50E CYLR6D H'FFFFF50F H'FFFFF510 BFR6A H'FFFFF511 H'FFFFF512 BFR6B H'FFFFF513 H'FFFFF514 BFR6C H'FFFFF515 H'FFFFF516 BFR6D H'FFFFF517 H'FFFFF518 DTR6A H'FFFFF519 H'FFFFF51A DTR6B H'FFFFF51B H'FFFFF51C DTR6C H'FFFFF51D H'FFFFF51E DTR6D H'FFFFF51F H'FFFFF520 TCR6B -- CKSELD2 CKSELD1 CKSELD0 -- CKSELC2 CKSELC1 CKSELC0 H'FFFFF521 TCR6A -- CKSELB2 CKSELB1 CKSELB0 -- CKSELA2 CKSELA1 CKSELA0 H'FFFFF522 TSR6 -- -- -- -- -- -- -- -- UD6D UD6C UD6B UD6A CMF6D CMF6C CMF6B CMF6A TIER6 -- -- -- -- -- -- -- -- -- -- -- -- CME6D CME6C CME6B CME6A H'FFFFF526 PMDR DTSELD DTSELC DTSELB DTSELA CNTSELD CNTSELC CNTSELB CNTSELA H'FFFFF527 to H'FFFFF57F -- -- -- -- -- -- -- -- -- H'FFFFF580 TCNT7A H'FFFFF523 H'FFFFF524 H'FFFFF525 ATU-II (Channel 7) H'FFFFF581 H'FFFFF582 -- TCNT7B H'FFFFF583 H'FFFFF584 TCNT7C H'FFFFF585 H'FFFFF586 TCNT7D H'FFFFF587 Rev. 5.00 Feb. 24, 2010 Page 919 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation H'FFFFF588 CYLR7A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ATU-II (Channel 7) H'FFFFF589 H'FFFFF58A Module CYLR7B H'FFFFF58B H'FFFFF58C CYLR7C H'FFFFF58D H'FFFFF58E CYLR7D H'FFFFF58F H'FFFFF590 BFR7A H'FFFFF591 H'FFFFF592 BFR7B H'FFFFF593 H'FFFFF594 BFR7C H'FFFFF595 H'FFFFF596 BFR7D H'FFFFF597 H'FFFFF598 DTR7A H'FFFFF599 H'FFFFF59A DTR7B H'FFFFF59B H'FFFFF59C DTR7C H'FFFFF59D H'FFFFF59E DTR7D H'FFFFF59F H'FFFFF5A0 TCR7B -- CKSELD2 CKSELD1 CKSELD0 -- CKSELC2 CKSELC1 CKSELC0 H'FFFFF5A1 TCR7A -- CKSELB2 CKSELB1 CKSELB0 -- CKSELA2 CKSELA1 CKSELA0 H'FFFFF5A2 TSR7 -- -- -- -- -- -- -- -- UD7D UD7C UD7B UD7A CMF7D CMF7C CMF7B CMF7A -- -- -- -- -- -- -- -- -- -- -- -- CME7D CME7C CME7B CME7A -- -- -- -- -- -- -- -- H'FFFFF5A3 H'FFFFF5A4 TIER7 H'FFFFF5A5 H'FFFFF5A6 to H'FFFFF5BF -- H'FFFFF5C0 TCNT11 ATU-II (Channel 11) H'FFFFF5C1 H'FFFFF5C2 GR11A H'FFFFF5C3 H'FFFFF5C4 -- GR11B H'FFFFF5C5 H'FFFFF5C6 TIOR11 -- IO11B2 IO11B1 IO11B0 -- IO11A2 IO11A1 IO11A0 H'FFFFF5C7 -- -- -- -- -- -- -- -- -- Rev. 5.00 Feb. 24, 2010 Page 920 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFF5C8 TCR11 -- -- CKEG1 CKEG0 -- CKSELA2 CKSELA1 CKSELA0 ATU-II H'FFFFF5C9 -- -- -- -- -- -- -- -- -- (Channel 11) H'FFFFF5CA TSR11 -- -- -- -- -- -- -- OVF11 -- -- -- -- -- -- IMF11B IMF11A -- -- -- -- -- -- -- OVE11 -- -- -- -- -- -- IME11B IME11A -- -- -- -- -- -- -- -- H'FFFFF5CB H'FFFFF5CC TIER11 H'FFFFF5CD H'FFFFF5CE to H'FFFFF5FF -- H'FFFFF600 TCNT2A ATU-II (Channel 2) H'FFFFF601 H'FFFFF602 -- TCNT2B H'FFFFF603 H'FFFFF604 GR2A H'FFFFF605 H'FFFFF606 GR2B H'FFFFF607 H'FFFFF608 GR2C H'FFFFF609 H'FFFFF60A GR2D H'FFFFF60B H'FFFFF60C GR2E H'FFFFF60D H'FFFFF60E GR2F H'FFFFF60F H'FFFFF610 GR2G H'FFFFF611 H'FFFFF612 GR2H H'FFFFF613 H'FFFFF614 OCR2A H'FFFFF615 H'FFFFF616 OCR2B H'FFFFF617 H'FFFFF618 OCR2C H'FFFFF619 H'FFFFF61A OCR2D H'FFFFF61B H'FFFFF61C OCR2E H'FFFFF61D H'FFFFF61E OCR2F H'FFFFF61F Rev. 5.00 Feb. 24, 2010 Page 921 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation H'FFFFF620 OCR2G Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ATU-II (Channel 2) H'FFFFF621 H'FFFFF622 Module OCR2H H'FFFFF623 H'FFFFF624 OSBR2 H'FFFFF625 H'FFFFF626 TIOR2B -- IO2D2 IO2D1 IO2D0 -- IO2C2 IO2C1 H'FFFFF627 TIOR2A -- IO2B2 IO2B1 IO2B0 -- IO2A2 IO2A1 IO2A0 H'FFFFF628 TIOR2D -- IO2H2 IO2H1 IO2H0 -- IO2G2 IO2G1 IO2G0 H'FFFFF629 TIOR2C -- IO2F2 IO2F1 IO2F0 -- IO2E2 IO2E1 IO2E0 H'FFFFF62A TCR2B -- -- CKEGB1 CKEGB0 CKSELB3 CKSELB2 CKSELB1 CKSELB0 H'FFFFF62B TCR2A -- -- CKEGA1 CKEGA0 CKSELA3 CKSELA2 CKSELA1 CKSELA0 H'FFFFF62C TSR2A -- -- -- -- -- -- -- OVF2A IMF2H IMF2G IMF2F IMF2E IMF2D IMF2C IMF2B IMF2A TSR2B -- -- -- -- -- -- -- OVF2B CMF2H CMF2G CMF2F CMF2E CMF2D CMF2C CMF2B CMF2A TIER2A -- -- -- -- -- -- -- OVE2A IME2H IME2G IME2F IME2E IME2D IME2C IME2B IME2A TIER2B -- -- -- -- -- -- -- OVE2B CME2H CME2G CME2F CME2E CME2D CME2C CME2B CME2A -- -- -- -- -- -- -- -- H'FFFFF62D H'FFFFF62E H'FFFFF62F H'FFFFF630 H'FFFFF631 H'FFFFF632 H'FFFFF633 H'FFFFF634 to H'FFFFF63F -- H'FFFFF640 DCNT8A DNCT8B H'FFFFF643 H'FFFFF644 DNCT8C H'FFFFF645 H'FFFFF646 DCNT8D H'FFFFF647 H'FFFFF648 DCNT8E H'FFFFF649 H'FFFFF64A DCNT8F H'FFFFF64B H'FFFFF64C DCNT8G H'FFFFF64D H'FFFFF64E DCNT8H H'FFFFF64F H'FFFFF650 -- ATU-II (Channel 8) H'FFFFF641 H'FFFFF642 IO2C0 DCNT8I H'FFFFF651 Rev. 5.00 Feb. 24, 2010 Page 922 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation H'FFFFF652 DCNT8J Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ATU-II (Channel 8) H'FFFFF653 H'FFFFF654 Module DCNT8K H'FFFFF655 H'FFFFF656 DCNT8L H'FFFFF657 H'FFFFF658 DCNT8M H'FFFFF659 H'FFFFF65A DCNT8N H'FFFFF65B H'FFFFF65C DCNT8O H'FFFFF65D H'FFFFF65E DCNT8P H'FFFFF65F H'FFFFF660 RLDR8 H'FFFFF661 H'FFFFF662 TCNR CN8P CN8H CN8G CN8F CN8E CN8D CN8C CN8B CN8A OTR OTEP OTEO OTEN OTEM OTEL OTEK OTEJ OTEI OTEH OTEG OTEF OTEE OTED OTEC OTEB OTEA DSTR DST8P DST8O DST8N DST8M DST8L DST8K DST8J DST8I DST8H DST8G DST8F DST8E DST8D DST8C DST8B DST8A H'FFFFF668 TCR8 -- CKSELB2 CKSELB1 CKSELB0 -- CKSELA2 CKSELA1 CKSELA0 H'FFFFF669 -- -- -- -- -- -- -- -- -- H'FFFFF66A TSR8 OSF8P OSF8O OSF8N OSF8M OSF8L OSF8K OSF8J OSF8I OSF8H OSF8G OSF8F OSF8E OSF8D OSF8C OSF8B OSF8A TIER8 OSE8P OSE8O OSE8N OSE8M OSE8L OSE8K OSE8J OSE8I OSE8H OSE8G OSE8F OSE8E OSE8D OSE8C OSE8B OSE8A H'FFFFF663 H'FFFFF664 H'FFFFF665 H'FFFFF666 H'FFFFF667 H'FFFFF66B H'FFFFF66C H'FFFFF66D CN8O CN8N CN8M CN8L CN8K CN8J CN8I H'FFFFF66E RLDENR RLDEN -- -- -- -- -- -- -- H'FFFFF66F to H'FFFFF67F -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- H'FFFFF680 ECNT9A H'FFFFF681 -- H'FFFFF682 ECNT9B H'FFFFF683 -- H'FFFFF684 ECNT9C H'FFFFF685 -- H'FFFFF686 ECNT9D H'FFFFF687 -- H'FFFFF688 ECNT9E H'FFFFF689 -- -- ATU-II (Channel 9) Rev. 5.00 Feb. 24, 2010 Page 923 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation H'FFFFF68A ECNT9F H'FFFFF68B -- H'FFFFF68C GR9A H'FFFFF68D -- H'FFFFF68E GR9B H'FFFFF68F -- H'FFFFF690 GR9C H'FFFFF691 -- H'FFFFF692 GR9D H'FFFFF693 -- H'FFFFF694 GR9E H'FFFFF695 -- H'FFFFF696 GR9F Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ATU-II -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- H'FFFFF697 -- -- -- -- -- -- -- -- H'FFFFF698 TCR9A -- TRG3BEN EGSELB1 EGSELB0 -- TRG3AEN EGSELA1 EGSELA0 H'FFFFF699 -- -- -- -- -- -- -- -- -- H'FFFFF69A TCR9B -- TRG3DEN EGSELD1 EGSELD0 -- TRG3CEN EGSELC1 EGSELC0 -- H'FFFFF69B -- -- -- -- -- -- -- -- H'FFFFF69C TCR9C -- -- EGSELF1 EGSELF0 -- -- EGSELE1 EGSELE0 H'FFFFF69D -- -- -- -- -- -- -- -- -- H'FFFFF69E TSR9 -- -- -- -- -- -- -- -- -- -- CMF9F CMF9E CMF9D CMF9C CMF9B CMF9A -- -- -- -- -- -- -- -- -- -- CME9F CME9E CME9D CME9C CME9B CME9A -- -- -- -- -- -- -- -- H'FFFFF69F H'FFFFF6A0 TIER9 H'FFFFF6A1 H'FFFFF6A2 to H'FFFFF6BF -- H'FFFFF6C0 TCNT10AH -- (Channel 10) TCNT10AL H'FFFFF6C3 H'FFFFF6C4 TCNT10B H'FFFFF6C5 -- H'FFFFF6C6 TCNT10C -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- H'FFFFF6C7 H'FFFFF6C8 TCNT10D H'FFFFF6C9 -- H'FFFFF6CA TCNT10E H'FFFFF6CB H'FFFFF6CC (Channel 9) ATU-II H'FFFFF6C1 H'FFFFF6C2 Module TCNT10F H'FFFFF6CD Rev. 5.00 Feb. 24, 2010 Page 924 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation H'FFFFF6CE TCNT10G Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ATU-II (Channel 10) H'FFFFF6CF H'FFFFF6D0 Module ICR10AH H'FFFFF6D1 H'FFFFF6D2 ICR10AL H'FFFFF6D3 H'FFFFF6D4 OCR10AH H'FFFFF6D5 H'FFFFF6D6 OCR10AL H'FFFFF6D7 H'FFFFF6D8 OCR10B H'FFFFF6D9 -- H'FFFFF6DA RLD10C -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- H'FFFFF6DB H'FFFFF6DC GR10G H'FFFFF6DD H'FFFFF6DE TCNT10H H'FFFFF6DF -- H'FFFFF6E0 NCR10 H'FFFFF6E1 -- -- -- -- -- -- -- -- -- ATU-II H'FFFFF6E2 TIOR10 RLDEN CCS PIM1 PIM0 -- IO10G2 IO10G1 IO10G0 (Channel 10) H'FFFFF6E3 -- -- -- -- -- -- -- -- -- H'FFFFF6E4 TCR10 TRG2BEN TRG1BEN TRG2AEN TRG1AEN TRG0DEN NCE CKEG1 CKEG0 H'FFFFF6E5 -- -- -- -- -- -- -- -- -- H'FFFFF6E6 TCCLR10 -- -- -- -- -- -- -- -- -- -- -- -- CMF10G CMF10B ICF10A CMF10A -- -- -- -- -- -- -- -- -- -- -- IREG CME10G CME10B ICE10A CME10A -- -- -- -- -- -- -- H'FFFFF6E7 H'FFFFF6E8 TSR10 H'FFFFF6E9 H'FFFFF6EA TIER10 H'FFFFF6EB H'FFFFF6EC to H'FFFFF6FF -- -- H'FFFFF700 POPCR PULS7ROE PULS6ROE PULS5ROE PULS4ROE PULS3ROE PULS2ROE PULS1ROE PULS0RO APC E H'FFFFF701 -- PULS7SOE PULS6SOE PULS5SOE PULS4SOE PULS3SOE PULS2SOE PULS1SOE PULS0SO E H'FFFFF702 to H'FFFFF707 -- H'FFFFF708 SYSCR1 -- -- -- -- -- -- H'FFFFF709 -- -- -- -- -- -- -- H'FFFFF70A SYCSR2* H'FFFFF70B* SYCSR2* -- -- -- -- -- -- -- -- -- AUDSRST RAME Power-Down State -- -- 4 -- -- -- -- -- -- -- -- 5 -- -- -- -- MSTOP3 MSTOP2 MSTOP1 MSTOP0 Rev. 5.00 Feb. 24, 2010 Page 925 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFF70C to H'FFFFF70F -- -- -- -- -- -- -- -- -- -- H'FFFFF710 CMSTR -- -- -- -- -- -- -- -- CMT -- -- -- -- -- -- STR1 STR0 -- -- -- -- -- -- -- -- CMF CMIE -- -- -- -- CKS1 CKS0 -- -- -- -- -- -- -- -- CMF CMIE -- -- -- -- CKS1 CKS0 H'FFFFF711 H'FFFFF712 CMCSR0 H'FFFFF713 H'FFFFF714 CMCNT0 H'FFFFF715 H'FFFFF716 CMCOR0 H'FFFFF717 H'FFFFF718 CMCSR1 H'FFFFF719 H'FFFFF71A CMCNT1 H'FFFFF71B H'FFFFF71C CMCOR1 H'FFFFF71D H'FFFFF71E -- -- -- -- -- -- -- -- -- H'FFFFF71F -- -- -- -- -- -- -- -- -- H'FFFFF720 PAIOR PA15IOR PA14IOR PA13IOR PA12IOR PA11IOR PA10IOR PA9IOR PA8IOR PA7IOR PA6IOR PA5IOR PA4IOR PA3IOR PA2IOR PA1IOR PA0IOR PA15MD1 PA15MD0 PA14MD1 PA14MD0 -- PA13MD -- PA12MD PA11MD1 PA11MD0 PA10MD1 PA10MD0 PA9MD1 PA9MD0 PA8MD1 PA8MD0 PACRL -- PA7MD -- PA6MD -- PA5MD -- PA4MD -- PA3MD -- PA2MD -- PA1MD -- PA0MD PADR PA15DR PA14DR PA13DR PA12DR PA11DR PA10DR PA9DR PA8DR PA7DR PA6DR PA5DR PA4DR PA3DR PA2DR PA1DR PA0DR PH15IOR PH14IOR PH13IOR PH12IOR PH11IOR PH10IOR PH9IOR PH8IOR PH7IOR PH6IOR PH5IOR PH4IOR PH3IOR PH2IOR PH1IOR PH0IOR PH15MD PH14MD PH13MD PH12MD PH11MD PH10MD PH9MD PH8MD PH7MD PH6MD PH5MD PH4MD PH3MD PH2MD PH1MD PH0MD PHDR PH15DR PH14DR PH13DR PH12DR PH11DR PH10DR PH9DR PH8DR PH7DR PH6DR PH5DR PH4DR PH3DR PH2DR PH1DR PH0DR H'FFFFF72E ADTRGR1 EXTRG -- -- -- -- -- -- -- H'FFFFF72F ADTRGR2 EXTRG -- -- -- -- -- -- -- H'FFFFF721 H'FFFFF722 PACRH H'FFFFF723 H'FFFFF724 H'FFFFF725 H'FFFFF726 H'FFFFF727 H'FFFFF728 PHIOR H'FFFFF729 H'FFFFF72A PHCR H'FFFFF72B H'FFFFF72C H'FFFFF72D Rev. 5.00 Feb. 24, 2010 Page 926 of 950 REJ09B0177-0500 Port A Port H A/D Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFF730 PBIOR PB15IOR PB14IOR PB13IOR PB12IOR PB11IOR PB10IOR PB9IOR PB8IOR Port B PB7IOR PB6IOR PB5IOR PB4IOR PB3IOR PB2IOR PB1IOR PB0IOR PBCRH PB15MD1 PB15MD0 PB14MD1 PB14MD0 PB13MD1 PB13MD0 PB12MD1 PB12MD0 PB11MD1 PB11MD0 PB10MD1 PB10MD0 PB9MD1 PB9MD0 PB8MD1 PB8MD0 PBCRL PB7MD1 PB7MD0 PB6MD1 PB6MD0 PB5MD1 PB5MD0 PB4MD1 PB4MD0 -- PB3MD -- PB2MD -- PB1MD -- PB0MD PBIR PB15IR PB14IR PB13IR -- PB11IR PB10IR PB9IR PB8IR PB7IR PB6IR PB5IR PB4IR PB3IR PB2IR PB1IR PB0IR PBDR PB15DR PB14DR PB13DR PB12DR PB11DR PB10DR PB9DR PB8DR PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR PCIOR -- -- -- -- -- -- -- -- -- -- -- PC4IOR PC3IOR PC2IOR PC1IOR PC0IOR PC4MD H'FFFFF731 H'FFFFF732 H'FFFFF733 H'FFFFF734 H'FFFFF735 H'FFFFF736 H'FFFFF737 H'FFFFF738 H'FFFFF739 H'FFFFF73A H'FFFFF73B H'FFFFF73C PCCR -- -- -- -- -- -- -- PC3MD1 PC3MD0 PC2MD1 PC2MD0 -- PC1MD -- PC0MD PCDR -- -- -- -- -- -- -- -- -- -- -- PC4DR PC3DR PC2DR PC1DR PC0DR PDIOR -- -- PD13IOR PD12IOR PD11IOR PD10IOR PD9IOR PD8IOR PD7IOR PD6IOR PD5IOR PD4IOR PD3IOR PD2IOR PD1IOR PD0IOR -- -- -- -- PD13MD1 PD13MD0 -- PD12MD -- PD11MD -- PD10MD -- PD9MD -- PD8MD -- PD7MD -- PD6MD -- PD5MD -- PD4MD -- PD3MD -- PD2MD -- PD1MD -- PD0MD PDDR -- -- PD13DR PD12DR PD11DR PD10DR PD9DR PD8DR PD7DR PD6DR PD5DR PD4DR PD3DR PD2DR PD1DR PD0DR PFIOR PF15IOR PF14IOR PF13IOR PF12IOR PF11IOR PF10IOR PF9IOR PF8IOR PF7IOR PF6IOR PF5IOR PF4IOR PF3IOR PF2IOR PF1IOR PF0IOR PFCRH CKHIZ PF15MD0 PF15MD1 PF14MD0 PF14MD1 PF13MD -- PF12MD -- PF11MD -- PF10MD -- PF9MD -- PF8MD PFCRL -- PF7MD -- PF6MD PF5MD1 PF5MD0 -- PF4MD -- PF3MD -- PF2MD -- PF1MD -- PF0MD PFDR PF15DR PF14DR PF13DR PF12DR PF11DR PF10DR PF9DR PF8DR PF7DR PF6DR PF5DR PF4DR PF3DR PF2DR PF1DR PF0DR H'FFFFF73D H'FFFFF73E H'FFFFF73F H'FFFFF740 H'FFFFF741 H'FFFFF742 PDCRH H'FFFFF743 H'FFFFF744 PDCRL H'FFFFF745 H'FFFFF746 H'FFFFF747 H'FFFFF748 H'FFFFF749 H'FFFFF74A H'FFFFF74B H'FFFFF74C H'FFFFF74D H'FFFFF74E H'FFFFF74F Port C Port D Port F Rev. 5.00 Feb. 24, 2010 Page 927 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFF750 PEIOR PE15IOR PE14IOR PE13IOR PE12IOR PE11IOR PE10IOR PE9IOR PE8IOR Port E PE7IOR PE6IOR PE5IOR PE4IOR PE3IOR PE2IOR PE1IOR PE0IOR PE15MD PE14MD PE13MD PE12MD PE11MD PE10MD PE9MD PE8MD PE7MD PE6MD PE5MD PE4MD PE3MD PE2MD PE1MD PE0MD PE15DR PE14DR PE13DR PE12DR PE11DR PE10DR PE9DR PE8DR PE7DR PE6DR PE5DR PE4DR PE3DR PE2DR PE1DR PE0DR -- -- PL13IOR PL12IOR PL11IOR PL10IOR PL9IOR PL8IOR PL7IOR PL6IOR PL5IOR PL4IOR PL3IOR PL2IOR PL1IOR PL0IOR -- -- -- -- PL13MD1 PL13MD0 PL12MD1 PL12MD0 PL11MD1 PL11MD0 PL10MD1 PL10MD0 PL9MD1 PL9MD0 -- PL8MD PLCRL PL7MD1 PL7MD0 -- PL6MD -- PL5MD -- PL4MD -- PL3MD PL2MD1 PL2MD0 PL1MD1 PL1MD0 -- PL0MD0 PLIR -- -- -- -- -- -- PL9IR PL8IR PL7IR -- -- -- -- -- -- -- PLDR -- -- PL13DR PL12DR PL11DR PL10DR PL9DR PL8DR PL7DR PL6DR PL5DR PL4DR PL3DR PL2DR PL1DR PL0DR -- -- -- -- -- -- -- -- -- -- -- -- PG3IOR PG2IOR PG1IOR PG0IOR -- -- -- -- -- -- -- -- PG3MD1 PG3MD0 PG2MD1 PG2MD0 -- PG1MD PG0MD1 PG0MD0 -- H'FFFFF751 H'FFFFF752 PECR H'FFFFF753 H'FFFFF754 PEDR H'FFFFF755 H'FFFFF756 PLIOR H'FFFFF757 H'FFFFF758 PLCRH H'FFFFF759 H'FFFFF75A H'FFFFF75B H'FFFFF75C H'FFFFF75D H'FFFFF75E H'FFFFF75F H'FFFFF760 PGIOR H'FFFFF761 H'FFFFF762 PGCR H'FFFFF763 H'FFFFF764 PGDR -- -- -- -- -- -- -- -- -- -- -- PG3DR PG2DR PG1DR PG0DR PJ15IOR PJ14IOR PJ13IOR PJ12IOR PJ11IOR PJ10IOR PJ9IOR PJ8IOR PJ7IOR PJ6IOR PJ5IOR PJ4IOR PJ3IOR PJ2IOR PJ1IOR PJ0IOR PJCRH -- PJ15MD -- PJ14MD -- PJ13MD -- PJ12MD -- PJ11MD -- PJ10MD -- PJ9MD -- PJ8MD PJCRL -- PJ7MD -- PJ6MD -- PJ5MD -- PJ4MD -- PJ3MD -- PJ2MD -- PJ1MD -- PJ0MD PJ15DR PJ14DR PJ13DR PJ12DR PJ11DR PJ10DR PJ9DR PJ8DR PJ7DR PJ6DR PJ5DR PJ4DR PJ3DR PJ2DR PJ1DR PJ0DR H'FFFFF765 H'FFFFF766 PJIOR H'FFFFF767 H'FFFFF768 H'FFFFF769 H'FFFFF76A H'FFFFF76B H'FFFFF76C PJDR H'FFFFF76D H'FFFFF76E ADTRGR0 EXTRG -- -- -- -- -- -- -- H'FFFFF76F -- -- -- -- -- -- -- -- -- Rev. 5.00 Feb. 24, 2010 Page 928 of 950 REJ09B0177-0500 Port L Port G Port J A/D Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFF770 PKIOR PK15IOR PK14IOR PK13IOR PK12IOR PK11IOR PK10IOR PK9IOR PK8IOR Port K PK7IOR PK6IOR PK5IOR PK4IOR PK3IOR PK2IOR PK1IOR PK0IOR -- PK15MD -- PK14MD -- PK13MD -- PK12MD -- PK11MD -- PK10MD -- PK9MD -- PK8MD -- PK7MD -- PK6MD -- PK5MD -- PK4MD -- PK3MD -- PK2MD -- PK1MD -- PK0MD PK15IR PK14IR PK13IR PK12IR PK11IR PK10IR PK9IR PK8IR PK7IR PK6IR PK5IR PK4IR PK3IR PK2IR PK1IR PK0IR PK15DR PK14DR PK13DR PK12DR PK11DR PK10DR PK9DR PK8DR PK7DR PK6DR PK5DR PK4DR PK3DR PK2DR PK1DR PK0DR -- -- -- Port A H'FFFFF771 H'FFFFF772 PKCRH H'FFFFF773 H'FFFFF774 PKCRL H'FFFFF775 H'FFFFF776 PKIR H'FFFFF777 H'FFFFF778 PKDR H'FFFFF779 H'FFFFF77A to H'FFFFF77F -- -- -- -- -- -- -- H'FFFFF780 PAPR PA15PR PA14PR PA13PR PA12PR PA11PR PA10PR PA9PR PA8PR PA7PR PA6PR PA5PR PA4PR PA3PR PA2PR PA1PR PA0PR PB15PR PB14PR PB13PR PB12PR PB11PR PB10PR PB9PR PB8PR PB7PR PB6PR PB5PR PB4PR PB3PR PB2PR PB1PR PB0PR -- -- PD13PR PD12PR PD11PR PD10PR PD9PR PD8PR PD7PR PD6PR PD5PR PD4PR PD3PR PD2PR PD1PR PD0PR PJ15PR PJ14PR PJ13PR PJ12PR PJ11PR PJ10PR PJ9PR PJ8PR PJ7PR PJ6PR PJ5PR PJ4PR PJ3PR PJ2PR PJ1PR PJ0PR -- -- PL13PR PL12PR PL11PR PL10PR PL9PR PL8PR H'FFFFF781 H'FFFFF782 PBPR H'FFFFF783 H'FFFFF784 PDPR H'FFFFF785 H'FFFFF786 PJPR H'FFFFF787 H'FFFFF788 PLPR H'FFFFF789 Port B Port D Port J Port L PL7PR PL6PR PL5PR PL4PR PL3PR PL2PR PL1PR PL0PR H'FFFFF78A to H'FFFFF7BF -- -- -- -- -- -- -- -- -- -- H'FFFFF7C0 SDIR TS3 TS2 TS1 TS0 -- -- -- -- H-UDI -- -- -- -- -- -- -- -- SDSR -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SDTRF -- -- -- -- -- -- -- -- H'FFFFF7C1 H'FFFFF7C2 H'FFFFF7C3 H'FFFFF7C4 SDDRH H'FFFFF7C5 H'FFFFF7C6 SDDRL H'FFFFF7C7 H'FFFFF7C8 to H'FFFFF7FF -- -- Rev. 5.00 Feb. 24, 2010 Page 929 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFF800 ADDR0H AD9 AD8 AD7 AD6 AD5 ADR AD3 AD2 A/D H'FFFFF801 ADDR0L AD1 AD0 -- -- -- -- -- -- H'FFFFF802 ADDR1H AD9 AD8 AD7 AD6 AD5 ADR AD3 AD2 H'FFFFF803 ADDR1L AD1 AD0 -- -- -- -- -- -- H'FFFFF804 ADDR2H AD9 AD8 AD7 AD6 AD5 ADR AD3 AD2 H'FFFFF805 ADDR2L AD1 AD0 -- -- -- -- -- -- H'FFFFF806 ADDR3H AD9 AD8 AD7 AD6 AD5 ADR AD3 AD2 H'FFFFF807 ADDR3L AD1 AD0 -- -- -- -- -- -- H'FFFFF808 ADDR4H AD9 AD8 AD7 AD6 AD5 ADR AD3 AD2 H'FFFFF809 ADDR4L AD1 AD0 -- -- -- -- -- -- H'FFFFF80A ADDR5H AD9 AD8 AD7 AD6 AD5 ADR AD3 AD2 -- H'FFFFF80B ADDR5L AD1 AD0 -- -- -- -- -- H'FFFFF80C ADDR6H AD9 AD8 AD7 AD6 AD5 ADR AD3 AD2 H'FFFFF80D ADDR6L AD1 AD0 -- -- -- -- -- -- H'FFFFF80E ADDR7H AD9 AD8 AD7 AD6 AD5 ADR AD3 AD2 H'FFFFF80F ADDR7L AD1 AD0 -- -- -- -- -- -- H'FFFFF810 ADDR8H AD9 AD8 AD7 AD6 AD5 ADR AD3 AD2 H'FFFFF811 ADDR8L AD1 AD0 -- -- -- -- -- -- H'FFFFF812 ADDR9H AD9 AD8 AD7 AD6 AD5 ADR AD3 AD2 H'FFFFF813 ADDR9L AD1 AD0 -- -- -- -- -- -- H'FFFFF814 ADDR10H AD9 AD8 AD7 AD6 AD5 ADR AD3 AD2 H'FFFFF815 ADDR10L AD1 AD0 -- -- -- -- -- -- H'FFFFF816 ADDR11H AD9 AD8 AD7 AD6 AD5 ADR AD3 AD2 H'FFFFF817 ADDR11L AD1 AD0 -- -- -- -- -- -- H'FFFFF818 ADCSR0 ADF ADIE ADM1 ADM0 CH3 CH2 CH1 CH0 H'FFFFF819 ADCR0 TRGE CKS ADST ADCS -- -- -- -- H'FFFFF81A to H'FFFFF81F -- -- -- -- -- -- -- -- -- H'FFFFF820 ADDR12H AD9 AD8 AD7 AD6 AD5 ADR AD3 AD2 H'FFFFF821 ADDR12L AD1 AD0 -- -- -- -- -- -- H'FFFFF822 ADDR13H AD9 AD8 AD7 AD6 AD5 ADR AD3 AD2 H'FFFFF823 ADDR13L AD1 AD0 -- -- -- -- -- -- H'FFFFF824 ADDR14H AD9 AD8 AD7 AD6 AD5 ADR AD3 AD2 H'FFFFF825 ADDR14L AD1 AD0 -- -- -- -- -- -- H'FFFFF826 ADDR15H AD9 AD8 AD7 AD6 AD5 ADR AD3 AD2 H'FFFFF827 ADDR15L AD1 AD0 -- -- -- -- -- -- H'FFFFF828 ADDR16H AD9 AD8 AD7 AD6 AD5 ADR AD3 AD2 H'FFFFF829 ADDR16L AD1 AD0 -- -- -- -- -- -- Rev. 5.00 Feb. 24, 2010 Page 930 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFF82A ADDR17H AD9 AD8 AD7 AD6 AD5 ADR AD3 AD2 A/D H'FFFFF82B ADDR17L AD1 AD0 -- -- -- -- -- -- H'FFFFF82C ADDR18H AD9 AD8 AD7 AD6 AD5 ADR AD3 AD2 H'FFFFF82D ADDR18L AD1 AD0 -- -- -- -- -- -- H'FFFFF82E ADDR19H AD9 AD8 AD7 AD6 AD5 ADR AD3 AD2 H'FFFFF82F ADDR19L AD1 AD0 -- -- -- -- -- -- H'FFFFF830 ADDR20H AD9 AD8 AD7 AD6 AD5 ADR AD3 AD2 H'FFFFF831 ADDR20L AD1 AD0 -- -- -- -- -- -- H'FFFFF832 ADDR21H AD9 AD8 AD7 AD6 AD5 ADR AD3 AD2 H'FFFFF833 ADDR21L AD1 AD0 -- -- -- -- -- -- H'FFFFF834 ADDR22H AD9 AD8 AD7 AD6 AD5 ADR AD3 AD2 H'FFFFF835 ADDR22L AD1 AD0 -- -- -- -- -- -- H'FFFFF836 ADDR23H AD9 AD8 AD7 AD6 AD5 ADR AD3 AD2 H'FFFFF837 ADDR23L AD1 AD0 -- -- -- -- -- -- H'FFFFF838 ADCSR1 ADF ADIE ADM1 ADM0 CH3 CH2 CH1 CH0 H'FFFFF839 ADCR1 TRGE CKS ADST ADCS -- -- -- -- H'FFFFF83A to H'FFFFF83F -- -- -- -- -- -- -- -- -- H'FFFFF840 ADDR24H AD9 AD8 AD7 AD6 AD5 ADR AD3 AD2 H'FFFFF841 ADDR24L AD1 AD0 -- -- -- -- -- -- H'FFFFF842 ADDR25H AD9 AD8 AD7 AD6 AD5 ADR AD3 AD2 H'FFFFF843 ADDR25L AD1 AD0 -- -- -- -- -- -- H'FFFFF844 ADDR26H AD9 AD8 AD7 AD6 AD5 ADR AD3 AD2 H'FFFFF845 ADDR26L AD1 AD0 -- -- -- -- -- -- H'FFFFF846 ADDR27H AD9 AD8 AD7 AD6 AD5 ADR AD3 AD2 H'FFFFF847 ADDR27L AD1 AD0 -- -- -- -- -- -- H'FFFFF848 ADDR28H AD9 AD8 AD7 AD6 AD5 ADR AD3 AD2 H'FFFFF849 ADDR28L AD1 AD0 -- -- -- -- -- -- H'FFFFF84A ADDR29H AD9 AD8 AD7 AD6 AD5 ADR AD3 AD2 H'FFFFF84B ADDR29L AD1 AD0 -- -- -- -- -- -- H'FFFFF84C ADDR30H AD9 AD8 AD7 AD6 AD5 ADR AD3 AD2 H'FFFFF84D ADDR30L AD1 AD0 -- -- -- -- -- -- H'FFFFF84E ADDR31H AD9 AD8 AD7 AD6 AD5 ADR AD3 AD2 H'FFFFF84F ADDR31L AD1 AD0 -- -- -- -- -- -- H'FFFFF850 to H'FFFFF857 -- -- -- -- -- -- -- -- -- H'FFFFF858 ADCSR2 ADF ADIE ADM1 ADM0 -- CH2 CH1 CH0 H'FFFFF859 ADCR2 TRGE CKS ADST ADCS -- -- -- -- H'FFFFF85A to H'FFFFF85F -- -- -- -- -- -- -- -- -- -- Rev. 5.00 Feb. 24, 2010 Page 931 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation H'FFFFF860 ADCNT0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MTAD H'FFFFF861 H'FFFFF862 ADCYLR0 H'FFFFF863 H'FFFFF864 ADDR0A H'FFFFF865 H'FFFFF866 ADDR0B H'FFFFF867 H'FFFFF868 ADGR0A H'FFFFF869 H'FFFFF86A ADGR0B H'FFFFF86B H'FFFFF86C ADTCR0 CKSEL10 CKSEL00 -- -- DTSEL0B DTSEL0A ADSEL0B ADSEL0A H'FFFFF86D ADTSR0 -- TADF0B TADF0A ADDF0B ADDF0A ADCYLF0 ADCMF0B ADCMF0A H'FFFFF86E ADTIER0 ADTRG0 TADE0B TADE0A ADDE0B ADDE0A ADCYLE0 ADCME0B ADCNE0A H'FFFFF86F H'FFFFF870 ADCNT1 H'FFFFF871 H'FFFFF872 ADCYLR1 H'FFFFF873 H'FFFFF874 ADDR1A H'FFFFF875 H'FFFFF876 ADDR1B H'FFFFF877 H'FFFFF878 ADGR1A H'FFFFF879 H'FFFFF87A Module ADGR1B H'FFFFF87B H'FFFFF87C ADTCR1 CKSEL11 CKSEL01 -- -- DTSEL1B DTSEL1A ADSEL1B ADSEL1A H'FFFFF87D ADTSR1 -- TADF1B TADF1A ADDF1B ADDF1A ADCYLF1 ADCMF1B ADCMF1A H'FFFFF87E ADTIER1 ADTRG1 TADE1B TADE1A ADDE1B ADDE1A ADCYLE1 ADCME1B ADCNE1A H'FFFFF87F Rev. 5.00 Feb. 24, 2010 Page 932 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Bit Names Register Name Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'FFFFFC00 SSCRH_0 MSS BIDE -- SOL SOLP SCKS CSS1 CSS0 H'FFFFFC01 SSCRL_0 -- -- SRES -- -- -- DATS1 DATS0 SSU* (Channel 0) H'FFFFFC02 SSMR_0 MLS CPOS CPHS -- -- CKS2 CKS1 CKS0 H'FFFFFC03 SSER_0 TE RE -- -- TEIE TIE RIE CEIE H'FFFFFC04 SSTDR0_0 H'FFFFFC05 SSTDR1_0 H'FFFFFC06 SSTDR2_0 H'FFFFFC07 SSTDR3_0 H'FFFFFC08 SSRDR0_0 H'FFFFFC09 SSRDR1_0 H'FFFFFC0A SSRDR2_0 H'FFFFFC0B SSRDR3_0 H'FFFFFC0C SSSR_0 -- ORER -- -- TEND TDRE RDRF CE H'FFFFFC10 SSCRH_1 MSS BIDE -- SOL SOLP SCKS CSS1 CSS0 H'FFFFFC11 SSCRL_1 -- -- SRES -- -- -- DATS1 DATS0 H'FFFFFC12 SSMR_1 MLS CPOS CPHS -- -- CKS2 CKS1 CKS0 H'FFFFFC13 SSER_1 TE RE -- -- TEIE TIE RIE CEIE H'FFFFFC14 SSTDR0_1 H'FFFFFC15 SSTDR1_1 H'FFFFFC16 SSTDR2_1 H'FFFFFC17 SSTDR3_1 H'FFFFFC18 SSRDR0_1 -- ORER -- -- TEND TDRE RDRF CE H'FFFFFC19 SSRDR1_1 H'FFFFFC1A SSRDR2_1 H'FFFFFC1B SSRDR3_1 H'FFFFFC1C SSSR_1 6 6 SSU* (Channel 1) Notes: 1. This is the read address. The Write Address is H'FFFEC10 for TCSR and TCNT, and H'FFFEC12 for RSTCSR. For details, see section 13.2.4, Register Access. 2. Version with 1-Mbyte ROM and 48-Kbyte RAM 3. Version with 1.5-Mbyte ROM and 80-Kbyte RAM 4. Program in the word unit. Programming in the byte or longword unit is not enabled. 5. Read in the byte unit. Correct values cannot be read in the word or longword unit. 6. SSU: Synchronous Serial Communication Unit * This is the read address. The write address is H'FFFFF70A. For details, see section 27.2.4, Notes on Register Access. Rev. 5.00 Feb. 24, 2010 Page 933 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers A.2 Register States in Reset and Power-Down States Table A.2 Register States After Reset and Power-Down States Reset State Power-Down State Type Name Power-On Hardware Standby Software Standby Sleep CPU R0 to R15 Initialized Initialized Initialized Held Initialized Initialized Initialized Held Initialized Initialized Initialized Held Initialized Initialized Initialized Held Initialized Initialized Initialized Held Undefined Undefined Undefined Held Initialized Initialized Initialized Initialized Initialized Initialized SR GBR VBR MACH, MACL PR PC FPU FR0 to FR15 FPUL FPSCR Interrupt controller (INTC) IPRA to IPRL ICR ISR User break controller (UBC) UBARH, UBARL UBAMRH, UBAMRL UBBR UBCR Bus state controller (BSC) BCR1, BCR2 Direct memory access controller (DMAC) SAR0 to SAR3 WCR DAR0 to DAR3 DMATCR0 to DMATCR3 CHCR0 to CHCR3 DMAOR Advanced timer unit-II (ATU-II) BFR6A-D, BFR7A-D CYLR6A-D, CYLR7A-D DCNT8A-P DSTR Rev. 5.00 Feb. 24, 2010 Page 934 of 950 REJ09B0177-0500 Held Appendix A On-chip peripheral module Registers Reset State Power-Down State Type Name Power-On Hardware Standby Software Standby Sleep Advanced timer unit-II (ATU-II) DTR6A-D, DTR7A-D Initialized Initialized Initialized Held ECNT9A-F GR1A-H, GR2A-H GR3A-D, GR4A-D GR5A-D, GR9A-F GR10G, GR11A, 11B ICR0A-D, ICR10A ITVRR1, ITVRR2A, 2B NCR10 OCR1, OCR2A-H OCR10AH, 10AL OCR10B OSBR1, OSBR2 OTR PMDR PSCR1-4 PSTR RLD10C RLDENR RLDR8 TCCLR10 TCNR TCNT0H, L, TCNT1A, 1B, TCNT2A, 2B TCNT3-5, TCNT6A-D TCNT7A-D TCNT10AH, 10AL TCNT10B-H, TCNT11 TCR1A, 1B, TCR2A, 2B, TCR3-5, TCR6A, 6B, TCR7A, 7B, TCR8, TCR9A-C, TCR10, TCR11 Rev. 5.00 Feb. 24, 2010 Page 935 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Type Name Advanced timer unit-II TIER0, TIER1A, 1B (ATU-II) TIER2A, 2B, TIER3, TIER6-11 Reset State Power-Down State Power-On Hardware Standby Software Standby Sleep Initialized Initialized Initialized Held TIOR0, TIOR1A-D, TIOR2A-D, TIOR3A, 3B, TIOR4A, 4B, TIOR5A, 5B, TIOR10,11 TMDR TNCT10E TRGMDR TSR0, TSR1A, 1B, TSR2A, 2B, TSR3, TSR6-11 TSTR1-3 Advanced pulse controller (APC) POPCR Initialized Initialized Initialized Held Watchdog timer (WDT) TCNT Initialized Initialized Initialized Held Initialized Initialized Initialized Held Initialized Initialized Initialized Held TCSR RSTCSR Serial communication interface (SCI) SMR0 to SMR4 BRR0 to BRR4 SCR0 to SCR4 TDR0 to TDR4 SSR0 to SSR4 RDR0 to RDR4 SDCR0 to SDCR4 Synchronous Communication Unit (SSU) SSCRH_0,1 SSCRL_0,1 SSMR_0,1 SSER_0,1 SSSR_0,1 SSRDR0 to 3_0,1 SSTRSR_0,1 Rev. 5.00 Feb. 24, 2010 Page 936 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Reset State Power-Down State Type Name Power-On Hardware Standby Software Standby Sleep A/D converter ADDR0 (H/L) to ADDR31 (H/L) Initialized Initialized Initialized Held Initialized Initialized Initialized Held Initialized Initialized Initialized Held Initialized Initialized Initialized Held PADR, PBDR, PCDR, Initialized PDDR, PEDR, PFDR, PGDE, PHDR, PJDR, PKDR, PLDR Initialized Initialized Held PAPR, PBPR, PDPR, PJPR, Pin state PLPR Pin state Pin state Pin state ADSCR0, ADCSR1, ADCSR2 ADCR0, ADCR1, ADCR2 ADTRGR0, ADTRGR1, ADTRGR2 Multi-trigger A/D (MTAD) ADTCR0, ADTCR1 ADTSR0, ADTSR1 ADTIER0, ADTIER1 ADCNT0, ADCNT1 ADGR0A, ADGR0B ADGR1A, ADGR1B ADCYLR0, ADCYLR1 ADDR0A, ADDR0B ADDR1A, ADDR1B Compare match timer (CMT) CMSTR CMCSR0, CMCSR1 CMCNT0, CMCNT1 CMCOR0, CMCOR1 Pin function controller PAIOR, PBIOR, (PFC) PCIOR, PDIOR, PEIOR, PFIOR, PGIOR, PHIOR, PJIOR, PKIOR, PLIOR PACRH, PACRL, PBCRH, PBCRL, PBIR, PCCR, PDCRH, PDCRL, PECR, PFCRH, PFCRL, PGCR, PHCR, PJCRH, PJCRL, PKCRH, PKCRL, PKIR, PLCRH, PLCRL, PLIR I/O ports Rev. 5.00 Feb. 24, 2010 Page 937 of 950 REJ09B0177-0500 Appendix A On-chip peripheral module Registers Reset State Power-Down State Type Name Power-On Hardware Standby Software Standby Sleep Flash ROM RAMER Initialized Initialized Initialized Held Initialized Initialized Initialized Held Initialized Initialized Initialized Held MB Undefined Undefined Undefined Held SDIR Held Undefined Undefined Held FCCS FPCS FECS FKEY FMATS FTDAR Power-down state related SBYCR Controller area network-II (HCAN-II) MCR SYSCR1, SYSCR2 GSR HCAN_BCR 0/1 IRP IMR TXPR 0/1 TXCR 0/1 TXACK 0/1 ABACK 0/1 RXPR 0/1 RFPR 0/1 MBIMR 0/1 UMSR 0/1 TCNTR TCR TSR TMR TDCR LOSR CCR CMAX ICR 0/1 TCMR 0-2 High-performance user debug interface (H-UDI) SDSR SDDRH, SDDRL Rev. 5.00 Feb. 24, 2010 Page 938 of 950 REJ09B0177-0500 Appendix B Pin States Appendix B Pin States Tables B.1, B.2, and B.3 show this LSI pin states. Table B.1 Pin States Pin State Reset State Power-Down State Power-On ROMless Expanded Mode Expanded Mode with ROM SingleChip Mode Hardware Standby Software Standby H-UDI Module Standby AUD Module BusStandby Released State Type Pin Name 8 Bits Clock CK*1 O Z Z O O O XTAL I/O L L I/O I/O I/O I System control Interrupt 16 Bits EXTAL I Z Z I I PLLCAP I I I I I I RES I Z I I I I FWE I I I I I I HSTBY I I I I I I MD0 I I I I I I MD1 I I I I I I MD2 I I I I I I WDTOVF O Z Z O O O BREQ -- Z Z I I I BACK -- Z Z O O L NMI I Z I I I I IRQ0 to IRQ7 -- Z Z I I I IRQOUT -- Z Z O O O -- Z Z O O Z -- Z Z I/O I/O Z -- Z Z I/O I/O Z Address bus A0 to A21 O Data bus D0 to D7 Z D8 to D15 -- WAIT I -- Z Z I I I WRH, WRL H -- Z Z O O Z RD H -- Z Z O O Z CS0 H -- Z Z O O Z CS1 to CS3 -- Z Z O O Z Port POD -- Z Z I I I ATU-II TI0A to TI0D -- Z Z I I I TIO1A to TIO1H -- Z Z I/O I/O I/O Bus control Z TIO2A to TIO2H -- Z Z I/O I/O I/O TIO3A to TIO3D -- Z Z I/O I/O I/O Rev. 5.00 Feb. 24, 2010 Page 939 of 950 REJ09B0177-0500 Appendix B Pin States Pin State Reset State Power-Down State Power-On ROMless Expanded Mode Expanded Mode with ROM SingleChip Mode Hardware Standby Software Standby H-UDI Module Standby AUD Module BusStandby Released State Type Pin Name 8 Bits ATU-II TIO4A to TIO4D -- Z Z I/O I/O I/O TIO5A to TIO5D -- Z Z I/O I/O I/O TO6A to TO6D -- Z Z O O O TO7A to TO7D -- Z Z O O O TO8A to TO8P -- Z Z O O O TI9A to TI9F -- Z Z I I I TI10 -- Z Z I I I TIO11A, TIO11B -- Z Z I/O I/O I/O TCLKA, TCLKB -- Z Z I I I SCI A/D converter MTAD 16 Bits SCK0 to SCK4 -- Z Z I/O I/O I/O TxD0 to TxD4 -- Z Z O O O RxD0 to RxD4 -- Z Z I I I AN0 to AN31 Z Z Z I I I ADTRG0, ADTRG1 -- Z Z I I I ADEND -- Z Z O O O AVref I I I I I I ADTO0A -- Z Z O O O ADTO0B -- Z Z O O O ADTO1A -- Z Z O O O ADTO1B -- Z Z O O O APC PULS0 to PULS7 -- Z Z O O O HCAN-II HTxD0, HTxD1 -- Z Z O O O HRxD0, HRxD1 -- Z Z I O I UBC UBCTRG -- Z Z O O O I/O port PA0 to PA15 Z Z Z I/O I/O I/O PB0 to PB15 Z Z Z I/O I/O I/O PC0 to PC4 Z Z Z I/O I/O I/O PD0 to PD13 Z Z Z I/O I/O I/O PE0 to PE15 -- Z Z Z I/O I/O I/O PF0 to PF5 -- Z PF6 to PF10 -- SSU*2 Note: Z Z Z I/O I/O I/O Z Z I/O I/O I/O PH11 to PF15 Z Z Z I/O I/O I/O PG0 to PG3 Z Z Z I/O I/O I/O PH0 to PH7 -- PH8 to PH15 Z -- Z Z Z I/O I/O I/O Z Z Z I/O I/O I/O PJ0 to PJ15 Z Z Z I/O I/O I/O PK0 to PK15 Z Z Z I/O I/O I/O PL0 to PL13 Z Z Z I/O I/O I/O SSCK0, SSCK1 -- Z Z O O O SSI0, SSI1 -- Z Z I I I SSO0, SSO1 -- Z Z O O O SCS0, SCS1 -- Z Z I/O I/O I/O 1. When the CKHIZ bit in PFCRH is set to 1, becomes high-impedance unconditionally. 2. SSU: Synchronous Serial Communication Unit Rev. 5.00 Feb. 24, 2010 Page 940 of 950 REJ09B0177-0500 Appendix B Pin States Table B.2 Pin States Pin State Reset State Power-Down State Power-On ROMless Expanded Mode Pin Name Type H-UDI Table B.3 8 Bits 16 Bits Expanded Mode Singlewith ROM Chip Hardware Mode Standby Software Standby H-UDI Module Standby AUD Module Standby BusReleased State No Connection TMS I Z Z Z I I Pulled up internally TRST I Z Z Z I I Pulled up internally TDI I Z Z Z I I Pulled up internally TDO O/Z Z Z Z O/Z O/Z O/Z TCK I Z Z Z I I Pulled up internally Pin States Pin State Type Pin Name Hardware Standby Software Standby AUD Module Standby AUD AUDRST Z AUD Reset (AUDRST = L) AUDSRST = 1/ Normal Operation No Connection L input H input Pulled down internally AUDMD Z I I Pulled up internally AUDATA0 to AUDATA3 Z When AUDMD = H: I When AUDMD = L: H (pulled up internally) When AUDMD = H: I/O When AUDMD = L: O Pulled up internally AUDCK Z When AUDMD = H: I When AUDMD = L: H (pulled up internally) When AUDMD = H: I When AUDMD = L: O Pulled up internally AUDSYNC Z When AUDMD = H: I When AUDMD = L: H (pulled up internally) When AUDMD = H: I When AUDMD = L: O Pulled up internally Legend: -- : Not initial value I : Input O : Output H : High-level output L : Low-level output Z : High impedance K : Input pins become high-impedance, output pins retain their state. Rev. 5.00 Feb. 24, 2010 Page 941 of 950 REJ09B0177-0500 Appendix B Pin States Rev. 5.00 Feb. 24, 2010 Page 942 of 950 REJ09B0177-0500 Appendix C Product Lineup Appendix C Product Lineup Table C.1 SH7059 F-ZTAT Product Lineup Product Type SH7059 Table C.2 F-ZTAT Package Operating Temperature (Except for W/E of Flash Memory) R4F70590L80FP R4F70590 256-pin (FP-256H) - 40C to 105C R4F70590K80FP R4F70590 256-pin (FP-256H) - 40C to 125C R4F70590L80BG R4F70590 272-pin (BP-272) - 40C to 105C R4F70590K80BG R4F70590 272-pin (BP-272) - 40C to 125C Model Name Mark Model Name Package Operating Temperature (Except for W/E of Flash Memory) R4F70580SCL80FP R4F70580SC 256-pin (FP-256H) - 40C to 105C R4F70580SCK80FP R4F70580SC 256-pin (FP-256H) - 40C to 125C R4F70580SCL80BG R4F70580SC 272-pin (BP-272) - 40C to 105C R4F70580SCK80BG R4F70580SC 272-pin (BP-272) - 40C to 125C SH7058S F-ZTAT Product Lineup Product Type SH7058S Model Name Mark Model Name F-ZTAT Rev. 5.00 Feb. 24, 2010 Page 943 of 950 REJ09B0177-0500 Appendix C Product Lineup Rev. 5.00 Feb. 24, 2010 Page 944 of 950 REJ09B0177-0500 Appendix D Package Dimensions Appendix D Package Dimensions The package dimension that is shown in the Renesas Semiconductor Package Data Book has Priority. Figure D.1 shows the FP-256H package dimensions of this LSI. Figure D.2 shows the BP-272 package dimensions of this LSI. JEITA Package Code P-QFP256-28x40-0.50 RENESAS Code PRQP0256KB-A Previous Code FP-256H/FP-256HV MASS[Typ.] 7.5g NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. HD *1 D 204 129 205 128 HE b1 c Reference Symbol ZE c1 *2 E bp 77 256 1 Terminal cross section 76 ZD Index mark c A S A2 F L A1 e *3 y S bp x L1 M Detail F D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 Dimension in Millimeters Min 42.3 30.3 0.05 0.17 0.12 0 0.3 Nom Max 40 28 3.20 42.6 42.9 30.6 30.9 3.56 0.15 0.25 0.22 0.27 0.20 0.17 0.22 0.15 8 0.5 0.10 0.08 1.25 1.25 0.5 0.7 1.3 Figure D.1 Package Dimensions (FP-256H) Rev. 5.00 Feb. 24, 2010 Page 945 of 950 REJ09B0177-0500 Appendix D Package Dimensions JEITA Package Code P-BGA272-21x21-1.00 RENESAS Code PRBG0272FA-A MASS[Typ.] 1.3g Previous Code BP-272/BP-272V D w S B E w S A 4x v y1 S y A1 A S S e A e Y ZD W V U T R Reference Symbol P B N Dimension in Millimeters Min Nom D 21.0 K E 21.0 J v M L H G F Max 0.20 w 0.30 A 2.10 E A1 D ZE C B b A 1 2 3 4 5 6 7 8 0.36 0.46 0.56 1.00 e 0.53 0.63 0.73 x 0.10 y 0.15 y1 0.35 9 10 11 12 13 14 15 16 17 18 19 20 b x M S A B SD SE Figure D.2 Package Dimensions (BP-272) Rev. 5.00 Feb. 24, 2010 Page 946 of 950 REJ09B0177-0500 ZD 1.00 ZE 1.00 Main Revisions for This Edition Main Revisions for This Edition Item Page Revision (See Manual for Details) 9.2.4 RAM Emulation Register (RAMER) 120 Table note added Table 9.7 RAM Area Setting Method (SH7059) RAM Area Bit 3: RAMS Bit 0: RAM0 H'FFFE8000 to H'FFFEBFFF 0 * 1 3 1 0 2 3 1 1 H'00000000 to H'00003FFF* * H'00004000 to H'00007FFF* * Notes: 1. Simultaneously, H'00100000 to H'00103FFF is also overlapped by the same RAM area. 2. Simultaneously, H'00104000 to H'00107FFF is also overlapped by the same RAM area. 3. To prevent overlapping use of a RAM area, either leave one of the affected address areas unused or temporarily disable the RAM emulation function by changing the setting of RAMS to 0 before accessing the address area for which overlapping use is to be avoided. 11.4.1 Status Flag Setting Timing 302 Description deleted OSF Setting Timing in Underflow: When a down-counter (DCNT) counts down from H'0001 to H'0000 on DCNT input clock input, the OSF bit is set to 1 in the timer status register (TSR) when the next DCNT input clock pulse is input (when underflow occurs). The timing in this case is shown in figure 11.40. 16.3.6 SS Transmit Data Register 0 to 3 (SSTDR0 to SSTDR3) 407 16.3.7 SS Receive Data Register 0 to 3 (SSRDR0 to SSRDR3) 408 Description amended Although SSTDR can be read or written to by the CPU and DMAC at all times, to achieve reliable serial transmission, write transmit data to SSTDR after confirming that the TDRE bit in SSSR is set to 1, and ensure that the write data size matches the data length specified by DATS1 and DATS0. Description amended Read SSRDR after confirming that the RDRF bit in the SSSR register is set to 1, and ensure that the read data size matches the data length specified by DATS1 and DATS0. SSRDR is a read-only register. SSRDR cannot be written to by the CPU. Rev. 5.00 Feb. 24, 2010 Page 947 of 950 REJ09B0177-0500 Main Revisions for This Edition Item Page Revision (See Manual for Details) 19.1.2 Block Diagram 518 Figure amended Timer control logic Module data bus Bus interface ADTRGR0 ADCR0 Internal data bus A/D conversion control circuit + - Channel A interrupt A/D Priority ATU0 ADTRG0 Interrupt A/D end Sample-andhold circuit ADCSR0 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 Channel B interrupt A/D 10-bit D/A ADDR 0 to 11 Avcc Avref Avss Successiveapproximation register A/D conversion part Analog multiplexer Figure 19.1 Simplified Block Diagram of Multi-Trigger A/D Converter ADI0 ADT00A ADT00B Timer control logic ADT0 Bus interface ADTSR0 ADTIER0 ADDR0B ADDR0A ADCYLR0 ADGR0B ADGR0A ADCNT0 Clock select A/D timer part Module data bus ADTRGR1 ADCR1 ADCSR1 Channel A interrupt A/D Priority Interrupt A/D end Analog multiplexer - ATU1 ADTRG1 ADI1 ADT01A ADT01B ADT1 Timer control logic Module data bus Bus interface ADTSR1 ADTIER1 ADDR1B ADDR1A ADCYLR1 ADGR1B ADGR1A ADCNT1 Clock select A/D timer part Rev. 5.00 Feb. 24, 2010 Page 948 of 950 REJ09B0177-0500 Internal data bus A/D conversion control circuit + Channel B interrupt A/D AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 ADDR 12 to 23 10-bit D/A Successiveapproximation register Avcc Avref Avss Bus interface Module data bus A/D conversion part Main Revisions for This Edition Item Page Revision (See Manual for Details) 25.4.4 RAM Emulation Register (RAMER) 749 Description amended Table 25.7 Overlapping of RAM Area and User MAT Area * Bits 15 to 4, 2, 1--Reserved: These bits are always read as 0. The write value should always be 0. * Bit 0--User MAT Area Select: These bits are used with bit 3 to select the user-MAT area to be overlapped with the on-chip RAM. (See table 25.7.) Table note added RAM Area Block Name RAMS RAM0 H'FFFE8000 to H'FFFEBFFF RAM area (16 Kbytes) 0 * 1 3 EB0 - EB3 (16 Kbytes) 1 0 2 3 EB4 - EB7 (16 Kbytes) 1 1 H'00000000 to H'00003FFF* * H'00004000 to H'00007FFF* * Notes: 1. Simultaneously, H'00100000 to H'00103FFF is also overlapped by the same RAM area. 2. Simultaneously, H'00104000 to H'00107FFF is also overlapped by the same RAM area. 3. To prevent overlapping use of a RAM area, either leave one of the affected address areas unused or temporarily disable the RAM emulation function by changing the setting of RAMS to 0 before accessing the address area for which overlapping use is to be avoided. Appendix D Package Dimensions 945 Package dimensions replaced 946 Package dimensions replaced Figure D.1 Package Dimensions (FP-256H) Figure D.2 Package Dimensions (BP-272) Rev. 5.00 Feb. 24, 2010 Page 949 of 950 REJ09B0177-0500 Main Revisions for This Edition Rev. 5.00 Feb. 24, 2010 Page 950 of 950 REJ09B0177-0500 Renesas 32-Bit RISC Microcomputer Hardware Manual SH-2E SH7059 F-ZTATTM, SH7058S F-ZTATTM Publication Date: Rev.1.00, February 21, 2007 Rev.5.00, February 24, 2010 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. (c) 2010. Renesas Technology Corp., All rights reserved. Printed in Japan. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES http://www.renesas.com Refer to "http://www.renesas.com/en/network" for the latest and detailed information. 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