SN54F10, SN74F10 TRIPLE 3-INPUT POSITIVE-NAND GATES SDFS039A - MARCH 1987 - REVISED OCTOBER 1993 * SN54F10 . . . J PACKAGE SN74F10 . . . D OR N PACKAGE (TOP VIEW) Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs 1A 1B 2A 2B 2C 2Y GND description These devices contain three independent 3-input NAND gates. They perform the Boolean functions Y = A * B * C or Y = A + B + C in positive logic. The SN54F10 is characterized for operation over the full military temperature range of - 55C to 125C. The SN74F10 is characterized for operation from 0C to 70C. 1B 1C 2A 2B 2C 3A 3B 3C 1 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3C 3B 3A 3Y 1B 1A NC VCC 1C OUTPUT Y B C H H H L L X X H X L X H X X L H 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 1Y NC 3C NC 3B 2Y GND NC 3Y 3A A 2A NC 2B NC 2C logic symbol 1A 14 2 SN54F10 . . . FK PACKAGE (TOP VIEW) FUNCTION TABLE (each gate) INPUTS 1 NC - No internal connection & 2 12 13 1Y 3 4 logic diagram, each gate (positive logic) A 6 5 B 2Y Y C 9 10 11 8 3Y This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages. Copyright 1993, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 2-1 SN54F10, SN74F10 TRIPLE 3-INPUT POSITIVE-NAND GATES SDFS039A - MARCH 1987 - REVISED OCTOBER 1993 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 1.2 V to 7 V Input current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 30 mA to 5 mA Voltage range applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VCC Current into any output in the low state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA Operating free-air temperature range: SN54F10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 125C SN74F10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input voltage ratings may be exceeded provided the input current ratings are observed. recommended operating conditions SN54F10 VCC VIH Supply voltage VIL IIK Low-level input voltage IOH IOL High-level output current Low-level output current TA Operating free-air temperature High-level input voltage SN74F10 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 2 2 Input clamp current - 55 UNIT V V 0.8 0.8 V - 18 - 18 mA -1 -1 mA 20 20 mA 70 C 125 0 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VOL II TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, II = - 18 mA IOH = - 1 mA VCC = 4.75 V, VCC = 4.5 V, IOH = - 1 mA IOL = 20 mA VCC = 5.5 V, VCC = 5.5 V, VI = 7 V VI = 2.7 V VCC = 5.5 V, VCC = 5.5 V, VI = 0.5 V VO = 0 VCC = 5.5 V, VCC = 5.5 V, VI = 0 VI = 4.5 V MIN SN54F10 TYP MAX MIN SN74F10 TYP MAX - 1.2 2.5 3.4 - 1.2 2.5 3.4 0.5 V 0.1 0.1 mA 20 20 A - 0.6 mA -150 mA 1.4 2.1 mA ICCL 5.1 7.7 5.1 All typical values are at VCC = 5 V, TA = 25C. Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. 7.7 mA IIH IIL IOS ICCH 2-2 POST OFFICE BOX 655303 0.5 0.3 V V 2.7 0.3 UNIT - 0.6 - 60 -150 1.4 * DALLAS, TEXAS 75265 2.1 - 60 SN54F10, SN74F10 TRIPLE 3-INPUT POSITIVE-NAND GATES SDFS039A - MARCH 1987 - REVISED OCTOBER 1993 switching characteristics (see Note 2) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 5 V, CL = 50 pF, RL = 500 , TA = 25C VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 , TA = MIN to MAX F10 tPLH tPHL A B, A, B or C Y SN54F10 UNIT SN74F10 MIN TYP MAX MIN MAX MIN 1.6 3.3 5 1.2 7 1.6 MAX 6 1 2.8 4.3 1 6.5 1 5.3 ns For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. NOTE 2: Load circuits and waveforms are shown in Section 1. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 2-3 PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) 5962-9757901Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 59629757901Q2A SNJ54F 10FK 5962-9757901QCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9757901QC A SNJ54F10J JM38510/33003B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 33003B2A JM38510/33003BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 33003BCA JM38510/33003BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 33003BDA M38510/33003B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 33003B2A M38510/33003BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 33003BCA M38510/33003BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 33003BDA SN54F10J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SN54F10J SN74F10D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 F10 SN74F10DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 F10 SN74F10N ACTIVE PDIP N 14 25 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 SN74F10N SN74F10NSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 74F10 SNJ54F10FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 59629757901Q2A SNJ54F 10FK SNJ54F10J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9757901QC A Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 24-Aug-2018 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) SNJ54F10J (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. 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OTHER QUALIFIED VERSIONS OF SN54F10, SN74F10 : * Catalog: SN74F10 Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 * Military: SN54F10 NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product * Military - QML certified for Military and Defense Applications Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74F10DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74F10NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74F10DR SN74F10NSR SOIC D 14 2500 367.0 367.0 38.0 SO NS 14 2000 367.0 367.0 38.0 Pack Materials-Page 2 PACKAGE OUTLINE J0014A CDIP - 5.08 mm max height SCALE 0.900 CERAMIC DUAL IN LINE PACKAGE PIN 1 ID (OPTIONAL) A 4X .005 MIN [0.13] .015-.060 TYP [0.38-1.52] 1 14 12X .100 [2.54] 14X .014-.026 [0.36-0.66] 14X .045-.065 [1.15-1.65] .010 [0.25] C A B .754-.785 [19.15-19.94] 8 7 B .245-.283 [6.22-7.19] .2 MAX TYP [5.08] C .13 MIN TYP [3.3] SEATING PLANE .308-.314 [7.83-7.97] AT GAGE PLANE .015 GAGE PLANE [0.38] 0 -15 TYP 14X .008-.014 [0.2-0.36] 4214771/A 05/2017 NOTES: 1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is hermitically sealed with a ceramic lid using glass frit. 4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only. 5. Falls within MIL-STD-1835 and GDIP1-T14. www.ti.com EXAMPLE BOARD LAYOUT J0014A CDIP - 5.08 mm max height CERAMIC DUAL IN LINE PACKAGE (.300 ) TYP [7.62] SEE DETAIL A SEE DETAIL B 1 14 12X (.100 ) [2.54] SYMM 14X ( .039) [1] 8 7 SYMM LAND PATTERN EXAMPLE NON-SOLDER MASK DEFINED SCALE: 5X .002 MAX [0.05] ALL AROUND (.063) [1.6] METAL ( .063) [1.6] SOLDER MASK OPENING METAL (R.002 ) TYP [0.05] .002 MAX [0.05] ALL AROUND SOLDER MASK OPENING DETAIL A DETAIL B SCALE: 15X 13X, SCALE: 15X 4214771/A 05/2017 www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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