1Doc. No. MD-1071, Rev. E© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
■CMOS and TTL Compatible I/O
■Automatic Page Write Operation:
– 1 to 64 Bytes in 10ms
– Page Load Timer
■End of Write Detection:
– Toggle Bit
– DATADATA
DATADATA
DATA Polling
■Hardware and Software Write Protection
■100,000 Program/Erase Cycles
■100 Year Data Retention
FEATURES
■3.0V to 3.6V Supply
■Read Access Times: 200/250/300 ns
■Low Power CMOS Dissipation:
– Active: 15 mA Max.
– Standby: 150 µA Max.
■Simple Write Operation:
– On-Chip Address and Data Latches
– Self-Timed Write Cycle with Auto-Clear
■Fast Write Cycle Time:
– 10ms Max.
■Commercial, Industrial and Automotive
Temperature Ranges
DESCRIPTION
The CAT28LV256 is a fast, low power, low voltage
CMOS Parallel E2PROM organized as 32K x 8-bits. It
requires a simple interface for in-system programming.
On-chip address and data latches, self-timed write cycle
with auto-clear and VCC power up/down write protection
eliminate additional timing and protection hardware.
DATA Polling and Toggle status bits signal the start and
end of the self-timed write cycle. Additionally, the
CAT28LV256 features hardware and software write
protection.
The CAT28LV256 is manufactured using Catalyst’s
advanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC–
approved 28-pin DIP, 28-pin TSOP or 32-pin PLCC
packages.
BLOCK DIAGRAM
28LV256 F01
ADDR. BUFFER
& LATCHES
ADDR. BUFFER
& LATCHES
INADVERTENT
WRITE
PROTECTION
CONTROL
LOGIC
TIMER
ROW
DECODER
COLUMN
DECODER
HIGH V OL TA GE
GENERATOR
A6–A14
CE
OE
WE
A0–A5
I/O0–I/O7
I/O BUFFERS
32,768 x 8
E
2
PROM
ARRAY
64 BYTE PAGE
REGISTER
VCC
DATA POLLING
AND
TOGGLE BIT
256K-Bit CMOS PARALLEL EEPROM
CAT28LV256
CAT28LV256
2
Doc. No. MD-1071, Rev. E © 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
PLCC Package (N, G)
DIP Package (P, L)
PIN CONFIGURATION
TSOP Top View (8mm X 13.4mm) (H)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
I/O6
I/O5
I/O4
GND
I/O2
A1
A2
VCC
WE
A8
A9
A11
OE
A7
A6
A5
A4
A3
A10
I/O7
A12
16
15
CE
I/O3
I/O1
I/O0
A0
A13
A14
I/O2
VSS
I/O6
I/O5
13
14
20
19
18
17
9
10
11
12
24
23
22
21
A1
A0
I/O0
I/O1
OE
A10
CE
I/O7
A5
A4
A3
A2
5
6
7
8
1
2
3
4
A14
A12
A7
A6A9
A11
28
27
26
25
VCC
WE
A13
A8A6
A5
A4
A3
5
6
7
8
A2
A1
A0
NC
9
10
11
12
I/O013
A8
A9
A11
NC
29
28
27
26 OE
A10
CE
25
24
23
22 I/O7
21
I/O1
I/O2
VSS
NC
I/O3
I/O4
I/O5
14 15 16 17 18 19 20
4321323130
A7
A12
A14
NC
VCC
WE
A13
I/O4
I/O3
16
15
I/O6
TOP VIEW
PIN FUNCTIONS
Pin Name Function Pin Name Function
A0–A14 Address Inputs WE Write Enable
I/O0–I/O7Data Inputs/Outputs VCC 3.0 to 3.6 V Supply
CE Chip Enable VSS Ground
OE Output Enable NC No Connect
CAT28LV256
3Doc. No. MD-1071, Rev. E© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAPACITANCE TA = 25°C, f = 1.0 MHz
Symbol Test Max. Units Conditions
CI/O(1) Input/Output Capacitance 10 pF VI/O = 0V
CIN(1) Input Capacitance 6 pF VIN = 0V
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC +1V.
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground(2) ........... –2.0V to +VCC + 2.0V
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C)................................... 1.0W
Lead Soldering Temperature (10 secs)............ 300°C
Output Short Circuit Current(3) ........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol Parameter Min. Max. Units Test Method
NEND(1) Endurance 100,000 Cycles/Byte MIL-STD-883, Test Method 1033
TDR(1) Data Retention 100 Years MIL-STD-883, Test Method 1008
VZAP(1) ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015
ILTH(1)(4) Latch-Up 100 mA JEDEC Standard 17
MODE SELECTION
Mode CE WE OE I/O Power
Read L H L DOUT ACTIVE
Byte Write (WE Controlled) L H DIN ACTIVE
Byte Write (CE Controlled) L H DIN ACTIVE
Standby, and Write Inhibit H X X High-Z STANDBY
Read and Write Inhibit X H H High-Z ACTIVE
CAT28LV256
4
Doc. No. MD-1071, Rev. E © 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
D.C. OPERATING CHARACTERISTICS
VCC = 3.0V to 3.6V, unless otherwise specified
Limits
Symbol Parameter Min. Typ. Max. Units Test Conditions
ICC VCC Current (Operating, TTL) 15 mA CE = OE = VIL,
f = 1/tRC min, All I/O’s Open
ISBC(2) VCC Current (Standby, CMOS) 150 µACE = VIHC,
All I/O’s Open
ILI Input Leakage Current –1 1 µAV
IN = GND to VCC
ILO Output Leakage Current –5 5 µAV
OUT = GND to VCC,
CE = VIH
VIH(2) High Level Input Voltage 2 VCC +0.3 V
VIL Low Level Input Voltage –0.3 0.6 V
VOH High Level Output Voltage 2 V IOH = –100µA
VOL Low Level Output Voltage 0.3 V IOL = 1.0mA
VWI Write Inhibit Voltage 2 V
A.C. CHARACTERISTICS, Read Cycle
VCC = 3.0V to 3.6V, unless otherwise specified
28LV256-20 28LV256-25 28LV256-30
Symbol Parameter Min. Max. Min. Max. Min. Max. Units
tRC Read Cycle Time 200 250 300 ns
tCE CE Access Time 200 250 300 ns
tAA Address Access Time 200 250 300 ns
tOE OE Access Time 80 100 110 ns
tLZ(1) CE Low to Active Output 0 0 0 ns
tOLZ(1) OE Low to Active Output 0 0 0 ns
tHZ(1)(3) CE High to High-Z Output 50 55 60 ns
tOHZ(1)(3) OE High to High-Z Output 50 55 60 ns
tOH(1) Output Hold from Address Change 0 0 0 ns
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) VIHC = VCC –0.3V to VCC +0.3V.
(3) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer.
CAT28LV256
5Doc. No. MD-1071, Rev. E© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
A.C. CHARACTERISTICS, Write Cycle
VCC = 3.0V to 3.6V, unless otherwise specified
28LV256-20 28LV256-25 28LV256-30
Symbol Parameter Min. Max. Min. Max. Min. Max. Units
tWC Write Cycle Time 10 10 10 ms
tAS Address Setup Time 0 0 0 ns
tAH Address Hold Time 100 100 100 ns
tCS CE Setup Time 0 0 0 ns
tCH CE Hold Time 0 0 0 ns
tCW(3) CE Pulse Time 150 150 150 ns
tOES OE Setup Time 0 0 0 ns
tOEH OE Hold Time 0 0 0 ns
tWP(3) WE Pulse Width 150 150 150 ns
tDS Data Setup Time 50 50 50 ns
tDH Data Hold Time 0 0 0 ns
tINIT(1) Write Inhibit Period After Power-up 5 10 5 10 5 1 0 ms
tBLC(1)(4) Byte Load Cycle Time 0.15 100 0.15 100 0.15 100 µs
Vcc
1.8K
CL = 100 pF
CL INCLUDES JIG CAPACITANCE
1.3K
DEVICE
UNDER
TEST
OUTPUT
INPUT PULSE LEVELS REFERENCE POINTS
2.0 V
0.6 V
VCC - 0.3V
0.0 V
Figure 1. A.C. Testing Input/Output Waveform(2)
28LV256 F04
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Input rise and fall times (10% and 90%) < 10 ns.
(3) A write pulse of less than 20ns duration will not initiate a write cycle.
(4) A timer of duration tBLC max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin;
however a transition from HIGH to LOW within tBLC max. stops the timer.
Figure 2. A.C. Testing Load Circuit (example)
28LV256 F05
CAT28LV256
6
Doc. No. MD-1071, Rev. E © 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
ADDRESS
CE
OE
WE
DATA OUT
tAS
DATA IN D A TA VALID
HIGH-Z
tCS
tAH tCH
tWC
tOEH
tBLC
tDH
tDS
tOES tWP
ADDRESS
CE
OE
WE
tRC
DATA OUT D A TA VALIDD A TA VALID
tCE
tOE
tOH
tAA
tOHZ
tHZ
VIH
HIGH-Z
tLZ
tOLZ
DEVICE OPERATION
Read
Data stored in the CAT28LV256 is transferred to the
data bus when WE is held high, and both OE and CE are
held low. The data bus is set to a high impedance state
when either CE or OE goes high. This 2-line control
architecture can be used to eliminate bus contention in
a system environment.
Byte Write
A write cycle is executed when both CE and WE are low,
and OE is high. Write cycles can be initiated using either
WE or CE, with the address input being latched on the
falling edge of WE or CE, whichever occurs last. Data,
conversely, is latched on the rising edge of WE or CE,
whichever occurs first. Once initiated, a byte write cycle
automatically erases the addressed byte and the new
data is written within 10 ms.
Figure 3. Read Cycle
28LV256 F06
Figure 4. Byte Write Cycle [WEWE
WEWE
WE Controlled]
28LV256 F07
CAT28LV256
7Doc. No. MD-1071, Rev. E© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
OE
CE
WE
ADDRESS
I/O
tWP tBLC
BYTE 0 BYTE 1 BYTE 2 BYTE n BYTE n+1 BYTE n+2
LAST BYTE
tWC
ADDRESS
CE
OE
WE
DATA OUT
tAS
DATA IN D A TA VALID
HIGH-Z
tAH
tWC
tOEH
tDH
tDS
tOES
tBLC
tCH
tCS
tCW
Page Write
The page write mode of the CAT28LV256 (essentially
an extended BYTE WRITE mode) allows from 1 to 64
bytes of data to be programmed within a single E2PROM
write cycle. This effectively reduces the byte-write time
by a factor of 64.
Following an initial WRITE operation (WE pulsed low, for
tWP, and then high) the page write mode can begin by
issuing sequential WE pulses, which load the address
and data bytes into a 64 byte temporary buffer. The page
address where data is to be written, specified by bits A6
to A14, is latched on the last falling edge of WE. Each
byte within the page is defined by address bits A0 to A5
(which can be loaded in any order) during the first and
subsequent write cycles. Each successive byte load
cycle must begin within tBLC MAX of the rising edge of the
preceding WE pulse. There is no page write window
limitation as long as WE is pulsed low within tBLC MAX.
Upon completion of the page write sequence, WE must
stay high a minimum of tBLC MAX for the internal auto-
matic program cycle to commence. This programming
cycle consists of an erase cycle, which erases any data
that existed in each addressed cell, and a write cycle,
which writes new data back into the cell. A page write will
only write data to the locations that were addressed and
will not rewrite the entire page.
Figure 5. Byte Write Cycle [CECE
CECE
CE Controlled]
28LV256 F08
Figure 6. Page Mode Write Cycle
28LV256 F09
CAT28LV256
8
Doc. No. MD-1071, Rev. E © 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
WE
CE
OE
I/O6
tOEH tOE tOES
tWC
(1) (1)
ADDRESS
CE
WE
OE
I/O7DIN = X DOUT = X DOUT = X
tOE
tOEH
tWC
tOES
DATADATA
DATADATA
DATA Polling
DATA polling is provided to indicate the completion of
write cycle. Once a byte write or page write cycle is
initiated, attempting to read the last byte written will
output the complement of that data on I/O7 (I/O0–I/O6
are indeterminate) until the programming cycle is com-
plete. Upon completion of the self-timed write cycle, all
I/O’s will output true data during a read cycle.
Toggle Bit
In addition to the DATA Polling feature, the device can
determine the completion of a write cycle, while a write
cycle is in progress, by reading data from the device.
This results in I/O6 toggling between one and zero. Once
the write is complete, however, I/O6 stops toggling and
valid data can be read from the device.
Figure 7. DATA Polling
28LV256 F10
Figure 8. Toggle Bit
28LV256 F11
Note:
(1) Beginning and ending state of I/O6 is indeterminate.
CAT28LV256
9Doc. No. MD-1071, Rev. E© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
WRITE DATA: AA
ADDRESS: 5555
WRITE DATA: 55
ADDRESS: 2AAA
WRITE DATA: 80
ADDRESS: 5555
WRITE DATA: AA
ADDRESS: 5555
WRITE DATA: 55
ADDRESS: 2AAA
WRITE DATA: 20
ADDRESS: 5555
SOFTWARE DATA
PRO TECTION A CTIV A TED (1)
WRITE DATA: XX
WRITE LAST BYTE
TO
LAST ADDRESS
TO ANY ADDRESS
WRITE DATA: AA
ADDRESS: 5555
WRITE DATA: 55
ADDRESS: 2AAA
WRITE DATA: A0
ADDRESS: 5555
(4) Noise pulses of less than 20 ns on the WE or CE
inputs will not result in a write cycle.
SOFTWARE DATA PROTECTION
The CAT28LV256 features a software controlled data
protection scheme which, once enabled, requires a data
algorithm to be issued to the device before a write can be
performed. The device is shipped from Catalyst with the
software protection NOT ENABLED (the CAT28LV256
is in the standard operating mode).
Figure 9. Write Sequence for Activating Software
Data Protection Figure 10. Write Sequence for Deactivating
Software Data Protection
28LV256 F12 28LV256 F13
Note:
(1) Write protection is activated at this point whether or not any more writes are completed. Writing to addresses must occur within tBLC
Max., after SDP activation.
HARDWARE DATA PROTECTION
The following hardware data protection features are
incorporated into the CAT28LV256.
(1) VCC sense provides write protection when VCC falls
below 2.0V min.
(2) A power on delay mechanism, tINIT (see AC charac-
teristics), provides a 5 to 10 ms delay before a write
sequence, after VCC has reached 2.4V min.
(3) Write inhibit is activated by holding any one of OE
low, CE high, or WE high.
CAT28LV256
10
Doc. No. MD-1071, Rev. E © 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
CE
WE
AA
5555 55
2AAA
DATA
ADDRESS tWC80
5555 AA
5555 55
2AAA 20
5555 SDP
RESET
DEVICE
UNPROTECTED
CE
WE
tWP
AA
5555 55
2AAA A0
5555
DATA
ADDRESS
tBLC
tWC
BYTE OR
PAGE
WRITES
ENABLED
To activate the software data protection, the device must
be sent three write commands to specific addresses with
specific data (Figure 9). This sequence of commands
(along with subsequent writes) must adhere to the page
write timing specifications (Figure 11). Once this is done,
all subsequent byte or page writes to the device must be
preceded by this same set of write commands. The data
protection mechanism is activated until a deactivate
sequence is issued, regardless of power on/off transi-
tions. This gives the user added inadvertent write pro-
tection on power-up in addition to the hardware protec-
tion provided.
To allow the user the ability to program the device with
an E2PROM programmer (or for testing purposes) there
is a software command sequence for deactivating the
data protection. The six step algorithm (Figure 10) will
reset the internal protection circuitry, and the device will
return to standard operating mode (Figure 12 provides
reset timing). After the sixth byte of this reset sequence
has been issued, standard byte or page writing can
commence.
Figure 11. Software Data Protection Timing
Figure 12. Resetting Software Data Protection Timing
CAT28LV256
11 Doc. No. MD-1071, Rev. E© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
Prefix Device # Suffix
28LV256
Product
Number
CAT
Optional
Company
ID
NI
T
Tape & Reel
T: 500/Reel
Package
P: PDIP(2)
N: PLCC(2)
-25
Temperature Range
Blank = Commercial (0˚C to +70˚C)
I = Industrial (-40˚C to +85˚C)
A = Automotive (-40˚ to +105˚C)
Speed
25: 250ns
30: 300ns
20: 200ns(3)
E = Extended (-40˚C to +125˚C)
L: PDIP (Lead free, Halogen free)
G: PLCC (Lead free, Halogen free)
H: TSOP (Lead free, Halogen free)
EXAMPLE OF ORDERING INFORMATION(1)
ORDERING INFORMATION
Notes:
(1) The device used in the above example is a CAT28LV256NI-25T (100,000 Cycle Endurance, PLCC, Industrial temperature, 250 ns
Access Time, Tape & Reel).
(2) Solder-plate (tin-lead) packages, contact Factory for availability.
(3) Commercial and industrial temperature range only.
srebmuNtraPelbaredrO )seciveDeerF-bProf(
T02-IG652VL82TACT52EH652VL82TAC
T52-IG652VL82TACT03EH652VL82TAC
T03-IG652VL82TAC02IL652VL82TAC
T52-AG652VL82TAC52IL652VL82TAC
T03-AG652VL82TAC03IL652VL82TAC
T52-EG652VL82TAC52AL652VL82TAC
T03-EG652VL82TAC03AL652VL82TAC
T02IH652VL82TAC52EL652VL82TAC
T52IH652VL82TAC03EL652VL82TAC
T03IH652VL82TAC T52AH652VL82TAC T03AH652VL82TAC
CAT28LV256
12
Doc. No. MD-1071, Rev. E © 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
REVISION HISTORY
Date Revision Description
03-Feb-04 A Assigned doc number
Updated Ordering Info
27-Feb-04 B Added Green Packages
15-Oct-08 C Eliminate TSOP (8mm x 13.4mm) SnPb package.
18-Nov-08 D Change logo and fine print to ON Semiconductor
30-Jul-09 E Update Example of Ordering Information
Update Ordering Information table
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any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising
out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights
of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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