General Description
The MAX17005A/MAX17006A/MAX17015A are high-fre-
quency multichemistry battery chargers. These circuits
feature a new high-frequency current-mode architecture
that significantly reduces component size and cost. The
charger uses a high-side MOSFET with n-channel syn-
chronous rectifier. Widely adjustable charge current,
charge voltage, and input current limit simplify the con-
struction of highly accurate and efficient chargers.
The charge voltage and charge current are set with
analog control inputs. The charge current setting can
also be adjusted with a PWM input. High-accuracy cur-
rent-sense amplifiers provide fast cycle-by-cycle cur-
rent-mode control to protect against short circuits to the
battery and respond quickly to system load transients.
In addition, the charger provides a high-accuracy ana-
log output that is proportional to the adapter current. In
the MAX17015A, this current monitor remains active
when the adapter is absent to monitor battery dis-
charge current.
The MAX17005A charges three or four Li+ series cells,
and the MAX17006A charges two or three Li+ series
cells. The MAX17015A adjusts the charge voltage set-
ting and the number of cells through a feedback resis-
tor-divider from the output. All variants of the charger
can provide at least 4A of charge current with a 10mΩ
sense resistor.
The charger utilizes a charge pump to control an n-channel
adapter selection switch. The charge pump remains
active even when the charger is off. When the adapter
is absent, a p-channel MOSFET selects the battery.
The MAX17005A/MAX17006A/MAX17015A are avail-
able in a small, 4mm x 4mm x 0.8mm 20-pin, lead-free
TQFN package. An evaluation kit is available to reduce
design time.
Applications
Notebook Computers
Tablet PCs
Portable Equipment with Rechargeable Batteries
Features
♦High Switching Frequency (1.2MHz)
♦Controlled Inductor Current-Ripple Architecture
Reduced BOM Cost
Small Inductor and Output Capacitors
♦±0.4% Accurate Charge Voltage
♦±2.5% Accurate Input-Current Limiting
♦±3% Accurate Charge Current
♦Single-Point Compensation
♦Monitor Outputs for
±2.5% Accurate Input Current Limit
±2.5% Battery Discharge Current
(MAX17015A Only)
AC Adapter Detection
♦Analog/PWM Adjustable Charge-Current Setting
♦Battery Voltage Adjustable for 3 and 4 Cells
(MAX17005A) or 2 and 3 Cells (MAX17006A)
♦Adjustable Battery Voltage (4.2V to 4.4V/Cell)
♦Cycle-by-Cycle Current Limit
Battery Short-Circuit Protection
Fast Response for Pulse Charging
Fast System-Load-Transient Response
♦Programmable Charge Current < 5A
♦Automatic System Power Source Selection with
n-Channel MOSFET
♦Internal Boost Diode
♦+8V to +26V Input-Voltage Range
MAX17005A/MAX17006A/MAX17015A
1.2MHz, Low-Cost,
High-Performance Chargers
________________________________________________________________
Maxim Integrated Products
1
Ordering Information
19-4355; Rev 0; 10/08
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
+
Denotes a lead-free/RoHS compliant package.
*
Future product—contact factory for availability.
*
*
EP = Exposed pad.
PART TEMP RANGE
PIN-PACKAGE
MAX17005AETP+ -40°C to +85°C 20 TQFN-EP**
MAX17006AETP+*
-40°C to +85°C 20 TQFN-EP**
MAX17015AETP+ -40°C to +85°C 20 TQFN-EP**
Pin Configuration and Minimal Operating Circuit appear at
end of data sheet.
MAX17005A/MAX17006A/MAX17015A
1.2MHz, Low-Cost,
High-Performance Chargers
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VDCIN = VCSSP = VCSSN = 19V, VBATT = VCSIP = VCSIN = 16.8V, VVCTL = VAA, VISET = 1V, TA= 0°C to +85°C,
unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DCIN, CSSP, CSSN, BATT, CSIN, CSIP, ACOK,
LX to AGND .......................................................-0.3V to +30V
BST to LDO.............................................................-0.3V to +30V
CSIP to CSIN, CSSP to CSSN .............................. -0.3V to +0.3V
IINP, FB, ACIN to AGND.............................-0.3V to (VAA + 0.3V)
VAA, LDO, ISET, VCTL, CC to AGND .......................-0.3V to +6V
DHI to LX ....................................................-0.3V to (BST + 0.3V)
BST to LX..................................................................-0.3V to +6V
DLO to PGND ............................................-0.3V to (LDO + 0.3V)
PGND to AGND .................................................... -0.3V to +0.3V
Continuous Power Dissipation (TA= +70°C)
16-Pin TQFN (derate 16.9mW/°C above +70°C)....1349.1mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER CONDITIONS MIN TYP MAX UNITS
CHARGE-VOLTAGE REGULATION
2 cells, VVCTL = GND (MAX17006A) 8.3664 8.40 8.4336
3 cells, VVCTL = VAA (MAX17005A/MAX17006A) 12.549 12.60 12.651
4 cells, VVCTL = GND (MAX17005A) 16.733 16.80 16.867
Battery Regulation-Voltage Accuracy
FB accuracy using FB divider (MAX17015A)
(Note 1) 2.0916 2.1 2.1084
V
FB Input Bias Curent -1 +1 μA
2 cells (MAX17006A), 4 cells (MAX17005A) 0 VAA/2
-0.2
VCTL Range
3 cells (MAX17005A/MAX17006A) VAA/2
+0.2 V
AA
V
VCTL Gain VCELL/VVCTL 5.85 6 6.15 V/V
VCTL Input Bias Current VVCTL = GND and VCTL = VAA -1 +1 μA
CHARGE-CURRENT REGULATION
ISET Range 0 VAA/2 V
ISET = 1.4V 80
ISET Full-Scale Setting ISET = 99.9% duty cycle 60 mV
58.2 60 61.8 mV
VISET = VAA/4 or ISET
= 99.9% duty cycle -3 +3 %
38.2 40 41.8 mV
Full-Charge Current Accuracy
(CSIP to CSIN) VISET = VAA/6 or ISET
= 66.7% duty cycle -4.5 +4.5 %
1.4 3 4.6 mV
Trickle Charge-Current Accuracy
VBATT = 1V to 16.8V
VISET = VAA/80 or ISET
= 5% duty cycle -52 +52 %
Charge-Current Gain Error Based on VISET = VVAA/4 and VISET = VVAA/80 -2 +2 %
Charge-Current Offset Error Based on VISET = VVAA/4 and VISET = VVAA/80 -1.4 +1.4 mV
BATT/CSIP/CSIN Input-Voltage Range 0 24 V
ISET falling 21 26 31
ISET Power-Down Mode Threshold ISET rising 33 40 47 mV
MAX17005A/MAX17006A/MAX17015A
1.2MHz, Low-Cost,
High-Performance Chargers
_______________________________________________________________________________________ 3
PARAMETER CONDITIONS MIN TYP MAX UNITS
VISET = 3V -0.2 +0.2
ISET Input Bias Current CSSN = BATT, VISET = 5V -0.2 +0.2 μA
Rising 2.4
ISET PWM Threshold Falling 0.8
V
ISET Frequency 0.128 500 kHz
ISET Effective Resolution fPWM = 3.2MHz 8 Bits
INPUT-CURRENT REGULATION
58.5 60 61.5 mV
Input Current-Limit Threshold VCSSP - VCSSN -2.5 +2.5 %
CSSN Input Bias Current Adapter present -0.1 +0.1 μA
CSSP/CSSN Input-Voltage Range 8.0 26.0 V
IINP Transconductance VCSSP - VCSSN = 60mV 2.66 2.8 2.94 μA/mV
VCSSP - VCSSN = 60mV, VIINP = 0 to 4.5V -2.5 +2.5
IINP Accuracy VCSSP - VCSSN = 35mV -2.5 +2.5 %
SUPPLY AND LINEAR REGULATOR
DCIN Input-Voltage Range 8 26 V
DCIN falling 7.9 8.1
DCIN Undervoltage-Lockout (UVLO) Trip-Point DCIN rising 8.7 8.9 V
Adapter present (Note 2) 3 6 mA
DCIN + CSSP + CSSN Quiescent Current Adapter absent (Note 2) 30 50 μA
Adapter absent (Note 2) 10 20
VBATT = 16.8V Charger shutdown (Note 2) 10 20
BATT + CSIP + CSIN + LX Input Current
VBATT = 2V to 19V, adapter present (Note 2) 200 500
μA
LDO Output Voltage 8.0V < VDCIN < 26V, no load 5.15 5.35 5.55 V
LDO Load Regulation 0 < ILDO < 40mA 100 200 mV
LDO UVLO Threshold 3.2 4.1 5.0 V
REFERENCES
VAA Output Voltage IVAA = 50μA 4.18 4.20 4.22 V
VAA UVLO Threshold VAA falling 3.1 3.9 V
ACIN
ACIN Threshold 2.058 2.1 2.142 V
ACIN Threshold Hysteresis 10 20 30 mV
ACIN Input Bias Current -1 +1 μA
ACOK
ACOK Sink Current V
ACOK = 0.4V, VACIN = 1.5V 6 mA
ACOK Leakage Current V
ACOK = 5.5V, VACIN = 2.5V 1 μA
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VDCIN = VCSSP = VCSSN = 19V, VBATT = VCSIP = VCSIN = 16.8V, VVCTL = VAA, VISET = 1V, TA= 0°C to +85°C,
unless otherwise noted. Typical values are at TA= +25°C.)
MAX17005A/MAX17006A/MAX17015A
1.2MHz, Low-Cost,
High-Performance Chargers
4 _______________________________________________________________________________________
PARAMETER CONDITIONS MIN TYP MAX UNITS
SWITCHING REGULATOR
DHI Off-Time K Factor VDCIN = 19V, VBATT = 10V 0.029 0.030 0.041 μs/V
Sense Voltage for Minimum Discontinuous
Mode Ripple Current VCSIP - VCSIN 10 mV
Zero-Crossing Comparator Threshold VCSIP - VCSIN 10 mV
Cycle-by-Cycle Current-Limit Sense Voltage VCSIP - VCSIN 105 110 115 mV
DHI Resistance High IDLO = 10mA 1.5 3
DHI Resistance Low IDLO = -10mA 0.8 1.75
DLO Resistance High IDLO = 10mA 3 6
DLO Resistance Low IDLO = -10mA 3 7
ADAPTER DETECTION
Adapter Absence-Detect Threshold VDCIN - VBATT, VDCIN falling +70 +120 +170 mV
Adapter Detect Threshold VDCIN - VBATT, VDCIN rising +360 +420 +580 mV
Adapter Switch Charge-Pump Frequency Charger Shutdown 180 200 220 Hz
DLO 0.04 0.1 0.20
Adapter Switch Charge-Pump Refresh Pulse DHI 0.07 0.15 0.30 μs
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VDCIN = VCSSP = VCSSN = 19V, VBATT = VCSIP = VCSIN = 16.8V, VVCTL = VAA, VISET = 1V, TA= 0°C to +85°C,
unless otherwise noted. Typical values are at TA= +25°C.)
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VDCIN = VCSSP = VCSSN = 19V, VBATT = VCSIP = VCSIN = 16.8V, VVCTL = VAA, VISET = 1V, TA= -40°C to +85°C,
unless otherwise noted.)
PARAMETER CONDITIONS MIN TYP MAX UNITS
CHARGE-VOLTAGE REGULATION
2 cells, VVCTL = GND (MAX17006A) 8.366 8.433
3 cells, VVCTL = VAA (MAX17005A/MAX17006A) 12.549 12.651
4 cells, VVCTL = GND (MAX17005A) 16.73 16.86
Battery Regulation-Voltage Accuracy
FB accuracy using FB divider (MAX17015A)
(Note 1) 2.091 2.108
V
2 cells (MAX17006A),
4 cells (MAX17005A) 0.
VAA/2
- 0.2
VCTL Range
3 cells (MAX17005A/MAX17006A) VAA/2
+ 0.2 V
AA
V
VCTL Gain VCELL/VVCTL 5.85 6.15 V/V
MAX17005A/MAX17006A/MAX17015A
1.2MHz, Low-Cost,
High-Performance Chargers
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VDCIN = VCSSP = VCSSN = 19V, VBATT = VCSIP = VCSIN = 16.8V, VVCTL = VAA, VISET = 1V, TA= -40°C to +85°C,
unless otherwise noted.)
PARAMETER CONDITIONS MIN TYP MAX UNITS
CHARGE-CURRENT REGULATION
ISET Range 0 VAA/2 V
57.5 62.5 mV
VISET = VAA/4 or
ISET = 99.9% duty cycle -4.2 +4.2 %
38 42 mV
Full Charge-Current Accuracy
(CSIP to CSIN) VISET = VAA/6 or
ISET = 66.7% duty cycle -5 +5 %
1.4 4.6 mV
Trickle Charge-Current Accuracy
VBATT = 1V to 16.8V
VISET = VAA/80 or
ISET = 5% duty cycle -52 +52 %
Charge-Current Gain Error Based on VISET = VVAA/4 and VISET = VVAA/80 -2 +2 %
Charge-Current Offset Error Based on VISET = VVAA/4 and VISET = VVAA/80 -1.4 +1.4 mV
BATT/CSIP/CSIN Input-Voltage Range 0 24 V
ISET falling 21 31
ISET Power-Down Mode Threshold ISET rising 33 47 mV
Rising 2.4
ISET PWM Threshold Falling 0.8
V
ISET Frequency 0.128 500 kHz
INPUT-CURRENT REGULATION
58.2 61.8 mV
Input Current-Limit Threshold VCSSP - VCSSN -3 +3 %
CSSN Input Bias Current Adapter present -2 +2 μA
CSSP/CSSN Input-Voltage Range 8.0 26.0 V
IINP Transconductance VCSSP - VCSSN = 60mV 2.66 2.94 μA/mV
VCSSP - VCSSN = 60mV, VIINP = 0 to 4.5V -2.5 +2.5
IINP Accuracy VCSSP - VCSSN = 35mV -2.5 +2.5 %
SUPPLY AND LINEAR REGULATOR
DCIN Input-Voltage Range 8 26 V
DCIN falling 7.9
DCIN UVLO Trip-Point DCIN rising 8.9 V
Adapter present (Note 2) 6 mA
DCIN + CSSP + CSSN Quiescent Current Adapter absent (Note 2) 50 μA
Adapter absent (Note 2) 20
VBATT = 16.8V Charger shutdown (Note 2) 20
BATT + CSIP + CSIN + LX Input Current
VBATT = 2V to 19V, adapter present (Note 2) 500
μA
LDO Output Voltage 8.0V < VDCIN < 26V, no load 5.15 5.55 V
LDO Load Regulation 0 < ILDO < 40mA 200 mV
LDO UVLO Threshold 3.2 5.0 V
MAX17005A/MAX17006A/MAX17015A
1.2MHz, Low-Cost,
High-Performance Chargers
6 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VDCIN = VCSSP = VCSSN = 19V, VBATT = VCSIP = VCSIN = 16.8V, VVCTL = VAA, VISET = 1V, TA= -40°C to +85°C,
unless otherwise noted.)
PARAMETER CONDITIONS MIN TYP MAX UNITS
REFERENCES
VAA Output Voltage IVAA = 50μA 4.18 4.22 V
VAA UVLO Threshold VAA falling 3.9 V
ACIN
ACIN Threshold 2.058 2.142 V
ACIN Threshold Hysteresis 10 30 mV
ACOK
ACOK Sink Current V
ACOK = 0.4V, VACIN = 1.5V 6 mA
SWITCHING REGULATOR
DHI Off-Time K Factor VDCIN = 19V, VBATT = 10V 0.029 0.041 μs/V
Cycle-by-Cycle Current-Limit Sense Voltage VCSIP - VCSIN 105 115 mV
DHI Resistance High IDLO = 10mA 3
DHI Resistance Low IDLO = -10mA 1.75
DLO Resistance High IDLO = 10mA 6
DLO Resistance Low IDLO = -10mA 7
ADAPTER DETECTION
Adapter Absence-Detect Threshold VDCIN - VBATT, VDCIN falling +70 +170 mV
Adapter Detect Threshold VDCIN - VBATT, VDCIN rising +320 +620 mV
Adapter Switch Charge-Pump Frequency 180 220 Hz
DLO 0.04 0.2
Adapter Switch Charge-Pump Refresh Pulse DHI 0.07 0.3 μs
Note 1: Accuracy does not include errors due to external resistance tolerances.
Note 2: Adapter present conditions are tested at VDCIN = 19V and VBATT = 16.8V. Adapter absent conditions are tested at
VDCIN = 16V, VBATT = 16.8V.
MAX17005A/MAX17006A/MAX17015A
1.2MHz, Low-Cost,
High-Performance Chargers
_______________________________________________________________________________________ 7
Typical Operating Characteristics
(Circuit of Figure 1, adapter = 19V, battery = 10V, ISET = 1.05V, VCTL = GND, TA= +25°C, unless otherwise noted.)
IINP DC ERROR
vs. SYSTEM CURRENT
MAX17005A toc01
SYSTEM CURRENT (A)
IINP ERROR (%)
4312
-8
-6
-4
-2
0
2
4
6
8
10
-10
05
IINP ERROR
vs. SYSTEM CURRENT
MAX17005A toc02
SYSTEM CURRENT (A)
IINP ERROR (%)
4.03.52.5 3.01.0 1.5 2.00.5
-8
-6
-4
-2
0
2
4
6
8
10
-10
04.5
VBATT = 16.8V
VBATT = 8.4V
VBATT = 12.6V
ISET PWM DUTY-CYCLE CHANGE
MAX17005A toc03
DUTY CYCLE
CHARGE-CURRENT ERROR (%)
0.8 0.90.1 0.2 0.3 0.4 0.5 0.6 0.7
0.5
1.0
1.5
2.0
2.5
3.0
0
01.0
ISET PWM DUTY-CYCLE CHANGE
MAX17005A toc04
DUTY CYCLE
CHARGE CURRENT (A)
80 9010 20 30 40 50 60 70
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
0100
ISET PWM FREQUENCY SWEEP
MAX17005A toc05
FREQUENCY (kHz)
CHARGE-CURRENT ERROR (%)
600 700100 200 300 400 500
0.5
1.0
1.5
2.0
2.5
3.0
0
0 800
DUTY CYCLE = 75%
DUTY CYCLE = 25%
BATTERY VOLTAGE-SETTING ERROR
MAX17005A toc06
VCTL (V)
BATTERY VOLTAGE ERROR (%)
3.0 3.5 4.00.5 1.0 1.5 2.0 2.5
-0.5
-0.4
-0.3
-0.2
-0.1
0
-0.6
04.5
SYSTEM LOAD TRANSIENT
MAX17005A toc07
200μs/div
SYSTEM
CURRENT
5A/div
CHARGING
CURRENT
5A/div
INDUCTOR
CURRENT
5A/div
EFFICIENCY
vs. CHARGE CURRENT
MAX17005A toc08
CHARGE CURRENT (A)
EFFICIENCY (%)
2.5 3.0 3.50.5 1.0 1.5 2.0
70
65
75
80
85
95
90
100
60
04.0
2 CELLS
3 CELLS
4 CELLS
VAA LOAD REGULATION
MAX17005A toc11
LOAD CURRENT (mA)
VAA VOLTAGE (V)
0.80.2 0.4 0.6
4.197
4.196
4.198
4.200
4.199
4.201
4.203
4.202
4.205
4.204
4.195
01.0
MAX17005A/MAX17006A/MAX17015A
1.2MHz, Low-Cost,
High-Performance Chargers
8 _______________________________________________________________________________________
LDO LOAD REGULATION
MAX17005A toc09
LDO CURRENT (mA)
LDO VOLTAGE (V)
3551015202530
5.35
5.40
5.45
5.50
5.30
040
LDO LINE REGULATION
MAX17005A toc10
INPUT VOLTAGE (V)
LDO VOLTAGE (V)
242210 12 14 16 18 20
5.35
5.40
5.45
5.50
5.30
826
VAA vs. TEMPERATURE
MAX17005A toc12
TEMPERATURE (°C)
VAA (V)
60 80-40 -20 0 20 40
4.1970
4.1980
4.1975
4.1985
4.1995
4.1990
4.2005
4.2000
4.1965
-60 100
HIGH-SIDE MOSFET OFF-TIME AND
SWITCHING FREQUENCY vs. BATTERY VOLTAGE
MAX17005A toc13
BATTERY VOLTAGE (V)
SWITCHING FREQUENCY (MHz)
HIGH-SIDE MOSFTE OFF-TIME (μs)
161410 124682
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6 6
5
4
3
2
1
0
0
018
VIN = 20V
HIGH-SIDE MOSFET OFF-TIME
SWITCHING FREQUENCY
ADAPTER REMOVAL
MAX17005A toc16
200ms/div
5.00V
5.00V
5.00V
ADAPTER CURRENT
vs. ADAPTER VOLTAGE
MAX17005A toc14
ADAPTER VOLTAGE (V)
ADAPTER CURRENT (mA)
15510
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0
020
Typical Operating Characteristics (continued)
(Circuit of Figure 1, adapter = 19V, battery = 10V, ISET = 1.05V, VCTL = GND, TA= +25°C, unless otherwise noted.)
MAX17005A/MAX17006A/MAX17015A
1.2MHz, Low-Cost,
High-Performance Chargers
_______________________________________________________________________________________ 9
Pin Description
PIN NAME FUNCTION
1 DCIN Charger Bias Supply Input. Bypass DCIN with a 1μF capacitor to PGND.
2 AGND Analog Ground
3 CSIP Output Current-Sense Positive Input. Connect a current-sense resistor from CSIP to CSIN.
4 CSIN Output Current-Sense Negative Input
5 IINP
Input Current-Monitor Output. IINP sources the current proportional to the current sensed across
CSSP and CSSN. The transconductance from (CSSP - CSSN) to IINP is 2.8μA/mV. See the Analog
Input Current-Monitor Output section to configure the current monitor for a particular gain setting.
6 BATT Battery Voltage Feedback Input
7ACOK AC Detect Output. This open-drain output is high impedance when ACIN is lower than VAA/2.
Connect a 10k pullup resistor from LDO to ACOK.
8 CSSP Input Current Sense for Positive Input. Connect a current-sense resistor from CSSP to CSSN.
9 CSSN Input Current-Sense Negative Input
10 ISET
Dual Mode™ Input for Setting Maximum Charge Current. ISET can be configured either with a
resistor voltage-divider or with a PWM signal from 128Hz to 500kHz. If there is no clock edge
within 20ms, ISET defaults to analog input mode. Pull ISET to GND to shut down the charger. In the
MAX17015A, when the adapter is absent, drive ISET above 1V to enable IINP during battery
discharge. When the adapter is reinserted, ISET must be released to the correct control level within
300ms.
11 PGND Power Ground Connection for MOSFET Drivers
12 DLO Low-Side Power-MOSFET Driver Output. Connect to low-side n-channel MOSFET gate.
13 LDO
Linear Regulator Output. LDO provides the power to the MOSFET drivers. LDO is the output of the 5.4V
linear regulator supplied from DCIN. Bypass LDO with a 4.7μF ceramic capacitor from LDO to PGND.
14 BST High-Side Driver Supply. Connect a 0.68μF capacitor from BST to LX.
15 DHI High-Side Power-MOSFET Driver Output. Connect to high-side n-channel MOSFET gate.
16 LX High-Side Driver Source Connection. Connect a 0.68μF capacitor from BST to LX.
17 ACIN AC Adapter Detect Input. ACIN is the input to an uncommitted comparator.
18 VAA 4.2V Voltage Reference and Device Power-Supply Input. Bypass VAA with a 1μF capacitor to GND.
19 CC
Voltage Regulation Loop-Compensation Point. Connect 3k and 0.01μF capacitor in series from
CC to GND.
20 VCTL
Battery Voltage Adjust Input. VCTL sets the number of cells and adjusts the voltage per cell. The
adjustment range is 4.2V to 4.4V per cell. See the Setting Charge Voltage section.
— BP Backside Paddle. Connect the backside paddle to analog ground.
Dual Mode is a trademark of Maxim Integrated Products, Inc.
MAX17005A/MAX17006A/MAX17015A
1.2MHz, Low-Cost,
High-Performance Chargers
10 ______________________________________________________________________________________
BATT
ADAPTER
BST
CSSP CSSN
DHI
LX
DLO
PGND
RS1
15mΩ
CSIN
CSIP
BATT
BATTERY
CC
VCTL
ISET
LDO
AGND
IINP
VAA
ADAPTER
PWM SIGNAL
R1
22.6kΩ
C4
0.68μF
C2
0.1μF
C5
0.01μF
R2
R3
R4
200kΩ
R5
3kΩ
R6
200kΩ
CIN
COUT
RS2
10mΩ
N1
N2
N3
N4
Q1b
C3
1μF
C1
4.7μF
R7
R8
ONLY FOR MAX17015A
L1
SYSTEM LOAD
D1
C6
1μF
CIN = 2 x 4.7μF
COUT = 4.7μF
L1 = 2μH
R9
2MΩ
Q1a
DCIN
C7
0.1μF
RACIN1
RACIN2
ACIN
ACOK
LDO 10kΩ
MAX17005A
MAX17006A
MAX17015A
Figure 1. Typical Operating Circuit
Detailed Description
The MAX17005A/MAX17006A/MAX17015A include all
the functions necessary to charge Li+, NiMH, and NiCd
batteries. An all n-channel synchronous-rectified step-
down DC-DC converter is used to implement a preci-
sion constant-current, constant-voltage charger. The
charge current and input current-limit sense amplifiers
have low-input offset errors (250μV typ), allowing the
use of small-valued sense resistors.
The MAX17005A/MAX17006A/MAX17015A use a new
thermally optimized high-frequency architecture. With this
new architecture, the switching frequency is adjusted to
control the power dissipation in the high-side
MOSFET. Benefits of the new architecture include:
reduced output capacitance and inductance, resulting in
smaller printed-circuit board (PCB) area and lower cost.
MAX17005A/MAX17006A/MAX17015A
1.2MHz, Low-Cost,
High-Performance Chargers
______________________________________________________________________________________ 11
CSA
A = 17.5V/V
CSSN
CSSP
Gm =
2.8μA/mV
IINP
GMS
CSIN
CSIP
GMI
ISET
26mV
CHARGER
SHUTDOWN
CELL
SELECT
LOGIC
BATT
VAA
VCTL
GMV
CC
LOWEST
VOLTAGE
CLAMP
CSI
60mV
PWM
FILTER
DHI
DLO
PGND
LX
BST
LEVEL
SHIFT HIGH-SIDE
DRIVER
LOW-SIDE
DRIVER
CCMP
IMIN
IMAX
IZX
10mV
OVP
DC-DC
CONVERTER
110mV
10mV
BDIV
BDIV
VCTL + 100mV
5.4V LINEAR
REGULATOR
4.2V
REFERENCE
DCIN
LDO
VAA
POWER
FAIL
LDO
AGND
BATT
VAA/2
ACOK
LDO
ACIN
MAX17005A
MAX17006A
MAX17015A
CSA
A = 17.5V/V
Figure 2. Functional Diagram
The MAX17005A/MAX17006A/MAX17015A feature a
voltage-regulation loop (CCV) and two current-regula-
tion loops (CCI and CCS). The loops operate indepen-
dently of each other. The CCV voltage-regulation loop
monitors BATT to ensure that its voltage never exceeds
the voltage set by VCTL. The CCI battery charge cur-
rent-regulation loop monitors current delivered to BATT
to ensure that it never exceeds the current limit set by
ISET. The charge current-regulation loop is in control as
long as the battery voltage is below the set point. When
the battery voltage reaches its set point, the voltage-
regulation loop takes control and maintains the battery
voltage at the set point. A third loop (CCS) takes control
and reduces the charge current when the adapter cur-
rent exceeds the input current limit.
The MAX17005A/MAX17006A/MAX17015A have single-
point compensation. The two current loops are internal-
ly compensated while the voltage loop is compensated
with a series RC network at CC pin. See the
CC Loop
Compensation
section for the resistor and capacitor
selection. A functional diagram is shown in Figure 2.
MAX17005A/MAX17006A/MAX17015A
1.2MHz, Low-Cost,
High-Performance Chargers
12 ______________________________________________________________________________________
Setting Charge Voltage
The VCTL input adjusts the battery-output voltage,
VBATT, and determines the number of cells. For 3- and
4-cell applications, use the MAX17005A; for 2- and
3-cell applications, use the MAX17006A. Use the
MAX17015A to adjust the cell number and set the cell
voltage with a resistive voltage-divider from the output.
Based on the version of the part, the number of cells
and the level of VCTL should be set as in Table 1:
The MAX17005A/MAX17006A support from 4.2V/cell to
4.4V/cell, whereas the MAX17015A supports minimum
2.1V. The maximum voltage is determined with the
dropout performance of IC. When the required voltage
falls outside the range available with the MAX17005A or
MAX17006A, the MAX17015A should be used.
The charge-voltage regulation for the MAX17005A and
MAX17006A is calculated with the following equations:
for 3-cell selection of MAX17005A and MAX17006A,
4.2V > VCTL > 2.4V:
for 2- or 4-cell selection of MAX17006A or MAX17005A,
respectively, 0 < VCTL < 1.8V. Connect VCTL to GND
or to VAA for default 4.2V/cell battery-voltage setting.
For the MAX17015A, connect VCTL to GND to set the FB
regulation point to 2.1V. The charge-voltage regulation is
calculated with the following equation:
There are two constraints in choosing R7 and R8. The
resistors cannot be too small since they discharge the
battery, and they cannot be too large because FB pin
consumes less than 1μA of input bias current. Pick R8
to be approximately 10kΩand then calculate R7.
FB regulation error (±0.5% max) and the tolerance of R7
and R8 both contribute to the error on the battery volt-
age. Use 0.1% feedback resistors for best accuracy.
Setting Charge Current
The voltage at ISET determines the voltage across cur-
rent-sense resistor RS2. ISET can accept either analog
or digital inputs. The full-scale differential voltage
between CSIP and CSIN is 80mV (8A for RS2 = 10mΩ)
for the analog input, and 60mV (6A for RS2 = 10mΩ) for
the digital PWM input.
When the MAX17005A/MAX17006A/MAX17015A power
up and the charger is ready, if there is no clock edge
within 20ms, the circuit assumes ISET is an analog
input, and disables the PWM filter block. To configure
the charge current, force the voltage on ISET according
to the following equation:
The input range for ISET is from 0 to VAA/2. To shut
down the charger, pull ISET below 26mV.
If there is a clock edge on ISET within 20ms, the PWM
filter is enabled and ISET accepts digital PWM input.
The PWM filter has a DAC with 8-bit resolution that cor-
responds to equivalent VCSIP-CSIN steps.
ImV
RS
V
V
CHG ISET
AA
=×
240
2
VV RR
R
CHG REG FB SETPOINT__
=×
+87
8
VV
V
CELL VCTL
=+42 6
.
VV
VV
CELL VCTL
=+42 42
6
..-
VERSION NO. OF CELLS LEVEL
MAX17005A 3 2.4V < VCTL < 4.2V
MAX17005A 4 0 < VCTL < 1.8V
MAX17006A 2 0 < VCTL < 1.8V
MAX17006A 3 2.4V < VCTL < 4.2V
MAX17015A Sets FB VCTL = GND or VCTL = VAA
Table 1. Cell Configuration
CSIN
FB
BATTERY
COUT
R7
R8
MAX17015A
Figure 3. The MAX17015A Charge-Voltage Regulation Feedback
Network
MAX17005A/MAX17006A/MAX17015A
1.2MHz, Low-Cost,
High-Performance Chargers
______________________________________________________________________________________ 13
The PWM filter accepts the digital signal with a frequency
from 128Hz to 500kHz. Zero duty cycle shuts down the
MAX17005A/MAX17006A/MAX17015A, and 99.5% duty
cycle corresponds to full scale (60mV) across CSIP
and CSIN.
Choose a current-sense resistor (RS2) to have a suffi-
cient power-dissipation rating to handle the full-charge
current. The current-sense voltage can be reduced to
minimize the power-dissipation period. However, this can
degrade accuracy due to the current-sense amplifier’s
input offset (0.25mV typ). See
Typical Operating
Characteristics
to estimate the charge-current accuracy
at various set points.
Setting Input-Current Limit
The total input current, from a wall adapter or other DC
source, is the sum of the system supply current and the
current required by the charger. When the input current
exceeds the set input-current limit, the controller
decreases the charge current to provide priority to sys-
tem load current. System current normally fluctuates as
portions of the system are powered up or down. The
input-current-limit circuit reduces the power require-
ment of the AC wall adapter, which reduces adapter
cost. As the system supply rises, the available charge
current drops linearly to zero. Thereafter, the total input
current can increase without limit.
The total input current is the sum of the device supply cur-
rent, the charger input current, and the system load cur-
rent. The total input current can be estimated as follows:
where ηis the efficiency of the DC-to-DC converter
(typically 85% to 95%).
In the MAX17005A/MAX17006A/MAX17015A, the volt-
age across CSSP and CSSN is constant at 60mV.
Choose the current-sense resistor, RS1, to set the input
current limit. For example, for 4A input current limit,
choose RS1 = 15mΩ. For the input current-limit set-
tings, which cannot be achievable with standard sense
resistor values, use a resistive voltage-divider between
CSSP and CSSN to tune the setting (Figure 4).
To minimize power dissipation, first choose RS1
according to the closest available value. For conve-
nience, choose Ra = 6kΩand calculate Rb from the
above equation.
Choose a current-sense resistor (RS1) to have a suffi-
cient power rating to handle the full system current. The
current-sense resistor can be reduced to improve effi-
ciency, but this degrades accuracy due to the current-
sense amplifier’s input offset (0.15mV typ). See
Typical
Operating Characteristics
to estimate the input current-
limit accuracy at various set points.
Automatic Power-Source Selection
The MAX17005A/MAX17006A/MAX17015A use an
external charge pump to drive the gate of an n-channel
adapter selection switch (N3 and Q1a). In Figure 1,
when the adapter is present, BST is biased 5V above
VADAPTER so that N3 and Q1a are on, and Q1b is off.
As long as the adapter is present, even though the
charger is off, the power stage forces a refresh pulse
to the BST charge pump every 5ms.
When the adapter voltage is removed, the charger
stops generating BST refresh pulses and N4 forces N2
off, Q1b turns on and supplies power to the system
from the battery.
In Figure 1, D1 must have low forward-voltage drop and
low reverse-leakage current to ensure sufficient gate
drive at N3 and Q1a. A 100mA, low reverse-leakage
Schottky diode is the right choice.
Analog Input Current-Monitor Output
Use IINP to monitor the system-input current, which is
sensed across CSSP and CSSN. The voltage at IINP is
proportional to the input current:
where IINPUT is the DC current supplied by the AC
adapter, GIINP is the transconductance of the sense
amplifier (2.8mA/V typ), and RIINP is the resistor con-
nected between IINP and ground. Typically, IINP has a
0 to 3.5V output-voltage range. Leave IINP unconnected
when not used.
IV
RS G R
INPUT IINP
IINP IINP
=××1
ImV
RS
Rb
Ra
INPUT LIMIT_()=×+
60
11
IIIV
V
INPUT LOAD CHARGE BATTERY
IN
=+ ×
×η
CSSP CSSN
RS1
Ra
Rb
MAX17005A/MAX17006A/MAX17015A
Figure 4. Input Current-Limit Fine-Tuning
MAX17005A/MAX17006A/MAX17015A
1.2MHz, Low-Cost,
High-Performance Chargers
14 ______________________________________________________________________________________
IINP can also be used to monitor battery discharge cur-
rent (see Figure 5). In the MAX17015A, when the adapter
is absent, drive ISET above 1V to enable IINP during bat-
tery discharge. When the adapter is reinserted, ISET must
be released to the correct control level within 300ms.
AC Adapter Detection
The MAX17005A/MAX17006A/MAX17015A include a
hysteretic comparator that detects the presence of an
AC power adapter. When ACIN is lower than 2.1V, the
open-drain ACOK output becomes high impedance.
Connect a 10kΩpullup resistance between LDO and
ACOK. Use a resistive voltage-divider from the
adapter’s output to the ACIN pin to set the appropriate
detection threshold. Select the resistive voltage-divider
so that the voltage on ACIN does not to exceed its
absolute maximum rating (6V).
LDO Regulator and VAA
An integrated low-dropout (LDO) linear regulator pro-
vides a 5.4V supply derived from DCIN, and delivers
over 40mA of load current. Do not use the LDO to
external loads greater than 10mA. The LDO powers the
gate drivers of the n-channel MOSFETs. See the
MOSFET Drivers
section. Bypass LDO to PGND with a
4.7μF ceramic capacitor. VAA is 4.2V reference sup-
plied by DCIN. VAA biases most of the control circuitry,
and should be bypassed to GND with a 1μF or greater
ceramic capacitor.
Operating Conditions
The MAX17005A/MAX17006A/MAX17015A have the fol-
lowing operating states:
•Adapter Present: When DCIN is greater than 8.7V,
the controller detects the adapter. In this condition,
both the LDO and VAA turn on and battery charging
is allowed:
a) Charging: The total MAX17005A/MAX17006A/
MAX17015A quiescent current when charging is
3mA (max) plus the current required to drive the
MOSFETs.
b) Not Charging: To disable charging drive ISET
below 26mV. When the adapter is present and
charging is disabled, the total adapter quiescent
current is less than 1.5mA and the total battery
quiescent current is less than 60μA. The charge
pump still operates.
•Adapter Absent (Power Fail): When VDCIN is less
than VCSIN + 120mV, the DC-DC converter is in
dropout. The charger detects the dropout condition
and shuts down.
The MAX17005A/MAX17006A/MAX17015A allow
charging under the following conditions:
• DCIN > 7.5V, LDO > 4V, VAA > 3.1V
•V
DCIN > VCSIN + 420mV (300mV falling hysteresis)
•V
ISET > 45mV or PWM detected
____________________DC-DC Converter
The MAX17005A/MAX17006A/MAX17015A employ a
synchronous step-down DC-DC converter with an n-
channel high-side MOSFET switch and an n-channel
low-side synchronous rectifier. The charger features a
controlled inductor current-ripple architecture, current-
mode control scheme with cycle-by-cycle current limit.
The controller’s off-time (tOFF) is adjusted to keep the
high-side MOSFET junction temperature constant. In
this way, the controller switches faster when the high-
side MOSFET has available thermal capacity. This
allows the inductor current ripple and the output-volt-
age ripple to decrease so that smaller and cheaper
components can be used. The controller can also oper-
ate in discontinuous conduction mode for improved
light-load efficiency.
BST
CSSP CSSN
DHI
LX
RS1
15mΩ
BATTERY
ADAPTER
C4
0.1μF
R6
50kΩ
CIN
N1
Q1b
SYSTEM LOAD
D1
Q1a
C7
10nF
MAX17015A
Figure 5. Current-Monitoring Design Battery Discharge
MAX17005A/MAX17006A/MAX17015A
1.2MHz, Low-Cost,
High-Performance Chargers
______________________________________________________________________________________ 15
The operation of the DC-to-DC controller is determined
by the following five comparators as shown in the func-
tional diagram in Figures 2 and 6:
• The IMIN comparator triggers a pulse in discontinu-
ous mode when the accumulated error is too high.
IMIN compares the control signal (LVC) against
10mV (referred at VCSIP - VCSIN). When LVC is less
than this threshold, DHI and DLO are both forced
low. Indirectly, IMIN sets the peak inductor current
in discontinuous mode.
• The CCMP comparator is used for current-mode
regulation in continuous-conduction mode. CCMP
compares LVC against the inductor current. The
high-side MOSFET on-time is terminated when the
CSI voltage is higher than LVC.
• The IMAX comparator provides a secondary cycle-
by-cycle current limit. IMAX compares CSI to
110mV (corresponding to 11A when RS2 = 10mΩ).
The high-side MOSFET on-time is terminated when
the current-sense signal exceeds 11A. A new cycle
cannot start until the IMAX comparator’s output
goes low.
• The ZCMP comparator provides zero-crossing detec-
tion during discontinuous conduction. ZCMP com-
pares the current-sense feedback signal to 1A (RS2
= 10mΩ). When the inductor current is lower than
the 1A threshold, the comparator output is high,
and DLO is turned off.
• The OVP comparator is used to prevent overvoltage
at the output due to battery removal. OVP com-
pares BATT against the VCTL. When BATT is
100mV/cell above the set value, the OVP compara-
tor output goes high, and the high-side MOSFET
on-time is terminated. DHI and DLO remain off until
the OVP condition is removed.
R
Q
Q
S
OFF-TIME
ONE SHOT
11A
1A
1A
CSI
LVC
OFF-TIME
COMPUTE
CSSP
BDIV
SET POINT + 100mV
CSIN
DL DRIVER
DH DRIVER
OVP
IMAX
CCMP
IMIN
ZCMP
Figure 6. DC-DC Converter Functional Diagram
MAX17005A/MAX17006A/MAX17015A
1.2MHz, Low-Cost,
High-Performance Chargers
16 ______________________________________________________________________________________
CC, CCI, CCS, and LVC Control Blocks
The MAX17005A/MAX17006A/MAX17015A control
input current (CCS control loop), charge current (CCI
control loop), or charge voltage (CC control loop),
depending on the operating condition. The three con-
trol loops, CC, CCI, and CCS are brought together
internally at the lowest voltage clamp (LVC) amplifier.
The output of the LVC amplifier is the feedback control
signal for the DC-DC controller. The minimum voltage
at the CC, CCI, or CCS appears at the output of the
LVC amplifier and clamps the other control loops to
within 0.3V above the control point. Clamping the other
two control loops close to the lowest control loop
ensures fast transition with minimal overshoot when
switching between different control loops (see the
Compensation
section). The CCS and CCI loops are
compensated internally, and the CC loop is compen-
sated externally.
Continuous-Conduction Mode
With sufficiently large charge current, the MAX17005A/
MAX17006A/MAX17015s’ inductor current never cross-
es zero, which is defined as continuous-conduction
mode. The controller starts a new cycle by turning on
the high-side MOSFET and turning off the low-side
MOSFET. When the charge-current feedback signal
(CSI) is greater than the control point (LVC), the CCMP
comparator output goes high and the controller initiates
the off-time by turning off the high-side MOSFET and
turning on the low-side MOSFET. The operating fre-
quency is governed by the off-time and is dependent
upon VCSIN and VDCIN.
The on-time can be determined using the following
equation:
where:
The switching frequency can then be calculated:
At the end of the computed off-time, the controller initi-
ates a new cycle if the control point (LVC) is greater
than 10mV (VCSIP - VCSIN referred), and the charge
current is less than the cycle-by-cycle current limit.
Restated another way, IMIN must be high, IMAX must
be low, and OVP must be low for the controller to initi-
ate a new cycle. If the peak inductor current exceeds
IMAX comparator threshold or the output voltage
exceeds the OVP threshold, then the on-time is termi-
nated. The cycle-by-cycle current limit effectively pro-
tects against overcurrent and short-circuit faults.
If during the off-time the inductor current goes to zero,
the ZCMP comparator output pulls high, turning off the
low-side MOSFET. Both the high- and low-side
MOSFETs are turned off until another cycle is ready to
begin. ZCOMP causes the MAX17005A/MAX17006A/
MAX17015A to enter into the discontinuous conduction
mode (see the
Discontinuous Conduction
section).
Discontinuous Conduction
The MAX17005A/MAX17006A/MAX17015A can also
operate in discontinuous conduction mode to ensure that
the inductor current is always positive. The MAX17005A/
MAX17006A/MAX17015A enter discontinuous conduction
mode when the output of the LVC control point falls below
10mV (referred at VCSIP - VCSIN). For RS2 = 10mΩ, this
corresponds to a peak inductor current of 1A.
In discontinuous mode, a new cycle is not started until
the LVC voltage rises above IMIN. Discontinuous mode
operation can occur during conditioning charge of
overdischarged battery packs, when the charge cur-
rent has been reduced sufficiently by the CCS control
loop, or when the charger is in constant-voltage mode
with a nearly full battery pack.
Compensation
The charge voltage, charge current, and input current-
limit regulation loops are compensated separately. The
charge current and input current-limit loops, CCI and
CCS, are compensated internally, whereas the charge
voltage loop is compensated externally at CC.
ftt
SW ON OFF
=+
1
IVt
L
RIPPLE BATT OFF
=×
tLI
VV
ON RIPPLE
DCIN BATT
=×
-
MAX17005A/MAX17006A/MAX17015A
1.2MHz, Low-Cost,
High-Performance Chargers
______________________________________________________________________________________ 17
CC Loop Compensation
The simplified schematic in Figure 7 is sufficient to
describe the operation of the controller’s voltage loop,
CC. The required compensation network is a pole-zero
pair formed with CCC and RCC. The zero is necessary
to compensate the pole formed by the output capacitor
and the load. RESR is the equivalent series resistance
(ESR) of the charger output capacitor (COUT). RLis the
equivalent charger output load, where RL= ΔVBATT/
ΔICHG. The equivalent output impedance of the GMV
amplifier, ROGMV, is greater than 10MΩ. The voltage-
amplifier transconductance, GMV = 0.125μA/mV. The
DC-DC converter transconductance is dependent upon
charge current-sense resistor RS2:
where ACSI = 20, and RS2 = 10mΩin the typical appli-
cation circuits, so GMOUT = 5A/V.
The loop transfer function is given by:
The poles and zeros of the voltage-loop transfer function
are listed from lowest frequency to highest frequency in
Table 2.
Near crossover, CCC is much lower impedance than
ROGMV. Since CCC is in parallel with ROGMV, CCC domi-
nates the parallel impedance near crossover. Additionally,
RCC is much higher impedance than CCC and dominates
the series combination of RCC and CCC, so:
COUT is also much lower impedance than RLnear
crossover so the parallel impedance is mostly capaci-
tive and:
R
sC R sC
L
OUT L OUT
()1
1
+×
≅
RsCR
sC R R
OGMV CC CC
CC OGMV CC
×+ ×
+× ≅
()
()
1
1
LTF R GMV R
sC R
=×××
×+×
GMOUT L OGMV
OUT ESR
(1 ))( )
()()
1
11
+×
+× + ×
sC R
sC R sC R
CC CC
CC OGMV OUT L
GM =
OUT
1
2ARS
CSI ×
NAME EQUATION DESCRIPTION
CCV Pole Lowest frequency pole created by CCV and GMV’s finite output resistance.
CCV Zero
Voltage-loop compensation zero. If this zero is at the same frequency or lower
than output pole fP_OUT, the loop-transfer function approximates a single-pole
response near the crossover frequency. Choose CCV to place this zero at
least one decade below crossover to ensure adequate phase margin.
Output
Pole
Output pole formed with the effective load resistance RL and the output
capacitance COUT. RL influences the DC gain but does not affect the stability
of the system or the crossover frequency.
Output
Zero
Output ESR Zero. This zero can keep the loop from crossing unity gain if
fZ_OUT is less than the desired crossover frequency; therefore, choose a
capacitor with an ESR zero greater than the crossover frequency.
Table 2. CC Loop Poles and Zeros
fRC
PCV OGMV CC
_=×
1
2π
fRC
ZCV CC CC
_=×
1
2π
fRC
POUT LOUT
_=×
1
2π
fRC
ZOUT ESR OUT
_=×
1
2π
GMOUT
BATT
RESR
COUT
RL
VCTL
ROGMV
RCC
CCC
CC
GMV
Figure 7. CC Loop Diagram
MAX17005A/MAX17006A/MAX17015A
1.2MHz, Low-Cost,
High-Performance Chargers
18 ______________________________________________________________________________________
If RESR is small enough, its associated output zero has
a negligible effect near crossover and the loop-transfer-
function can be simplified as follows:
Setting LTF = 1 to solve for the unity-gain frequency
yields:
For stability, choose a crossover frequency lower than
1/10 the switching frequency (fOSC). For example,
choose a crossover frequency of 50kHz and solve for
RCC using the component values listed in Figure 1 to
yield RCC = 3kΩ:
GMV = 0.125μA/mV
GMOUT = 5A/V
COUT = 4.7μF
fOSC = 600kHz
RL = 0.2Ω
fCO_CV = 50kHz
To ensure that the compensation zero adequately can-
cels the output pole, select fZ_CV ≤fP_OUT:
CCC ≥(RL/RCC) x COUT
CCC ≥300pF (assuming 2 cells and 2A maximum
charge current).
Figure 8 shows the Bode plot of the voltage-loop-
frequency response using the values calculated above.
MOSFET Drivers
The DHI and DLO outputs are optimized for driving
moderate-sized power MOSFETs. The MOSFET drive
capability is the same for both the low-side and high-
sides switches. This is consistent with the variable duty
factor that occurs in the notebook computer environ-
ment where the battery voltage changes over a wide
range. There must be a low-resistance, low-inductance
path from the DLO driver to the MOSFET gate to pre-
vent shoot-through. Otherwise, the sense circuitry in the
MAX17005A/MAX17006A interpret the MOSFET gate as
“off” while there is still charge left on the gate. Use very
short, wide traces measuring 10 to 20 squares or fewer
(1.25mm to 2.5mm wide if the MOSFET is 25mm from
the device). Unlike the DLO output, the DHI output uses
a 50ns (typ) delay time to prevent the low-side MOSFET
from turning on until DHI is fully off. The same consider-
ations should be used for routing the DHI signal to the
high-side MOSFET.
The high-side driver (DHI) swings from LX to 5V above
LX (BST) and has a typical impedance of 1.5Ωsourcing
and 0.8Ωsinking. The strong high-side MOSFET driver
eliminates most of the power dissipation due to switch-
ing losses. The low-side driver (DLO) swings from LDO
to ground and has a typical impedance of 3Ωsinking
and 3Ωsourcing. This helps prevent DLO from being
pulled up when the high-side switch turns on due to
capacitive coupling from the drain to the gate of the
low-side MOSFET. This places some restrictions on the
MOSFETs that can be used. Using a low-side
MOSFET with smaller gate-to-drain capacitance can
prevent these problems.
Design Procedure
MOSFET Selection
Choose the n-channel MOSFETs according to the maxi-
mum required charge current. The MOSFETs must be
able to dissipate the resistive losses plus the switching
losses at both VDCIN(MIN) and VDCIN(MAX).
For the high-side MOSFET, the worst-case resistive
power losses occur at the maximum battery voltage
and minimum supply voltage:
PD High Side V
VI
COND
BATT MAX
DCIN MIN CHG
()()
()
=×
2×× RDS ON()
RCf
GMV GM k
CC OUT CO CV
OUT
=×
×≅
×23
π_Ω
fGMG
R
C
CO CV OUT MV CC
OUT
_=××
×2π
LTF GM R
sC G
OUT CC
OUT MV
=×
FREQUENCY (Hz)
MAGNITUDE (dB)
PHASE (DEGREES)
100k10k1k100101
-20
0
20
40
60
80
-40
-90
-45
0
-135
0.1 1M
MAG
PHASE
Figure 8. CC Loop Response
MAX17005A/MAX17006A/MAX17015A
1.2MHz, Low-Cost,
High-Performance Chargers
______________________________________________________________________________________ 19
Generally, a low gate charge high-side MOSFET is pre-
ferred to minimize switching losses. However, the
RDS(ON) required to stay within package power dissi-
pation often limits how small the MOSFET can be. The
optimum occurs when the switching losses equal the
conduction losses. High-side switching losses do not
usually become an issue until the input is greater than
approximately 15V. Calculating the power dissipation in
N1 due to switching losses is difficult since it must
allow for difficult quantifying factors that influence the
turn-on and turn-off times. These factors include the
internal gate resistance, gate charge, threshold volt-
age, source inductance, and PCB layout characteris-
tics. The following switching-loss calculation provides
only a very rough estimate and is no substitute for
breadboard evaluation, preferably including a verifica-
tion using a thermocouple mounted on N1:
where tTRANS is the drivers transition time and can be
calculated as follows:
IGSRC and IGSNK are the peak gate-drive source/sink
current (3Ωsourcing and 0.8Ωsinking, typically). The
MAX17005A/MAX17006A/MAX17015A control the
switching frequency as shown in the
Typical Operating
Characteristics
.
The following is the power dissipated due to high-side
n-channel MOSFET’s output capacitance (CRSS):
The following high-side MOSFET’s loss is due to the
reverse-recovery charge of the low-side MOSFET’s
body diode:
Ignore PDQRR(HS) if a Schottky diode is used parallel
to a low-side MOSFET.
The total high-side MOSFET power dissipation is:
Switching losses in the high-side MOSFET can become
an insidious heat problem when maximum AC adapter
voltages are applied. If the high-side MOSFET chosen
for adequate RDS(ON) at low-battery voltages becomes
hot when biased from VDCIN(MAX), consider choosing
another MOSFET with lower parasitic capacitance.
For the low-side MOSFET (N2), the worst-case power
dissipation always occurs at maximum input voltage:
The following additional loss occurs in the low-side
MOSFET due to the body diode conduction losses:
The total power low-side MOSFET dissipation is:
These calculations provide an estimate and are not a
substitute for breadboard evaluation, preferably
including a verification using a thermocouple mounted
on the MOSFET.
Inductor Selection
The selection of the inductor has multiple trade-offs
between efficiency, transient response, size, and cost.
Small inductance is cheap and small, and has a better
transient response due to higher slew rate; however, the
efficiency is lower because of higher RMS current. High
inductance results in lower ripple so that the need of the
output capacitors for output-voltage ripple goes low.
The MAX17005A/MAX17006A/MAX17015A combine all
the inductor trade-offs in an optimum way by controlling
switching frequency. High-frequency operation permits
the use of a smaller and cheaper inductor, and conse-
quently results in smaller output ripple and better tran-
sient response.
The charge current, ripple, and operating frequency
(off-time) determine the inductor characteristics. For
optimum efficiency, choose the inductance according
to the following equation:
where k = 35ns/V.
LkV
ILIR
IN
CHG MAX
=×
××
2
4
PD LS PD LS PD LS
TOTAL COND BDY
() () ()≈+
PD LS I V
BDY PEAK
() . .=× ×005 04
PD LS V
VI
COND BATT MIN
CSSP MAX CH
() ()
()
=⎛
⎝
⎜⎞
⎠
⎟×1- GGDSON
R
2×()
PD HS PD HS PD HS
TOTAL COND SW
() () ()≈+
() ()++PD HS PD HS
CRSS QRR
PD HS QV f
QRR RR CSSP SW
()=××
2
2
PD HS VCf
CRSS CSSP RSS SW
()≈××
2
2
tII QQ
TRANS GSRC GSNK GD GS
=+
⎛
⎝
⎜⎞
⎠
⎟×+
()
11
PD HS t V I f
SW TRANS CSSP CHG SW
()=× × × ×
1
2
MAX17005A/MAX17006A/MAX17015A
1.2MHz, Low-Cost,
High-Performance Chargers
20 ______________________________________________________________________________________
For optimum size and inductor current ripple, choose
LIRMAX = 0.4, which sets the ripple current to 40% the
charge current and results in a good balance between
inductor size and efficiency. Higher inductor values
decrease the ripple current. Smaller inductor values
save cost but require higher saturation current capabili-
ties and degrade efficiency.
Inductor L1 must have a saturation current rating of at
least the maximum charge current plus 1/2 the ripple
current (ΔIL):
ISAT = ICHG + (1/2) ΔIL
The ripple current is determined by:
Input Capacitor Selection
The input capacitor must meet the ripple current
requirement (IRMS) imposed by the switching currents.
Nontantalum chemistries (ceramic, aluminum, or
OS-CON) are preferred due to their resilience to power-
up and surge currents:
The input capacitors should be sized so that the tem-
perature rise due to ripple current in continuous con-
duction does not exceed approximately 10°C. The
maximum ripple current occurs at 50% duty factor or
VDCIN = 2 x VBATT, which equates to 0.5 x ICHG. If the
application of interest does not achieve the maximum
value, size the input capacitors according to the worst-
case conditions.
Output Capacitor Selection
The output capacitor absorbs the inductor ripple cur-
rent and must tolerate the surge current delivered from
the battery when it is initially plugged into the charger.
As such, both capacitance and ESR are important
parameters in specifying the output capacitor as a filter
and to ensure the stability of the DC-to-DC converter
(see the
Compensation
section.) Beyond the stability
requirements, it is often sufficient to make sure that the
output capacitor’s ESR is much lower than the battery’s
ESR. Either tantalum or ceramic capacitors can be
used on the output. Ceramic devices are preferable
because of their good voltage ratings and resilience to
surge currents. Choose the output capacitor based on:
Choose kCAP-BIAS is a derating factor of 2 for typical 25V-
rated ceramic capacitors.
For fSW = 800kHz, IRIPPLE = 1A, and to get ΔVBATT =
70mV, choose COUT as 4.7μF.
If the internal resistance of battery is close to the ESR of
the output capacitor, the voltage ripple is shared with
the battery and is less than calculated.
Applications Information
Setting Input Current Limit
The input current limit should be set based on the cur-
rent capability of the AC adapter and the tolerance of
the input current limit. The upper limit of the input cur-
rent threshold should never exceed the adapter’s mini-
mum available output current. For example, if the
adapter’s output current rating is 5A ±10%, the input
current limit should be selected so that its upper limit is
less than 5A ×0.9 = 4.5A. Since the input current-limit
accuracy of the MAX17005A/MAX17006A/MAX17015A
is ±3%, the typical value of the input current limit should
be set at 4.5A/1.03 ≈4.36A. The lower limit for input cur-
rent must also be considered. For chargers at the low
end of the specification, the input current limit for this
example could be 4.36A ×0.95 or approximately 4.14A.
Layout and Bypassing
Bypass DCIN with a 0.1μF ceramic capacitor to ground
(Figure 1). N1 and N2 protect the MAX17005A/
MAX17006A/MAX17015A when the DC power source
input is reversed. Bypass VAA, CSSP, and LDO as shown
in Figure 1.
Good PCB layout is required to achieve specified noise
immunity, efficiency, and stable performance. The PCB
layout designer must be given explicit instructions—
preferably, a sketch showing the placement of the
power switching components and high current routing.
Refer to the PCB layout in the MAX17005A/MAX17006A/
MAX17015A evaluation kit for examples. A ground
plane is essential for optimum performance. In most
applications, the circuit is located on a multilayer
board, and full use of the four or more copper layers is
recommended. Use the top layer for high-current con-
nections, the bottom layer for quiet connections, and
the inner layers for an uninterrupted ground plane.
Use the following step-by-step guide:
1) Place the high-power connections first, with their
grounds adjacent:
a) Minimize the current-sense resistor trace lengths,
and ensure accurate current sensing with Kelvin
connections.
CI
fV
k
OUT RIPPLE
SW BATT CAP BIAS
=×× ×−
8Δ
II VVV
V
RMS CHG BATT DCIN BATT
DCIN
=×
()
⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟
×-
Δ=×
IkV
L
LIN2
4
MAX17005A/MAX17006A/MAX17015A
1.2MHz, Low-Cost,
High-Performance Chargers
______________________________________________________________________________________ 21
b) Minimize ground trace lengths in the high-current
paths.
c) Minimize other trace lengths in the high-current
paths.
d) Use > 5mm wide traces in the high-current
paths.
e) Connect CIN to high-side MOSFET (10mm max
length).
f) Minimize the LX node (MOSFETs, rectifier cath-
ode, inductor (15mm max length)). Keep LX on
one side of the PCB to reduce EMI radiation.
Ideally, surface-mount power components are flush
against one another with their ground terminals
almost touching. These high-current grounds are
then connected to each other with a wide, filled
zone of top-layer copper, so they do not go through
vias. The resulting top-layer subground plane is
connected to the normal inner-layer ground plane
at the paddle. Other high-current paths should also
be minimized, but focusing primarily on short
ground and current-sense connections eliminates
about 90% of all PCB layout problems.
2) Place the IC and signal components. Keep the
main switching node (LX node) away from sensitive
analog components (current-sense traces and VAA
capacitor). Important: the IC must be no further than
10mm from the current-sense resistors. Quiet con-
nections to VAA and CC should be returned to a sep-
arate ground (GND) island. There is very little current
flowing in these traces, so the ground island need not
be very large. When placed on an inner layer, a siz-
able ground island can help simplify the layout
because the low-current connections can be made
through vias. The ground pad on the backside of the
package should also be connected to this quiet
ground island.
3) Keep the gate drive traces (DHI and DLO) as short
as possible (L < 20mm), and route them away from
the current-sense lines and VAA. These traces
should also be relatively wide (W > 1.25mm).
4) Place ceramic bypass capacitors close to the IC.
The bulk capacitors can be placed further away.
Place the current-sense input filter capacitors under
the part, connected directly to the GND pin.
5) Use a single-point star ground placed directly
below the part at the PGND pin. Connect the power
ground (ground plane) and the quiet ground island
at this location.
MAX17005A/MAX17006A/MAX17015A
1.2MHz, Low-Cost,
High-Performance Chargers
22 ______________________________________________________________________________________
19
20
18
17
7
6
8
AGND
IINP
9
DCIN
BST
DLO
PGND
DHI
1 2
VAA
45
15 14 12 11
CC
VCTL
CSSN
CSSP
ACOK
BATT
MAX17005A
MAX17006A
MAX17015A
CSIP LDO
3
EXPOSED PADDLE
13
ACIN
16 10 ISET
LX
THIN QFN
4mm x 4mm
TOP VIEW
CSIN
Pin Configuration
BATT
ADAPTER
BST
CSSP CSSN
DHI
LX
DLO
PGND
CSIN
CSIP
BATT
BATTERY
CC
VCTL
ISET ACIN
AGND
IINP
VAA
LDO
ADAPTER
SYSTEM
DCIN
ACOK
MAX17005A
MAX17006A
MAX17015A
Minimal Operating Circuit
MAX17005A/MAX17006A/MAX17015A
1.2MHz, Low-Cost,
High-Performance Chargers
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
23
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
Chip Information
TRANSISTOR COUNT: 12,990
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
20 TQFN T2044-3 21-0139