a
AD8565/AD8566/AD8567
REV. C
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16 V Rail-to-Rail
Operational Amplifiers
PIN CONFIGURATIONS
FEATURES
Single-Supply Operation: 4.5 V to 16 V
Input Capability beyond the Rails
Rail-to-Rail Output Swing
Continuous Output Current: 35 mA
Peak Output Current: 250 mA
Offset Voltage: 10 mV
Slew Rate: 6 V/s
Unity Gain Stable with Large Capacitive Loads
Supply Current: 700 A per Amplifier
APPLICATIONS
LCD Reference Drivers
Portable Electronics
Communications Equipment
GENERAL DESCRIPTION
The AD8565, AD8566, and AD8567 are low cost, single-supply
rail-to-rail input and output operational amplifiers optimized for
LCD monitor applications. They are built on an advanced high
voltage CBCMOS process. The AD8565 contains a single
amplifier, the AD8566 has two amplifiers, and the AD8567 has
four amplifiers.
These LCD op amps have high slew rates, 35 mA continuous
output drive, 250 mA peak output drive, and high capacitive load
drive capability. They have a wide supply range and offset volt-
ages below 10 mV. The AD8565, AD8566, and AD8567 are
ideal for LCD grayscale reference buffer and V
COM
applications.
The AD8565, AD8566, and AD8567 are specified over the –40°C
to +85°C temperature range. The AD8565 single is available in a
5-lead SC70 package. The AD8566 dual is available in an 8-lead
MSOP package. The AD8567 quad is available in 14-lead TSSOP
and 16-lead LFCSP packages.
5-Lead SC70
(KS Suffix)
1
2
3
5
4–IN
+IN
V–OUT
AD8565
V+
14-Lead TSSOP
(RU Suffix)
OUT B
+IN B
–IN B
V+
–IN A
+IN A
OUT A
78
510
69
411
213
312
114
OUT C
+IN C
–IN C
V–
–IN D
+IN D
OUT D
AD8567
16-Lead LFCSP
(CP Suffix)
TOP VIEW
16
5
13
8
9
12
1
4
1415
2
3
76
11
10
–IN D
+IN D
V–
+IN C
–IN A
+IN A
V+
+IN B
NC
OUT A
OUT D
NC
–IN B
OUT B
OUT C
–IN C
AD8567
NC = NO CONNECT
8-Lead MSOP
(RM Suffix)
45
27
36
18
OUT A
–IN A
+IN A
V–
V+
OUT B
–IN B
+IN B
AD8566
–2– REV. C
AD8565/AD8566/AD8567–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage V
OS
210 mV
Offset Voltage Drift ∆V
OS
/∆T–40°C ≤ T
A
≤ +85°C5 µV/°C
Input Bias Current I
B
80 600 nA
–40°C ≤ T
A
≤ +85°C800 nA
Input Offset Current I
OS
180 nA
–40°C ≤ T
A
≤ +85°C130 nA
Input Voltage Range Common-Mode Input –0.5 V
S
+ 0.5 V
Common-Mode Rejection Ratio CMRR V
CM
= 0 to V
S
,
–40°C ≤ T
A
≤ +85°C5495 dB
Large Signal Voltage Gain AVO R
L
= 10 kΩ,
V
O
= 0.5 V to (V
S
– 0.5 V) 3 10 V/mV
Input Impedance Z
IN
400 kΩ
Input Capacitance C
IN
1pF
OUTPUT CHARACTERISTICS
Output Voltage High V
OH
I
L
= 100 µAV
S
– 0.005 V
V
S
= 16 V, I
L
= 5 mA 15.85 15.95 V
–40°C ≤ T
A
≤ +85°C15.75 V
V
S
= 4.5 V, I
L
= 5 mA 4.2 4.38 V
–40°C ≤ T
A
≤ +85°C4.1 V
Output Voltage Low V
OL
I
L
= 100 µA5mV
V
S
= 16 V, I
L
= 5 mA 42 150 mV
–40°C ≤ T
A
≤ +85°C250 mV
V
S
= 4.5 V, I
L
= 5 mA 95 300 mV
–40°C ≤ T
A
≤ +85°C400 mV
Continuous Output Current I
OUT
35 mA
Peak Output Current I
PK
V
S
= 16 V 250 mA
POWER SUPPLY
Supply Voltage V
S
4.5 16 V
Power Supply Rejection Ratio PSRR V
S
= 4 V to 17 V,
–40°C ≤ T
A
≤ +85°C7090 dB
Supply Current/Amplifier I
SY
V
O
= V
S
/2, No Load 700 850 µA
–40°C ≤ T
A
≤ +85°C1mA
DYNAMIC PERFORMANCE
Slew Rate SR R
L
= 10 kΩ, C
L
= 200 pF 4 6 V/µs
Gain Bandwidth Product GBP R
L
= 10 kΩ, C
L
= 10 pF 5 MHz
Phase Margin ØoR
L
= 10 kΩ, C
L
= 10 pF 65 Degrees
Channel Separation 75 dB
NOISE PERFORMANCE
Voltage Noise Density e
n
f = 1 kHz 26 nV/√Hz
e
n
f = 10 kHz 25 nV/√Hz
Current Noise Density i
n
f = 10 kHz 0.8 pA/√Hz
Specifications subject to change without notice.
(4.5 V ≤ VS ≤ 16 V, VCM = VS/2, TA = 25C, unless otherwise noted.)
AD8565/AD8566/AD8567
–3–
REV. C
ABSOLUTE MAXIMUM RATINGS
*
Supply Voltage (V
S
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
S
+ 0.5 V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . V
S
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Junction Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
Temperature Package
Model Range Package Description Option Branding
AD8565AKS-R2 –40°C to +85°C5-Lead Thin Shrink Small Outline Transistor Package KS-5 ASA
AD8565AKS-REEL7 –40°C to +85°C5-Lead Thin Shrink Small Outline Transistor Package KS-5 ASA
AD8565AKSZ-REEL7*–40°C to +85°C5-Lead Thin Shrink Small Outline Transistor Package KS-5 ASA
AD8566ARM-R2 –40°C to +85°C8-Lead Micro Small Outline Package RM-8 ATA
AD8566ARM-REEL –40°C to +85°C8-Lead Micro Small Outline Package RM-8 ATA
AD8566ARMZ-REEL*–40°C to +85°C8-Lead Micro Small Outline Package RM-8 ATA
AD8567ARU –40°C to +85°C14-Lead Thin Shrink Small Outline Package RU-14
AD8567ARU-REEL –40°C to +85°C14-Lead Thin Shrink Small Outline Package RU-14
AD8567ARUZ*–40°C to +85°C14-Lead Thin Shrink Small Outline Package RU-14
AD8567ARUZ-REEL*–40°C to +85°C14-Lead Thin Shrink Small Outline Package RU-14
AD8567ACP-R2 –40°C to +85°C16-Lead Lead Frame Chip Scale Package CP-16
AD8567ACP-REEL –40°C to +85°C16-Lead Lead Frame Chip Scale Package CP-16
AD8567ACP-REEL7 –40°C to +85°C16-Lead Lead Frame Chip Scale Package CP-16
AD8567ACPZ-REEL*–40°C to +85°C16-Lead Lead Frame Chip Scale Package CP-16
AD8567ACPZ-REEL7*–40°C to +85°C16-Lead Lead Frame Chip Scale Package CP-16
*Z = Pb-free part.
Package Type
JA1
JC
Unit
5-Lead SC70 (KS) 376 126 °C/W
8-Lead MSOP (RM) 210 45 °C/W
14-Lead TSSOP (RU) 180 35 °C/W
16-Lead LFCSP (CP) 38
2
30
2
°C/W
NOTES
1
θ
JA
is specified for worst-case conditions, i.e., θ
JA
is specified for a device soldered
onto a circuit board for surface-mount packages.
2
DAP is soldered down to PCB.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8565/AD8566/AD8567 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
AD8565/AD8566/AD8567
–4– REV. C
–Typical Performance Characteristics
TEMPERATURE (C)
0
0.25
1.50 40
INPUT OFFSET VOLTAGE (mV)
25 85
0.50
0.75
1.00
1.25
V
CM
= V
S
/2
V
S
= 16V
V
S
= 4.5V
TPC 1. Input Offset Voltage vs. Temperature
FREQUENCY (Hz)
10
1
0.110 10k100 1k
4.5V V
S
16V
T
A
= 25C
CURRENT NOISE DENSITY (pA Hz)
TPC 2. Current Noise Density vs. Frequency
FREQUENCY (1s/DIV)
TIME (50mV/DIV)
V
S
= 16V
R
L
= 10k
C
L
= 100pF
A
V
= +1
T
A
= 25C
TPC 3. Small Signal Transient Response
VOLTAGE NOISE DENSITY (nV Hz)
FREQUENCY (Hz)
1000
100
110 10k100 1k
4.5V V
S
16V
T
A
= 25C
10
TPC 4. Voltage Noise Density vs. Frequency
SUPPLY VOLTAGE (V)
1.0
0.8
00182
SUPPLY CURRENT/AMPLIFIER (mA)
4681012 14 16
0.6
0.4
0.2
V
O
= V
S
/2
A
V
= +1
T
A
= 25C
TPC 5. Supply Current/Amplifier vs. Supply Voltage
TEMPERATURE (C)
0.80
0.75
0.50 40
SUPPLY CURRENT/AMPLIFIER (mA)
25 85
0.70
0.65
0.60
0.55
VCM = VS/2
VS = 16V
VS = 4.5V
TPC 6. Supply Current/Amplifier vs. Temperature
AD8565/AD8566/AD8567
–5–
REV. C
LOAD CAPACITANCE (pF)
100
90
010 1k100
OVERSHOOT (%)
80
70
60
50
40
30
20
10
V
S
= 16V
V
IN
= 100mV p-p
R
L
= 10k
A
V
= +1
T
A
= 25C
–OS
+OS
TPC 7. Small Signal Overshoot vs. Load Capacitance
FREQUENCY (Hz)
OUTPUT SWING (V p-p)
0100
10 1k 10k 100k 1M 10M
2
4
6
8
10
12
14
16
18
VS = 16V
AV = +1
RL = 10k
DISTORTION < 1%
TA = 25C
TPC 8. Closed-Loop Output Swing vs. Frequency
FREQUENCY (Hz)
CLOSED-LOOP GAIN (dB)
10010 1k 10k 100k 1M 10M
10
20
30
40
50
4.5V V
S
16V
R
L
= 10k
C
L
= 40pF
T
A
= 25C
60
0
A
VCL
= –100
A
VCL
= –10
A
VCL
= +1
TPC 9. Closed-Loop Gain vs. Frequency
1k 100M10k
GAIN (dB)
100k 1M 10M
100
80
60
40
20
FREQUENCY (Hz)
45
90
135
180
0
225
270
PHASE SHIFT (degrees)
V
S
= 16V
R
L
= 10k
C
L
= 40pF
T
A
= 25C
0
TPC 10. Open-Loop Gain and Phase Shift vs. Frequency
LOAD CURRENT (mA)
10
0.1
0.001 1000.01 0.1 1 10
1
100 VS = 4.5V
1k
TA = 25C
VS = 16V
OUTPUT VOLTAGE (mV)
TPC 11. Output Voltage to Supply Rail vs. Load Current
TEMPERATURE (C)
150
40
OUTPUT VOLTAGE (mV)
25 85
ISINK = 5mA
VS = 16V
VS = 4.5V
135
120
105
90
75
60
45
30
15
0
TPC 12. Output Voltage Swing to Rail vs. Temperature
AD8565/AD8566/AD8567
–6– REV. C
TEMPERATURE (C)
150
40
OUTPUT VOLTAGE (mV)
25 85
I
SOURCE
= 5mA
V
S
= 16V
V
S
= 4.5V
135
120
105
90
75
60
45
30
15
0
TPC 13. Output Voltage Swing to Rail vs. Temperature
FREQUENCY (Hz)
100 10M1k
IMPEDANCE ()
10k 100k 1M
500
450
0
400
350
300
250
200
150
100
50
A
V
= +1
T
A
= 25C
V
S
= 16V
V
S
= 4.5V
TPC 14. Closed-Loop Output Impedance vs. Frequency
FREQUENCY (Hz)
CMRR (dB)
10010 1k 10k 100k 1M 10M
20
40
60
80
100
VS = 16V
TA = 25C
120
0
140
TPC 15. Common-Mode Rejection Ratio vs. Frequency
FREQUENCY (Hz)
100 10M1k
POWER SUPPLY REJECTION RATIO (dB)
10k 100k 1M
160
140
40
120
100
80
60
40
20
0
20
V
S
= 16V
T
A
= 25C
+PSRR
–PSRR
TPC 16. Power Supply Rejection Ratio vs. Frequency
TIME (40s/DIV)
VOLTAGE (3V/DIV)
VS = 16V
RL = 10k
AV = +1
TA = 25C
TPC 17. No Phase Reversal
INPUT OFFSET VOLTAGE (mV)
10 10
864202468
1.8k
1.6k
0
QUANTITY (Amplifiers)
800
600
400
200
1.2k
1.0k
1.4k
V
S
= 16V
T
A
= 25C
TPC 18. Input Offset Voltage Distribution
AD8565/AD8566/AD8567
–7–
REV. C
TEMPERATURE (C)
–5 –40
INPUT OFFSET CURRENT (nA)
25 85
–1
–2
–3
–4
VS = 16V
VS = 4.5V
5
1
0
3
2
4
TPC 19. Input Offset Current vs. Temperature
TEMPERATURE (C)
–350 –40
INPUT BIAS CURRENT (nA)
25 85
–150
–200
–250
–300
V
S
= 16V
V
S
= 4.5V
0
–50
–100
V
CM
= V
S
/2
TPC 20. Input Bias Current vs. Temperature
16V
CROSSTALK (dB)
–20
–40
–180
–60
–80
–160
–100
–120
–140
4.5V
FREQUENCY (Hz)
50 1k 60k10k100
TPC 21. Channel A vs. Channel B Crosstalk
COMMON-MODE VOLTAGE (V)
7
00162
BANDWIDTH (MHz)
4681012 14
6
4
3
2
1
5
VS = 16V
AV = +1
RL = x
TA = 25C
TPC 22. Frequency vs. Common-Mode Voltage (V
S
= 16 V)
COMMON-MODE VOLTAGE (V)
6
5
0051
BANDWIDTH (MHz)
234
4
3
2
1
V
S
= 5V
A
V
= +1
R
L
= 10k
T
A
= 25C
TPC 23. Frequency vs. Common-Mode Voltage
(V
S
= 5.0 V)
AD8565/AD8566/AD8567
–8– REV. C
APPLICATIONS
Theory of Operation
The AD856x family is designed to drive large capacitive loads in
LCD applications. It has high output current drive, rail-to-rail
input/output operation, and is powered from a single 16 V supply.
It is also intended for other applications where low distortion and
high output current drive are needed.
Figure 1 illustrates a simplified equivalent circuit for the AD856x.
The rail-to-rail bipolar input stage is composed of two PNP
differential pairs, Q4 to Q5 and Q10 to Q11, operating in series
with diode protection networks, D1 to D2. Diode network
D1 to D2 serves as protection against large transients for
Q4 to Q5 to accommodate rail-to-rail input swing. D5 to D6
protect Q10 to Q11 against Zenering. In normal operation,
Q10 to Q11 are off and their input stage is buffered from the
operational amplifier inputs by Q6 to D3 and Q8 to D4. Opera-
tion of the input stage is best understood as a function of applied
common-mode voltage: when the inputs of the AD856x are
biased midway between the supplies, the differential signal
path gain is controlled by resistive loads (via R9, R10) Q4 to Q5.
As the input common-mode level is reduced toward the negative
supply (V
NEG
or GND), the input transistor current sources, I1
and I2, are forced into saturation, thereby forcing the Q6 to D3
and Q8 to D4 networks into cutoff. However, Q4 to Q5 remain
active, providing input stage gain. Inversely, when common-mode
input voltage is increased toward the positive supply, Q4 to Q5
are driven into cutoff, Q3 is driven into saturation, and Q4
becomes active, providing bias to the Q10 to Q11 differential
pair. The point at which Q10 to Q11 differential pair becomes
active is approximately equal to (V
POS
– 1 V).
R1
R3 R4
D1 D2
Q4
Q3 BIAS LINE
V–
D3 D4
Q5
Q4
R5 R6
Q10 Q11
C1
C2
D5
D6
Q8
Q6
R9 R10
FOLDED
CASCADE
V+
I1 I2
VNEG
VPOS
Figure 1. AD856x Equivalent Input Circuit
The benefit of this type of input stage is low bias current. The
input bias current is the sum of base currents of Q4 to Q5 and
Q6 to Q8 over the range from (V
NEG
+ 1 V) to (V
POS
– 1 V). Out-
side of this range, input bias current is dominated by the sum of
base currents of Q10 to Q11 for input signals close to V
NEG
and of
Q6 to Q8 (Q10 to Q11) for signals close to V
POS
. From this type
of design, the input bias current of AD856x not only exhibits
different amplitude but also exhibits different polarities. Figure 2
provides the characteristics of the input bias current versus the
common-mode voltage. It is important to keep in mind that the
source impedances driving the AD856x inputs are balanced for
optimum dc and ac performance.
INPUT COMMON-MODE VOLTAGE (V)
1,000
–1,000 0162
INPUT BIAS CURRENT (nA)
468101214
800
200
–200
–600
–800
600
400
0
–400
VS = 16V
TA = 25C
Figure 2. AD856x Input Bias Current vs. Common-Mode
Voltage
In order to achieve rail-to-rail output performance, the AD856x
design uses a complementary common-source (or gmRL) output.
This configuration allows output voltages to approach the power
supply rails, particularly if the output transistors are allowed to
enter the triode region on extremes of signal swing, which are
limited by V
GS
, the transistor sizes, and output load current.
Also, this type of output stage exhibits voltage gain in an open-loop
gain configuration. The amount of gain depends on the total
load resistance at the output of the AD856x.
Input Overvoltage Protection
As with any semiconductor device, whenever the input exceeds
either supply voltages, attention needs to be paid to the input
overvoltage characteristics. As an overvoltage occurs, the amplifier
could be damaged, depending on the voltage level and the magnitude
of the fault current. When the input voltage exceeds either supply
by more than 0.6 V, internal pn junctions allow current to flow
from the input to the supplies.
This input current is not inherently damaging to the device as
long as it is limited to 5 mA or less. If a condition exists using
the AD856x where the input exceeds the supply more than 0.6 V,
an external series resistor should be added. The size of the resis-
tor can be calculated by using the maximum overvoltage divided
by 5 mA. This resistance should be placed in series with either
input exposed to an overvoltage.
AD8565/AD8566/AD8567
–9–
REV. C
Output Phase Reversal
The AD856x family is immune to phase reversal. Although
the device’s output will not change phase, large currents due
to input overvoltage could damage the device. In applications
where the possibility of an input voltage exceeding the supply
voltage exists, overvoltage protection should be used as described
in the previous section.
Power Dissipation
The maximum allowable internal junction temperature of 150°C
limits the AD856x family’s maximum power dissipation of
AD856x devices. As the ambient temperature increases, the
maximum power dissipated by AD856x devices must decrease
linearly to maintain the maximum junction temperature. If this
maximum junction temperature is exceeded momentarily, the
device will still operate properly once the junction temperature is
reduced below 150°C. If the maximum junction temperature is
exceeded for an extended period of time, overheating could lead
to permanent damage of the device.
The maximum safe junction temperature, T
J
MAX
, is 150°C. Using
the following formula, we can obtain the maximum power that
an AD856x device can safely dissipate as a function of temperature:
PDISS = T
J
MAX – TA/
θ
J
A
where:
P
DISS
= the AD856x power dissipation.
T
J
MAX
= the AD856x maximum allowable junction
temperature (150°C).
T
A
= the ambient temperature of the circuit.
θ
J
A
= the AD856x package thermal resistance,
junction-to-ambient.
The power dissipated by the device can be calculated as
PDISS = (VS – VOUT) ⫻ ILOAD
where:
V
S
= the supply voltage.
V
OUT
= the output voltage.
I
LOAD
= the output load current.
Figure 3 shows the maximum power dissipation versus temperature.
To achieve proper operation, use the previous equation to calculate
P
DISS
for a specific package at any given temperature or use the
figure below.
AMBIENT TEMPERATURE (C)
1.25
0.75
0
–35
MAXIMUM POWER DISSIPATION ( W)
0.50
0.25
14-LEAD SOIC
5-LEAD SOT-23
8-LEAD MSOP
14-LEAD TSSOP
1.00
–15 5 25 456585
Figure 3. Maximum Power Dissipation vs. Temperature
for 5-, 8-, and 14-Lead Packages
Total Harmonic Distortion + Noise (THD+N)
The AD856x family features low total harmonic distortion.
Figure 4 shows a graph of THD+N versus frequency. The THD+N
for the AD856x over the entire supply range is below 0.008%.
When the device is powered from a 16 V supply, the THD+N
stays below 0.003%. Figure 4 shows the AD8566 in a unity
noninverting configuration.
FREQUENCY (Hz)
20 30k
THD+N (%)
100 1k 10k
10
1
0.01
0.1
VS = 2.5V
VS = 8V
Figure 4. THD+N vs. Frequency Graph
Short-Circuit Output Conditions
The AD856x family does not have internal short-circuit protection
circuitry. As a precautionary measure, it is recommended not to
short the output directly to the positive power supply or to ground.
It is not recommended to operate the AD856x with more than
35 mA of continuous output current. The output current can be
limited by placing a series resistor at the output of the amplifier
whose value can be derived using the following equation:
RV
X
S
≥35 mA
For a 5 V single-supply operation, R
X
should have a minimum
value of 143 Ω.
LCD Panel Applications
The AD856x amplifier is designed for LCD panel applications
or applications where large capacitive load drive is required. It
can instantaneously source/sink greater than 250 mA of current.
At unity gain, it can drive 1 µF without compensation. This
makes the AD856x ideal for LCD V
COM
driver applications.
To evaluate the performance of the AD856x family, a test circuit
was developed to simulate the V
COM
driver application for an
LCD panel.
AD8565/AD8566/AD8567
–10– REV. C
Figure 5 shows the test circuit. Series capacitors and resistors
connected to the output of the op amp represent the load of the
LCD panel. The 300 Ω and 3 kΩ feedback resistors are used to
improve settling time. This test circuit simulates the worst-case
scenario for a V
COM
. It drives a represented load that is connected
to a signal switched symmetrically around V
COM
. Figure 6 displays
a scope photo of the instantaneous output peak current capability
of the AD856x family.
INPUT 0V TO 8V
SQUARE WAVE WITH
15.6s PULSE WIDTH
300
3k
10101010
10nF 10nF 10nF 10nF
MEASURE
CURRENT
4V
8V
10–20
Figure 5. V
COM
Test Circuit with Supply Voltage at 16 V
10
0%
100
90
TIME (2s/DIV)
CH 1 = 5V/DIV
CH 2 =
100mA/DIV
Figure 6. Scope Photo of the V
COM
Instantaneous
Peak Current
AD8565/AD8566/AD8567
–11–
REV. C
14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
4.50
4.40
4.30
14 8
71
6.40
BSC
PIN 1
5.10
5.00
4.90
0.65
BSC
SEATING
PLANE
0.15
0.05 0.30
0.19
1.20
MAX
1.05
1.00
0.80 0.20
0.09
8
0
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MO-153AB-1
COPLANARITY
0.10
OUTLINE DIMENSIONS
5-Lead Thin Shrink Small Outline Transistor Package [SC70]
(KS-5)
Dimensions shown in millimeters
0.30
0.15
1.00
0.90
0.70
SEATING
PLANE
1.10 MAX
0.22
0.08 0.46
0.36
0.26
3
5 4
1 2
2.00 BSC
PIN 1
2.10 BSC
0.65 BSC
1.25 BSC
0.10 MAX
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-203AA
8-Lead Micro Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
0.80
0.60
0.40
8
0
85
4
1
4.90
BSC
PIN 1
0.65 BSC
3.00
BSC
SEATING
PLANE
0.15
0.00
0.38
0.22
1.10 MAX
3.00
BSC
COPLANARITY
0.10
0.23
0.08
COMPLIANT TO JEDEC STANDARDS MO-187AA
–12–
C01909–0–3/04(C)
REV. C
–12–
AD8565/AD8566/AD8567
Revision History
Location Page
3/04—Data Sheet changed from REV. B to REV. C.
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Changes to TPC 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Changes to TPC 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Changes to TPC 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Changes to TPC 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
12/03—Data Sheet changed from REV. A to REV. B.
Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
10/01—Data Sheet changed from REV. 0 to REV. A.
Edit to 16-Lead CSP and 5-Lead SC70 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edit to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
16-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body
(CP-16)
Dimensions shown in millimeters
16
5
13
8
9
12 1
4
BOTTOM
VIEW
2.25
2.10
1.95
0.75
0.60
0.50
0.65 BSC
1.95 BSC
0.35
0.28
0.25
12MAX
0.20 REF
SEATING
PLANE
PIN 1
INDICATOR TOP
VIEW
4.0
BSC SQ
3.75
BSC SQ
0.60 MAX
0.60 MAX
0.05 MAX
0.02 NOM
0.80 MAX
0.65 TYP
PIN 1
INDICATOR
1.00
0.85
0.80 COPLANARITY
0.08
SQ
0.25 MIN
COMPLIANT TO JEDEC STANDARDS MO-220-VGGC
OUTLINE DIMENSIONS