a FEATURES Single-Supply Operation: 4.5 V to 16 V Input Capability beyond the Rails Rail-to-Rail Output Swing Continuous Output Current: 35 mA Peak Output Current: 250 mA Offset Voltage: 10 mV Slew Rate: 6 V/s Unity Gain Stable with Large Capacitive Loads Supply Current: 700 A per Amplifier 16 V Rail-to-Rail Operational Amplifiers AD8565/AD8566/AD8567 PIN CONFIGURATIONS 5-Lead SC70 (KS Suffix) 8-Lead MSOP (RM Suffix) AD8565 OUT 1 5 V- OUT A 1 -IN A V+ 2 +IN 3 4 -IN APPLICATIONS LCD Reference Drivers Portable Electronics Communications Equipment 8 V+ 2 7 OUT B +IN A 3 6 -IN B V- 4 5 +IN B 14-Lead TSSOP (RU Suffix) OUT A 1 13 -IN D +IN A 3 12 +IN D V+ 4 11 V- AD8567 +IN B 5 10 +IN C -IN B 6 9 -IN C OUT B 7 The AD8565, AD8566, and AD8567 are specified over the -40C to +85C temperature range. The AD8565 single is available in a 5-lead SC70 package. The AD8566 dual is available in an 8-lead MSOP package. The AD8567 quad is available in 14-lead TSSOP and 16-lead LFCSP packages. 8 OUT C OUT A OUT D NC 16-Lead LFCSP (CP Suffix) NC 16 15 14 13 -IN A 1 12 -IN D +IN A 2 AD8567 11 +IN D V+ 3 TOP VIEW 10 V- +IN B 4 5 6 7 8 -IN C 9 OUT C These LCD op amps have high slew rates, 35 mA continuous output drive, 250 mA peak output drive, and high capacitive load drive capability. They have a wide supply range and offset voltages below 10 mV. The AD8565, AD8566, and AD8567 are ideal for LCD grayscale reference buffer and VCOM applications. -IN A 2 -IN B The AD8565, AD8566, and AD8567 are low cost, single-supply rail-to-rail input and output operational amplifiers optimized for LCD monitor applications. They are built on an advanced high voltage CBCMOS process. The AD8565 contains a single amplifier, the AD8566 has two amplifiers, and the AD8567 has four amplifiers. 14 OUT D OUT B GENERAL DESCRIPTION AD8566 +IN C NC = NO CONNECT REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2004 Analog Devices, Inc. All rights reserved. AD8565/AD8566/AD8567-SPECIFICATIONS ELECTRICAL CHARACTERISTICS (4.5 V V 16 V, V S CM = VS /2, TA = 25C, unless otherwise noted.) Parameter Symbol Conditions INPUT CHARACTERISTICS Offset Voltage Offset Voltage Drift Input Bias Current VOS VOS/T IB -40C TA +85C Input Offset Current IOS Input Voltage Range Common-Mode Rejection Ratio CMRR Large Signal Voltage Gain AVO Input Impedance Input Capacitance ZIN CIN OUTPUT CHARACTERISTICS Output Voltage High Output Voltage Low Continuous Output Current Peak Output Current POWER SUPPLY Supply Voltage Power Supply Rejection Ratio Supply Current/Amplifier DYNAMIC PERFORMANCE Slew Rate Gain Bandwidth Product Phase Margin Channel Separation NOISE PERFORMANCE Voltage Noise Density Current Noise Density VOH VOL IOUT IPK VS PSRR ISY Min Typ Max Unit 2 5 80 10 mV V/C nA nA nA nA V -40C TA +85C 1 -40C TA +85C Common-Mode Input VCM = 0 to VS, -40C TA +85C RL = 10 k, VO = 0.5 V to (VS - 0.5 V) IL = 100 A VS = 16 V, IL = 5 mA -40C TA +85C VS = 4.5 V, IL = 5 mA -40C TA +85C IL = 100 A VS = 16 V, IL = 5 mA -40C TA +85C VS = 4.5 V, IL = 5 mA -40C TA +85C -0.5 54 95 dB 3 10 400 1 V/mV k pF VS - 0.005 15.95 V V V V V mV mV mV mV mV mA mA 15.85 15.75 4.2 4.1 4.38 5 42 95 4.5 SR GBP Oo RL = 10 k, CL = 200 pF RL = 10 k, CL = 10 pF RL = 10 k, CL = 10 pF en en in f = 1 kHz f = 10 kHz f = 10 kHz 150 250 300 400 35 250 VS = 16 V VS = 4 V to 17 V, -40C TA +85C VO = VS/2, No Load -40C TA +85C 600 800 80 130 VS + 0.5 70 4 90 700 16 V 850 1 dB A mA 6 5 65 75 V/s MHz Degrees dB 26 25 0.8 nV/Hz nV/Hz pA/Hz Specifications subject to change without notice. -2- REV. C AD8565/AD8566/AD8567 ABSOLUTE MAXIMUM RATINGS * Supply Voltage (VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Input Voltage . . . . . . . . . . . . . . . . . . . . . -0.5 V to VS + 0.5 V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . VS Storage Temperature Range . . . . . . . . . . . . -65C to +150C Operating Temperature Range . . . . . . . . . . . -40C to +85C Junction Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Package Type JA1 JC Unit 5-Lead SC70 (KS) 8-Lead MSOP (RM) 14-Lead TSSOP (RU) 16-Lead LFCSP (CP) 376 210 180 382 126 45 35 302 C/W C/W C/W C/W NOTES 1 JA is specified for worst-case conditions, i.e., JA is specified for a device soldered onto a circuit board for surface-mount packages. 2 DAP is soldered down to PCB. ORDERING GUIDE Model Temperature Range Package Description Package Option AD8565AKS-R2 AD8565AKS-REEL7 AD8565AKSZ-REEL7* AD8566ARM-R2 AD8566ARM-REEL AD8566ARMZ-REEL* AD8567ARU AD8567ARU-REEL AD8567ARUZ* AD8567ARUZ-REEL* AD8567ACP-R2 AD8567ACP-REEL AD8567ACP-REEL7 AD8567ACPZ-REEL* AD8567ACPZ-REEL7* -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C 5-Lead Thin Shrink Small Outline Transistor Package 5-Lead Thin Shrink Small Outline Transistor Package 5-Lead Thin Shrink Small Outline Transistor Package 8-Lead Micro Small Outline Package 8-Lead Micro Small Outline Package 8-Lead Micro Small Outline Package 14-Lead Thin Shrink Small Outline Package 14-Lead Thin Shrink Small Outline Package 14-Lead Thin Shrink Small Outline Package 14-Lead Thin Shrink Small Outline Package 16-Lead Lead Frame Chip Scale Package 16-Lead Lead Frame Chip Scale Package 16-Lead Lead Frame Chip Scale Package 16-Lead Lead Frame Chip Scale Package 16-Lead Lead Frame Chip Scale Package KS-5 KS-5 KS-5 RM-8 RM-8 RM-8 RU-14 RU-14 RU-14 RU-14 CP-16 CP-16 CP-16 CP-16 CP-16 Branding ASA ASA ASA ATA ATA ATA *Z = Pb-free part. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8565/AD8566/AD8567 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. C -3- WARNING! ESD SENSITIVE DEVICE AD8565/AD8566/AD8567-Typical Performance Characteristics 0 1000 4.5V VS TA = 25C VOLTAGE NOISE DENSITY (nV Hz) 0.25 0.50 VS = 16V 0.75 VS = 4.5V 1.00 1.25 1.50 40 25 TEMPERATURE (C) 10 1 10 TPC 1. Input Offset Voltage vs. Temperature 10k 1.0 16V SUPPLY CURRENT/AMPLIFIER (mA) 4.5V VS TA = 25C CURRENT NOISE DENSITY (pA Hz) 100 1k FREQUENCY (Hz) TPC 4. Voltage Noise Density vs. Frequency 10 1 0.1 16V 100 85 10 100 1k FREQUENCY (Hz) TPC 2. Current Noise Density vs. Frequency VO = VS/2 AV = +1 TA = 25C 0.8 0.6 0.4 0.2 0 10k 0 4 2 6 8 10 12 SUPPLY VOLTAGE (V) 14 16 18 TPC 5. Supply Current/Amplifier vs. Supply Voltage 0.80 VS = 16V RL = 10k CL = 100pF AV = +1 TA = 25C SUPPLY CURRENT/AMPLIFIER (mA) VCM = VS/2 TIME (50mV/DIV) INPUT OFFSET VOLTAGE (mV) VCM = VS/2 0.75 VS = 16V 0.70 0.65 0.60 VS = 4.5V 0.55 0.50 FREQUENCY (1s/DIV) TPC 3. Small Signal Transient Response 40 25 TEMPERATURE (C) 85 TPC 6. Supply Current/Amplifier vs. Temperature -4- REV. C AD8565/AD8566/AD8567 100 80 80 60 GAIN (dB) OVERSHOOT (%) 70 VS = 16V RL = 10k CL = 40pF TA = 25C 100 -OS 50 +OS 40 0 60 45 40 90 20 135 0 180 30 225 20 270 PHASE SHIFT (degrees) VS = 16V VIN = 100mV p-p RL = 10k AV = +1 TA = 25C 90 10 0 10 100 LOAD CAPACITANCE (pF) 1k 1k TPC 7. Small Signal Overshoot vs. Load Capacitance 10M 100M 1k TA = 25C 16 OUTPUT VOLTAGE (mV) 14 OUTPUT SWING (V p-p) 100k 1M FREQUENCY (Hz) TPC 10. Open-Loop Gain and Phase Shift vs. Frequency 18 12 10 8 6 VS = 16V AV = +1 RL = 10k DISTORTION < 1% TA = 25C 4 2 0 10k 10 100 1k 10k 100k FREQUENCY (Hz) 1M 100 VS = 16V 10 1 0.1 0.001 10M TPC 8. Closed-Loop Output Swing vs. Frequency VS = 4.5V 0.01 0.1 1 LOAD CURRENT (mA) 10 100 TPC 11. Output Voltage to Supply Rail vs. Load Current 150 4.5V VS 16V RL = 10k CL = 40pF TA = 25C 60 AVCL = -100 40 30 AVCL = -10 20 10 AVCL = +1 0 ISINK = 5mA 120 OUTPUT VOLTAGE (mV) CLOSED-LOOP GAIN (dB) 50 135 105 VS = 4.5V 90 75 60 45 VS = 16V 30 15 0 10 100 1k 100k 10k FREQUENCY (Hz) 1M 10M TPC 9. Closed-Loop Gain vs. Frequency REV. C 40 25 TEMPERATURE (C) 85 TPC 12. Output Voltage Swing to Rail vs. Temperature -5- AD8565/AD8566/AD8567 150 160 ISOURCE = 5mA OUTPUT VOLTAGE (mV) 120 POWER SUPPLY REJECTION RATIO (dB) 135 VS = 4.5V 105 90 75 60 VS = 16V 45 30 15 0 40 25 TEMPERATURE (C) VS = 16V TA = 25C 140 120 100 80 +PSRR 60 -PSRR 40 20 0 20 40 100 85 TPC 13. Output Voltage Swing to Rail vs. Temperature 1k 10k 100k FREQUENCY (Hz) 1M 10M TPC 16. Power Supply Rejection Ratio vs. Frequency 500 VS = 16V RL = 10k AV = +1 TA = 25C AV = +1 TA = 25C 450 400 VOLTAGE (3V/DIV) IMPEDANCE () 350 VS = 4.5V 300 250 200 150 100 50 VS = 16V 0 100 10k 100k FREQUENCY (Hz) 1k 1M 10M TIME (40s/DIV) TPC 14. Closed-Loop Output Impedance vs. Frequency TPC 17. No Phase Reversal 1.8k VS = 16V TA = 25C 140 120 QUANTITY (Amplifiers) 1.4k 100 CMRR (dB) VS = 16V TA = 25C 1.6k 80 60 40 20 1.2k 1.0k 800 600 400 0 200 10 100 1k 100k 10k FREQUENCY (Hz) 1M 0 10 10M TPC 15. Common-Mode Rejection Ratio vs. Frequency 8 6 0 2 4 4 2 INPUT OFFSET VOLTAGE (mV) 6 8 10 TPC 18. Input Offset Voltage Distribution -6- REV. C AD8565/AD8566/AD8567 7 5 6 3 2 BANDWIDTH (MHz) INPUT OFFSET CURRENT (nA) 4 VS = 4.5V 1 0 VS = 16V -1 -2 5 4 3 2 VS = 16V AV = +1 RL = x TA = 25C -3 1 -4 0 -5 -40 25 TEMPERATURE (C) 85 TPC 19. Input Offset Current vs. Temperature 0 2 4 6 8 10 12 COMMON-MODE VOLTAGE (V) 6 VS = 5V AV = +1 RL = 10k TA = 25C VCM = VS /2 5 VS = 16V -100 BANDWIDTH (MHz) INPUT BIAS CURRENT (nA) -50 VS = 4.5V -150 -200 -250 -350 25 TEMPERATURE (C) -40 3 2 0 85 TPC 20. Input Bias Current vs. Temperature -40 -60 -80 -100 4.5V -120 16V -140 -160 100 1k FREQUENCY (Hz) 10k 0 1 2 3 COMMON-MODE VOLTAGE (V) 4 5 TPC 23. Frequency vs. Common-Mode Voltage (VS = 5.0 V) -20 CROSSTALK (dB) 4 1 -300 60k TPC 21. Channel A vs. Channel B Crosstalk REV. C 16 TPC 22. Frequency vs. Common-Mode Voltage (VS = 16 V) 0 -180 50 14 -7- AD8565/AD8566/AD8567 The benefit of this type of input stage is low bias current. The input bias current is the sum of base currents of Q4 to Q5 and Q6 to Q8 over the range from (VNEG + 1 V) to (VPOS - 1 V). Outside of this range, input bias current is dominated by the sum of base currents of Q10 to Q11 for input signals close to VNEG and of Q6 to Q8 (Q10 to Q11) for signals close to VPOS. From this type of design, the input bias current of AD856x not only exhibits different amplitude but also exhibits different polarities. Figure 2 provides the characteristics of the input bias current versus the common-mode voltage. It is important to keep in mind that the source impedances driving the AD856x inputs are balanced for optimum dc and ac performance. APPLICATIONS Theory of Operation The AD856x family is designed to drive large capacitive loads in LCD applications. It has high output current drive, rail-to-rail input/output operation, and is powered from a single 16 V supply. It is also intended for other applications where low distortion and high output current drive are needed. Figure 1 illustrates a simplified equivalent circuit for the AD856x. The rail-to-rail bipolar input stage is composed of two PNP differential pairs, Q4 to Q5 and Q10 to Q11, operating in series with diode protection networks, D1 to D2. Diode network D1 to D2 serves as protection against large transients for Q4 to Q5 to accommodate rail-to-rail input swing. D5 to D6 protect Q10 to Q11 against Zenering. In normal operation, Q10 to Q11 are off and their input stage is buffered from the operational amplifier inputs by Q6 to D3 and Q8 to D4. Operation of the input stage is best understood as a function of applied common-mode voltage: when the inputs of the AD856x are biased midway between the supplies, the differential signal path gain is controlled by resistive loads (via R9, R10) Q4 to Q5. As the input common-mode level is reduced toward the negative supply (VNEG or GND), the input transistor current sources, I1 and I2, are forced into saturation, thereby forcing the Q6 to D3 and Q8 to D4 networks into cutoff. However, Q4 to Q5 remain active, providing input stage gain. Inversely, when common-mode input voltage is increased toward the positive supply, Q4 to Q5 are driven into cutoff, Q3 is driven into saturation, and Q4 becomes active, providing bias to the Q10 to Q11 differential pair. The point at which Q10 to Q11 differential pair becomes active is approximately equal to (VPOS - 1 V). 1,000 INPUT BIAS CURRENT (nA) 600 D2 R3 R4 Q6 R5 D3 Q10 R6 C2 Q11 14 16 This input current is not inherently damaging to the device as long as it is limited to 5 mA or less. If a condition exists using the AD856x where the input exceeds the supply more than 0.6 V, an external series resistor should be added. The size of the resistor can be calculated by using the maximum overvoltage divided by 5 mA. This resistance should be placed in series with either input exposed to an overvoltage. I2 FOLDED CASCADE R9 4 6 8 10 12 INPUT COMMON-MODE VOLTAGE (V) As with any semiconductor device, whenever the input exceeds either supply voltages, attention needs to be paid to the input overvoltage characteristics. As an overvoltage occurs, the amplifier could be damaged, depending on the voltage level and the magnitude of the fault current. When the input voltage exceeds either supply by more than 0.6 V, internal pn junctions allow current to flow from the input to the supplies. D4 D6 2 Input Overvoltage Protection D5 I1 0 In order to achieve rail-to-rail output performance, the AD856x design uses a complementary common-source (or gmRL) output. This configuration allows output voltages to approach the power supply rails, particularly if the output transistors are allowed to enter the triode region on extremes of signal swing, which are limited by VGS, the transistor sizes, and output load current. Also, this type of output stage exhibits voltage gain in an open-loop gain configuration. The amount of gain depends on the total load resistance at the output of the AD856x. V- Q5 Q4 -200 -400 Figure 2. AD856x Input Bias Current vs. Common-Mode Voltage Q8 C1 V+ 0 -800 BIAS LINE D1 200 -1,000 R1 Q4 400 -600 VPOS Q3 VS = 16V TA = 25C 800 R10 VNEG Figure 1. AD856x Equivalent Input Circuit -8- REV. C AD8565/AD8566/AD8567 Output Phase Reversal Total Harmonic Distortion + Noise (THD+N) The AD856x family is immune to phase reversal. Although the device's output will not change phase, large currents due to input overvoltage could damage the device. In applications where the possibility of an input voltage exceeding the supply voltage exists, overvoltage protection should be used as described in the previous section. The AD856x family features low total harmonic distortion. Figure 4 shows a graph of THD+N versus frequency. The THD+N for the AD856x over the entire supply range is below 0.008%. When the device is powered from a 16 V supply, the THD+N stays below 0.003%. Figure 4 shows the AD8566 in a unity noninverting configuration. Power Dissipation 10 The maximum allowable internal junction temperature of 150C limits the AD856x family's maximum power dissipation of AD856x devices. As the ambient temperature increases, the maximum power dissipated by AD856x devices must decrease linearly to maintain the maximum junction temperature. If this maximum junction temperature is exceeded momentarily, the device will still operate properly once the junction temperature is reduced below 150C. If the maximum junction temperature is exceeded for an extended period of time, overheating could lead to permanent damage of the device. THD+N (%) 1 0.1 VS = 8V The maximum safe junction temperature, TJMAX, is 150C. Using the following formula, we can obtain the maximum power that an AD856x device can safely dissipate as a function of temperature: 0.01 20 PDISS = TJMAX - TA/JA The AD856x family does not have internal short-circuit protection circuitry. As a precautionary measure, it is recommended not to short the output directly to the positive power supply or to ground. It is not recommended to operate the AD856x with more than 35 mA of continuous output current. The output current can be limited by placing a series resistor at the output of the amplifier whose value can be derived using the following equation: where: VS = the supply voltage. VOUT = the output voltage. ILOAD = the output load current. RX 1.25 MAXIMUM POWER DISSIPATION ( W) 14-LEAD SOIC LCD Panel Applications The AD856x amplifier is designed for LCD panel applications or applications where large capacitive load drive is required. It can instantaneously source/sink greater than 250 mA of current. At unity gain, it can drive 1 F without compensation. This makes the AD856x ideal for LCD VCOM driver applications. To evaluate the performance of the AD856x family, a test circuit was developed to simulate the VCOM driver application for an LCD panel. 1.00 14-LEAD TSSOP 8-LEAD MSOP 0.50 5-LEAD SOT-23 0.25 65 85 Figure 3. Maximum Power Dissipation vs. Temperature for 5-, 8-, and 14-Lead Packages REV. C VS 35 mA For a 5 V single-supply operation, RX should have a minimum value of 143 . Figure 3 shows the maximum power dissipation versus temperature. To achieve proper operation, use the previous equation to calculate PDISS for a specific package at any given temperature or use the figure below. 5 25 45 AMBIENT TEMPERATURE (C) 30k Figure 4. THD+N vs. Frequency Graph PDISS = (VS - VOUT) ILOAD -15 10k Short-Circuit Output Conditions The power dissipated by the device can be calculated as 0 -35 1k 100 FREQUENCY (Hz) where: PDISS = the AD856x power dissipation. TJMAX = the AD856x maximum allowable junction temperature (150C). TA = the ambient temperature of the circuit. JA = the AD856x package thermal resistance, junction-to-ambient. 0.75 VS = 2.5V -9- AD8565/AD8566/AD8567 Figure 5 shows the test circuit. Series capacitors and resistors connected to the output of the op amp represent the load of the LCD panel. The 300 and 3 k feedback resistors are used to improve settling time. This test circuit simulates the worst-case scenario for a VCOM. It drives a represented load that is connected to a signal switched symmetrically around VCOM. Figure 6 displays a scope photo of the instantaneous output peak current capability of the AD856x family. 100 90 CH 2 = 100mA/DIV CH 1 = 5V/DIV 10 0% 300 8V INPUT 0V TO 8V SQUARE WAVE WITH 15.6s PULSE WIDTH TIME (2s/DIV) 3k 10 10 10 Figure 6. Scope Photo of the VCOM Instantaneous Peak Current 10 4V MEASURE CURRENT 10nF 10nF 10nF 10nF 10-20 Figure 5. VCOM Test Circuit with Supply Voltage at 16 V -10- REV. C AD8565/AD8566/AD8567 OUTLINE DIMENSIONS 5-Lead Thin Shrink Small Outline Transistor Package [SC70] (KS-5) 8-Lead Micro Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters Dimensions shown in millimeters 3.00 BSC 2.00 BSC 4 5 1.25 BSC 8 2.10 BSC 1 2 5 4.90 BSC 3.00 BSC 3 1 4 PIN 1 0.65 BSC 1.00 0.90 0.70 0.10 MAX PIN 1 1.10 MAX 0.65 BSC 0.22 0.08 0.30 0.15 0.10 COPLANARITY 0.46 0.36 0.26 SEATING PLANE 1.10 MAX 0.15 0.00 0.38 0.22 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-203AA 0.23 0.08 8 0 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-187AA 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters 5.10 5.00 4.90 14 8 4.50 4.40 4.30 6.40 BSC 1 7 PIN 1 1.05 1.00 0.80 0.65 BSC 1.20 MAX 0.15 0.05 0.30 0.19 0.20 0.09 SEATING COPLANARITY PLANE 0.10 8 0 COMPLIANT TO JEDEC STANDARDS MO-153AB-1 REV. C -11- 0.75 0.60 0.45 0.80 0.60 0.40 AD8565/AD8566/AD8567 OUTLINE DIMENSIONS 16-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm x 4 mm Body (CP-16) 4.0 BSC SQ PIN 1 INDICATOR 0.60 MAX 13 12 3.75 BSC SQ TOP VIEW 0.75 0.60 0.50 12 MAX PIN 1 INDICATOR 0.60 MAX 0.65 BSC C01909-0-3/04(C) Dimensions shown in millimeters 16 1 BOTTOM VIEW 2.25 2.10 SQ 1.95 4 9 8 5 0.25 MIN 1.95 BSC 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 1.00 0.85 0.80 SEATING PLANE 0.35 0.28 0.25 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VGGC Revision History Location Page 3/04--Data Sheet changed from REV. B to REV. C. Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Changes to TPC 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Changes to TPC 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Changes to TPC 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Changes to TPC 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 12/03--Data Sheet changed from REV. A to REV. B. Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 10/01--Data Sheet changed from REV. 0 to REV. A. Edit to 16-Lead CSP and 5-Lead SC70 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Edit to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 -12- REV. C