KAI-04022 2048 (H) x 2048 (V) Interline CCD Image Sensor Description The KAI-04022 Image Sensor is a high-performance 4-million pixel sensor designed for a wide range of medical, scientific and machine vision applications. The 7.4 mm square pixels with microlenses provide high sensitivity and the large full well capacity results in high dynamic range. The two high-speed outputs and binning capabilities allow for 16-50 frames per second (fps) video rate for the progressively scanned images. The vertical overflow drain structure provides anti-blooming protection and enables electronic shuttering for precise exposure control. Other features include low dark current, negligible lag and low smear. www.onsemi.com Table 1. GENERAL SPECIFICATIONS Parameter Typical Value Architecture Interline CCD, Progressive Scan Total Number of Pixels 2112 (H) x 2072 (V) Number of Effective Pixels 2056 (H) x 2062 (V) Number of Active Pixels 2048 (H) x 2048 (V) Features Pixel Size 7.4 mm (H) x 7.4 mm (V) Active Image Size 15.15 mm (H) x 15.15 mm (V), 21.43 mm (Diagonal), 4/3 Optical Format Aspect Ratio 1:1 Number of Outputs 1 or 2 Charge Capacity 40,000 e- Output Sensitivity 33 mV/e- * * * * * * * Peak Quantum Efficiency KAI-04022-ABA KAI-04022-FBA (BRG) KAI-04022-CBA (BRG) 50% 44%, 42%, 36% 45%, 42%, 35% Read Noise (f = 10 MHz) 9 e-, rms Dark Current < 0.5 nA/cm2 Dark Current Doubling Temp. 7C Dynamic Range 72 dB Charge Transfer Efficiency > 0.999999 Blooming Suppression 300X Smear -80 dB Image Lag < 10 e- Maximum Frame Rates 8 fps (Single Output) 16 fps (Single Output) Package 34-pin, CERDIP Cover Glass AR Coated, 2-Side Figure 1. KAI-04022 Interline CCD Image Sensor High Resolution High Sensitivity High Dynamic Range Low Noise Architecture High Frame Rate Binning Capability for Higher Frame Rate Electronic Shutter Applications * * * * Intelligent Transportation Systems Machine Vision Scientific Imaging Surveillance ORDERING INFORMATION See detailed ordering and shipping information on page 2 of this data sheet. NOTE: All Parameters are specified at T = 40C unless otherwise noted. (c) Semiconductor Components Industries, LLC, 2015 August, 2015 - Rev. 2 1 Publication Order Number: KAI-04022/D KAI-04022 ORDERING INFORMATION Table 2. ORDERING INFORMATION - KAI-04022 IMAGE SENSOR Part Number Description KAI-04022-AAA-CR-BA Monochrome, No Microlens, CERDIP Package (Sidebrazed), Taped Clear Cover Glass with AR Coating (2 Sides), Standard Grade KAI-04022-AAA-CR-AE Monochrome, No Microlens, CERDIP Package (Sidebrazed), Taped Clear Cover Glass with AR Coating (2 Sides), Engineering Grade KAI-04022-ABA-CD-BA Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed), Clear Cover Glass with AR Coating (2 Sides), Standard Grade KAI-04022-ABA-CD-AE Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed), Clear Cover Glass with AR Coating (2 Sides), Engineering Grade KAI-04022-ABA-CR-BA Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed), Taped Clear Cover Glass with AR Coating (2 Sides), Standard Grade KAI-04022-ABA-CR-AE Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed), Taped Clear Cover Glass with AR Coating (2 Sides), Engineering Grade KAI-04022-FBA-CD-BA Color (Bayer RGB), Telecentric Microlens, CERDIP Package (Sidebrazed), Clear Cover Glass with AR Coating (2 Sides), Standard Grade KAI-04022-FBA-CD-AE Color (Bayer RGB), Telecentric Microlens, CERDIP Package (Sidebrazed), Clear Cover Glass with AR Coating (2 Sides), Engineering Grade KAI-04022-FBA-CR-BA Color (Bayer RGB), Telecentric Microlens, CERDIP Package (Sidebrazed), Taped Clear Cover Glass with AR Coating (2 Sides), Standard Grade KAI-04022-FBA-CR-AE Color (Bayer RGB), Telecentric Microlens, CERDIP Package (Sidebrazed), Taped Clear Cover Glass with AR Coating (2 Sides), Engineering Grade KAI-04022-CBA-CD-BA* Color (Bayer RGB), Telecentric Microlens, CERDIP Package (Sidebrazed), Clear Cover Glass with AR Coating (2 Sides), Standard Grade KAI-04022-CBA-CD-AE* Color (Bayer RGB), Telecentric Microlens, CERDIP Package (sidebrazed), Clear Cover Glass with AR Coating (2 Sides), Engineering Grade KAI-04022-CBA-CR-BA* Color (Bayer RGB), Telecentric Microlens, CERDIP Package (sidebrazed), Taped Clear Cover Glass with AR Coating (2 Sides), Standard Grade KAI-04022-CBA-CR-AE* Color (Bayer RGB), Telecentric Microlens, CERDIP Package (sidebrazed), Taped Clear Cover Glass with AR Coating (2 Sides), Engineering Grade Marking Code KAI-04022-AAA Serial Number KAI-04022-ABA Serial Number KAI-04022-FBA Serial Number KAI-04022-CBA Serial Number *Not recommended for new designs. See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at www.onsemi.com. www.onsemi.com 2 KAI-04022 DEVICE DESCRIPTION Architecture B G G R B G G R 8 Buffer Rows Single or Dual Output 28 Dark Columns 4 Buffer Columns 2048 (H) x 2048 (H) Active Pixels B G G R 12 Dummy Pixels Pixel 1,1 12 Dummy Pixels Video L B G G R 4 Buffer Columns 28 Dark Columns B G G R B G G R 6 Buffer Rows B G G R B G G R 10 Dark Rows 12 28 4 12 28 4 2048 1024 1024 4 28 12 4 28 12 Video R Figure 2. Sensor Architecture out Video R. Each row consists of 12 empty pixels followed by 28 light shielded pixels followed by 1,028 photosensitive pixels. When reconstructing the image, data from Video R will have to be reversed in a line buffer and appended to the Video L data. There are no dark reference rows at the top and 10 dark rows at the bottom of the image sensor. The 10 dark rows are not entirely dark and so should not be used for a dark reference level. Use the 28 dark columns on the left or right side of the image sensor as a dark reference. Of the 28 dark columns, the first and last dark columns should not be used for determining the zero signal level. Some light does leak into the first and last dark columns. Only use the center 26 columns of the 28 column dark reference. There are 10 light shielded rows followed 2,062 photoactive rows. The first 6 and the last 8 photoactive rows are buffer rows giving a total of 2,048 lines of image data. In the single output mode all pixels are clocked out of the Video L output in the lower left corner of the sensor. The first 12 empty pixels of each line do not receive charge from the vertical shift register. The next 28 pixels receive charge from the left light-shielded edge followed by 2,056 photo-sensitive pixels and finally 28 more light shielded pixels from the right edge of the sensor. The first and last 4 photosensitive pixels are buffer pixels giving a total of 2,048 pixels of image data. In the dual output mode the clocking of the right half of the horizontal CCD is reversed. The left half of the image is clocked out Video L and the right half of the image is clocked www.onsemi.com 3 KAI-04022 Pixel EEEEEEEEE EEEEE EEEEEEEEE EEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEE EEEEEEEEE EEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE Top View Direction of Charge Transfer Cross Section Down Through VCCD V1 V2 V1 7.4 mm V1 Photodiode Transfer Gate EE EE EE EE n- V2 n- EE EE n- n p Well (GND) Direction of Charge Transfer 7.4 mm n Substrate True Two Phase Burried Channel VCCD Lightshield over VCCD not shown Cross Section Through Photodiode and VCCD Phase 1 Cross Section Through Photodiode and VCCD Phase 2 at Transfer Gate Light Shield Light Shield E E p Photodiode EE IIIIIII E EE EEIIIIIIIE EE V1 p+ n p n Transfer Gate p+ p p n p IIIIII EE IIIIIIEE V2 n p p p n Substrate n Substrate NOTE: Drawings not scale. p Cross Section Showing Lenslet Lenslet Red Color Filter Light Shield Light Shield VCCD VCCD Photodiode Figure 3. Pixel Architecture An electronic representation of an image is formed when incident photons falling on the sensor plane create electron-hole pairs within the individual silicon photodiodes. These photoelectrons are collected locally by the formation of potential wells at each photosite. Below photodiode saturation, the number of photoelectrons collected at each pixel is linearly dependent upon light level and exposure time and non-linearly dependent on wavelength. When the photodiodes charge capacity is reached, excess electrons are discharged into the substrate to prevent blooming. www.onsemi.com 4 KAI-04022 Vertical to Horizontal Transfer EEEEEEEEEE EEEEEE EEEEEEEEEE EEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEE EEEEEEEEEE EEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEE EEEEEEEEEE EEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEE EEEEEE EE EE EE EE EE EE EE EE EE EE EE EE EE EE Top View Direction of Vertical Charge Transfer V1 Photodiode Transfer Gate V2 V1 Fast Line Dump V2 H2B H2S H1B Lightshield Not Shown H1S Direction of Horizontal Charge Transfer Figure 4. Vertical to Horizontal Transfer Architecture When the V1 and V2 timing inputs are pulsed, charge in every pixel of the VCCD is shifted one row towards the HCCD. The last row next to the HCCD is shifted into the HCCD. When the VCCD is shifted, the timing signals to the HCCD must be stopped. H1 must be stopped in the high state and H2 must be stopped in the low state. The HCCD clocking may begin tHD ms after the falling edge of the V1 and V2 pulse. Charge is transferred from the last vertical CCD phase into the H1S horizontal CCD phase. Refer to Figure 36 for an example of timing that accomplishes the vertical to horizontal transfer of charge. If the fast line dump is held at the high level (FDH) during a vertical to horizontal transfer, then the entire line is removed and not transferred into the horizontal register. www.onsemi.com 5 KAI-04022 Horizontal Register to Floating Diffusion RD R n+ n OG n+ Floating Diffusion H2S H2B H1S III H1B H2S IIII n- n- n (burried channel) H2B H1S IIII n- p (GND) n (SUB) Figure 5. Horizontal Register to Floating Diffusion Architecture fast line dump (FD) should be not be pulsed. This prevents unwanted noise from being introduced. The HCCD is a type of charge coupled device known as a pseudo-two phase CCD. This type of CCD has the ability to shift charge in two directions. This allows the entire image to be shifted out to the video L output, or to the video R output (left/right image reversal). The HCCD is split into two equal halves of 1,068 pixels each. When operating the sensor in single output mode the two halves of the HCCD are shifted in the same direction. When operating the sensor in dual output mode the two halves of the HCCD are shifted in opposite directions. The direction of charge transfer in each half is controlled by the H1BL, H2BL, H1BR, and H2BR timing inputs. The HCCD has a total of 2,124 pixels. The 2,112 vertical shift registers (columns) are shifted into the center 2,112 pixels of the HCCD. There are 12 pixels at both ends of the HCCD, which receive no charge from a vertical shift register. The first 12 clock cycles of the HCCD will be empty pixels (containing no electrons). The next 28 clock cycles will contain only electrons generated by dark current in the VCCD and photodiodes. The next 2,056 clock cycles will contain photo-electrons (image data). Finally, the last 28 clock cycles will contain only electrons generated by dark current in the VCCD and photodiodes. Of the 28 dark columns, the first and last dark columns should not be used for determining the zero signal level. Some light does leak into the first and last dark columns. Only use the center 26 columns of the 28 column dark reference. When the HCCD is shifting valid image data, the timing inputs to the electronic shutter (SUB), VCCD (V1, V2), and www.onsemi.com 6 KAI-04022 Horizontal Register Split H1 H2 H2 H1 H1 H2 H2 H1BL H2SL H2BL H1SL H1BL H2SL H1BR Pixel 1068 H1 H1SR H1 H2 H2BR H2SR Pixel 1069 Single Output H1 H2 H2 H1 H1 H2 H1 H1 H2 H2 H1BL H2SL H2BL H1SL H1BL H2SL H1BR H1SR H2BR H2SR Pixel 1068 Pixel 1068 Dual Output Figure 6. Horizontal Register change the direction of charge transfer of the right side horizontal shift register. In dual output mode both VDDL and VDDR (pins 11, 24) should be connected to 15 V. The H1 timing from the timing diagrams should be applied to H1SL, H1BL, H1SR, H1BR, and the H2 timing should be applied to H2SL, H2BL, H2SR, and H2BR. The clock driver generating the H1 timing should be connected to pins 16, 15, 19, and 20. The clock driver generating the H2 timing should be connected to pins 17, 14, 18, and 21. The horizontal CCD should be clocked for 12 empty pixels plus 28 light shielded pixels plus 1,028 photoactive pixels for a total of 1,068 pixels. If the camera is to have the option of dual or single output mode, the clock driver signals sent to H1BR and H2BR may be swapped by using a relay. Another alternative is to have two extra clock drivers for H1BR and H2BR and invert the signals in the timing logic generator. If two extra clock drivers are used, care must be taken to ensure the rising and falling edges of the H1BR and H2BR clocks occur at the same time (within 3 ns) as the other HCCD clocks. Single Output Operation When operating the sensor in single output mode all pixels of the image sensor will be shifted out the Video L output (pin 12). To conserve power and lower heat generation the output amplifier for Video R may be turned off by connecting VDDR (pin 24) and VOUTR (pin 23) to GND (0 V). The H1 timing from the timing diagrams should be applied to H1SL, H1BL, H1SR, H2BR, and the H2 timing should be applied to H2SL, H2BL, H2SR, and H1BR. In other words, the clock driver generating the H1 timing should be connected to pins 16, 15, 19, and 21. The clock driver generating the H2 timing should be connected to pins 17, 14, 18, and 20. The horizontal CCD should be clocked for 12 empty pixels plus 28 light shielded pixels plus 2,056 photoactive pixels plus 28 light shielded pixels for a total of 2,124 pixels. Dual Output Operation In dual output mode the connections to the H1BR and H2BR pins are swapped from the single output mode to www.onsemi.com 7 KAI-04022 Output H2B H2S HCCD Charge Transfer H1B H1S H2B H2S VDD OG R RD Floating Diffusion VOUT Source Follower #1 Source Follower #2 Source Follower #3 Figure 7. Output Architecture This means a full signal of 20,000 electrons will produce a 640 mV change on the output amplifier. The output amplifier was designed to handle an output swing of 640 mV at a pixel rate of 40 MHz. If 40,000 electron charge packets are generated in the binned or summed interlaced modes then the output amplifier output will have to swing 1,280 mV. The output amplifier does not have enough bandwidth (slew rate) to handle 1,280 mV at 40 MHz. Hence, the pixel rate will have to be reduced to 20 MHz if the full dynamic range of 40,000 electrons is desired. The charge handling capacity of the output amplifier is also set by the reset clock voltage levels. The reset clock driver circuit is very simple, if an amplitude of 5 V is used. But the 5 V amplitude restricts the output amplifier charge capacity to 20,000 electrons. If the full dynamic range of 40,000 electrons is desired then the reset clock amplitude will have to be increased to 7 V. Charge packets contained in the horizontal register are dumped pixel by pixel onto the floating diffusion (FD) output node whose potential varies linearly with the quantity of charge in each packet. The amount of potential charge is determined by the expression DVFD = DQ / CFD. A three-stage source-follower amplifier is used to buffer this signal voltage off chip with slightly less than unity gain. The translation from the charge domain to the voltage domain is quantified by the output sensitivity or charge to voltage conversion in terms of microvolts per electron (mV/e-). After the signal has been sampled off chip, the reset clock (R) removes the charge from the floating diffusion and resets its potential to the reset drain voltage (RD). When the image sensor is operated in the binned or summed interlaced modes there will be more than 20,000 electrons in the output signal. The image sensor is designed with a 31 mV/e charge to voltage conversion on the output. www.onsemi.com 8 KAI-04022 The following table summarizes the previous explanation on the output amplifier's operation. Certain trade-offs can be made based on application needs such as Dynamic Range or Pixel frequency. If you only want a maximum signal of 20,000 electrons in binned or summed interlaced modes, then a 40 MHz pixel rate with a 5 V reset clock may be used. The output of the amplifier will be unpredictable above 20,000 electrons so be sure to set the maximum input signal level of your analog to digital converter to the equivalent of 20,000 electrons (640 mV). Table 3. OUTPUT AMPLIFIER'S OPERATION Pixel Frequency (MHz) Reset Clock Amplitude (V) Output Gate (V) Saturation Signal (mV) Saturation Signal (ke-) 40 5 -2 640 20 20 5 -2 640 20 20 7 -3 1280 40 20 7 -3 2560 80 Notes 1 1. 80,000 electrons achievable in summed interlaced or binning modes. ESD Protection D2 D2 RL D2 H1SL D2 D2 H2SL H1BL D2 H2BL OGL ESD D1 VSUB D2 D2 RR D2 H1SR D2 D2 H2SR H1BR D2 H2BR OGR Figure 8. ESD Protection to forward bias these junctions then diodes D1 and D2 should be added to protect the image sensor. Put one diode D1 between the ESD and VSUB pins. Put one diode D2 on each pin that may forward bias the base-emitter junction. The diodes will prevent large currents from flowing through the image sensor. Note that external diodes D1 and D2 are optional and are only needed if it is possible to forward bias any of the junctions. Note that diodes D1 and D2 are added external to the KAI-04022. The ESD protection on the KAI-04022 is implemented using bipolar transistors. The substrate (VSUB) forms the common collector of all the ESD protection transistors. The ESD pin is the common base of all the ESD protection transistors. Each protected pin is connected to a separate emitter as shown in Figure 8. The ESD circuit turns on if the base-emitter junction voltage exceeds 17 V. Care must be taken while operating the image sensor, especially during the power on sequence, to not forward bias the base-emitter or base-collector junctions. If it is possible for the camera power up sequence www.onsemi.com 9 KAI-04022 Pin Description and Physical Orientation SUB 1 34 GND V2E 2 33 V2E V2O 3 32 V2O V1E 4 31 V1E V1O 5 30 V1O ESD 6 29 SUB GND 7 28 FD OGL 8 27 OGR GND 9 26 GND RDL 10 25 RDR VDDL 11 24 VDDR VOUTL 12 23 VOUTR RL 13 22 RR H2BL 14 21 H2BR H1BL 15 20 H1BR H1SL 16 19 H1SR H2SL 17 18 H2SR Pixel 1,1 Figure 9. Package Pin Description- Top View Table 4. PIN DESCRIPTION Pin Name Pin Name 1 SUB Substrate 18 H2SR H2 Storage, Right 2 V2E Vertical Clock, Phase 2, Even 19 H1SR H1 Storage, Right 3 V2O Vertical Clock, Phase 2, Odd 20 H1BR H1 Barrier, Right 4 V1E Vertical Clock, Phase 1, Even 21 H2BR H2 Barrier, Right 5 V1O Vertical Clock, Phase 1, Odd 22 RR Reset Gate, Right 6 ESD ESD 23 VOUTR 7 GND Ground 24 VDDR 8 OGL Output Gate, Left 25 RDR Reset Drain, Right 9 GND Ground 26 GND Ground 10 RDL Reset Drain, Left 27 OGR Output Gate. Right VDD, Left 28 FD Video Output, Left 29 SUB Substrate 11 VDDL 12 VOUTL Description Description Video Output. Right VDD, Right Fast Line Dump Gate 13 RL Reset Gate, Left 30 V1O Vertical Clock, Phase 1, Odd 14 H2BL H2 Barrier, Left 31 V1E Vertical Clock, Phase 1, Even 15 H1BL H1 Barrier, Left 32 V2O Vertical Clock, Phase 2, Odd 16 H1SL H1 Storage, Left 33 V2E Vertical Clock, Phase 2, Even 17 H2SL H2 Storage, Left 34 GND Ground NOTE: The pins are on a 0.070 spacing. www.onsemi.com 10 KAI-04022 IMAGING PERFORMANCE Table 5. TYPICAL OPERATIONAL CONDITIONS (Unless otherwise noted, the Imaging Performance Specifications are measured using the following conditions.) Condition Description Frame Time (Note 1) 538 ms Horizontal Clock Frequency 10 MHz Light Source (Notes 2, 3) Continuous Red, Green and Blue LED Illumination Centered at 450, 530 and 650 nm Operation Nominal Operating Voltages and Timing 1. Electronic shutter is not used. Integration time equals frame time. 2. LEDs used: Blue: Nichia NLPB500, Green: Nichia NSPG500S and Red: HP HLMP-8115. 3. For monochrome sensor, only green LED used. Specifications Table 6. PERFORMANCE SPECIFICATIONS Temperature Tested at (5C) Min. Nom. Max. Unit Sample Plan Dark Center Non-Uniformity N/A N/A 2 mV rms Die 27, 40 Dark Global Non-Uniformity N/A N/A 5.0 m Vpp Die 27, 40 Global Non-Uniformity (Note 1) N/A 2.5 5.0 % rms Die 27, 40 N/A 10 20 % pp Die 27, 40 N/A 1.0 2.0 % rms Die 27, 40 Description Symbol ALL CONFIGURATIONS Global Peak to Peak Non-Uniformity (Note 1) PRNU Center Non-Uniformity (Note 1) Maximum Photoresponse Non-Linearity (Notes 2, 3) NL N/A 2 - % Design Maximum Gain Difference Between Outputs (Notes 2, 3) G N/A 10 - % Design Max. Signal Error due to Non-Linearity Dif. (Notes 2, 3) NL N/A 1 - % Design Horizontal CCD Charge Capacity HNe - 100 - ke- Design Vertical CCD Charge Capacity VNe 50 60 - ke- Die Photodiode Charge Capacity PNe 38 40 - ke- Die Horizontal CCD Charge Transfer Efficiency HCTE 0.99999 - N/A Vertical CCD Charge Transfer Efficiency VCTE 0.99999 - N/A Photodiode Dark Current IPD N/A 40 Design Design 350 e-/p/s Die Die Photodiode Dark Current IPD N/A 0.01 0.1 nA/cm2 Vertical CCD Dark Current IVD N/A 400 1711 e-/p/s Die Vertical CCD Dark Current IVD N/A 0.12 0.5 nA/cm2 Die e- Design Image Lag Lag N/A < 10 50 Anti-Blooming Factor XAB 100 300 N/A Vertical Smear Smr N/A -80 -75 dB Design Read Noise (Note 4) ne-T - 9 - e- rms Dynamic Range (Notes 4, 5) DR - 72 - dB Design Output Amplifier DC Offset VODC 4 8.5 14 V Die Output Amplifier Bandwidth f-3dB - 140 - MHz Design www.onsemi.com 11 KAI-04022 Table 6. PERFORMANCE SPECIFICATIONS (continued) Symbol Min. Nom. Max. Unit Sample Plan Output Amplifier Impedance ROUT 100 130 200 W Die Output Amplifier Sensitivity V/N - 31 - mV/e- Design QEMAX - 55 - % Design lQE - 470 - nm Design % Design - - - 36 42 44 - - - nm Design - - - 605 530 455 - - - % Design - - - 35 42 45 - - - nm Design - - - 620 540 470 - - - Description ALL CONFIGURATIONS KAI-04022-ABA CONFIGURATION Peak Quantum Efficiency Peak Quantum Efficiency Wavelength KAI-04022-FBA GEN2 COLOR CONFIGURATIONS Peak Quantum Efficiency Red Green Blue Peak Quantum Efficiency Wavelength Red Green Blue QEMAX lQE KAI-04022-CBA GEN1 COLOR CONFIGURATIONS (Note 6) Peak Quantum Efficiency Red Green Blue Peak Quantum Efficiency Wavelength Red Green Blue QEMAX lQE NOTE: N/A = Not Applicable. 1. Per color. 2. Value is over the range of 10% to 90% of photodiode saturation. 3. Value is for the sensor operated without binning. 4. At 10 MHz. 5. Uses 20LOG (PNe / ne-T). 6. This color filter set configuration (Gen1) is not recommended for new designs. www.onsemi.com 12 Temperature Tested at (5C) KAI-04022 TYPICAL PERFORMANCE CURVES Quantum Efficiency Monochrome with Microlens 0.6 Measured with AR Coated Cover Glass Absolute Quantum Efficiency 0.5 0.4 0.3 0.2 0.1 0.0 300 400 500 600 700 800 900 1000 Wavelength (nm) Figure 10. Monochrome with Microlens Quantum Efficiency Monochrome without Microlens 0.12 Absolute Quantum Efficiency 0.10 0.08 0.06 0.04 0.02 0.00 240 340 440 540 640 740 840 Wavelength (nm) Figure 11. Monochrome without Microlens Quantum Efficiency www.onsemi.com 13 940 KAI-04022 Color (Bayer RGB) with Microlens Figure 12. Color Quantum Efficiency Angular Quantum Efficiency For the curves marked "Horizontal", the incident light angle is varied in a plane parallel to the HCCD. For the curves marked "Vertical", the incident light angle is varied in a plane parallel to the VCCD. Monochrome with Microlens 100 Relative Quantum Efficiency (%) 90 80 Horizontal 70 60 50 Vertical 40 30 20 10 0 -30 -20 -10 0 10 20 Angle (degress) Figure 13. Monochrome with Microlens Angular Quantum Efficiency www.onsemi.com 14 30 KAI-04022 Dark Current vs. Temperature 100000 10000 Electrons/Second VCCD 1000 100 Photodiodes 10 1 1000/T(K) 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 T (C) 97 84 72 60 50 40 30 21 Figure 14. Dark Current vs. Temperature Power-Estimated Right Output Disabled 400 350 Output Power One Output (mW) Vertical Power One Output (mW) Power (mW) 300 Horizonatl Power (mW) Total Power One Output (mW) 250 200 150 100 50 0 0 5 10 15 20 Horizontal Clock Frequency (MHz) Figure 15. Power www.onsemi.com 15 25 30 KAI-04022 Frame Rates 30 Dual 2x2 Binning Frame Rate (fps) 25 20 Dual Output or or Single 2x2 Binning 15 Single output 10 5 0 10 15 20 25 Pixel Clock (MHz) Figure 16. Frame Rates www.onsemi.com 16 30 35 40 KAI-04022 DEFECT DEFINITIONS Table 7. DEFECT DEFINITIONS Definition Maximum Temperature(s) Tested at (5C) Major Dark Field Defective Pixel (Note 1) Defect 148 mV 40 27, 40 Major Bright Field Defective Pixel (Note 1) Defect 10% 40 27, 40 Minor Dark Field Defective Pixel Defect 76 mV 400 27, 40 Description Defect 80% 5 27, 40 Saturated Pixel (Note 1) Defect 340 mV 10 27, 40 Cluster Defect (Note 1) A group of 2 to 10 contiguous major defective pixels, but no more than 2 adjacent defects horizontally 8 27, 40 Column Defect (Note 1) A group of more than 10 contiguous major defective pixels along a single column 0 27, 40 Dead Pixel (Note 1) 1. There will be at least two non-defective pixels separating any two major defective pixels. Defect Map The defect map supplied with each sensor is based upon testing at an ambient (27C) temperature. Minor point defects are not included in the defect map. All defective pixels are reference to pixel 1,1 in the defect maps. www.onsemi.com 17 KAI-04022 TEST DEFINITIONS Test Regions of Interest Overclocking Active Area ROI: Pixel (1, 1) to Pixel (2048, 2048) Center 100 by 100 ROI: Pixel (974, 974) to Pixel (1073, 1073) The test system timing is configured such that the sensor is overclocked in both the vertical and horizontal directions. See Figure 17 for a pictorial representation of the regions. Only the active pixels are used for performance and defect tests. H Horizontal Overclock Pixel 1,1 V Vertical Overclock Figure 17. Overclock Regions of Interest Tests Dark Field Center Non-Uniformity This test is performed under dark field conditions. Only the center 100 by 100 pixels of the sensor are used for this test - pixel (974, 974) to pixel (1073, 1073). Where i = 1 to 256. During this calculation on the 256 sub regions of interest, the maximum and minimum signal levels are found. The dark field global non-uniformity is then calculated as the maximum signal found minus the minimum signal level found. Dark Field Center Non-Uniformity + Standard Deviation of Center 100 by 100 Pixels Global Non-Uniformity This test is performed with the imager illuminated to a level such that the output is at 70% of saturation (approximately 868 mV). Prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 1,240 mV. Global non-uniformity is defined as: Units : mV rms Dark Field Global Non-Uniformity This test is performed under dark field conditions. The sensor is partitioned into 256 sub regions of interest, each of which is 128 by 128 pixels in size. The average signal level of each of the 256 sub regions of interest is calculated. The signal level of each of the sub regions of interest is calculated using the following formula: Global Non-Uniformity + 100 @ Active Area Standard Deviation Active Area Signal Units : % rms Active Area Signal = Active Area Average - H. Column Average Signal of ROI[i] + (ROI Average in ADU * * Horizontal Overclock Average in ADU) @ @ mV per Count Units : mVpp (millivolts Peak to Peak) www.onsemi.com 18 KAI-04022 Global Peak to Peak Non-Uniformity This test is performed with the imager illuminated to a level such that the output is at 70% of saturation (approximately 868 mV). Prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 1,240 mV. The sensor is partitioned into 256 sub regions of interest, each of which is 128 by 128 pixels in size. The average signal level of each of the 256 sub regions of interest (ROI) is calculated. The signal level of each of the sub regions of interest is calculated using the following formula: Bright Field Defect Test This test is performed with the imager illuminated to a level such that the output is at 70% of saturation (approximately 28,000 electrons). Prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 40,000 electrons. The average signal level of all active pixels is found. The bright and dark thresholds are set as: A[i] + (ROI Average * Horizontal Overclock Average) The sensor is then partitioned into 256 sub regions of interest, each of which is 128 by 128 pixels in size. In each region of interest, the average value of all pixels is found. For each region of interest, a pixel is marked defective if it is greater than or equal to the median value of that region of interest plus the bright threshold specified or if it is less than or equal to the median value of that region of interest minus the dark threshold specified. Example for major bright field defective pixels: * Average value of all active pixels is found to be 868 mV (28,000 electrons) * Dark defect threshold: 868 mV 15% = 130.2 mV * Bright defect threshold: 868 mV 15% = 130.2 mV * Region of interest #1 selected. This region of interest is pixels 1,1 to pixels 128,128 Median of this region of interest is found to be 868 mV. Any pixel in this region of interest that is (868 + 130.2 mV) 998.2 mV in intensity will be marked defective. Any pixel in this region of interest that is (868 - 130.2 mV) 737.8 mV in intensity will be marked defective. * All remaining 255 sub-regions of interest are analyzed for defective pixels in the same manner Dark Defect Threshold = Active Area Signal @ Threshold Bright Defect Threshold = Active Area Signal @ Threshold Where i = 1 to 256. During this calculation on the 256 sub regions of interest, the maximum and minimum average signal levels are found. The global peak to peak non-uniformity is then calculated as: Global Non-Uniformity + 100 @ A[i] Max. Signal * A[i] Min. Signal Active Area Signal Units : % pp Active Area Signal = Active Area Average - H. Column Average Center Non-Uniformity This test is performed with the imager illuminated to a level such that the output is at 70% of saturation (approximately 868 mV). Prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 1,240 mV. Defects are excluded for the calculation of this test. This test is performed on the center 100 by 100 pixels (See Test Regions of Interest ) of the sensor. Center non-uniformity is defined as: Center ROI Non-Uniformity + 100 @ Center ROI Standard Deviation Center ROI Signal Units : % rms Center ROI Signal = Center ROI Average -H. Colum Average Dark Field Defect Test This test is performed under dark field conditions. The sensor is partitioned into 256 sub regions of interest, each of which is 128 by 128 pixels in size. In each region of interest, the median value of all pixels is found. For each region of interest, a pixel is marked defective if it is greater than or equal to the median value of that region of interest plus the defect threshold specified in "Defect Definitions" section. www.onsemi.com 19 KAI-04022 OPERATION Absolute Maximum Ratings Absolute maximum rating is defined as a level or condition that should not be exceeded at any time per the description. If the level or the condition is exceeded, the device will be degraded and may be damaged. Table 8. ABSOLUTE MAXIMUM RATINGS Description Symbol Minimum Maximum Unit Operating Temperature (Note 1) TOP -50 70 C Humidity (Note 2) RH 5 90 % Output Bias Current (Note 3) IOUT 0.0 10 mA CL - 10 pF Off-Chip Load (Note 4) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Noise performance will degrade at higher temperatures. 2. T = 25C. Excessive humidity will degrade MTTF. 3. Each output. See Figure 18. Note that the current bias affects the amplifier bandwidth. 4. With total output load capacitance of CL = 10 pF between the outputs and AC ground. Table 9. MAXIMUM VOLTAGE RATINGS BETWEEN PINS Description RL, RR, H1S, H2S, H1BL, H2BL, H1BR, H2BR, OGR, OGL to ESD Pin to Pin with ESD Protection (Note 1) VDDL, VDDR to GND Minimum Maximum Unit 0 17 V -17 17 V 0 25 V 1. Pins with ESD protection are: RL, RR, H1S, H2S, H1BL, H2BL, H1BR, H2BR, OGL, and OGR. www.onsemi.com 20 KAI-04022 Table 10. DC BIAS OPERATING CONDITIONS Symbol Minimum Nominal Maximum Unit Maximum DC Current Output Gate (Notes 4, 5) OG -3.0 -2.0 -1.5 V 1 mA Reset Drain (Note 4) RD 11.5 12.0 12.5 V 1 mA Output Amplifier Supply (Note 3) VDD 14.5 15.0 15.5 V 1 mA Ground GND 0.0 0.0 0.0 V Substrate (Notes 1, 7) VSUB 8.0 VAB 17.0 V ESD Protection (Note 2) ESD -9.5 -9.0 -8.0 V Output Bias Current (Note 6) IOUT 0.0 5.0 10.0 mA Description 1. The operating value of the substrate voltage, VAB, will be marked on the shipping container for each device. The value VAB is set such that the photodiode charge capacity is 40,000 electrons. 2. VESD must be equal to FDL and more negative than H1L, H2L and RL during sensors operation AND during camera power turn on. 3. One output, unloaded. The maximum DC current is for one output unloaded and is shown as ISS in Figure 18. This is the maximum current that the first two stages of one output amplifier will draw. This value is with VOUT disconnected. 4. May be changed in future versions. 5. Output gate voltage level must be set to -3 V for 40,000 - 80,000 electrons output in summed interlaced or binning modes. 6. One output. 7. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions. VDD IDD Floating Diffusion IOUT VOUT ISS Source Follower #1 Source Follower #2 Figure 18. Output Architecture www.onsemi.com 21 Source Follower #3 KAI-04022 AC Operating Conditions Table 11. CLOCK LEVELS Description Symbol Minimum Nominal Maximum Unit V2H 8.5 9.0 9.5 V Vertical CCD Clocks Midlevel V1M, V2M -0.5 0.0 0.2 V Vertical CCD Clocks Low V1L, V2L -9.5 -9.0 -8.5 V Horizontal CCD Clocks High H1H, H2H 0.0 0.5 1.0 V Horizontal CCD Clocks Low H1L, H2L -5.0 -4.5 -4.0 V Vertical CCD Clock High Reset Clock Amplitude RH - 5.0 - V Reset Clock Low RL -3.5 -3.0 -2.5 V VSHUTTER 44 48 52 V Fast Dump High FDH 4 5 5 V Fast Dump Low (Note 1) FDL -9.5 -9.0 -8.0 V Electronic Shutter Voltage (Note 2) 1. Reset amplitude must be set to 7.0 V for 40,000 - 80,000 electrons output in summed interlaced or binning modes. 2. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions. Clock Line Capacitances V1E H1SL+H1BL 5 pF 20 pF 50 pF 25 pF V1O H2SL+H2BL 5 pF 20 pF 50 pF V2E H1SR+H1BR 5 pF 20 pF 50 pF 25 pF V2O H2SR+H2BR 5 pF 20 pF 50 pF GND GND Reset SUB FD 10 pF GND 4 nF GND 40 pF GND Figure 19. Clock Line Capacitances www.onsemi.com 22 KAI-04022 TIMING Table 12. TIMING REQUIREMENTS Description Symbol Minimum Nominal Maximum Unit tHD 1.3 1.5 10.0 ms VCCD Transfer Time tVCCD 1.3 1.5 20.0 ms Photodiode Transfer Time HCCD Delay tV3rd 3.0 5.0 15.0 ms VCCD Pedestal Time t3P 50.0 60.0 80.0 ms VCCD Delay t3D 10.0 20.0 80.0 ms Reset Pulse Time tR 2.5 5.0 - ns Shutter Pulse Time tS 3.0 4.0 10.0 ms Shutter Pulse Delay tSD 1.0 1.5 10.0 ms HCCD Clock Period (Note 1) tH 25.0 50.0 200.0 ns VCCD Rise/Fall Time tVR 0.0 0.1 1.0 ms Fast Dump Gate Delay tFD 0.5 - - ms Vertical Clock Edge Alignment tVE 0.0 - 100 ns 1. For operation at the minimum HCCD clock period (40 MHz), the substrate voltage will need to be raised to limit the signal at the output to 20,000 electrons. www.onsemi.com 23 KAI-04022 Timing Modes Progressive Scan Photodiode CCD Shift Register 7 6 5 4 3 2 1 0 Output HCCD Figure 20. Progressive Scan Operation In progressive scan read out every pixel in the image sensor is read out simultaneously. Each charge packet is transferred from the photodiode to the neighboring vertical CCD shift register simultaneously. The maximum useful signal output is limited by the photodiode charge capacity to 40,000 electrons. Vertical Frame Timing Line Timing Repeat for 2072 Lines Figure 21. Progressive Scan Flow Chart www.onsemi.com 24 KAI-04022 Summed Interlaced Scan 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 Even Field Odd Field Figure 22. Summed Interlaced Scan Operation image sensor two fields, even and odd, are read out. In the even field rows 0 + 1, 2 + 3, 4 + 5, ... are summed together. In the odd field rows 1 + 2, 3 + 4, 5 + 6, ... are summed together. The modulation transfer function (MTF) of the summed interlaced scan mode is less in the vertical direction than the progressive scan. But the dynamic range is twice that of progressive scan. The vertical MTF is better than a simple binning operation. In this mode the VCCD needs to be clocked for only 1,037 rows to read out each field. In the summed interlaced scan read out mode, charge from two photodiodes is summed together inside the vertical CCD. The clocking of the VCCD is such that one pixel occupies the space equivalent to two pixels in the progressive scan mode. This allows the VCCD to hold twice as many electrons as in progressive scan mode. Now the maximum useful signal is limited by the charge capacity of two photodiodes at 80,000 electrons. If only one field is read out of the image sensor the apparent vertical resolution will be 1,024 rows instead of the 2,048 rows in progressive scan (equivalent to binning). To recover the full resolution of the Summed Interlaced Even Frame Timing Summed Interlaced Odd Frame Timing Interlaced Line Timing Interlaced Line Timing Repeat for 1037 Lines Repeat for 1037 Lines Figure 23. Summed Interlaced Scan Flow Chart www.onsemi.com 25 KAI-04022 Non-Summed Interlaced Scan 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 Even Field Odd Field Figure 24. Non-Summed Interlaced Scan Operation maximum usable signal is still only 40,000 electrons. The large extra capacity of the VCCD causes the anti-blooming protection to be increased dramatically compared to the progressive scan. The vertical MTF is the same between the non-summed interlaced scan and progressive scan. There will be motion related artifacts in the images read out in the interlaced modes because the two fields are acquired at different times. In the non-summed interlaced scan mode only half the photodiode are read out in each field. In the even field rows 0, 2, 4, ... are transferred to the VCCD. In the odd field rows 1, 3, 5, ... are transferred to the VCCD. When the charge packet is transferred from a photodiode is occupies the equivalent of two rows in progressive scan mode. This allows the VCCD to hold twice as much charge a progressive scan mode. However, since only one photodiode for each row is transferred to the VCCD the Non-Summed Interlaced Even Frame Timing Non-Summed Interlaced Odd Frame Timing Interlaced Line Timing Interlaced Line Timing Repeat for 1037 Lines Repeat for 1037 Lines Figure 25. Non-Summed Interlaced Scan Flow Chart www.onsemi.com 26 KAI-04022 Frame Timing Frame Timing without Binning - Progressive Scan V1 tL tV3rd tL V2 Line 2071 Line 2072 t3P t3D Line 1 H1 H2 Figure 26. Frame Timing without Binning Frame Timing for Vertical Binning by 2 - Progressive Scan V1 tL tV3rd tL 3 x tVCCD V2 t3P Line 1035 t3D Line 1 Line 1036 H1 H2 Figure 27. Frame Timing for Vertical Binning by 2 www.onsemi.com 27 KAI-04022 Frame Timing Non-Summed Interlaced Scan (Even) V1M V1E V1L V2H V2M V2E V2L V1M V1O V1L V2M V2O V2L IIIIIIIIIII IIIIIIIIIII tV3rd H2 tV3rd tV3rd tVCCD Even Frame Timing Vertical Retrace Last Odd Line Readout IIII IIII Horizontal Retrace First Even Line Readout Figure 28. Non-Summed Interlaced Scan Even Frame Timing Frame Timing Non-Summed Interlaced Scan (Odd) V1M V1E V1L V2M V2E V2L V2M V1O V1L V2H V2O V2M V2L IIIIIIIIIII IIIIIIIIIII tV3rd H2 Last Even Line Readout tV3rd tV3rd Odd Frame Timing Vertical Retrace tVCCD IIII IIII Horizontal Retrace Figure 29. Non-Summed Interlaced Scan Odd Frame Timing www.onsemi.com 28 First Odd Line Readout KAI-04022 Frame Timing Summed Interlaced Scan (Even) V1M V1E V1L V2H V2M V2E V2L V1M V1O V1L V2H V2O Even Frame Timing Vertical Retrace IIII IIII tVCCD tVCCD IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII H2 Last Odd Line Readout V2L tVCCD tVCCD t3D tVCCD tV3rd tVCCD t3P tVCCD V2M Horizontal Retrace First Even Line Readout Figure 30. Summed Interlaced Scan Even Frame Timing Frame Timing Summed Interlaced Scan (Odd) V1M V1E V1L V2H V2M V2E V2L V1M V1O V1L V2H V2O t3D H2 Last Even Line Readout Odd Frame Timing Vertical Retrace Horizontal Retrace Figure 31. Summed Interlaced Scan Odd Frame Timing www.onsemi.com 29 IIII IIII IIII tVCCD tV3rd tVCCD IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII t3P V2L tVCCD tVCCD tVCCD tVCCD tVCCD V2M First Odd Line Readout KAI-04022 Frame Timing Edge Alignment V1M V1 V1L V2H V2M V2 tVE V2L Figure 32. Frame Timing Edge Alignment www.onsemi.com 30 KAI-04022 Line Timing Line Timing Single Output - Progressive Scan tL V1 tVCCD V2 tHD H1 H2 2122 2123 2124 2093 2094 2095 2096 2097 2098 39 40 41 42 43 44 11 12 13 14 Pixel Count 1 2 R Figure 33. Line Timing Single Output Line Timing Dual Output - Progressive Scan tL V1 tVCCD V2 tHD H1 H2 1058 1059 1060 1061 1062 1063 1064 1065 1067 1068 39 40 41 42 43 44 11 12 13 14 Pixel Count 1 2 R Figure 34. Line Timing Dual Output www.onsemi.com 31 KAI-04022 Line Timing Vertical Binning by 2 - Progressive Scan tL V1 3 x tVCCD V2 tHD H1 H2 Figure 35. Line Timing Vertical Binning by 2 Line Timing Detail - Progressive Scan V1 tVCCD V2 1/2 tH tHD H1 H2 R Figure 36. Line Timing Detail Line Timing Binning by 2 Detail - Progressive Scan V1 V2 1/2 tH tVCCD tVCCD tVCCD tHD H1 H2 R Figure 37. Line Timing by 2 Detail www.onsemi.com 32 2122 2123 2124 2093 2094 2095 2096 2097 2098 39 40 41 42 43 44 11 12 13 14 Pixel Count 1 2 R KAI-04022 Line Timing Binning Interlaced Modes V1E V2E V1O V2O H2 tVCCD Figure 38. Line Timing Interlaced Modes Line Timing Edge Alignment Applies to all modes. tVCCD V1 V2 tVE tVE Figure 39. Line Timing Edge Alignment www.onsemi.com 33 KAI-04022 Pixel Timing V1 V2 H1 H2 Pixel Count 11 1 13 12 39 40 41 R VOUT Dummy Pixels Light Shielded Pixels Photosensitive Pixels Figure 40. Pixel Timing Pixel Timing Detail tR RH R RL H1H H1 H1L H2H H2 H2L VOUT Figure 41. Pixel Timing Detail www.onsemi.com 34 KAI-04022 Fast Line Dump Timing fFD fV1 fV2 tFD tVCCD tFD tVCCD fH1 fH2 Figure 42. Fast Line Dump Timing www.onsemi.com 35 KAI-04022 Electronic Shutter Electronic Shutter Line Timing fV1 fV2 tVCCD tHD VSHUTTER tS VSUB tSD fH1 fH2 fR Figure 43. Electronic Shutter Line Timing Electronic Shutter - Integration Time Definition fV2 Integration Time VSHUTTER VSUB Figure 44. Integration Time Definition www.onsemi.com 36 KAI-04022 Electronic Shutter - DC and AC Bias Definition The figure below shows the DC bias (VSUB) and AC clock (VES) applied to the SUB pin. Both the DC bias and AC clock are referenced to ground. VSHUTTER SUB GND GND Figure 45. DC Bias and AC Clock Applied to the SUB Pin Electronic Shutter Description The voltage on the substrate (SUB) determines the charge capacity of the photodiodes. When SUB is 8 V the photodiodes will be at their maximum charge capacity. Increasing VSUB above 8 V decreases the charge capacity of the photodiodes until 48 V when the photodiodes have a charge capacity of zero electrons. Therefore, a short pulse on SUB, with a peak amplitude greater than 48 V, empties all photodiodes and provides the electronic shuttering action. It may appear the optimal substrate voltage setting is 8 V to obtain the maximum charge capacity and dynamic range. While setting VSUB to 8 V will provide the maximum dynamic range, it will also provide the minimum anti-blooming protection. The KAI-04022 VCCD has a charge capacity of 60,000 electrons (60 ke-). If the SUB voltage is set such that the photodiode holds more than 60 ke-, then when the charge is transferred from a full photodiode to VCCD, the VCCD will overflow. This overflow condition manifests itself in the image by making bright spots appear elongated in the vertical direction. The size increase of a bright spot is called blooming when the spot doubles in size. The blooming can be eliminated by increasing the voltage on SUB to lower the charge capacity of the photodiode. This ensures the VCCD charge capacity is greater than the photodiode capacity. There are cases where an extremely bright spot will still cause blooming in the VCCD. Normally, when the photodiode is full, any additional electrons generated by photons will spill out of the photodiode. The excess electrons are drained harmlessly out to the substrate. There is a maximum rate at which the electrons can be drained to the substrate. If that maximum rate is exceeded, (for example, by a very bright light source) then it is possible for the total amount of charge in the photodiode to exceed the VCCD capacity. This results in blooming. The amount of anti-blooming protection also decreases when the integration time is decreased. There is a compromise between photodiode dynamic range (controlled by VSUB) and the amount of anti-blooming protection. A low VSUB voltage provides the maximum dynamic range and minimum (or no) anti-blooming protection. A high VSUB voltage provides lower dynamic range and maximum anti-blooming protection. The optimal setting of VSUB is written on the container in which each KAI-04022 is shipped. The given VSUB voltage for each sensor is selected to provide anti-blooming protection for bright spots at least 100 times saturation, while maintaining at least 40 ke- of dynamic range. The electronic shutter provides a method of precisely controlling the image exposure time without any mechanical components. If an integration time of tINT is desired, then the substrate voltage of the sensor is pulsed to at least 40 V tINT seconds before the photodiode to VCCD transfer pulse on V2. Use of the electronic shutter does not have to wait until the previously acquired image has been completely read out of the VCCD. www.onsemi.com 37 KAI-04022 Large Signal Output The charge handling capacity of the output amplifier is also set by the reset clock voltage levels. The reset clock driver circuit is very simple if an amplitude of 5 V is used. But the 5 V amplitude restricts the output amplifier charge capacity to 20,000 electrons. If the full dynamic range of 40,000 electrons is desired then the reset clock amplitude will have to be increased to 7 V. If you only want a maximum signal of 20,000 electrons in binned or summed interlaced modes, then a 40 MHz pixel rate with a 5 V reset clock may be used. The output of the amplifier will be unpredictable above 20,000 electrons so be sure to set the maximum input signal level of your analog to digital converter to the equivalent of 20,000 electrons (640 mV). When the image sensor is operated in the binned or summed interlaced modes there will be more than 20,000 electrons in the output signal. The image sensor is designed with a 31 mV/e charge to voltage conversion on the output. This means a full signal of 20,000 electrons will produce a 640 mV change on the output amplifier. The output amplifier was designed to handle an output swing of 640 mV at a pixel rate of 40 MHz. If 40,000 electron charge packets are generated in the binned or summed interlaced modes then the output amplifier output will have to swing 1,280 mV. The output amplifier does not have enough bandwidth (slew rate) to handle 1,280 mV at 40 MHz. Hence, the pixel rate will have to be reduced to 20 MHz if the full dynamic range of 40,000 electrons is desired. www.onsemi.com 38 KAI-04022 REFERENCES For information on ESD and cover glass care and cleanliness, please download the Image Sensor Handling and Best Practices Application Note (AN52561/D) from www.onsemi.com. For quality and reliability information, please download the Quality & Reliability Handbook (HBD851/D) from www.onsemi.com. For information on device numbering and ordering codes, please download the Device Nomenclature technical note (TND310/D) from www.onsemi.com. For information on environmental exposure, please download the Using Interline CCD Image Sensors in High Intensity Lighting Conditions Application Note (AND9183/D) from www.onsemi.com. For information on Standard terms and Conditions of Sale, please download Terms and Conditions from www.onsemi.com. For information on soldering recommendations, please download the Soldering and Mounting Techniques Reference Manual (SOLDERRM/D) from www.onsemi.com. www.onsemi.com 39 KAI-04022 MECHANICAL INFORMATION Completed Assembly Notes: 1. See Ordering Information for marking code. 2. The Cover Glass is manually placed and aligned. Figure 46. Completed Assembly www.onsemi.com 40 KAI-04022 Die to Package Alignment Figure 47. Die to Package Alignment www.onsemi.com 41 KAI-04022 Glass Notes: 1. Multi-layer anti-reflective coating on 2 sides: a. Double sided reflectance b. Range (nm): i. 420-435 nm < 2.0% ii. 435-630 nm < 0.8% iii. 630-680 nm < 2.0% 2. Dust, Scratch specification: 10 mm maximum. 3. Substrate - Schott D263T eco or equivalent. 4. Epoxy: NCO-150HB a. Thickness: 0.002-0.005 5. Dimensions a. Units: Inch [mm] 6. Tolerance, unless otherwise specified: a. Ceramic: 1% no less than 0.004 b. L/F: 1% no more than 0.004 Figure 48. Glass Drawing www.onsemi.com 42 KAI-04022 Glass Transmission 100 90 80 Transmission (%) 70 60 50 40 30 20 10 0 200 300 400 500 600 700 800 900 Wavelength (nm) Figure 49. Glass Transmission ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC's product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor 19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5817-1050 www.onsemi.com 43 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative KAI-04022/D