71M6511/71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 GENERAL DESCRIPTION FEATURES The TDK 71M6511 is a highly integrated SOC with an MPU core, RTC, FLASH and LCD driver. TDK's patent pending Single Converter Technology with a 22-bit delta-sigma ADC, 3 analog inputs, digital temperature compensation, precision voltage reference and 32-bit computation engine support a wide range of residential metering applications with very few low cost external components. A 32kHz crystal timebase for the entire system and Internal battery backup support for RAM and RTC further reduce system cost. Maximum design flexibility is supported with multiple UARTs, I2C, power fail comparator, 5V LCD charge pump, up to 12 DIO pins and in system programmable FLASH which can be updated with data or application code in operation. Easy conversion to ROM offers unprecedented cost structure for high volume applications. A complete array of ICE and development tools, programming libraries and reference designs enable rapid development and certification of TOU, AMR and Prepay meters that meet world wide electricity metering standards. * < 0.1% Wh accuracy over 2000:1 range (71M6511H version), < 0.5% Wh accuracy over 2000:1 range (71M6511 version) * Exceeds IEC62053 / ANSIC12.20 standards * Voltage reference < 10ppm/C spec (71M6511H version), < 50ppm/C (71M6511 version) * Three sensor inputs--VDD referenced * Digital temperature compensation * 22-bit delta-sigma ADC * Independent 32-bit compute engine * Low jitter Wh and VARh pulse outputs * 40-70Hz line frequency range * Phase compensation (7) * Battery backup for RAM and RTC * 29mW @3.3V, 7.2W battery backup CT/SHUNT LIVE * Flash memory option with security POWER SUPPLY LOAD * 8-bit microcontroller (80515) NEUT * Integrated ICE for MPU debug CONVERTER * RTC for time of use functions 5V BOOST VA V or I * High speed SSI serial output V3.3A V3.3D GNDA GNDD IA TDK 71M6511 IB VDRV * Two event counter/timers REGULATOR VBAT BATTERY V2.5 VOLTAGE REF TEMP SENSOR VREF RAM VBIAS SERIAL PORTS AMR IR TX 32 kHz Rev 2.9 COM0..3 3/5V LCD FLASH/ ROM SEG0..19 SEG 24..32 DIO 0..11 88.88.8888 COMPUTE ENGINE SEG 32..41 DIO 12..21 EEPROM SENSE DRIVE RX TX V1 OSC/PLL XIN XOUT MPU DIO 0..3 * Up to 12 general purpose I/O pins * 32kHz timebase for RTC, CE, and MPU * 64kB FLASH or ROM, 7kB total RAM RX COMPARATOR POWER FAULT VLCD * Watchdog timer, power fail monitor * LCD driver (up to 128 pixels) LCD DRIVER DIO, PULSE TEST PULSES RTC TIMERS * Two UARTs for IR and AMR * Third software UART via DIO pins * 64-lead LQFP package * Lead Free package option ICE PRELIMINARY DATA SHEET Page: 1 of 52 71M6511/71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 Table of Contents GENERAL DESCRIPTION ........................................................................................................................ 1 FEATURES.................................................................................................................................. 1 FUNCTIONAL DESCRIPTION................................................................................................................... 6 Meter Equations........................................................................................................................... 6 Digital Computation Engine (CE) ................................................................................................. 8 80515 MPU Core ......................................................................................................................... 11 Internal Resources....................................................................................................................... 12 Memory........................................................................................................................................ 14 I/O Peripherals ............................................................................................................................. 14 Digital I/O ..................................................................................................................................... 15 EEPROM Interface ...................................................................................................................... 16 LCD Drivers ................................................................................................................................. 17 Optical Interface........................................................................................................................... 17 Synchronous Serial Interface (SSI).............................................................................................. 18 SSI SIGNAL................................................................................................................................. 19 System Timing Summary............................................................................................................. 19 Fault and Reset Behavior ............................................................................................................ 20 Battery Operation/Power Save Modes ......................................................................................... 21 Watchdog Timer .......................................................................................................................... 22 Program Security ......................................................................................................................... 22 Voltage Reference ....................................................................................................................... 23 Meter Calibration.......................................................................................................................... 23 I/O RAM DESCRIPTION - Alphabetical Order ............................................................................ 25 I/O RAM MAP - Ordered by Function.......................................................................................... 32 CE Data Memory ......................................................................................................................... 34 MPU Data Memory (XRAM)......................................................................................................... 38 Rev 2.9 PRELIMINARY DATA SHEET Page: 2 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 ELECTRICAL SPECIFICATIONS .............................................................................................................. 40 ABSOLUTE MAXIMUM RATINGS .............................................................................................. 40 RECOMMENDED EXTERNAL COMPONENTS ......................................................................... 40 RECOMMENDED OPERATING CONDITIONS .......................................................................... 41 PERFORMANCE SPECIFICATIONS .......................................................................................... 41 LOGIC LEVELS............................................................................................................. 41 SUPPLY CURRENT ...................................................................................................... 42 VREF, VBIAS ................................................................................................................ 42 2.5V VOLTAGE REGULATOR ...................................................................................... 43 COMPARATORS .......................................................................................................... 43 FLASH MEMORY TIMING ............................................................................................ 43 ADC CONVERTER, VDD REFERENCED .................................................................... 44 CRYSTAL OSCILLATOR .............................................................................................. 44 OPTICAL INTERFACE.................................................................................................. 45 TEMPERATURE SENSOR ........................................................................................... 45 LCD BOOST.................................................................................................................. 45 LCD DRIVERS .............................................................................................................. 45 FOOTNOTES ................................................................................................................ 46 PACKAGE OUTLINE ................................................................................................................... 48 PINOUT: ...................................................................................................................................... 49 PIN DESCRIPTIONS ................................................................................................................... 50 Power/Ground Pins:....................................................................................................... 50 Analog Pins: .................................................................................................................. 50 Digital Pins:.................................................................................................................... 51 ORDERING INFORMATION ....................................................................................................... 52 List of Figures Figure 1: IC Functional BLOCK DIAGRAM.....................................................................................................5 Figure 2: RTM Output Format..........................................................................................................................9 Figure 3: MPU/CE Communication ................................................................................................................10 Figure 4: SSI Timing, (SSI_FPOL = SSI_RDYPOL = 0) ................................................................................18 Figure 5: SSI Timing, 16 bit field example. External device delays SRDY. ...................................................18 Figure 6: Timing relationship between ADC MUX, CE, and Serial Transfers................................................20 Figure 7: 71M6511H WH accuracy performance ..........................................................................................47 Figure 8: Meter Accuracy over Harmonics at 240V, 30A ..............................................................................47 Rev 2.9 PRELIMINARY DATA SHEET Page: 3 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 List of Tables Table 1: Standard Meter Equations .................................................................................................................6 Table 2: RAM Locations for ADC Results ........................................................................................................7 Table 3: CE Outputs. .......................................................................................................................................8 Table 4: MPU Data Memory Space ...............................................................................................................11 Table 5: External MPU Interrupts..................................................................................................................11 Table 6: Interrupt Control Bits .......................................................................................................................12 Table 7: EECTRL status bits........................................................................................................................16 Table 8: Liquid Crystal Display Segment Table(typical) .................................................................................17 Table 9: SSI Pins ...........................................................................................................................................19 Table 10: Power Saving Measures ................................................................................................................21 Rev 2.9 PRELIMINARY DATA SHEET Page: 4 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 Figure 1: IC Functional BLOCK DIAGRAM VREF IA VA IB VBIAS V3P3A GNDA GNDA ADC CONVERTER MUX VOLTAGE BOOST VBIAS V3P3A VDRV FIR FILTER + LCD_IBST LCD_BSTEN VREF TEMP MUX CTRL V2P5NV VOLT REG 0.1V MCK PLL V2P5 4.9MHz CK_GEN CE RAM (1KB) CK_2X ECK_DIS MPU_DIV WPULSE VARPULSE RTM STRT CKCE CE <4.9MHz SCALE_TAGS HW_TAGS LCD DISPLAY DRIVER WPULSE VARPULSE CE_RUN CE PROG RAM (4KB) 3000-3FFF CE_LOAD I/O RAM CE_BUSY XFER BUSY RTM_EN CE_EN <4.9MHz SDCK SDOUT SDIN TX MPU (8051) UART EEPROM INTERFACE 0000-07FF MPU XRAM (2KB) PROG 0000-FFFF OPT_TX OPTICAL V1 FLASH (64KB) EERDSLOW EEWRSLOW VREF POWER FAULT COMP_STAT COMP_INT 0000-FFFF MPU_RSTZ V3P3 WAKE EMULATOR PORT FAULTZ V2P5NV SEG3/SCLK SEG4/SSDATA SEG5/SFR SEG6/SRDY SEG7/ MUX_SYNC CONFIGURATION PARAMETERS XFER_BUSY CE_BUSY RTCLK PULSE_OUT CK_MPU DMUX F E D C B CK_10M MUX_SYNC OPTRX A 9 8 V3_OK V2_OK WDTR_EN RTM VBIAS PLL_2.5V 7 6 5 4 3 2 IBIAS E_RXTX E_TCLK RTCLK RTC DGND RESETZ SEG24/DIO4 ... SEG31/DIO11 SEG34/DIO14 ... SEG37/DIO17 RTC_HOLD RTC_SET 2000-20FF DATA 0000-FFFF SEG8..SEG19 LCD_NUM LCD_MODE LCD_CLK LCD_EN DIGITAL I/O DIO_EEX PULSEV/W DIO_IN DIO_OUT LCD_NUM DIO_GP CONFIG RAM V2PNV5 OPT_TXDIS COM0..3 SEG0..SEG2 1000-13FF CKMPU OPT_RX LCD_MODE LCD_FS LCD_EN MEMORY SHARE PROG 000-7FF CE CONTROL EQU PRE_SAMPS SUM_CYCLES VLCD MUX DATA 00-FF 32 bit Compute Engine V2P5 LCD DAC SSI CTRL CKMPU_2X MUX_SYNC TEST MODE 2.5V to logic CKFIR 4.9MHz VLC0 VLC1 VLC2 CK_EN CKOUT_EN RX GNDD OSC_DIS CKTEST TEST V3P3D VBAT V2P5NV RTCLK (32KHz) OSC (32KHz) XOUT GNDD FIR_LEN CK32 EQU MUX_ALT MUX_DIV XIN VREF CHOP_EN VREF_DIS MUX DIGITAL ANALOG 1 0 TMUX TMUXOUT September 17, 2004 E_RST (Open Drain) Rev 2.9 PRELIMINARY DATA SHEET Page: 5 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 FUNCTIONAL DESCRIPTION The TDK 71M6511 single chip power meter integrates all primary functional blocks required to implement a solidstate electricity meter. Included on chip are an analog front end (AFE), a digital computation engine, an 8051compatible microprocessor, a voltage reference, a temperature sensor, LCD drivers, RAM, Flash memory, a real time clock, and a variety of I/O pins. In a typical application, the 71M6511 sequentially samples the voltage inputs on pins IA, VA, IB and performs calculations to measure active power (Wh), reactive power (VARh), A2h, and V2h. These and other measurement functions which are primarily executed on the internal 32-bit Compute Engine are provided as part of TDK's standard library. A standard ANSI "C" 80515 application programming interface library is available to help reduce design cycle. In addition to advanced measurement functions, the real time clock function allows the device to record time of use metering information for multi-rate or time-of-use (TOU) applications. Measurements can be displayed on either 3V or 5V LCD commonly used in low temperature environments. Flexible mapping of LCD display segments will facilitate integration if exisiting custom LCD. Design trade-off between number of LCD segments vs. DIO pins can be implemented in software to accommodate various requirements. One of the two internal UARTs is adapted to support an Infrared LED with internal drive and sense amplification but it can also function as a standard UART. In addition to the two hardware UART modules, customers can implement a third UART function using a Bit-Bang scheme through two DIO pins. This flexibility makes it possible to implement AMR meters with two ports plus a third Infrared interface. A detailed describtion of various functions are follows: Meter Equations The Compute Engine (CE) implements the equations in Table 1. Compute Engine (CE) firmware for industrial configurations implements the equations in Table 1. The register EQU (located in the I/O RAM) specifies the equation to be used based on the number of phases used for metering. . Table 1: Standard Meter Equations Channels used from MUX EQU 000 001 Rev 2.9 Formula VA IA (1 element, 2W 1) VA(IA-IB)/2 (1 element, 3W 1) Sequence Channels used from alternative MUX Sequence States 0 5 States 0 5 0 1 2 3 4 5 0 1 2 3 4 5 IA VA IB - - - TEMP VA - - - - IA VA IB - - - TEMP VA IB - - - PRELIMINARY DATA SHEET Page: 6 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 Analog Front End (AFE) The AFE of the 71M6511 is comprised of an input multiplexer, a delta-sigma A/D converter and a voltage reference. Input multiplexer: The input multiplexer supports up to three input signals that are applied to pins IA, VA and IB of the device. Alternatively, it has the ability to select temperature (TEMP),VA and in some cases, IB. The ALT mux selection is intended to be commanded infrequently (every second or so) by the MPU. In order to prevent disruption of the voltage tracking PLL and voltage allpass networks, VA is not replaced in the ALT selections. Table 1 details the regular and alternative MUX sequences. In a typical application, IA and IB are connected to current transformers that sense the current on each phase of the line voltage. VA is typically connected to voltage sensors through a resistor divider. MUX Control: MUX advance, FIR filter initiation, and VREF chopping (using the CROSS signal - described below) are controlled by the MUX_CTRL circuit. Additionally, MUX_CTRL launches each pass through the CE program. MUX_CTRL is clocked by CK32, the 32768Hz clock from the PLL block. The behavior of MUX_CTRL is governed by MUX_ALT, EQU, and MUX_DIV. The MUX_ALT bit requests an alternative multiplexer frame. The bit may be asserted on any MPU cycle and may be subsequently deasserted on any cycle including the next one. A rising edge on MUX_ALT will cause MUX_CTRL to wait until the next multiplexer frame and implement a single alternate frame. Another control input to the multiplexer is MUX_DIV. This signal can request 2, 3, 4, or 6 multiplexer states per frame. Delta-sigma A/D Converter: A single delta-sigma A/D converter digitizes the power inputs to the device. The resolution of the ADC is programmable using the FIR_LEN register as shown in the I/O RAM section. ADC resolution can be selected to be 21 bits (FIR_LEN=0), or 22 bits (FIR_LEN=1). Conversion time is two cycles of CK32 with FIR_LEN = 0 and three cycles with FIR_LEN = 1. Accuracy and timing specifications inthis data sheet are based on FIR_LEN = 0. Initiation of each ADC conversion is controlled by MUX_CTRL as described previously. At the end of each ADC conversion the FIR filter output data is stored into the CE RAM location determined by the multiplexer selection. Table 2 details the RAM locations. Table 2: RAM Locations for ADC Results ADDRESS (HEX) 00 01 02 03 04 05 06 07 Rev 2.9 NAME IA VA IB TEMP -- DESCRIPTION Phase A current Phase A voltage Phase B current Reserved Reserved Reserved Temperature Reserved PRELIMINARY DATA SHEET Page: 7 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 Voltage Reference: The device includes an on-chip precision bandgap voltage reference that incorporates autozero techniques as well as production trims to minimize errors caused by component mismatch and drift. The result is a voltage output with a predictable temperature coefficient. Rather than internally compensating for the temperature variation, a digital output corresponding to the bandgap temperature is provided to the embedded microcontroller which then digitally compensates the power outputs. This permits a system wide temperature correction over the entire system than local to the chip. This effective thermal coefficients may include the current sensors, the voltage sensors, and the crystal frequency. Since the band gap is chopper stabilized via the CHOP_EN bits, the most significant long term drift mechanism in the voltage reference is removed. CHOP_EN has 3 states: Positive, reverse, and chop. Digital Computation Engine (CE) A dedicated 32-bit CE performs the precision computations necessary to accurately measure power. The CE calculations include frequency insensitive offset cancellation on all six channels and a frequency insensitive 90 phase shifter for VAR calculations. Table 3: CE Outputs. CE Output TEMP FREQ W0SUM, W1SUM VAR0SUM, VAR1SUM I0SQSUM, I1SQSUM V0SQSUM Description Resolution (LSB size) The bandgap temperature with respect to calibration 0.1 C temperature. 232 bit information. The frequency of V0. The actual value is 232F0/FS. 0.5869 Hz F0 is the measured fundamental frequency in Hz. FS is the MUX frame rate, typically 2.5kHz. 216.99 Ws The sum of output samples of the selected power (250mVpk at Current =200A RMS, equation. 250mVpk at Voltage = 450V RMS) 216.99 Ws The sum of output samples of the selected power (250mVpk at Current =200A RMS, equation, with voltage inputs lagging 90 degrees. 250mVpk at Voltage = 450V RMS) The square of the sum of the samples of each 9.644x10-5 A2s current. (250mVpk at Current =200A) 4.8823x10-4 V2s The sum of the squared samples of each voltage. (250mVpk at Voltage = 450V RMS) The number of samples summed is controlled by the bits PRE_SAMPS and SUM_CYCLES. The integration time for each energy output is PRE_SAMPS * SUM_CYCLES/2520.6. The CE contains a Real Time Monitor (RTM) which can be programmed through the UART to monitor four selectable CE RAM locations at full sample rate. The four monitored locations are serially output to the TMUXOUT pin via the digital output multiplexer at the beginning of each CE code pass. The RTM can be enabled and disabled with RTM_EN. The RTM output is clocked by CKTEST. Each RTM word is clocked out in 35 cycles and contains a leading flag bit. Figure 1 illustrates the RTM output format. RTM is low when not in use Rev 2.9 PRELIMINARY DATA SHEET Page: 8 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 Figure 2: RTM Output Format CK32 MUX_SYNC CKTEST 30 0 31 FLAG 1 30 0 31 FLAG 1 30 31 SIG N 1 LSB FLAG SIG N 0 31 LSB 30 SIG N 1 LSB FLAG RTM DATA0 (32 bits) RTM DATA1 (32 bits) RTM DATA2 (32 bits) RTM DATA3 (32 bits) LSB 0 SIG N TMUXOUT/RTM Clock Generator: The CE clock frequency is always CK32 * 150. The MPU clock frequency is determined by MPU_DIV and can be CE*2-MPU_DIV Hz where MPU_DIV varies from 0 to 7. This makes the MPU clock scalable from 4.9152MHz down to 38.4kHz. CK32 is the 32kHz clock. The circuit also generates a 2x MPU clock for use by the emulator. This clock is not generated when ECK_DIS is asserted by the emulator. CE RAM: The CE data RAM can be accessed by the FIR filter block, the RTM, the CE, and the MPU. Assigned time slots are reserved for FIR, RTM, and MPU, respectively, such that memory accesses to CE RAM do not collide. Holding registers are used to convert 8-bit wide MPU data to/from 32-bit wide CE RAM data, and wait states are inserted as needed, depending on the frequency of CKMPU. RTM data is read from the CE RAM locations specified by RTM0, RTM1, RTM2, and RTM3 after the rise of MUX_SYNC. CE PRAM: The CE program RAM is loaded at boot time by the MPU and then accessed as necessary by the CE. Each CE instruction word is 2 bytes long. PRAM memory size is 2048 words. The CE program counter begins a pass through the CE code each time mux state 0 begins. The code pass ends when a HALT instruction is executed. For proper operation, the code pass must be completed before the `S' muxstate begins. CE Communication with MPU: The CE outputs two signals to the MPU: CE_BUSY and XFER_BUSY. These are connected to the MPU interrupt service inputs. CE_BUSY indicates that the CE is actively processing data. This signal will occur once every multiplexer frame. XFER_BUSY indicates that the CE is updating to the Output region of the CE RAM. This will occur whenever the CE has finished generating a sum. MPU interrupts occur on the falling edges of these signals. On power-up the MPU loads the code for the CE into the CEPRAM. The CE executes its code, generating results and storing them in the CE RAM. Once, control of the CEDRAM is transferred to the MPU, the MPU can then access the CEDRAM data. Rev 2.9 PRELIMINARY DATA SHEET Page: 9 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 CE PRAM FLASH TRANSFER CTRL COMPUTATION ENGINE CE DRAM MPU Figure 3: MPU/CE Communication Pulse Generator: The chip contains two pulse generators which create low jitter pulses at a rate set by APULSEW*WRATE and APULSER*WRATE if EXT_PULSE is 15. If EXT_PULSE is 0 APULSEW is replaced with WSUM_X and APULSER is replaced with VARSUM_X. The DIO_PV and DIO_PW as described in the Digital I/O section can be programmed to route WPULSE and VARPULSE to the output pins DIO_7 and DIO_6 respectively. LCD_NUM lets the user configure the number of dual purpose pins to be configured as DIO pins. The maximum time jitter is the MUX frame period (normally 400s) and is independent of the number of pulses measured. Thus, errors due to jitter are attenuated by the number of pulses averaged, rather than by the square root of the number of pulses averaged. The actual pulse rate, using WSUM as an example, is: RATE = WRATE * WSUM / (246 * TMUX), measured in Hz. Rev 2.9 PRELIMINARY DATA SHEET Page: 10 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 80515 MPU Core The device includes an 80515 microcontroller (8-bit, 8051 compatible) that processes one instruction each clock cycle. Using a 5MHz clock, the fastest operations are processed at 5 MIPS. Actual processor clocking speed can be adjusted to the total processing demand of metering calculations, AMR management, memory management, LCD driver management, and I/O management. The MPU has the peripheral set of an 80515, but without the MDU and timer 3. It has addressable memory space of up to 64k bytes. Data bus address space is allocated to on-chip memory as follows: Table 4: MPU Data Memory Space ADDRESS (hex) 0000-07FF 1000-13FF 2000-20FF 3000-3FFF MEMORY TYPE MEMORY SIZE MPU Data RAM CE Data RAM Misc I/O RAM CE Prog RAM 2KB 1KB 256 4KB Interrupts: The 71M6511 MPU allows seven external interrupts. These are connected as shown in table 5. The direction of interrupts 2 and 3 is programmable in the MPU. Interrupts 2 and 3 should be programmed for falling sensitivity. The generic 8051 MPU literature states that interrupt 4 through 6 are defined as rising edge sensitive. Thus, the hardware signals attached to interrupts 5 and 6 are inverted to achieve the edge polarity shown in Table 5. Table 5: External MPU Interrupts INTERRUPT 0 1 2 3 4 5 6 Rev 2.9 CONNECTION Digital I/O High Priority Digital I/O Low Priority Comparator (falling) CE_BUSY (falling) Comparator (rising) EEPROM busy (falling) XFER_BUSY (falling), RTC_1SEC PRELIMINARY DATA SHEET Page: 11 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 Table 6: Interrupt Control Bits NAME EX0 EX1 EX2 EX3 EX4 EX5 EX6 EX_XFER EX_RTC IE0 IE1 IEX2 IEX3 IEX4 IEX5 IEX6 IE_XFER IE_RTC DESCRIPTION Enable external interrupt 0 Enable external interrupt 1 Enable external interrupt 2 Enable external interrupt 3 Enable external interrupt 4 Enable external interrupt 5 Enable external interrupt 6 Enable XFER_BUSY interrupt Enable RTC_1SEC interrupt External interrupt 0 flag External interrupt 1 flag External interrupt 2 flag External interrupt 3 flag External interrupt 4 flag External interrupt 5 flag External interrupt 6 flag XFER_BUSY interrupt flag RTC_1SEC interrupt flag SFR (special function register) enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has its own flag bit which is set by the interrupt hardware and must be reset by the MPU interrupt handler. Note that XFER_BUSY and RTC_1SEC have their own enable and flag bits in addition to the interrupt 6 enable and flag bits. Internal Resources Oscillator: The oscillator drives a standard 32.768kHz watch crystal. These crystals are accurate and do not require a high current oscillator circuit. The 71M6511 oscillator has been designed specifically to handle these crystals and is compatible with their high impedance and limited power handling capability. The oscillator power dissipation is very low to maximize the lifetime of any battery backup device attached to the VBAT pin. PLL: All internal clocks are based on the The CE clock is generated by an on-chip PLL which multiplies the watch crystal frequency (32,768Hz). The PLL multiplies this frequency by 150 to yield 4.9152MHz. This frequency is supplied to the ADC, which then supplies the clock to the FIR filter (CKFIR), the clock test output pin (CKTEST), the CE RAM and the clock generator. The clock generator provides two clocks, one for the MPU (CKMPU) and one for the CE (CKCE). Clock/Timers: Timing for the device is derived from the 32.768kHz watch crystal. On-chip timing functions include the 80515 master clock, a real time clock (RTC), delta-sigma sample clock, and two 80515 general counter/timers, timer 0 and timer 1. Rev 2.9 PRELIMINARY DATA SHEET Page: 12 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 Real-Time Clock (RTC): The RTC is driven directly by the crystal oscillator. It is powered by the V2P5NV net, which is the battery-backed up supply. The RTC consists of a counter chain and output registers. The counter chain consists of seconds, minutes, hours, day of week, day of month, month, and year. Each counter has its own output register. Whenever the MPU reads the seconds register, all other registers are automatically updated. Since the RTC clock is not coherent to the MPU clock, the MPU must read the seconds register until two consecutive reads are the same (requires either 2 or 3 reads). At this point, all RTC registers will have the correct time. Regardless of the MPU clock speed, RTC reads require 1 wait state. RTC time is set by writing to the registers. Each byte written to RTC must be delayed at least 3 RTC clock cycles from any previous byte written to RTC. Two time correction bits, RTC_DEC_SEC and RTC_INC_SEC are provided to adjust the RTC time. A pulse on one of these bits causes the time to be decremented or incremented by an additional second at the next update of the RTC_SEC register. If the crystal temperature coefficient is known, the MPU can integrate temperature and correct the RTC time as necessary as discussed in temperature compensation. Temperature Sensor: The device includes an on-chip temperature sensor for determining the temperature of the bandgap reference. The MPU may request an alternate mux frame containing the temperature sensor output by asserting MUX_ALT. The primary use of the temperature data is to determine the magnitude of compensation required to offset the thermal drift in the system (see section titled "Temperature Compensation"). The secondary use of the temperature data is to monitor the ambient temperature of the meter. The user can characterize the temperature of the 71M6511 compared to the ambient temperature within the meter. Based on this characterization data, the user can determine an over-temperature value. The on-chip temperature can also be monitored to determine if the ambient is approaching an unsafe level. In the event that the temperature exceeds the set level, the firmware can generate an interrupt. This interrupt can be used to trigger I/O functions that disable power supplies, contact the utility through an AMR port, measure the duration of the over-temp condition, etc. Rev 2.9 PRELIMINARY DATA SHEET Page: 13 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 Memory Flash Memory: The 71M6511 includes 64KB of on-chip flash memory. The flash memory primarily contains MPU program code. It also contains images of the CE program code, CE coefficients, MPU RAM, and CONFIG RAM. On power-up, before enabling the CE, the MPU copies these images to their respective memory locations. The bit Flash66Z (see I/O RAM table) defines the speed for accessing flash. With this flag being high flash 33ns read pulse is used otherwise 66ns read pulse is required. To minimize supply current draw, this bit should be set to 1. Flash erasure is initiated by writing a specific data pattern to specific SFR registers in the proper sequence. These special pattern/sequence requirements prevent inadevertent erasure of the flash memory. The mass erase sequence is: 1. Write 1 to the FLSH_MEEN bit (SFR address 0xB2[1]. 2. Write pattern 0xAA to FLSH_ERASE (SFR address 0x94) Note: The mass erase cycle can only be initiated when the ICE port is enabled. The page erase sequence is: 1. Write the page address to FLSH_PGADR (SFR address 0xB7[7:1] Write pattern 0x55 to FLSH_ERASE (SFR address 0x94) The MPU may write to the flash memory. This is one of the non-volatile storage options available to the user. The other option, battery backed-up RAM, is the lower supply current option for non-volatile storage. FLSH_PWE (flash program write enable) differentiates 80515 data store instructions (MOVX@DPTR,A) between Flash and RAM writes. MPU RAM: The 71M6511 includes 2k-bytes of static RAM memory on-chip plus 256-bytes of internal RAM in the MPU core. The 2k-bytes of RAM are used for data storage during MPU normal operations. CE RAM: The CE RAM is the working memory of the CE. The MPU can read and write the CE RAM as the primary means of data communication between the two processors. I/O Peripherals The 71M6511 includes several I/O peripheral functions that improve the functionality of the device and reduce the component count for most meter applications. The I/O peripherals include two UARTs, digital I/O, comparator inputs, LCD display drivers, I2C interface and an IR interface. Note: Clock stretching and multi-master operation is not supported for the I2C interface. UART: The device includes a UART that can be programmed to communicate with a variety of AMR modules. The UART also provides a mechanism for programming the on-chip flash memory. A second UART is connected to the optical port, as described in the optical port description. Rev 2.9 PRELIMINARY DATA SHEET Page: 14 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 The UART is a dedicated 2 wire serial interface which can communicate with an external host processor. The operation of each pin is as follows: RX: Is the serial input data. It transfers inputs the contents of a block of internal registers or CE memory. The bytes are input LSB first. TX: Is the serial output data. Outputs the contents of a block of internal registers or CE memory. The bytes are output LSB first. The 71M6511 has several on-chip registers which can be read and written. All UART transfers are programmable for parity enable, parity, 2 stop bits/1 stop bit and XON/XOFF options for variable communication baud rates from 300 to 38400 bps. UART Memory Operations: In addition to the registers, the CE program and data memory can be read and written. This is accomplished via use of the CE program and data address registers. After a write to the CE memory address register with a start address, subsequent reads/writes of the CE program register will read/write succesive CE program memory locations. Similarly, subsequent reads/writes of the CE data register will read/write successive CE data memory locations. Digital I/O The device includes up to 12 pins of general purpose digital I/O. These pins are dual function and can alternatively be used as LCD drivers. The pins are configured by the DIO registers and by the five bits of the LCD_NUM register (located in I/O RAM). Each pin can be configured independently as an input or output with the DIO_DIR bits. If configured as input, each pin has a 3 bit configuration word, DIO_Rx, that indicates whether it is connected to a resource such as an interrupt or a timer control. Additionally, DIO6 and DIO7 are configured as a WPULSE and VARPULSE outputs using DIO_PW and DIO_PV registers. An EEPROM interface is multiplexed onto DIO4 and DIO5. Analog and Digital Output Multiplexer: One out of 16 digital or 4 analog signals can be selected to be output on the TMUXOUT pin. The function of the multiplexer is controled with the TMUX bits (located in the I/O RAM). Rev 2.9 PRELIMINARY DATA SHEET Page: 15 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 EEPROM Interface A dedicated 2 pin serial interface communicates with external EEPROM devices. The interface is multiplexed onto DIO4 and DIO5. See DIO_EEX bit in the I/O RAM table. The MPU communicates with the interface through two SFR registers: EEDATA and EECTRL. If the MPU wishes to write a byte of data to EEPROM, it places the data in EEDATA and then writes the `Transmit' code to EECTRL. The write to EECTRL initiates the transmit. The transmit is finished when the Busy bit falls. Interrupt 5 is also asserted when BUSY falls. The MPU can then check the RX_ACK bit to see if the EEPROM acknowledged the transmission. A byte is read by writing the `Receive' command to EECTRL and waiting for Busy to fall. Upon completion, the received data is in EEDATA. The serial transmit and receive clock is 78kHz during each transmission, and then holds in a high state until the next transmission. The bits in EECTRL are shown in the table below: Table 7: EECTRL status bits Statu s Bit 7 Error Read/Writ e R 6 Busy 5 4 Name Polarity Description High Asserted when an illegal command is received. R High Asserted when serial data bus is busy. RX_ACK R High Indicates the EEPROM sent an ACK bit. TX_ACK R High Indicates when an ACK bit has been sent to EEPROM CMD 0 2 3-0 CMD[3:0] W See CMD Table 3 5 6 Receive the last byte from EEPROM and don't send ACK. 9 Issue a `START' sequence Others Rev 2.9 Operation No-op Receive a byte from EEPROM and send ACK. Transmit a byte to EEPROM Issue a `STOP' sequence No Operation, assert Error bit PRELIMINARY DATA SHEET Page: 16 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 LCD Drivers The device contains 19 dedicated LCD segment drivers and 17 multi-purpose pins which may be configured as additional LCD segment drivers. The device is capable of driving between 60 to 128 pixels of LCD display with 25% duty cycle. At 7 pixels per digit, the LCD can be designed for 8 to 18 digits of display. Since each pixel is addressed individually, the LCD display can be a combination of alphanumeric digits and enunciator symbols. The LCD drivers are grouped into 4 commons (COM0 to COM3) and up to 32 segments. A typical LCD map is shown below. A charge pump suitable for driving VLCD is included. This circuit creates 5v from the 3.3v supply. A contrast DAC is provided that permits the LCD full scale to be adjusted between VLCD and 70% of VLCD. LCD_NUM defines the number of dual purpose pins used for LCD segment interface. Table 8: Liquid Crystal Display Segment Table (typical) Seg0 Seg1 Seg2 Seg3 Seg4 Seg5 ..... .... Seg31 Com0 P0 P4 P8 P12 P16 P20 .... ... P124 Com1 P1 P5 P9 P13 P17 P21 .... .... P125 Com2 P2 P6 P10 P14 P18 P22 .... .... P126 Com3 P3 P7 P11 P15 P19 P23 ..... ..... P127 Note: P0, P1, ... Represent the pixel numbers on the LCD. Optical Interface The device includes an interface to implement an IR or optical port. The pin OPT_Tx is designed to directly drive an external LED for transmitting data on an optical link. The pin OPT_Rx is designed to sense the input from an external photo detector used as the receiver for the optical link. These two pins are connected to a dedicated UART port. OPT_Tx can be tristated if it is desired to multiplex another IO pin to the OPT_Tx output. This control bit is OPT_TXDIS. Rev 2.9 PRELIMINARY DATA SHEET Page: 17 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 Synchronous Serial Interface (SSI) A high speed, handshake, serial interface is available to send a contiguous block of CE data to an external data logger or DSP. The block of data, configurable as to location and size, is sent starting 1 cycle of 32kHz before each CE code pass begins. If the block of data is big enough that transmission has not completed when the code pass begins, it will complete during the CE code pass with no timing impact to the CE or the serial data. In this case, care must be taken that the transmitted data is not modified unexpectedly by the CE. The SSI interface is enabled by the SSI_EN bit and consists of SCLK, SSDATA, and SFR as outputs and, optionally, SRDY as input. The interface is compatible with 16bit and 32bit processors. The operation of each pin is as follows: SCLK is the serial clock. The clock can be 5MHz or 10MHz, as specified by the SSI_10M bit. The SSI_CKGATE bit controls whether SCLK runs continuously or is gated off when no SSI activity is occurring. If SCLK is gated, it will begin 3 cycles before SFR rises and will persist 3 cycles after the last data bit is output. SSDATA is the serial output data. SSDATA changes on the rising edge of SCLK and outputs the contents of a block of CE RAM words starting with address SSI_STRT and ending with SSI_END. The words are output MSB first. Figure 4: SSI Timing, (SSI_FPOL = SSI_RDYPOL = 0) If SSI_CKGATE =1 If 16bit fields If 32bit fields If SSI_CKGATE =1 SFR (Output) SRDY (Input) SCLK (Output) 31 SSDATA (Output) 30 16 15 1 0 31 30 SSI_BEG 16 15 1 0 31 SSI_BEG+1 1 0 SSI_END MUX_SYNC Figure 5: SSI Timing, 16 bit field example. External device delays SRDY. Next field is delayed while SRDY is low SFR (Output) SRDY (Input) SCLK (Output) SSDATA (Output) 31 30 29 18 17 16 16 16 16 15 14 13 12 SFR is the framing pulse. Although CE words are always 32 bits, the SSI interface will frame the entire data block as a single field, as multiple 16 bit fields, or as multiple 32-bit fields. The SFR pulse is one clock cycle wide, Rev 2.9 PRELIMINARY DATA SHEET Page: 18 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 changes state on the rising edge of SCLK and preceeds the first bit of each field. The field size is set with SSI_FSIZE: 0 entire data block, 1-8 bit fields, 2-16 bit fields, 3-32 bit fields. The polarity of the SFR pulse can be inverted with SSI_FPOL. If SRDY does not delay it, the first SFR pulse in a frame will rise on the third SCLK after MUX_SYNC (fourth SCLK if 10MHz). MUX_SYNC can be used to synchronize the fields arriving at the data logger or DSP. The pins used for the SSI are multiplexed with the LCD segment outputs, as shown in table 9. Table 9: SSI Pins SSI SIGNAL LCD SEGMENT OUTPUT PIN SCLK SEG3 SSDATA SEG4 SFR SEG5 SRDY SEG6 SRDY is an optional handshake input that indicates that the DSP or data logging device is ready to receive data. SRDY must be high to enable SFR to rise and initiate the transfer of the next field. It is expected that SRDY changes state on the rising edges of SCLK. If SRDY is not high when the SSI port is ready to transmit the next field, transmission will be delayed until it is. SRDY is ignored except at the beginning of a field transmission. If SRDY is not enabled (by SSI_RDYEN), the SSI port will behave as if SRDY is always one. System Timing Summary Figure 6 summarizes the timing relationships between the input MUX states, the CE_BUSY signal, and the two serial output streams. In this example, MUX_DIV=6 and FIR_LEN = 288. Since FIR filter conversions required two or three CK32 cycles, the duration of each MUX frame is 1 + MUX_DIV * 2 if FIR_LEN = 288, and 1 + MUX_DIV * 3 if FIRLEN = 384. Followed by the conversions is a single CK32 cycle. Each CE program pass begins when MUX_SYNC falls. Depending on the length of the CE program, it may continue running until the end of the ADC5 conversion. CE opcodes are constructed to ensure that all CE code passes consume exactly the same number of cycles. The result of each ADC conversion is inserted into the CE DRAM when the conversion is complete. The CE code must be written to tolerate sudden changes in ADC data. The exact CK count when each ADC value is loaded into DRAM is shown in Figure 6. Figure 6 also shows that the two serial data streams, RTM and SSI, begin transmitting at the beginning of MUX_SYNC. RTM, consisting of 140 CK cycles, will always finish before the next code pass starts. The SSI port begins transmitting at the same time as RTM, but may significantly overrun the next code pass if a large block of data is required. Neither the CE nor the SSI port will be affected by this overlap. Rev 2.9 PRELIMINARY DATA SHEET Page: 19 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 Figure 6: Timing relationship between ADC MUX, CE, and Serial Transfers. ADC MUX Frame ADC TIMING MUX_DIV Conversions (MUX_DIV=6 is shown) Settle CK32 150 MUX_SYNC MUX STATE S 0 1 2 3 4 5 S ADC EXECUTION ADC0 CE TIMING 0 ADC1 600 300 ADC2 ADC3 900 1200 ADC4 ADC5 1500 1800 CE_EXECUTION CK COUNT = CE_CYCLES + floor(CE_CYCLES + 2) / 5) MAX CK COUNT CE_BUSY XFER_BUSY INITIATED BY A CE OPCODE AT END OF SUM INTERVAL RTM and SSI TIMING 140 RTM SSI NOTES: LAST SSI TRANSFER BEGIN SSI TRANSFER 1. ALL DIMENSIONS ARE 5MHZ CK COUNTS. 2. THE PRECISE FREQUENCY OF CK IS 150*CRYSTAL FREQUENCY = 4.9152MHz. 3. XFER_BUSY OCCURS ONCE EVERY (PRESAMPS * SUM_CYCLES) CODE PASSES. Fault and Reset Behavior Reset Mode: When RESETZ is pulled low, all digital activity in the chip stops. The exceptions are the oscillator and RTC module which continue to run. Additionally, all IO RAM bits are cleared. As long as V1 > VBIAS, the internal 2.5v regulator will continue to provide power to the digital section. Once initiated, the reset mode will persist until the reset timer times out, signified by WAKE rising. This will occur in 4100 cycles of the real time clock, at which time the MPU will begin executing its preboot and boot sequences from address 00. See the security section for more description of preboot and boot. Power Fault Circuit: The V1 input is connected to the power fault detection circuitry. The output of power fault detection circuit controls WAKE and FAULTZ signals. Upon power fault, WAKE and FAULTZ are both lowered immediately to stop the MPU and engage the battery backup circuit for RTC and MPU DRAM. When power fault ends, FAULTZ rises immediately and disengages the battery backup. The MPU remains in reset and will not start until 4100 OSC clocks later, when WAKE rises. The delay before asserting WAKE permits the MCK PLL to settle. Rev 2.9 PRELIMINARY DATA SHEET Page: 20 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 Battery Operation/Power Save Modes With V3P3 down, the external battery will power the following parts of the 71M6511 via the V2P5 internal voltage: * * * * RTC Crystal oscillator circuitry MPU XRAM WD_OVF bit In normal mode of operation, running on 3.3V supply, various resources of the device may be shut down by the MCU firmware in order to reduce power consumption while other essential resources such as UARTs may remain active. The following list outlines these resources and their typical current consumption: Table 10: Power Saving Measures Rev 2.9 Power Saving Measure Software Control Typical Savings Disable the CE CE_EN = 0 0.16mA Disable the ADC ADC_DIS = 1 1.8mA Disable clock test output CKTEST CKOUTDIS = 1 0.6mA Disable emulator clock ECK_DIS = 1 0.1mA Set flash read pulse timing to 33 ns FLASH66Z =1 0.04mA Disable the LCD voltage boost circuitry LCD_BSTEN = 0 0.9mA Disable RTM outputs RTM_EN = 0 0.01mA Disable SSI output SSI_EN = 0 Select DGND for the multiplexer input TMUX[3:0] = 0 Disable reference voltage output VREF_DIS = 1 Reduce the clock for the MPU MPU_DIV = 5 PRELIMINARY DATA SHEET 0.4mA Page: 21 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 Watchdog Timer In addition to the basic watchdog timer included in the 80515, an independent, robust, fixed duration, watchdog timer (WD) is included in the device. It uses the RTC crystal oscillator as its timebase and requires a firmware reset every 1.5 seconds. When WD overflow occurs, the part is momentarily reset as if RESETZ were pulled low for half of a crystal oscillator cycle. Thus, 4100 cycles later, the MPU will be launched from address 00. A status bit, WD_OVF, is set when WD overflow occurs. This bit is powered by the NV supply and can be read by the MPU when WAKE rises to determine if the part is initializing after a WD overflow event or after a power up. After it is read, MPU firmware must clear WD_OVF. The WD_OVF bit is cleared by the RESETZ pin The watchdog timer also includes an oscillator check. If the crystal oscillator stops or slows down, WD_OVF is set and a system reset will be performed when the crystal oscillator resumes. There is no internal digital state that deactivates the WD. For debug purposes, however, the WD can be disabled by tying the V1 pin to V3P3. Of course, this also deactivates V1 power fault detection. Since there is no firmware way to disable the crystal oscillator or the WD, it is guaranteed that whatever state the part might find itself in, upon watchdog overflow, the part will be reset to a known state. In normal operation, the WD is reset by periodically writing a one to the WDT_RST bit. The watchdog timer is also reset when WAKE=0 and when a 14h command is received from the ICE. Program Security When enabled, the security feature limits ICE to global flash erase only. All other ICE operations are blocked. This guarantees the security of the user's MPU and CE program code. Security is enabled by MPU code that is executed in a 32 cycle preboot interval before the primary boot sequence begins. Once security is enabled, the only way to disable it is to perform a global erase of the flash, followed by a chip reset. Global flash erase also clears the CE program RAM. The first 32 cycles of the MPU boot code is called preboot because it happens while ICE is inhibited. A read-only status bit, PREBOOT, identifies these cycles to the MPU. Upon completion of preboot, the ICE can be enabled and is permitted to take control of the MPU. SECURE, the security enable bit, is reset whenever the chip is reset. Hardware associated with the bit permits only ones to be written to it. Thus, preboot code may set SECURE to enable the security feature but may not reset it. Once SECURE is set, the preboot code is protected and no external read of program code is possible Specifically, when SECURE is set: * * * Rev 2.9 The ICE is limited to bulk flash erase only. Page zero of flash memory, the preferred location for the user's preboot code, may not be page-erased by either MPU or ICE. Page zero may only be erased with global flash erase. Note that global flash erase erases CE program RAM whether SECURE is set or not. Writes to page zero, whether by MPU or ICE are inhibited. PRELIMINARY DATA SHEET Page: 22 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 Voltage Reference Initial Calibration: The internal voltage reference is calibrated during device manufacture. Trim data is stored in on-chip fuses and is not accessible to the user. Temperature Compensation: The internal voltage reference has a predictable temperature dependency that, if not compensated, can result in measurement errors. Two fuse registers, TRIMBGA and TRIMBGB are used to implement temperature compensation. TC1 and TC2 for VREF are calculated from x, where x = (TRIMBGB - TRIMBGA)/10. TRIMBGA and TRIMBGB are read by first writing either 5 or 6 to TRIMSEL (20FD) and then reading the value of TRIM (20FF). The MPU compensates for temperature variation of the reference, along with other system components such as the crystal and the input attenuators, by reading the temperature output of the CE and modifying the gain constants accordingly. Meter Calibration The TDK71M6511 power meter device has to be calibrated for current sensors, voltage dividers and signal conditioning component tolerances. The device can be calibrated using gain and phase adjustment factors. The gain adjustment is used to compensate for tolerances of components used for signal conditioning, especially the resistive components. Phase adjustment is provided to compensate for phase shifts introduced by the current sensors. The readings (Reading1 to Reading 4) below are directly available to the on-chip 80515 and through the ICE and used to perform the calibration. Alternatively, the readings can be obtained from the pulse generator as described in the procedure below. Calibration Procedure: Typically, a meter calibrator is used to apply a calibrated load, e.g. 240V at 30A, while interfacing the voltage and current sensors to the 71M6511. This load should result in an observable pulse rate at the WPULSE output depending on the selected energy per pulse. For example, 7.2kW will result in a pulse rate corresponding to 7200Wh/3600s = 2Wh/s. 1. Apply a load of rated voltage, test current and phase angle of 00 and record the instantaneous values (reading 1) 2. Apply a load of rated voltage, test current and phase angle of 600 lag and record the instantaneous values (reading 2). 3. Apply a load of rated voltage, test current and phase angle of 600 lead and record the instantaneous values (reading 3). 4. Apply a load of rated voltage, test current and phase angle of 1800 lead and record the instantaneous values (reading 4). Calibration Calculations: The accuracy of performance for each step above is to be calculated. Desired performance is always assumed to be 100%. The corresponding terms ERR60, ERR300, ERR0 and ERR180 are derived as the percentage error from the desired accuracy of 100%. A spreadsheet is provided by TDK on the TDK TSC web site to ease calibration. Alternatively, the calibration coefficients can be determined using the formulae below. Rev 2.9 PRELIMINARY DATA SHEET Page: 23 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 Formulae for Phase and Gain Adjust: The calibration constants CAL_I and CAL_V are determined by: G_CORR = -0.5 * (ERR0 + ERR180) CAL_ADJ = 16384 * SQRT (1 + GCORR_x/100) P_CORR = -0.5 * ((ERR60 - ERR300) / (1 + 0.005 * (ERR0 + ERR180))) ANG_ERR = ACOS(0.5 * (1 - (P_CORR/100))) - RADIANS(60) P_ADJ = 220 * 0.02229 * TAN(-ANG_ERR) / (0.1487 - 0.0131 * TAN(-ANG_ERR)) CAL_I = CAL_ADJ / SQRT(1 + (2.5 * 10-8 * P_ADJ + 0.91 * 10-12 * P_ADJ2) / 0.0223) if f0 = 60Hz CAL_V = 16384 * SQRT(1 + (G_CORR/100)) P_ADJ = 220 * 0.0155 * TAN(-ANG_ERR) / (0.1241 - 0.009695 * TAN(-ANG_ERR)) CAL_I -9 = CAL_ADJ / SQRT(1 + (18.5 * 10 * P_ADJ + 0.91 * 10 -12 if f0 = 60Hz if f0 = 50Hz 2 * P_ADJ ) / 0.0155) if f0 = 50Hz Calibration Example: The meter performed the test at 60 degree phase angle with an accuracy of 98.15%. Therefore, ERR60 is (98.15 - 100) = -1.85. Assume, the tests were repeated at other angles and yielded the errors ERR300 = -1.55, ERR0 = -1.69, ERR180 = -1.71. By applying these values we obtain: Calibration Example: At 60Hz the meter performed the test at 60 degree phase angle with an accuracy of 98.15%. Therefore, ERR60 is (98.15 - 100) = -1.85. Assume, the tests were repeated at other angles and yielded the errors ERR300 = -1.55, ERR0 = -1.69, ERR180 = -1.71. By applying these values we obtain: G_CORR CAL_ADJ P_CORR ANG_ERR P_ADJ CAL_I CAL_V = -0.5 * (-1.69 + -1.71) = 1.7 = 16384 * SQRT (1 + 1.7/100) = 16522.7 = -0.5 * (-1.85 - (-1.55)) / (1 + 0.005 * (-1.69 + (-1.71))) = 0.152594 = ACOS(0.5 * (1 - (-0.2134/100))) - 1.047198 = 0.000881 = 220 * (0.02229 * TAN(-0.000881)) / (0.1487 - (0.0131 * TAN(-0.000881))) = -138 = CAL_ADJ / SQRT(1 + (2.5 * 10-8 * (-138) + 9.1 * 10-13 * (-138)2) / 0.0223) = 16523.95 = 16384*(SQRT(1+(1.7 / 100))) = 16522.7 CAL_I, CAL_V and P_ADJ are rounded to the nearest integer values, 16524, 16523, and -138. The calibration factors may first be loaded to RAM to test the accuracy of the meter. For permanent calibration, the calibration factors may be written to Flash memory or to an external I2C EEPROM. Rev 2.9 PRELIMINARY DATA SHEET Page: 24 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 I/O RAM DESCRIPTION - Alphabetical Order Bits with a W (write) direction are written by the MPU into configuration RAM. Typically, they are initially stored in flash memory and copied to the configuration RAM by the MPU. Some of the more frequently programmed bits are mapped to the MPU SFR memory space. The remaining bits are mapped to 2xxx. Bits with R (read) direction can be read by the MPU. On power up, all bits are cleared to zero unless otherwise stated. NAME LOCATIO N DIR DESCRIPTION ADC_DIS 2005[3] R/W Disables ADC and removes bias current CE_EN 2000[4] R/W CE enable. CHOP_EN[1:0] 2002[5:4] R/W Chop enable for the reference band gap circuit. 00-enabled 01-disabled 10-disabled 11-enabled RESERVED 2004[5] R/W Must be 0. CKOUT_DIS 2004[4] R/W CKOUT Disable. When zero, CKTEST is an active output. RESERVED 2003[4:3] R/W Must be 00 DIO_R4[2:0] 200B[2:0] R/W DIO_R5[2:0] 200B[6:4] Connects dedicated I/O pins 4 to 11 to internal resources. If more than one input is connected to the same resource, the `MULTIPLE' column below specifies how they are combined. DIO_R6[2:0] 200C[2:0] DIO_R7[2:0] 200C[6:4] DIO_R8[2:0] 200D[2:0] DIO_R9[2:0] 200D[6:4] DIO_R10[2:0] 200E[2:0] DIO_R11[2:0] 200E[6:4] DIO_GP Resource MULTIPLE 0 NONE -- 1 Reserved OR 2 T0 (Timer0 clock or gate) OR 3 T1 (Timer1 clock or gate) OR 4 High priority IO interrupt (int0 rising) OR 5 Low priority IO interrupt (int1 rising) OR 6 High priority IO interrupt (int0 falling) OR 7 Low priority IO interrupt (int1 falling) OR RESERVED 2009..200A R/W Must be 0000. RESERVED SFRA2[3:0] R/W Must be 1111. Rev 2.9 PRELIMINARY DATA SHEET Page: 25 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 DIO_DIR0[7:4] SFRA2[7:4] R/W Programs the direction of DIO pins 7 through 4. 1 indicates output. Ignored if the pin is not configured as I/O. See DIO_PV and DIO_PW for special option for DIO_6 and DIO_7 outputs. See DIO_EEX for special option for DIO_4 and DIO_5. Note: Bit 0, Bit 1, Bit 2 and Bit 3 must be set to 1. DIO_DIR1[7:6] SFR91 R/W DIO_DIR1[3:0] Programs the direction of DIO pins 15, 14 and 11 through 8. 1 indicates output. Ignored if the pin is not configured as I/O. Note: Bit 4 and Bit 5 must be set to 1. DIO_DIR2[1:0] SFRA1[5:0] R/W Programs the direction of DIO pins 17 and 16. 1 indicates output. Ignored if the pin is not configured as I/O. Note: Bit 2, Bit 3, Bit 4 and Bit 5 must be set to 1. DIO_0[7:4] SFR80 DIO_1[7:6], SFR90 R/W The value on the DIO pins. Pins configured as LCD will read zero. When written, changes data on pins configured as outputs. Pins configured as LCD or input will ignore writes. DIO_1[3:0] DIO_2[1:0] SFRA0[1:0] DIO_EEX 2008[4] R/W When set, converts DIO_4 and DIO_5 to interface with external EEPROM. DIO_4 becomes SDCK and DIO_5 becomes bidirectional SDATA. LCD_NUM must be less than 17. DIO_PV 2008[2] R/W Causes VARPULSE to be output on DIO_7, if DIO_7 is configured as output. LCD_NUM must be less than 15. DIO_PW 2008[3] R/W Causes WPULSE to be output on DIO_6, if DIO_6 is configured as output. LCD_NUM must be less than 16. EEDATA[7:0] SFR9E R/W Serial EEPROM interface data EECTRL[7:0] SFR9F R/W Serial EEPROM interface control ECK_DIS 2005[5] R/W Emulator clock disable. When one, the emulator clock is disabled. EQU[2:0] 2000[7:5] R/W Specifies the power equation. EX_XFR 2002[0] R/W EX_RTC 2002[1] Interrupt enable bits. These bits enable the XFER_BUSY and the RTC_1SEC interrupts. Note that if either interrupt is to be enabled, EX6 in the 80515 must also be set. FIR_LEN 2005[4] R/W The length of the ADC decimation FIR filter. 1 - 22 ADC bits/3 CK32 cycles 0 - 21 ADC bits/2 CK32 cycles Rev 2.9 PRELIMINARY DATA SHEET Page: 26 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 FLASH66Z 2005[1] R/W Should be set to 1 to minimize power supply current. FLSH_ERASE SFR94 W Flash Erase Initiate FLSH_ERASE is used to initiate either the Flash Mass Erase cycle or the Flash Page Erase cycle. Specific patterns are expected for FLSH_ERASE in order to initiate the appropriate Erase cycle. (default = 0x00). 0x55 - Initiate Flash Page Erase cycle. Must be proceeded by a write to FLSH_PGADR @ sfr 0xB7. 0xAA - Initiate Flash Mass Erase cycle. Must be proceeded by a write to FLSH_MEEN @ sfr 0xB2 and the debug (CC) port must be enabled. Any other pattern written to FLSH_ERASE will have no effect. FLSH_MEEN SFRB2[1] W Mass Erase Enable 0 - Mass Erase disabled (default). 1 - Mass Erase enabled. Must be re-written for each new Mass Erase cycle. FLSH_PGADR SFRB7[7:1] W Flash Page Erase Address FLSH_PGADR[6:0] - Flash Page Address (page 0 thru 127) that will be erased during the Page Erase cycle. (default = 0x00). Must be re-written for each new Page Erase cycle. FLSH_PWE SFRB2[0] R/W Program Write Enable 0 - MOVX commands refer to External RAM Space, normal operation (default). 1 - MOVX @DPTR,A moves A to External Program Space (Flash) @ DPTR. This bit is automatically reset after each byte written to flash. Writes to this bit are inhibited when interrupts are enabled. IE_XFER SFRE8[0] IE_RTC SFRE8[1] INTBITS LCD_BSTEN Rev 2.9 R/W Interrupt flags. These flags monitor the XFER_BUSY interrupt and the RTC_1SEC interrupt. The flags are set by hardware and must be cleared by the interrupt handler. Note that IE6, the interrupt 6 flag bit in the 80515 must also be cleared when either of these interrupts occur. SFRF8[6:0] R Interrupt inputs. The MPU may read these bits to see the input to external interrupts INT0, INT1, up to INT6. These bits do not have any memory and are primarily intended for debug use. 2020[7] R/W Enables the LCD voltage boost circuit. PRELIMINARY DATA SHEET Page: 27 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 LCD_CLK[1:0] 2021[1:0] R/W Sets the LCD clock frequency. Note: fw = CKADC/128 00-fw/2^9, 01-fw/2^8, 10-fw/2^7, 11-fw/2^6 LCD_EN 2021[5] R/W Enables the LCD display. When disabled, VLC2, VLC1, and VLC0 are ground as are the COM and SEG outputs. LCD_FS[4:0] 2022[4:0] R/W The LCD full scale voltage, VLC2. 00 is (0.7 * VLCD) and 1F is VLCD LCD_MODE[2:0] 2021[4:2] R/W The LCD bias mode: 000-4 states, 1/3 bias 001-3 states, 1/3 bias 010-2 states, 1/2 bias 011-3 states, 1/2 bias 100-static display LCD_NUM[4:0] 2020[4:0] R/W Controls the number of dual-purpose LCD/DIO pins to be configured as LCD. LCD_NUM will be between 0 and 18. The first dual-purpose pin to be allocated as LCD is SEG37/DIO17. The table below lists which SEG and DIO functions are selected for each LCD_NUM value. LCD_NUM 1-4 Rev 2.9 SEG DIO None DIO4-11, DIO14-17 5 SEG37 DIO4-11, DIO14-16 6 SEG36-37 DIO4-11, DIO14-15 7 SEG35-37 DIO4-11, DIO14 8-10 SEG34-37 DIO4-11 11 SEG34-37, SEG31 DIO4-10 12 SEG34-37, SEG30-31 DIO4-9 13 SEG34-37, SEG29-31 DIO4-8 14 SEG34-37, SEG28-31 DIO4-7 15 SEG34-37, SEG27-31 DIO4-6 16 SEG34-37, SEG26-31 DIO4-5 17 SEG34-37, SEG25-31 DIO4 18 SEG34-37, SEG24-31 None PRELIMINARY DATA SHEET Page: 28 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 LCD_SEG0[3:0]- 2030[3:0]- LCD_SEG19[3:0], 2043[3:0], LCD_SEG24[3:0]- 2048[3:0]- LCD_SEG31[3:0], 204f[3:0], LCD_SEG34[3:0]- 2052[3:0]- LCD_SEG37[3:0], 2055[3:0] MPU_DIV[2:0] 2004[2:0] R/W LCD Segment Data. Each word contains information for from 1 to 4 time divisions of each segment. In each word, bit 0 corresponds to COM0, on up to bit 3 for COM3. R/W The MPU clock divider (from CKCE). These bits may be programmed by MPU without risk of losing control. 000-CKCE, 001-CKCE/2, ..., 111-CKCE/27 MUX_ALT 2005[2] R/W The MPU asserts this bit when it wishes the MUX to perform ADC conversions on an alternate set of inputs. MUX_DIV[1:0] 2002[7:6] R/W The number of states in the input mux. 00-6 states 10-3 states 11-2 states MUX_E 2005[0] R/W MUX_SYNC enable. When high, converts SEG7 into a MUX_SYNC output. OPT_TXDIS 2008[5] R/W Tristates the OPT_TX output. PREBOOT SFRB2[7] R Indicates that preboot sequence is active. PRE_SAMPS[1:0] 2001[7:6] R/W Together w/ SUM_CYCLES, this value determines the number of samples in one sum cycle between XFER interrupts. Number of cycles = PRE_SAMPS*SUM_CYCLES. 01-4 states 00-42, 01-50, 10-84, 11-100 RTC_SEC[5:0] 2015 RTC_MINI[5:0] 2016 RTC_HR[4:0] 2017 RTC_DAY[2:0] 2018 RTC_DATE[4:0] 2019 RTC_MO[3:0] 201A RTC_YR[7:0] 201B Rev 2.9 R/W The RTC interface. These are the `year', `month', `day', `hour', `minute' and `second' parameters for the RTC. The RTC is set by writing to these registers. Year 00 is defined as a leap year. SEC 00 to 59 MIN 00 to 59 HR 00 to 23 (00=Midnight) DAY 01 to 07 (01=Sunday) DATE 01 to 31 MO 01 to 12 YR 00 to 255 PRELIMINARY DATA SHEET Page: 29 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 RTC_DEC_SEC 201C[1] W RTC time correction bits. Only one bit may be pulsed at a time. When pulsed, causes the RTC time value to be incremented (or decremented) by an additional second the next time the RTC_SEC register is clocked. The pulse width may be any value. If an additional correction is desired, the MPU must wait 2 seconds before pulsing one of the bits again. RTC_INC_SEC 201C[0] RTM_EN 2002[3] R/W Real Time Monitor enable. When `0', the RTM output is low. This bit enables the two wire version of RTM RTM0[7:0] 2060 R/W RTM1[7:0] 2061 Four RTM probes. Before each CE code pass, the values of these registers are serially output on the RTM pin. The RTM registers are ignored when RTM_EN=0. RTM2[7:0] 2062 RTM3[7:0] 2063 SECURE SFRB2[6] R/W Enables security provisions that prevent external reading of flash memory and CE program RAM. This bit is reset on chip reset and may only be set. Attempts to write zero are ignored. SSI_EN 2070[7] R/W Enables the Synchronous Serial Interface (SSI) on SEG3, SEG4, and SEG5 pins. If SSI_RDYEN is set, SEG6 is enabled also. The pins take on the new functions SCLK, SSDATA, SFR, and SRDY, respectively. When SSI_EN is high and LCD_EN is low, these pins are converted to the SSI function, regardless of LCDEN and LCD_NUM. For proper LCD operation, SSI_EN must not be high when LCD_EN is high. SSI_10M 2070[6] R/W SSI clock speed: 0-5MHz 1-10MHz SSI_CKGATE 2070[5] R/W SSI gated clock enable. When low, the SCLK is continuous. When high, the clock is held low when data is not being transferred. SSI_FSIZE[1:0] 2070[4:3] R/W SSI frame pulse format: 0-once at beginning of SSI sequence. 1-every 8 bits. 2-every 16 bits. 3-every 32 bits. SSI_FPOL 2070[2] R/W SFR pulse polarity: 0-positive 1-negative SSI_RDYEN 2070[1] R/W SRDY enable. If SSI_RDYEN and SSI_EN are high, the SEG6 pin is configured as SRDY. Otherwise, it is an LCD driver. SSI_RDYPOL 2070[0] R/W SRDY polarity: 0-positive 1-negative SSI_BEG[7:0] 2071[7:0] R/W SSI_END[7:0] 2072[7:0] The beginning and ending address of the transfer region of the CE data memory. If Synchronous Serial Interface is enabled, a block of words starting with SSI_BEG and ending with SSI_END will be sent. SSI_END must be equal or larger than SSI_BEG. The maximum number of output words is limited by the number of SSI clocks in a CE code pass--see FIR_LEN, MUX_DIV, and SSI_10M. Rev 2.9 PRELIMINARY DATA SHEET Page: 30 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 SUM_CYCLES [5:0] 2001[5:0] R/W Together w/ PRE_SAMPS, this value determines the number of samples in one sum cycle between XFER interrupts. Number of cycles = PRE_SAMPS*SUM_CYCLES. TMUX[3:0] 2000[3:0] R/W Selects one of 16 inputs for TMUXOUT. 0 - DGND (analog) 1 - IBIAS (analog) 2 - PLL_2.5v (analog) 3 - VBIAS (analog) 4 - RTM (Real time output from CE) 5 - WDTR_EN (Comparator 1 Output AND V1LT3) 6 - Reserved 7 - Reserved 8 - RXD (from Optical interface) 9 - MUX_SYNC (from MUX_CTRL) A - CK_10M B - CK_MPU C - PULSE_OUT D - RTCLK E - CE_BUSY F - XFER_BUSY RESERVED 2005[7] R/W Must be Zero. VERSION[7:0] 2006 R The silicon revision number. This data sheet does not apply to revisions 000 0010. VREF_CAL 2004[7] R/W Makes voltgae reference available to VREF pin. This feature is disabled when VREF_DIS=1. VREF_DIS 2004[3] R/W Disables the internal voltage reference. WD_RST SFRE8[7] W Reset the WD timer. The WD is reset when a 1 is written to this bit. WD_OVF 2002[2] R/W The WD overflow status bit. This bit is set when the WD timer overflows. It is powered by the NV supply and at bootup will indicate if the part is recovering from a WD overflow or a power fault. This bit should be cleared by the MPU on bootup. It is also automatically cleared when RESETZ is low. Rev 2.9 PRELIMINARY DATA SHEET Page: 31 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 I/O RAM MAP - Ordered by Function `Not Used' bits blacked-out in the following table, contain no memory and are read by the MPU as zero. RESERVED bits are in use and should not be changed. Name Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Configuration: CE0 2000 EQU[2:0] CE_EN TMUX[3:0] CE1 2001 PRE_SAMPS[1:0] SUM_CYCLES[5:0] CE2 2002 MUX_DIV[1:0] CHOP_EN[1:0] RTM_EN WD_OVF EX_RTC EX_XFR COMP0 2003 RESERVED RESERVED CONFIG0 2004 VREF_CAL RESERVED CKOUT_DIS VREF_DIS MPU_DIV CONFIG1 2005 RESERVED ECK_DIS FIR_LEN ADC_DIS MUX_ALT FLSH66Z MUX_E VERSION 2006 VERSION[7:0] Digital I/O: DIO0 2008 OPT_TXDIS DIO_EEX DIO_PW DIO_PV DIO1 2009 RESERVED RESERVED DIO2 200A RESERVED RESERVED DIO3 200B DIO_R5[2:0] DIO_R4[2:0] DIO4 200C DIO_R7[2:0] DIO_R6[2:0] DIO5 200D DIO_R9[2:0] DIO_R8[2:0] DIO6 200E DIO_R11[2:0] DIO_R10[2:0] DIO7 SFR80 DIO_0[7:4] RESERVED DIO8 SFRA2 DIO_DIR0[7:4] 1111 DIO9 SFR90 DIO_1[7:6] RESERVED DIO_1[3:0] DIO10 SFR91 DIO_DIR1[7:6] 11 DIO_DIR1[3:0] DIO11 SFRA0 RESERVED DIO_2[1:0] DIO12 SFRA1 1111 DIO_DIR2[1:0] Interrupts and WD Timer: INTBITS SFRF8 INT6 INT5 INT4 INT3 INT2 INT1 INT0 WDI SFRE8 WD_RST IE_RTC IE_XFER Flash: ERASE SFR94 FLSH_ERASE[7:0] FLSHCTL SFRB2 PREBOOT SECURE FLSH_MEEN FLSH_PWE PGADR SFRB7 FLSH_PGADR[6:0] Real Time Clock: RTC0 2015 RTC_SEC[5:0] RTC1 2016 RTC_MIN[5:0] RTC2 2017 RTC_HR[4:0] RTC3 2018 RTC_DAY[2:0] RTC4 2019 RTC_DATE[2:0] RTC5 201A RTC_MO[3:0] RTC6 201B RTC_YR[7:0] RTC_DEC_SEC RTC_INC_SEC RTC7 201C LCD Display Interface: LCDX 2020 LCD_BSTEN LCD_NUM[4:0] LCDY 2021 LCD_EN LCD_MODE[2:0] LCD_CLK[1:0] LCDZ 2022 LCD_FS[4:0] RESERVED:SEG20-23,32-33,38-41 Rev 2.9 PRELIMINARY DATA SHEET Page: 32 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 LCD0 LCD1 ... LCD19 LCD20 LCD21 LCD22 LCD23 LCD24 LCD25 LCD26 LCD27 LCD28 LCD29 LCD30 LCD31 LCD32 LCD33 LCD34 LCD35 LCD36 LCD37 LCD38 LCD39 LCD40 LCD41 2030 2031 ... 2043 2044 2045 2046 2047 2048 2049 204A 204B 204C 204D 204E 204F 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 RTM0 RTM1 RTM2 RTM3 2060 2061 2062 2063 SSI 2070 SSI_BEG 2071 SSI_END 2072 EEDATA SFR9E EECTRL SFR9F Rev 2.9 ... SSI_EN RTM Probes: RTM0[7:0] RTM1[7:0] RTM2[7:0] RTM3[7:0] Synchronous Serial Interface: SSI_10M SSI_CKGATE SSI_FSIZE[1:0] SSI_BEG[7:0] SSI_END[7:0] Serial EEPROM: EEDATA[7:0] EECTRL[7:0] PRELIMINARY DATA SHEET LCD_SEG0[3:0] LCD_SEG1[3:0] ... LCD_SEG19[3:0] RESERVED RESERVED RESERVED RESERVED LCD_SEG24[3:0] LCD_SEG25[3:0] LCD_SEG26[3:0] LCD_SEG27[3:0] LCD_SEG28[3:0] LCD_SEG29[3:0] LCD_SEG30[3:0] LCD_SEG31[3:0] RESERVED RESERVED LCD_SEG34[3:0] LCD_SEG35[3:0] LCD_SEG36[3:0] LCD_SEG37[3:0] RESERVED RESERVED RESERVED RESERVED SSI_FPOL SSI_RDYEN SSI_RDYPOL Page: 33 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 CE Data Memory All CE words are 4 bytes. Unless specified otherwise, they are in 32-bit two's complement. `Calibration' parameters are defined in flash memory and are copied to CE memory by the MPU before enabling the CE. `Internal' variables are used in internal CE calculations. `Input' variables allow the MPU to control the behavior of the CE code. `Output' variables are outputs of the CE calculations. CE data memory is mapped to the MPU address space as shown in the MPU column. The MPU address is the most significant byte. Constants used in the CE Data Memory table are: FS 32768 / 13 2520.6 Hz . F0 is the fundamental frequency. IMAX is the external rms current corresponding to 250mV pk at inputs IA and IB. VMAX is the external rms voltage corresponding to 250mV pk at input VA. Accumulation time for energy measurements is PRE_SAMPS*SUM_CYCLES/FS. NAME ADDRESS CE MPU DESCRIPTION ADC Input Data: I_RAW 0 1000 V_RAW 1 1004 I1_RAW3 2 1008 Input data from ADC, valid at end of MUX frame. These addresses RESERVED 3 100C are hard-wired in the ADC converter circuit. RESERVED 4 1010 RESERVED 5 1014 TEMP 6 1018 RESERVED 7 101C CE Calibration Parameters: (Assignments to address 8 and higher describe CE code and are not hardwired) CAL_I0 8 1020 These two constants control the gain of their respective channels. CAL_V0 9 1024 The nominal value for each parameters is 214=16384. The gain of CAL_I1 A 1028 each channel is directly proportional to its CAL parameter. Thus, if RESERVED B 102C the gain of a channel is 1% slow, CAL should be increased by 1%. RESERVED C 1030 RESERVED PHADJ_0 D 1034 E 1038 PHADJ_1 RESERVED TEMP_NOM F 10 11 103C 1040 1044 Rev 2.9 These two constants control the CT phase compensation. No compensation occurs when PHADJ=0. As PHADJ is increased, more compensation is introduced. TEMP_RAWX reading at calibration temperature PRELIMINARY DATA SHEET Page: 34 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 CE Input Data: I0SHUNT I1SHUNT 2B 2C 10AC 10B0 WRATE 2D 10B4 RESERVED QUANT RESERVED 2E 2F 30 10B8 10BC 10C0 SAG_THR 31 10C4 SAG_CNT 32 10C8 RESERVED QUANT_VAR QUANT_I SUMPRE 33 34 35 36 10CC 10D0 10D4 10D8 EXT_PULSE 37 10DC RESERVED RESERVED RESERVED RESERVED 38 39 3A 3B 10E0 10E4 10E8 10E8 APULSEW 5B 116C APULSER 5C 1170 Rev 2.9 When positive, 8x gain is applied to the I0 channel When positive, 8x gain is applied to the I1 channel Kh=VMAX*IMAX*4.11021*10-3*16384/(WRATE*3600) = IMAX*VMAX*0.018706/WRATE Wh/pulse. Default is 16384. Compensation for truncation in CE code. Default is 0. V inputs must be above this threshold to prevent sag alarms. LSB = 2.35*10-9 VMAX Volts. Default is 26000. Number of consecutive voltage samples below SAG_THR before a sag alarm is declared. Default is 80. Compensation for truncation in VAR calculation. Default is 0. Compensation for truncation in I2 and V2 calculation. Product of PRE_SAMPS and SUM_CYCLE. Default is 2520. Should be 15 or 0. When zero, causes pulse generators to respond to WSUM_X and VARSUM_X. Otherwise, they respond to values the host places in APULSEW and APULSER. Default is 15 (host driven). Watt pulse generator input (see DIO_PW bit). Output pulse rate is: APULSEW*FS*2-32*WRATE*2-14. This input is buffered and can be loaded during a computation interval and will take effect at the beginning of the next interval. Default value is 0. VAR pulse generator input (see DIO_PV bit). Output pulse rate is: APULSER*FS*2-32*WRATE*2-14. This input is buffered and can be loaded during a computation interval and will take effect at the beginning of the next interval. Default value is 0. PRELIMINARY DATA SHEET Page: 35 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 CE Outputs: TEMP_X 40 1100 Deviation from Calibration temperature. LSB = 0.1 0C. FREQ_X 41 1104 Fundamental frequency. LSB RESERVED W0SUM_X W1SUM_X RESERVED VARSUM_X VAR0SUM_X VAR1SUM RESERVED I0SQSUM_X I1SQSUM_X RESERVED RESERVED V0SQSUM_X RESERVED RESERVED RESERVED RESERVED 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 52 53 1108 110C 1110 1114 1118 111C 1120 1124 1128 112C 1130 1134 1138 113C 1140 1148 114C TEMP_RAW_X 54 1168 CE Status: CE Status Word 51 1144 Rev 2.9 FS 0.587 10 - 6 Hz 32 2 The sum of Watt samples from each wattmeter element. LSB = 6.6972*10-13 VMAX IMAX Wh The signed sum: VAR0SUM_X The sum of VAR samples from each wattmeter element. LSB = 6.6972*10-13 VMAX IMAX Wh The sum of squared current samples from each element. LSB = 6.697210-13 IMAX2 A2h The sum of squared voltage samples from each element. LSB= 6.6972*10-13 VMAX2 V2h Filtered, unscaled reading from the temperature sensor. This value should be written to TEMP_NOM during meter calibration. This word contains sag warnings for phase A, B, and C, as well as F0, the derived clock operating at the fundamental input frequency. The CE STATUS Word contains information about events that occurred during the immediately preceding code pass. PRELIMINARY DATA SHEET Page: 36 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 CE Internal Data: First CE 5D Address ... ... Last CE FF Address 1174 First CE memory location ... 13FC ... Last CE memory location CE Status Word: The CE Status Word minimizes the computation required in the interrupt handler of the MPU (CE_BUSY interrupt occurs at 2520.6Hz). It contains sag warnings for phase A, B, and C, as well as F0, the derived clock operating at the fundamental input frequency. The CE STATUS word contains information about events that occured during the immediately preceding code pass. BIT NAME 31-29 Not Used 28 F0 27 RESERVED 26 RESERVED 25 SAG_A 24-0 Not Used Rev 2.9 DESCRIPTION These unused bits will always be zero. F0 is a square wave at the exact fundamental input frequency. Normally zero. Becomes one when VA remains below SAGTHR for SAGCNT samples. Will not return to zero until VA rises above SAG_THR. These unused bits will always be zero. PRELIMINARY DATA SHEET Page: 37 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 MPU Data Memory (XRAM) NAME ADDRESS TYPE DESCRIPTION First MPU Address 0000 MPU First MPU XRAM location ... 0xxx MPU ... Last MPU Address 07FF MPU Last internal MPU XRAM location Certain MPU XRAM parameters have been given fixed addresses in order to permit easy external modification of the meter behavior. These parameters are loaded by the MPU at startup and should not need adjustment during meter calibration. These parameters are defined and implemented in MPU code. MPU Input Parameters: MPU Word Name Address Address 0 0 CREEP_THR Description For each element, if WSUM_X or VARSUM_X of that element exceeds CREEP_THR, the sample values for that element are not zeroed. Otherwise, the accumulators for Wh, VARh, and VAh are not updated and the instantaneous value of IRMS for that element is zeroed. LSB = 6.69722*10-13 VMAX IMAX Wh Bit 0: Sets VA calculation mode. 1 4 CONFIG 0-VRMS*ARMS 1- W 2 + VAR 2 Bit 1: Clears accumulators for Wh, VARh, VAh. This bit need not be reset. 2 8 PK_VTHR When the voltage exceeds this value, the MPU might choose to log a warning. Event logs are not implemented in `demo' code. LSB=0.1VRMS 3 C PK_ITHR When the current exceeds this value, the MPU might choose to log a warning. Event logs are not implemented in `demo' code. LSB=0.1ARMS 4 10 Y_CAL 5 14 Y_CALC 6 Rev 2.9 18 Y_CALC2 The values in these locations implement RTC trim using the following formula: CORRECTION( ppm) = PRELIMINARY DATA SHEET Y _ CAL Y _ CALC Y _ CALC 2 +T +T2 10 100 1000 Page: 38 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 PULSEW source and PULSER source. Values are: 7 1C PULSEW_SRC 8 20 PULSER_SRC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 9 24 VMAX The nominal external RMS voltage that corresponds to 250mV pk at the ADC input. The meter uses this value to convert internal quantities to external. LSB=0.1V A 28 IMAX The nominal external RMS current that corresponds to 250mv pk at the ADC input. The meter uses this value to convert internal quantities to external. LSB=0.1A PPMC PPM/C*26.84. Linear temperature compensation. A positive value will cause the meter to run faster when hot. This is applied to both V and I and will therefore have a double effect on products. Default is 0. PPMC2 PPM/C2*1374. Square law compensation. A positive value will cause the meter to run faster when hot. This is applied to both V and I and will therefore have a double effect on products. Default is 0. B C 2C 30 - - - WSUM W0SUM W1SUM W2SUM VARSUM VAR0SUM VAR1SUM VAR2SUM I0SQSUM I1SQSUM I2SQSUM INSQSUM V0SQSUM V1SQSUM V2SQSUM VASUM VA0SUM VA1SUM VA2SUM Scale factor for TEMP_X. D 34 DEGSCALE TEMP_X=DEGSCALE*2-22*(TEMP_RAW_X - TEMP_NOM). Default is 9879. Rev 2.9 PRELIMINARY DATA SHEET Page: 39 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Supplies and Ground Pins: V3P3D, V3P3A VLCD VBAT GNDD Analog Output Pins: -0.5V to 4.6V -0.5V to 7V -0.5V to 4.6V -0.5V to +0.5V -1mA to 1mA, -0.5V to V3P3A+0.5V -1mA to 1mA, -0.5V to 3.0V VREF, VBIAS V2P5 Analog Input Pins: IA, VA, IB, V1 XIN, XOUT OPT_RX All Other Pins: All other pins -0.5V to V3P3A+0.5 -0.5V to 3.0V -1mA to 1mA -0.5V to V3P3D+0.5V Operating junction temperature (peak, 100ms) Operating junction temperature (continuous) Storage temperature Solder temperature - 10 second duration 140 C 125 C -45 C to 165 C 250 C Stresses beyond Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GNDA. RECOMMENDED EXTERNAL COMPONENTS NAME C1 C2 FROM V3P3A V3P3D TO AGND DGND XTAL XIN XOUT CXS XIN AGND CXL XOUT AGND CBIAS CBST1 CBST2 VBIAS VDRV VLCD AGND external DGND Rev 2.9 FUNCTION Bypass capacitor for 3.3V supply Bypass capacitor for 3.3V supply 32.768kHz crystal. Electrically similar to Ecliptek (www.ecliptek.com) ECPSM310T series Load capacitor for crystal (depends on crystal specs and board parasitics). Load capacitor for crystal (depends on crystal specs and board parasitics). Bypass capacitor for VBIAS Boost charging capacitor Boost bypass capacitor PRELIMINARY DATA SHEET VALUE 0.120% 0.120% UNIT F F 32.768 kHz 1010% pF 1010% pF 100020% 3320% 0.2220% pF nF F Page: 40 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 RECOMMENDED OPERATING CONDITIONS PARAMETER 3.3V Supply Voltage (V3P3A, V3P3D) CONDITION Normal Operation Battery Backup VLCD No Battery Battery Backup VBAT Operating Temperature MIN TYP MAX UNIT 3.0 3.3 3.6 V 0 3.45 V 2.9 5.5 V Externally Connect to V3P3D 2.0 3.8 V -40 85 C PERFORMANCE SPECIFICATIONS LOGIC LEVELS PARAMETER Digital high-level input voltage, VIH Digital low-level input voltage, VIL Digital high-level output voltage VOH CONDITION ILOAD = 1mA ILOAD = 15mA Digital low-level output voltage VOL Input pull-up current, IIL RESETZ E_RXTX, CKTEST , E_RST Other digital inputs Input pull down current, IIH TEST ILOAD = 1mA ILOAD = 15mA VIN=0V TYP MAX V3P3D 0.8 UNIT V V V3P3D V V 0.4 0.8 V V 10 10 10 -1 100 100 100 1 A A A A 10 10 -1 100 100 1 A A A VIN=V3P3D Other digital inputs Rev 2.9 MIN 2 -0.3 V3P3D -0.4 V3P3D -0.6 0 PRELIMINARY DATA SHEET Page: 41 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 SUPPLY CURRENT PARAMETER V3P3A + V3P3D + VLCD current V3P3A current V3P3D current VLCD current VBAT current V3P3A + V3P3D current V3P3D current, Write Flash VBAT current, VBAT=3.6V CONDITION Normal Operation, V3P3A=V3P3D=VLCD=3.3V CKMPU=614kHz VBAT=3.6V No Flash memory write Power save/sleep mode V3P3A=V3P3D=VLCD=3.3V Normal Operation as above, except write Flash at maximum rate. Battery backup, V3P3A=V3P3D=VLCD=0V MIN 7.89 3.7 4.1 0.04 -300 TYP 8.74 3.9 4.79 0.05 MAX 10.4 4.2 5.8 0.4 300 UNIT mA mA mA mA nA 6 7 mA 8 mA 4 A 2 VREF, VBIAS Unless otherwise specified, VREF_DIS=0 PARAMETER CONDITION MIN TYP MAX Ta = 22C 1.193 1.195 1.197 VREF output voltage, VNOM(25) 40 VREF chop step CAL =1, 2.5 VREF output impedance ILOAD = 10A, -10A 2 A VNOM(T) = VREF(22) + (T-22)TC1 + (T-22) TC2 VNOM definition -- If TRIMBGA and TRIMBGB available (6511H) -VREF temperature coefficients TRIMBGB- TRIMBGA x= 14.95x + 19 TC1 10 0.0174x - 0.307 TC2 VREF(T) deviation from VNOM(T) VREF(T ) - VNOM (T ) 106 -10 10 VNOM max(| T - 22 |,40) (For 71M6511H version only) -- If TRIMBGA and TRIMBGB not available (6511) -VREF temperature coefficients -6.68 TC1 -0.341 TC2 VREF(T) deviation from VNOM(T) VREF(T ) - VNOM (T ) 106 Ta = -40C to +85C -40 +40 VNOM max(| T - 22 |,40) (For 71M6511H version only) Ta = 25C (-1%) 1.5 (+1%) VBIAS output voltage Ta = -40C to 85C (-2%) 1.5 (+2%) ILOAD = 1mA, -1mA 240 500 VBIAS output impedance A This relationship describes the nominal behavior of VREF at different temperatures. Rev 2.9 PRELIMINARY DATA SHEET UNIT V mV k V ppm/C ppm/C2 ppm/C ppm/C ppm/C ppm/C V V Page: 42 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 2.5V VOLTAGE REGULATOR Unless otherwise specified, load = 5mA PARAMETER Voltage overhead V3P3-V2P5 PSSR V2P5/V3P3 CONDITION Reduce V3P3 until V2P5 drops 200mV ResetZ=1, iload=0 MIN TYP MAX UNIT 250 mV +3 mV/V MAX UNIT -15 15 mV 0.8 1.2 A 2 -400 15 -30 s mV MAX UNIT -3 COMPARATORS PARAMETER Offset Voltage V1-VBIAS Hysteresis Current V1 Response Time V1 WD Disable Threshold (V1-V3P3A) CONDITION Vin = VBIAS - 100mV +100mV overdrive MIN TYP FLASH MEMORY TIMING PARAMETER Write Time per Byte CONDITION MIN TYP 42 s 20 ms 200 ms Read Time: No wait states Page Erase (512 bytes) Mass Erase Rev 2.9 PRELIMINARY DATA SHEET Page: 43 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 ADC CONVERTER, VDD REFERENCED FIR_LEN=0, VREF_DIS=0, VDDREFZ=0 PARAMETER Recommended Input Range (Vin-V3P3A) CONDITION Voltage to Current Crosstalk: Vin = 200mV peak, 65Hz, on VA, VB, or VC 10 6 *Vcrosstalk cos(Vin - Vcrosstalk ) Vcrosstalk = largest Vin measurement on IA, IB, or IC THD (First 10 harmonics) Vin=65Hz, 250mV-pk 64kpts FFT, Blackman20mV-pk Harris window Input Impedance Vin=65Hz LSB size Digital Full Scale ADC Gain Error vs %Power Supply Variation Vin=200mV pk, 65Hz 10 6 Nout PK 357 nV / VIN V3P3A=3.0V, 3.6V MIN TYP MAX UNIT mV peak -250 250 -10 10 V/V 60 -75 -90 90 dB dB k nV/LSB LSB 357 +884736 50 ppm/ % 10 mV 100 V 3P3 A / 3.3 -10 Input Offset (Vin-V3P3A) CRYSTAL OSCILLATOR Crystal is disconnected. Test load is series 200pF, 100k connected between DGND and XOUT. PARAMETER CONDITION MIN TYP MAX UNIT S4 Vin=32.8kHz, 5 50 10mV-pp sin, (mho) Transconductance measure voltage 4.5 50 mV-pp across 100k Vin=0V to 0.1V step Bias Settling Time, 10% 0.05 4 ms CL20pF I(XOUT) when 0.25 1 A Peak Output Source Current XOUT=0V Vin=0.2V-pp sin wave, 1.5 V Maximum Output Voltage 32.8kHz, no test load Maximum Output Power to Crystal4 Crystal connected 1 W Xin to Xout Capacitance1 3 pF Capacitance to DGND1 Xin 5 pF Xout 5 pF Watchdog RTC_OK threshold 25 kHz Rev 2.9 PRELIMINARY DATA SHEET Page: 44 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 OPTICAL INTERFACE PARAMETER OPT_TX VOH (V3P3D-OPT_TX) OPT_TX VOL OPT_RX Vin Threshold (VinRISING+VinFALLING)/2 OPT_RX Vin Hysteresis (VinRISING-VinFALLING) OPT_RX input impedance CONDITION ISOURCE=1mA ISINK=20mA MIN TYP MAX 0.4 0.7 UNIT V V 200 250 300 mV 30 mV 5 |Vin|300mV 1 M TEMPERATURE SENSOR PARAMETER Nominal Sensitivity (Sn)4 Nominal Offset (Nn) 4 Temperature Error 1 ERR = (T - 25) - ( N (T ) - N (25)) Sn CONDITION TA=25C, TA=75C Nominal relationship: N(T)= Sn*T+Nn MIN TA = -40C to +85C -3 TYP -923 MAX 428500 UNIT LSB/C LSB 3 C MAX 2.7 2.6 5.5 UNIT Hz mA mA V 450 A LCD BOOST PARAMETER VDRV Frequency VDRV Sink Current VDRV Source Current VLCD Target Voltage VLCD Input Current CONDITION Vol=1.5V Voh=1.5V VLCD=5.0V, LCD_FS=1F, LCD_MODE=0,1,2,3 MIN 1.2 1.2 4.5 TYP OSC/2 LCD DRIVERS Applies to all COM and SEG pins. Unless otherwise stated, VLCD=5.0V, LCD_FS=1F CONDITION PARAMETER MIN TYP MAX VLC0 Max Voltage (LCD_FS =1F) With respect to VLCD -0.2 0 VLC0 Min Voltage (LCD_FS =00) With respect to VLCD*0.7 -0.2 0.2 Rev 2.9 PRELIMINARY DATA SHEET UNIT V V Page: 45 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 FOOTNOTES 1 This spec is guaranteed, has been verified in production samples, but is not measured in production. 2 This spec is guaranteed, has been verified in production samples, but is measured in production only at DC. 3 This spec is measured in production at the limits of the specified operating temperature. 4 This spec defines a nominal relationship rather than a measured parameter. Correct circuit operation is verified with other specs that use this nominal relationship as a reference. Rev 2.9 PRELIMINARY DATA SHEET Page: 46 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 Figure 7: 71M6511H WH accuracy performance Test Time = 7s when I>3.0A @ Test Time = 7s when I>1.0A @ 100.6 IEC 62053-22, ANSI C12.20-1998, class 02 Accuracy (%) 100.4 100.2 PH=0 PH=60 100 PH=0 upper Test Light 99.8 PH=0 lower 200A Must 99.6 99.4 0.01 0.1 1 10 100 1000 Current (A) Figure 8: Meter Accuracy over Harmonics at 240V, 30A Meter Performance over Harmonics -- %Error 2 1 0 -1 1 3 5 7 9 11 13 15 17 19 21 23 25 -2 -3 -4 -5 -6 -7 -8 50Hz Harmonic data 60Hz Harmonic Data Measured at current distortion amplitude of 40% and voltage distortion amplitude of 10%. Rev 2.9 PRELIMINARY DATA SHEET Page: 47 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 PACKAGE OUTLINE 11.7 12.3 11.7 + 12.3 PIN No. 1 Indicator 9.8 10.2 0.60 Typ. NOTE: Rev 2.9 0.50 Typ. 0.00 0.20 0.14 0.28 1.40 1.60 CONTROLLING DIMENSIONS ARE IN mm PRELIMINARY DATA SHEET Page: 48 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 VBIAS VA V3P3A GNDA 51 50 49 IB 52 53 OPT_RX 57 IA GNDA 58 54 XIN 59 V1 TEST 60 VREF XOUT 61 55 VLCD 56 E_RST 48 RESETZ 2 47 V2P5 OPT_TX 3 46 VBAT TMUXOUT 4 45 RX TX 5 44 SEG31/DIO11 SEG3/SCLK 6 43 SEG30/DIO10 42 SEG29/DIO9 41 SEG28/DIO8 40 SEG27/DIO7 VDRV 7 CKTEST 8 V3P3D Rev 2.9 62 E_RXTX E_TCLK 1 63 GNDD 64 PINOUT: TDK 71M6511-IGT 9 PRELIMINARY DATA SHEET 30 31 SEG13 SEG14 SEG15 29 32 28 SEG11 SEG12 27 SEG16 SEG9 SEG10 33 26 COM3 SEG8 SEG17 16 25 34 24 15 SEG7/MUX_SYNC SEG18 COM2 23 COM1 SEG6/SRDY SEG19 35 SEG36/DIO16 36 14 22 13 21 COM0 SEG35/DIO15 SEG24/DIO4 20 37 SEG34/DIO14 12 19 SEG37/DIO17 18 SEG25/DIO5 SEG1 38 SEG2 SEG26/DIO6 11 17 39 SEG5/SFR SEG0 SEG4/SSDATA 10 Page: 49 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 PIN DESCRIPTIONS Power/Ground Pins: Name Pin # Type Description GNDA P Analog ground: This pin should be connected directly to the ground plane. GNDD V3P3A V3P3D VBAT 49, 58 1 50 9 46 P P P P V2P5 47 O Digital ground: This pin should be connected directly to the ground plane. Analog power supply: A 3.3V power supply should be connected to this pin. Digital power supply: A 3.3V power supply should be connected to this pin. Battery backup power supply. A battery or super-capacitor is to be connected between VBAT and GNDD. If no battery is used, connect VBAT to V3P3D. Output of the internal 2.5v regulator. No connection should be made to this pin. VLCD 62 P LCD power supply. Analog Pins: Name Pin # Type IA 54 I VA 51 I IB 53 I V1 56 I VREF VBIAS XIN XOUT 55 52 59 61 O O I VDRV 7 O Rev 2.9 Description Line Current Sense Input: This pin is a voltage input to the internal A/D converter. Typically, it is connected to the output of a current transformer. Line Voltage Sense Input: This pin is a voltage input to the internal A/D converter. Typically, it is connected to the output of a resistor divider. Line Current Sense Input: This pin is a voltage input to the internal A/D converter. Typically, it is connected to the output of a current transformer. Comparator Input: This pin is a voltage input to the internal comparator. The voltage applied to the pin is compared to an internal reference voltage of 1.5V. If the input voltage is above the reference, the comparator output will be high (1). The comparator output is maintained in Register 4 bit 0. Voltage Reference for the ADC The reference voltage used by the power fault detection circuit. Crystal Inputs: A 32kHz style crystal should be connected across these pins. Typically, a 10pf capacitor is also connected from each pin to GNDA. It is important to minimize the capacitance between these pins. See crystal manufacturer datasheet for details. Voltage boost output. PRELIMINARY DATA SHEET Page: 50 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 Digital Pins: Name COM3, COM2, COM1, COM0 SEG19...SEG8, SEG2...SEG0 SEG24/DIO4... SEG31/DIO11, SEG34/DIO14... SEG37/DIO17 SEG7/ MUX_SYNC Pin # 16 15 14 13 See pinout Type Description O LCD Common Outputs: These 4 pins provide the select signals for the LCD display. O Dedicated LCD Segment Output. See pinout O Multi-use pin, configurable as either LCD SEG driver or DIO. 24 O SEG6/SRDY 23 I/O SEG5/SFR 11 O SEG4/SDATA 10 O SEG3/SCLK 6 O CKTEST TMUXOUT 8 4 O O OPT_RX 57 I OPT_TX 3 O RESETZ 48 I RX TX E_RXTX E_TCLK E_RST TEST 45 5 2 64 63 60 I O I/O O I I Rev 2.9 Multi-use-pin LCD Segment Output/ MUX_SYNC is output for Synchronous serial interface Multi-use-pin, LCD Segment Outputs/ SRDY input for Synchronous serial interface. Multi-use-pin, LCD Segment Output/ SFR output for Synchronous serial interface. Multi-use-pin, LCD Segment Output/ SDATA output for Synchronous serial interface. Multi-use-pin, LCD Segment Output/ SCLK output for Synchronous serial interface. Clock PLL output. Can be enabled and disabled by CKOUT_EN. Digital output test multiplexor. Controlled by DMUX[3:0]. OPT LED Receive Input: This pin receives a signal from an external photo-detect diode used in an IR serial interface. OPT LED Transmit Output: This pin is designed to directly drive an LED for transmitting data in an IR serial interface. Can be tristated with OPT_TXDIS to be multiplexed with other GPIO pins. Chip reset: This input pin is used to reset the chip into a known state. For normal operation, this pin is set to 1. To reset the chip, this pin is driven to 0. This pin has an internal 30A (nom.) current source pull up. UART input. UART output. Emulator serial data. Emulator clock. Emulator reset. Enables Production Test. Must be grounded in normal operation. PRELIMINARY DATA SHEET Page: 51 of 52 71M6511/ 71M6511H Power Meter IC PRELIMINARY DATASHEET SEPTEMBER 2004 ORDERING INFORMATION PART DESCRIPTION 71M6511 64 pin LQFP, 0.5% accuracy 71M6511 64 pin LQFP Lead Free, 0.5% accuracy 71M6511H 64 pin LQFP, 0.1% accuracy 71M6511H 64 pin LQFP Lead Free, 0.1% accuracy ORDERING NUMBER PACKAGE MARKING 71M6511-IGT 71M6511-IGT 71M6511-IGT/F 71M6511-IGT/F 71M6511H-IGT 71M6511H-IGT 71M6511H-IGT/F 71M6511HIGT/F Preliminary Data Sheet: This Preliminary Data Sheet is proprietary to TDK Semiconductor Corporation (TSC) and sets forth design goals for the described product. The data sheet is subject to change. TSC assumes no obligation regarding future manufacture, unless agreed to in writing. If and when manufactured and sold, this product is sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement and limitation of liability. TDK Semiconductor Corporation (TSC) reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that a data sheet is current before placing orders. TSC assumes no liability for applications assistance. TDK Semiconductor Corp., 6440 Oak Canyon, Irvine, CA 92618 TEL (714) 508-8800, FAX (714) 508-8877, http://www.tdksemiconductor.com 9/23/2004 (c) 2004 TDK Semiconductor Corporation Rev 2.9 PRELIMINARY DATA SHEET Page: 52 of 52