Introduction
User Program
Program Execution
O per ating M odes an d Pr ogram
Processing Levels
Interrupt and Error Diagnosis
I nte grat ed S peci al F u ncti ons
Extended Data Block DX 0
Memory Assignment and
Memory Organization
Memory Access Using
Absolute Addresses
Multiprocessor Mode and
Communication
PG Interfaces and Functions
Appendix
Further Reading
List of Abbreviations
Index
List of Tables and Figures
The CPU 922/CPU 928/CPU 928B/CPU 948 List o f
Operations, Order No. 6ES5 997-3UA22 is included
with this manual.
SIMATIC S5
Programming Guide
Order No. 6ES5 998-2PR21
Release 01
S5-135U
CPU 928B
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C79000-H8576-C898-01
Copyright
Copyright © Siemens AG 1994 All Rights Reserved
The reproduction, t ransmission or use of this document or i ts contents is not permitted without express
written authority.
Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a
utility model or design, are reserved.
Disclaimer of liability
We have checked the contents of this manual for agreement wi th the hardware and software described.
Since deviations cannot be precluded en tirely, we cannot guarantee full agreement. However, the data in
this manual are reviewed regularly and any necessary corrections included in subsequent editions.
Suggesti ons for improvement are welcomed.
Technical data subject to change.
Safety-related guidelines
This manual contains notices which you should observe to ensure your own personal safety, as
well as to protect the product and connected equipment. These notices are highlighted in the
manual by a warning triangle and are marked as follows according to the level of danger:
Warning
indicates that death, severe personal injury or substantial p roperty damage can
result if proper precautions are not taken.
Caution
indicates t hat minor personal injury or property damage can resul t if p roper
precautions are not taken.
Only qualified personnel should be allowed to install and work on this equipment. Qualified persons
are defined as persons who are authorized to commission, to ground and to tag equipment,
systems and circuits in accordance with established safety practices and standards.
Siemens Aktiengesellschaf t 6ES5 998-2PR21
EWK Elektronikwerk Karlsruhe
Printed in the Federal Republic of Germany
!
!
How to use this M anual
Scope
Thi s programmi n g gu ide d es cribe s the foll ow i n g ve rsion s o f t he
CPU 928B-3UB11 and CPU 928B-3UB12 and its system software:
The ad dit io n al fu nc ti ons o f th e CPU 928B -3UB 1 2 are in d ic at ed i n th e
manual. Some o f them can be retro fit ted to t he CPU 928B-3UB11
(see Section 1.8 for details).
CPU 928B Programming G uide
C79000-D8576-C898-01 0 - 1
Overview of th e Chapters
Chapter 1
Thi s inform s you a bo ut th e area s o f a ppl icat io n of th e S5-135U
prog ramma bl e co n tro ll er w i th t he C PU 928B a nd its d ev i ce st ruc tu re.
It explains the typical mode of operation of the CPU and illustrates
ho w a CPU program is structured.
The chapter also contains suggestions about how to tackle
progra mming and whic h characteristics of the CPU 928B are
importan t for program mi n g.
If you have already worked wit h the CPU 928B-3UB11 and want to
know the differences between these CPU and the CPU 928B-3UB12
you will find this information in this chapter.
Chapter 2
T his explains the compone nts of a STEP 5 user program and how the
program can be str uc tur ed .
Chapter 3
This is intended f or readers who do not y et have much experience of
using the STEP 5 programming language. It therefore deals with the
basics of STEP 5 programming and explains the STEP 5 operations i n
detail (with examples).
E xperienced readers who may find that the infor mation about specific
operat ion s in th e pocket gu i de i s i nad equat e, ca n us e Se ction 3.5 a s a
refe rence sectio n.
Chapter 4
T his provides an ov ervie w of the mod es and program executio n levels
of th e CPU 928B . I t prov id es you w i th d e ta il ed i nform a ti on a bou t
various start -up mo de s a n d the assoc ia ted o rga ni zati o n blo ck s i n
which you can program your routines for differrent start-up situati ons.
The chapter also explains the differences between the program
execution levels " cy clic processing", "time-controlled processing" and
"int errupt-d rive n proce ssi n g" and wh ic h bl ock s a re a v ai labl e for yo ur
user program.
Chapter 5
Th i s i nfo rms you a bout errors to be av oided w h e n plan ning a nd
writing your STEP 5 programs.
The chap t e r tell s you ab out the help y o u can ob t ain fr om the sys tem
progra m for diagnosi ng errors and which reactions can be expected
and i nfo rm s you a bou t the bl ock s i n whic h you c an program rea ct io ns
t o certain errors.
T he chapter also explai ns the CPU 948 sel f-test.
How to Use this Manual
CPU 928B Programming Guide
0 - 2 C79000-D8576-C898-01
Chapter 6
This covers the special functions integrated in the system program. It
tells you ho w to use the special functions and how to call an d assign
parameters to the special functio n OBs. The chapter also explains how
t o rec ognize an d deal with errors in the processin g of a special
function.
Chapter 7
This describes the use o f data block DX 0 and its structure. The chapter
in forms yo u o f the significance o f the various DX 0 parameters. Based on
examples, you will learn h o w to create data block DX 0 or ho w to assign
the parameters in a screen form.
Chapter 8
This is a ref erence section for experienced sy stem users. It provides
information about the memory organization of the CPU 928B and
certain system data words which contain inform ation that can be
calle d up by the user.
Chapter 9
T his is also for experie nced syste m users. The chapter explains how to
a ddress data in certain me mor y areas using absolut e addresses.
Chapter 10
This explains when the m ultiprocessor mode can be used and how
dat a c an be ex c han ge d betw ee n th e CPUs an d C Ps. Th e ch apter
provi des information about progra mmin g for multipr ocessor operation.
The remainder o f the chapter provides detailed information an d
appli ca ti on exam ples fo r ex ch ang i ng l arg er amounts of data in the
multiprocessor mo de (multiprocessor communication).
Chapter 11
This tells you how to connect your CPU to a PG and the f unctions
provid ed by t he PG software to test your STE P 5 program.
Chapter 12
T his contains the Appendix with technical specifications of the CPUs
which ca n be u sed on t he S5-135U, some refere nce ta bles wit h
importan t in f ormatio n o n error diag nos tics and an I ST ACK eval uat ion
example.
How to Use this Manual
CPU 928B Programming G uide
C79000-D8576-C898-01 0 - 3
Chapter 13
This lists documentation for f urther reading.
Chapter 14
This is in tended to help you find theme s quickly and contain s a l ist of
abbreviations and a list of k eywords as well as lists of all the
nu mbered tables and figures.
How to Use this Manual
CPU 928B Programming Guide
0 - 4 C79000-D8576-C898-01
Co nv e nt ion s us e d in the te xt
To provide you with an overview of the contents of the pages, the
manual uses the following conventions in addition to a 2nd and 3rd
orde r of titl es:
Ent ries in the margin
E ntries in the margin are keywords printed in italics on the left-hand
edge of a page. They provide information about the contents of one or
more pa rag raphs o n the page.
Fou rth or der entri e s
Fourth order entries are not n umbered but appear in the margin in bold
face and identif y a longer section of text.
T he following conventions are also used.
Notes
Note
Important information is indicated in this f ormat.
Instructions
Instructions (often a sequence of operations to be perfor me d) are
represe n ted in t ables, e.g .
Step Action Result
1 Swi tc h th e m ode selector
from RUN to STOP. Th e CP U is in the s top
mode. The STOP LED is lit
continuously.
2 Hold the reset switch in the
OVERALL RESET position;
at the same ti me, switch the
mode selector fro m STOP to
RUN and ba ck to STOP.
An OVERALL RESET is
requested. The STOP LED
flashes q ui ck ly.
How to Use this Manual
CPU 928B Programming G uide
C79000-D8576-C898-01 0 - 5
Reference tables
Speci fic in for mation you may require at any ti me is con tained in
numbered t ables as sh ow n i n the fol low i ng e x ampl e an d ca n be fo u nd
in the list of tables (refer to Chapter 14).
Operation Operand Function
A
O
I 0.0 to 127.7
......
AND logic operati on with scan for sig nal state "1"
OR logic operation with scan f or signal state "1"
of an input in the PII
........
Examples
Examples, some of which cover several pages, are highlighted by a gray
frame. When the examples cover more than one page this is clearl y
indicated.
T able 3-2 B ina ry logic oper at ions
Example 1: Calling and assignin g pa rameters to a fu ncti on block in the
methods of r epresent atio n STL an d LAD/CS F in a progr am block
Method of representation STL
......
How to Use this Manual
CPU 928B Programming Guide
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Contents of Chapter 1
1.1 Area of App lication for the S5-135U with the CPU 928B. . . . . . . . . . . . . . . . . . . . . . . . 1 - 4
1.2 Typical Mode of Operation o f a CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 6
1.3 The Programs in a CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 8
Sys tem progra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 8
U ser program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 1 0
1.4 Which Operands are available to the User Program?. . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 12
1.5 Accessi ng Operand Areas and Me mory Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 16
1.6 How to Tackle Programming? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 17
1.7 Programming Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 20
1 .8 W hat is N ew with the C PU 928B? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 21
1
Introduction
1
CPU 928B Programm ing Guide
C79000-D8576-C898-01 1 - 1
1Introduction
Aims of the m anual
Thi s manu al is in t en ded t o prov id e spec ia li ze d in f orm at io n abo u t
program mi ng t he C PU 928B for u se rs w ho al read y h ave basi c
know l ed ge o f prog rammin g PLC s a n d wan t to use the C P U 928B i n
the S5-135U programmable c ontrol ler. I f you do n o t yet hav e t h is
basic knowledge, we strongly adv ise yo u rea d the documentation
intr oducin g the pr ogr amming language STEP 5 (STEP 5 Manual,
re fer to Ch apter 13) or take part in a course at our training center.
SIEMENS provides co mprehensive training for SIMATIC S5. For
more d etailed information, contact your local SIEMENS office.
Contents of Chapter 1
Chapter 1 explains how to use the manual and deals with the areas of
appli cati on of th e S5-135U pro gra mm able c on t rol ler wit h th e
CPU 928 B and its structure.
The chapter explains the typical m ode of operation of a CPU and the
structure of the CPU program.
You will also find a few suggestions about how to tackle
program ming and will learn some of the features of the CPU 928B
(-3 UB12) which are imp ortant fo r programming.
If you have already worke d wit h the CPU 928B (-3UB11) and woul d
like to know the differences between these modules and the
CPU 928B (-3UB12), refer to Section 1.8.
1
CPU 928B Programming G uide
C79000-D8576-C898-01 1 - 3
1.1 Area of Application for the S5 -135U with the CP U 928B
SIMATIC S 5 family
Th e S5-135U program mable co ntro ller belongs to the famil y of
SIMATIC S5 program ma ble co n troll ers. With the C PU 928B, i t is the
most powerful multi p roc essor u n it for proce ss au tom at io n (ope n an d
closed loop control, signalling, monitoring, logging).
Ow in g to it s modu larity and h ig h performan ce, it ca n be u sed for
medium to extremely large control systems as well as for com plex
autom ation tasks at the plant and process supervision level.
Suitability
T he S5-135U with t he CPU 928 B is particu larly s uitable for the
followi ng:
•• Tasks requiring fast bit and word-oriented processing and fast
reaction times, i.e. with extremely fast open and closed loop contro ls.
Examples o f this are fast processes in mechanical engineering
(bottling plant, packing ma chines or similar systems) and in the
automobile industry.
•• Ta sks requ i ri n g an e xtremely hig h storage cap acit y an d fast acc ess
times, e.g. in the autom obile industry, process and plant
engineering.
•• Ta sk s requi rin g fast com mun ic atio n w ith oth er C PUs in st al led in
t he PLC and operatin g in the multiproc essor mo de and with CP
mod ules (e.g. whe n co n nec te d to bus syst ems, ho st c omput ers, for
v isualization, operation and monitorin g).
•• Complex tasks which can be handled efficiently and clearly using
the high level languages C and SCL.
Area of Appli cation for the S5-135U wi th the CPU 928B
CPU 928B Programming Guide
1 - 4 C79000-D8576-C898-01
T his p ag e has been left in tentionally blank.
1
Area of A pplication fo r the S5 -135U with the CPU 928B
CPU 928B Programming G uide
C79000-D8576-C898-01 1 - 5
1.2 Typ ic al M ode of Ope r ation of a C PU
Mode of operation of a CPU
T he foll owin g modes of operati on are possible in a CPU:
Cyclic processing
This is the main part of all activities in the CPU. As the name already
says, the same operations are repeated in an endless cycle.
Cyclic processing can be divided into three main phases, as f ollows:
Phase Sequence
1All the input modules assigned to the
CPU are scanne d by the syste m
program and the values read in are
st ore d in t he process ima ge of th e
inputs (PI I ).
2The values contained in the PII are
processed by the user program and the
val ue s t o be o u tpu t are en te red i n the
proce s s ima ge of the outputs ( P IQ) .
3The values contained in the process
im age of the outputs are output by the
system program to the output modules
a ssi gn ed to the CPU.
Cyclic processing
Interrupt-driven processing
Time-controlled processing
1. 2. 3.
Read in process image
of the inputs
Output process image
of the outputs
&
&=
1
I1.5
I1.6
I1.4
I1.3 Q3.1
Evaluate input signals,
set output signals
Input I 1.3
Input I 1.4
Input I 1.5
Output Q 3
.1
Output Q 2.0
Output Q 4.7
CPU Process
Typical Mode of Operation of a CPU
CPU 928B Programming Guide
1 - 6 C79000-D8576-C898-01
Tim e- controlled processing
In addition to the cyclic processing, time-controlled processing is
al so a va il able for proc esses re qui ring co n trol sig n al s a t co n stan t
int erval s, e .g . n o n -t ime crit ic al mon i to ring func tion s pe rfo rm e d ev e ry
second.
Interrupt-driven processin g
If the reaction to a particular process signal must be particularly fast, this
should be handled with interrupt-driven processing. With, for ex a mple,
a process interrupt, triggered via an interrupt generating module, you can
activate a special processing section within your program.
Pro cessin g accordi ng to
p ri orit y
The types of processing listed above are handled by the CPU
according to their priority.
Since a fast reaction is required to a ti me or in terrupt ev ent, the CPU
in t errupts c yc lic proce ssin g to han dle a ti me o r in t errupt ev ent . Cyclic
proc essing th e ref ore h as th e lo w es t priority.
1
Typical Mode of Operation of a CPU
CPU 928B Programming G uide
C79000-D8576-C898-01 1 - 7
1.3 The Pr ograms in a C PU
The program existing on every CPU is divided into the following:
•• the system program
and
•• the us er program.
System program
The system program organizes all the functions and sequences o f the
CPU which do not involve a specific control task (re fer to Fig. 1-2).
Update process image
of the inputs
Output process image
of the outputs
System
program
Call
user
processin
g
(inter-
faces)
Execute start-up
Handle errors
Execute communications
with the programmer
Handle communications
via 2nd serial interface
Manage memory
Fig. 1-1 Tasks of the system program
The Program s in a CP U
CPU 928B Programming Guide
1 - 8 C79000-D8576-C898-01
Tasks
The tasks include t he fo ll owing: 1)
•• col d an d warm rest art,
•• u p d a ting the p roc es s im a g e of the in put s and ou tp utti ng the
process im age of the outputs,
•• calling the cyclic, time-controlled an d interrupt-driven programs,
•• detectio n and handling of errors,
•• m em ory man a ge me nt ,
•• comm u n icati on with the prog ra mme r ( PG) .
User interfaces
As the user, y ou can influence the reaction of the CPU to particular
situ atio ns a n d errors vi a spec ial i nte rfa ce s t o th e syste m prog ram.
Def ault sy stem reaction
The following chapters, except for Chapter 7, describe the default
system reaction to process eve nts or errors. Depen din g on the
de faults, the CPU changes to t he st op mo de if an operati on code error
occ urs and th e erro r organ i za tion bl oc k is n ot l oa ded .
M odif ying t he def aults
You ca n modify the system respon se by assigni ng paramet ers f o r th e
data blo ck DX 0.
Chapter 7 de sc ri bes the syste m respons e follow ing modification.
1) When operating with several CP Us (multipro cessing) further tasks are involved.
1
The Program s in a CPU
CPU 928B Programming G uide
C79000-D8576-C898-01 1 - 9
User program
Tasks
The user program contains all the functions required for processing a
specific control tas k. I n ge n eral terms, the se fun c ti ons can be
assigned to the interface provided b y the s ystem program for the
various types of processing, as follows:
Type of processing Task
Cold an d warm restart To provide the co nditions under which
th e oth er proc essin g fu ncti ons ca n start
from a defined status f ollowing a cold or
warm re start of th e co nt rol syst em (e.g.
assigni ng speci fic values to signals).
Cyclic processing Constantly repeated signal processing
(e.g. logic operations on binary signals,
r e ading in and analyzing analog values,
speci fyi ng binar y signals for output,
outputting analog values).
Time-controlled
processing
Special, ti me-dependent processi ng with
the following tim e conditions:
- f aster than the average cycle,
- at a time inte rva l greater than th e
average cycle time,
- at a specified point in ti me.
In te rru pt-d ri ven proces sin g Spe ci al , fa st re ac ti o ns to c ertai n proce ss
signals.
E r r or re ac tion H andl ing p r ob lems within the normal
sequence of the program.
The Program s in a CP U
CPU 928B Programming Guide
1 - 10 C79000-D8576-C898-01
Structure
User memory
Code blocks
Data blocks
Organization
blocks
OB
DB
DX
PB FB/FX SB
FB 8
SEGMENT 1
NAME :TRANS
0005 :L IB 3
0006 :T FW 200
0007 :C DB 5
0008 :DO FW 200
0009 :L DW 0
000A :T QW 6
000B :BE
1: KH = 0101;
2: KF = +120;
3: KS = xy;
4: KY = 4.5;
5: KG =
6: KM =
7:
1: KH = FFFF;
2: KH = FFFF;
3: KH = FFFF;
4: KH = FFFF;
5: KH = FFFF;
6: KH = FFFF;
7:
STEP 5
operations
static or dynamic data
(bits, bytes, words, double words)
static or dynamic data
(bits, bytes, words, double words)
STEP 5
operations STEP 5
operations STEP 5
operations
Program
blocks Function
blocks Sequence
blocks
&
&=
1
I1.5
I1.6
I1.4
I1.3 Q3.1
=
1
F 50.1
F 50.2
F 50.3 Q5.3
F1.7
I2.6 S
RQ
I1.3
User program
Fig . 1-2 St ructure of a STEP 5 user progr am
1
The Program s in a CPU
CPU 928B Programming G uide
C79000-D8576-C898-01 1 - 11
St o ring the user program
The CP U 928 B has two areas for storing bl ocks:
•• User memory: m ax. 64 Kby tes
The user memory is on a plug-in RAM or EPROM submodule and
contains logic and data blocks (if the user memory is an EPROM
submodule, the data blocks whose data are changed by the user
program m ust be loaded in the DB RAM ).
D a ta block RAM (DB RAM): m ax. 46 Kbytes
The DB RAM is an additional m em o ry area for storin g dat a
blocks.
Interfaces to the system
program
Organization blocks are available as interfaces to the system
progra m fo r the special ty pes of p roces sing.
The Program s in a CP U
CPU 928B Programming Guide
1 - 12 C79000-D8576-C898-01
1.4 Which Operands are available to the User Program?
The CPU 928B provides the following operand areas for
programming:
•• proces s i mage and I/Os
•• flag s (F flag s and S flags )
•• timers/counters
•• data blocks
Process im age of the inputs
and outputs PII/PIQ
Characteristics Size
The user program can access the following data types
in the pro ce ss imag e ex tremely quic kl y :
- single bits,
- bytes,
- words,
- double word s
128 bytes
each for
inputs an d
outputs
I/O area (P a rea)
Characteristics Size
The u ser program can access the I/ O modules direct ly
via the S5 bus.
The f ollowing data types are possible:
-bytes,
- words.
256 bytes
each for
inputs an d
outputs
Extended I/O area (O area)
Characteristics Size
The u ser program can access the I/ O modules direct ly
via the S5 bus.
The f ollowing data types are possible:
-bytes,
- words.
256 bytes
each for
inputs an d
outputs
1
Which Operands are available to the User Program ?
CPU 928B Programming G uide
C79000-D8576-C898-01 1 - 13
F flags
Characteristics Size
The flag area is a memory area which the user
p r ogr am can ac cess extre me ly q u i ckly wi th ce r tain
operations.
The flag area should be used ideally f or working data
req uir ed of te n.
Th e fo llowing data ty pes can be acc ess ed :
- single bits,
- bytes,
- words,
- doub l e wo r ds.
Single flag bytes can be used as interprocessor
co mmun ication flags (IPC flags) to exch ange data
bet wee n the CPUs in the multiprocessor mo de (refer
to Chapter 10). IPC flags are updated b y the s ystem
pr ogram at the en d of th e cycl e via a buf fer in t h e
coordinator or CP/IP.
2048 bits
S flags (extended flag area)
Characteristics Size
The CPU 928B als o contai ns an ad ditio nal fla g area,
the S flag area. The user program can also access this
area extrem e ly q uickly as wi th the F flags .
S fl ag s cannot however by used as actual operands
w i th function block call s nor as I PC flag s f o r data
exchange bet ween the CPUs. The bit test operati ons
of the CPU 948 can also not be used with the S f lags.
These f lags can only be used with the PG system
software "S5-DOS" from version 3.0 upwards or
"S5-DOS/MT" from version 1.0 upwards.
8192 bits
Which Operands are available to the User Program ?
CPU 928B Programming Guide
1 - 14 C79000-D8576-C898-01
Tim e r s (T)
Characteristics Size
The user program loads timer cells with a t ime valu e
between 10 ms and 9990 s and by means o f a start
operation, decre ments the ti mer from this value at the
preselected intervals until it reaches the value zero.
256 ti mer
cells
Counters (C )
Characteristics Size
The user program loads counter cells with a start value
(m a x . 999) a n d then in cremen t s o r d ec re men ts th em. 256
counters
Data words in the current data
block
Characteristics Size
A data block contains constants and/or variables in the
byte, word or double word format. With STEP 5
operations, you can always access the "current" data
block (re fer to Section 2.4.2).
The following data types can be accessed:
- sin gle bits,
- bytes,
- words,
- do uble words.
256
words
1)
1) In data blocks with a length greater than 256 words, you can only acc ess data
words with the num b ers > 255 wit h ope ratio n s for abso lute m e m ory acc e ss
(refer to Chapter 9).
1
Which Operands are available to the User Program ?
CPU 928B Programming G uide
C79000-D8576-C898-01 1 - 15
1.5 Accessing Operan d Areas and Mem ory Areas
STEP 5 operations use two different mechanis ms for accessing
operand areas and the entire memor y:
Re lative addressing
The majority of S TEP 5 operations address a memo ry location
relati ve to th e beginnin g of the operand area. If t hese operations are
used exclusi vely, code and data areas of the user program are
protected against unintentional overwriting. At the same time, the user
pro gram is d ependen t o n the CPU as lo ng as th e CPU has an
appropriate operand area.
Absolute addressing
Some STEP 5 operations work with absolu te addresses. These
operations can be used to access the entire m em ory area. They can
only be used in f unction blocks and should only be used with great
care due to the danger of data corruption. These operations are
depend en t on th e CPU used . H ow e ver, t here is n o d ifferenc e betw e en
the C PU 928 an d CPU 928B regarding t he se o pe rat io n s.
Current data block
Data blocks are loaded into the user memory or the DB-RAM by the
syste m progra m. Their locatio n depends on the memor y space
ava il able in ea ch c ase. T h e l en gth s of the i n di v idu al d at a bloc k s c an
vary and are set when programming the data blocks.
Th e cu rren t da ta blo c k is the da ta blo c k whose start in g ad dress an d
length are entered in special registers. This entr y is made via a special
STE P 5 operation for ca lling o r "openi n g" a data block (l ik e th e pa g e
of book). Unless o perations with absolute addressin g are used, the
user program can only access the current data blo ck. The following
data types are possible: single bits, bytes, words and double words.
Accessing Operand Areas and M emory Areas
CPU 928B Programming Guide
1 - 16 C79000-D8576-C898-01
1.6 How to Tackle Programming
If you are an e xperienced user, you have probably found the most
suitable method for creating progra ms for yourself and you can skip
this section.
Less ex perie n ce d re ade rs wil l fin d ti ps for d e sign ing , progra mm ing ,
testing and starti ng up your STEP 5 progra m.
Impl ementatio n stages
T he implementati on of t he STEP 5 co ntrol program can be divide d
into three stages:
Stage Activity
1 Determining the technological task
2 Designing th e program
3 Creating , tes ting and starti ng the program
Recursive procedure
In pra ct ic e, you wi ll recog niz e th at c erta in s te ps must be repea te d
(recursive procedure), e.g. when you realize that more signals are
requ ired to imp rov e th e ha ndl in g o f the ta sk .
Stage 1
D ete rmini ng the te chnologica l tas k:
Stage Activity
1 Create a general block diagram outlining the control
tasks of yo ur process.
2 Cre ate a l ist of th e in put a n d ou tpu t sign a ls re quired
fo r the task.
3 Im prove the block diagram by assigning the signals
a nd any particu lar time conditions and/or co unter
statuses to the individual blocks.
1
How to Tac kle Programm ing
CPU 928B Programming G uide
C79000-D8576-C898-01 1 - 17
Stage 2
De signi ng the program:
Stage Activity
1 Based on the improved block diagram, decide on the
types of pro ce ssi ng requ ire d o f your program (cycl ic
processing, time-controlled processing etc.) and select
the OBs required fo r thi s.
2 Divide the types of processing into technological
and/or fu nc tional units .
3 Check whether the units can be assigned to a program
or fun ct ion blo ck a n d sel ec t the blo ck s yo u require
(PB x, FB y etc.)
4 Fi nd ou t which timers, cou nters and data or results
memory you require.
5 Specif y th e ta sks fo r each of the pro posed lo gic bl o ck s
and the data for f lags and data blocks which m ay be
required. Create f low diagram s f or the logic blocks.
No tes on the scope of
cyclic pr ocessi ng
When decid ing o n the types of processing, keep the following
conditions in mind:
•• The cycle must run through quickly enough. The process statuses
must not change m ore quickly than the CPU can react. Otherwise
the process can get out of control.
•• The maximum r eaction time should b e taken as twi ce the cycle
time.
The cycle time is determined by the cyclic processing of the
syste m progra m an d th e type an d scope o f th e us er prog ram. I t is
o fte n not constan t, si nce the cyclic user progra m ma y be
inte r rupte d when t im e a n d in te rru pt-d riv en pro gram sec ti ons are
called.
How to Tackle Programmin g
CPU 928B Programming Guide
1 - 18 C79000-D8576-C898-01
Stage 3
Creating, testing and starting up the program:
Stage Activity
1 Dec ide on th e ty pe of representa tion for th e lo gic
bl ocks (LAD, CSF or ST L, refer to Chapter 2).
Remember that f unction blocks can only be created in
the STL method of representation.
2 Program al l lo gic and d ata block s (ple ase refer to you r
STEP 5 manu al).
3St art up the bl oc ks o ne after the ot her ( you may have
to program a different OB for each individual step, to
call the logic blocks):
1a: load the block(s)
1b: test the block(s)
(For m ore detailed inform ation please refer to your
STEP 5 manual and Chapter 11).
4When yo u are ce rt ai n th a t a ll the l ogi c bloc ks run
correctly and all the data can be correctly calculated
and stored, you can star t up your who le prog ra m.
Note on test str ategies
When you actually start up your program for the first time in genu ine
process operation, i.e. with real input and more importantly output
signals, is a decision that must be left up to yourself or to a team of
experts.
The mo re co mpl ex t he proc ess, th e grea te r th e risk a n d th erefore the
greater the care required when startin g up.
1
How to Tac kle Programm ing
CPU 928B Programming G uide
C79000-D8576-C898-01 1 - 19
1.7 Programming Tools
Suitable PGs
T he following programmers are available for creating your user
program, PG 685, PG 710, PG 730, PG 750 and PG 770. You can
check on the performance an d characteristics of these devices in the
c atalog ST 59 (se e Ch apter 13).
Note
Enter the CPU ID for C PU 922 (0010H ) in sy stem da ta wo r d
RS 29 (see Chapter 8) in order to be able to use a PG 615 or a CP
3xx. In this case, you cannot use S f lags.
If y ou do not change the ID, this will lead to erroneous indicators,
e.g. in the case of ISTACK output, or to the loss of some
deb ugging aids .
I n all programmers, the S TA TUS test function operates without
restriction only at scan times of ≤ 2.5 s. This value is halved in the
case o f parallel operation of 2 programmer inter faces (see
Chapter 11).
Suitable software
You can crea te user programs for SIM A TIC S5 programm able
controllers as fol lo ws:
•• In the STEP 5 p rogramming langu age,
Here you require th e STE P 5 programmi n g pa cka ge a lo n g wit h th e
system software STEP 5/ST or STEP 5/MT (description, refer to
/3/ in C h apte r 13),
or
•• In a higher programming language:
I f you are familiar with program ming in higher programming
languages, you can also formulate your STEP 5 program for th e
CPU 928B as follo ws:
- SCL (re f er t o /12/ i n Further R ead in g , the SCL co mpiler is
c ontai ne d in the PG soft ware "S5-DOS/MT" fro m version 6
upwards.)
You can also create progra m s for sequence control systems in a
graphic representation using the GRAPH 5 programming packag e
(de scri ption , ref er t o /4/ in C h apte r 13).
Depen din g on the task, you ca n also incorporate "o ff-the-peg"
stan dard fun c tion block s i n you r u ser pro gra m. Th e perf o rma nce and
c haracteristics of t hese blo cks are described in the cata log ST 57 (see
Cha pter 13).
Program m ing Tools
CPU 928B Programming Guide
1 - 20 C79000-D8576-C898-01
1.8 What is New with the CPU 928B (-3UB12)?
Th e CPU 928B (-3UB1 2) offers you t he foll ow in g new functi ons
com pa red t o the CPU 928B (-3UB 11).
Additional restart type:
RETENTIVE COLD
RESTART
1)
As well as the existing restart t ypes (MANUAL/AUTOMATIC
COLD RE ST AR T; MAN UAL/AU TOMATIC WAR M RES TA R T)
you can use the following additional restart t ypes:
•• R E TE N TI V E MA N U AL COLD REST AR T
•• RETEN TIV E AU TOMA T IC COLD RES T AR T
You can set t hese restart types by ass ign ing parameters in DX 0.
Delay interrupt
As well as the fa miliar time interrupts, an additional d elay in ter rup t
is processed by the new OB 6 organi za tion block .
T he delay interrupt has a time resoluti on of 1 ms.
You assign parameters to the desired delay time with the ne w O B 153
organi zation block.
Alternative loading of data
blocks
1) You can use the programmer to load data blocks into DB RAM f irst,
instead of into the user memory. Selection of the loading m ode is
contr olled via bit 0 in sys tem data word RS 144.
SI NEC L1 via the 2nd
serial
interface
1) Connection to the SINEC L1 LAN (with the new L1 interface card)
has been expanded f or communication via the second serial interface:
•• Use as slave in
- Normal co mmunicatio n
- Inte rnode c om m u n icati on
- Interrupt co mmun ic at ion
- Broadcast;
•• Use as master in point-to-point connections.
1) can be retrofitted to CPU 928B (-3UB11)
1
What is New with the CPU 928B (-3UB12)?
CPU 928B Programming G uide
C79000-D8576-C898-01 1 - 21
Contents of Chapter 2
2.1 STEP 5 Programming Language . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 4
2.1.1 T he LAD, CSF, S TL Methods of Represen tation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 4
2.1.2 Structured Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 5
2.1.3 STEP 5 Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 6
2.1.4 Number Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 8
2.1.5 ST EP 5 Block s and Storing them in Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 12
2.2 Program, Organization and Sequence Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 16
2.2.1 Organizatio n Blo cks as User Inter fa ces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 18
2.2.2 Organization Blocks for Spec ial Func tions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 22
2 .3 F u nctio n Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 23
2.3.1 Structure of Fun ction Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 24
2.3.2 Programming Function Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 26
2.3.3 Callin g Functi on Blocks and Assi gni ng Paramet ers to the m . . . . . . . . . . . . . . . . . . . . . 2 - 28
2.3.4 Special Function Bl ocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 33
2 .4 Data Blo cks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 3 5
2.4.1 Creati ng Dat a Bloc ks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 37
2.4.2 Opening Data Bl oc ks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 38
2.4.3 Special Data Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 41
2
User Program
2
CPU 928B Programm ing Guide
C79000-B8576-C898-01 2 - 1
2User Program
The fol lo wi ng ch apter explains th e compon en ts th a t mak e u p a
STEP 5 user program for the CPU 928B and how it can be structured.
2
CPU 928B Programming G uide
C79000-B8576-C898-01 2 - 3
2.1 STEP 5 Pr ogrammin g Lan gu a ge
With the STEP 5 programming languag e, you convert a utomation
tasks into programs that run on SIMAT IC S5 progra mmable
con tro ll ers. Yo u ca n pro g ram sim ple binary fu ncti o ns , c omple x di g it al
fun c ti ons an d arith me ti c ope ra ti o ns in c lu din g float in g po in t arit h me ti c
using STEP 5.
Types of operation
The operations o f the STE P 5 prog ram mi ng l ang u age are div id ed
into the f o llow ing gr oup s :
Basi c op erat io ns
•• you can use these operations in all logic blocks
•• methods of representat io n: ladd er diagram ( LAD), control system
flowc hart (CSF), statement list (STL).
Supplem entary opera tions and system o perations:
•• can only be used in fun ction blocks
•• only st atemen t li st (ST L) method of repres enta tion
•• syst em o peration s: on l y ex perience d STE P 5 programme rs sh o uld
use system operat ions
2.1.1
The LAD, CSF, STL
Metho ds of Represent ation When programming in STEP 5, you can choose between the three
methods of representation ladder diagra m (LAD), control system
flowchart (CSF) and statement list (STL) for each individual logic block.
You can choose the method of representation that best suits your
particular application.
T he mac hin e code MC5 that the programmers (PGs) generate is the
same for all three methods of representation.
If you foll ow ce rtai n rul es w hen prog rammi n g in ST EP 5 (se e /3/ in
Chapter 13), th e programm er c an tran slate yo ur use r program from
one me th od of representatio n into any oth er.
G raphic representation or
list of st atem e nt s
Whil e th e la dd e r di ag ram (L AD) an d co n tro l s ys te m flowc h art (CSF)
methods of representation represent yo ur STEP 5 program
graphically, statemen t li st (STL) rep resent s STEP 5 operatio ns
in div idu ally as mnemoni c abbreviations.
STEP 5 Program m ing Language
CPU 928B Programming Guide
2 - 4 C79000-B8576-C898-01
G raphic representation of
sequential cont rols
GRAPH 5 is a programming language f or graphic representation of
sequential controls. It is at a higher level than the LAD, CSF, STL
method s of represe n tati on . A program w rit ten in GR APH 5 as a
graphic representation is automatically converted to a STEP 5
program by the P G. (Refer to /4/ in Chapter 13)
2.1.2
Structured Programming Using STEP 5, you can structure your program by dividing it into
self-cont ained program sections (blocks). This division of your
prog ram c larifi es t he ess ential p rogram structures ma king it ea sy to
rec ogn iz e th e syste m parts that a re rel at ed wi th i n th e soft ware .
Ladder diagram Statement list Control system flowchart
Programming with
graphic symbols
like a circuit diagram
Programming with
graphic symbols
IEC 117-15
DIN 40700
DIN 40719
DIN 19239
DIN 19239 DIN 19239
STL CSFLAD A
AN
A
ON
O
=
&
> = 1
I
I
I
I
I
Q
Programming with
mnemonic abbreviations
of function designations
complies with complies with complies with
Fig. 2-1 Methods of repre sentation in the STEP 5 pr ogr amming language
2
STEP 5 Programming Language
CPU 928B Programming G uide
C79000-B8576-C898-01 2 - 5
Structu red programming offers yo u the fol lowi ng adva nta ges:
•• simple and clear creation of programs, even large ones
•• stand ardiz atio n of prog ram par t s
•• simple program organization
•• easy program ch anges
•• simple, sectio n b y section program test
•• simple syste m start-up
What is a block?
A block is a part of the user program tha t is distinguished by its
func tion, stru ct u re o r appli ca ti on. You can di ffe ren tiat e betw e en
blo ck s th at con t ai n statements (code) i.e. org anization blocks ,
program block s, f unction blocks o r sequence blocks, an d blo ck s th at
contain data (data blocks).
2.1.3
STEP 5 O perati ons A STEP 5 operation is the smallest independent unit of the user progra m.
It is the work specification for the CPU. A STEP 5 operation consists o f
an operation and an operand as sho wn in the following example:
Example
Operation code
Operation Operand
Parameter
:O F 54.1
(what is to be done?) (with what is the
operation to be done?)
STEP 5 Program m ing Language
CPU 928B Programming Guide
2 - 6 C79000-B8576-C898-01
Absolut e and symbolic
operands
You can enter the operand absolutely or symbolically (using an
assignment list) as shown in the following example:
Absolu te representation: :A I 1.4
Symbolic re pre senta tion: :A - M otor1
For more information o n absolute and symbolic programming , refer to
your STEP 5 manual.
Appli cation of STE P 5
operations
The STEP 5 operatio n se t enables you t o do t he foll o win g:
•• set or reset and com bine binary values logically
•• load and transfer values
•• compare val ues and process them arithmetically
•• speci fy ti mer and counter values
•• co nv ert nu m ber represen tati on s
•• call blocks and execute jumps within a block
and
•• influence program execution
Result of logic operation RLO
The central bit for controlling the program is the result of lo gic
operation RLO. T his is obtained as a result of binary logic operations
and is inf luenced by som e operations.
Section 3.5 describes the whole STEP 5 operation set and explains h ow
the R LO is obtained. This section also includes programming exa mples
for individual ST EP 5 ope rations.
2
STEP 5 Programming Language
CPU 928B Programming G uide
C79000-B8576-C898-01 2 - 7
2.1.4
Number Representation To allow the CPU to logically combine, modif y or compare numerical
values, these values must be located in the accumulators (working
registe rs of the CPU) as bi na ry nu mbers.
Depending on the operations to be carried out, the following n u mber
representations are permitted in STEP 5:
Binary numbers: 16-bit fixed point nu mbers
32-bit fixed point nu mbers
32-bit floatin g po int nu mbe rs (w it h a 24-bit
mant is sa)
Decimal numbers: BCD-coded numbers (sign an d 3 dig its)
Num erical input on the PG
When you use a programmer to i nput or display number values, you
set the data f orm at on the programmer (e.g. K F or f ixed point) in
whic h you i nten d t o en te r or di splay the v al ues. Th e prog ramm er
c onverts the internal representat io n into the form you h ave requested.
Permitted operations
You can carry out all arithmetic ope ra tio n s with the 16-bit fixed
point numbers and fl oating point nu mbers, includ ing c omparison,
addition, subtraction, multiplication and division.
Note
Do not use BCD-coded numbers for arithmetical operations, since
this leads to incorrect results.
Use 32-bit fixe d point nu mbers to e xecut e co mpari son ope rati ons .
The se are al so n ec essary as an i nte rm ed i at e l ev e l wh e n co n ve rti ng
numbers i n B CD co d e t o flo at ing po in t nu m be rs. Wit h th e ope rati o ns
+D an d -D th e y can also be u sed for ad diti o n an d su btrac ti o n.
The STEP 5 progra m ming language also has conversion operations that
enable you to convert nu mbers directly to the most i mportant of the other
numerical representations.
STEP 5 Program m ing Language
CPU 928B Programming Guide
2 - 8 C79000-B8576-C898-01
16-bit and 32-bit fixed
poi nt nu mbers
Fix e d point nu mbers are who l e binary numbers w i th a si gn.
Coding of fixed point numbers
Fixed point numbers are 16 bit (= 1 word) or 32 bit (= 2 words) in
binary representation. Bit 15 or bit 31 contains the sign.
•• ’0’ = positive number
•• ’1’ = negative number
T he two’s complement representation is used for ne gative numbers.
PG input
Input of 16-bit fixed point nu mber data form at at the PG: KF
Input of 32-bit fixed point nu mber data form at at the PG: DH
Permitted num erical range
-32768 to +32767 (16 bit)
-2147483648 to +2147483647 (32 bit)
Using fixed point num bers
Use fixed point nu mbers for simple calculations and for comparing
nu mber values. Since fixed point numbers are always wh ole numbers,
rem em ber that the result of dividing two fixed point numbers is also a
fixed point nu mber without deci mal places.
2
STEP 5 Programming Language
CPU 928B Programming G uide
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Flo atin g poin t nu m bers
Fl oating poi nt nu mbers are positive an d negative fractions. They
always oc cu py a do uble w ord (32 bits). A fl oati ng point n umber is
represe nte d as an e xponenti al n umber. The mant is sa is 16 or 24 bit s
long and the e xponent is 8 bits long.
In the CPU 928B , the d efa ult ma nt is sa (a ssum in g you h a ve n o t
ch a ng e d the settin g) is 16-bits long (bits 8 to 23) for a ddin g,
subtracting, multiplying and dividing. The least signi fica nt (on the
right) bits 0 to 7 always have the value "0".
If you require floating point calculations with a hi gher accuracy (and
can ac ce pt a slig htl y lon ger runt ime), pro gra m th e set ti ng "flo at ing
point arithmetic with 24-bit mantissa " in DX 0 (see Chapter 7).
The exponent indicates the order of magnitude of the floating point
number. T he s ig n o f th e ex pon ent t ells you w het her the v al ue o f t he
floating point number is greater or less than 0.1.
Using floating point numbers
Use f loating point numbers f or solving extensive calculations,
especia lly for mu l tiplica tion and di vis ion or when you are wo rki ng
w ith very larg e or very small numbers!
Accuracy
The mantissa indicates the accuracy of the floating point number as
follows:
•• Accura cy with a 24-bit mantissa:
2-24 = 0.000000059604 (corresponds t o 7 de cimal plac es)
•• Accuracy with a 16-bit mantissa:
2-16 = 0,000015258 (correspond s to 4 decimal pla ces)
If the sign of the mantissa is "0 " the number is positi ve; if the sig n is
"1" it i s a neg at ive n umber i n it s t w o’s complem en t represe nt at ion .
The floa ting point value ’0’ is represented as the binary value
80000000H (32 bits, see below).
STEP 5 Program m ing Language
CPU 928B Programming Guide
2 - 10 C79000-B8576-C898-01
Coding floating point numbers
C oding a floating point number :
31 30 24 23 22 0
V2
6 ... . ... 20V2
-1 .... . . . . . ... 2-23
Exponent Mantissa
Speci ficati on of the data for mat for floating point n umbers at the
PG: KG
Permissible num erical range
± 0.1469368 x 10-38 to ± 0.1701412 x 1039
Input/output on PG
a) in a logic block:
Y ou wan t to l oad the number N = 12.3456 7 as a fl oat ing point
number.
Input:
:LKG1234567+2
b) in a data block:
Yo u wa nt to de fine the num ber N = - 0.005 as a flo ating po in t
constant.
Input:
6: KG = - 5 - 2
PG di splay aft er yo u enter the lin e:
6 : KG =- 5000000 - 02
Mant issa with sig n E xpon ent (base 10)
with sig n
Value of the number input: - 0.5 x 10-2 = 0.005
PG di splay after you en te r the line:
:L KG + 1234567 + 02
Mantis sa wit h sig n Ex pone nt (base 10)
with sign
Value of the numbe r in put: +0.1234567 x 10+2 = 12.34567
2
STEP 5 Programming Language
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Numbers in BCD code
Decim al numbers are rep rese nted a s numbe rs in B CD code . W i th
th e i r si g n an d three dig i t s, th e y oc cupy 16 bits (1 word) in an
accumulator as shown in the f ollowing exam ple:
15 12 11 8 7 4 3 0
V V V V hundreds tens ones
The individual digits are positive 4-bit binary numbers between 0000 and
1001 (0 and 9 decimal).
The le f t bi ts are re serv e d for t he si g n as follo ws:
Sign for a positive number: 0000
S ign for a negat iv e number: 1111
Permissible num erical range
-999 to +999
STEP 5 Program m ing Language
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2 - 12 C79000-B8576-C898-01
2.1.5
STEP 5 Bl ocks and Stori ng
them in Memory
Identifier
A block is identified as f ollows:
•• the block type (OB, PB, SB, FB, FX, DB, DX)
and
•• the block nu mber (number betw e en 0 and 255).
Block types
T he STEP 5 programming langua ge differentiates between the
followi ng block typ es:
Organization blocks (OB)
Orga n iz at ion block s are th e in te rf a ce betw ee n th e syst em program and
t he user program. T hey can be divided int o two groups as follo ws:
With OB 1 t o OB 39, you c an c ont ro l program ex e cuti o n, the restart
procedure of the CPU and the reaction in the event of an error. You
program these blocks yourself ac co rdi ng to your a uto mation task.
The se OBs are ca ll ed by t he system program.
OBs 40 to 100 are blocks belongi ng to the operat ing system. You
must not call these blocks.
OBs 121 to 255 contain special f unctions of the system program. You
can call th ese blocks, i f required, in your user program.
Program blocks (PB)
You require pro gra m bloc k s t o stru ct u re yo ur pro gram. Th ey c o ntai n
program parts d iv ide d ac cordi ng to t echno lo g ical a nd funct ional
criteria. Program blocks represent the heart of the user program.
Sequence blocks (SB )
Sequence blocks were originally special program blocks for step b y
step proc es sing of se que ncers. I n th e meanti me , howeve r, se que nc ers
can be programmed with GRAPH 5. Sequence blocks have therefore
lost their original significance in STEP 5.
Sequence blocks now represent an extension of the program blocks
and are used as program blocks.
2
STEP 5 Programming Language
CPU 928B Programming G uide
C79000-B8576-C898-01 2 - 13
Function blocks (FB/FX)
You use fu nct io n blo ck s to program frequen tl y rec urring a nd/ or
complex f unctions (e.g. digital f unctions, sequence control sy stems,
closed loop controls and signalling functions).
A func ti on blo ck c an be ca ll ed sev eral t im es by h i ghe r order bloc k s
a nd supplied wit h new operands (assi gne d parameters) at each call.
Using block t ype FX increases the max imu m n u mber of possible
function blocks from 256 to 512.
Data blocks (DB/DX)
Data blocks contain the (fixed or variable) data with which the user
program works. This type of block contains no STEP 5 statem ents and
has a di sti nct ly d if ferent functi on fro m th e ot her blo cks. Using block
type DX doubles the number of possible data blocks.
Formal structure of the
blocks
All blocks co nsist of t he following tw o parts:
•• a block header
and
•• a blo ck body
Block header
The block header is always 5 words long and contains information for
block management in the PG and data for the syste m progra m.
Block body
Depe ndi ng o n the bloc k type, th e block body conta in s the followin g:
•• STEP 5 operati ons (in OB, PB, SB, FB, FX),
•• variable or constant data (in DB, DX)
and
•• a fo rm al opera n d li st (i n FB , F X ).
STEP 5 Program m ing Language
CPU 928B Programming Guide
2 - 14 C79000-B8576-C898-01
Block preheader
The programmer also generates a block preheader (DV, DXV, FV,
FXV) for bl oc k types DB , DX, FB and FX. T hese blo c k prehe ad ers
con ta in i n form a ti on abo ut t he data form a t (for DB an d DX) or th e
j ump labels (for FB an d FX). On ly the PG can evaluate this
i nformation. Consequently th e block prehea ders are not trans ferred to
the CPU memory. You cannot influence the contents of the block
header directly.
M aximum length
A STEP 5 block can occupy a maximum of 4 09 6 words in th e
program memo ry of the CPU (1 w o rd correspo n ds to 16 bits).
Available blocks
You can pro gra m th e fol lo win g bloc k types:
Data blocks DB 0, DB 1, DB2, DX 0, DX 1 and DX 2 contain
parameters. These are reserved for specific functions and you cannot use
them as normal data blocks.
OB 1 to 39
FB 0 to 255
total 512
FX 0 to 255
PB 0 to 255
SB 0 to 255
D B 3 to 255
total 506
DX 3 to 255
2
STEP 5 Programming Language
CPU 928B Programming G uide
C79000-B8576-C898-01 2 - 15
Block storag e
Th e pro g rammer stor es al l prog ra m m ed bl oc k s in th e program
memory in the order in which they are trans ferre d (Fig. 2-2). Th e
prog ram me r funct ion "Tra n sfer d at a block s B " t ran sf ers fi rst the cod e
blocks then the data blocks to the PLC. In RAM mode, the RAM card
is first to be filled with data blocks after trans fer of the code blocks
and then the rem aining data blocks are written into internal DB RAM.
The start ad d resses of a ll stored blo ck s a re plac ed i n data bloc k DB 0.
Alternative loading (only in the
case of Version -3UB12 )
By setting bit 0 in system data word RS 144, y ou can load data blocks
first in t o in te rnal DB RA M first (i .e . a s l on g a s spa ce is av a il able )
("Alternati ve l oadin g" - see Chapter 8/RS 144). Dat a blocks are
t ran sferred to the RAM car d on ly wh en the D B RA M has b e en fill ed.
Correcting and deleting
blocks
When you correct blocks in " RAM m ode", the old block is declared
invali d in the memor y and a new block is entered.
Similarly, when blocks are deleted, they are not r eally dele ted, instead
the y are decl ared inv al id. Dele te d and c orrecte d blo ck s therefore
continue to use up mem ory space.
Note
You can use the COMPRESS MEMORY online functio n to make
space for new blo cks. This function optimizes th e utilization of
the memory by deleting blocks m arked as invalid and shif ting
va li d blo cks to g ether. C o mpress ion is h andle d separate ly
ac cording to mem ory c ard an d i nt ernal R AM (se e Section 11.2.2).
Location of blocks
in the user memory
Address 0
FB1
OB1
SB10
DB1
PB1
PB2
Fig. 2-2 Exampl e of block storage in the user memory
STEP 5 Program m ing Language
CPU 928B Programming Guide
2 - 16 C79000-B8576-C898-01
2.2 Pro gr am, Org a niza tio n a n d Seq ue nce B locks
Program blocks (PBs), organization blocks (OBs) an d sequence
bloc ks (SBs) are the sa me with respect to programmin g and calling.
You can prog ram al l thre e types in the LAD, C SF a nd ST L me tho ds
of representation.
Programming
When progr ammi ng organization , progra m and sequenc e bloc ks,
proceed as follows:
Step Action
1 First i ndicate the type of bloc k and the n the number of the
blo ck that you wa nt t o progr am.
Th e fol lowin g n u mbers are avai la ble for t he t y pe o f
b l o ck li s ted:
- progra m blocks 0 to 2 55
- seque nce blocks 0 to 255
- o rganizat ion b locks 1 to 3 9
2 Enter your program in the STEP 5 pro grammin g l an gua ge.
When programmi ng PBs , OBs an d SBs , yo u can onl y
use the STEP 5 basic operations!
A STEP 5 block sho uld always be a self-contained
program section.
Logic operations m ust always be completed
within a block.
3 Complete your program input with the block end
operation "BE".
Bl ock calls
With the exception of OB 1 to OB 39 y ou m ust call the blocks to
proc ess th e m. Use th e spec ia l STEP 5 block c all o perati ons to c al l t h e
block s.
You can program block calls inside an organization, program,
function or sequence block. They can be compared with jum ps to a
subroutine. Each jum p causes a block change. The return address
within the calling block is buffered by the system.
2
Program , Organizat ion and Sequence Blocks
CPU 928B Programming G uide
C79000-B8576-C898-01 2 - 17
Block calls can be unconditional or conditional as follows:
Unconditional call
The " JU" statement belongs to the unconditional operations. It has no
ef fect on the RLO. The RLO is carried along with the jump to the new
block. Within the new block, it can be evaluated but no longer
c omb ined lo gic al ly.
Th e add ress ed blo c k is pro ce sse d regardless of t h e prev ious re sult of
l ogic operation (RLO - see Section 3.4).
Example: JU PB 100
Conditional call
The JC statement b elongs to the conditional oper ation s. The addressed
block is processed only i f the previous RLO = 1. If the RLO = 0, the
jump is no t executed.
Example: JC PB 100
Note
After the con ditio nal jump operati on is executed, the RLO is set
to "1" regardless of whether or not the jump to the block is
executed.
P
B1 PB5 PB10
PB 6
BE
BE
BE
BE
AA
O
I1.0 I2.0
I3.0
JU PB 5
OI5.3
AI1.5
JC PB 6
AI3.2
JC PB 10
OF1.5
Fig. 2-3 Block cal ls that enable processing of a program block
Program , O rganization and Sequence Blocks
CPU 928B Programming Guide
2 - 18 C79000-B8576-C898-01
Ef fect of the B E statem ent
After the "BE" statement (block end), the CPU continues the user
program in the block in which the block call was program med.
Prog ram e xe cu t io n co n ti n ue s at th e STEP 5 st at emen t fo l lo w in g the
b loc k call .
The " BE" statement is executed regardless of the RLO. After " BE",
t he RLO can no lo nger be combined lo gically. Howe ver, the RLO or
arithmetic result occurring directly before execution of the BE
ope rat io n is trans fe rre d to t h e bl oc k wh ere th e call o rig in at ed a n d can
be evaluated there. W hen program execution returns from the block
tha t h as bee n call ed , th e content s o f A CCU 1, A CCU 2, ACCU 3 and
ACCU 4, the condition codes CC 0 and CC 1 and the RLO are not
changed. (Refer to Sectio n 3.5 for more detailed information about th e
ACCUs, CC0/CC1 and RLO).
2.2.1
Organization Blocks as
User Interfaces Organization blocks form the inte rf ace s be tw een the system program
and t he use r prog ra m. Organ iz at io n blo ck s OB 1 to OB 39 belon g t o
your user p rogram j ust a s p rog ra m b loc ks. By p rogram m ing these
OBs, yo u ca n in flu e nce the beh avio r o f th e C PU d uri ng sta rt -up,
progra m execution and in the event of an error. The organization
blo cks are effec ti ve a s so o n as th e y are lo ad e d in t he PLC memo ry.
T his is also possible while the PL C is in the run mode.
Once the s yste m program has called a speci fic organization block, the
user program it contains is execu ted.
Note
You can program blocks OB 1 to OB 39 as user interf aces and
they are ca lled aut o mati cally by the s yste m pro gram a s a rea ction
to certain events.
For test purpo se s, you can also call these organization blocks
from the user program (JC/JU OB xxx). It is, however, not
possible to trig ger a CO LD RESTART, e. g. b y calling OB 20.
The f ollowing table provides you with an overview of the user
in terfaces (OBs ) .
2
Program , Organizat ion and Sequence Blocks
CPU 928B Programming G uide
C79000-B8576-C898-01 2 - 19
O rg anization blocks for controlling p rogram execution
Bloc k F unction and call criterion
OB 1 Organization of cyclic program execution;
first call after a start-up, then cyclic call
OB 2 Organization of i nterrupt-driven program
execution;
Call by interrupt sign al of S5 bus (process
interrupt)
OB 3 to O B 5 Not used with the CPU 9 28B
OB 6 Delay interrupt (from Version -3UB12)
OB 7, OB 8 Not us ed with the CP U 928 B
OB 9 Processing clock-controlle d time i nterrupts
O B 10
O B 11
O B 12
O B 13
O B 14
O B 15
O B 16
O B 17
O B 18
Time interrupts wit h fixed intervals:
cal l every 1 0 ms
cal l every 2 0 ms
cal l every 5 0 ms
cal l every 100 ms
cal l every 200 ms
cal l every 500 ms
cal l every 1 s
cal l every 2 s
cal l every 5 s
Table 2-1 Overvi ew of the organization blocks for program execution
Program , O rganization and Sequence Blocks
CPU 928B Programming Guide
2 - 20 C79000-B8576-C898-01
O rganization blocks to control the start-up procedure
Bl oc k F unction and call criterion
O B 20 Call on request for COL D RESTART (manual
and automa tic)
O B 21 Call on request for MANUAL WARM
RESTART/RETENTIVE CO LD
RESTART
O B 22 Call on request for AUTOMATIC
W A RM RE S TART/RETENTI V E COLD
RESTART
O rganiza tio n blocks for reactions to device or
program errors 1)
Bl oc k F unction and call criterion
O B 19 Ru ntim e error (LZF):
called block not loaded
O B 23 T imeo ut (QVZ) in user prog ram (du ring direct
acces s to I/O modules or ot her S 5 b us
addresses)
O B 24 Timeout (QVZ) when updating the process
image and trans ferring interprocessor
commu ni ca ti on fl ags
O B 25 Add ressin g error (ADF )
O B 26 Cycle tim e exceeded (ZYK )
O B 27 Op. c o de e rro r (BC F): su bs titu tio n error
O B 28 STOP by PG function/stop switch/
S5 bus 2)
O B 29 Op. code error (BCF):
co de not permitted
O B 30 Op. code error (BCF):
parame te r not permitt ed
O B 31 Other runtime errors (LZF)
O B 32 Ru ntim e error (LZF): load a n d transf e r error
with data blocks
O B 33 Collision of tim e interrupts (WECK-FE)
Table 2-2 Overview of the organizati on blocks for start- up
Table 2-3 Overvi ew of the organization blocks for error handling
2
Program , Organizat ion and Sequence Blocks
CPU 928B Programming G uide
C79000-B8576-C898-01 2 - 21
O rganization blocks for reaction s to device or
program errors 1)
Bloc k Function and call criterion
Table 2-3 continued:
O B 34 Erro r in clo sed loop con troller proc essin g
(REG-FE)
O B 35 Commu nic atio n e rro r on the seco nd serial
interface (FE-3)
O B 36 to O B 39 do not exist for the CPU 928B
1) If the OB is not programmed, the CPU changes to the stop mode in the event of
an error.
EXCEPTION: if OB 23, OB 24 and OB 35 do not exist, there is no reaction.
2) OB28 is called before the CPU changes to the stop mode. The CPU stops regard-
less of wheth e r an d how OB 28 is p ro gramm e d.
EXCEPTION: OB28 is not called if the power i s switched off.
Program , O rganization and Sequence Blocks
CPU 928B Programming Guide
2 - 22 C79000-B8576-C898-01
2.2.2
Organization Blocks for
Special Functions The follow i ng organiza tion b locks con tain sp e cial functions of t he
system program. You cannot prog ram th e se bl o cks, bu t si mply c al l
t hem (this appli es to all OBs with nu mbers betwee n 40 and 255!).
Th e y do n ot conta in a STE P 5 program . Speci al func tion OB s can be
called in all logic blocks.
Integral organization blocks with special functions
Bl ock : Bl ock function :
O B 110
O B 111
O B 112
O B 113
Access to the status (condition code) byte
Cl ear ACCU 1, 2, 3 a nd 4
ACCU roll up
ACCU roll d own
O B 120
O B 121
O B 122
O B 123
"B lock all interru pts" on/of f
"B lock in d ividu al time in terrupts" on/off
"Delay all in terrupts" on/off
"Delay individu al time in terrupts" on/off
OB 150 Set/read system time
OB 151 Set/read tim e for clock-controlled tim e
interrupt
OB 152 Cycle statistics
OB 153 Set/read tim e for delay interrupt
OB 160-163 Counter loops
OB 170 Read block stack (BSTACK)
O B 180
O B 181
O B 182
Varia ble da ta b lock access
Test data blocks DB/DX
Copy data area
O B 190, 192
O B 191, 193
Transfer flags to data block
Transf er data fields to flag area
OB 200, 202-205 Multiprocessor communication
OB 216-218 Access to "pages" (CPs and some IPs)
OB 220 Sign extension
OB 221 Set cycle monitoring time
OB 222 Restart cycle monitor ing time
Table 2-4 Overview of organizati on blocks for speci al functions
2
Program , Organizat ion and Sequence Blocks
CPU 928B Programming G uide
C79000-B8576-C898-01 2 - 23
Inte gral organ ization blocks w ith special fun ction s
Block: Block function:
Table 2-4 continued:
OB 223 C ompare re st art type
OB 224 Transfer blocks of IPC f lags
OB 226 Read word from the syste m program
OB 227 Read checksum of the system program
memory
OB 228 Read status information of a program
execution level
OB 230-23 7 Fun ction s for stan dard functi on bl ocks
(han dling bloc ks)
O B 240
O B 241
O B 242
Initialize shif t register
Process shift register
Clear shift register
O B 250
O B 251
O B 254, 255
Ini ti al iz e PID co ntroller a lgo ri th m
Process PID co ntroller algorithm
T ran sfer da ta b lock to the D B-RAM
The se special fun ct io ns are des cribe d in d et ai l in C h apte r 6.
Program , O rganization and Sequence Blocks
CPU 928B Programming Guide
2 - 24 C79000-B8576-C898-01
2.3 Fun ction B loc k s
Functi o n blo cks (F B /F X) are als o parts of t he u se r program just l ik e
program blocks. FX function blocks have the same structure as FB
function blocks and are programmed in the sam e way.
You use fu nct io n blo ck s to i mplemen t frequ en t ly rec u rri ng o r v ery
complex functions. In the user program, each function block re presents a
complex co mplete function. You can obtain function blocks as follows:
•• as a s oftwa r e pr oduc t from S IE MENS (st and ard func ti on blocks
on diskette - see /11/ in Chapter 13); wit h these fun ction bloc ks
you can generate user programs for fast and simple open loop
control, signalling, closed loop control and logging;
or
•• you can program function blocks yourself.
Co mpared with organization, program and sequence blo cks, function
blocks ha ve the foll owing four essent ial differences:
O B, PB, S B F B/ FX
1. Range of operations
only basic operations - basic operations,
- supplementary operations
- system operatio ns
2. M ethod of represen tation
prog rammi ng and ca ll
in STL, LAD, CSF programming only in AWL
3. Name
n ame envi r onment not
possible
(on ly number)
in addition to the numb e r
a name with max. 8 ch ars. ca n
be assig ned
4. Operands
none form al operands (block
parameters).
When the block is called
form al operands are assig ned
actual operands
2
Function B locks
CPU 928B Programming G uide
C79000-B8576-C898-01 2 - 25
2.3.1
Stru c ture of F un ctio n
Blocks The block header (f ive words) of a function block has the same
structure as the headers of the other STEP 5 block types.
The block bod y on t h e o t he r han d , h as a di ffe rent stru ct u re from t he
bodies of the other block types. The block body contains the f unction
to be executed in the form of a statem ent list in the STEP 5
program ming language. Between the block header and the STEP 5
statem ents, the f unction block needs additional mem ory space f or its
name and for a list of formal operands. Since this list contains no
statements for the CPU, it is skipped wit h an unconditio nal jump that
the programmer generates auto matically. T his jump statement is not
displayed wh e n th e funct io n blo c k is di splayed on th e PG!
When a f unction block is called, only the block body is processed.
Absolut e or symbolic
operands
Yo u ca n enter ope rand s i n a fun ct io n block i n absol ut e form
(e.g . F 2.5) or symbolically (e. g. MOTOR1). You must st ore the
assignment of the symbolic operands in an assignment list before you
ent er the operan d s i n a funct ion bloc k (see /3/ in C hapte r 13).
Fig. 2-4 shows the structure of a function block in the memory of a
prog ram ma bl e co n tro ll er.
JU
N
ame of the FB/FX
Formal operand 1
Formal operand 2
Formal operand n
5 words
1word
4 words
3 words
Block
header
Block
body
BE
3 words
Skip formal
operand
list
1st STEP 5 user operation
3 words
List of
formal
operands
STEP 5
user
program
Fig. 2-4 Structure of a function block (F B/F X)
Function B locks
CPU 928B Programming Guide
2 - 26 C79000-B8576-C898-01
The memory contains all the information that the programmer needs
to repr es ent the function b lock grap hic ally wh en it is call ed and to
check the operands during parameter assign ment and programming o f
the fu nctio n block. The programmer rejects incorrect input.
When handling f unction blocks, distinguish between the following
procedures:
•• programming FB/FX
and
•• calling FB/FX and then assigning actual va lues to the para mete rs .
Di stinction: "program min g" –
"calling and assigning
parameters"
When programming, y ou specify the function of the block. You m ust
dec id e which i n put o peran ds t he fu nc ti on requires an d which ou t put
resu l ts it sh o ul d tra ns fe r to t h e c al lin g prog ra m. Yo u def in e the in put
operands an d output results as formal operands. These functi on as
tokens.
When a block is called by a higher order block (OB, PB , SB, FB, FX),
the formal operands (block parameters) are replaced by actual operands;
i.e. parameters are assigned to the function block.
How to program
IF... THEN...
You want to p rogram a functio n
block "directly", i.e. with out
formal operands.
Program it a s yo u wou l d a
program or sequence block.
You want to use formal operands
in a f unction block. P roc e ed as exp l ained on the
f ollowing pages.
Make sure you keep to the
required order:
First program the FB/FX wit h the
formal operands and keep it on
the PG (of fline) or in the CPU
memory (o n lin e)
T he n program the block(s) t o be
called with the actual operands.
2
Function B locks
CPU 928B Programming G uide
C79000-B8576-C898-01 2 - 27
2.3.2
Pro gr am m ing Fu nctio n
Blocks You can program a function block only in the "statement list"
met hod of representation. When entering a function block at a
programmer, perform the following steps:
Step Action
1Enter the block ty p e ( FB /FX) and the number of the
func ti on bloc k.
Number your function blocks in descending order
startin g wit h FB 255, so that t hey d o not colli de with
the standard function blocks. The standard f unction
bloc ks are numbered from FB 1 to FB 199.
2Enter the name of the function block.
The name c an hav e a ma ximu m of ei ght ch a ract ers
and must start with a letter.
3If the function block is to process for mal operands:
Enter the formal operands y ou require in the block as
block parameters.
Enter the f ollowing information for each formal
operand:
- the name of the block parameter (maximum
4 characters),
- the type of block param eter and the data type of
th e blo ck parame te r (if applica ble )
Yo u can defin e a maximum of 40 for mal oper ands.
4 Enter your STEP 5 progra m in the form of a statement
list (STL). The formal operands are preceded by an
e qua li ty sig n (e.g . A = X1). Th ey c an a lso be refere n ce d
m ore tha n once at v ariou s positi ons in t he fu nc ti o n block .
5 Ter mi nate your progr a m input wit h the blo ck end
operation "BE".
Function B locks
CPU 928B Programming Guide
2 - 28 C79000-B8576-C898-01
Note
If you change the order or the number of formal operands in the
f ormal operand lis t, you m u st also up date all STEP 5 s tatements
in the function block that reference a for mal operand an d also
the block parameter list in the calling block!
Program or change fu nction blocks onl y on diskette or hard disk
and then transf e r t he m to your CPU !
Form al operands
T he following parameter and data types are permitted as the formal
operands of a function block (also known as block param eters):
Parameter type Data typ e
I = input parameter
Q = output paramet er BI/BY/W/D
D = d ata KM/KH/KY/KS/ KF/
KT/KC/KG
B = block op eration
T = tim er
C = counter
none
(no type can be speci fied)
I, D, B, T or C a re pa ra me ters tha t are in d icat ed t o th e left of the
function symbol in graphic representation.
Parameters labelled with Q are indicated on the right of th e fu n ction
symbol.
The d at a t y pe i nd i ca te s whet h er yo u are workin g wi th bit s, by t es,
words or double words for I and Q parameters and which data format
applies to D para meters (e.g. bit pattern or hexadecimal pattern).
Table 2-5 Per mi tt ed f o rmal o per and s fo r funct ion b lo c ks
2
Function B locks
CPU 928B Programming G uide
C79000-B8576-C898-01 2 - 29
2.3.3
Call ing Func t io n Block s and
Assigning Par amete rs to
them
You can call every f unction block as often as you want anywhere in
your STEP 5 program. You can call function blocks in a statem ent list
or in one of the graphic methods of representation (CSF or LAD).
To c al l a fu n ct ion blo ck a n d assig n parameters to i t, perfo rm th e
followi ng st eps:
Step Action Reaction on PG
1 Make sure th at the c alle d function block ex is ts ei th er
in the PG memory (offline ) o r in the C PU memory
(online).
none
2 Enter the call statement f or the function block in the
b loc k wh e r e the ca ll is to orig inate .
Yo u can program a function block ca ll in an
organization, program or sequen ce bloc k or
in another function block.
After you en ter th e call statement
(e .g. JU FB200) , the name of t he
relevant f unction block and the formal
operand list appear automatically.
3 Assign the actual operand relevant to t his call to
each of the formal operands, i.e. you assign
parameters to the funct ion block.
These actual operands can be d i fferent for
separate calls (e.g. inputs and outputs for the
first call of FB 200, flags for the second call).
Using the formal opera nd list, you assign the
required actual operands for each function
block call.
none
Unconditional/conditi onal call
Unconditional call C onditional call
" JU FBn" for FB function blocks or
"DOU FXn" for FX ex tended function blocks:
the referenced function block is processed
reg ard less of the prev i ous re sult o f lo gic
oper ati on ( R LO).
"JC FBn" f or FB f unction blocks or
"DOC FXn" for FX extend ed fun cti on blocks :
the ref erence d function block is on ly
proc es sed w h e n th e result of log ic o peratio n
RLO = 1. If RLO = 0 th e bl ock call is n ot
execu ted . Re gar dl ess of whet her th e bl ock cal l
is executed or not, the RLO is alsways set to "1".
After the unconditional or conditional call, the RLO can no longer be com bined logically. However, it is
carried over to the called f unction block with the jum p and can be evaluated there.
Function B locks
CPU 928B Programming Guide
2 - 30 C79000-B8576-C898-01
Permitted actual operands
Which operands can be assigned as actual op erands is shown in the
foll owing ta b le.
Parameter
type Da ta type Actual operands permitted
I, Q BI fo r an operand
wit h bit address
BY fo r an operand
with byte address
W for an operand
wi th word ad d re ss
D fo r an operand
with double word address
I n.m input
Q n.m output
Fn.mflag
IB n i nput byte
QB n output byte
FY n flag b yte
DL n data byte left
DR n data byte right
PY n peri phe ral byte
OY n b yte from extended periphery
IW n i nput word
Q W n output word
FW n flag word
DW n d ata word
PW n periphe ral word
OW n word fro m exte nde d periphery
ID n input do u bl e w o rd
QD n outp ut double wor d
F D n f l ag do ub l e wo r d
DD n d at a do u ble w o rd
DKM f or a binary pa ttern (1 6 bits)
KY fo r tw o absolu te numbers,
on e byt e each, e ach in t he
range from 0 to 255
K H for a he xadecimal pattern
w ith a ma ximum of four
digits
KS for tw o alphanumeric
characters
KT for timer v alue (B CD-
coded) units .0 to .3 and
values 0 to 999
K C fo r a co unter value
0 to 999
Constants
Table 2-6 Permitted actual operands for function blocks
2
Function B locks
CPU 928B Programming G uide
C79000-B8576-C898-01 2 - 31
Parameter
type Da ta type Actual operands permitted
Table 2-6 continued:
D
(Cont.) KF for a fixed po int number
-32768 to +32767
KG for a fl oa ti ng point
number1)
Constants
BData ty pe designation not possible DB n Data block; the operation
C DB n is executed
FB n Function block (permitted
only without parameters)
called unconditionally (JU . .n)
OB n Organization block called
unconditionally (JU . .n)
PB n Progra m blocks - called
unconditionally (JU . .n)
SB n Sequence blocks - called
unconditionally (JU . .n)
TData type desi gnati on not possible T 0 to 255 Ti mer
CData type designation not possible Z 0 t o 255 Counter
1) ±0.1469368 x 10-38 to ±0.1701412 x 1039
Note
S fl ags are not permitted as actual operands f or f unction blocks.
After th e ju mp t o a funct io n bloc k, th e ac tua l operand s fro m th e block
the n call ed a re used in t he func ti on blo ck program i ns te ad o f th e
formal operands.
Thi s fea tu re of pro gramm able fu nc ti on blo ck s a ll o w th e m t o be used
for a wi de va rie ty of pur poses in your user program.
Function B locks
CPU 928B Programming Guide
2 - 32 C79000-B8576-C898-01
Examples
Example 1: the foll owin g (com plet e) exa mple i s in te nded to fu rthe r
clarify the pr og ramm in g an d ca ll ing of a f unct ion bl ock an d th e
assign ment o f pa rame te rs t o it. You yo urse lf c an eas ily
try ou t th e exam pl e.
Programming the function block FB 202:
FB 202
SEGMENT 1
NAME EXAMPLE
DECL : INP1 I/Q/ D/ B/T/ C: I BI /BY/ W/ D: BI
DECL : INP2 I/Q/ D/ B/T/ C: I BI /BY/ W/ D: BI
DECL : OUT1 I/Q/ D/ B/T/ C: Q BI /BY/ W/ D: BI
:A= INP1
:A= INP2
:== OUT1
:
:BE
Function block FB 202 is called and has parameters assigned to
it in program block PB 25:
STL method of representation CSF/LAD method of representation
PB 25
SEGMENT 1
: JU FB 202 FB 202
NAME : EXAMPLE EXAMPLE
INP1 : I 13.5 I 13.5 INP1 OUT1 Q 23.0
INP2 : F 17.7 F 17.7 INP2 :BE
OUT1 : Q 23.0
:BE
The following operations are executed after the jump to FB 202
: A I 13 .5
: A F 17 .7
: = Q 23 .0
Formal
operand
list
STEP 5
state-
ments
Formal
operands Parameter
type Data
type
Formal
operandes Actual
operands
2
Function B locks
CPU 928B Programming G uide
C79000-B8576-C898-01 2 - 33
Example 2: calling a fu nction b lock and ass igning p aram eters to it with
the STL and CSF/LAD meth ods of repre sentation in a program block .
STL method of representation
PB 25
SEGMENT 1
:
:CDB5
:
: JU FB 201
NAME : REQUEST
DATA : DW 1
RST : I 3.5
SET : F 2.5
MTIM : T2
TIME : KT 010.1
TRAN : DW 2
BEC : Q 2.3
LOOP : Q 6.0
:BE
CSF/LAD method of representation
PB 25
SEGMENT 1
FB 201
REQUEST
DW1 DATA TRAN DW 2
I 3.5 RST BEC Q 2.3
F 2.5 SET LOOP Q 6.0
T2 MTIM :B E
KT 010.1 TIME
Formal
operands Actual
operands
Function B locks
CPU 928B Programming Guide
2 - 34 C79000-B8576-C898-01
2.3.4
Special Function Blocks Apart from th e funct io n blo cks tha t yo u program yourse lf, you ca n
order standa rd functio n blo cks as a finishe d so ftware product . T he se
con ta in s ta nda rd fu n ct ion s fo r ge n eral u se (e.g. sig n al li ng fun ct ion s
and sequence control).
St andard func tion blocks are assigned numbers FB 1 to FB 199.
If you order standard funct ion blo cks, remember the special
i nstructions in the accompanying description (i.e. areas assig ned and
conv ent io ns e tc.) .
T he sta ndard fu nction blocks for the S5-135 U are liste d in c at al o g
ST 57.
Example
Floating point root extractor RAD:GP FB 6
The function block RAD:GP extracts the root of a floating point number
(8-bit exponent and 24-bit mantissa). It forms the square root. The
result is also a floating point number (8-bit exponent and 24-bit
mantissa). The least significant bit of the mantissa is not rounded up
or down .
If ap plic ab le, for th e re st of the pr oces sing , the func ti on b lo ck s ets
the "radicand negative" identifier.
Numerical range:
Radic and - 0.14 6936 8 Exp. -38 t o +0 .1 7014 12 E xp . +3 9
Root +0.3 8334 34 E xp . - 19 to +0.1 30 4384 Exp . +20
Function: Y = √
A
Y = SQRT ; A = RADI
Calling the function block FB 6:
In the exa mple, th e ro ot is ex tracted from a float ing poin t nu mber tha t is
locate d in DD5 of DB 1 7 with a n 8-bit expo nent and a 24-bi t ma ntissa. The
result , an other 32 -bit floatin g point numb er, is w ritten t o DD 10. Pri or
to thi s, t he appro pria te data block mu st b e opened . The pa rame ter VZ
(param eter type: Q , da ta type: BI) ind icat es the s ign of t he r adicand: VZ
= 1 fo r a negative rad icand.
Occupi ed f lag word s: F W 238 to FW 254.
Continued on the next page
2
Function B locks
CPU 928B Programming G uide
C79000-B8576-C898-01 2 - 35
Using F
B 0
If you have not programmed organ ization block OB 1, the system
program calls FB 0 (provided it is lo aded) c yclically instead of OB 1.
Sinc e you hav e th e to ta l opera tio n set o f th e STE P 5 programmi n g
language available in a function block, programming FB 0 instead of
FB 1 can be an advantage, particularly when you wish to execute a
short ti me-critical program.
Note
Yo u should on ly use FB 0 for p rogr a mming cyclic program
e xecution (it must not contai n paramet ers).
If both OB 1 a n d FB 0 are lo ad e d, the syst em program w il l onl y
ca ll organization block O B 1 cyclically.
"Floating point root extractor" continued:
STL me thod o f re pres en tati on LAD m etho d of r epre se ntat ion
Seg - : C DB 17
ment : SEGM EN T 2
1:***
: JU F B 6 FB 6
Seg- NAME : RAD : GP RA D
ment RADI : DD 5 DD 5 RAD I VZ F 15.0
2 VZ : F 15 .0 SQRT DD 1 0
*) SQRT : DD 1 0 :BE
DD= da ta d ou ble word
*) Must be lo cate d in s epar at e se gmen ts , si nce th e op erat io n "C D B 17 "
in segment 1 cannot be converted to LAD/CSF.
Function B locks
CPU 928B Programming Guide
2 - 36 C79000-B8576-C898-01
2.4 Data Blocks
Data blocks (DB) or extend ed data blo cks (DX) are used to store the
fixed or variable data with which the user program works. No STEP 5
operations are processed in data blo cks.
The data of a data block includes the following:
•• various bit patterns (e.g. for stat us of a controlled process)
•• numbers (h exadecima l, bin ary, d ecima l) fo r time r value s or
arithmetic results
•• alphanumeric characters, e.g. for message texts.
Struc ture of a data bl ock
A data block (DB/DX) consists of the following parts:
•• bl ock preheader (DV, DXV),
•• block header
•• block body.
Block preheader
The block preheader is created automatically on the hard or floppy
disk of the PG and n ot transferred to the CPU. I t co ntains the data
format s o f th e dat a w ords entere d in the bloc k body. You h ave no
inf lue nc e ov e r th e crea ti on of t h e bl oc k pre hea de r.
Note
When yo u transfer a data bl oc k f rom the PLC to di skette or ha rd
disk, th e cor res pondi ng bloc k pre h ea der can be d e leted. Fo r this
reason, you m ust never m odify a data block with dif ferent data
form ats in the PL C and then transf er it back to diskette, otherwise
all the data words in the DB are automatically assigned the data
format you selected in the presets screen form.
2
Data Blocks
CPU 928B Programming G uide
C79000-B8576-C898-01 2 - 37
Block header
The block header occupies f ive words in the m em ory and contains
t he fo ll ow in g:
•• the block iden tifier
•• the programmer identifier
•• the bl ock type and the block number
•• the library n umb er
•• the block length (in cl uding the lengt h of the block header).
Block body
The block bod y contains the data words wi th which the user program
works. These data word s are in ascending order in the block bod y,
starting with data word DW 0. Each data word occupi es one word
(16 bits) in the memory.
M aximum length
A data block can occupy a total of maxim um 32 767 words (including
header) in the CPU m em ory. W hen you use your programmer to enter
and t ra n sfer d at a bl ock s, re me mber the size of yo u r CPU memo ry!
Data Blocks
CPU 928B Programming Guide
2 - 38 C79000-B8576-C898-01
2.4.1
Creating Data Blocks To create a data block, perform the following steps:
Step Action
1 E n ter the blo ck t ype (DB/DX) and d at a block number
between 3 an d 255.
2 Enter individual data word s in the data format you
require.
(Do not com plete your input of the data words with a
BE state ment!)
Note
Data blocks DB 0, DB 1, DX 0, DX 1 and DX 2 are reserved for
speci fic functions an d you cann ot use the m freel y for other
fun ctions (see Secti o n 2. 4.3)!
Type Data forma t Examples
KM Bit pattern 00100110 00111111
KH Hexadecimal 263F
KY 2 Bytes 038,063
KF Fixe d point nu mber +09791
KG Fl oat in g point number +1356123 +12
KS Character ?!ABCD123-+.,%
KT Timer va lue 055.2
K C Counter value 23 4
T ab le 2-7 Dat a fo rm ats permi tted in a da ta block
2
Data Blocks
CPU 928B Programming G uide
C79000-B8576-C898-01 2 - 39
2.4.2
Open in g Data Bl ocks Yo u can on ly open a d a ta blo ck (DB /DX) unconditionally. This is
possible wit hin an organization, program, sequence or fu nction block.
You can open a specific data block more than once in a program.
T o open a data block, perform the following steps:
IF... THEN...
You want t o op en a DB da ta
block Type in the STEP 5 operation
"C DB.."
You want t o op en a DX data
block Type in the STEP 5 operation
"CX DX.."
Vali dity of a data block
A f ter y o u op en a data b lock, all s tatement s that follow with the
oper and area ’D’ re fer to the op ene d da ta b l ock.
The opened data block also remains valid when the program is
continued in a dif ferent block following a block call.
If a second data block is opened in this new block, the second data
block is only valid in the newly called block f rom the point at which it
is called. After program execution returns to the calling block, the old
data block is once again valid.
Access
You can access th e data st ored in the opened da ta block during
program execu tion us in g load or transfer opera tion s (refer to
Chapter 3 for m ore detailed inform ation).
With a binary operation, the addressed data word bit is used to f orm
the RLO. The content of the data word is not changed.
With a set/reset operatio n, the addressed data word bit is assi gned the
value of the RLO. The content of the data word may be changed.
A load op eration transfers the con tents of the referenced data word
into ACCU 1. The contents of a data word are not changed.
A trans fer operati on transfers data from ACCU 1 to th e referenced
data word. The old co nte nts of the data word a re overwritten.
Data Blocks
CPU 928B Programming Guide
2 - 40 C79000-B8576-C898-01
Note
Bef ore accessing a data word, you m ust open the data block you
requ ire in yo ur pro gram. This is th e onl y w ay t hat th e CPU ca n
find the correct data word.
The referenced data word m ust be contained in the opened block,
oth erwi se th e system progra m dete cts a loa d or transfe r error.
With l oa d and tra ns fer operations, you can only a ccess dat a word
numbers up to 255!
An opened dat a block remains valid until one of the following
eve nts occur:
a) a sec ond d at a block i s open e d
or
b) the block, in which the data block was
opened, is completed with ’BE’, ’BEC’
or ’B EU’.
Examples
Example 1: tran sfer ri ng d ata wo rds
You want to transfer the contents of data word
DW 1 from d ata bloc k DB 1 0 to d ata wo rd D W 1 of
data bloc k DB 2 0.
Enter the following statements:
:C DB 10 (ope n DB 1 0)
:L DW 1 (load the co nten ts o f DW 1 i nto
: ACCU 1)
:C DB 20 (ope n DB 2 0)
:T DW 1 (trans fer th e co nten ts of AC CU 1
: to DW 1)
:
2
Data Blocks
CPU 928B Programming G uide
C79000-B8576-C898-01 2 - 41
Example 2: range of v al idit y of d ata bloc ks
(Fig . 2- 5)
Data block DB 10 is opened in program block
PB 7 (C D B 10). Dur in g th e subs eque nt pro gram
execu tion , the data o f th is dat a bl oc k ar e
processed.
After the call (JU PB 20) program block PB 20
is pr oc esse d. Dat a bl ock DB 10, how ev er,
remains valid. The data area only changes when
dat a bl ock DB 11 (C DB 11 ) is ope ne d.
Data bloc k DB 1 1 no w rema in s va lid un til the
end o f pr og ram bloc k PB 2 0 (BE) .
After the jump back to program block PB 7,
data block DB 10 is once again valid.
PB 7
CDB11
BE
PB 20
CDB10
JU PB 20
BE
Range of validity of DB 10
Range of validity of DB 11
Fig. 2- 5 Range of validi ty of an opened data block
Data Blocks
CPU 928B Programming Guide
2 - 42 C79000-B8576-C898-01
2.4.3
Special Data Blocks On the CPU 948 data blocks DB 0, DB 1, DX 0, DX 1 and DX 2 are
reserved for special functions. They are managed by the syste m
program and you cannot use them f reely f or other functions.
DB 0
•• Da ta block DB 0 (see Section 8.3.2)
Dat a bl oc k DB 0 co n ta in s the add re ss li st wit h th e sta rt ad dresses
of all blocks that are located in the data block RAM of the CPU.
The system pro g ram ge n erates this add ress list duri n g
in itialization ( f o llo w ing each POWER UP or O VERA LL RES ET)
and it is updated autom atically when you use a programmer to
chan g e da ta bloc ks o r ge n erate a n e w d at a bloc k .
DB 1
•• Da ta block DB 1 (s ee Se ctio n 10.1.6)
Data block DB 1 contains the list of digital inputs/outputs (P
peripheral with relative byte addresses from 0 to 127) and the
interprocessor communication (IPC) flag inputs and outpu ts that are
assigned to the CPU. If applicable, the block may also contain a timer
field length.
DB 1 can have parameters assigned and be loade d as follo ws:
to reduce the cycle time in single processor operation, since
only the inputs, outputs or timers entered in DB1 are updated.
D B 1 must be a ssigne d paramet ers an d lo ad e d as follo ws:
a) for multiprocessing
b ) when IPC fl ags exist wi th CPs
DB 2
•• Data block DB 2 (see S ection 4.4.3)
You u se d at a block DB 2 t o ass ign paramet ers to t he c losed lo o p
c ontroller struct ure R64. The closed loop control function ca n be
ordered as a soft ware pro d uc t an d o perates suppo rted by t he
system pro g ram.
2
Data Blocks
CPU 928B Programming G uide
C79000-B8576-C898-01 2 - 43
DX 0
•• Da ta block DX 0 (see Chapter 7)
I f you assign para meters to data block DX 0 and load it, you can
change the d e faults o f certain system program functions (e.g. the
start-up procedure) and adapt the performance of the s ystem program
to your particular application.
DX 1
•• Da ta block DX 1
Reserved.
DX 2
•• Data block DX 2 is used to specify the communication via the
sec o nd serial in te rfa ce . See th e "CPU 928B C ommun ic at ion "
Man u al for de tail s of as signin g paramete rs to t h is bl ock (/14/ in
Chapter 13).
Data Blocks
CPU 928B Programming Guide
2 - 44 C79000-B8576-C898-01
Contents of Chapter 3
3.1 Principle of Program Exec ution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 4
3.2 Program Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 5
3.3 Storing Program and Data Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 10
3.4 Processing the User Progra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 11
3.4.1 D efin ition of Terms used i n Program Execution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 12
3.5 STEP 5 Operations with Exa mples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 15
3.5.1 Basic Operati ons. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 19
Binary logic operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 19
Set/reset operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 20
Load and transfer operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 21
T imer and counter operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 26
Arith metic operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 31
Comparison operatio ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 32
Block operatio ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 32
NOP/display/stop operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 33
3.5.2 Programming Examples in the STL, LAD and CSF Methods of Representation. . . . . 3 - 34
3.5.3 S upplementary Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 49
Binary logic operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 50
Digital lo gic o per a tions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 50
Set/reset operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 51
T imer and counter operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 52
Load and transfer operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 54
Arith metic operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 56
3
3
Program Execution
CPU 928B Programm ing Guide
C79000-B8576-C898-01 3 - 1
3.5.4 E xec utive Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 58
Jump operatio ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 58
Shift operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 60
Conversion operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 62
Decre ment/increment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 6 5
Processing operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 65
Disabling/enabling process interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 71
3.5.5 Semaphore Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 75
Contents
CPU 928B Programming Guid e
3 - 2 C79000-B8576-C898-01
3Program Execution
T his chapter is i ntended for readers who do not yet have any great
e xperie nce in using the progra mmin g la nguage. The chapter therefore
deals with the basics of STEP 5 programming and explains in detail
(with e xamples) the STEP 5 operations for the CPU 928B.
E xperienced readers who require more infor mation about a specific
STEP 5 operation listed in the Pocket Guide can refer to the re ference
secti on in 3.5.
3
CPU 928B Programming G uide
C79000-B8576-C898-01 3 - 3
3.1 Prin cip le of Pr ogram Ex ec u tio n
You can pr oce s s your ST EP 5 use r pro gr a m i n va ri ou s ways .
Cyclic program execution is m ost common with programmable
c ontrollers (P LCs). The s yste m program runs through a program loop
(the cy cle, refer to Section 3.4) and calls organization block OB 1
cyclically in each loop (refer to Fig. 3-1).
Call OB1 BE
Call PB 20
BE
PB 20
OB 1
Update inter-
processor comm.
flag outputs
image outputs
(PIQ)
Update process
Trigger cycle time
Update inter-
processor comm.
flag inputs
image inputs
(PII)
Update process
from start-up
System program User program
Fig. 3-1 Principle of cycl ic program execution
Principle of Program Execution
CPU 928B Programming Guide
3 - 4 C79000-B8576-C898-01
3.2 Pro gr am Org a niza tio n
Progra m organization allo ws you to specify which conditions affect the
processing of your blocks and the order in which they are processed.
Organize your progra m by programming organization blocks with
conditional or unconditional calls for the blocks you require.
Yo u ca n ca ll ad dit io n al program, fun ct io n an d se quence block s in a ny
combination in the program of individual organization, program,
function and sequence blocks. You can call these one after anot her or
nes ted in one another .
F or m a ximum efficiency, yo u should organize your program to
empha si se th e most im portant pro gra m stru ct u re s a n d in su c h a w a y
t hat you can cle arly recog nize parts of t he controlled syste m which are
re lated in the softwa r e.
Figs. 3-2 a n d 3-3 a re e xa mples of a prog ram st ruc tu re.
3
Program Organization
CPU 928B Programming G uide
C79000-B8576-C898-01 3 - 5
PB ‘B‘
O
B1 PB’A’ FB
FB
Go to initial
state
Stop to the system
EMERGENCY
OFF
PB ‘D‘
Message output
FB
Message output
via standard
peripherals
FB
Message output
via standard
peripherals
DX
Message
texts
PB ‘C‘
Individual
control level
FB
Group
initialization
DB
Interface flags
of the individual
control
elements
FX
Individual
initialization
FX
Individual
initialization
Sequence
control Control of
sequence
cascade
FB SB
Sequence
step
SB
Sequence
step
JU PB ’A’
JU PB ‘B‘
JU PB ‘C‘
JU PB ‘D‘
BE
Operating mode
program
Fig. 3-2 Example of the organizati on of the user program according to the program structure
Program O rganization
CPU 928B Programming Guide
3 - 6 C79000-B8576-C898-01
O
B1
JU PB ‘X‘
JU PB ‘Y‘
BE
Controlled
system part ‘Z‘
PB ‘X‘
Controlled
system part ‘X‘
FB
Individual control
FB
Closed loop control
FX
Signalling
Controlled
system part ‘Y‘
PB ‘Y‘ FB
Sequence control
FX
Signalling
FB
Closed loop control
FB
Arithmetic
JU PB ‘Z‘
FB
Data logging output
FB ‘Z‘
Fig. 3-3 Example of the organizati on of the user program according to the structure of the control led system
3
Program Organization
CPU 928B Programming G uide
C79000-B8576-C898-01 3 - 7
Nesting blocks
Fig. 3-4 shows the principle of nested block calls.
Block addresses
A block start address specifies the location of a block in the user
memor y (oder DB-RAM). For logic blocks, this is the address of the
memory location containing the f irst STEP 5 operation (with FB and
FX, the JU operation via the f orm al operand list); with data blocks, it
is the address of the first dat a word.
To e n able t he C PU t o loca te t he c al le d blo ck i n the me mory, th e st art
ad d resses of a ll v al id bloc ks a re e ntered in t he blo c k ad dre ss list in
data block DB 0. DB 0 is m anaged by the system program, you cannot
cal l it you rse lf.
The CPU stores a return address every time a new blo ck is called. A fter
the new block has been processed, this return addre ss enables the
program to find the block fro m which the call originated. The return
address is the address o f the memory location containing the next STEP 5
statement after the block call. The CPU also store s the s tar t add ress and
length o f th e data b lock valid at this location.
O
B1
BE
PB 20
BE
PB 5
CC
DB 20 DB 30
BE
JU PB 5
F 200.5 *)
JU JU
PB 20 FB 30
=Q 60.6*) NAME: KURV
AI 55.0 *)
*
)Operation to which the program returns
A
1st STEP 5 Op. 1st STEP 5 Op.
Fig. 3-4 Nested l ogi c block calls
Program O rganization
CPU 928B Programming Guide
3 - 8 C79000-B8576-C898-01
Nesting depth
You can only nest 62 blocks within one another. If more than 62
block s are call ed, t he C PU s ig nal s a n error a nd go es to th e sto p mode .
Exa mple of nest ing dept h
You can determine the nesting depth of your program as follows:
- Add all the organization blocks you have programmed
(in the example: 4 OBs).
- Add the n esting d epth of the individu al o rganizat ion blocks
(in the e xample: 2 + 2 + 1 + 0 = 5).
- Add the two amounts together to obtain the program nesting depth
(in the example: 4 + 5 = nest i n g d e p t h 9 ) . I t m ay n o t e xc e e d a valu e
of 62.
OB 25
Nesting depth
123456789
OB 1 PB 1 FB 1
OB 13 PB 131 FB 131
OB 2 FB 21
Program
processing
level
Fig. 3-5 Exa mp le of block nes ti ng de pth
3
Program Organization
CPU 928B Programming G uide
C79000-B8576-C898-01 3 - 9
3.3 Storing Program and Data Blocks
You must load your program into the user memor y so that the CPU
can proc e ss i t. As prog ra m me mory you can use a p l ug -in sub mo d ule
(opt io n al either RA M or E PR OM) and the DB-RAM.
Diffe rent storage types
1) •• If you use a plug- in RAM submodule yo u can tran sfe r you r
pro g ram di rectl y from th e prog ram m er to the CPU.
You can change the contents of a RAM submodule quickly and
easily. A central back-up batter y prevents your program being
del eted in the memory if the p ower goes of f .
All programmed blocks are stored in random order in the RAM
(see Sec tio n 2.1. 5, Fig. 2-2). I f you c han ge a blo c k, the se quence
of the blocks in the RAM also changes.
I f you use a RAM sub module wi th a bac k-up bat ter y, you can
remove it from the CPU without losing data. Havin g its own
b attery protects the submodule from loss of data and ensur es
that the d ata is retained until it is required a gain.
•• Yo u can also stor e you r c ompl ete pr o g ram in plug- in EPROM
submodules. Your program is completely protected in EPROM
submodules even when the power goes off and no back-up battery
is nece ssary.
You cannot change the contents of an EPROM submodule from
t he PC. For this reason, data blocks that contain variable data t hat
have to be changed during the course of y our program m ust be
copied fro m th e EPROM subm odule to t he d a ta block R AM o f t he
CPU during the first cold restart following an overall reset. You
must program th i s func ti on (see specia l funct io n OB 254 an d
OB 255, Se ction 6.4.6).
•• Data blocks DB/DX are written into the DB-RAM b y ge ne r at in g
or copying them. If you transf er data blocks from the PG to the
CPU, they are written to the DB-RAM if the RAM submodule is
full o r if an EPROM submodu le is plugged in.
Caution
Battery-backed RAM submodules must not be programmed via
the EPROM interf ace; this can damage the RAM.
1) When storing data blocks, please note the possibility of "alternative loading" - Section 2.1.5.
Storing Program and Data Blocks
CPU 928B Programming Guide
3 - 10 C79000-B8576-C898-01
3.4 Processing th e User Program
The co m pl et e so ftw are o n the CPU (c ons isting o f th e system prog ram
and the S TEP 5 user p rog ram) has the following tas ks:
•• CPU START-UP
•• Controlling an au to mation proce s s by continuousl y r epe atin g
operatio ns (CYCLE).
•• Cont ro llin g a n au to mation proce s s by reactin g to even ts
occurring sporad ically or a t cer tain times ( int err upts ) and
reactin g t o er rors.
For al l t hre e ta sk s, yo u ca n se lect specia l parts of yo ur prog ram to ru n
on th e CPU by programmin g u ser in te rfa ce s (org a niza ti o n bl ock s
O B 1 to O B 35 - refer t o Secti on 2.2.1).
START-UP
Before the CPU can star t cyclic progr am execution , an initialization
must be perfo rm e d to e st ablish a d efine d init ia l sta tu s fo r c yc li c
prog ram ex e cuti o n an d, fo r ex ample , t o spec ify a ti me base fo r th e
execution of certain functions. The way in which this initialization is
perfor med depen ds o n the event that led to a START-UP an d on
se tt in gs tha t you c an mak e on yo ur CPU. F or more de tail ed
inform ation, refer to Chapter 4.
You ca n in fluenc e t he ST ART-UP procedu re o f yo ur CPU by
programming organization bloc ks OB 20, OB 21 and OB 22 o r by
assi gni ng parameters in DX 0 (refer to Chapter 7).
CYCLE
Foll ow i n g th e STA RT-UP, th e syste m pro gra m go e s over t o cycl ic
pro c essin g . I t is respons ible fo r back g rou n d fun c ti ons re quired fo r the
autom ation tasks (refer to Fig. 3-1 at the beginning of this section).
After the sy stem functions have been executed at the beginning of a
CYCLE, the system program calls organization block OB 1 or
fu nctio n blo ck FB 0 as the cyclic user progr a m. Y ou progr a m the
STEP 5 operations for c yclic processing in t his block.
3
Processing the User Program
CPU 928B Programming G uide
C79000-B8576-C898-01 3 - 11
Reactions to interrupts
and error s
T o allow you to speci fy the reactions to interrupts or errors, special
organization blocks (OB 2, OB6 an d OB9 to OB 18 for interrupt
servi cing, OB 19 and OB 23 to OB 35 for re ac tions to e rrors) are
available on the CPU 928B. You can store an appropriate STEP 5
program in these bl ocks.
When interrupts or errors are to be processed, the syste m progra m
activates the corresponding organization block during cyclic
proc essin g . T hi s mea n s t ha t th e cycl ic proc essin g i s i nt erru pt ed to
servi ce an i nte rrupt o r to reac t to a n error. Th e ne st ing o f th e
organization blocks has a fixed priority (for further informatio n, refer
t o Chapters 4 and 5).
In addition to the organization blocks, you can also influence the
rea ct io n o f the CPU to int errupt se rvicin g by a ssi g ni ng parameters in
data blo ck DX 0.
Orga n iz at ion blo ck s OB 1 to OB 39 ca n be calle d by the system
program as soon as th ey are loaded i n the program m e mory (also
during operation).
If th e OBs are n ot l oa d ed, t h ere is ei th er n o rea ct io n from t he C PU o r
(in the ev ent of errors) it goes to the stop mode (refer also to
Sec tion 5. 4).
You can also load da ta bloc k D X 0 int o the prog ram memo ry duri ng
operation like th e or ganiza tion b locks. It is, how ev er, only effective
after the next COL D RESTART. If DX 0 is not loaded, the stand ar d
settings app ly (refer t o Chapter 7).
3.4.1
Definition of Terms used in
Program Execution
Cycle time
The cycle begin s when the cycle m onitoring time is triggered and
e nds wit h the next trigger. The ti me that the CPU requires to execute
the program between two triggers is called the cycle time. The cycle
time co nsists of the runti me of the s yste m program and the runtime of
t he user program.
The cycle t im e ther efore incl ud es t he foll ow i ng:
•• the ti me required to proc es s the c yc li c pro g ra m (sys te m a n d us er
program),
•• the time required to process interrupts (e.g. time-controlle d
interrupt),
•• the time required to process in terrupti ons (errors).
Processing the User Program
CPU 928B Programming Guide
3 - 12 C79000-B8576-C898-01
Cycle tim e monitoring
The CPU monitors the cycle time in case it exceeds a max i mu m value.
The standard setting for this maximum value is 150 ms. You can set the
cycle time monitoring yourself or restart it during user program execution
(re fer to D X 0/Chapter 7 and special function OB OB 221 and
OB 222/Sections 6. 22 and 6. 23).
Process input and output
image (PI I and PIQ )
The process image of the inputs and outputs is a memory area in the
internal RAM.
Bef ore cyclic execution of the user program begins, the system
program reads the sig nal states of the input periph eral modul es an d
transfers them to the process input i mage. The user program evaluates
the signal states in the process input image and then sets the
appropriate signal st ates for the outputs in t he process output imag e.
Afte r th e user program h as been pro ce ssed , t he syst em prog ram
transfers the sign al states of the process output image to the output
peripheral mod ules.
Bu ffering the I/O sig nals in the process image of the inputs and
outputs avoids a chan ge in a bit within a program cycle from causing
t he corresponding o utput to "flutter ".
The proc ess im ag e is th e re f ore a memory area who se con te nt s are
out put t o th e periph erals a nd read i n from the peripherals once per
cycle.
Note
The process image only exists for input and output bytes o f the "P "
peripherals with byte addre sses fro m 0 to 127!
Interprocessor com m unication
(I PC) flags
IPC flags exchange data between individual CPUs (multiprocessing) or
between the CPU and some communication pro cessors.
The s ystem program reads the input IPC flags of the CPU before
cyclic execu tion of the user program begins. After the STEP 5
progra m is processed, the system program transfers the o utput IPC
flag s to the coordinator or to the commun ica tions proces sors.
You define the input and output IPC flags when you cre ate data block
DB 1 (re fer to Section 10.1.5).
3
Processing the User Program
CPU 928B Programming G uide
C79000-B8576-C898-01 3 - 13
Interrupt events
Cyclic program e xecution ca n be interrupted b y the fo ll owin g:
•• process interrupt-driven program processing,
•• time-controlled program processing,
•• delay interrupt,
•• t ime interrupt clock-controlle d.
T he cyclic program can be interrupted or even aborte d completely b y
t he fo ll ow in g:
•• a d evice hardware fault or program error,
•• o per ato r inter v e nti on (using the PC stop f u n ction, or s etting the
mode selector to "st op", multiprocessor st op MP-STP),
•• a stop operat io n.
Processing the User Program
CPU 928B Programming Guide
3 - 14 C79000-B8576-C898-01
3.5 STEP 5 Operations with Examples
A STEP 5 operation consists of the operati on and an operand. The
operation specifies what the CPU is to do (operatio n). The operan d
speci fies w ith w h a t a n operatio n is to be executed.
STEP 5 operations ca n be di vided into the followi ng groups:
•• basic opera tio n s (can be used in all logic blocks),
•• supple mentary op erations,
•• execu tive opera tion s (c an only be used in FB/FX function b locks ),
•• semaphore operations (can only be used in FB/FX functi on
blocks).
Accumul ators as working
registers
The CPU 92 8B ha s four accu mu lators, ACCU 1 t o ACC U 4. Most
STEP 5 ope rations use two 32-bit registers (ACCU 1 and ACCU 2)
as the sour ce of operan ds and the desti nat ion for resu lts.
T he STEP 5 operati on to be carried out a ffects the acc umulators, e.g.:
•• ACCU 1 is al ways th e de sti nat ion in l oad operatio ns. A loa d
operation shif ts the old contents of ACCU 1 to ACCU 2 (stack
lift). Accumulators 3 and 4 are no t changed by any load operations.
1) analo go us for A CCU 2 to ACCU 4
ACCU-1-H
High byte Low byte High byte Low byte
ACCU 1
1)
H i gh wor d L ow wo r d
31 24 23 16 15 8 7 0
ACCU-1-HL ACCU-1-LH ACCU-1-LL
ACCU-1-L
ACCU-1-HH
3
STE P 5 Operations with E xam ples
CPU 928B Programming G uide
C79000-B8576-C898-01 3 - 15
•• Arith metic operations combine the contents of ACCU 1 with th ose
of ACCU 2, write the result to ACCU 1 and transfer the contents
of ACCU 3 to ACCU 2 and the contents of ACCU 4 to ACCU 3
(stack drop). In 16-bit fixed point arithmetic, only the low word or
ACCU 3 is transf erred to the low word of ACCU 2 and the low
word of ACCU 4 to the low word of ACCU 3.
•• When a constant is added (ADD BF/KF/DH) to the contents of
ACC U 1, the accu mu l ators 2, 3 an d 4 are not c han g ed.
Condition codes
STEP 5 operations either set or evaluate condition codes. The condition
codes are written to a condition code byte. Two groups o f condition
codes can be distinguished: condition codes o f digital operations (word
condition codes - bits 4 to 7 in the condition code byte) and condition
codes from binary and executive operations (bi t condition codes - bits 0
to 3 in the condition code byte). You can see how the various condition
codes are in fluenced or evaluated by STEP 5 ope rations be re ferring to
the operation list (see /1/ in Chapter 13).
You can display the conditi on code byte on a programmer usi ng the
"STAT US" o n li ne function (re fer to Section 11.2.3). The by te ha s t h e
followi ng structure:
W o rd condition code s Bit condition code s
CC 1 CC 0 OV OS OR STA RLO ERAB
Bit 7 6 5 4 3 2 1 0
Bit condit ion codes
•• ERAB Fi rst bit scan
A logic operation sequenc e containin g binar y operations always
begins with the first bit sc a n, fol lowi ng which a new RLO is
fo rmed. The bit condition code ERAB = 1 is then set. W hile the
remaining logic operations in the sequence are being performed,
ERAB rem ains set to 1 and the RLO cannot be changed by these
l ogic oper ations.
The active sequence of logic operations is terminated by a binary
set/reset operati on (e.g . S Q 5.0). The set/reset operation sets
ERAB to 0; the RLO can be eval uated (e.g. by RLO-dependent
operations) but can no longer be combined logically. The next
binar y logic operation follo wing a binar y set/reset operation is
once again a f irst bit scan.
ST EP 5 O pe rations with Exam ples
CPU 928B Programming Guide
3 - 16 C79000-B8576-C898-01
Ex ample of ERAB
O ther bit conditio n codes
•• RLO Res ult of logic operatio n
T his is the result of bit logic operations. It is the truth state ment for
comparison operations (refer to operati ons list, binar y logic
o p erat io ns or c om p arison oper a tions ) .
•• STA Status
For bit operatio ns, this indicates the lo gical status of the bit just
scanned or set. The status is updated in binar y logic operations -
e xcept for A(, O(,), O and for set/reset operati ons.
•• OR Or
Internal CPU bit f or handling "AND bef ore OR" logic operations.
W o rd condition codes
•• OV Overflow
This indicates whether the pe rmissible number range was exceeded
during the arithmetic operation just co mpleted.
•• OS Stored overflow
It can be used in several arithmetic operations to indicate whether an
overflow occurred at any point during the operations.
:S Q 7.7 Last op er atio n of the pre -
vious logic operation
sequence
:A I 1.0 ERAB is set to ’1’,
: the new RLO is formed by
: a n AND op er atio n
:O I 6.3 The RLO is influenced by
: an OR operation
:AN I 2.1 The R LO i s infl uenc ed by
: a n AND NO T op erat io n.
:S Q 2.4 ERAB is set to ’0’,
: the sequence is now complete
:JC FB 150 The function block is called
: d epen dent o n th e RL O.
:
:
3
STE P 5 Operations with E xam ples
CPU 928B Programming G uide
C79000-B8576-C898-01 3 - 17
•• CC 1 and CC 0
These are the result condition codes that you can interpret from the
following table:
Note
To evaluate the condition codes dire ctly, co mparison and jump
operations are available (refer to Sections 3.5.1 and 3.5.3).
Word
condition codes Arith-
metical
operations
Digital
logic
operations
Com-
parison
operations
Shift
operations For
SED,
SEE
Jump
operations
executed
CC 1 CC 0
0 0 Result
= 0 Result
= 0 AC CU 2
=
AC CU 1
Shifted
bit
= 0
Semaphore
is
set JZ
0 1 Result
< 0 – AC CU 2
<
AC CU 1 ––
JM
JN
1 0 Result
> 0 Result
≠ 0A C CU 2
>
AC CU 1
Shifted
bit
= 1
Semaphore
is
set
or
enabled
JP
JN
1 1 Division
by 0––––
JN
Note
When a change of level takes place, e.g. servicing a timed interrupt,
all accumulators and the bit and word condition codes (RLO etc.) are
saved and loaded again when the interrupt ed level is resu med.
Table 3-1 Result c ondition co des o f STEP 5 operations
ST EP 5 O pe rations with Exam ples
CPU 928B Programming Guide
3 - 18 C79000-B8576-C898-01
3.5.1
Basic Operations You can us e t h e ba sic operat ion s i n all logic b locks a nd all me thod s of
represe nta tion (STL, LAD, CSF ).
Binary logic
operations
Operation Operand Function
A
O
I 0.0 to 127.7
Q 0.0 to 127.7
F 0.0 to 255.7
S 0.0 to 4095.7
D 0.0 to 255.15
T 0 to 255
C 0 to 255
AND logic operation after scannin g for sig nal state "1"
OR logic operat io n af ter scan nin g for signal state "1"
of an input in the PII
of an outp ut in the P IQ
of a flag bit
of an S flag bit
of a data word bit
of a ti mer
of a cou nter
AN
ON
I 0.0 to 127.7
Q 0.0 to 127.7
F 0.0 to 255.7
S 0.0 to 4095.7
D 0.0 to 255.15
T 0 to 255
C 0 to 255
AND logic operation after scannin g for sig nal state "0"
OR logic operat io n af ter scan nin g for signal state "0"
of an input in the PII
of an outp ut in the P IQ
of a flag bit
of an S flag bit
of a data word bit
of a ti mer
of a cou nter
O – Combine AND operations through logic OR
U(
O(
)
– ANDing of expressions in parentheses
ORin g of e x pre ssi on s in parent hese s
Clo se pa ren th e sis (to c omple te th e brack e te d exp re ssi o n)
Ma ximum of 8 leve ls are permitted, i.e. 7 opened brackets
RLO form ation
Th e binary l ogi c opera ti on s ge nerate the resu lt of log ic operatio n
(RLO).
At the be gin n in g o f a logi c sequ en c e, th e RLO o nly d epend s on t h e
sig nal state scanned (first scan) and not on the type of logic operation
(O = OR, A = AND).
T able 3-2 B ina ry logic oper at ions
3
Basic Operations
CPU 928B Programming G uide
C79000-B8576-C898-01 3 - 19
Within a sequence o f logic operations, the RLO is formed fro m the type
o f operation, previous R LO and the scanned signal state. A sequence o f
logic operations is co mpleted by an operation (e.g. set/re set opera tions)
which retains the RLO (ER AB = 0). Following this, the R LO can be
evaluated but cannot be further co mbined.
Example
Set/r eset operations
Operation Operand Function
S
R
I 0.0 to 127.7
Q 0.0 to 127.7
F 0.0 to 255.7
S 0.0 to 1023.7
D 0.0 to 255.15
Set i f RLO = 1
Res et if RLO = 1
an input in th e PII
an output in the PIQ
a fl ag
an S flag
a bit in the data word
=
I 0.0 to 127.7
Q 0.0 to 127.7
F 0.0 to 255.7
S 0.0 to 1023.7
D 0.0 to 255.15
The RLO is assigned to
an input in th e PII
an output in the PIQ
a fl ag
an S flag
a bit in the data word
Program Status RLO ERAB
:
= Q 0.0
A I 1.0
A I 1.1
A I 1.2
= Q 0.1
0
1
1
0
0
0
1
1
0
0
0 RLO retained
1 first bi t sca n
1
1
0 RLO retained, end o f
the logic op era tion s
sequence
T ab le 3-3 S e t/r es et operations
Basic Operations
CPU 928B Programming Guide
3 - 20 C79000-B8576-C898-01
Load and transfer
operations
Operation Operand Function
L
T
I B 0 to 127
IW 0 to 126
ID 0 to 124
QB 0 to 127
Q W 0 to 126
QD 0 to 124
FB 0 to 255
FW 0 to 254
FD 0 to 252
SY 0 to 1023
SW 0 t o 1022
SD 0 to 1020
DR 0 to 255
DL 0 to 255
D W 0 to 255
DD 0 to 254
PY 0 to 127
PY 128 to 255
P W 0 to 126
PW 12 8 to 254
OY 0 to 255
O W 0 to 254
Load
Transfer
an input by te from/to the PII
an input wo rd fr om / to the P II
an input double word from/to the PII
an output byte from/to the PIQ
an out put w or d from/to the PIQ
an output double word f rom/to the PIQ
a flag byte
a fl ag w o rd
a flag double word
an S flag byte
an S flag word
an S flag double word
the ri gh t byte of a da ta wo r d fr om/to DB, DX
the left byte of a data word from/to DB,DX
a data w o rd fro m/to DB, DX
a data double word f rom/to DB, DX
a peripheral byte of the digital inputs/ outputs (P area)
a periph eral byte of the anal o g or di gi ta l in put s/ou t put s
(P area)
a periph eral w ord of the digi ta l in put s/ ou tpu t s (P a re a)
a periph eral w o rd of the a n al og o r d ig i ta l i n put s/o u tpu ts
(P area)
a byte of the extended I/O area (O area)
a word of the extended I/O area (O area)
T ab le 3-4 L o a d and tran s fe r ope rations/part 1
3
Basic Operations
CPU 928B Programming G uide
C79000-B8576-C898-01 3 - 21
Operation Operand Function
L
KB 0 to 255
K S 2 ASCII
characters
KF -32768 to
+32767
KG 1)
KH 0 to FFFF
DH 0 to
FFFF FFFF
KM 16-bit pattern
KY 0 to 255 for
each byte
KT 0.0 to 999.3
KC 0 to 999
T 0 t o 255
C 0 to 255
Load
a con stan t, 1 byt e
a con stant, 2 ASCII c ha racte rs
a co nsta nt a s fixed point n umber
a constant as floating point number
a constant as hexadecimal num ber
a double word constant as a hexadecimal number
a c onstant as bit pattern
a con stan t, 2 byt es
a co nsta nt t im er v a lue (in BCD)
a constant counter value
a time r, binary c ode d
a co unt er, bin ary co ded
LC
T 0 t o 255
C 0 to 255
Load
a tim er
a co unt er
in BC D
1) ±0,1469368 x 10-38 to ±0,1701412 x 1039
Load operations
Load operat ions wri te th e address ed value into ACCU 1. The
former conten ts of ACC U 1 ar e saved in ACCU 2 (s tack lift).
Transfer operatio n s
Transfer operations write the contents of ACCU 1 to the addressed
memor y location.
T ab le 3-5 L o a d and tran s fe r ope rations/part 2
Basic Operations
CPU 928B Programming Guide
3 - 22 C79000-B8576-C898-01
Ex amples of load a nd
transfer operations
Example 1:
Fig. 3-6 il lust rate s load in g/tr ansf er ring a b yt e, w ord or dou bl e wo rd
from/to a memory area organized in bytes (P II, PIQ, f lags , I/O) .
:L IB i load byte i of the PII into ACCU-1-LL
:L IW j load bytes j and j+1 of the PII into ACCU-1-L
:L FD k load flag bytes k to k+3 in ACCU 1
ACCU 1
ACCU 1
ACCU 1
j
j+1
i
k
k+1
k+2
k+3
31 23 15 7 0
31 23 15 7 0
31 23 15 7 0
k+1 k+2 k+3
00jj+1
000i
70
Addresses
in
ascending
order
k
1) 1)
1) 1)
1)
LIBi
TIBi
TIWj
LIWj
TFDk
LFDk
1) only with load operations
Fig. 3- 6 Load and transfer operati ons i n a by te- ori ented memory area
3
Basic Operations
CPU 928B Programming G uide
C79000-B8576-C898-01 3 - 23
Note
Load operation s do not af f ect t he condition codes.
Transfer operations clear the OS bit.
When a byte or word is loaded the extra bits are cleared
in ACCU 1.
Ex ample 2:
Fig. 3-7 illustrates the loading/transfer of a byte, word or double word
from/i nto a memo ry a re a or ga nize d in words.
:L DR i load th e ri ght by te o f da ta wor d i in to A CC U-1- LL
:L DL j load th e le ft b yt e of dat a word j i nt o AC CU -1-L L
:L DW k load da ta w ord k into ACC U- 1-L
:L DD l load data words l and l+1 into ACCU 1
l
l+1
k
31 23 15 7 0
31 23 15 7 0
31 15 0
31
15
0
ACCU 1
ACCU 1
ACCU 1
ACCU 1
15 0
l
l+1
k
j
000i
000
1) 1) 1)
0
1) 1) 1)
1)
left byte
Data word j
LDRi
TDRi
LDLj
TDLj
LDWk
TDWk
LDDl
TDDl
right byte
Data word i
Addresses
in
ascending
order
1)
only with load operations
Fig. 3- 7 Load and transfer operati ons i n a word-oriented memory area
Basic Operations
CPU 928B Programming Guide
3 - 24 C79000-B8576-C898-01
Addressing I/Os
You ca n us e l oad a nd t ran sfer operati ons to a ddress t he I/O
periph era ls as follo ws:
•• directly using the follow ing operatio ns :
L../T.. ..PY, ..PW, ..OY, ..OW
or
•• usin g the process image with the following op erations :
L../T.. ..IB, ..I W, ..ID, .QB, ..QW, ..QD
a nd with logic and set/reset operations
Note
If you use the transfer operations T PY 0 to 127 and T PW 0 to
126, th e process ou tput im age is u pdated at th e same time.
Exc eption: c omma n d ou t pu t is d isabled by the STEP 5 ope ra ti o n
BAS (refer to Section 3.5.4).
Note the followin g points about I/O peripherals:
•• A process inp ut/ou tput image ex ists for 128 input and 128 output
bytes o f the P peripherals with byte addresses from 0 to 127.
•• No proc ess im ag e ex i sts for th e e n ti re a re a of t h e O pe riph erals
a nd the P peripherals with relative byte addresses fro m 128 to 256.
(For more information on address space allocation see
Se ction 8.2.2).
•• I/O m odules with addresses of the O peripherals can only be
plugge d in to e x pan sion un it s (n ot i n th e cent ral con troll er).
•• In one expansi on un it, you can use either on ly P peripherals or
onl y O peripherals.
Caution
If you use relative addresses of the O peripherals in an expansion
unit, yo u ca n no lo nger use th ese addresses for I/O modules in the
cen tral c ont rol le r (this wou l d re su lt i n do u ble ad dressing ).
3
Basic Operations
CPU 928B Programming G uide
C79000-B8576-C898-01 3 - 25
Timer and counter
operations
To load a timer using a start operation or a counter using a set
ope rat io n, you must first lo a d th e va lu e in A CC U 1.
The followin g load operations are preferable:
For timers: L KT, L IW, L QW, L FW, L DW, L SW.
For c oun ters: L KC, L IW, L QW, L FW, L DW, L SW.
Starting a timer with the selected timer val ue requires an RLO signal
change.
A counter is set or started with the selected counter value when a
positive-going RLO signal edge is detected.
The f ollowing table indicates the signal edge change with
co rrespondin g arrow s .
Operation Operand RLO
1) Function
SP
SE
SD
SS
SF
R
T 0 to 255
T 0 to 255
T 0 to 255
T 0 to 255
T 0 to 255
T 0 to 255
↑
↑
↑
↑
↓
1
Start a timer as a pulse
Start a timer as extended pulse
Start a timer as ON delay
Start a timer as stored ON delay
Start a tim e r as OFF delay
Res et a time r
S
R
CU
CD
C 0 to 255
C 0 to 255
C 0 to 255
C 0 to 255
↑
1
↑
↑
Set a counter (BCD nu mber from 0 to 999)
Res et a counter
C ount up
C ount down
1) positive-going edge ( ↑ ): signal change from ’0’ to ’1’
negative-going edge ( ↓ ): signal change from ’1’ to ’0’
When executing the timer or counter operations SP T, SE T, SD T,
SS T, SF T and S C the value in ACCU 1 is transf erred to the timer or
c ounter (as with the transfer operation) an d the appropriate operation
is started.
Table 3-6 Ti mer and counter operati ons
Basic Operations
CPU 928B Programming Guide
3 - 26 C79000-B8576-C898-01
Tim er value
With the operation L KT, you can load a t imer value directly into
ACCU 1 or indirectly from a flag or data word. The value must have
the foll owin g structure (with L KT, you speci fy the ti me base a fter the
perio d i n th e ope ran d as shown be lo w):
Example
Note
T he start o f each timer is liable to an inaccuracy of 1 ti me base!
When using timers, you should therefore select the smallest
possible ti me base (time base < timer value):
Example:
time value 4s n ot: 1 s x 4 inaccuracy : 1 s
but: 0.01 s x 400 inac curac y: 0.01 s
You wa nt t o set a ti me of 12 7 se c.:
Bit as si gnme nt :
Timer value 127
01
11
0
0
0
00
00
x
x
111
17
22
Irrelevant
Time base 1 sec
Bit no.
Timer value 0 ... 999 in BCD
012
3
4
5
6
7
8
9
10
11
12
15 14 13
2
10 10
0
10
1
These bits are irrelevant
(i.e. they are ignored when
the timer is started)
Time base specified in BCD: 0: 0.01 sec
1: 0.1 sec
2: 1 sec
3: 10 sec
3
Basic Operations
CPU 928B Programming G uide
C79000-B8576-C898-01 3 - 27
Counter value
With the operation L KC, you can load a counter v a lue directly in
ACCU 1 or indirectly fro m a flag or a data word. The value must have
the follo wing structure:
Example
In the t imer or counter itse l f, the value is in binary code. I f you want t o
scan the tim er or counter, y ou can load the actual timer or counter
value into ACCU 1 directly or in BCD code.
Counter value 127
01
11
0
0
00
00
x
xxx11
17
2
Irrelevant
Bit no.
Counter value 0 ... 999
specified in BCD
012
3
4
5
6
7
8
9
10
11
12
15 14 13
10
2
10
0
10
1
These bits are irrelevant,
(i.e. they are ignored when
the counter is set)
You wa nt t o spec ify a coun te r va lue of 127 :
Bit as si gnme nt :
Basic Operations
CPU 928B Programming Guide
3 - 28 C79000-B8576-C898-01
Further examples of timer
and counter values
Loadin g ti mer valu es directly:
"L T 10": Loads the binary timer value of timer T 10
directly into ACCU 1
The time base is not loaded.
Loading counter values di rect ly :
"L C 10" : Load s th e bina ry c ou nter val ue of coun te r C 10
direct ly i nt o AC CU 1
Counter value
Counter C 10
ACCU 1
90’0’
90
90
90
Timer value
Timer T 10
ACCU 1
’0’
3
Basic Operations
CPU 928B Programming G uide
C79000-B8576-C898-01 3 - 29
If you load values in BCD, status bits 14 and 15 of the timer or 12 to
15 of the counter are not loaded. They have the value 0 in ACCU 1.
The value in the ACCU can now be processed further.
Timer value
Timer T 10
ACCU 1
10
2
10
0
10
1
901213
1213 0
347811’0’
Time base Timer value
Time base
Binary BCD
Counter value
Counter C 10
ACCU 1
10
2
10
0
10
1
Counter value in BCD
Binary BCD
90
0
3
478
11
’0’
Loading timer values in BCD code:
"LC T 10" :Load s th e ti me r va lu e an d ti me bas e of
timer T 10 i nto ACCU 1 in BC D
The time base is also loaded.
Loading counter values in BCD code:
"LC C 10 ": Load s th e co un ter va lue of c ou nter C 1 0
into A CCU 1 in B CD
Basic Operations
CPU 928B Programming Guide
3 - 30 C79000-B8576-C898-01
Arithmetic operations
Operation Operand Function
+F
-F
xF
:F
+G
-G
xG
:G
– Add two fixed point numbers (16 bits)
Subt ra ct o n e fixed poin t number from ano ther (16 bits)
Multiply two fixed point numbers (16 bits)
Divi de one fixed point number by anoth er (16 bits):
quot ient in ACC U-1-L, re main der i n ACC U-1-H
Add two f loating point numbers (32 bits)
Subtract one flo ating point number from another (32 bits)
Multiply two floating point numbers (32 bits)
Divide one floating point nu mber by another (32 bits)
Arithmetic operations logically combine the contents of ACCU 1 and
ACCU 2 (e.g. ACCU 2 - ACCU 1). The result is then contained in
ACCU 1. An arithmetic operation changes the arithmetic registers as
follo ws (in fixed point operations only the low word):
Note
Within the supplem en tary operations, there are operations for
subtraction and addition of double word fixed point numbers.
In addition, you can use the ENT operati on fro m the set o f
supplementary operations for loading ACC U 3 and ACC U 4 (see
Sec tion 3. 5.3) .
T able 3-7 Arith m et ic o per ation s
ACCU 1 ACCU 2 ACCU 3 ACCU 4
before: < ACCU 1> <ACCU 2> <ACCU 3> < ACCU 4>
after: <result> <ACCU 3> <ACCU 4> <ACCU 4>
3
Basic Operations
CPU 928B Programming G uide
C79000-B8576-C898-01 3 - 31
Co mpar iso n op eratio ns
Operation Operand Function
! =
>< F
>D
> = G
<
<=
– C ompare for equal to
Compare for not eq u a l to
Comp ar e for greate r than
Compare for gr e ater than or equal to
C ompare for less than
C ompare for less than or equal to
...F: c om pare two fixe d poi nt nu mbers (16 bits)
...D: c ompare two fix e d poi nt nu mbers (32 bits)
...G: compare two fl oat in g point numbers (32 bits)
Block op eratio ns
Operation Operand Function
J U
J C
OB 1 to 39 1)
OB 110 to 255
PB 0 to 255
FB 0 to 255
SB 0 to 255
Jump unconditio nal ly
Jump conditionally (only when RLO = 1)
to a n o rgani za tion block
t o a s yste m program special functio n
to a program block
to an FB function block
to a s equ en ce block
D O U
D O C
FX 0 to 255
Jump unconditio nal ly
Jump conditionally (only when RLO = 1)
to an FX f unction block
B E
B E C
B E U
– Block en d
Block end, conditional (only when RL O = 1)
Block end, unconditional
C
C X D B 3 to 255
DX 3 to 255 Call a DB data block
Call a DX data block
G
GX D B 3 to 255
DX 3 to 255 Generat e data block DB
G enerate data block DX
(AC CU 1 must contain the number of data words
– max imu m 4091 – that t he new block is to ha ve )
1) onl y for te st p urpo se s!
T ab le 3-8 Com pa rison operatio n s
T able 3-9 B loc k oper at ion s
Basic Operations
CPU 928B Programming Guide
3 - 32 C79000-B8576-C898-01
G DB/GX DX
Generating a data block
T he operation G DBx generates a DB data blo ck with the nu mber x
(3 ≤ x ≤ 255) in the user memory of th e CPU. The con tent of the data
block is not assigned the value 0, i.e. the data words can have any
contents.
Before programmin g th is stat em en t, you mu st sto re th e nu m be r o f
data w o rds t ha t th e ne w DB is t o ha v e i n ACCU-1-L. Th e ope ratio n
"G DB" or "GX DX" creates the block header. A data block generated
in t h is w ay ( without block header) can occupy a maxi mum of 4091
words. Yo u ca n ge nerat e longe r d ata block s usi ng OB 125.
If the data block already exists, the length of the DB is not permitted
or th ere is n ot e no ug h space i n the DB -RAM, th e syste m pro gra m
calls O B 31. If t his is not loaded, th e CPU goes t o th e stop mo d e.
The GX DXx o perat ion generate s a DX data blo ck in t he DB-RAM
and is o th erwise the same as G DB x.
NO P /disp lay/ s top operatio ns
Operation Operand Function
N O P 0
N O P 1 – No opera ti o n
No ope ratio n
B L D 0 to 255 Display g ene rati o n ope ra tio n for t he PG :
the CPU handles the operation like a no operation
S T P – CPU ch ang es to s oft STOP.
Table 3-10 NOP/display/stop operat ions
3
Basic Operations
CPU 928B Programming G uide
C79000-B8576-C898-01 3 - 33
3.5.2
Pro g r am min g Exam p les in
the STL, LAD and CSF
Metho ds of Represent ation
Log ic operatio ns
I 1.7
I 1.3
I 1.1
Q 3.5
Logical/circuit diagram STEP 5 representation
Ladder Control system
AI 1.1
A
A
I 1.3
I 1.7
= Q3.5
I 1.1 I 1.3 I 1.7 Q 3.5
I 1.1 1.3 1.7
Q 3.5
&
Output Q 3.5 is "1" when all inputs are "1" simultaneously
I 1.1
I 1.3
I 1.7 Q 3.5
&
Statement
list
AND operation
diagram flowchart
Output Q 3.5 is "0" if any of the inputs has signal state "0"
The number of scans and the sequence of the logic
statements are optional
Program m ing Exam ples in the ST L, LAD and CSF Methods of Representation
CPU 928B Programming Guide
3 - 34 C79000-B8576-C898-01
Logic operations
(continued)
OI 1.2
O
O
I 1.7
I 1.5
= Q3.2
I 1.2
I 1.7
I 1.5
Q 3.2
state "0" simultaneously
Output Q 3.2 is "1" when at least one of the inputs is "1"
I 1.5I 1.7I 1.2
Q 3.2
I 1.2 1.7 1.5
Q 3.2
I 1.2
I 1.7
I 1.5 Q 3.2
1
1
Logical/circuit diagram STEP 5 representation
Ladder Control system
Statement
list
OR operation
diagram flowchart
Output Q 3.2 is "0" when all inputs have the signal state
The number of scans and sequence of programming is optional
I 1.5 I 1.6
I 1.4
Q 3.1
Q 3.1 is "1" when at least one AND condition is satisfied
I 1.1
I 1.7
Q 3.1
&
I 1.6
I 1.5
Q 3.1
I 1.3
I 1.4
I 1.5 I 1.6
Q 3.1
&
I 1.4 I 1.3
&
AI 1.5
A
A
I 1.6
I 1.3
= Q3.1
O
A I 1.4
I 1.3 I 1.1
I 1.7 &
1
1
Logical/circuit diagram STEP 5 representation
Ladder Control system
Statement
list
AND-before-OR operation
diagram flowchart
Q 3.1 is "0" when no AND condition is satisfied
3
Programming Exam ples in the STL, LAD and CSF M ethods of Representation
CPU 928B Programming G uide
C79000-B8576-C898-01 3 - 35
Logic operations
(continued)
I 6.0
I 6.3
I 6.2
Q 2.1
Output Q 2.1 is "1" when input I 6.0 or input I 6.1 and one
of the inputs I 6.2 or I 6.3 has signal state "1"
Output Q 2.1 is "0" when input I 6.0 has signal state "0"
and the AND condition is not satisfied
I 6.1
&
I 6.0 I 6.1 I 6.2 I 6.3
Q 2.1
I 6.0 I 6.2 I 6.3
I 6.1
Q 2.1
AI 6.0
O
OI 6.2
= Q2.1
AI 6.1
OI 6.3
)
I 6.0
I 6.1
I 6.2
I 6.3
Q 2.1
&
1
1
1
1
A (
Logical/circuit diagram STEP 5 representation
Ladder Control system
Statement
list
OR-before-AND operation /1st example
diagram flowchart
OR-before-AND operation
I 1.4 I 2..0
I 1.5
Q 3.0
Output Q 3.0 is "1" when both OR conditions are satisifed
I 1.4
I 1.5
Q 3.0
I 2.1 I 2.0
I 2.1
I 1.4 I 1.5
Q 3.0
I 2.0 I 2.1
&
I 2..0
I 1.4
Q3.0
I 2.1
I 1.5
OI 1.4
O
O
I 1.5
I 2.1
= Q3.0
)
O I 2.0
)
&
1
1 1
A (
1
A (
Logical/circuit diagram STEP 5 representation
Ladder diagram Control system
Statement
list
/2nd example
flowchart
Output Q 3.0 is "0" when at least one OR condition is not satisfied
Program m ing Exam ples in the ST L, LAD and CSF Methods of Representation
CPU 928B Programming Guide
3 - 36 C79000-B8576-C898-01
Logic operations
(continued)
Set/r eset operations
I 1.5 Q 3.0
I 1.5 I 1.6
Q 3.0
&I 1.6
I 1.5
Q 3.0
AI 1.5
AN I 1.6
= Q3.0
I 1.6 I 1.5
I 1.6 Q 3.0
&
Output Q 3.0 is "1" only when input I 1.5 has signal state "1"
state "0" (normally closed contact activated)
(normally open contact activated) and input I 1.6 has signal
Logical/circuit diagram STEP 5 representation
Ladder Control systemStatement
list
Scan for signal state "0"
diagram flowchart
I 1.4 I 2.7
I 2.7
Q 3.5
I 1.4
Q 3.5
I 2.7 Q3.5
I 1.4
S
RQ
A I 2.7
I 1.4
Q 3.5
S
R
Q 3.5
AI 2.7
I 1.4
Q3.5
R
S
Q R S
11
10
Signal state "1" at input I 2.7 sets the flip-flop
(signal state "1" at output Q 3.5).
If the signal state at input I 2.7 changes to "0", the
state of output Q 3.5 is retained (i.e. the signal is latched).
If the signal state at input I 1.4 changes to "0", the
state of Q 3.5 is retained.
Signal state "1" at input I 1.4 resets the flip-flop
(signal state "0" at output Q 3.5).
When the set signal (input I 2.7) and the reset signal
(input I 1.4) are applied at the same time, the scan
operation programmed last (in this case AI 1.4)
remains in effect for the rest of the program (reset priority).
Logical/circuit diagram STEP 5 representation
Ladder Control system
Statement
list
RS flip-flop for a latching signal output
diagram flowchart
3
Programming Exam ples in the STL, LAD and CSF M ethods of Representation
CPU 928B Programming G uide
C79000-B8576-C898-01 3 - 37
Set/reset operations
(continued)
I 1.3 I 2.6
I 2.6
F1.7
I 1.3
F 1.7
I 2.6 F 1.7
I 1.3
S
RQ
A I 2.6
I 1.3
F 1.7
S
R
F 1.7
A
I 2.6
I 1.3
F 1.7
S
RS
11
10
Signal state "1" at input I 2.6 sets the flip-flop.
If the signal state at input I 1.3 changes to "0", the
signal state of the flag is retained.
When the set signal (input I 2.6) and the reset signal
(input I 1.3) are applied at the same time, the scan
operation last programmed (in this case AI 1.3) remains
in effect for the rest of the program (reset priority).
Signal state "1" at input I 1.3 resets the flip-flop.
If the signal state at input I 2.6 changes to "0", the
signal state of the flag is retained, i.e. the signal is latched.
R Q
Logical/circuit diagram STEP 5 representation
Ladder Control system
Statement
list
RS flip-flop with flags
flowchartdiagram
Program m ing Exam ples in the ST L, LAD and CSF Methods of Representation
CPU 928B Programming Guide
3 - 38 C79000-B8576-C898-01
Set/reset operations
(continued)
On each leading edge of the signal at input I 1.7,
the AND condition (AI 1.7 and AN F 4.0) is satisfied;
the RLO is "1". This sets flags F 4.0 (edge flag) and
F 2.0 (pulse flag).
Flag F 2.0 is reset.
In the next processing cycle, the AND condition
AI 1.7 and AN F 4.0 is not satisfied, since flag F 4.0
has already been set.
Flag F 2.0 therefore only remains "1" for one program
run.
I 1.7
F 4.0
F 2.0
I 1.7
F2.0
F4.0
I 1.7
F2.0
A
AN
=
A
S
AN
R
I 1.7
F 4.0
F 2.0
F 2.0
F 4.0
I 1.7
F 4.0
Logical/circuit diagram STEP 5 representation
Ladder Control system
Statement
list
Simulation of a momentary contact relay (one shot)
diagram flowchart
I 1.7
F 2.0
I 1.7
F 4.0
F 2.0
F 4.0
S
RQ
&
F 2.0
I 1.7 F 4.0
S
RQ
F 4.0
F 2.0
I 1.7
I 1.0
I 1.0
A I 1.0
Q3.0
I 1.0
M1.0
M1.1
F 2.0
Q 3.0
A N F 1.0
= F 1.1
F 1.1A F 1.0S I 1.0AN F 1.0R
A F 1.1
A Q3.0
= F 2.0
A F 1.1
AN Q3.0
Q 3.0S
A N F 2.0
A F 2.0
R Q 3.0
The binary scaler (output Q 3.2) changes its state
to 1 (leading edge). Therefore, only half the input
frequency appears at the output of the memory cell.
each time input I 1.0 changes its signal state from 0
F1.1 Q3.0 F 2.0
S
RQ
F1.1
I1.0
F1.0
I1.0 F1.0 F1.1
S
RQ
F1.1 Q3.0 F2.0 Q3.0
F2.0
0
&
I1.0
F1.0
&F1.1
F1.1
I1.0 S
F1.0
RQ
F1.1
Q3.0
F2.0
F2.0
Q3.0
S
RQ
F1.1
Q3.0
&F2.0
Q 3.0
Logical/circuit diagram STEP 5 representation
Ladder Control system
Statement
list
Binary scaler (binary divider)
diagram flowchart
3
Programming Exam ples in the STL, LAD and CSF M ethods of Representation
CPU 928B Programming G uide
C79000-B8576-C898-01 3 - 39
Timer operations
Subsequent scans with an RLO of "1" do not affect the
If the RLO is "0", the timer is reset (cleared).
timer.
KT 10.2:
the time base:
0 = 0.1sec 2 = 1sec
The timer is loaded with the specified value (10).
The number to the right of the decimal point indicates
BI and DE are digital outputs of the timer. The time at
output BI is in binary code. The time at DE is in BCD code
with time base.
I 3.0
Q4.0
T
as the timer is running.
Q4.0
The timer is started during the first scan if the RLO is "1".
I 3.0
T 1
RS
10s
1
I 3.0
T 1
Q4.0
I 3.0
Q
10.2
T1
BI
Q4.0
QW0
DE QW2
I 3.0
Q
10.2
T1
1
TV BI
Q4.0
QW0
DE QW2
R
Logical/circuit diagram STEP 5 representation
Ladder Control system
Statement
list
Pulse timer
=
SP T 1
L KT 10.2
A I 3.0
AN I 3.0
RT1
LT1
TQW0
LC T 1
TQW2
AT1
= Q 4.0
1
TV
R
diagram flowchart
The scan AT or OT produces the signal "1" as long
3 = 10 sec1 = 0.1 sec
KT KT
I 3.0
Program m ing Exam ples in the ST L, LAD and CSF Methods of Representation
CPU 928B Programming Guide
3 - 40 C79000-B8576-C898-01
Tim er operati o n s (continued)
The timer is started during the first scan if the RLO is
"1".
A I 3.1
L IW 15
SE T 2
T 2A Q 4.1=
I 3.1
Q
IW15
T2
1
TW BI
Q4.1
DE
I 3.1
Q
IW15
T2
1
TW BI
Q4.1
DE
R
Q4.1
V
R
V
Q4.1
I 3.1
T 2
RS
1
T2
I 3.1
T 2
(IB 15) (IB 16)
An RLO of "0" does not affect the timer.
The scan AT or OT produces a signal "1" as long as
the timer is running.
IW 15:
Set the timer with the value of the operand I, Q, F or
D in BCD code (in this example, input word 15). I 3.1
Q4.1 TT
Timer value
Time
base
5 43 07 43 0
0
10101
102
Logical/circuit diagram STEP 5 representation
Ladder Control system
Statement
list
Extended pulse timer
=
diagram flowchart
3
Programming Exam ples in the STL, LAD and CSF M ethods of Representation
CPU 928B Programming G uide
C79000-B8576-C898-01 3 - 41
Tim er operati o n s (continued)
The timer is started during the first scan if the RLO
is "1". An RLO of "1" during subsequent scans does
Q
KT9.2
T3
TW BI
Q4.2
DE
I 3.5
Q
KT9.2
T3
TV
Q4.2
DE
R
Q4.2 R
I 3.5
T 3
RS
I 3.5
T 3
9s 0
Q4.2
BI
TO TO
When the RLO is "0", the timer is reset (cleared).
not affect the timer.
KT 9.2:
The timer is loaded with the specified value (9). The
number to the right of the decimal point indicates
0 = 0.1sec 2 = 10 sec
I 3.5
Q4.2 T
The scan AT or OT produces the signal "1" when the
timer has elapsed and the RLO is still applied to the
input.
Logical/circuit diagram STEP 5 representation
Ladder Control system
Statement
list
ON-delay timer
I
KT
T
I
T
T
Q
3.5
9.2
3
3.5
3
3
4.2
A
L
SD
AN
R
A
=
I 3.5
I 3.5 =
diagram flowchart
the time base:
3 = 10 sec1 = 0.1 sec
Program m ing Exam ples in the ST L, LAD and CSF Methods of Representation
CPU 928B Programming Guide
3 - 42 C79000-B8576-C898-01
Tim er operati o n s (continued)
TS
TV BI
DE
RQ
I 3.3
Q 4.3
I 3.2 I 3.3
Q 4.3 T4
Q 4.3
RS
20s 0
I 3.3
T4
I 3.2 I 3.2
TS
BI
DE
RQ
I 3.3
I 3.2
T4 T4
I 3.3
Q 4.3
TT
timer has elapsed. The signal state does not change
to "0" until the R T operation resets the timer.
The timer is started during the first scan if the RLO is "1".
An RLO of "0" does not affect the timer.
T4
= Q 4.3
AI 3.3
L KT 20.2
SS T4
A I 3.2
RT4
AT4
E
The scan AT or OT produces the signal "1" when the
Logical/circuit diagram STEP 5 representation
Ladder Control system
Statement
list
Stored ON-delay timer
20.2 TV
Q 4.3
=
20.2
diagram flowchart
I 3.4
Q 4.4
I 3.4
Q 4.4 T5
Q 4.4
RS
01 I 3.4
T5
OT
TV
BI
DE
RQ
OT
BI
DE
RQ
I 3.4
T5 T5
T5
AI
=Q
3.4
L KT 10.1
SF T5
AT5
4.3
I 3.4
Q 4.4
TTT
The scan AT or OT produces signal state "1" if
the timer is running
When the RLO is "1", the timer is reset (cleared).
When the RLO at the start input changes from "1" to
"0", the timer is started. It runs for the length of time
programmed.
Logical/circuit diagram STEP 5 representation
Ladder Control system
Statement
list
OFF-delay timer
10.1 TV 10.1
Q 4.4
=
diagram flowchart
or the RLO at the input is "1".
3
Programming Exam ples in the STL, LAD and CSF M ethods of Representation
CPU 928B Programming G uide
C79000-B8576-C898-01 3 - 43
Counter operations
When the result of logic operation changes at the start input
(I 4.1) from "0" to "1", the counter is loaded with the specified
is incorporated in the counter word.
BI and DE are digital outputs of the counter cell. The
value at BI is in binary code and the value at DE is in
BCD.
I 4.1
RS
CQ
CI
+
binary
16 bits
KC 150
KC 150
CD
BI
DE
RQ
C1
CU
S
CV
I 4.1
CD
BI
DE
RQ
C1
CU
S
CV
value (150).
Logical/circuit operation STEP 5 representation
Ladder Control system
Statement
list
Set counter
I 4.1
I 4.0
I 4.0
A
CU
A
L
S
I
C
I
KC
C
4.0
1
4.1
150
1
diagram flowchart
The flag necessary for edge evaluation of the set input
KC 150
I 4.2
RSCI
binary
16 bits
CU
BI
DE
RQ
C2
CD
S
CV
An RLO of "1" (I 4.2) resets the counter to zero.
Q 2.4
Q 2.4
CQ I 4.2
CU
BI
DE
RQ
C2
CD
S
CV Q 2.4
=0 /
An RLO of "0" does not affect the counter.
Logical/circuit diagram STEP 5 representation
Ladder Control system
Statement
list
Reset counter
A
CD
A
R
A
=
I
C
I
C
C
Q
4.0
2
4.2
2
2
2.4
I 4.2
I 4.0
I 4.0
=
diagram flowchart
Program m ing Exam ples in the ST L, LAD and CSF Methods of Representation
CPU 928B Programming Guide
3 - 44 C79000-B8576-C898-01
Counter operatio n s
(continued)
I 4.1
RS
CQ
CI
+
binary
16 bits
CD
BI
DE
RQ
C1
CU
S
CV
Owing to the two separate edge flags for CU and CD,
a counter with two different inputs can be used as an
up/down counter.
The value of the addressed counter is incremented
by "1" to a maximum value of 999. The function CU
is only executed on a positive edge (from "0" to "1")
of the logic operation programmed before CU. The
flags necessary for edge evaluation of the counter
inputs are incorporated in the counter word.
I 4.1
AI 4.1
CU C 1 CD
DU
DE
RQ
C1
CU
S
CV
I 4.1
Logical/circuit diagram STEP 5 representation
Ladder Control system
Statement
list
Count up
diagram flowchart
3
Programming Exam ples in the STL, LAD and CSF M ethods of Representation
CPU 928B Programming G uide
C79000-B8576-C898-01 3 - 45
Counter operatio n s
(continued)
I 4.0
RSCI
-
binary
16 bits
CU
BI
DE
RQ
C1
CD
S
CV
Owing to the two separate edge flags for CU and CD,
a counter with two different inputs can be used as an
up/down counter.
The value of the addressed counter is decremented
by 1 to a maximum counter value of 0. The function
is only executed on a positive edge (from "0" to "1")
of the logic operation programmed before the CD.
The flags necessary for edge evaluation of the
counter inputs are incorporated in the counter word.
I 4.0
AI 4.0
CD C 1 CU
BI
DE
RQ
C1
CD
S
CV
I 4.0
CQ
Logical/circuit diagram STEP 5 representation
Ladder Control system
Statement
list
Count down
diagram flowchart
Program m ing Exam ples in the ST L, LAD and CSF Methods of Representation
CPU 928B Programming Guide
3 - 46 C79000-B8576-C898-01
Co mpar iso n op eratio ns
V1
V2
! = F
QQ 3.0
LI B19
L IB20
! = F
= Q 3.0
IB19
IB20 Q 3.0
IB19
IB20
C1
C2
! = F
Q
not equal to ACCU-2-L.
in the list of operations.
ACCU-2-H and ACCU-1-H are not involved in the operation
for a 16-bit fixed point comparison.
In a 32-bit fixed point comparison (! = D) and floating point
comparison (! = G) the entire contents of ACCU 1 and
ACCU 2 (32 bits) are compared with each other.
During the comparison, the numerical representation of the
operands is taken into account, i.e. the contents of ACCU-1-L
The first operand is compared with the second operand
by the comparison operation. The RLO of the comparison
is binary.
Q 3.0
=
V1 V2
=
IB19 IB20
The condition codes CC1 and CC0 are set as described
RLO = "0": comparison is not satisfied, when ACCU-1-L is
Logical/circuit diagram STEP 5 representation
Ladder Control system
Statement
list
Compare for equal to
RLO = "1": comparison is satisfied if ACCU-1-L = ACCU-2-L
diagram flowchart
and ACCU-2-L are interpreted here as a fixed point number.
3
Programming Exam ples in the STL, LAD and CSF M ethods of Representation
CPU 928B Programming G uide
C79000-B8576-C898-01 3 - 47
Com parison operations
(continued)
Q 3.1
LI B21
L DW3
> < F
= Q 3.1
IB21
DW3
V1
V2
> < F
Q Q 3.1
IB21
DW3
V1
V2
> < F
Q
RLO = "0": comparison is not satisfied if ACCU-1-L
equals ACCU-2-L.
The condition codes CC1 and CC0 are set as described
at the beginning of Section 3.5.
ACCU-2-H and ACCU-1-H are not involved in the operation
for a 16-bit fixed point comparison.
This information also applies to comparison operations for
"greater than", "greater than or equal to", "less than" and
"less than or equal to" (see the operations list). During the
The first operand is compared with the second operand
by the comparison operation.
The RLO of the comparison is binary.
Q 3.1
V1 V2
IB21 DW3
=/
=/
ACCU-2-H and ACCU-1-H are involved in a 32-bit fixed
point comparison and floating point comparison.
RLO = "1": comparison is satisfied if ACCU-1-L is not
equal to ACCU-2-L.
Logical/circuit diagram STEP 5 representation
Ladder Control system
Statement
list
Compare for not equal to
diagram flowchart
comparison, the numerical representation of the operands
is taken into account, i.e. the contents of ACCU-1-L and
ACCU-2-L are interpreted here as a fixed point number.
Program m ing Exam ples in the ST L, LAD and CSF Methods of Representation
CPU 928B Programming Guide
3 - 48 C79000-B8576-C898-01
3.5.3
Supplementary Operations Yo u ca n us e t h e s upple me n ta ry opera ti on s set on the program me r
only in f unction blocks (FB and FX). This m eans that the total
operations set for f unction blocks consists of the basic operations and
the suppleme ntar y op er a tions .
T he syste m operations also bel ong t o the supplementa ry functions.
You ca n us e th e s yste m operati on s, for ex ample to ov erwrit e th e
memory at optional locations or to change the contents of the working
registers of the CPU.
If you inte nd to use system operatio ns, you shoul d be fa miliar with
Cha pter 9 "Memory access" .
Caution
Onl y experienced s yste m programmers should use the s yste m
oper a tions and then only with ca ution.
You can only write operations in function blocks in STL. You cannot
program function blocks in graphic form (LAD and CSF methods of
representation).
This section describes the suppl ementary operations and covers possible
combinations of substitution operations with actual operands.
System operat ions
System operations are mark ed in th e first column of the
tables with S
3
Supplementary O perations
CPU 928B Programming G uide
C79000-B8576-C898-01 3 - 49
Binary logic operations
Operation Operand Function
A=
AN =
O=
ON =
AN D op eration, scan a formal o p e r and for signal s tate ’1 ’
AN D op eration, scan a formal o p e r and for signal s tate ’0 ’
OR o pera ti on , scan a form a l ope ra nd for sig nal state ’1’
OR o pera ti on , scan a form a l ope ra nd for sig nal state ’0’
Insert formal operand
Inputs, outputs, data and flags addressed in binary (parameter
types: I, Q; data t ype BI) and ti mers and counters (parameter
type: T, C) are permitted as actual operands.
Di gital lo gic operati on s
Operation Operand Function
AW
OW
XOW
AND operat io n on th e co ntents of AC CU-1-L and ACCU-2-L
OR operation on the contents o f ACCU-1- L and ACCU-2- L
Exklusive OR operation on the contents o f ACCU-1-L and
ACCU-2-L
ACCUs 2, 3 and 4 are not a ffected, however, the condition codes
CC 1 an d CC 0 are affec ted (see wo rd c ondi ti on c o des).
T able 3-1 1 Binary logic ope rat ion s with form al operand s
T able 3-12 Digit al logic operations
Supplementary Op erations
CPU 928B Programming Guide
3 - 50 C79000-B8576-C898-01
Set/r eset operations
Operation Operand Function
S=
RB =
RD=
==
Set a formal operand (binar y)
Reset a formal operand (binary )
Reset a formal operand (digital)
for timers a nd co unters
A s sign the value of the RLO to a
formal operand
Insert for mal operand
Inputs , outp uts a nd F flags addr essed in binary
(parameter ty pe: I, Q; da ta t ype B I) are perm it te d
as actual operands.
Table 3-13 Set/reset operations with formal operands
3
Supplementary O perations
CPU 928B Programming G uide
C79000-B8576-C898-01 3 - 51
Timer and counter
operations
Operation Operand Function
SP =
SD =
SEC =
SSU =
SFD =
FR =
Start ti mer specified by the formal ope rand as a pul se with the
va lu e stored i n A C CU-1-L (parameter type T).
Start timer specified by the formal operand as ON del a y with th e
value stored in ACCU-1-L (para meter type T).
Start timer specified by the formal operand as extended pulse
with the value stored in ACCU-1-L or set counter specified
as formal operand with the counter value stored in ACCU-1-L
(parame ter type: T, C) .
Start timer specified by the formal operand as stored
ON delay with the value stored in ACCU-1-L or
increment a counter specified as formal operand
(parame ter type: T, C) .
Start timer specified by the formal operand as stored
OFF del a y with the value store d in ACCU-1-L or
decrement a counter specified as formal operand
(para meter type: D, C).
Enable formal operand (timer/counter) for cold
re start (see FR T o r F R R ); (para me ter type: T, C).
Insert formal operand
FR T 0 to 255
C 0 to 255
Enable timer for cold restart:
The operatio n is only executed on the leading edge
of the RLO (change f rom 0 to 1). The timer is
re sta rted if t he RLO is 1 at th e ti me of th e st art
operati on. (See timi ng d i agram below th e ta ble).
Enable a counter for setting or resetti ng:
The operatio n is executed only on the le ad ing edge
of the RLO (change f rom 0 to 1). The counter is only
started if the RLO = 1 at the ti me of the start operati on.
Table 3-14 T imer and counter operations with formal operands
tt
R
LO
f
or SP T
R
LO
f
or FR T
S
can
w
ith A T
Supplementary Op erations
CPU 928B Programming Guide
3 - 52 C79000-B8576-C898-01
Examples
F unction block call Pr ogram in the
function bloc k Program executed
a)
:JU FB 20 3
NAME :EXAMPLE1
ANNA : I 10. 3
BERT : T 17
JOHN : Q 18. 4
:A =ANNA
:L KT 010.2
:SSU =BERT
:U =BERT
:= =JOHN
:A I 10.3
:L KT 010.2
:SS T 17
:U T 17
:= Q 18.4
b)
:JU FB 20 4
NAME :EXAMPLE2
MAXI : I 10. 5
IRMA : I 10. 6
EVA : I 10.7
DORA : C 15
EMMA : F 58. 3
:A =MAXI
:SSU =DORA
:A =IRMA
:SFD =DORA
:A =EVA
:L KC 100
:SEC =DORA
:AN =DORA
:= =EMMA
:A I 10.5
:CU C 15
:A I 10.6
:CD C 15
:A I 10.7
:L KC 100
:S C 15
:AN C 15
:= F 58.3
c)
:JU FB 20 5
NAME :EXAMPLE3
BILL : I 10. 4
JACK : T 18
EGON : IW 20
YOGI : F 100 .7
:A =BILL
:L =EGON
:SEC =JACK
:A =JACK
:= =YOGI
:A I 10.4
:L IW 20
:SE T 18
:A T 18
:= F 100.7
3
Supplementary O perations
CPU 928B Programming G uide
C79000-B8576-C898-01 3 - 53
Load and transfer
operations
Operation Operand Function
L=
LCD =
LW =
LWD =
T=
Load a formal operand:
The value of the operand specified as a formal
operand is lo aded into the ACCU (parameter
type: I , T, C, Q; da ta t ype : B Y, W, D).
Load a formal operand in BCD code:
The v al u e of t he t imer o r cou nte r spec ifie d as a form a l ope ran d is
loaded into the ACCU in BCD code (parameter type: T, C).
Load the bit patter n of a formal ope rand:
The bit pattern of a formal operand is loaded into the ACCU
(parameter ty pe : D; da ta type: KF, KH, KM, KY, KS, KT, KC).
Load the bit patter n of a formal ope rand:
The bit pattern of a formal operand is loaded into the ACCU
(parameter type: D; data type: KG).
Trans fer to a formal operand:
The contents of the accumulator are transf erred to
the operand specifie d as a formal operand (parameter
type: I, Q; data type: BY, W , D).
Insert for mal operand
Actua l operands permitted include those of the correspond ing basic
oper ati ons e xcept for S flags. For the "LW= " operation, permissible
data types include a binary pattern (KM) or a hexadecim al pattern
(KH), tw o a bso lute nu mbers of 1 byte e ac h (KY), a c haracte r (K S), a
fixed poi nt nu mber (KF), a timer valu e ( KT) and a counter value
( KC). For "LWD=" permissible data is a floatin g point number.
Table 3-15 Load and transfer operati ons with formal operands
Supplementary Op erations
CPU 928B Programming Guide
3 - 54 C79000-B8576-C898-01
Operation Operand Function
L RI 0 to 255
RJ 0 to 255
Load a word f rom the interf ace data area
into ACCU 1 (RI area)
Load a word fro m the extended interface area
into ACCU 1 (RJ area)
L RS 0 to 255
RT 0 to 255
L oad a word from the system d at a area
into ACCU 1 (RS area)
Load a word fro m the extended system data
area into ACCU 1 (RT area)
T RI 0 to 255
RJ 0 to 255
Tran sfer the content s of ACCU 1 to a
word in the interf ace data area (RI area)
Transfer the contents o f ACCU 1 to a word
in the extended interface data area (RJ area)
T R S 60 to 63
RT 0 to 255
Tran sfer the content s of ACCU 1 to a
word in t he syst em data area (RS area)
Transf er the contents of ACCU 1 to a word
in the extended system data area (RT area)
In contrast to the RI, RJ and RT areas, you can only use words RS 60 to
RS 63 o f the RS area. Refer to Section 8.3.4 "RS/RT Area".
You can use the RT area in its complete length (RT 0 to RT 255)
provid ing you do no t use an y stan dard fun ction bl oc ks.
Ta ble 3- 16 Load and transfer o per ations wi th special op erands
3
Supplementary O perations
CPU 928B Programming G uide
C79000-B8576-C898-01 3 - 55
Arithmetic operations
Operation Operand Function
ENT – This causes a stack li ft into ACCUs 3 and 4:
< ACCU 4> := <ACCU 3>
< ACCU 3> := <ACCU 2>
< ACCU 2> := <ACCU 2>
< ACCU 1> := <ACCU 1>
ACCUs 1 and 2 are not changed. The old contents
of ACC U 4 are lost .
Example
The following fraction must be calculated: (30 + 3 * 4) / 6 = 7
Table 3-17 Arithmetic operation ENT
ACCU 1 ACCU 2 ACCU 3 ACCU 4
LKF+30 d30 ca
LKF+3 d3c30
a
Contents of the ACCUs
before the sequence of
arithmetic operations bcd
xF c12 c30
+F c42 c
c
LKF+4 c4303
ENT 3 30 30 c
c7cc
LKF+6 c
6c
42
:F
Supplementary Op erations
CPU 928B Programming Guide
3 - 56 C79000-B8576-C898-01
Operation Operand Function
SADD BN -128 to
+127 Add a byte constant (fixed point) to ACCU-1- L (includes
sign change)/the condition code in CC 0, CC 1, OV and
OS are not af fected! – ACCU-1-H and ACCUs 2 to 4
r ema in unchanged.
SADD KF -32 768 to
+32 767 Add a fixed point constant (word) to ACCU-1-L/ th e
condition codes in CC 0, CC 1, OV and OS are not
a ffected! – ACCU-1-H and ACCUs 2 to 4 remain unchanged.
SADD 1) DH 0000 0000
to
FFFF FFFF
Add a double word fixed point constant to ACCU 1/the
condition codes in CC 0, CC 1, OV and OS are not af fected! –
ACCUs 2 to 4 remain unchanged.
S+D 1) Add two double word fixed point constants
(ACCU 2 + ACCU 1)/ the result can be evaluated
in CC 0/CC 1. 2)
S-D 1) S ubtract two double word f ixed point cons tants
(ACCU 2 - ACCU 1)/the result can be evaluated in CC 0/CC 1. 2)
STAK Sw ap th e content s o f A CCU 1 and A CCU 2
1) Programming is dependent on the PG type and the release of the PG system software.
2) For c h ang e s in ACCU 2 an d ACCU 3: see S e ctio n 3.5. 1 "Bas ic Ope ratio n s/A rith m etic Operation s".
Table 3-18 Supplementary arithmetic op erations
3
Supplementary O perations
CPU 928B Programming G uide
C79000-B8576-C898-01 3 - 57
3.5.4
Executive Operations The executive operatio ns also include system operations.
Caution
Syste m operati on s shou l d onl y be use d wit h ca re a nd t hen o nly by
ex perience d pro g ramm ers fami li ar w i th t h e s ys tem.
System operations are in d icat ed i n th e tabl e by
Jum p operatio ns
When you use th e su ppl ementa ry jump o pera ti ons, you i n dica te t he
jump des tina tion for unconditional jump s s ymbolica lly. Th e sy mbo lic
parameter of the ju mp operation is identical to the symbolic address of
the destination statement. W hen program ming, remember that the
abso l ut e ju mp d i stance sho ul d not e xc ee d ± 127 wo rds and a ST EP 5
statem ent can consist of m ore than one word. You can only execute
the se ju mps wit hin a block; ju mps ove r segm en t boundaries a re n ot
permitted ("segment" = structural element in PBs, SBs, FBs, FXs and
OBs; see STEP 5 manual).
Note
The jump statement and jump destination (symbolic address)
m ust be in the same segment. A symbo lic address can on ly b e
used once per se gment.
Except ion: this does not apply to the JUR ju mp for which you
specify an absolute j u mp distance as the para meter.
Operation Operand Function
JU =
JC =
JZ =
addr
( addr =symbolic
a ddress with
maximum
4 characters)
Jump un conditio nally:
The jum p is executed regardless of conditions
Ju m p condi tiona lly:
the conditional jump is exe cut ed only if the RL O is 1.
If the RLO is 0, the statement is not executed and the RLO
is set to 1.
Jump if resu lt is ’0’ :
the jump is executed only if CC 1 is 0 and CC 0 is 0.
The R LO is not ch ang ed.
S
Ta ble 3- 19 Jump op era tions
Executive Operations
CPU 928B Programming Guide
3 - 58 C79000-B8576-C898-01
Operation Operand Function
Tabl e 3-19 c o ntin ued :
JN =
JP =
JM =
JO =
JOS =
addr
(addr = symbolic
a ddress with
maximum
4 characters)
Jump if resul t is not 0 :
the ju mp is ex ecu ted only i f CC1
is not equ al to CC0.
The R LO is no t ch anged.
Jump if result > ’0’ :
the ju mp is only execut ed i f C C 1 = 1
and CC 0 = O. The RLO i s no t ch ang ed .
Jump if result < ’0’:
the ju mp is only execut ed i f C C 1 = 0 a nd CC 0 = 1 .
The R LO is no t ch anged.
Jump on overflow:
the ju mp is ex ecu ted when the OV co ndition code is 1 . If
ther e is n o over fl ow (OV is 0 ), th e ju mp is not executed. The
RLO is no t ch an ged .
An ove rflow occurs w he n an arithmetic oper ation exce eds
the p ermiss ib le r ang e f or a gi ven nu mer ical re pres en tation.
Jump wh en the OS (st ored o ve rflow) condi tio n co de is set:
the ju mp is ex ecu ted when the con di tio n co de OS is 1 . If
ther e is n o over fl ow (OS is 0 ), th e ju mp is not executed . The
RLO is no t ch an ged .
An ove rflow occurs w he n an arithmetic oper ation exce eds
the p ermiss ib le r ang e f or a gi ven nu mer ical re pres en tation.
SJUR -32 768 to
+32 767 Relative jump within the user mem or y o r with in a fu nc tion
bloc k (e.g. t o ar ri ve i n a d if ferent seg men t). T he o pe rat ion is
alwa ys ex ecu ted regardl ess of co nd itio ns.
The o perand is t he num ber of w ords differ enc e be tween the
addres s o f th e ju mp destina tio n - the cur rent destinat ion . Th e
jump is ex ecu ted either to a hig he r (po sitive oper an d) or
lower (ne gat ive opera nd) addres s than the curre nt operat ion.
Caution
If you use JUR i nc orr ect ly , undefined stat uses can occur in the
syst em. It sh ou l d on l y be used by e x tremel y experienced
program mers with detailed knowledge of the sy stem.
3
Ex ecutive O perations
CPU 928B Programming G uide
C79000-B8576-C898-01 3 - 59
Shift operations
Operation Operand Function (ope ration with ACCU 1)
SLW
SRW
SLD
SSW
SSD
RLD
RRD
0 to 15
0 to 15
0 to 32
0 to 15
0 to 32
0 to 32
0 to 32
Sh ift a word to th e left (vac ant po sitio ns
to the right are padded with zeros)
Sh ift a word to th e rig ht (v acan t po siti o n
to the left are padded with zeros)
Shift a do uble w ord t o the left (vacan t positio ns
to the right are padded with zeros)
Shif t a word with sign to the right (vacant positions
to the left are padded with the sign - bit 15)
Shif t a double word with sign to the right (vacant
positions to the left are padded wi th t he sign - bit 31)
Ro tat e to the left
Rotate to th e right
On l y ACCU 1 is involved in the execution of shift operations. The
parameter part of these operations specifies the nu mber of positions by
which the accu mulator contents should be sh i fted or rotated. For the
SLW, SRW and SSW operations, only the low word of ACCU 1 is
involved in the shi ft operations. For SLD, SSD, R LD and RRD
operations, the entire contents of ACCU 1 (32 bits) are involved.
Sh i ft operations are executed regardle ss o f conditions.
You can use jump operati ons to sca n the value of the last bits shifted
out using CC 1/CC 0.
S h ift: las t
bit shifted CC 1 CC 0 Jump operation
000JZ=
110JN=
JP=
T ab le 3-2 0 S hift operations
Executive Operations
CPU 928B Programming Guide
3 - 60 C79000-B8576-C898-01
Examples
1. You want to shift the contents of data word DW 52 four bits to the
left and
write them to data word DW 53.
STEP 5 program: Contents of the data words:
:L DW 52 K H = 14 AF
:SLW 4
:T DW 53 K H = 4A F0
2. You w ant to r ead the inpu t double word ID 0, and shif t th e conten ts of
ACCU 1 so that th e bi t positi ons of t he i nput dou ble word sho wn in bo ld
face are retained and the rem aining b it p ositions are set to defined
value s (0 H or 0FH ).
STEP 5 pr og ram: C on tent s of A CCU 1 (h ex adec imal )
ACCU-1-H: ACCU-1-L:
:L ID 0 2 348 ABCD
:SLW 4 2348 BCD0
:SRW 4 2348 0BCD
:SLD 4 3480 BCD0
:SSW 4 3480 FBCD
:SSD 4 0348 0FBC
:RLD 4 3480 FBC0
:RRD 4 0348 0FBC
3. App lica tion : Mult ipli ca tion by th e 3r d powe r, e .g . ne w va lu e = old
value x 8
:L FW 1 0
:SLW 3
:T FW 10 Caution: do not exceed the
po siti ve a re a li mi t!
4. App lica tion : Divi sion b y th e 2n d powe r, e.g . ne w valu e = ol d va lue : 4
:C DB 5
:L DW 0
3
Ex ecutive O perations
CPU 928B Programming G uide
C79000-B8576-C898-01 3 - 61
Co nver sio n operatio ns
Operation Function
CFW
CSW
CSD
DEF
DUF
DED
DUD
FDG
GFD
Fo r m the 1’s complement of AC CU-1- L (16 bits)
Fo r m the 2’s complement of AC CU-1- L (16 bits)
Form the 2’s comple me nt of AC CU 1 (32 bits)
Co n vert a fi xed poi n t nu mbe r (16 bit s) from B CD to bi na ry
C onvert a fix ed point number (16 bits) from binary to BCD
Con v ert a do uble w ord (32 bi ts) fro m BC D t o bin ary
Con v ert a do u bl e w ord (32 bits) fro m bi n ary to BC D
Co nv ert a fi xed poi nt n umbe r (32 bit s) to a floa ting point n umber (32 bits)
Co n vert a floa tin g poi nt nu mber t o a fixed po int nu m ber (32 bi ts)
DEF
T he value in AC CU-1-L (bits 0 to 15) is interpreted as a BCD
nu mber. After the conversion, ACCU-1-L contains a 16-bit fixed
p oint num ber .
DUF
The value in ACCU-1-L (bits 0 to 15) is interpreted as a 16-bit fixed
point nu mber. After the conversion, ACCU-1-L contains a BCD n u mber.
15 14 0
S2
14 . . . . . . . . . . . . . . . 2 0
DUF ↓DEF ↑
15 0
S S S S 10 2 10 110 0
S (sig n): 0 = positiv e
1 = negative
T able 3 -2 1 Conv ersion oper ations
Executive Operations
CPU 928B Programming Guide
3 - 62 C79000-B8576-C898-01
DED
The value in ACCU 1 (bits 0 to 31) is interpreted as a BCD number.
A fter the conversion, ACCU 1 contains a 32-bit fixed point number.
DUD
T he value in AC CU 1 (bits 0 to 31) is interprete d as a 32-bit fixed
point number. After the conversion, ACCU 1 contains a B CD number.
31 30 0
S2
30 . . . . . . . . . 2 0
DUD ↓DED ↑
31 0
S S S S 10 610 5 10 410 3 10 2 10 110 0
S (sign): 0 = positive
1 = negative
FDG
T he value in AC CU 1 (bits 0 to 31) is interprete d as a 32-bit fixed
point number. After t he conv ersion, ACCU 1 contains a floating point
number (exponent and mantissa).
GFD
The value in ACCU 1 (bits 0 to 31) is interpreted as a floating point
nu mber. After the conversion, ACCU 1 contains a 32-bit fixed point
number.
31 30 0
S2
30 . . . . . . . . . 2 0
FDG ↓GFD ↑
31 30 ... ... 24 23 0
S2
6
. . . . . . . . . . . . . . 2 0S2
-1 . . . . . . . . . . 2 -23
Exponent Mantissa
The conversion is made by multiplying the (binary) mantissa by the value
of the (binary) exponent by sh i fting the mantissa value to more
significant bits past an imaginary decimal point by the value of the
exponent (ba se 2). After the multiplication, remnants o f the original
mantissa re main to the right o f the i maginary deci mal point. These bit
places are cut off from the whole result.
3
Ex ecutive O perations
CPU 928B Programming G uide
C79000-B8576-C898-01 3 - 63
Thi s c onv ersio n al go rit h m pro duc es th e follo win g resul t classes:
•• Fl oatin g point nu mbers ≥ 0 or ≤ -1 re sult in th e n e xt low e r
number.
•• Fl oating poi nt numbers < 0 and > -1 result in the value ’0’.
Conversion exam ples
Examples of C FW, CS W
Flo at ing po in t numb er 32- bit fi xed po in t numb er
GFD
+5,7 → 5
-2,3 → -3
-0,6 → 0
+0,9 → 0
1. You want th e co nten ts of da ta wor d DW 6 4
inver ted bi t fo r bi t (rev er sed) and s tore d in
data word DW 78.
STEP 5 program: Assignment of the data words:
:L DW 6 4 KM = 00 1111 1001 01 1011
:CFW
:T DW 7 8 KM = 11 0000 0110 10 0100
2. The contents of data word DW 207 are
interpreted
as a fixe d poin t nu mb er a nd sto red in dat a
wor d 51 w ith a re vers ed sig n.
STEP 5 program: Assignment of the data words:
:L DW 2 07 KF = +51
:CSW
:T DW 51 KF = -51
Executive Operations
CPU 928B Programming Guide
3 - 64 C79000-B8576-C898-01
Decrement/
increment
Operation Operand Function
D
I
1 to 255
1 to 255
Decrement the low byte (bits 0 to 7) of ACCU-1-L
by t he valu e of the oper and 1)
Increment the low b yte (bits 0 to 7) of ACCU-1-L
by t he valu e of the oper and 1)
1) T he cont en ts of the low byte of ACCU-1 -L a r e decr em e nted or increm e nted by the number sp ec if ied as the
operand with out a carry . Th e op eration is e xe cute d re gard les s of c on di tio ns .
Example
Pro cessin g op eratio ns
Operation Operand Function
DO
DO =
D W 0 to 255
FW 0 to 254
P rocess data word:
the f ollowing operation is combined with
the parameter specified i n the address data
word and executed.
Process flag word:
the f ollowing operation is combined with
the parameter specified i n the addressed
F flag and execute d.
Process formal operand (parameter type B):
Only C DB, JU PB, JU OB, JU FB, JU SB
can be substituted.
Insert for mal operand
STEP 5 pr og ram: Assi gn ment of th e da ta w or ds:
:L DW 7 KH = 1010
:I 16
:T DW 8 KH = 1020
:D 33
:T DW 9 KH = 10FF
Tab le 3-2 2 Decrem ent/in crement ope ration
T ab le 3-2 3 P roce ssi ng operatio ns
3
Ex ecutive O perations
CPU 928B Programming G uide
C79000-B8576-C898-01 3 - 65
Operation Operand Function
Tabl e 3-23 c o ntin ued :
SBI 1) Indirect processing of a for mal oper and:
execute an operation whose operation code is
stored in a formal operand. The n u mber o f the
formal operan d must be stored in ACCU 1.
B RS 60 to 63 1) Ex ec ute an operati on who se operatio n cod e
is stored in the sy s tem da ta area (RS = fr e e
syste m data: RS 60 to 63). In 2-word operati ons
the 2nd word m ust be loaded in RS n + 1.
1) The value in the formal operand or system data is interpreted as the operation code o f a STEP 5
operation and is then executed.
Note
Onl y the follo wing o pera ti on s can be combined wi th DO DW, or
DO FW , DI or D O RS:
- A.. , A N.. , O.. , ON.. , S.. , R .. , = ..
with areas I, Q, F, S,
- FR T, R T, S F T, SD T, SP T, SS T, SE T,
- FR C, R C, S C, CD C, CU C,
- L. ., T .. w it h area s P, O, I, Q, F , S, D, RI , RJ , R S, R T ,
- L T, L C,
- L C T, LC C,
- JU=, JC=, JZ=, JN=, JP=, JM=, JO=,
- SLW, SRW,
- D, I , SED, SEE ,
- C DB, JU.. , JC.., G DB, GX DX, CX DX, DOC FX, DOU FX.
The PG does not check the legali ty of the combinations!
Executive Operations
CPU 928B Programming Guide
3 - 66 C79000-B8576-C898-01
Exam p les of DO o per ation s
DO DW/DO FW
Operand substi tution
Using the statements "DO DW" and "DO F W" you can access data with
a substitution, e.g. in a program loop. The substituted access consists of
the statement DO DW/DO FW follo wed im mediately by one of the
STEP 5 operations listed above.
"Substituted" means that the operand for the operation is not progra mmed
as a static value but is fixed during the course of the STEP 5 program.
Select the operand type fro m the range permitted for the ope ration when
you write your program, e.g. PB for the operation "JU PB nn ":
You must first load the ope rand value (nn in the example) in a data word
or F flag word (parameter word) before the substituted access with
DO DW/DO FW.
1.Principle of substitution:
:L KF +120
:T FW 14 load FW with the value "KF +120"
:DO FW 14
:L IB 0
before the operation "L IB" is executed,
the op eran d valu e ’0 ’ is r ep lace d by t he v alue
’120’;
Oper at ion ex ec uted : L IB 120
2. Data word as index register:
The contents of data words DW 20 to DW 100 are set to signal state ’0’.
The index register for the parameter of the data words is DW 1.
:L KF +20 supply the index register
:T DW 1
M001 : L KF +0 rese t
:DO DW 1
:T DW 0
:L DW 1 incr em ent th e in dex re gist er
:L KF +1
:+F
:T DW 1
:L KF +100
:<=F
:JC =M0 01 jump i f th e inde x is w ithi n the rang e
... remaining STEP 5 program
Continued on next page
3
Ex ecutive O perations
CPU 928B Programming G uide
C79000-B8576-C898-01 3 - 67
Operand substituti on wit h binary operatio ns
For operand substit utions with binar y operati ons you can use the
followin g operan d types: inputs, ou tputs, F flags, S fla gs, timers and
counters.
In th is su bstitu t ion , t he st ruc tu re of t h e F flag word o r da ta wo rd
(pa ramet er w o rd) d epe n ds o n th e opera tio n you are u si ng .
Parameter word for inputs and outputs
Bit no. 1 5 1 1 1 0 8 7 6 0
no significanc e Bit addr ess
from 0 to 7 0 Byte address from 0 to 127
Examples of operand substitution continued:
3. Jump distributor for subroutine techniques:
:DO FW 5
:JU =M001 Cont en ts o f flag wor d FW 5 :
+ :JU =M002
Jump :JU =M003 jum p dist ance
distance :JU =M004 (maximum ± 127)
:JU =M005
: .
: .
M001 : .
: .
:BEU
M002 : . Advantage:
: . all pr ogra m sect ions a re
:BE U cont aine d in one block.
M003 : .
: .
:BEU
4. Jump distributor for block calls:
:DO FW 10 Contents of flag word FW 10:
:JU PB 0 PB 0
PB 1 Bl oc k no . x
PB 2
PB 3
.
.
PB x
Executive Operations
CPU 928B Programming Guide
3 - 68 C79000-B8576-C898-01
Para me ter wo rd for F flags
Bit no. 1 5 1 1 1 0 8 7 0
no significanc e Bit addr ess
from 0 to 7 Byte address from 0 to 255
Parameter word for S flags
Bit no. 1 5 14 12 1 1 0
0 Bit addr e ss
from 0 to 7 Byte address f rom 0 to 1023
Parameter word for timers and counters
Bit no. 1 5 8 7 0
no significanc e Num ber of timer or
c ounter c ell from 0 t o 255
Principle of the substitution
wi th a binary operatio n
15 8 7 011 10
0DW 2
7
DO DW
AI0.0
27
30
4
AI4
.
30
statement executed
3
Ex ecutive O perations
CPU 928B Programming G uide
C79000-B8576-C898-01 3 - 69
Exa mple of DI operat io n
In fu ncti on blo ck F B 1, S TE P 5 oper at ions are e xecu ted wh ose op erat ion
codes wer e tran sfer re d
by a call in g bl ock as for ma l op eran ds FW 10, FW 12 and FW 14.
Which of the operation codes is executed is written by the calling
block as a cons ecut iv e nu mb er i n fl ag wor d FW 16.
The res ult of the exe cu ted op erat io n is the n en tere d in ACC U 1 an d is
transferred to flag word FW 18.
FB 1
NAME :TEST
DECL :FW1 0 I/Q/D/ B/T/ C: D KM/K H/ KY/K S/ KF/K T/KC /K G: KH
DECL :FW1 2 I/Q/D/ B/T/ C: D KM/K H/ KY/K S/ KF/K T/KC /K G: KH
DECL :FW1 4 I/Q/D/ B/T/ C: D KM/K H/ KY/K S/ KF/K T/KC /K G: KH
:L FW 16 cons. number of formal operand
: with required operation code
:D I transferred operation code is executed
:T FW 16 result from ACCU 1
:BE
FB 2
:
:L KF +1
:T FW 16 cons. no. of formal operand with operation code
:JU =AUFR
:
:
AUFR :
:JU FB 1 cal l FB TES T
NAME :TEST
FW10 : KH 4A5A op. code "L IB 90", formal operand 1
FW12 : KH xxxx other operation code, formal operand 2
FW14 : KH yyyy other operation code, formal operand 3
:T FW 18 ACCU 1 → FW 18
:BE
FW 10 4A5AH
:L IB 90
0001H
0001H
List of actual operands in FB 2 Principle of sequence in FB 1
xxxxH
yyyyH
Operationexecutedwith"DI"
(cons. no. of actual operand)
FW 12
FW 14 FW 16
ACCU 1
:L FW 16
:DI
Executive Operations
CPU 928B Programming Guide
3 - 70 C79000-B8576-C898-01
Disabling/enabling
process interrupts
Function
IA
RA
Disable external process interrupt servicing
Enable external process interrupt servicing
You can use operations "disable/enable process interrupts", for exa mple
to suppress external process interrupts when you are using time-driven
processing. External process interrupt -driven processing is then no longer
possible in the program section between the IA and RA operations.
See also the special function OB 120 "disable interrupts" , Section 6.5.
3.5.5
Semaphore Operations If two or more CPUs in one programmable controller (see Chapter 10)
requ ire ac ce ss t o the sa me g lobal memo ry area (periphe ra ls , CPs, IPs ),
there is a danger that one CPU will overwrite the data of another CPU
or that one CPU could read invalid interm ediate data statuses of
ano the r CPU an d mi si nt erpret th e m. You mu st therefore coo rdi nate
CPU accesses to the common memor y areas.
You can coordinate the individual CPUs using the SED and SEE
operations.
You can, for ex ample, progra m the following coordination be tween tw o
CPUs: a CPU involved in multiprocessing can only access the common
memory area a fter it has success fully set a declared se maphore (SES). A
se maphore xx can only be set by a single CPU. I f a CPU fails to set (i.e.
disable) the se maphore, it cannot access the memory area. In the same
w ay, a CPU can no longer access the memory once it has released t he
se maphore again (SEE).
T able 3-2 4 Dis abling/e nablin g pro cess in ter rupts
3
Semaphore Operations
CPU 928B Programming G uide
C79000-B8576-C898-01 3 - 71
SED/ SEE disable/enable
sem ap ho re
(non-system o perations)
Operation Operand Function
SED
SEE
0 to 31
0 to 31
Disable (set) a semaphore
E nable (release) a semaphore
e valuati on of the result of the operation via
CC 0/CC 1
Note
Th e SED x x a nd SEE xx o pera ti ons must be pro gra mm ed in all
CPUs that requ ire synch ron ize d ac cess to a common global
memory area.
Stan dard FBs, handlin g blo cks an d blocks for multiprocessor
communication manage the coordination internally. If you use
t hese blocks, you do n ot need to program the operati ons SEE x x
a nd SED xx.
Effect of SED/SEE
The CPU that execu tes the operation SED xx (disable semaphore)
accesses a specific byte in the coordinator (provided that no other
CPU has ac ce ss to tha t byte alread y). Onc e a C PU ha s reserved
acce ss, th e o ther CPUs ca n no l ong er acce ss th e memory a rea
protected by the semaphore (numbers 0 to 31). The area is therefore
disa bled for all o th er C PUs.
Make sure that the coordination f unctions correctly, all CPUs
requ iring a cc ess to t h e sam e a rea of glo ba l memo ry mu st u se the sam e
semaphore.
The SEE xx (enable sem aphore) operation resets the byte on the
coo rdin at or. Th e pro te ct ed memory a rea is th e n on c e ag ai n acce ssible
to the other CPUs. A se maphore can only be enabled b y the CPU that
disable d it .
T able 3-2 5 Dis able/ enab le s emapho re
Semaphore Operations
CPU 928B Programming Guide
3 - 72 C79000-B8576-C898-01
Use of SED/SEE
Fig. 3-8 illustrates the basic sequence of coordi nated access using a
se ma phore.
Be fore disabling or enabling a particular semaphore, the SED and SEE
operations scan the status of the se maphore. The condition codes CC 0
and CC 1 are a ffected as follows:
CC 1 CC 0 Evalu ation Significance
0 0 J Z S emaphore was disabled b y
ano the r CPU an d can no t be
disabled/enabled.
1 0 JN, JP Semaphore was disabled/
enabled.
START
Operation
successful?
Disable semaphore
Access to sema-
phore protected
global memory
Enable semaphore:
No
Yes
End
SED
SEE
Fig. 3 -8 Coordination of access to th e global memo ry
3
Semaphore Operations
CPU 928B Programming G uide
C79000-B8576-C898-01 3 - 73
Note
T he scanning of a particu lar semaphore (= read proce dure) an d
t he d isabling or enabli ng of the semaphore (=write procedure) are
one unit. No other CPU can access the semaphore during these
procedures!
When using sem aphores, remember the following points:
•• A semaphore is a global variable, i.e. the sem aphore with num ber
16 ex ists on ly once in the entire system, even i f your con troller is
using three CPUs.
•• All CPUs that require coordinated access to a com mon memory area
m ust use t he SED an d SE E oper atio ns.
•• All participating CPUs must execute the same start-up type.
Duri ng a C OLD RE STA RT , all th e se ma pho res are cl ea red .
Durin g a manual or automatic war m restart, the semaphores are
retained.
•• Start-up in mu ltiprocessor operatio n must be s ync hronized. For
t his reason, no test operation is allowed.
Semaphore Operations
CPU 928B Programming Guide
3 - 74 C79000-B8576-C898-01
Appli cation e xam ple for
semaphores
Tasks:
Four CPUs are plugged into an S5-135U. They output status messages to a
statu s si gn alli ng d ev ice vi a a comm on mem ory ar ea o f th e O pe ri pher als
(OW 6). A CPU must output each status message for 10 seconds. Only after
a 10 seco nd out put ca n a ne w me ssag e be o utpu t from the s ame CP U or a
different CPU overwrite the first message. The use of peripheral word OW
6 (ex tend ed I/O are a, no pr oces s im ag e) i s co nt roll ed b y a se ma phor e.
Only the CPU that was able to reserve this area for itself by disabling
the a ssig ne d se maph or e ca n writ e th is mes sage t o OW 6. Th e se ma phor e
remains disabled for 10 seconds at a time (TIMER T 10). The CPU
re-en able s the sema ph ore on ly a fter t his time r has elap se d. A ft er t he
semap hore h as b een re -ena bl ed, the ot her CPUs c an a cces s the re serv ed
area. The new message can then be written to OW 6.
If on e CP U atte mpts t o di sa ble a se ma phor e an d the sema ph ore is alr eady
disabled by a second CPU, the first CPU waits until the next cycle. It
then re-attempts to set the semaphore and output its message.
Implementation:
The following program can run in all four CPUs, each with a different
message. The blocks shown below are loaded.
5 flags are used as follows:
F 10. 0 = 1: a me ssag e wa s requ es ted or i s bein g pr oc esse d
F 10. 1 = 1: the sema phor e was di sabl ed s uc cess full y
F 10. 2 = 1: the time r wa s star te d
F 10. 3 = 1: the mess age wa s tr an smit ted
F 10. 4 = 1: the sema phor e was re -ena bled
Continued on next page
FB 0:
MAIN PROGRAM FB 10 :
REPORT
FB 100:
DISABLE SEMAPHORE
FB 110:
OUTPUT REPORT
FB 101:
ENABLE SEMAPHORE
3
Semaphore Operations
CPU 928B Programming G uide
C79000-B8576-C898-01 3 - 75
Semaphore application example continued:
FB 0
NAME :MAIN
:A F 10.0
:JC =M0 01 If no mess ag e is act iv e,
:
:AN I 0.0
:BEC
:
:L KH 2222 generate message and
:T FW 12
:AN F 10.0
:S F 10. 0 set "M ES SAGE " fl ag .
:
M001 :JU FB10 Call "REPORT" FB
NAME :REPORT
:
:BE
FB 10
NAME :REPORT
:AN F 1 0.1 If n o sema ph ore is d is able d,
:JC FB 100 call "disable semaphore" FB.
NAME :SEMADIS
:
:A F 10.1 If the semaphore is disabled
:AN F 1 0.2 and th e ti me r ha s no t star ted,
:S F 10.2
:L KT010.2 start the timer.
:SE T 10
:
:A F 10.2 If the timer has started
:AN F 1 0.3 and no mes sa ge i s be in g tr ansm it ted,
:JC FB 110 call "output message" FB.
NAME :MSGOUT
:
:A F 10.2 If the timer has started
:AN F 1 0.4 and th e se ma phor e is n ot e nabl ed
:AN T 1 0 and th e time r ha s elap sed,
:JC FB 101 call "enable semaphore" FB.
NAME :SEMAENAB
:
:AN F 10.4 If the semaphore is enabled,
:BEC
:
:L KH0000
:T FY1 0 rese t all fl ag s.
:BE
Continued on next page
Semaphore Operations
CPU 928B Programming Guide
3 - 76 C79000-B8576-C898-01
Semaphore application example continued:
FB 100
NAME :SEMADIS
:SE D 10 Disa bl e sema ph ore no . 10
:JZ =M001
:AN F 10.1 If the semaphore is disabled successfully,
:S F 10. 1 set "S EM APHO RE-D IS ABLE D" fla g.
M001 :BE
FB 110
NAME:MSGOUT
:L FW12 Transmit a message
:T OW 6 to the peripherals
:AN F 10.3
:S F 10. 3 Set "T RA NSFE R ME SS AGE"
:flag
:BE
FB 101
NAME :SEMAENAB
:SEE 10 Enable semaphore no. 10
:JZ =M001
:AN F 10.4
:S F 10.4 Set "SEMAPHORE ENABLED"
: flag
M001 :BE
3
Semaphore Operations
CPU 928B Programming G uide
C79000-B8576-C898-01 3 - 77
Contents of Chapter 4
4 .1 Intr oduction and Overvi ew. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 4
4.2 Program Processin g Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 7
4.3 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 13
4.3.1 Ch aracteris tics an d Indi cati on of t he Opera ting Mod e . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 13
4.3.2 Requestin g a n OVERALL RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 15
4.3.3 Performing an OVERALL RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 16
4 .4 RES TART Mod e. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 1 7
4.4.1 MANUA L an d AUTOMATIC CO LD RESTART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 18
4.4.2 MANUA L an d AUTOMATIC WARM REST ART . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 19
4.4.3 Com paris on of t he Different Restart Ty pes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 21
4.4.4 User I nte r fa ces for Restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 22
4.4.5 Interruptions in t he RESTART Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 25
4 .5 RUN Mo de . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 27
4.5.1 Cyclic Progra m E xec ution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 28
4.5.2 T ime-Driven Program Execution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 31
Delay i nte rrupt (f rom Versi on -3UB 12) 4 - 31
Clock-driven tim e interrupts 4 - 33
TIME INTER RUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 35
Colli sion o f time in terrupts (W EC K-FE) 4 - 36
4.5.3 CLOSE D LOOP CONT R OLL ER I NTE RRUPT: Proc ess in g
Clos ed Loo p Contr olle rs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 3 8
4.5.4 PR OCESS INTERRUPT: I nterrupt-Driv en Program Executi on . . . . . . . . . . . . . . . . . . 4 - 39
4.5.5 Nes te d In t errupt -Driven an d Time-Dri ve n Program Execution . . . . . . . . . . . . . . . . . . . 4 - 42
44
Operating Modes and Program
Processing Levels
CPU 928B Programm ing Guide
C79000-B8576-C898-01 4 - 1
4Operating Modes and Pro gram
Pro cess ing Leve ls
Thi s cha pt er provi de s an ov er vie w of t he ope ra ti ng sta tu se s an d
pr ogra m exec ut ion leve ls of t he CPU 928B. It info rms you in de tai l
abou t va rious types of start -up and t he orga ni z atio n blo ck s asso cia te d
wi th the m, in whic h you ca n pro gra m your own sequences f or va ri o us
sit ua tions whe n re sta rt ing .
You will also le a rn th e chara c te ri stic s of th e pr ogra m ex ec ut io n mo des
"c ycl ic proce s sing" , "time -c ont rol led pr oc essin g" a nd
"i nter rupt -dr ive n pr ocessing" a nd wil l see whic h blo ck s are avai labl e
fo r your user progra m .
4
CPU 928B Programming Guide
C79000-B8576-C898-01 4 - 3
4.1 Introduction and Over view
The CPU 928B has three oper atin g modes:
•• STOP mode
•• RESTART mode
•• RUN mo de
In the RESTAR T and RUN mode s, cert ain e vents c an o ccur t o which
the system pro gra m h as to r eac t. In ma ny c ase s, a spec i fic
or ga nizati on bl oc k (a blo ck from OB 1 to OB 35 ) is ca l le d a s a
reaction to an event and serves as the user interface.
The mo de s are displ aye d by L EDs on t he front pane l of the CPU.
Som e of th e m ode s mu st be a c ti va te d us i ng th e operat in g el e me nt s on
the front pa ne l of the C PU. T he positio n of th e LEDs and operating
ele me nts c an b e seen i n Fig. 4-1.
SIEMENS 6ES5 948-3UA11
RUN
STOP
RUN
STOP
SYS FAULT
RESET
RÜCKSETZEN
URLÖSCHEN
OVERALL
RESET
QVZ
ADF
ZYK
BASP
INIT
SI1
SI2
Receptacle for
S5-155U CPU948
memory card
Mode selector
LED (green)
LED (red)
LED (red)
Reset switch
Error display LEDs (red)
Error display LED (red)
Interface error LEDs (red)
Order number and version
Interface SI1
PG interface, 15-pin
Lever
Securing bolt
SI1 SI2
Second serial interface SI2
Receptacle for interface submodule
Fig. 4-1 Front p anel of the CPU 928B wit h di spl ay and operating eleme nts
Introduction and Overview
CPU 928B Programming Guide
4 - 4 C79000-B8576-C898-01
LED display of modes
Vari ous LEDs on th e front p anel of th e CPU signal the curr en t CPU
mode . The followin g tabl e shows you the rela tionshi p betwe e n the
ST O P an d R UN LE D disp la ys an d the m ode the y i ndi ca t e.
Othe r LEDs (BASP, ADF, QVZ, ZYK) pr ovi de m ore infor mat ion .
LED
RUN LED
STOP Mode
ON OFF The CPU is i n the RUN mode .
OFF ON The CPU is in the STOP mode.
Aft er a ST OP reque st at the switch or from th e PG, the STOP LE D is li t
cont inu ously, bec ause t he STOP c ondi tion was req ue ste d by the use r or, in
mult ip roc essor o pe rati on, by anot he r CPU and was not prompt e d by the CPU
itself.
OFF OFF The CPU is in the RESTART mode
or
the CPU is in the RE START /RUN mode , the progra m te st is ac tive a nd th e
pro gra m has rea ch ed a bre a kpo int (wa it stat e)
or
the CPU is in the RE START /RUN mode , the progra m te st is ac tive a nd a
bre akpo int was eli mi na ted a gain bef ore it was re ache d (wa i t state )
OFF flashing
slowly The CPU is in the STOP mode.
The C PU itse lf prom pt ed t he STOP cond it ion (possibl y also of the other CPUs).
Typical causes:
ADF, QVZ , LZ F, BCF, CL c ontro ll er e rror, interrupt coll ision, cy cl e t im e error,
BST ACK ove rf low, ISTACK ove rflow, stop com m a nd, end of pro cessing c he ck.
If yo u switc h the mo d e sele ctor to ST OP, t he f lashin g stops a nd th e LE D is l it
continuously.
OFF flashing
quickly The CPU is in the STOP mode.
An ove ra l l re set ha s bee n re que ste d. T his re que st c a n be p rom pt ed by the CPU
itsel f or by a n op er ator i nput .
ON ON Serious system error
Remedy:
- Overall Reset o f CPU;
if er ror pe rsists,
- Switc h off volt ag e at PLC, remo ve and re-inse rt t he CPU an d
pe rform Ove rall Reset;
if er ror pe rsists,
- Replace CPU or have it rep aired.
Tabl e 4-1 Meani ng of th e LEDs "RUN" and "STOP"
4
Introduction and Overview
CPU 928B Programming Guide
C79000-B8576-C898-01 4 - 5
Signalling and error LEDs
BASP LED
Thi s indi cat es wheth er the S5 bus signa l BASP (disa bl e comm an d
output) is active:
In the single proc e ssor mod e, the CPU clea rs BASP whe n it cha ng es
to the RUN mode an d set s BASP when it changes to the STOP mo de.
BASP is activa ted in the RESTART and in the STOP mod e and in the
first cycle fol lowing a warm r estar t.
In the multiprocessor mode , the c onditions for BASP are iden ti ca l
wi th those in the sin gle pro cessor m ode , provi de d the switc h on the
coor din at or i s set to R UN. (Se e your Syste m Manua l (/2/ in Chap ter
13 ) for more in form a ti on on the "T est mod e" spec ia l case.)
Note
If BASP i s a cti ve , a l l digita l output s are disabl e d.
If an AUT OMATIC or MANUAL WARM RESTART has been
exe cuted befo re the transi tion to the RUN mode , the B ASP LED
go es out onl y afte r the rem a ining c ycle has bee n proc esse d.
"QVZ" LED
Tim e out of an I/O m odu le .
"ADF " LED
Add re ssing e rror ; the use r progra m has acc e ssed an a ddre ss in the
pr oc ess ima ge f or whi ch the re is no module inse rte d in the I/ O s.
"ZYK" L ED
Cycle error; cycle monitoring time has been exceeded.
The errors ADF an d QVZ can onl y occu r in REST ART and in RUN,
the cyc l e erro r ZYK ca n only oc cur in RUN.
At the end of the progra m proce s sing level s ADF, QVZ or ZYK, the
erro r LED is clea re d by th e system prog ra m, if the CPU has not gone
to the STOP mode.
Introduction and Overview
CPU 928B Programming Guide
4 - 6 C79000-B8576-C898-01
4.2 P rogram Proc essi ng Le vels
Fi g. 4-2 gi ve s an ove rv ie w of th e op er atin g sta te s and t he proce s sing
lev els i n the CPU 928B (-3UB12) . The expla nat ions of t he
abbrevia ti ons a re on the following pag e.
RESTART mode
NAU
STP
PEU
BAU
DOPP
STUEU
STUEB
NAU
BAU
STP
PEU
DOPP
STUEU
STUEB
LED BASP: LED BASP: LED BASP:
LED STOP: LED STOP: LED STOP:
LED RUN: LED RUN: LED RUN:off off
off off
off
on
on on
on
RUN
mode
STOP
mode
CYCLE
PROCESS
INTERRUPT
DELAY
INTERRUPT
TIME INT.
CONTR. INT.
TIMED JOB WECK-FE
REG-FE
ZYK
BCF
LZF
ADF
QVZ
SSF
BCF
LZF
ADF
QVZ
SSF
POWER UP
ABORT (OB 28)
(mode selector,
PG-STP or MP-STP)
POWER
DOWN
NAU
In multiproc.
operation:
Wait to start
cycle together
AUTOMAT.
C. RESTART/
RETENTIVE
C. RESTART/
WARM REST.
MANUAL COLD
RESTART/
RETENTIVE
C. RESTART/
WARM REST.
Fig. 4-2 Operating states and program processing levels
4
Program Processing Levels
CPU 928B Programming Guide
C79000-B8576-C898-01 4 - 7
Features of a program
processing level
A program processing level is characterized by specific features which
are explai ne d on th e followin g page s.
1) from Version -3UB12
Progr am processing levels in RESTART:
MANUAL COLD RESTART
MANUAL WARM RESTART
RET ENTIVE MANUAL COLD RE START Restart
RET ENTIVE AUT OMATIC COLD R EST ART levels
AUTOMATI C COL D R ESTART
AUTOMATI C WAR M R ESTART
BCF (o pera ting c ode error)
LZF (runtime error) error
ADF (add re ssing error ) levels
QVZ (timeout)
SSF (int er face error)
Pro gram pr oce ssing leve ls in the RUN mode:
CYCLE (cyc l ic program e xe c uti on)
TIMED JOB (time-driven pr ogram execution)
TIME INT 5 se c (time-driven pr ogram ex ec utio n)
TIME INT 2 se c (time-driven pr ogram ex ec utio n)
TIME INT 1 se c (time-driven pr ogram ex ec utio n)
TIME INT 5 00 m s (t im e -dr ive n pr ogra m ex ec ut io n)
TIME INT 2 00 m s (time -dr iven pr ogra m exec ut io n) B asi c
TIME INT 1 00 m s (time -dr iven pr ogra m exec ut io n) le ve ls
TIME INT 50 ms (t ime-driven progra m ex ecut ion)
TIME INT 20 ms (t ime-driven progra m ex ecut ion)
TIME INT 10 ms (t ime-driven progra m ex ecut ion)
CONTROLLER INT ( collision of tim e interrupts)
DELAY INT E RRUPT (t ime -dr iven pr ogra m ex ecut ion) 1)
PROCE SS INT (p roc e ss interru pt-dri ve n prog. exe cuti on)
WECK-FE (collision of time interrupts)
REG-FE (C L cont rol ler e rro r)
ZYK (cycle time error)
BCF (o pera ting c ode error) Er ror
LZF (runtime error) levels
ADF (add re ssing error )
Program Processing Levels
CPU 928B Programming Guide
4 - 8 C79000-B8576-C898-01
Nesting other levels
Whe n an ev en t occurs, whic h requi re s high er prio rity pro cessing, the
curr en t leve l is int er rupt e d by the syste m progra m and t he h igh er
priority level is activated.
This occ urs in t he fol lowing situa ti ons:
•• at erro r levels
and program processing
le vels at RESTAR T: a lway s at operat ion boun daries,
•• all other levels: at block or operation boundaries
( de pe nding on t he sett in g in D X 0
refer to Chapter 7)
Specific system progra m
Ea ch progr am pro cessing l eve l has its spe cia l system p rogr am.
ISTACK
Aft er the syste m p rogr am cal ls a n organi z atio n blo ck , the CP U
exe c ute s the ST EP 5 sta tem e nt s it cont ains. The curre nt regist er reco r d
is save d in the ISTACK and a ne w regist er r ecor d is set u p (regi ster:
ACC U 1 t o 4, block stac k point e r, block a ddr ess re gist er, dat a bloc k
sta rt address, data block lengt h, step address c ou nte r and the base
addr ess re gist er ).
If " norm a l" p rogr am e xecu ti on is in terrupte d by the oc cu rre nc e o f an
eve nt , followin g the exe cu tion of the OB, the CPU con ti nue s the
pr ogra m execut io n at the point of inte rrup ti on as long a s no stop i s
pr ogra m med i n th e OB.
Example:
CYCLE CYCLE
BCF BCF
ADF
ADF
ADF
BCF
CYCLE
Depth 3
Depth 2
Depth 1
ISTACK =
ISTACK
ISTACK
ISTACK
Image of the
interrupted levels
STP WARM RESTART
Fi g. 4- 3: Princi pl e of l e vel chan g e an d I ST A C K
Example:
At the CYCLE processing level, the system program
updates the process image of the inputs and
outputs, triggers the cycle monitoring time and
invokes management of the programmer interface
(s ys tem chec kpoint ).
4
Program Processing Levels
CPU 928B Programming Guide
C79000-B8576-C898-01 4 - 9
Priority
Program processing levels have a fixed priority. Depending on this
pr ior it y, the y c an i nt er rupt eac h ot he r or c an b e nested wi thi n e ach
other.
The warm resta rt and er ror le ve ls dif fer from th e basic le vel s i n that
the y ca n always be nest e d at ope ra ti on bo unda ri e s whenever the
appr opri a te even t occ urs. T he y ca n be nest ed both in th e basic leve l s
and wi thi n eac h ot her. In th e eve nt of er rors, the last t o occu r always
ha s the highe st priority .
A basic le vel on the other hand c an be neste d in a lower prior it y
lev el only at block boundar i es unless this def ault is chang ed by
writ ing the appropr ia te prog ra m in DX 0 (see Chapter 7).
Pri ority of the "ba sic leve ls":
CYCLE
TIME D J OB
TIME INT 5 s asc e nding prior it y
TIME INT 2 s
.
.
CONTR OLL ER INT
PROCESS INT
Example:
A process interrupt occurs during the
processing of a time interrupt. Since the
process interrupt has a higher priority, the
processing of the time interrupt level is
interrupted at the next block boundary and the
PROCESS INTERRUPT program processing level is
activated. If, for example, an addressing
error is detected while the process interrupt
is being serviced, the process interrupt is
stopped immediately at the next operation
boundary to activate the ADF level.
Program Processing Levels
CPU 928B Programming Guide
4 - 10 C79000-B8576-C898-01
Response to double
error
Once an e rror leve l has been act ivated (ADF, BCF, LZ F, QVZ, REG,
ZYK) it cann ot be act iv ate d agai n until it h as be en proc e ssed
com pl et e ly, not even if a diff eren t pro gra m p roc e ssi ng level is nested
wi thin it . In this case , the P LC cha nge s to t he STOP mode
owing to the double cal l of a program pro cessing l evel (DO PP in
the ISTACK).
Co llisions of time in terrupts are a n exc e pti on, re fe r to the re le va nt
sect ion). In the IST ACK, a t de pth "01" , the DOPP identifi er and the
error level called twice are marked.
Examples of double
call errors
Example 1:
During the pro cess ing of t he A DF l evel (us er
interface OB 2 5) a further pro cess ing erro r oc curs .
Since the ADF leve l is sti ll a ctiv e, it ca nnot be
called a secon d ti me; the CPU changes to STOP.
STOP
Addressing error in PB 30
causes STOP
Addressing error in FB 5:
Call OB 25/
ADF level
CYCLE
ADF
FB 5
OB 1
PB 25 PB 26
PB 30
OB 25
Fig. 4-4 Change of level as a result of a double call error
4
Program Processing Levels
CPU 928B Programming Guide
C79000-B8576-C898-01 4 - 11
Description of the individual
levels
The individual program processing le vels and the corresponding user
interf ac es are descr ibed in more detail in the fo llowin g sections:
Section 4.4 describes the program processing le ve ls
in REST ART .
Section 4.5 desc ribes the program processing le ve ls
in RUN
Se cti ons 5.6 an d 5.7 d esc ribe the er ror lev el s i n REST ART
an d RUN .
Example 2:
If an oper atio n co de error occ urs in the L ZF p rogr am proce ssin g le vel, the
system pro gram att empts to cal l th e BCF le vel (use r interf ace OB 2 9). This
has, howev er, alre ady been act ivat ed by th e oc curr ence of a pa rame ter erro r
(user inte rfac e OB 30) and has not yet bee n co mple tely pro cess ed. Calling the
BCF level agai n at this po int is n ot permi tted ; th e CPU ch ange s to STOP (s ee
Fig. 4-5).
if op code error
STOP
BCF
LZF
CYCLE
OB 27
OB 29 PB 5 FB 7
OB 30
OB 1
FB 2 FB 3
OB 31 FB 22
FB 21
error
if parameter
error
if substitution
Parameter error in FB 3:
OB 30 call /
BCF level
Runtime error processing OB 30:
OB 31 call /
LZF level
Op code error in FB 22
causes STOP
Fi g. 4-5 Double ca l l of er ror le vel BC D
Program Processing Levels
CPU 928B Programming Guide
4 - 12 C79000-B8576-C898-01
4.3 STOP Mode
4.3.1
Characteristics an d
Indicati o n of the Operati n g
Mode
The STOP mode is dist ingui sh ed b y the follo wing feat ure s:
User program
The user program is not proc essed.
Retention of data
If p rogr am exe cu ti on ha s al read y be en ac ti ve , the value s of counte rs,
tim e rs, fl a gs an d p roc e ss ima ges are re ta i ne d at the tr an si tion t o the
stop mode .
BASP signal
The BASP signa l (disabl e com man d out put ) is active . This disa bles a ll
di gi ta l ou tpu ts.
Exce ption: In multiproce ssor mod e the B ASP signal is not active
du ring the te st mode of the coordi nator - ple ase see your Syste m
Ma nua l ( /2/ in Chap te r 13) f or more information.
ISTACK
If program e xecuti on was already acti ve , the re is an info rmatio n field
fo r eac h inte rru pte d pr ogra m proce s sing l ev el in the int er rupt sta ck
(ISTAC K) tha t indic ate s the c ause of the interru pt when the CPU is in
the STOP mode (see Section 5. 4).
LEDs on the front panel
of the CPU
RUN LE D: off
ST OP LED: on (ste ady or fl a sh ing )
BASP LE D: on (except in te st mo de)
The STOP LED indi c at es the pos sible ca uses of t he c ur re nt stop sta te.
The fol lowing para grap hs d escri be a c ontinuously lit or fl ashing
STOP LE D.
4
STOP Mode
CPU 928B Programming Guide
C79000-B8576-C898-01 4 - 13
STOP LED lit continuously
The STOP mode wa s trigge re d by the followin g:
•• in the single proce s so r mo de
- the mode selector was switched from RUN to STOP
- the PLC STOP prog ra mm er fun ctio n was act ivat ed
- a de vice fa ult oc cu rre d (BAU, PE U)
- an OVE RAL L RESE T was pe rfor med
•• in the m ult iproc e sso r m od e
- by switc hi ng th e mode sel ect or on the coordi nator to STOP,
- by ano ther CPU go ing i nto STOP as the resu lt o f a faul t (a CPU
not causi ng a fault is lit co nti nuously) .
STOP LED flashes slowly
(approximately once every
two seconds)
Whe n the STOP LE D fl ashe s slowl y, this norm ally i ndi cat es an error .
In the mult ipr oc essor mode, slow fl ashi ng indi ca t es the CPU whic h
ca used t he stop mode (owi ng t o an e rr or).
The STOP LE D fla she s slowly in the follo wing situat ion s:
- a stop ope ra t ion wa s prog ramm e d in t he user progr am
- an ope ra to r er ror ha s occurre d (e . g. DB 1 e rr or, sel ec t ion of an
i ll ega l start-up type , etc.)
- progra m ming or dev ic e e rr ors (c al ling a blo ck tha t is not load ed ,
add re ssing e rror , time out , operat io n code err or etc .); the followi ng
LEDs also light up to define the possible cause of error more
exactly:
ADF LED
QVZ LE D
ZYK LE D
- the END PROGRAM TEST progra mmer fu nction wa s activated in
thi s CPU.
The STO P LED flas hes
quickly (approximately twice
per second)
Whe n th e ST OP LED fl ashes quick ly, th is is a wa rni ng t ha t an
OVERALL RESET is being requested.
STOP Mode
CPU 928B Programming Guide
4 - 14 C79000-B8576-C898-01
4.3.2
Requesti n g an OVERAL L
RESET
Request by the syste m
program
Ea ch tim e you turn on the powe r and pe rfo rm a n over all re se t, the
CPU ru ns t hro ugh a n init iali zat io n routin e. If e rro rs are de tec ted
durin g thi s ini tializa tion, the CPU change s to the STOP m ode and the
ST OP LED fl ashe s quick ly.
Possible errors: Conten ts of the RAMs are not correct .
Remedy: overall reset on the CPU
Cont ents of the user EPROM are not
correct
R emedy: insert programm ed EPR OM
and overall reset on the CPU
You m ust dea l wi th the ca use of the probl em and then p erform a n
ov er all re se t on the CPU aga i n. OVERAL L RE SET is also re que ste d
if a CPU or system error occur s. You ca n reco gni ze this er ror by t he
fac t tha t the requ est a pp ears a ga in foll owin g an OVERAL L RESET.
In this case, call your SIE MENS re pr ese ntat ive.
Operator request
You req ue st OVERALL RESET as follows:
1. Switc h the mode selec tor fro m RUN to STOP.
Re sult: the CPU is in the STOP mode . The ST OP LED is lit
contin uously.
2. H o ld the momentary-contact mode selector in the OVERALL
RE SET position; at th e sa me ti me, switch the mode sele ctor from
STOP to RUN and back to STOP.
Result: you reque st an OVERAL L RESE T . The STOP LE D
fl ash es quic kly.
Note
If y ou do no t want t he OVERAL L RESET th at you re qu est ed to
be exe cu ted, carr y out a COL D RE START or MANUAL W ARM
RESTART.
4
STOP Mode
CPU 928B Programming Guide
C79000-B8576-C898-01 4 - 15
4.3.3
Performin g an OVERALL
RESET Regardless of whether you yourself or the system progra m requested
an overal l reset, you perform the OVERALL RESE T as follows:
•• Hold th e mode selector i n the OVE RAL L R ESE T positio n; at the
sam e time , switc h the mode select or from ST OP to RUN and once
a ga i n to S T O P.
Result: the O VERALL RE SET is p erform e d, the STOP LED is li t
continuously.
•• OR: use the PG func ti on OVE RAL L RE SE T
( If you per form an OVER ALL RESE T at the PG, the ma nua l
overall reset request using the switches and selector can be
o mitte d. The positi on of the rese t swit ch an d mode se lec tor ar e
t he n ir rele va nt.)
Result: the OVE RALL RESE T i s per form e d. Th e STOP LE D is
lit co ntinuo usly.
Note
Onc e you have pe rformed an O VERALL R ESET , the onl y
perm i tted rest ar t mode is a COL D RESTART .
STOP Mode
CPU 928B Programming Guide
4 - 16 C79000-B8576-C898-01
4.4 RE START Mode
The RESTAR T mode is distingui shed by the following feature s:
Transition from STOP
to RU N
The RESTAR T is the tra nsit io n from the ST OP mode to th e RUN
mode.
Restart types
The CPU 928B has the foll owin g restart mode s:
- COL D RESTAR T (manual o r automatic )
- WARM RE STAR T (m anua l or automatic )
- RET ENTIVE COL D RESTAR T (ma nual or au tomati c -
only with Version -3UB 12)
Fol lowing a COLD RE STAR T, the cyc lic user progra m is proce s sed
fr om t he begin nin g. Foll owin g a WARM REST ART , the cyc l ic user
pr ogra m is proce s sed from t he point a t whic h it was int errup te d.
Organization blocks
The fol lowi ng orga niz a ti on bl oc ks ar e c a lled :
for MANUAL or AUT OMATIC COL D REST ART : OB 20
for MANUAL WARM RE ST ART or RETENT IVE
COL D REST ART : OB 21
for AUTOMAT IC WARM RE ST ART or RE TENT IVE
COL D REST ART : OB 22
The lengt h of the STEP 5 sta rt- up pro gra m in the OBs is not rest rict e d.
The organi zat ion block s a re not t ime -monito red. Ot her bloc ks can be
called in the start-up OBs.
Data handling
In each start-up type, the values of counters, timers, flags and process
i ma ge s are ha nd led di fferent ly.
BASP signal
The BASP signa l (disabl e com man d out put ) is active . This disa bles a ll
di gi ta l ou tpu ts.
Exception: in the test m ode , BASP is not ac tiva ted! (Plea se see your
System Manual for inform ation on the t est mode.)
LEDs on the front panel of the
CPU
RUN LE D: off
STOP LE D: off
BASP LE D: on (exc ept in te st mode)
Restart characterist ics in
multiprocessor mode
For i nfo rm atio n on th e start -up proc e dure in the mult ipr oc essor mode,
refer to Section 10.1.7.
4
RESTART Mode
CPU 928B Programming Guide
C79000-B8576-C898-01 4 - 17
4.4.1
MANUAL and AUTOMATIC
COLD REST ART
When is a COLD RESTART
permitted?
A COLD RESTAR T is always pe rm it ted provi de d th e system is not
re qu est ing a n OVE RAL L R ESE T .
MANUAL COLD RESTART
You carry out a MANUAL COLD REST ART as fol lows:
•• Hol d the m ode selector i n the RESE T positi on; at the sam e ti me ,
switch the mode selector from STOP to RUN.
•• Or use the PC START progr amm e r funct ion (COL D REST ART ).
AUT OMAT IC CO L D
RESTART
AUTOMAT IC COLD RESTAR T is triggered in the followi ng case:
Afte r power fail ure/ POWE R OFF in R ESTART or RUN followe d by
po wer rest ore /POWE R ON, the CPU runs an initi a lizat ion rout ing and
then at te mpt s to autom atically exe c ute a COLD RESTART as l ong as
DX 0 is corre c tl y para m et e riz e d (see Ch ap te r 7).
Prerequisite: • The switch es on all CPUs and on the
co or dinato r mus t rema i n at RUN .
•There must have be en no fa ults in th e
initialization run.
•The CPU was not in the STOP m ode
wh en t he power wa s swit ched off.
In the case of power fa ilure in an expansi on uni t (PEU sign al ), the
CPU go es to STOP. It rem ains in STOP unt il the PEU signa l is
switc hed inacti ve and then attemp ts to exe cute an AUTOMAT IC
COLD RE ST ART or an AUTOMATIC WARM RE ST ART .
RESTART Mode
CPU 928B Programming Guide
4 - 18 C79000-B8576-C898-01
4.4.2
MANUAL and AUTOMATIC
WARM RESTART
When is a WARM RESTART
not
permitted?
A MANUAL WARM RE ST ART is not perm itte d in the fol lo wing
situations:
•• whe n the system is re que sti ng OVE RAL L R ESE T
or
•• after the following events:
- do ubl e call of a progra m proce ssing lev el (IST ACK: DOPP),
- OVERALL RESET (control bits: URGELOE),
- start -up aborted (c on tro l bits: ANL-ABB),
- ST OP after the END PROGRAM TEST progra mmer fu nction,
- whe n compre ssing the memory i n the STOP mode ,
- stac k ove rf low,
- when t he u ser pr ogra m has be en m odi fie d i n the ST OP mode.
MANUAL WARM RESTART
You carry out a MANUAL WARM REST ART as fol lows:
•• The mode sele cto r is in the mi d-po sition.
•• Switch the mode selector from STOP to RUN.
•• Or use the PLC STAR T progra m m er func tion (W ARM
RESTART).
4
RESTART Mode
CPU 928B Programming Guide
C79000-B8576-C898-01 4 - 19
AUT OM ATIC WARM
RESTART
If there is a power failure /POW ER OFF during REST ART or RUN,
when t he powe r retur ns agai n/POW E R ON, t he CPU pe rfor ms an
initialization routine and then attempts to perform a WARM
RESTART automatically, as long as DX 0 is correctly parameterized
(see Chapte r 7).
Conditions: •• The sel ect ors on all the CPUs and on the
coo rdi na tor rema in set to RUN.
•• No e rr ors ar e det ec t ed d uri ng th e init ia liz a ti on.
•The CPU was not in STOP be for e the powe r
fai lure/POW E R OFF.
If the re is a power f ailu re in an ex pansion unit (PE U signa l) , the CP U
cha nge s to ST OP . I t rem ai ns in this sta te unt il the PE U signa l is
clea re d and then at tem pts to per form an AUTOMATIC W ARM
REST ART or AUTOMATIC COL D RESTART .
RETENTIVE COLD
RESTART (from Version
-3UB12)
If the parame t er "Re tentive c old rest art" is sto re d in DX 0, the system
pr ogra m exec ut e s RET E NTI VE COL D RE ST ART i nste a d of WA RM
RESTART. See the following sect ion to find out how this differs t o a
"n orm al" COL D REST ART.
RESTART Mode
CPU 928B Programming Guide
4 - 20 C79000-B8576-C898-01
4.4.3
Comparison of the
Diffe rent Restart
Types
System program
performs
COLD REST ART WARM RESTART RETENTIVE COL D
RESTART
manual automatic manual automatic manual automatic
Eva luat ion of :
- DB 1
- DB 2
- DX 0
- DX2
yes
yes
yes
yes
yes
yes
yes
yes
no
no
no
no
no
no
no
no
no
no
no
no
no
no
no
no
Initi aliz ati on of:
- DB 0
- 9th track
- Disable/
enable
interrupts
- Cycle
statistics
no 1)
yes
yes
yes
no 1)
yes
yes
yes
no 1)
no
no
no
no 1)
no
no
no
no 1)
no
yes
no
no 1)
no
yes
no
De leti on of:
- Timed job
- Dela y
interrupt
- ISTACK/
BSTACK
- Proce ss image
of the inputs
- Proce ss image
of t he out put s/
digi ta l I/ O
- Analog I/O
yes
yes
yes
y es (c om -
pletely)
y es (c om -
pletely)
yes
yes
yes
yes
ye s (c om -
pletely)
ye s (c om -
pletely)
yes
no
yes
no
no
no
no
no
yes
no
no
no
no
no
yes
yes
no
yes (acc. to
9t h tr ac k )
no
no
yes
yes
no
y es (a c c. to
9t h tra c k )
no
Table 4-2 Comparison of the different restart types
4
RESTART Mode
CPU 928B Programming Guide
C79000-B8576-C898-01 4 - 21
System program
performs
COLD REST ART WARM RESTART RETENTIVE COL D
RESTART
manual automatic manual automatic manual automatic
Table 4-2 continued:
De leti on of
(cont.):
- IPC fl ags
- Sema ph ore s
- F fla gs a nd
S flags
- Timers and
counters
yes
yes
yes
yes
yes
yes
yes
yes
no
no
no
no
no
no
no
no
no
no
no
no
no
no
no
no
Pro cessing of
rem ai ning cyc le
in the case of
active BASP
signal no no yes yes no no
Rest art type
de te rm ine d b y
OB 223
COLD
RESTART COLD
RESTART MANUAL
WARM
RESTART
AUTO.
WARM
RESTART
MANUAL
WARM
RESTART
AUTO.
WARM
RESTART
Indicati on of the
restart type at
the progr ammer
in the ISTACK
control bits
NEUSTA NEUSTA
+ AWA MWA AWA ANL-6 +
MWA ANL- 6 +
AWA
User interface OB 20 OB 20 OB 21 OB 21 OB 22 OB 22
1) DB 0 is always initialized after POWER ON or OVERALL RESET
De finiti on of the "9th trac k "
The "9t h trac k" i s a li st of input an d o utp ut byte s in the pr oc ess ima ge
tha t ack nowl edge d at the last COL D REST ART .
If you pro gra m and load DB 1, then fo llowin g a succ essful COL D
RE ST ART , t he 9th tra ck co nta i ns only the input a nd ou tpu t byt es
liste d i n DB 1.
You ca nno t acce s s the 9th tra ck wi th ST EP 5 ope ra tions.
4.4.4
User Interfaces for Restart The organiz atio n blo ck s OB 20, OB 21 an d OB 2 2 are used a s user
inte rf ace s for the diffe re nt re start type s. You ca n stor e your STEP 5
pr ogra m for ea ch rest ar t ty pe in th ese blocks.
RESTART Mode
CPU 928B Programming Guide
4 - 22 C79000-B8576-C898-01
You can do the followi ng in the RESTAR T OBs:
•• se t fl ag s,
•• sta rt time rs (t he star t is dela ye d by the syste m pr ogra m unt il the
u ser progra m en ters the RUN mode ),
•• prep ar e the data t raffi c of the CPU with the I/ O modules,
•• exe c ute synchro nization of the CPs.
OB 20
COLD RESTART :
When the CPU executes a MANUAL or AUTOMATI C COLD
RE ST ART , the syste m progra m cal ls OB 20 once. In OB 20, you can
sto re a ST EP 5 pr ogra m that e xe c ut es pre pa ra t ory ste ps for restarting
cyclic program execution:
Afte r OB 20 is processed , the c ycl ic prog ram exe c ution begi ns by
calling OB 1 or FB 0.
If OB 2 0 is not loa de d, the CPU be gins cyc l ic prog ram exe c ution
imm edi at e ly after t he end of a COLD RE ST ART (follo wing the
system act iviti e s) .
OB 21
MANUAL WARM RESTART or RET ENTIVE MANUAL
COLD RESTART :
Whe n the CPU carries out a MANUAL WARM RESTART or
RET E NTIVE MANUAL COLD RESTART, the system progr am c al ls
OB 21 o nce. In OB 21, yo u can sto re a ST EP 5 pr ogra m tha t ca rri e s
ou t speci fi c ac ti vit ies once bef ore cy cl ic pro gra m e xe cution is
resumed.
MANUAL WARM
RESTART
Afte r OB 21 is pro cessed , for MANUAL WARM REST ART t he
cyc li c program e xe cuti on c ont inu es wit h the next sta tem en t afte r the
po int at which i t was interr upted. The fol lowing cond it ions apply:
•• The disa bl e comm an d out put si gna l (BASP) re mai ns ac tive whil e
the rest of the cycle is processed . It is only clear ed a t t he beginnin g
of the next (complete) cycle.
•• The proc e s s outpu t ima ge is re set a t the en d of the re m a ini ng c yc le.
If OB 21 is not loaded, then at the end of a MANUAL WARM
RESTART an d af te r pe rform ing system a ct iv it ie s the CPU be gins
pr ogra m ex ecut ion ag ain at the po int at which t he progr am wa s
interrupted.
4
RESTART Mode
CPU 928B Programming Guide
C79000-B8576-C898-01 4 - 23
Note
The CPU regist ers a power down (NAU or PEU) even whe n this
occ urs in the STOP mode. If you then trigg er a MANUAL
WARM REST A RT, the CPU c alls OB 22 be fore OB 21. If,
instead, you trigger a MANUAL COLD RESTART, the previous
events are ignored by the CPU and OB22 is not called.
RETENTIVE MANUAL
COLD RESTART
If the parameter "RETENTIVE COLD RESTART" is entered in the
dat a bloc k DX 0, a ft er proc e ssing OB 21 , the system progra m t hen
goes th roug h a COLD RESTART ( the CPU resum es progra m
execution with the first STEP 5 statement in OB 1 or
FB 0). The si gna l stat es of the f lags, IPC flags, sema phor e and t he
bl oc k addre ss l ist ( DB 0) are retained.
OB 22
AUTOMAT IC WARM RE STAR T or RETE NT IVE AUTOMAT IC
COL D REST ART :
Whe n the CPU exec utes an AUTOMAT IC WARM RE ST ART or a
RET ENTI VE AUTOMAT IC COLD RE STAR T, the system prog ram
ca ll s OB 22 once. Here you can store a ST E P 5 program which
exe c utes sp eci fic actio ns onc e befo re rest ora tion of progr am exe cu ti on
pr eviou sly in terru pte d in RUN.
AUT OM ATIC WARM
RESTART
Whe n the power is restore d, the CPU car ries out the system func tions
me nti one d abov e and att e mpts to cont in ue the prog ra m from the poi nt
at whic h it was inte rrup ted.
If it is loa de d, OB 2 2 is cal led fi rst. Afte r OB 22 is proc e ssed, cy clic
pr ogra m ex ecution re su mes with the ne xt stat e ment af ter th e po int at
whi ch it was inte rrup ted.
Afte r a power f ailu re a nd subsequ ent restor atio n of power, the
fo llowin g co ndi tions ap ply :
•• The BASP signa l ( disa ble com m an d output) rema i ns acti ve while
the re ma i nin g cy cl e is proc e sse d. It is clea re d a t th e begi nning of
the next complete cycle.
•• The proc e s s outpu t ima ge is re set a t the en d of the re m a ini ng c yc le.
RETENTIVE AUTOMATIC
COLD RESTART
If the parameter "RETENTIVE COLD RESTART" is entered in the
dat a bloc k DX 0, a ft er proc e ssing OB 22 , the system progra m t hen
goes th roug h a COL D REST ART (the CPU resum es pro gra m
execution with the first STEP 5 state ment i n OB 1 or FB 0). The
sig na l state s of th e fl a gs, IP C f la gs, sem ap hore and th e bl oc k a ddre s s
list ( DB 0) ar e re taine d.
RESTART Mode
CPU 928B Programming Guide
4 - 24 C79000-B8576-C898-01
4.4.5
Interrup tio ns in the
RESTART Mo de A start -up pr ogra m can be in te rru pte d by the fol lowi ng:
•• NAU (po wer fai lure ) or PEU ( powe r failure in exp an sion unit),
•• acti vating the stop switch, the stop opera tion, MP-STP or PG-STP,
•• progra m an d devic e er rors (se e Sec tion 5. 6).
If you wa nt to conti nue an inte rrup ted REST ART with o ne of the
possible restart types, please remember the following points:
Power failure at RESTART
Afte r powe r re turns foll owing a power fai lur e you must di sti ngui s h
bet wee n t he situa t ion s liste d in the follo wing t able :
Selec ted mode : AUTOM ATIC WARM RESTART
The CPU is performing a COLD RESTART (OB 20):
fol lowing the return of power aft er p owe r failure , t he orga ni zat ion blo ck OB 2 2 (AUTOMATI C
WARM RE STAR T) i s ac tiva ted at the point of interr uption in OB 20.
The CPU is performing a MANUAL W ARM RESTART (OB 21):
follo wing the return of power aft er a power fai lure, org aniz ation bloc k OB 22 (AUTOMAT IC WARM
RE ST ART ) is act iva t ed a t the poi nt of int er rupt ion in OB 21.
The C PU is al re ady pe rfor ming an AUTOMATIC WARM RESTART (OB 22 ):
fol lowing the retur n of power a fter a power fa ilure, no se cond OB 22 is ac tiva te d. Th e interr upt ed
OB 22 is not continu ed a fte r the retu rn of power but is abor ted and then c all ed agai n and proce ssed
fro m the b eginning.
AUTOM ATIC COL D RESTART
The CPU is perform i ng a MANUAL or AUTOMATIC COL D RESTAR T or a MANUAL WAR M
RESTART:
fol lowing the retur n of power a fter powe r fail ure , the interrup te d OB 20 or OB 21 is not c on tinue d, but
aba ndon ed a nd t he newly c all ed OB 20 is proce s sed.
The sam e rules apply to an AUTOMATIC WARM RE ST ART
fo llowin g a PEU signa l .
4
RESTART Mode
CPU 928B Programming Guide
C79000-B8576-C898-01 4 - 25
MANUAL WARM RESTART
after abortin g a RESTART If the CPU goes t o the STOP mode d uring any REST ART (stop
switc h of ADF) and you the n trigger a MANUAL WARM
REST ART , the inte rrup ted RESTART i s co n tinue d fro m the poin t at
whi ch it was int errup te d. OB 21 is not act ivat ed .
MANUAL COLD RESTART
after abortin g a RESTART If the CPU goes t o the STOP mode d uring any REST ART a nd you
the n trigge r a MANUAL COLD RE ST ART , the i nter rupt e d
REST ART is aborted and a COL D RESTAR T is pe rf orme d (if it
exists, OB 20 is called).
Abo rti ng RETENT IVE
COLD REST ART
RET E NTI VE COLD RE ST ART i s a bo rted by :
•• Power failure in the centra l controller (NAU) or in the exp ansion
u nit (PE U) ,
•• St op switch, stop comma nd, MP-ST P or PG-STP
or
•• Progra m e rr ors an d hardwa re faults (see Sect ion 5.6).
An abor ted RE TENT IVE COLD RE STAR T is not continued at warm
restart. Instead, a new RETENTIVE COLD RESTART is started.
Pre vi ous eve nts a nd sta tu ses ar e not take n i nto ac c ount in the se lec ti on
of r est ar t ty pe . The fol lowi ng a ppl ie s espe c ial ly:
•• If a MANUAL or AUTOMATIC RETENTIVE COLD R ESTART
is aborte d by POWE R OFF or power failur e in the expa nsio n unit,
a RET ENTIVE AUTOM ATIC COLD RESTART always takes
p lac e at POWER ON if all othe r resta rt condi ti ons are me t.
•• If a MANUAL or AUTOMATIC RETENTIVE COLD R ESTART
is initiated by one of the other abort types, a new RETENTIVE
MANUAL COL D RESTART takes place.
RESTART Mode
CPU 928B Programming Guide
4 - 26 C79000-B8576-C898-01
4.5 RUN Mode
W hen th e CP U has executed a RES TART ( and on ly then) i t changes
to the RUN mod e. This mod e is characterized by t he fo ll owi n g
features:
Execution of the user program
T he user program in OB 1 or in FB 0 is ex ec ute d cyclically and
a dditi onal interrupt-driv en program sections can be n ested in it.
Tim er s, counte rs, process
image
All t he t imers a n d co u nters sta rted in t he prog ram are ru nni ng, th e
proce ss image is updated cyclically.
BASP signal
The B ASP sign a l (d is able c omman d ou t put ) is inac ti v e. All th e d igit al
outputs are therefore enabled.
IPC flags
Th e int erprocess or c omm un i ca tion (I PC) flag s are updat ed c y clic ally
(provided this is programmed in DB1).
LE Ds on the front panel of the
CPU
RUN LED: on
STOP LED: off
BAS P LED: off
Note
If an AUTOMA TIC or MA NU AL wa rm r est art wa s execute d
be fore the CP U went in to the RUN mo d e, t he BA SP LED
remai ns lit unt il the rest o f the cycle h as been proce ssed an d th e
process image has been updated.
The RUN mo de is only possible after the RESTAR T mode.
Program processing levels
In th e RUN mod e t h ere are 13 basic prog ram proc es sin g l ev el s, as
follows:
•• CYCLE: th e us er program i s e xe cut ed c ycli ca ll y
•• TI MED JOB: th e user program i s e xe cut ed a t fixe d
times you have programmed or once at a
fi x ed time (clock-contr o lled time
interrupt)
4
RUN Mode
CPU 928B Programming G uide
C79000-B8576-C898-01 4 - 27
•• 9 TI ME INTERRUPTS: t he user program is processed at
fixed intervals specified by the
system.
•• CONTROLLER time-driv e n proce ssi ng of a preset
INTERRUPT: number of closed loop contro l lers.
•• DELAY T he user progra m is processed
INTERRUPT once after a preset delay
time has elapsed.
•• PROCESS proce ss inte r rupt-d riv en user
INTERRUPT: program execution.
T he processing levels di ffer from each other in the fo llowing aspects:
•• th e y are trig g ered by diff e re nt e v en ts
•• t he user interface for each program processing level is a different
organi zation block or f u nction bloc k.
You can pro gra m all basic proc es sin g l ev el s a t the same time in a
CP U 928B. T h e l ev e ls are ca ll ed by th e syst em program acco rd in g to
t he de fault priority (see Secti on 4.2).
4.5.1
Cyclic Prog ram Executio n Most functions of a program mable controller involve cyclic progra m
execution (CYCLE pr og ram proc es sing level). This cycle is known
as a "free cycle" , i.e. after reaching the end of the program, the next
cycle i s execut ed imm e diately ( see Fig. 4-6 ).
Triggering
If th e CPU complet es th e rest art pro gra m withou t errors, it beg i ns
cyclic program execution.
RUN Mode
CPU 928B Programming Guide
4 - 28 C79000-B8576-C898-01
Principle
The system program activ ities are as follows:
User interface: OB 1 or FB 0
The system program calls organization block OB 1 or f unction block
FB 0 as the user interface regularly during cyclic progra m execut ion.
T he system program processes the STEP 5 user program in OB 1 or
F B 0 fr o m the b egi nn ing thr ou gh the vario us b loc k calls you have
program med. Following the system activities, the CPU starts again
with t he first STEP 5 state ment in OB 1 (or in FB 0).
In OB 1, you program the calls f or program, function and sequence
blo cks that a re t o be proc essed i n your cyc li c prog ram.
from restart
triggers the cycle time monitoring
updates the IPC flag inputs
updates the process input image
(PII)
calls the cyclic user program (OB 1
or FB 0)
User program
the other
basic processing levels
including nesting of
outputs the process output image
(PIQ)
updates IPC flag outputs
system activities, e.g.
loading or clearing blocks,
compressing blocks. . .
Fig. 4- 6 Cy clic pr ogram e xec uti on
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If you have a short time-critical user program in which you do not
requ ire struct u re d programmi ng , th en program FB 0. Since you use
th e to t al STEP 5 operatio n se t in t hi s bl oc k, you do n ot requi re bloc k
call s a nd can reduce the runti me o f you r program.
Note
If both OB 1 an d F B 0 are program med, only OB 1 is ca lled by
the system program . If y ou use FB 0 as the user interface, it must
not contain para meters.
Interrupt points
Cyclic program e xecution ca n be interrupted at block boundaries by
t he fo ll ow in g:
•• process interrupt-driven program execution,
•• clos ed loop controller pr oce ssing,
•• time-driven progra m execution.
Note
You can prog ram DX 0 to e n able t he se int erruptio n s t o oc cu r at
operation boundaries (see C hapter 7).
Cyclic program e xecution ca n be interrupted at op eration boundaries
or aborted completely as follows:
•• i f a de vice or pr ogram error occurs,
•• by operator interventi on (PG fu nction, stop switch, MP-STP),
•• by the STOP operation.
ACCUs as data storage
T he arithmetic registers ACCU 1, 2, 3 and 4 of the CPU 928B can be
used as data s tor age outs ide the cycle (fro m the end of on e program
cycle to the beginning of the next).
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4.5.2
Time-Dri ven P rog ram
Execution Time -drive n pro c ess in g o cc urs whe n a ti me si gna l fro m a c lo ck o r
int ernal clo ck pu lse prompts the CPU to i nterrupt t he c urrent pro gram
and execute a specific program. After executing this program, the
CPU return s t o the poi n t a t whi ch t h e prev i ous pro gra m was
i nterrupte d an d continues execution. This way, particular progra m
se ct ion s c an be insert ed a uto ma ti ca ll y in t o th e cycl ic program at a
speci fied ti me.
Yo u can trig g er tim e-driv en pro gram ex ec ut io n i n di f fe rent ways, as
follows:
•• One-off triggering after a freely selectable delay time in the
millisecond range, a "d elay in te r rup t" (DELAY INTER RUPT
prog ra m proce ssing le ve l). Th e OB 6 organ i za ti on bloc k is ca ll ed
vi a th is in terrupt.
•• Triggering using a freely selected time base or once only at an
abso lu te t im e, a "cl oc k-driv e n time in t errupt " (pro g ram proce ssing
leve l TIMED JOB ). Th i s i nt erru pt c al ls org ani za ti on bloc k OB 9.
•• Trig gering in 9 different time bases with a range fro m 10 ms to 5
seconds by "t im e in terrupts" (program processi ng levels TIME
INTERRUPTS). An organizatio n block (OB 10 to OB 18) is
ass ig ned t o ea ch t ime inte rru pt. Thes e h a ve a fixed c y cle, i.e . t he
time between t wo program starts is fixed.
Delay interrupt (from
Versi on -3UB12)
Small tim e intervals with a resolution of 1 m s can also be specified
with the dela y interrupt of the CPU 928B. Wh en the set ti me has
elapsed, t he syst em prog ram calls OB 6 once.
Resolution
A delay interrupt is gener ated by cal ling the special function
org a niza ti o n block OB 153 (see Secti o n 6.12). A s soo n as th e de la y
time parameterized wi th OB 153 has elapsed, the system program
int errupts the c urren t program ex e cuti o n an d ca ll s OB 6. Aft er t h is,
prog ram exe cu ti o n is resu me d at t he i nt erru pt poin t.
User interface O B 6
In the ca se of a d el ay i n te rru pt, OB 6 is ca ll ed a s the u se r in te rf a ce . I n
OB 6 you store a S TEP 5 program to be ex ecuted in this ca se. If OB 6
has not been lo ad e d, program ex e cuti o n wil l n ot be i nt erru pt ed.
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Interruptions
With the def ault setting, the TIMED INTERRUPTS level has the
highest priority of the basic le vels (can be modi fied b y changing the
parameter assign ment in DX 0).
In timed-con t ro l le d prog ra m exec u ti on , the servic in g of th e d el ayed
i nterrupt has high est priority.
O wing to t he distributi on of priorities, the processing of the dela ye d
i nterrupt cannot be interrupted by any other user program.
Special feat ur es
•• A delayed interrupt is only processed in the RUN m ode. Delayed
int er rupts owi ng in the STOP mode, du rin g pow er down or
ST ART-UP are discarded.
•• A generated delay ed alarm (= OB 153 call was processed) is not
retained in the transition to the STOP mode and during POWER
OFF.
•• If yo u generate a n ew de lay ed i nterrupt, i.e. call OB 15 3 with
new para meters, a pre vio usl y set del aye d inter ru pt is can celled.
A delayed in ter ru pt c urren tly be ing proc es s ed is continu ed.
This means th at o nly one delayed in terrupt i s val id a t an y o ne
time.
•• I f a d ela yed int errupt o cc urs withou t th e previ ous one bei n g
completely processed, the new interrupt is discarded. Delayed
interrupts are not checked for collision s!
•• Note the special functions OB 122 and OB 142 with which you
can di sabl e or de la y th e serv ic in g o f d el ayed i n te rru pts.
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Clock-driven time interrupts
The CPU 928B has a battery -backed clock (central back-up via the
pow e r sup ply o f th e cent ral co ntro ll er), wh i ch yo u ca n set a nd read
out using a STEP 5 program. Using this clock, you can execute a
program section time-driven.
Whil e th e de la y in t errupt is u sed for h ig h-s peed jo bs , the c lock -d riven
time interrupt is especially suitable for processing one-off jobs or jobs
occurring cyclically at large time intervals s uch as hou r ly, daily or
eve ry M onday. Whe n th e set t ime is reached , t he system pro gra m
calls OB 9.
Triggering
A cl ock-driven ti me interr upt (timed job) is ge nerat ed b y calli ng the
special func tion organiza tion bloc k OB 151 (see Sec tion 6.10). Once
the time transf erred to OB 151 (time of day , date) has been reached,
t he timed job is processed. This can be programmed to o ccur once
(abso lut e t ime) o r be repea te d (t ime ba se ). Once a job becomes due
for proce ssing, th e syste m pro gra m in te r rupts th e current pro g ram and
calls OB 9 (program processing level TIMED JOB). Followi ng this,
the progra m is resumed at the poi nt at which it was in terrupte d.
Example:
You wa nt t o trig ger a time i nter rupt a t th e
55th s econ d ever y mi nu te.
Settin g us in g OB 151 :
SECONDS: 55
JOB TYPE: 1 (every min ut e)
min
5’55 6’55 7’55
Call OB 9 Call OB 9 Call OB 9
Generate
(call OB 151)
clock-driven
time interrupt
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User interface: O B 9
OB 9 is called as the user interface for a clock-driven time i nterrupt.
You store a STEP 5 program in OB 9 that is to be processed whenever
it is called. If you do not lo ad OB 9, program ex ecution is not
interrupted.
Interruptions
Th e ex e cuti on of a c lock -co ntro ll ed t ime in ter rupt ca n be int errupt ed
at block boundaries, or operat ion boundaries ( if se lect ed in DX 0 ) b y
t he fo ll ow in g:
•• proce s si ng of a pr oc ess int err upt
•• proces si ng of a del ay i nterrup t
•• pro c es sing of a clos ed loop control ler inter rup t.
The proce s si ng c an be interrupted at operation boundaries or aborted
completely by the followin g:
•• the occurrence of a hardware fault or program error,
•• operator intervention (PG fun ction, stop switc h, MP-STP),
•• t he stop operation.
Special features
•• A clock-driven tim e interrupt is only processed in the RUN mode.
Clo ck-drive n ti me i nterrupts t h at occ ur in the STOP mode, whe n
t he power has failed or durin g RESTART are discarded provi ding
the trig g er time did n ot o cc ur du ring ST OP (see a bov e).
•• A clock-driven time interrupt generated following OVERALL
RESET and COLD RESTART (= OB 151 call) is retained during
a WAR M RESTART and follo wing POWER OFF/POWER ON,
prov idin g t he t ri gge r ti me d id n ot occu r d uri ng STOP (se e above ).
•• If you generate a ne w cl ock-controlled time interrupt, i.e. yo u call
OB 151 with new timer values, an already existing clock-driven
time int errupt is can ce ll ed . A cur ren tly acti ve clock -driv en
interrupt is continued. Only one clo ck-driven time interrupt is ever
val id at on e time .
•• If a clo c k-d riv en t ime in te r rupt oc curs wh e n a previ ou s
cloc k-d riv e n ti me in terrupt has not been proce ssed o r not been
completel y pro cessed , the new time int errupt is discard ed.
Clock-driven time interrupts are not checked for collisions.
•• Yo u ca n us e th e s pecial functio ns OB 120 a nd OB 122, t o d isable
or delay the processing of clock-driven tim e interrupts.
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TIME INTERRUPTS
Program execution in fixed time bases
In the CPU 928B , yo u ca n exec u te u p to 9 d if f ere nt t im e-driv en
programs, each program being called at a di fferent time interval.
Triggering
A time interrupt is triggered automatically at a fixed ti me interval i f
th e correspo n di n g OB is progra mmed.
User interfaces
When a part icul ar t ime in te r rupt occu rs, the co r respond i ng
organization block is activated as the user interface at the next block
bounda ry (or operatio n boun dary).
Assignment of the time interru p t tim e to the OBs:
T i me base O rgan ization block called
10 ms
20 ms
50 ms
100 ms
200 ms
500 ms
1 sec
2 sec
5 sec
O B 10
O B 11
O B 12
O B 13
O B 14
O B 15
O B 16
O B 17
O B 18
Fallin g priority
For exa mple, program the program section to be inserted into the
cyclic progr am every 1 00 ms in OB 13.
Note
OBs with shorter time bases have a hi gher priority and can
i nterrupt OBs wit h lo nger ti me bases.
T ime since last interrupt
processed
Whenever a time interrupt OB is called (OB 10 to OB 18) ACCU 1
contains the number of time units that have occurred since the last
time i nt errupt OB c al l, as fol lows:
ACCU 1 := number of tim e units - 1
If, f or exam ple, ACCU 1 contains the number "5" when OB 11 is
ca ll ed, th is mean s th at 120 ms (6 t ime un i ts) have e la ps ed sin ce
OB 11 was last called. As long as there is no collision of time
i nterrupts, a "0 " is trans ferred in ACCU 1.
T able 4-3 A ssi g n ment "Time inter rupt tim e - called OB"
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Interrupt points
Time -drive n prog ram ex e cuti o n ca n be i nterrupted e it h er a t block
boundaries (default) or at op eration boundaries (programm ed in
DX 0) by t he foll owing:
•• pr oces sing of a p r ocess interrupt
•• proces si ng of a del ay i nterrup t
•• pro c e ssing of a closed loop con tr olle r in ter rup t
•• renewed processing o f a tim e interrupt
Proc es sin g c an be inte r rupted at operat io n bound aries or aborted
completely by the followin g:
•• the occurrence of a hardware fault or program error
•• operator intervention (PG fun ction, stop switc h, MP-STP)
•• t he stop operation STP.
Note
Time -drive n prog ram ex e cuti o n ca nn ot be i nt erru pt ed by t he
same time interrupt (collision of time interrupts).
Collision of time interrupts
(WECK-FE)
If a tim e inte r rupt OB has n o t yet been c ompletely proce ssed an d is
called a second time, a collision occurs. A time interrupt collision als o
occ urs if a n OB is ca ll ed a seco nd ti me an d t he first c al l h a s n o t be en
proc essed. T h is is possible wh en t he t im e inte r rupts can only int errupt
the cyclic program at block lim its, particularly if your STEP 5
program contains blocks with long runtimes.
If a collisi on of time interrupts o ccurs, th e erro r pro g ra m pro cessin g
level WE CK-FE is act iv ate d and the sy stem program calls OB 33 as
t he user interface. In OB 33, yo u can program a specific reaction to
t his problem.
If OB 33 is not loaded, the CPU goes into Stop if an error occurs.
Then WECK-FE is indicated on the programmer in the control bits
"Output ISTAC K" scree n. The level ID of th e relevant ti me interrupt
(L EVEL) is indicated in the ISTACK.
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When the system program calls OB 33, it transfers addition al
i nformation to AC CU 1 and AC CU 2 whic h provides more de tail
about the f irst error to occur.
Er ror identifier Explanation
ACCU-1-
LACCU-2-
L
1001H
1001H
1001H
1001H
1001H
1001H
1001H
1001H
1001H
001H
0014H
0010H
0010H
000EH
000CH
000AH
0008H
0006H
Collision of tim e interrupts with OB 10 ( 10 ms)
Collision of tim e interrupts with OB 11 ( 20 ms)
Collision of tim e interrupts with OB 12 ( 50 ms)
Co llisi o n of time inte r rupts wit h OB 13 (100 ms )
Co llisi o n of time inte r rupts wit h OB 14 (200 ms )
Co llisi o n of time inte r rupts wit h OB 15 (500 ms )
Collision of tim e interrupts with OB 16 ( 1 sec)
Collision of tim e interrupts with OB 17 ( 2 sec)
Collision of tim e interrupts with OB 18 ( 5 sec)
T he identi fier in AC CU-2-L is th e le ve l id entifier (see Section 5.3) of
t he time in terrupt which caused the error.
Continuing program
execution
If you require the program to continue i f a collision of time interrupts
occ urs, ei th er prog ra m th e bl o ck end state me nt "BE" in OB 33 or
change t he defa ul t in DX 0 s o th at t he prog ra m is continued if a
c ollision occurs and OB 33 is not programmed.
Aft er OB 3 3 is processed , the progr a m is cont inued from t he po int at
which it w as in terrupted .
Table 4-4 Collision of ti me interrupt identifiers
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Note
With respect to time-driven program execution, remember the
spec ia l funct ion s OB 120, OB 121, OB 122 and OB 12 3 with
which you ca n disable or dela y the processing of time interrupts
for a partic ul ar progra m sec ti on. (T his is possible e it he r for all
progra mmed time interrupts or for individual time in terrupts.)
T he "faster " a ti me-driven program processing level is, the greater
t he danger of time interrupt collisio ns. If you have time in terrupts
wit h sho rt t ime ba ses (e.g . the 10 ms an d th e 20 ms tim e
i nterrupts) it is normally necessary to select interrupti on at
ope ratio n boun d arie s. Th is me an s that t he c lo sed lo op con troller
i nterrupt and the process interrupt must also be set t o interrupt at
operatio n bou nd arie s (see Ch a pt er 7, Assigni ng Param et ers to
DX 0).
4.5.3
CLOSED LOOP
CONT ROLLER INTERRUPT:
Pro cessin g Clo sed Lo op
Controllers
In the CPU 928B , a pa rt fro m c y cl ic , t ime a n d proce ss in te r rupt
prog ra m e xe cution, i t is al so p os sible t o p r oces s clos ed loop
co n tro ll ers. Yo u selec t in te rva ls (= sam pl ing t ime) at w hi ch t he c ycli c
or time-driven program execution is interrupted and the controller is
pro c ess ed . F ollo win g t hi s, the CPU re turns t o th e poi nt a t w hich t he
cyclic or ti me-driven program was interrupted and contin ues
execution.
Triggering
A closed loop controller interrupt is triggered whe n the sa mpling ti me
yo u have sel ecte d elapses.
System program activities
•• I t manages th e user int erfa ce for clo se d lo op co ntroller p roc essing.
•• It upd at es th e co n tro ller proces s i ma ge.
User interface: standard
function block "closed loop
controller structure R64"
Wh en proces sing a contro l ler, the R64 standard fun ction block is
called as the user interf ace. In conjunction with the controller
parameter assignment block DB 2, this allows up to 64 controllers to
be processed.
You ass ig n a spec if ic d at a block for each c ont ro l ler. I n da ta bloc k DB
2 , known as th e "contr oll er list" you spe cify which controller s are to
be processed by the system program at which point in tim e. DB 2 is
reserved for this task.
( When assignin g parameters, starti ng up and testing th e R64 stand ard
FB, yo u are su ppo rte d by a spe ci al program packa ge: "COM REG" ,
see Catalog ST 59.)
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Interrupt points
Closed loop control processin g can be interrupted either at block
boundaries (default) or at op eration boundaries (programm ed in
DX 0), by the fo llowin g:
•• pr ocessing of a pr ocess interrupt,
•• proces si ng of a del ay i nterrup t.
Processing can be i nterrupted at operation boundaries or ab o r t ed
completely by the followin g:
•• the occurrence of a hardware fault or program error,
•• operator intervention (PG fun ction, stop switc h, MP-STP),
•• t he stop operation STP.
4.5.4
PROCESS INT ERRUPT:
Interr up t-Driven P rog ram
Execution
Interrupt-dri ve n program ex e cuti on in v olv es the S5 bus sig nal o f an
interrupt-capable digi tal input module (e.g. 6ES5 432-4UAxx) or a
suitable IP module that causes the CPU to interrupt program
execution and to process a specific program section. On completion of
t his program, the CPU returns to the point at which exec ution was
i nterrupted an d continues from there.
The evaluation of a process interrupt can be triggered either by a
signal level or signal edge. You can write a program to either disable,
delay or enable t he interrupt. OB 2 can interrupt the current pr ogram
either at operation or block boundaries (when you program DX 0).
Triggering
T he active state of a n interrupt line o n the S5 bus triggers the process
int errupt. De pen di ng on t h e s lo t in t he rack , e ac h CPU is ass ign ed on e
of the interrupt lines (f or more detailed inf ormation, refer to Chapter 4
in the System Manual).
User interface O B 2
When a process interrupt occurs, OB 2 is called as the user inter face.
In OB 2, you pro gra m a speci fi c prog ram to be pro ce sse d if a proc es s
i nterrupt occurs.
If OB 2 is not programme d, the cyclic program is no t interrupted. No
in t errupt-drive n pro g ram exec u ti on t ak es place .
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Interrupt points
Process interrupt-driven progra m execution can only be interrupted by
t he fo ll ow in g:
•• a program or dev ice error (at operation boundaries)
•• operator intervention (PG fun ction, stop switch, MP-STP),
•• t he stop operation.
Note
Interrupt-dri ve n program ex e cuti on canno t be i nterrupt ed by
time-driven p rogr a m e xecutio n or b y a further process
interrupt.
M ultiple int e rrupts
If further proce ss in te r rupts occ ur du rin g the int errupt-drive n prog ra m
execution, these are ignored unti l OB 2 has been com pletely
processed (including all the blocks called in OB 2).
Th e C PU the n retu rn s t o th e point o f int erruptio n and e xecut es th e
program until the next block boundary. Only then is a new process
i nterrupt accepted and OB 2 called again. This means that a
permanently active interrupt cannot totally block cyclic program
e xec ution. (This is not the case if you selected process interrupts at
operation boundaries in DX 0.)
Note
Multiple interrupts are not detected.
OB 2 can also be calle d when the signal state of the interrupt line
is passiv e ag ain wh en t he blo c k bounda ry is reac hed.
E dge-triggered process in terrupts occ urring during th e execution
of OB 2 and remaining active f or a shorter time than OB 2 are not
detected (if level triggered).
The signal state of the interrupt signal between its becoming
acti v e a nd th e completio n o f OB 2 (BE o peratio n ) is irrelev ant .
Process interrupt signal
In the defaul t (DX 0), the process in terrupt signal for the CPU 928B is
level-triggered. i.e. the active state of the interrupt line sets a request
whic h ca us es OB 2 to be pro ce ssed at t he n ext block or o perat io n
boundary (de pen din g o n th e setting of DX 0).
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A process interrupt is also recognized and processed when the
i nterrupt signal is no lo nger acti ve when the block bounda ry is
reached.
When i t is called, OB 2 is pr oces s ed com p letely. If the in ter r u p t sign al
is still active or active once again at the end of OB 2, a block is
proc essed i n th e cycl ic prog ram and OB 2 is t hen c al le d ag ai n . If th e
level is no longer active, OB 2 is only called again at the next change
of signal state (from inactive to active).
Active interrupt signal states before processin g the blo ck end
ope ration (BE ) o f OB 2 are irrelev an t.
Process interrupt signal:
edge-triggered
You can selec t this sett in g by assig nin g parameters to DX 0. Aft er
OB 2 has been processed, a new process interrupt can only be
t riggere d by a signal state change (fr om inac tive to active). After
processing the block end command (BE) of OB 2 an "inactive-active
signal change" of th e inter rupt sign al must follow to generate a
process interrupt.
A process interrupt is also recognized and processed when the
interrupt is no longer active at the block boundary.
OB 2 OB 2 OB 2
Cycle
(at block boundaries)
Process interrupt
Interrupt
OB 2
active
inactive
= block boundaries
line
F i g . 4 -7 Proce ss inte rrupt, level t rigg ered
OB 2 OB 2
Cycle
(at block boundaries)
Process interrupts
Interrupt inactive
active
= block boundaries
OB 2
line
Fig. 4-8 Process interrupt , e dge-triggered
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Disabling interrupt-driven
processing
T he s ystem progra m i nserts an interrupt-driven program into the
cyclic program at a block boundar y or at a STEP 5 operation
boundary.
An interruption of t his t ype can h ave a negative effect i f a cycl ic
prog ram sect io n h as to be proce ssed with in a spec ifi c t ime (e.g . t o
achieve a specific response ti me) or if a sequence of operations should
not be inte r rupted (e.g. whe n readi n g or w riti ng rela te d valu e s).
If a section of the user program should not be interrupted by
in t errupt-drive n pro ce ssin g, you c an use t he foll ow i n g pro gra m
procedures:
•• Program this sectio n so that it does not co ntain a block change and
retai n the default in DX 0 (process interrupts at block li mits).
Program sections that do not contain block changes cannot be
interrupted.
•• Program the disable process interrupts (IA) operation. Enable
in te r rupt pro cessing wit h th e enable i n terru pts (RA) o peratio n . No
process interrupt driven progra m execution can take place between
t hese two opera ti ons.
I A and RA are only allowed in function bloc ks (supplementar y
ope ratio n set ) .
•• You can use the special functions OB 120 and OB 122 to disable
or de la y th e proce ssi n g of pro ce ss in terru pts for a particu lar
prog ram secti on.
4.5.5
Nested Interrupt-Driven and
Time-Dri ven P rog ram
Execution
Priorit ies f or interrupt and
tim e-driven program e xecution
If a process interrupt occurs during time controlled program
e xecution , the program is interrupted at the next interrupt point (block
or operation bounda ry) and th e proce ss in terrupt is proce ssed.
Following this, the ti me-controlle d program is completed.
If a t im e inte rrupt oc curs du rin g in t errupt -driv e n pro g ram exec u ti on ,
t he interrupt-driven program e xecutio n is completed first before the
time -driven program ex e cu ti o n is started.
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If a process interrupt and a tim e interrupt occur simultaneously the
process interrupt is processe d first at the nex t interrupt point. After
this is co mpleted , the pending time interrupt is then processed.
Fig. 4-9 is a schematic representation of how program execution is
i nterrupted at block boundaries b y ti me-controlle d and
program-con trolled interrupt processi ng.
cyclic
OB 1 PB Interrupt point at which
interrupt or time-driven
program execution can
normally be inserted
into cyclic, interrupt or
time-driven program
execution. Time-driven
program execution can
only be interrupted by
a process interrupt and
not vice-versa.
interrupt-driven
OB 2
time-driven
OB 9/OB 13
Fig. 4-9 Interrupt- dri ven program execution at bl ock boundari es
4
RUN Mode
CPU 928B Programming G uide
C79000-B8576-C898-01 4 - 43
Response time
Th e respon se time to a time i n te rrupt reque st cor respond s to t he
processing time of a block or a STEP 5 operation (depending on the
sele ct ed preset). If, however, proces s i nt erru pts a re sti ll in t he qu eue
when cyclic program e xecutio n is interrupted, the time-driven
program is only processe d after all pendi ng process in terrupts have
bee n completel y pro ce sse d .
The maximu m response time between the occurrence and processing
of a tim e inte r rupt is th en increased by t he proce ssing t im e of t h e
proc ess in t errupt s. I f yo u wan t to e xc lud e as fa r as possible t h e c han ce
of a collision for a particular time interr upt OB xy, remember the
followi ng rules:
A + B + C< D where A = th e su m of t he processin g t imes of
all high er priority program
processing levels (process,
con tro ll er, t im e inte r rupt OBs )
B = processing time of the time
inte r rupt OB xy
C = runtime of the longest block of all
l ower priority processi ng l evels
D = time base of the tim e interrupt
OB xy
Note
If you run your program not only cyclically but also tim e and
i nterrupt-driven, yo u run the risk of overwriting flags.
This can occur if you use flags as intermediate flags both in the
cyclic and i n the inserted time-driven or interrupt-driven
programs an d the cyclic program is interrupted b y a time or
in t errupt-driv e n pro g ram.
For this reason, save the signal states of the f lags in a data block
at th e beginnin g of time or interrupt-driv en program execution
and r ewr ite t hem into th e ( doubly as s ig ned) f lags a t the e nd of t he
interrupt.
Four spe cial o rga n izat io n block s are avai la ble for t h is purpos e:
OB 190 and OB 192 "transf er f lags to data block" and OB 191
and 19 3 "transfer da ta field s to flag area" (refer to the rel eva nt
section).
To avoid double assignment of f lags, you can also use the S-f lags
for most applications. Special "saving procedures" for flag s are
the n no l o nge r nece ssary (th ere are eno ugh S fl ag s a v ai la ble).
RUN Mode
CPU 928B Programming Guide
4 - 44 C79000-B8576-C898-01
Contents of Chapter 5
5.1 Frequent Errors in the User Program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 4
5.2 Error Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 5
5 .3 Control B its and In terrupt S tack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 1 0
5.3.1 Co ntrol bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 11
5.3.2 ISTACK Content. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 18
Ex planation of the ISTAC K s cre en . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 1 9
5.3.3 Example of Error Diagnosis usin g the ISTACK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 25
5.4 Error Handlin g using Orga nization Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 29
5.5 Errors durin g RESTAR T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 32
5.5.1 DB0- FE (DB 0 Errors). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 33
5.5.2 DB1- FE (DB 1 Errors). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 34
5.5.3 DB2- FE (DB 2 Errors). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 35
5.5.4 DX0-FE (DX 0 or DX 2 Err ors) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 36
5.6 Errors in RUN and in RESTART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 38
5.6.1 BC F (Operation C ode Errors) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 40
Substitu ti on error (OB 27) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 40
O per a tion cod e er ror (OB 29). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 4 1
Parameter error (OB 30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 42
5.6.2 LZF (Ru nti me Errors) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 43
LZF - calling a block that is n ot loaded (OB 19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 43
Load/transfer error (OB 32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 44
Other runtime errors(OB 31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 45
5.6.3 AD F (Addressin g Error). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 53
5
5
Interrupt and Error Handling
CPU 928B Programm ing Guide
C79000-B8576-C898-01 5 - 1
5.6.4 QVZ (T imeou t Error) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 53
QV Z during direct acce ss via the S5 bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 5 3
QVZ during PII update and transfer o f the IPC flags . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 54
5.6.5 ZYK (Cycle Time Exc eeded Error). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 56
5.6.6 WECK-FE (C ollision of Time Interrupts). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 57
5.6.7 REG-FE (Cont r oller Error) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 5 8
5.6.8 ABB R (Abort). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 60
5.6.9 Communi cation Errors (FE-3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 61
Contents
CPU 928B Programming Guid e
5 - 2 C79000-B8576-C898-01
5Interrupt and Error Handling
This chapter explains how to avoid errors when planning and
programming your S TEP 5 programs.
You will see what help you can get from the syste m progra m for
diagnosing and reacting to errors and which blocks you can use to
program reacti ons to errors. 5
CPU 928B Programming G uide
C79000-B8576-C898-01 5 - 3
5.5 Frequent Errors in the User Program
T he s yste m program can detect fau lty operatio n of th e CPU, errors in
the system program processing or the effect of user errors i n the
program.
This section contains a list of errors most likely to occur when you
first run your user program.
You can av o id t hese errors ea si ly by rem em be rin g th e follo wi ng
points when you write your STEP 5 program:
•• When s pe ci fyi ng byt e a ddresses fo r I/ Os, ma ke su re that t he
cor re spo nd i ng mo dul es are pl u gge d into t h e c ent ra l con tro ll er or
th e ex pansion u n it.
•• Ma ke sure that yo u have provided correct parameters for all
operands.
•• Ma ke sure that ou tputs, flags, timers and cou nters are not
processed at di fferen t poi nts in the program with operations tha t
counteract each other.
•• Make sure that all data blocks called in the program exist and are
long en oug h.
•• Check that all blocks called are actually in the m em ory.
•• Be careful when changing existing f unction blocks. Check that the
FBs /F Xs are assig n ed t he c orrect ope ran ds and t hat the ac tual
operands are speci fie d.
•• Ma ke sure that timers are scanned only once per cycle (e. g. A T1).
•• Make sure that scratchpad f lags (intermediate flags) are saved by
i nterrupt and time-driven programs and are loaded again o n
com p letion of the inser ted p r og r am whe n they ar e req uired by
oth er blo c ks (e.g. stan da rd FBs ).
Frequent Errors in the U ser Program
CPU 928B Programming Guide
5 - 4 C79000-B8576-C898-01
5.6 Err or Infor m a tio n
If an error occurs during system start-up or durin g cyclic execution of
your program, there are variou s so u rce s o f inf orm at ion t o he lp yo u
find the prob lem , a s foll ow s:
•• L E Ds on the front p ane l of the CPU
•• ISTACK in terrupt stack and co ntrol bits
•• sy stem data RS 3, RS 4 and RS 80
•• error identi fiers in ACCU 1 and ACCU 2
•• BSTACK block stack
The f ollowing sections describe how to evaluate the information
provided by these sources and how to use the error information to
analyze a problem.
LEDs on the Front Panel of
the CPU
If the CPU goes o v er to the STOP mo de wh en yo u d o no t w an t it t o,
check th e LEDs o n the fron t panel. They can indicate the cause of t he
problem.
LE D display M eanin g
STOP LED lit continu ously The various states o f
the STOP LED indicate
specific causes of
interrupt ions and errors
(see section 4.1).
S TOP LED fl ashe s slowly
S TOP LED fl ashe s quic kl y
ADF LED lit continuously Addressing error
QVZ LED lit continuously Timeout error
ZYK LED lit c on tinuously Cycle t im e exce ed ed er ror
5
Error Information
CPU 928B Programming G uide
C79000-B8576-C898-01 5 - 5
OUTPUT ISTACK
program mer online functio n
You can get inform ation about the status of the control bits and the
contents of the interrupt stack (= ISTACK) using the ISTACK
program mer on lin e funct ion.
When the CPU goes over to the STOP mo de, the s yste m program
e nters the following i nformation in the ISTACK. This information is
required for a warm restart:
•• register contents
•• accumulator contents
•• STEP 5 ad dress counter SAC
and
•• condi tion codes
These entries can be very helpful f or error diagnosis.
Bef ore the actual ISTACK is output on the programmer, the status of
the control bits is display ed . T h e control bit s mark the current
operating status and certain characteristics of the CPU and the user
progra m and provide ad ditio nal information on the cause of an error.
Yo u can us e t h e "Ou t put I STA C K" func ti o n in t he STOP, RESTAR T
and RUN modes; however, in RESTART and RUN you only get
information via the control bits and not via the contents of the
ISTACK.
The meaning of the control bits and the structure of the interrupt stack
are described in more d etail in Sectio n 5.3.
System data RS 3 and RS 4
If your CPU returns to the stop m ode owing to an error during the
RESTART, the cause of the error is def ined in greater detail in the
system data words RS 3 an d RS 4 (see Sect ion 5.5). These involve
erro rs d et ec te d by the sys te m program w h e n it sets up th e a d dre ss lis t
in DB 0 or evaluates DB 1, DB 2, DX 0 or DX 2.
Error Information
CPU 928B Programming Guide
5 - 6 C79000-B8576-C898-01
The tw o d a ta words are sto red at th e fol lo win g a bs ol u te m e mo ry
addresses:
sy stem data word RS 3: KH = EA03
sy stem data word RS 4: KH = EA04
T he error identi fier in system data word RS 3 tells you what type of
error has oc cu r re d .
Syst em data wor d RS 4 tells you where the error has occurred.
Th e error id ent ifie rs are i n th e KH d at a fo rma t.
Analyzing system data w o rds
RS 3 and RS 4 on the
programmer
Using the online function INFO ADDRESS (KH = EA03 or EA04)
you can read out the contents of the two system data words directly
a nd discover th e cause of t he error.
System dat a RS 80
If the system program detects a serious system error, it sets the control
bit INF i n the interrupt stac k (see Section 5.3) and en ters a n ad ditional
erro r iden t ifie r in t h e da ta format KH i n syste m data w ord RS 80.
The sys tem da ta wor d RS 80 h as the ab s olut e memory addr e ss
KH = EA 50. You can read it out in the same way as the sy stem data
RS 3 and RS 4.
Er ror identifiers in ACCU 1
and ACCU 2
If errors occu r i n the STEP 5 program exe cuti on in RESTART or in
the CYCLE for which there is a particular organization block as user
int erf ac e, the syste m prog ram auto m at ic ally e nt ers add it ion al erro r
inf orm at ion i n th e accu mul at ors ACC U 1 a n d ACC U 2 w h e n th e
organization block is called. These entries also def ine the cause of the
error more e x actl y (s ee Sectio n 5. 6).
T he error ide nti fier in ACCU 1 tells you what type of error has
occurred.
T he error identifier in ACCU 2 (if entered) tells you where th e error
occurred.
Th e error id ent ifie rs are i n th e KH d at a fo rma t.
5
Error Information
CPU 928B Programming G uide
C79000-B8576-C898-01 5 - 7
Analysis of ACCU 1 and
ACCU 2 on the program m e r
Usin g the onl ine functi on OUTPUT IST ACK, you can read the
contents o f the two accumulators directly out of the ISTACK to find
out the exac t cause of the error.
Analysis of ACCU 1 and
ACCU 2 with STEP 5
Sinc e t he e rror ide nti fiers are wri tten to AC CU 1 and A C CU 2
autom atically when an error organization block is called, y ou can take
the se id ent ifie rs int o acco un t whe n you prog ram yo ur e r ror OB.
Th i s a ll ow s you t o prog ram spec ific reac ti on s to v ari ous errors in your
organ ization bloc k depen din g on the err or iden ti fier trans ferrred to it.
OUTPUT BSTACK onlin e
function
T he PG online function OUTPUT BSTACK gives you infor mation in
STOP abo ut t he c on t en ts o f th e block st ac k (BST AC K - see
Sec ti o n 3.2 "Nesting bloc ks" ).
Starting f rom OB 1 or FB 0, the BSTACK contains a list of all blocks
ca ll ed i n se qu e nce an d n ot c omple te ly processed w he n the CPU wen t
int o the STOP mode . Sin ce th e B STAC K i s fil le d from th e bot to m ,
t he block on th e uppermost level of t he BS TACK display co ntains the
block that was last processed an d in which t he error occurred.
BSTACK information
The top lin e contain s the foll ow i ng information:
Information Meaning
BLOCK N O T ype and number o f the block that called th e
faulty block
BLOCK AD DR Absolute start address of the calling block in
the program me mory
RETURN ADDR Absolute address of the first STEP 5 operation
of this b lock i n th e us er mem o ry.
REL A DDR Relative address (= difference "RETU RN
ADDR - BLOC K AD D R") of the ne xt
ope rat ion to be pro ces sed in th e callin g bloc k.
(You can disp lay relati ve a ddress es on a
pro gramm er in the mode "disable i nput"/k ey
swi tch an d with S 5-DOS f ro m Sta ge I V
upwards using the functi on key "addresses ").
DB NO Nu mb e r of th e last data bl oc k op ene d in t he
calling block
DB ADDR Absolute start address in the program memory
of the last data block opened in the calling
bloc k (ad dress of da ta w ord DW 0)
Error Information
CPU 928B Programming Guide
5 - 8 C79000-B8576-C898-01
Ex a mple:
Evaluating the BSTACK function:
BLOCK NO BLOC K ADDR RETURN ADDR REL ADDR DB NO DB ADDR
O B 23
FB 5
FB 6
OB 1
0063
006A
008A
009D
0064
0072
0091
009E
0001
0008
0007
0001
13
13
100
0078
078
098
In th e ex am ple abov e, the s topp age oc curr ed i n OB 2 3 wh en pro ce ssin g th e
STEP 5 statement at the absolute memory address "0064 - 1 = 0063".
OB 23 (QV Z erro r OB ) was ca lled in FB 5 a t th e rela tive a ddre ss "00 08 -
1 = 0007".
The data block DB 100 was opened in FB 6. When the CPU went into the
stop mode, data block DB 13 was valid.
Data bloc k DB 1 3 wa s open ed in FB 5 .
5
Error Information
CPU 928B Programming G uide
C79000-B8576-C898-01 5 - 9
5.7 C ontro l B its a nd Inter ru pt S ta ck
Using the PL C INFO and OUTPUT ISTACK online programmer
functions, y ou can analyze the operating status, the characteristics of
the CPU and the user program and any possible causes of errors and
interruptions.
Note
You can di splay the control bits in any mo d e. Yo u can di splay
the ISTACK only in the STOP mode .
•• The contro l bits in dic at e t he c u rre nt a nd previ ous ope rati n g sta tu s
and t he cause of the problem.
If seve ral er rors oc curre d , the control bits indicat e all of t hem.
•• The ISTACK indicates the location of the interruption (addresses)
with the current condition codes, the accumulator contents and the
cause of the proble m.
If seve ral error s occurred, a multiple level in te rrupt stack i s
constructed as follows:
depth 01 = last cause of problem,
depth 02 = next to last cause of problem etc.
If an ISTACK overf low occurs (more than 13 entries) the CPU
go e s i nt o th e STOP mod e i mm edi at el y. If this h appen s, yo u mus t
perform a POWER OFF/POWER ON and a cold restart.
T he meanings of the indivi dual abbreviations in the con trol bits and in
t he IST ACK are described below.
Note
The text on the screen of your programmer depends on the PG
soft ware used . It ma y differ from the screen represented here.
Nevertheless, the description of the individual positions on the
screen in these programming instructions is valid.
Co ntrol B its and Inte rrupt Stack
CPU 928B Programming Guide
5 - 10 C79000-B8576-C898-01
5.7.1
Co ntro l Bits When you display the IST ACK on the PG the statuses of the control
bit s a re sh ow n o n th e first scre en pag e (see F i g. 5-1).
The co n trol bi ts (>>STP<<, >> ANL< < a n d >>RUN<<) a n d the
c ontrol bits in the first lines of the first screen page mark the current
or pre vi ous status o f the CPU an d prov ide in f o rmatio n a bou t ce rtai n
fea tures of t h e CPU an d you r STE P 5 program.
You ca n di splay th e co ntrol bits in a ll mod e s. Yo u c an , fo r exa mple,
make sure that organization block OB 2 is loaded and that interrupt
control program execution is possible at any tim e.
CONTROL BITS
>>STP<< STP-6
ANL-6
RUN-6 EINPROZ BARB OB1GEL FB0GEL OBPROZA OBWECKA
ANL-2 NEUZU MWA-ZULNEUSTA
X
XX
XXX
X
XX
MWA AWA
FE-STP BARBEND PG-STP STP-SCH STP-BEF MP-STP
>>ANL<<
>>RUN<<
32KWRAM 16KWRAM
URL-IA
FE-22
FE-6 FE-5 FE-4 FE-3 L Z F REG-FE DOPP-FE
PEU BAU ZYK QVZ ADF WECK-FESTUE-FE
MOF-FE RAM-FE DB0-FE DB1-FE DB2-FE KOR-FE
STP-VER ANL-ABB UA-PG UA-SYS UA-PRFE UA-SCH
8KWRAM KM-AUS KM-EIN DIG-EIN DIG-AUSEPROM
URGELOE
DX0-FE
NAU
BCF
Fig. 5-1 Examp le of the first screen f orm page "OUTPUT IST ACK" : control bits
5
Co ntrol Bi ts and Inter rupt Stack
CPU 928B Programming G uide
C79000-B8576-C898-01 5 - 11
The f ollowing tables explain the m eaning of the individual bits.
>>STP<< line (CONTRO L BITS)
Control bit M eanin g
»STP« CPU is in t he STOP m o d e
STP-6 N o t used
FE-STP Error stop: st op mode cause d b y NAU (power failure),
PEU (peri phe rals n ot read y), BAU (ba ttery n ot rea d y),
STUE B (BST ACK ov e rf low), STUEU (IST AC K
ov e rfl ow ), DOPP (dou ble ca ll e rro r) or CPU fa ul t
BARBEND Program test end: stop mode a fter PROGRAM TEST
END online function (COLD RESTART required)
Is not set if the END PROGRAM TEST f unction was
exec u te d wit h th e CPU in t he ST OP m o de.
PG-STP PG -STOP: sto p mod e d ue t o comm an d from PG
STP-SCH STOP s w it ch: stop mod e due t o mode s el ec to r in
posi tio n STOP
STP-BEF Stop operation:
-stop mode caused by STEP 5 operation "STP "
-stop m ode after stop c ommand from system
program, if error
-organi zati on bl ock is not pr ogr ammed
MP-STP Multiprocessor STOP:
-re set sw i tc h o n th e co o rdi nato r i n STOP po si tion or
-different CPU in the STOP mode in multiprocessing
Table 5-1 Meaning of the control bits in the >>STP<< l ine
Co ntrol B its and Inte rrupt Stack
CPU 928B Programming Guide
5 - 12 C79000-B8576-C898-01
>>ANL<< line (CON TROL BITS)
Control bit M eanin g
»ANL« CPU is in t he REST A R T mo de
ANL-6
+
MWA R ETENTIVE MANUAL CO LD RESTART
ANL-6
+
AWA RETENTIVE AUTOMATIC CO LD RESTART
NEUSTA MANUAL CO LD RESTAR T requested (STOP) or
was la st RE STA R T type (R E STA RT/R UN )
M W A MANUA L WA RM RESTAR T requested (ST OP) or
was la st RE STA R T type (R E STA RT/R UN )
A W A AUTOMATIC WAR M RESTART after power failure
is requeste d (STOP) or was last RESTART type
(RESTART/RUN)
MWA
+
AWA
AUTOMATIC CO LD RESTART was requested
(STOP) or was la st RESTA RT type
(RESTART/RUN)
ANL-2 Double function:
- is set after PROGRAM TEST END (in contrast to
BARBEND in the first line, it is also set wh en
PROG RAM T EST END is ca ll ed i n th e STOP
mode; prevents WARM RESTART)
- is se t a f te r "co mpressing i n th e STOP mo de" ;
preven ts WAR M REST ART
NEUZU C OLD RESTART permitted (STOP) or COLD
RESTART was permitted when the last RESTART
took place (RESTART/ RUN)
MWA-ZUL MA NUA L WARM RESTART permitt ed (STO P) or
COLD RESTART was pe rmitte d wh en the la st
R ES T ART t ook place (R ESTART/RUN)
Table 5-2 Meaning of the control bits in the >>ANL<< line
5
Co ntrol Bi ts and Inter rupt Stack
CPU 928B Programming G uide
C79000-B8576-C898-01 5 - 13
>>RUN<< line (CONTRO L BITS)
Control bit M eanin g
»RUN« CPU is in t he R UN mod e (cycl ic processin g i s a ct iv e)
RUN-6 N ot us ed
EINPROZ Si ngle pr oces sor mod e
BARB PROG R A M T EST on li ne fu nc tion is active
OB1GEL Organization block OB 1 is loaded in the user mem ory.
Cyclic p rogram executi on is dete rmine d by O B 1
FB0GEL Function block FB 0 i s loaded in the us er mem o ry.
Cyclic progr am execution is dete rmined by FB 0 if no
OB 1 is loaded. If FB 0 and OB 1 are both loaded, OB
1 determines the cyclic program executio n
OBPROZA Process i nterrupt organiz at ion block OB 2 is loade d,
i.e. process interrupt-driven program execution is
possible
OBWECK Time interrupt organ ization bloc k loade d, i.e.
ti me -drive n pro g ram ex ec ution i s po ssible
Lines 4 and 5 (CONTRO L BITS )
C ontrol bit M eaning
32KWRAM User memory submodule is a RAM with 32 x 210
words
16KWRAM User memory submodule is a RAM with 16 x 210
words
8KWRAM User memory submodule is a RAM with 8 x 210
words
EPROM User m e m o ry su bmo d ule is an E PROM
KM-AUS Address list for IPC f lag outputs from DB 1 exists
KM-EIN Address list for IPC f lag inputs from DB 1 exists
DIG-EIN Address list for digital inputs exists
Tabl e 5-3 Mea ni ng of t he c o ntr ol bits in t he > >RUN<< li ne
Table 5-4 Meaning of the control bits in l ines 4 and 5
Co ntrol B its and Inte rrupt Stack
CPU 928B Programming Guide
5 - 14 C79000-B8576-C898-01
Lines 4 and 5 (CONTRO L BITS )
C ontrol bit M eaning
DIG-AUS Address list for digital outputs exists
T able 5-4 continued:
URGELOE Overall reset pe rfo rm e d o n CPU (COLD R ESTART
required)
URL-IA Overall reset being performed on CPU
STP-VER CPU caused CP stop
ANL-ABB RESTART aborted (CO LD RESTART required)
UA-PG P G has requested OVERALL RESET
UA-SYS System program has requested OVER ALL RESET (no
RESTART possible); OVER ALL RESET must be
performed
UA-PRFE OVE RAL L RESET reques te d ow i ng to C PU erro r
UA-SCH OVERA L L RE SET requeste d at h ard ware sw itch :
perform an OVERALL RESET or select a restart
type if you do not want to perform the requested
OVERALL RESET
T he control bits in the following table indicate errors that ca n occur in
the RESTART (e.g. during an initial COL D RESTART) and RUN
(e.g . during tim e-driv en program e xe cu t io n) mod es.
If sev e ral errors oc cur, all causes of in terrupti ons that have occurred
up to n ow (and have no t yet bee n proce ssed ) are di splay ed i n the last
three lines of the control bits. See also system data word RS 2, th is
co n tain s th e IC MK (i nt erru pt c ondit ion c od e grou p wo rd, 16 bi ts), in
which al l e r rors no t yet pro cesse d are also e ntered (Se ction 8.3.5).
5
Co ntrol Bi ts and Inter rupt Stack
CPU 928B Programming G uide
C79000-B8576-C898-01 5 - 15
Lines 6 to 8 (CONTRO L BITS)
C ontrol bit M eaning
DX0-FE Param e te r assign m e n t e r ro r in DX 0 o r DX 2
FE-22 Not used
MOD-FE Error in contents of user sub module (OVERALL
RESET required )
RAM-FE Error in content s of sys tem prog ram RA M
or of DB R AM (OVERALL RESET required)
DB0-FE Structure of block address lists in DB 0 inc orrect
DB1-FE Structur e of the address lis ts in DB 1 for proc ess
ima ge upda tin g is incorrec t:
- DB 1 not programmed and coordinator
plu gged in or multiprocessor operation
required
- st ructure or c ontents of DB 1 incorr ect
DB2-FE Error evaluating the parameter assignment data block
DB 2 of controller structure R64
KOR-FE Error in da ta exchange wi th the coor dina tor
NAU Power failure in the central controller
PEU Peripherals not ready = power failure in expansion
unit
BAU Battery not ready = back-up battery failure in central
controller
STUE-FE Interrupt or block stack overf low (nesting depth too
great; COL D RESTART required)
ZYK Cy cle monit or ing time exceede d
QVZ Tim eout during data exchange with I/Os
ADF Ad dre ssi n g error w i th i n put s o r o ut put s:
error caused by accessing the process
ima g e, in w h ic h I /O mo dul es w ere add re sse d
that were not plugged in, def ect or not
specified in DB 1 at the last COLD RESTART
Table 5-5 Meaning of the control bits in l ines 6 to 8
Co ntrol B its and Inte rrupt Stack
CPU 928B Programming Guide
5 - 16 C79000-B8576-C898-01
Lines 6 to 8 (CONTRO L BITS)
C ontrol bit M eaning
WECK-FE Collision of t ime interrupts:
an attempt was made to call a particular ti me
in te rru pt OB a se co nd ti me wh il e or be fore fi rst
call was processed
T able 5-5 continued:
BCF Operation cod e error:
- substitution error: processed STEP 5 operation
cannot be substituted
- operation cod e error: processed STEP 5 operation
is incorr ect
- parameter error: parameter of the processed
STEP 5 ope ratio n is in co rrec t
FE-6 Not used
FE-5 Indicates a serious sys tem err or, additional
information in RS 80
FE-4 Power down error:
processing of a previous power failure (NAU)
b y the s ystem program did not run correctly;
WARM RES TART i s t her ef o re not pos s ib le
FE-3 Interface error (SS F)
LZF R unt ime error:
- called block not loaded
- load/transf er error with data blocks
- other runtime errors
REG-FE Error processing the controller structure R64
in th e CYCLE
DOPP-FE Do u ble call error:
a sti ll a ct ive error progr am proce ssing l eve l
(ADF, BCF, LZF, QVZ, REG, ZYK ) is
activated a second time (COL D RESTART
required)
5
Co ntrol Bi ts and Inter rupt Stack
CPU 928B Programming G uide
C79000-B8576-C898-01 5 - 17
5.7.2
ISTACK Con tent I f th e CPU is in t he st o p sta te , you ca n d isplay the c on t ent of the
ISTACK on the scree n after t he control bit display by pressing th e
enter key. When the CPU goes into the STOP m ode, the system
progra m enters all the in formatio n it needs in th is ISTACK for a
war m restart.
Yo u can us e t h e e n tries in th i s I STA C K t o see w h a t ki nd o f e rro r
occ urred a n d where it occu rred i n the pro gra m.
If the stop state was caused by a single error, onl y one le vel of the
ISTACK in formatio n is displayed. With several errors, the
corresponding number of ISTACK levels are output (DEPTH 01,
DEPTH 02, etc.). At all levels, only one error is marked as the
CAUSE OF INTE RRUPT.
If sev e ra l errors ha v e oc cu rre d DEPTH 01 m a rks th e erro r de te ct ed
imm ed iately b efor e the ch ange to the s to p st ate.
Fi g 5-2 is an exa mple of a PG display of the ISTAC K cont en t.
INTERRUPT STACK
DEPTH 02
OP-REG: SAC: 00F3 DB-ADD:
DB-NO.:
DBL-REG.: OB-NO.:
BA-ADD:0000
0000
0000
0000
C70A
0002 FB-NO.:
REL-SAC:
ICMK: ICRW:
0006
0200
226
0004
KE1 KE2 KE3111 100 111
BLK-STP:
LEVEL:
ACCU1: ACCU2: ACCU3: ACCU4:0000 C464 0000 00FF 0000 0000 0000 0000
KLAMMERN:
CONDITION CODE: CC1 CC0 OVFL OVFLS ODER
STATUS
NAU PEU
STP BCF S-6 LZF REG-FE
BAU MPSTP ZYK QVZ
VKE
CAUSE OF INTERR.:
ADF
X
X
X
X
STUEB STUEU WECK DOPP
ERAB
Fig. 5-2 Examp le of a screen page "OUTPUT ISTAC K"
Co ntrol B its and Inte rrupt Stack
CPU 928B Programming Guide
5 - 18 C79000-B8576-C898-01
Explanation of the ISTACK
screen
DEPTH
Inf ormation level of the ISTACK when more than one error has
occurred:
DEPTH 01 = last cause of stop to occur
D EPT H 0 2 = next to la st ca use of s top to occu r
......
DEPTH13 = ...... (maximum d epth)
Inform ati on about the error
The fo llowi ng table conta in s info rmation ab out t he IST AC K ID s with
which th e stateme nt i n the u ser pro gra m c an be fou nd wh ich ca us ed
t he CPU to change to the STOP mode.
Infor ma tio n about the error
ISTACK ID Meaning
OP-REG Operation reg ister:
Cont ains machi ne code ( first word) of th e
instruction processed last in an interrupted
program processin g level (see list of
operations, list of machine codes).
BLK-STP Bl ock stack pointer:
contains th e number of elemen ts entered
in the block stack at the tim e when
th e inter r upt ion of this p r oces s ing level
occurred
L EVEL Z Specifi es th e le ve l of progra m proce ssing t h at w as
interrupted
Z : 0002: C OLD RES TART
0004: CYCLE
0006: TI ME INTERRUPT / 5 sec (OB 18)
0008: TI ME INTERRUPT / 2 sec (OB 17)
000A : TI ME INTER RUPT / 1 s ec (OB 16)
000C: TIME INTER RUPT / 500 ms (OB 15)
000E: TI ME INT ERR UPT / 200 m s (OB 14)
0010: TI ME INTERRUPT / 100 ms (OB 13)
0012: TI ME INTERRUPT / 50 ms (OB 12)
0014: TI ME INTERRUPT / 20 ms (OB 11)
0016: TI ME INTERRUPT / 10 ms (OB 10)
0018: TI MED JOB
Tabl e 5-6 Meaning of the ISTA CK I Ds concerning the poi nt of error
5
Co ntrol Bi ts and Inter rupt Stack
CPU 928B Programming G uide
C79000-B8576-C898-01 5 - 19
Infor ma tio n about the error
ISTACK ID Meaning
T able 5-6 continued:
L EVEL Z
(continued) Z: 001A: n ot used
001C: CL CONTRO LLER
INTERRUPT
001E: not use d
0020: D ELAY INTERRUPT
0022: n ot use d
0024: PROCESS INTERRUPT
0026: n ot use d
0028: R ET ENT IV E MAN UAL C O LD
RESTART
002A: R ETENTIVE AUTOMATIC CO LD
RESTART
002C: transiti o n to sto p mo d e af ter stop
i n mu lt ip ro ce s si ng,
stop switch or PG STOP
002E: inter face error
0030: c ol lision of t ime interrupts
0032: CL co ntroll er error
0034: cycle error
0036: n ot use d
0038: ope ration co de error
003A: r untime error
003C: addre ssin g error
003E: timeout
0040: n ot use d
0042: n ot use d
0044: MAN UAL WAR M
RESTART
0046: AUTOMATI C WAR M
RESTART
SAC STEP address counter:
- co nta ins th e absolute a ddress of the last
operation of an i nterrupted program
processing level to be processed in the
program m em ory
- if an error occurs, SAC indicates the operation
that caused it.
- before th e first ope rati on of a proces sin g
level is executed, SAC is set to "0"
Co ntrol B its and Inte rrupt Stack
CPU 928B Programming Guide
5 - 20 C79000-B8576-C898-01
Infor ma tio n about the error
ISTACK ID Meaning
...NO. Block type and number of the last block
processed
T able 5-6 continued:
REL-SAC Rela tive S TEP address counter :
contains the relative ad d ress (rela ted t o
the bl ock s tart addres s) of t he l ast
operation to be e xecute d in the last block
processe d (you can display relative
address es on a program mer using th e
PG mode "i nput disabl e"/key-s witch
or wit h S5-DOS from sta ge IV usi ng
a function ke y or you ca n output th e
block on a printer)
ICMK I nter rup t condition co de group wo rd :
ICM K indicat es al l the c auses of int er ruptio ns
that ha ve occurred up to now and have
no t yet been c o mplete ly proce ssed (s ee
"Sys tem Data M emo ry Assign men t",
Section 8.3.5)
ICRW Interrupt condition code reset word (see "Sy stem
Data Me mory Assignment ", (Section 8.3.5)
DB-ADD Absolute start address o f the data block opened last
in the program memory (DW 0)
(DB-ADD = 0000, if no DB was opened)
DB-NO. Number of the data block opened last
DBL-REG Length of the data b lock open ed la s t
BA-ADD Absolute address in the p rog ram me mory of the
operatio n t o be proc es sed next i n th e block last
called
...No. Block type and number of the block last
called
5
Co ntrol Bi ts and Inter rupt Stack
CPU 928B Programming G uide
C79000-B8576-C898-01 5 - 21
Infor ma tio n about the error
ISTACK ID Meaning
ACCU 1...4 Co nten t s of th e ca lc u la ti on regi st ers a t the ti me of
interruption:
in the even t of ce rtai n erro rs , t he syst em prog ram
writes error ide ntifiers into
ACCUs 1 and 2 when the interruption occurs.
These identi fiers define the ca use of the
interruption more exactl y
T able 5-6 continued:
BRACKETS Nu mber of brac k et ed levels:
"KEx abc"
x = 1 to 7 levels
a = OR (OR see condition code bits)
b = RLO (result of logic operation, see
condition co de bits)
c = 1: A(
c = 0: O(
Condition code
see Section 3.5
Cause of interrupt
The followin g abbreviations (IST ACK IDs) represent the most
import an t caus es of inte rru ptions.
The only caus es of interruptio ns tha t are ma rked are th ose th at have
occurred in the currently displayed program processing le vel (see
LEVEL).
T he causes of interruptions represent the contents of the interrupt
condit ion co de group word (ICM K, 16 bi ts , see Section 8.3.5). Some
of the entries here are identical to those in the control bits.
Cause of interrupt
ISTACK
ID Meaning (called error OB)
NAU Power sup ply failur e in centra l con tr olle r
PEU Peripherals not ready = power failure in expansion unit
Tabl e 5-7 ISTACK I Ds cause of interrupt
Co ntrol B its and Inte rrupt Stack
CPU 928B Programming Guide
5 - 22 C79000-B8576-C898-01
Cause of interrupt
ISTACK
ID Meaning (called error OB)
BAU Batter y not ready = back-up batter y fail ure (central
controller)
MPSTP Multiprocessor STOP:
- reset switch on the coordinator in STOP position or
- STOP at a different CPU in multiprocessor
operation
T able 5-7 continued:
ZYK Cycle monitoring tim e exceeded
QVZ Tim eout during data exchange with I/O peripherals
ADF Add ress ing erro r for i nputs and ou tpu ts wit h pro ce ss
I/O image
STP - s top mode caused by s etting the s top switch to
STOP
- stop mod e cau sed by c omm a n d fro m PG
- stop mode after processing the STEP 5 operation
"STP"
- stop mode after stop command from system program,
if error organization block is not programmed
BCF Ope ra ti on co d e e rror: error de te ct ed d uri ng th e
operation decoding
- substitution error: processed STEP 5 operat ion
cannot be substituted
- ope rati on cod e e rror: pro ce ssed STE P 5 operat ion
is in co rrect
param eter error: parameter of the processed
STEP 5 operation is not permitted
S-6 In ter fa ce er ror
LZF Runtime error: error detected during the executi on
of a n operation:
- calle d b l ock not l oaded
- load/transfer error with data blocks
- other runtime errors
5
Co ntrol Bi ts and Inter rupt Stack
CPU 928B Programming G uide
C79000-B8576-C898-01 5 - 23
Cause of interrupt
ISTACK
ID Meaning (called error OB)
REG-FE Er ror proc essing the cont ro l ler stru ct u re R64 in the
CYCLE
STUEB Block stack overflow:
nesting depth too great; required
measu re: COLD RE STAR T )
STUEU Interrupt stack overf low:
nesting depth too great; required
measu re: COLD RE STAR T )
T able 5-7 continued:
WECK Collision of time interrupts:
before or d uring the processing of a time
interrupt OB, an attem pt was m ade to
call the same OB a second tim e
DOPP Double call error
a still act ive error progra m processing level
(A DF, BCF, LZF , Q VZ, RE G , ZYK) i s
activated a second tim e (COL D RESTART
required)
Co ntrol B its and Inte rrupt Stack
CPU 928B Programming Guide
5 - 24 C79000-B8576-C898-01
5.7.3
Exam p le of Err or Diagno sis
usin g the ISTA C K
Ex ample 1:
Fig. 5- 3 il lustrate s th e struct ure of t he I STACK in conjunc tion with th e
interru ptio ns that have occurre d.
- Die Programmbearbeitungsebene ZYKLUS (OB 1) w ird unte rb roch en d ur ch
das Auftreten eines Interrupts.
- Following this, the program processing level TIME INTERRUPT is
activated and OB 13 i s pr oc esse d.
- The TIME INTERRU PT l evel is exited o wing to the occurren ce o f a proc ess
inte rrup t, the P ROCE SS INTER RUPT lev el i s activa ted and OB 2 is
processed.
- An incorrect addressing operation activates level ADF where OB 25 is
processed. In the error handling program, the user has programmed a
sto p op er atio n (S TP ); t he CPU abo rt s pr ogra m exec utio n.
Before the CPU finally goes into the stop mode, a total of four
differ ent pr ogra m pr oc essi ng lev els ha ve b een in terr upte d. If yo u
displa y th e ISTA CK, yo u ob ta in a four level IS TACK , fi rst th e ISTA CK
with d epth 0 1, i n wh ic h th e iden tifi er of the pr ogra m pr oc essi ng lev el
last interrupted (=ADF) is marked. You can now "page down" through the
ISTACK until you reach the ISTACK with depth 04, that represents the
CYCLE prog ra m pr oces si ng l ev el, that w as i nter ru pted first.
OB13
Depth 01
OB2
OB1
CYCLE
ADF OB25
Program processing levels ISTACK
Level: 003C
Depth 02
Level: 0024
ADF
x
Depth 03
Level: 0010
Depth 04
Level: 0004
STP
STP
x
TIME
INTERRUPT
INTERRUPT
PROCESS
F ig . 5 -3 Exampl e 1 of evalu a t in g the ISTACK
5
Co ntrol Bi ts and Inter rupt Stack
CPU 928B Programming G uide
C79000-B8576-C898-01 5 - 25
Ex ample 2:
In this example the CPU dete cts an addre ssing error when executi ng the
"A I x.y " op eration in O B 1. Thi s leads to t he proce ssing of OB 25. As a
result o f an STP ope rati on in PB 5, the CPU goes int o the ST OP m ode (see
Fig. 5-4 ).
Continued on next page
CYCLE
ADF
JU PB 5
OB 25 0100
0105
0106
PB 5
STP
1000
1007
ADF
AIx.y
OB 1 0010
001A
CDB16
Fig. 5-4 Example 2 of evaluati ng the ISTACK
Co ntrol B its and Inte rrupt Stack
CPU 928B Programming Guide
5 - 26 C79000-B8576-C898-01
Continuation 1 of Example 2:
Two interrupted program execution levels lead to the creation of a
two-level ISTACK (see Figs 5-5 and 5-6):
Continued on the next page
INTERRUPT STACK
DEPTH 01
SAC: 1007 DB-ADD:
DB-NO.:
DBL-REG.: OB-NO.:
BA-ADD:
0000
0106
2516
0003 PB-NO.:
REL-SAC:
ICMK: ICRW:
0007
0300
5
003C
BLK-STP:
LEVEL:
ACCU1:
CONDITION CODE:...
CAUSE OF INTERR.:
STP
X
OP-REG: STP
Fig. 5-5 Exampl e 2 of evaluati ng the ISTACK: 1st ISTACK l evel
5
Co ntrol Bi ts and Inter rupt Stack
CPU 928B Programming G uide
C79000-B8576-C898-01 5 - 27
Continuation 2 of Example 2:
INTERRUPT STACK
DEPTH 02
SAC: 001A DB-ADD:
DB-NO.:
DBL-REG.:
BA-ADD:
0000
0000
0001 OB-NO.:
REL-SAC:
ICMK: ICRW:
000A
0200
116
0004
BLK-STP:
LEVEL:
ACCU1:
CONDITION CODE:...
CAUSE OF INTERR.:
ADF
X
OP-REG: AIx.y
Fig. 5-6 Exampl e 2 of evaluati ng the ISTACK: 2nd I STA CK level
Co ntrol B its and Inte rrupt Stack
CPU 928B Programming Guide
5 - 28 C79000-B8576-C898-01
5.4 Err or H an dlin g us ing Org an iza tio n B lo ck s
When the system program detects an error, it calls the appropria te
organization block to handle it. You can determine how the CPU
r e acts by prog r ammi ng the r elev an t or ganiza tion bloc k.
Depen din g on how yo u program the organizati on block, you ca n
achieve the f ollowing reactions:
•• nor mal program processing is c ontinued
•• the CPU goes to the STOP mode
and/or
•• a spec ia l e r ror han d li ng pro gra m is run t hro ugh .
Organization blocks exist for the following causes of errors:
Cause of error O rganization
block calle d Reaction of CPU
if OB is not
programmed 1)
Call o f a bl ock t hat is not lo a ded (LZ F) OB 19 STOP
Timeout in the user program during access to I/O
modules (QVZ) O B 23 none
Timeout during update of the process image and during transfer of
IPC flags (QVZ) O B 24 none
Ad dressing error (AD F) OB 25 STOP
Cycle time exceeded (ZY K) OB 26 STOP
Substitution error (SUF) OB 27 STOP
Mode selector set to STOP, PG functi on PC STOP,
STOP from S5 bus (multiprocessor operation) OB 28 STOP
Operation code error (BCF) OB 29 STOP
Parameter error (BCF) OB 30 STOP
Other runtime errors ( LZF) OB 31 STOP
Load /transfer error with data blo ck s (TRA F ) OB 32 STOP
C ollision of time in terrupts (WECK-FE) OB 33 STOP
Table 5-8 The organizati on blocks called in case of errors
5
Error H andling using Organiz ation B locks
CPU 928B Programming G uide
C79000-B8576-C898-01 5 - 29
Cause of error O rganization
block calle d Reaction of CPU
if OB is not
programmed 1)
Tabl e 5-8 c on tin ued :
Error processing the controller struct ure R64 (REG-FE) OB 34 STOP
C ommunication error on the 2nd serial inter face (FE-3) OB 35 no ne
1) with DX 0 de faults
Response of organization
block not loaded
If the organization block is n ot loaded the response depen ds o n the
particular error:
No int erruption of cyclic
program execution
If a tim eout occurs and OB 23, OB 24 or OB 35 is not loaded, cyclic
program execu tion is not interrupted. The CPU does not react.
If you want the CPU to go into the STOP mode when a timeout
occ urs, th e organi zati o n bl ock must c o ntai n a sto p st at ement and be
completed with the block end statem ent BE or DX 0 m ust have
suitable parameters assigned.
Program for STOP:
:
:
:STP
:BE
STOP mode
When any other error occurs, the CPU goes into th e STOP mode
i mmedi ately if you did not pr ogram the appropriate organization
blocks.
If, in exceptional circumstances, (e.g. during s ystem installation) you
do no t w ant one o f th e se errors to i nterrupt c ycli c pro g ram ex ec u tion,
a blo ck e nd s ta tement i n the appropriate orga nizati on blo ck i s
sufficient or assign suitable parameters to DX 0.
Program for uninterrupted operation:
:
:
:BE
Note
Organi zati on block OB 28 is an exception: here, the CPU al ways
goe s to the STOP mo de reg a rd l ess o f whe th e r you h av e lo a de d
OB 28 or not.
Error H andling using Organiz ation B locks
CPU 928B Programming Gu ide
5 - 30 C79000-B8576-C898-01
If you do not want to program the corresponding organization block,
you can prevent the transition to the STOP mod e b y assigning
appropriate paramet ers t o data block D X 0.
Interruptio n s during
processing of error
organiz at ion bl ocks
After the sy stem program calls the appropriate organization block, the
user program in that block is processed.
If another error occurs while the first organization block is being
processed , t he progra m i s interrupted at the next ope ration boundary
and the ap propr iate second org an izati on bloc k is ca lled, just as in
cyclic program execution.
The organization blocks are processed in the order in which they are
call ed . Th e nestin g d epth fo r erro r organ i za tion bl oc ks d epend s on t h e
following:
•• T he type of error
No organization blocks belonging to the same program processing
leve l can be nes ted withi n ea ch o the r. (See C hapter 6 for th e
assignment of error OBs to the program processin g level).
When proc es sin g OB 27 (pro g ram pro cessing le ve l BC F) it i s, for
example, possible t o nest OB 32 (program processing level LZF),
h owever, OB 29 or OB 30 (also BCF) cann ot be nested in OB 27.
If t w o block s fro m the same pro gra m pro ce ssi n g leve l are ca ll ed,
the CPU ch ang es im me d ia te ly to the STOP mode .
•• T he nu mb er of prog ram proc essing levels currently active a t
any on e time
For each activated program processing level, the system program
requi res ex tra me mo ry space to se t up t h e ISTA CK when an
in te r rupt occurs. If th ere is no t eno ugh memory l eft, a n IST AC K
over flow r esults .
If t h ere is an ISTAC K o v erflo w, the CPU ch ang es im me d ia te ly t o
the STOP mo de .
•• T he n umb er of blocks called at any one tim e
If th ere is a B ST A CK ove rf l ow, th e C PU cha ng e s i mm ed ia te ly to
the STOP mo de .
5
Error H andling using Organiz ation B locks
CPU 928B Programming G uide
C79000-B8576-C898-01 5 - 31
5.5 Err or s d ur ing R E START
Duri ng in it ia liza ti o n an d d uri ng a resta rt , c ause s o f i nt erru pt ion s a nd
errors can lead to the restart program bein g aborted an d put the CPU
int o the STOP mode . I n te r ruptions o cc urring d u rin g the re st art
progra m (organization blo cks OB 20, 21 and 22) are h and led just as i n
the CYCLE.
Exception: if a STOP o c curs du ri ng th e rest art, no organi za tion block
OB 28 is called.
Causes of interrupt a n d
causes of error
T her e is n o way of responding via a user interface (error OB) to t he
causes of i nterrupt a nd causes of error listed i n the table below.
C ontrol bit
or ID in
ISTACK
Explanation
STP Stop command from syste m program (at FE-STP)
or in th e us er prog ra m
BA U Fail ure o f th e ba ck-up ba ttery o n the ce ntral
controller
NAU Failure of the power supply in the central
controller
PEU Failure of the power supply in an expansion
unit
STUE U Stac k ov e rfl ow in i nt errupt st ac k (ISTAC K)
STE UB St ack ov e rf l ow in t he bloc k stack (BSTAC K )
DOPP-FE Do uble call of an e rror program processing
level
RAM-FE Error during initialization: the contents of the
operation s yste m RAM or the DB RAM are
incorrect
MOD-FE Error during initialization: the contents o f the user
s ub module (R AM or EPRO M sub modu le) are not
correct
DB0-FE 1) Error setting up the block address list
(DB 0)
DB1-FE 1) Error evaluati ng DB 1 to set up the address list for
updating the process im age
Table 5-9 Causes of error and causes of interrupt i n RESTA RT
Errors during RESTART
CPU 928B Programming Gu ide
5 - 32 C79000-B8576-C898-01
Control bit
or ID in
ISTACK
Explanation
T able 5-9 continued:
DB2-FE 1) Error evaluating DB 2 of th e controller structure
R64
DX0-FE 1) Error evaluating data block DX 0
or
Error evaluating data block DX 2
1) for further explanations: see the following pages
5.5.1
DB0-FE (DB 0 Error s ) Errors when setti ng up the block address list (data bloc k DB 0).
DB 0 is set up by t he syste m program foll owing POWER ON. If a
DB 0 error occu rs, you wi ll fin d erro r id en t if ie rs in th e system data
words RS 3 and RS 4 that define the error in greater detail.
Er ror identifier
RS 3 RS 4 Explanation
8001Hyyyy H Wrong b l ock le ngth
yyyy = a ddre ss o f the bloc k wit h th e wrong
length
8002HyyyyH Ca lc ul at ed e n d ad dre ss of t h e bloc k in t he
memo r y is wr on g
yyyy = bl ock address
8003Hyyyy H Inva lid bl ock ide ntifi er
yyyy = addre ss o f the bloc k with th e incorrec t
identifier
8004Hyyyy H Or ga nization block number to o high
(permitted: OB 1 to OB 39)
yyyy = addre ss o f the bloc k with th e incorrec t
number
8005HyyyyH Data block nu mber 0 (perm itted: DB 1 to
DB 255)
yyyy = addre ss o f the bloc k with th e incorrec t
number
Table 5-10 IDs for DB 0 errors
5
Er rors during RES TAR T
CPU 928B Programming G uide
C79000-B8576-C898-01 5 - 33
5.5.2
DB1-FE (DB 1 Error s ) Error ev al u at ing DB 1 to set u p th e ad dre ss li st for updati n g th e
proce ss image.
•• DB 1 does not exist in multiprocessor operation,
or
•• inc orrect DB 1 ad dress li st du ring C OLD RESTA RT.
Note
I n multiprocessor operation, the system checks whether DB 1
exists in all types of restart. DB 1 parameters are, howe ver, only
evaluated during a COL D RESTART.
E r ror identifier
RS 3 RS 4 Explanation
0410H yyyyH I llegal identifier :
- h e ader identifier m i ssing or inco rr ect
(c orrect KC MASK01)
- identifier illegal (permitted K H DE00,
D A00, CE00, C A00, BB00)
- e nd id ent ifier missi n g or i nco rrect (co rrec t
KH EEEE)
yy yy = illega l identif ier
0411H yyyyH "Digital inputs" , number of addresses illegal
(permitted 0...128)
yyyy = illegal number of addresses
0412H yyyyH "Digital outputs" , number of addresses illegal
(permitted 0...128)
yyyy = illegal number of addresses
0413H yyyyH "IPC f lag inputs" , number of addresses illegal
(permitted 0...256)
yyyy = illegal number of addresses
0414H yyyyH "IPC f lag outputs", number of addresses
illegal (permitted 0...256)
yyyy = illegal number of addresses
0415H yyyyH Illegal number of ti mers
(permitted: 256)
yyyy = illegal number of ti mers
0419H yyyyH Tim eout with digital inputs
yy yy = addr e ss of the unackno w ledged
inp ut b yte
Table 5-11 ID s for DB 1 errors
Errors during RESTART
CPU 928B Programming Gu ide
5 - 34 C79000-B8576-C898-01
Er ror identifier
RS 3 RS 4 Explanation
Table 5-11 continued:
041AH yyyyH T imeo ut with digital o utput s
yyyy = address of the unackn owledged
ou tput f lag byte
041BH yyyyH Tim eout wit h IPC fl ag inpu t
yyyy = address of the unackn owledged
IPC flag byte
041CH yyyyH Tim eout wit h IPC fl ag o utput
yyyy = address of the unackn owledged
IPC flag byte
5.5.3
DB2-FE (DB 2 Error s ) Errors in the evaluation o f the parameter assignment data block DB 2
for contr oller structure R64 (con tr olle r initialization).
If a DB 2 error occurs, system data words RS 3 and RS 4 contain error
i dentifiers that define the error in greater detail.
E rror identifier
RS 3 RS 4 Explanation
0421H D ByyH Dat a b l ock not l oaded
yy = nu mber of the data block that is not
loaded
0422H FBy yH Function block not loaded
yy = number of the functio n block that is not
loaded
0423H FByyH Function block no t recog niz ed
yy = nu mber of the unrec ogn ized function
block
0424H FByyH Function block lo aded wit h wrong PG
s oftw are
yy =number of the function block
0425H D ByyH Wrong contr oller data bloc k lengt h
yy = nu mber of the data block
0426H — There is not enough memory space in the
DB- RA M t o shift the controller D Bs fro m the
user EPROM to the DB-RAM
Table 5-12 IDs for DB 2 errors
5
Er rors during RES TAR T
CPU 928B Programming G uide
C79000-B8576-C898-01 5 - 35
5.5.4
DX0-FE (DX 0 or DX 2
Errors)
Note
DX 0 and DX 2 errors have a common c ontrol bit (DX0-FE) in
the co ntrol bi t screen form .
Errors evaluating data block
DX 0
In th e even t o f a DX 0 error yo u w il l fin d error i d enti f ie rs in t h e
system data words RS 3 an d RS 4 that de fine t he error i n more detail.
E r ror identifier
RS 3 RS 4 Explanation
043 1 H yyyyH Ille gal ident ifier:
- header identifier m i ssing or in correct
(correct KC MAS KX0)
- fi eld identifier il legal
- e nd id ent ifier missi n g or i nco rrect (co rrec t
K H EEEE )
yy yy = illega l identif ier
0432H yyyy H Ille gal parameter
yyyy = illegal parameter
043 4 H yyyyH Ille gal numb er of ti mers (pe rmit te d: 0...2 56)
yyyy = incorrect nu mber of timers
043 5 H yyyyH Ille gal cycle ti me moni tor in g (permitted: 1 ms
to 13000 ms)
yyyy = incorrect t ime value
Errors evaluating data block
DX 2
Parame ter assig n ment for the second s erial inte rf ace .
Data block DX 2 is set up by the system program after a COL D
RESTART. In the event of a DX 2 error, you will f ind error identifiers
in the system data words RS 3 and RS 4 that define the error in more
detail.
E r ror identifier
RS 3 RS 4 Explanation
0451H — DX 2 length (without block header) < 4 words
is not permitted
0452H yyyy H DX 2 le ngt h ( wit hou t bl ock hea der) is too
short for link type
yyyy = length D X 2
Table 5-13 ID s for DX 0 errors
Table 5-14 ID s for DX 2 errors
Errors during RESTART
CPU 928B Programming Gu ide
5 - 36 C79000-B8576-C898-01
Er ror identifier
RS 3 RS 4 Explanation
Table 5-14 continued:
0453H yyyyH Li nk type illega l
yyyy = link type
0454 H x x00H Data id entifier for stat. parameter set illegal
(not equal to 44H, 58H)
xx = data id ent if ier
0455H xxyy H B l ock fo r st atic parameter set illegal
xx = identifier / yy = DB nu mber
0456H x xyyH S tatic parameter set does not exist
xx = identifier / yy = DB nu mber
0457 H y yyyH Static parame ter set too sho rt
yyyy = number of the non-exist ent DW
0458H xx00H Data identifier for dynamic parameter invalid
(44H, 58H, 00H)
xx H = data ident if ier
0459 H yyyyH Blo ck for dyna mic parameter set illegal
xx = identifier / yy = DB nu mber
045AH xx00H Data identifier for send/job ma ilbox invalid
(not equal to 44H, 58H, 00H)
xx = data id ent if ier
045BH x xyyH Block for se nd/job ma ilb ox i llega l
xx = identifier / yy = DB nu mber
045CH xx 00H Data identi fier for receive mailbox invalid
(not equal to 44H, 58H, 00H)
xx = data id ent if ier
045DH xx yyH Bloc k for re ce iv e mail box i lleg al
xx = identifier / yy = DB nu mber
045EH xx00H Dat a identif i er for coordination byte s invalid
(not equal t o 44H, 58H, 4DH)
xx = identifie r
045FH xxyyH Bl ock fo r coor dination bytes ille ga l
xx = identifier / yy = DB nu mber
0460 H xxyyH B l ock fo r coordination byt es does not exis t
xx = identifier / yy = DB nu mber
0461 H yyyyH D W for coor dinatio n bytes does no t exist
yyyyH = number of the non-existent DW
5
Er rors during RES TAR T
CPU 928B Programming G uide
C79000-B8576-C898-01 5 - 37
5.6 Errors in RUN and in RESTART
In the RUN mo de, cycl ic , tim e-driv en o r int errupt -driven program
execution or controller processing can be interrupted at operation
boun daries by t he o ccu rre nce of c ertai n errors or fa ul ts , e .g. power
failure in the central controller or block stack o verflow.
Interruption s d urin g ini ti aliz at ion and i n th e RE STA RT m o d e ca us e
the restart program to be aborted and the CPU goes into the STOP
mode or calls the organization block intended f or this error.
Interruptions occurring d uring the start-up progra m are handled in the
s ame way as in the CYCLE .
A distinction is made between problems that cause the CPU to go
directly to the STOP mo de (e.g. STUEU) and problems that cause the
sy stem program to call certain organization blocks that you can
prog ram in st ea d of th e CPU go i ng d i rect ly t o th e STOP mod e (e.g .
ADF).
T her e is no way of responding vi a a user in ter fa ce (err or OB) to the
causes of interrupt and causes of error listed in the table below.
Errors which lead direct to
STOP
If these errors occur, an ISTACK is created in which the interrupt is
displayed.
C ontrol bit or
ID in ISTA C K Explanation
STP STOP caused by the system program
( machine error), when an error OB is not
loaded, or there is a stop operation in the user
program
BA U Fa ilure o f th e ba ck-u p ba ttery in th e cent ral
controller
NAU Failure of the power supply to the central
controller
PEU Failure of the power supply to one or m ore
ex pan sion unit s
STUEU Stack o verflow in the interrupt stack
(IST ACK), nest ing de pth too gre at
ST UEB Stac k overflow in t he blo c k stack (BSTA C K ),
nestin g depth too great
DOPP-F E Do ubl e call o f an e rro r program processing
level
T able 5-15 Causes of error and causes of interrupt in RESTART and RUN,
w hich lea d direct t o ST OP
Errors in RUN and in RES TAR T
CPU 928B Programming Gu ide
5 - 38 C79000-B8576-C898-01
Errors- which cau se an error
O B to be call ed
C ontrol bit
or ID in
ISTACK
Explanation O B no.
BCF Operation co de error:
- s ubstit ution error
- operati on code error
- parameter error
O B 27
O B 29
O B 30
LZF Runtime error:
- call for a block t hat is not loaded
- transfer error with DBs
- ot her runtime errors
O B 19
O B 32
O B 31
ADF Addressi ng error:
- when accessing the process im age OB 25
QVZ Timeout:
- i n the user pr og ram when a ccessing
I/O modules
- when updating the proc ess imag e
O B 23
O B 24
ZYK Cycl e error
- the cycl e mon itor ing t ime w as
exceeded O B 26
WECK-FE Collision of two ti me interrupts:
- error processing a time interrupt OB 33
REG-FE Controller err or:
- error processin g a co ntroll er
interrupt OB 34
ABBR Abort:
- (see Section 5.6.8) O B 28
S-6 Comm uni cati on error:
- during data exchange via the second
serial inter face O B 35
The f ollowing sections describe each of these causes of errors in more
detail.
Tab le 5-1 6 Causes of error and causes of interrupt in RESTA RT and
RUN, which lead direct to STOP
5
Er rors in RUN and in RE ST A R T
CPU 928B Programming G uide
C79000-B8576-C898-01 5 - 39
5.6.1
BCF (Operation Code
Errors) An operati on code error occurs when the CPU either canno t in terpret
or cannot execute a STEP 5 operation in the user program . All
perm i ssible ope ratio n co d es are li st ed i n th e li st of o perati ons.
T he operation that caused the operation code error is not executed. If
the relevant BCF organizat ion b lock is loaded, this is ca lled,
processed and the user program is then continued starting with the
next operation. If the BCF-OB is not loaded, the CPU goes into the
STOP mod e.
T he following operatio n cod e errors can occur. In each case, the error
O B named is call ed:
Substitution error
(OB 27)
If an operation with a for mal operand is to be executed in a fun ction
blo ck, th e CPU repla ce s thi s form a l opera nd w i th t h e a ct ual o pe ran d
contained in the f unction block call.
The C PU recog niz es an i ll eg a l s ubstitu ti on. Th e syste m pro g ram
i nterrupts the processing of the user program and cal ls organization
block OB 27, if it is loaded.
ACCU 1 co n tain s a dditi ona l in form at io n tha t de fin es th e error i n m ore
detail.
E rror identifier
ACCU-1-LACCU-2-L Explanation
1801H — Substitution error with the DO RS
operation
1802H — Substitution error with the DO DW, DO
FW operations
1803H — Subs ti tu ti on error w i th t h e DO=, DI
operations
1804H — Subs ti tuti o n error with t he L=, T=
operations
1805H — Substit ution error wit h the A=, AN=, O=,
ON=, ==, S= and RB= operations
1806H — Subs ti tu ti on error w i th t h e R D= , LD=,
FR=, SF D=, SD=, SSU; an d SEC=
operations
Table 5-17 B CF substitution error
Errors in RUN and in RES TAR T
CPU 928B Programming Gu ide
5 - 40 C79000-B8576-C898-01
O per ation code erro r
(OB 29)
An operation code error is detected b y the CPU during the execu ti on
of a ST EP 5 program when an o perati on is programmed that doe s not
belo ng to the STEP 5 set of operati ons for the CPU 928B (e.g. RU and
SU operations can be programmed at the programmer but cannot be
i nterpreted by the CPUs 928B, 928, 922 (R pro cessor) an d 921
(S process or) i n the S5 135U).
If the CPU detects an illegal operation code, the execution o f the user
program is interrupted and organization block OB 29 is called, if it is
loaded
When OB 29 is called, ACCU 1 contains additional information that
define s th e err or in greater deta il.
E r ror identifier
ACCU-1-LACCU-2-L Explanation
1811H — Operation with illegal OP code
1812H — Ille gal OP code for an operation in which
the hig h byte of th e first opera tio n word
contain s the value 6 8H
1813H — Ille gal OP code for an operation in which
the hig h byte of th e first opera tio n word
contain s the value 7 8H
1814H — Ille gal OP code for an operation in which
the hig h byte of th e first opera tio n word
contain s the value 7 0H
1815H — Il legal OP c ode for an operatio n in which
the hig h byte of th e first opera tio n word
contain s the value 6 0H
Caution
An operation code error sh ould not be acknowledged: the CPU
does not recognize whether the inc orrect operati on is a sin gle
word o r mul tiw ord o pera ti on. Once the CPU has proce ssed
OB 29, it attempts to cont inue the program at the next operati on
word. If this is the second word of a m ultiword operation, it either
detects a further operat ion cod e error or e xe cutes this word as a
valid operation, which ca n cause a variety of program errors.
Ta ble 5- 18 BCF operation code erro r 5
Er rors in RUN and in RE ST A R T
CPU 928B Programming G uide
C79000-B8576-C898-01 5 - 41
Param eter erro r
(OB 30)
An illegal parameter occurs when an operation is programmed with a
parameter that is no t permitted for the particular CPU (e.g. calling a
reserved data blo ck), or when a non-existent special fu nctio n is called.
If the CPU dete ct s an il le g al paramet er, the system prog ra m in te r rupts
the execution of the user program and calls organization block OB 30,
if it is loaded.
When OB 30 is called, ACCU 1 contains additional information that
define s th e err or in greater deta il.
Error iden tifier
ACCU-1-LACCU-2-L Explanation
(illegal p ara m eter in...)
1821H — C D B 0, 1, 2
182BH — JU(C) OB 0
182CH — JU(C) OB > 39: special function does
not ex ist
182DH — CX DX 0, CX DX 1, CX DX 2
182EH — L F W/T FW/L PW/T PW /L OW/T
O W/L DD/T DD/DO FW 255
182FH — L IW /T IW/L QW/ T Q W 12 7
1830H — L FD/T FD 253, 254, 255
1831H — L ID/ T ID / L QD/T QD 125,
126, 127
1832H — RLD/RRD/SSD/SLD 33-255
1833H — SLW/S RW/LIR/TIR 16-255
1834H — SED/SEE 32-255
1835H — A=/AN=/O=/ON=/S=/RB=/==/
RD=/FR=/SP=/SD=/SEC=/SSU=/
SFD=/L= /LD =/LW=/ T= 0, 127-2 55
1836H — DO=/LWD= 0, 126-255
1837H — A S/O S/ S S/ =S/AN S/ON S/R S
b yte number > 1023
1838H — A S/OS/ S S/=S/A N S/ON S/ R S
bit number > 7
1839H — L SY/T SY para meter>1023
183AH — L SW/T S W parameter > 1022
T ab le 5-1 9 BC F param eter error
Errors in RUN and in RES TAR T
CPU 928B Programming Gu ide
5 - 42 C79000-B8576-C898-01
E rror identifier
ACCU-1-LACCU-2-L Explanation
(illegal parameter in...)
Table 5-19 continued:
183BH — L SD/T SD parameter >1020
183CH — G DB/ GX DX parameter 0, 1 or 2 (DB
or DX 0, 1, 2 cannot be g enerated)
5.6.2
LZF (Runtime Errors) A runti me error occurs when the CPU detects an error during the
e xecution of a STEP 5 operatio n.The operation that causes t he
runtime error is not execut ed . ( Ex ception: opening a non-existent
da ta block DB/D X) . If there i s an LZ F o rgani zation block, this is
call ed . The in ter rupte d user progra m i s t hen c ont in u ed from t he n ext
operati on after th e operation that caused th e error. If no LZF-OB is
loaded, the CPU goes to the STOP mode.
The followin g runtime errors are possible. In each case, the named
erro r OB is ca ll ed :
LZF - callin g a b lo ck that
is not loaded (OB 19 )
If a block is calle d or opened in the user program and this block does
not exist, th e s yste m program automatically detects an error. This
appli es to a ll blo c k types an d is true for c on dit io nal a nd u nco n dit ion al
calls.
If the system program detects the call or opening of a block that is not
loaded, it calls organization block OB 19, if it is loaded. In OB 19,
you can specify how the CP U should p roc eed.
If you have program med OB 19, it is called and processed f ollowing
whic h th e in ter rupte d STE P 5 program i s c ont inu ed a t t he n e xt
operation unless OB 19 contains a stop operation. If, on the other
hand , you ha v e no t pro g ramm ed OB 19, the CPU g o es int o th e STOP
mode when a block that is not loaded is called or opened.
5
Er rors in RUN and in RE ST A R T
CPU 928B Programming G uide
C79000-B8576-C898-01 5 - 43
When OB 19 is called, ACCU 1 contains additional information that
define s th e err or in greater deta il.
E r ror identifier
ACCU-1-L ACCU-2-L Explanation
1A01H — Data block not lo aded for C DB
1A02H — Data block not lo aded for CX DX
1A03H — Bl ock not l oa ded for JU(C) F B, OB 1 to
39, PB, SB
1A04H — Block no t loaded for DOU(C) FX
1A05H — Data block not l oaded for OB 254 or
255
1A06H — Data block not loaded for OB 182
1A07H — Dat a block n ot load ed fo r
OB150/OB151/OB 153
Note
If y ou attempt to open a data block that is not loaded, the DBA
register (see Chapter 9) is affected. In this case a loaded data
block m ust be opened again before accessing DB/DX data.
Load/transfer error
(OB 32)
When you transfer data to data blocks (DB, DX), the CPU compares
the length of the DB that has been opened with the operand in the
tra ns fer ope rat io n. I f the specified parame te r ex ce ed s th e ac tual d ata
blo ck l en g th , th e CPU doe s no t ex ec ut e th e tran sfe r state men t t o
prevent data in the memory from being overwritten by m istake.
T he s yste m program also detects a load/transfer error if a single bit of
a no n-existe nt data word i s t o be se t/ reset or s ca nn e d.
T he syste m program also detects a load/trans fer error if you atte mpt to
access a data word before you call a data block (using C DBn or
CX DXn).
Tabl e 5-20 LZF - calling a block that is not l oaded
Errors in RUN and in RES TAR T
CPU 928B Programming Gu ide
5 - 44 C79000-B8576-C898-01
When the system program detects a l oad/transfer error, it calls
organi zation block OB 32, if it is loaded. The operation that caused
t he transfer error is n ot e xecuted.
When OB 32 is called, ACCU 1 contains additional information that
define s th e err or in greater deta il.
Er ror identifier
ACCU-1-L ACCU-2-L Explanation
1A11H — A/AN D, O/ON D, S/R D, = D ac ce ss to
a non-defined data word
1A12H — Tran sf e r error: T DR to a non -d efine d
data word
1A13H — Transfer error: T DL to a non-defined
data word
1A14H — Tran sf e r error: T DW t o a n o n -de fin ed
data word
1A15H — Transfe r error: T DD to a no n-d efi ne d
data word
1A16H — Load error: L DR to a non-defined data
word
1A17H — Load error: L DL to a non-defined data
word
1A18H — Load error: L DW to a non-def ined data
word
1A19H — Load error: L DD to a non-def ined data
word
O ther ru ntim e erro rs
(OB 31)
These include all runtim e errors that cannot be grouped with the
previous types of runtime error (tran sfer errors or calling a bloc k that
i s not loaded) .
If the system prog ram dete ct s one of these runtime errors, it calls
organi zation block OB 31. Th e o peration (or sp ecial func tion ) t hat
caused the error is not processed any f urther. If OB 31 is not loaded,
the CPU goes into the S TOP mo de.
If you want program execution to conti nue wh en one of the errors
listed below occurs, simpl y write the block end statement BE in
O B 31.
Table 5-21 LZF-load/transfer error (TRAF)
5
Er rors in RUN and in RE ST A R T
CPU 928B Programming G uide
C79000-B8576-C898-01 5 - 45
When OB 31 is called, ACCU 1 and ACCU 2 contain additional
inf o rm ation tha t de f in es the error in greater deta il.
Error identifiers of different
operations, OB 254/255 and
O B 250
E r ror identifier
ACCU-1-L ACCU-2-L Explanation
1A21H — G DB, GX DX: data block already
exists
1A22H — G DB, GX DX: illegal nu mber of data
wor ds (< 1 or > 4091)
1A23H — G DB, GX DX: not enou g h space in
the RAM
1A25H — DI: illegal parameter in ACCU 1
(< 1 or > 125)
1A29H — Bracket stack under or overflow
followi ng A(, O(, )
1A2AH — C DB, CX DX, block length in data
blo ck h e ad e r to o sh ort
(length < 5 words)
1A2B H — Function bloc k wit h inco rrec t PG
s oft w are load e d
1A2CH — A C R : il legal pa g e n u m ber in
ACCU-1-L (> 255)
1A31 H — OB 254 or OB 255 (shift) or
OB 250:
destination data block already
exists in DB-RAM
1A32H — OB 254 or OB 255 (dupli cate):
destination data block already
exists in DB-RAM
1A33H — OB 254 or OB 255 or OB 250:
not enough space in the
DB-RAM
Ta bl e 5- 2 2 LZF-o the r runtime e rr or s/ par t 1
Errors in RUN and in RES TAR T
CPU 928B Programming Gu ide
5 - 46 C79000-B8576-C898-01
O B 182 error identif iers
Er ror identifier
ACCU-1-L ACCU-2-L Explanation
1A34H 0001H d escriptio n of th e data field
1A34H 0100H addre ss area t ype is ille gal
1A34H 0101H data bloc k num be r is ille g al
1A34H 0102H "number of the first pa ramet er word"
illegal
1A3 4H 020 0H " sou rce da ta b lock type" illegal
1A34H 0201H "source data block number" illegal
1A34H 0202H numbe r of first da ta w o rd in the sou rce
to be trans mitted illegal
1A34H 0203H length of source data block in the block
header, value < 5 words entered
1A34H 0210H "destination data block type" illegal
1A34H 0211H "d esti nati on data bloc k" number illegal
1A34H 0 212H num ber of th e first da ta wo rd in t he
destination to be transmitted illegal
1A34H 0213H l en gth o f the destination data blo ck in
the bl ock h ea d er, v a lu e < 5 w o rd s
entered
1A34H 0220H number of data words to be transmitte d
i ll eg al ( = 0 or > 4 091)
1A34H 0221H source data block too short
1A34H 0222H destination data block too short
1A34H 0223H destination data block in EPROM
Table 5-23 LZF-other runtime err ors/p art 2 (OB 182 identifier)
5
Er rors in RUN and in RE ST A R T
CPU 928B Programming G uide
C79000-B8576-C898-01 5 - 47
Error identifiers of the
diffe rent special function OBs
The table below con ta in s iden ti f ie rs of OB 110, OB 121, OB 122,
OB 221, OB 240, OB 241, OB 242 an d OB 250.
E r ror identifier
ACCU-1-L ACCU-2-L Explanation
1A35H — OB 250: nu mber of the transfer block
illegal
1A3 6H — OB 250: DB x and DB x + 1 or DX x
and DX x +1 have different
lengths
1A3AH — O B 221: illegal value for the new cycle
time (c ycle t im e < 1 ms
or > 13000 ms)
1A3BH — OB 223: different CPU start-up t ypes in
multiprocessor operation
1A41 H — OB 240, OB 241 or OB 242:
illegal shift register or data
b l ock num b er
(number < 192 or > 255)
1A4 2 H — O B 241: shift re gister not i nit ialized
1A43H — OB 240: not enough space in the
DB-RAM
1A4 4H — OB 240: data word DW 0 of the data
block does not contain ’0’
1A4 5 H — O B 240: illega l shift register l ength in
DW 1 (not between 2 and 256)
1A4 6 H — O B 240: illega l pointer posit ion or
nu mber of pointers > 5
1A4 7H — O B 120: i llegal valu e in ACCU 1 or
ACCU-2-L
1A48 H — OB 122: illega l value in ACCU 1
1A4 9H — O B 110: i llegal valu e in ACCU 1 or
ACCU-2-L
1A4A H — OB 121: il legal val ue i n A C CU 1or
ACCU-2-L
1A4 BH — OB 123: i llegal value in AC CU 1
Table 5-24 LZF-other runtime errors/part 3
Errors in RUN and in RES TAR T
CPU 928B Programming Gu ide
5 - 48 C79000-B8576-C898-01
O B 150 error identif iers
Er ror identifier
ACCU-1-L ACCU-2-L Explanation
1A4CH 0001H illegal function number (=0 or >2)
1A4C H 0100H addre ss area type illeg al
1 A4 C H 0101 H d at a b lock n umb er ill egal
1A4CH 0102H "num be r of th e fi rst da ta field word"
illegal
1A4 C H 0 10 3H data bl oc k leng th en tere d i n header
< 5 words
1A4 CH 0201H year specification in data field illegal
1A4 C H 0 20 2H m o nth s pecificatio n in data field il leg al
1A4CH 0203H day of month specification in data field
illegal
1A4CH 0204H weekda y spec. in data fie ld ill eg al
1A4CH 0205H hour spec ificati on in data fi el d
illegal
1A4 CH 0206H minute specification in da ta field
illegal
1A4 CH 0207H second specification in data field
illegal
1A4CH 0208H 1/100 seconds in data field not equal
to 0
1A4CH 0209H data field word 3 / bits 0 to 3 not equal
to 0
1A4 C H 0 20AH hour format d oes no t m a tch s ettin g in
OB 151
Table 5 -25 LZF-other runtime errors/part 4 (OB 150 identif iers)
5
Er rors in RUN and in RE ST A R T
CPU 928B Programming G uide
C79000-B8576-C898-01 5 - 49
Error identifiers of OB 151,
O B 152 and OB 15 3
E r ror identifier
ACCU-1-L ACCU-2-L Explanation
O B 151 identifiers
1A4D H 0001H f u nct i on n u m ber illegal
(= 0 or > 2)
1A4DH 0100H addre ss area type ille ga l
1A4DH 0101H data block number illegal
1A4DH 0102H number of the first data fiel d word
illegal
1A4DH 0103H data block length entered in header
< 5 words
1A4DH 0201H year speci fica tio n in d at a fiel d ille gal
1A4DH 0202H m o nth specifi cati on i n d at a fi el d il lega l
1A4DH 0203H d a y of mo nth spec. i n data fiel d il le gal
1A4D H 0204H wee kday spec ificati on in data fiel d
illegal
1A4D H 0205H hour specification in data fiel d ille gal
1A4DH 0206H m inu te spe ci fica ti on in d ata fiel d
illegal
1A4DH 0207H s ec ond spe ci fica ti on in d ata fiel d
illegal
1A4DH 0208H 1/ 100 secon ds i n da ta fie ld no t equal
to 0
1A4DH 0209H job type in d ata fiel d il legal (> 7)
1A4DH 020AH
O B 152 identifiers
1A4EH 0001H function no . ill egal (n ot 0 to 3, or 8 or
15)
O B 153 identifiers
1A4FH 0001H function no. i llegal
(=0 or <1)
1A 4FH 0002H ille gal delay t ime
Table 5-26 LZF-other runtime errors/part 5 (identifi ers of
OB 151, OB 152 and OB 153)
Errors in RUN and in RES TAR T
CPU 928B Programming Gu ide
5 - 50 C79000-B8576-C898-01
Error identifiers of different
system operat ions
Er ror identifier
ACCU-1-L ACCU-2-L Explanation
1A50H — LRW, TRW:
the calculated memory ad dress
<BR + constant> not in range
"0 - EDFFH" 1)
1A51H — LRD, TRD:
the calculated memory address
<BR + constant> not in range
"0 - EDFEH" 1)
1A 52H — TSG, LY G B , L W GW , TY GB ,
TW GW:
the calculated linear address
<BR + constant>not in range
"0 - EF FFH"
1A53H — LY GW, LW GD, TY GW, TW GD:
the calculated linear address
<BR + constant> not in range
"0 - EF FE H"
1A54 H — LY GD, TY GD:
the calculated linear address
<BR + constant> not in range
"0 - EF FCH"
1A 55H — TSC, LY CB , LW C W , TY C B ,
TW CW:
the calculated page address
<BR + constant> not in range
"F400H - FBFFH"
1A5 6H — LY CW , LW CD, TY CW , TW CD:
the calculated page addr e ss
<BR + constant> not in range
" 400H - FB FEH"
1A 57H — LY C D, TY C D:
the calculated page addr e ss
<BR + constant> not in range
"F40 0H - FBFCH"
Table 5-27 LZF-other runtime errors/part 6 (identifiers of
di f f er e n t s ystem ope r atio n s)
5
Er rors in RUN and in RE ST A R T
CPU 928B Programming G uide
C79000-B8576-C898-01 5 - 51
E r ror identifier
ACCU-1-L ACCU-2-L Explanation
Tabl e 5-27 c o ntin ued :
1A5 8H — TNW, TNB:
the source f ield is not completely in one
of the f ollowing ranges:
0000 .. 7FFF user memory 1)
8000 .. DD7F data block RAM
DD80 .. E3FF DB 0
E400 .. E7FF S flags
E8 00 .. E DFF sys tem data (RI,
RJ, RS, RT, C, T)
EE00 .. EFFF flags, process image
F000 .. FFFF peripherals
1A59H — TNW, TNB:
the destination fiel d is not completely in
one of t he f ollowin g ran ges:
0000 .. 7FFF user memory 1)
8000 .. DD7F data block RAM
DD80 .. E3FF DB 0
E400 .. E7FF S flags
E8 00 .. E DFF sys tem data (RI,
RJ, RS, RT, C, T)
EE00 .. EFFF flags, process image
F000 .. FFFF peripherals
1) see Chap. 9
Errors in RUN and in RES TAR T
CPU 928B Programming Gu ide
5 - 52 C79000-B8576-C898-01
5.6.3
ADF ( Addressing Error) An ad dres s in g erro r occu rs wh e n a ST EP 5 opera ti o n references a
proce ss i ma ge input or outp ut to which n o I/O modul e was assi gned at
the time of the last COL D RESTART (e.g. the m odule is not plugged
i n, it is defective or it is not define d in DB 1 of t he CPU).
O B 25
T he s yste m program interrupts the ex ec ution of t he user progra m an d
cal ls or gani zation block OB 25. After executing the program in
OB 25, the CPU continu es wit h the next operation of the interrupted
program . The STEP 5 statement that caused ADF was executed but
with an undefined input or output value.
If OB 25 i s n o t prog ra mm ed, the CPU goe s int o th e STOP mode wh e n
t he error o ccurs, u nless you have specifie d in data block DX 0 that the
program shou ld continu e.
T he address error monitorin g can also be co mpletely suppressed i f
yo u program DX 0 appropriat ely.
Error identifiers
Th e syst em program tra ns fers t he fo llowi ng as error id enti fie rs:
ACCU-1-L = 1E40H
ACCU-2-L = ADF address
5.6.4
Q VZ (Timeo ut Error ) A tim eout error occurs when an input or output m odule is addressed
and does not respon d wit h th e read y sig nal (RDY) wi thin a speci fic
time. The cause of the timeout m ay be a defect on the I/O module or
t he module may ha ve bee n unplugged from the PC dur in g operatio n.
Th e follow ing t im eou t errors in te rrupt th e us er program , a n d ca ll the
appropriate organization blocks:
QV Z du rin g di rect access
via the S5 bus
Time o ut i n th e user program d uri ng di rect acc es s v ia t he S5 bus to
CP, IP, coordi nator or to a peripheral mod ule (e.g. wit h load and
transfer operati ons L/T P... or O...):
O B 23
The sys tem p rog ra m c alls organi zati on bl oc k OB 23, if i t is l oa ded.
5
Er rors in RUN and in RE ST A R T
CPU 928B Programming G uide
C79000-B8576-C898-01 5 - 53
Error identifiers
ACCUs 1 and 2 co ntain additional informati on that d efi nes the error
in greater detail .
ACCU1-L = 1E23H
ACCU2-L = QVZ a ddre ss
QV Z addre ss
The Q VZ addr es s ind i cate s the first peripheral byte to ge ne rate a
QV Z. Normally, this is the b yte with the lowest address in peripheral
operations.
An exception t o this are QVZ ad dresses supplied with the comman ds
TNB/TNW in the event of a timeout. Since these operations are
decremented, in this case the QVZ address indicates the byte with the
hig h est a dd ress t ha t trig g ered th e QVZ d u ring th e trans fer of data.
Timeout error durin g the update of the process image for
inputs/outputs and trans fer o f IPC flags:
Q V Z durin g PII upd a te
and transfer of the
IPC flags
O B 24
The sys tem p rog ra m c alls organi zati on bl oc k OB 24. ACCUs 1 an d 2
co n tain ad diti ona l in formatio n tha t de fi nes th e error i n gre ater d e tail :
E r ror identifier
ACCU-1-L ACCU-2-L Explanation
1E25 H yyyyH Tim eout outputting the process image
of the digital ou t put s
yyyy = address of the non-ack now-
l ed ged o utpu t b yte
1E26 H yyyyH T im eo u t upd at in g the process ima ge of
the digital inputs
yyyy = address of the non-ack now-
ledged input byte
1E27 H yyyyH Tim eout updating the IPC f lag outputs
yyyy = address of the non-ack now-
ledged IPC flag byte
1E28 H yyyyH Tim eout updating the IPC f lag inputs
yyyy = address of the non-ack now-
ledged IPC flag byte
Table 5-28 QVZ f lag s when calling OB 24
Errors in RUN and in RES TAR T
CPU 928B Programming Gu ide
5 - 54 C79000-B8576-C898-01
Note
If th e org ani za ti on bl ock s c al le d are not progra m med, the us er
program is continued.
If a t im eo ut occu rs, th e CPU read s in t he su bst it ute valu e "0 0H"
and continues to work with this value if the QVZ is
acknowledged.
A tim eout, however, increases the runtim e of the STEP 5
operation that caus ed it.
STOP in the case of QV Z
If you want a timeout to cause the CPU to stop, you must program the
stop operatio n STP in OB 23 or 24.
You can also program DX 0 to cause a system stop in the event of a
time o ut w i tho ut programmi n g OB 23/ 24. 5
Er rors in RUN and in RE ST A R T
CPU 928B Programming G uide
C79000-B8576-C898-01 5 - 55
5.6.5
ZYK (Cycle Time Exceeded
Error) T he c ycle time in cludes the entire d uration of c yclic program
execution. The cycle monitoring time can be exceeded owing to a
nu mber of reasons: e.g. incorrect programming, a program loop in a
func ti on bl oc k , fai lure of t he clo c k pulse ge n erat o r or by syst em
activities such as process im age updating in conjunction with long
programs.
O B 26
When the cycle time e xcee ded error occurs, the system program
int errupts t he use r pro g ram an d call s organiz ation bloc k OB 26, if it is
loa de d . T hi s re triggers th e cycl e time mon it ori n g. If th e mon it ori ng
time elapses again, bef ore OB 26 has been completely processed, the
CPU goes into the STOP mode owing to a double call error
(DOPP-FE).
Cycle monitoring tim e
The cycle monitoring time is variable (1 to 13000 ms) and can be
retriggered (see above). Regardless of the cycle tim e, 100 m s after the
cycle time has elapsed, BASP is activated if OB 26 h as not yet been
completed.
You can select the cycle monitoring tim e by m eans of an entry in DX
0 o r by calli n g th e spec ia l fun ct ion o rga ni za tio n block OB 221.
In the cycl ic program, t h e c y cl e t ime mon it oring c an be ret rig ge red by
c alli ng th e spec ia l fu nction OB 222.
STOP in the case of
unloaded OB 26
If you do no t progra m OB 26, the CPU ch anges to the STOP mode. I f
you do not want this to happen, you must change the default in DX 0.
No e rror identifiers
If a c y cl e tim e exce ede d error o c cu rs, no error id entifiers are
transferred to ACCU 1 or ACCU 2.
Errors in RUN and in RES TAR T
CPU 928B Programming Gu ide
5 - 56 C79000-B8576-C898-01
5.6.6
W ECK-F E (Collision of Time
Interrupts) If a part ic u lar time interrupt OB is requ ested be fore its last request ha s
bee n completel y pro ce sse d , t he syst em program rec o gni ze s a co l li sio n
of time in t errupts a nd cal ls orga ni za ti o n blo ck OB 33, if it is loaded,
or th e CPU go e s to th e STOP mode . Se e Sec ti on 4.5.2.
ACCUs 1 and 2 co ntain additional informati on that d efi nes the error
in greater detail .
Er ror identifier
ACCU-1-L ACCU-2-L Explanation
1001H 0016H C ollision of time interrupts in OB 10
(10 ms)
0014H C ollision of time interrupts in OB 11
(20 ms)
0012H C ollision of time interrupts in OB 12
(50 ms)
0010H C ollision of time interrupts in OB 13
(100 ms)
000EH Collision of time interrupts in OB 14
(200 ms)
000CH Collision of time in terrupts in OB 15
(500 ms)
000AH Collision of time interrupts in OB 16
(1 sec)
0008H C ollision of time interrupts in OB 17
(2 sec)
0006H C ollision of time interrupts in OB 18
(5 sec)
Note
The identif ier in ACCU 2 is the level identifier of the time
i nterrupt that ca used the error.
If you do no t program OB 33, the CPU goes int o the stop mode.
You ca n, h ow e ver, progra m DX 0 so that the program is
c ontinued when a collision of time interrupts occurs alth ough you
have no t programmed OB 33.
A seco nd ca ll for th e already a ctive error pro gra m pro ce ssi ng
level "collision of time interrupts" does not lead to a double call
erro r (DOPP).
Table 5-29 WECK-FE identifiers
5
Er rors in RUN and in RE ST A R T
CPU 928B Programming G uide
C79000-B8576-C898-01 5 - 57
5.6.7
REG-FE (Controller Error) An error occ urring during the processin g of the standard function
bloc k fo r control ler str ucture R64 is detected as a contr olle r error.
Note
While, fo r exa mple, a c o ll ision of time inter ru pts is alw ays
recognized by the syste m progra m, when a particu lar ti me
inte r rupt OB is not started an d c omple te d withi n a particula r time
inte rva l (e.g . OB 13 w i th in 100 ms), in c orrec t proce ssing of t he
closed loop control program is only detected when the program
pro ce ssi n g leve l CL C ONTR OL is called. The error is then
indicated in the ISTACK.
O B 34
If a c ont rolle r erro r oc curs, the progra m pro cessi n g leve l CL
CONTROL is ex it ed a n d th e CONTR OLL ER E RROR (L EVEL:
001CH ) level i s cal led wi th organi zation block OB 34.
T he subseque nt reaction of t he CPU d epends on how you ha ve
program med OB 34:
•• If you have not programmed OB 34, the CPU goes into the STOP
mode. You ca n see the cause o f the error by displaying the
IS TACK.
•• If you h ave programmed OB 34, the STEP 5 program it c ontains
(e.g. e val uati on of AC CU 1 and 2 an d th en a ppro priat e error
handli ng ) i s execut ed . Follow ing this, th e contr oll er proc e ssing i s
continued from the point at which it was interrupted.
Response to controller errors
If you wa nt to ig n ore al l co n tro ll er e rro rs, s im pl y writ e th e block end
statement BE in OB 34 .
If you want the controller processing to continue when a controller
error occurs and you do not program OB 34, chang e the de fault i n
DX 0.
Errors in RUN and in RES TAR T
CPU 928B Programming Gu ide
5 - 58 C79000-B8576-C898-01
When OB 34 is called, ACCUs 1 and 2 contain additional information
th a t defin es th e error i n g reat er d eta il .
E r ror identifier
ACCU-1-LACCU-2-L Explanation
0801H DByy H Sa mplin g ti me error
yy = number of con trolle r data block
involved
0802H DByy H Con trolle r da ta blo ck no t loaded
yy = number of the data block that
is not loaded
0803H FByyH Controller function block not loaded
yy = t he nu mber o f the fu nc tio n blo ck
that is no t loaded
0804H FByyH Controller function block not recognized
yy = nu mber o f the no n-recogni zed
function block
0805H FByyH Controller function block loaded with
inc orrect PC soft ware
yy = function block number
0806H DByy H W rong controller da ta block length
yy = data block number
0880H 00yyH T imeout (QVZ) during the controller
processing
yy = number of the I /O by te th at caused
the timeout.
Ent ry in the cont rol bit
screen fo rm
In all seven situations, the error identif ier REG-FE is mark e d in the
co n tro l bits on the pro g ramm er screen . I f you o pera te a PG with ou t
th e S5-DOS ope rati ng system, th e la st posit ion in t he l o wer l ine of t h e
co n trol bi ts sc re en is n o t labelled , bu t is al so marked. In the ISTAC K
sc reen , th e le vel CL C ONTROL, REG is ma rk e d as th e ca use o f t he
interruption.
T able 5-30 RE G-FE iden tifier s
5
Er rors in RUN and in RE ST A R T
CPU 928B Programming G uide
C79000-B8576-C898-01 5 - 59
Sampling time e rrors
Afte r the sel ec te d sa mpling time h as el apsed, th e cyc li c pro gram i s
st opped at the ne xt block boundary a n d the co ntro ller proces sin g i s
ins erted. It is possible t ha t th e p roc es sing of longer b locks ta kes t oo
l ong and th at the controller processi ng becomes "out of step": this
causes a sampli ng t ime error.
You can handle a sam pling tim e error just as the other controller
errors (as d escribed on the previ ous page) or you ca n suppres s t he
error by means of a mask. In this case, program execu ti on is not
i nterrupte d when a sampli ng time error occurs.
Refer a ls o to t he d es criptio n "com pa ct c lo se d lo op co n tro l i n th e R
processor of the S5 135U" in the R64 Contr oller Structur e.
You can so meti me s preven t a sampli ng t ime error by c ha n gin g th e
de fault in DX 0 "processing of controller and pr ocess i nterrupts at
block boundaries" to "processing of co ntroller and process interrupts
at operation boundaries ".
5.6.8
ABBR (Abort) If, during the RUN m ode, the stop mode is requested by one of the
following:
•• swi tc hi n g th e mo de sel ec to r on the CPU fro m RUN to STOP,
•• PG online function, PLC STOP,
•• reset swit ch o n c oo rd in ato r set t o STOP (i n multiproce sso r
operation),
the system progra m c alls OB 28, it is loaded. After OB 28 has been
processed, the CPU goes into the STOP mode.
Note
The tran siti o n to t he sto p mode tak e s place rega rd l ess o f wheth e r
you program OB 28 or not.
No e rror identifiers
No error i denti fiers are trans ferred to AC CU 1 or ACCU 2.
Errors in RUN and in RES TAR T
CPU 928B Programming Gu ide
5 - 60 C79000-B8576-C898-01
5.6.9
Communication Errors
(FE-3) If problems occur on the second serial inter face with the computer
link RK 517, data transfer with proce dure 3964/3964R, data trans fer
with " open driver" or data transf er with SINEC L1, the system
progra m c alls organi zati on bl oc k OB 35 and trans fers addit ional
information about the problems to ACCU 1.
Response in the case of
unloaded OB 35
If you do no t progra m OB 35, the syste m program does not react and
the CPU does not go into the stop m ode. This is the default reaction.
If you wan t the CPU to go into the stop mode when an in ter face error
occurs and yo u do not program OB 35, you must change the de fault in
DX 0.
Error information in ACCU 1
E very 100 ms the s yste m program chec ks whether commu nicatio n
erro rs h ave occu rred o n th e se co nd seri al int erfac e. If a n error is
detected, the system program transfers the error information to ACCU
1 and ACCU 2. If you program OB 35, the syst em program calls it
a nd transfers the error in for mat io n in ACCU 1 a nd ACCU 2.
Error num be rs for a maxi mu m of three ca uses of probl ems can be
tra ns fer re d when OB 35 is ca ll ed. If t h ere are mo re t h an t hree c au se s
of problems at th e sa me time , t h is is in dic at ed by a specia l o v erflo w
identifier.
St ructu re of the error
information in ACCU 1 and
ACCU 2
31 24 23 18 15 8 7 0
ACCU 1 0 0 0 0 F U B 0 Error number
1Error nu mber
2Error nu mber
3
F = ’0’, when there is no error entered in the error area
= ’1’, when th ere is an error entered in t he error area.
U = ’0 ’, wh en there is no er ror overflo w (maxim u m thr e e entries)
= ‘1 ‘, when the re i s an error ove rf low (mo re than three ent ries)
B = ’ 0’ , when there is no BREAK on the interface
= ’1 ’, wh en th ere is a BR EAK on the in ter face
5
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CPU 928B Programming G uide
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BREAK
If there is a BREAK on an interface, OB 35 is only called at the
beginning and end of the BREAK status.
Error numbers 1 to 3
Here, a maxi mum of three err or nu mbers belong ing t o problems
detected on the interface are entered in the order i n which they are
detected by the system.
M eaning of the error numbers
For the me an in g of th e erro r num be rs a nd fu rther in form ati o n on
handlin g interface errors, refer to the "CPU 928B Communication "
Ma nua l (/14/ in Chapter 13).
Errors in RUN and in RES TAR T
CPU 928B Programming Gu ide
5 - 62 C79000-B8576-C898-01
Contents of Chapter 6
6 .1 Intr oduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
6.2 OB 1 10: Acc essing the C ondition Code Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 1
6 .3 OB 111 : Clea r AC C Us 1, 2, 3 and 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
6.4 OB 1 12/113: R oll Up ACCU an d Roll Down ACC U . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
6.5 OB 120: Enabling/Disabli ng of Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
6.6 OB 121: Enable/Disable Ind ividual Time-Driven I nterrupts . . . . . . . . . . . . . . . . . . . . . . 6-19
6.7 OB 122: Enable/Disable "Delay of All Interrupts" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
6.8 OB 1 23: Ena ble/ Dis able " De la y of Individual Time-Driven Int errupts" . . . . . . . . . . . . . 6-25
6 .9 Sett in g/Reading the System Tim e (OB 150). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 28
6.10 OB 151: Sett ing /Re ading t he T ime for Clock-Driven Interrupts . . . . . . . . . . . . . . . . . . 6-33
6 .11 O B 152 : Cycle Sta tis tics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 -40
6.12 O B 153 : Set/Read Time for Delayed Interr upt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-48
6.13 O B 160 to 163: Loop Co unters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-51
6.14 O B 170 : Re ad B loc k Stack (BS TACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-53
6.15 OB 180: Acc essin g Variable Data Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-58
6.16 OB 181: Testing Dat a Bl oc ks (D B/DX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-62
6
Integrated Special Functions
6
CPU 928B Programm ing Guide
C79000-B8576-C898-01 6 - 1
6.17 O B 182 : Copyi ng a Da ta Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-65
6.18 OB 190/OB 192: Transferring Flags to a Data Block . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-68
6.19 OB 191/OB 193: Transferring Data Fields to a Flag Area . . . . . . . . . . . . . . . . . . . . . . . 6-71
6.20 OB 200 to OB 205: Multiprocess or Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-77
6.21 O B 216 to OB 218 : Pa ge Ac cess. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-78
What are pages? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-78
How to access pages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-79
Address areas for peripherals on the S5 bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-80
Notes on assign ing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-81
6.21.1 OB 216: Wr it ing t o a Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-82
6.21.2 OB 217 : Re ading fr om a Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-84
6.21.3 OB 218 : Res erving a Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-86
6.21.4 Program Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-88
6.22 O B 220 : S i gn Ex te nsion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 0
6.23 O B 221 : Se tting t he Cycle Mon it ori ng T ime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-91
6.24 O B 222 : Restarting the Cycl e Monitoring T ime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-92
6.25 OB 223: Comparing Restart T ypes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-93
6.26 OB 224: Tr ans ferring Bl ocks of I nterprocessor Communication Flags . . . . . . . . . . . . . 6-94
6.27 O B 226 : Re ading a Word from the Syst em Progr am . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-95
6.28 O B 227 : Re ad ing the Checksum of the System Program . . . . . . . . . . . . . . . . . . . . . . . . 6-96
6.29 O B 228 : Re ad ing Stat us Informati on of a Program Proces si ng Leve l . . . . . . . . . . . . . . 6-9 8
6.30 O B 230 to 237: Funct ions for Standar d Function Blocks . . . . . . . . . . . . . . . . . . . . . . . 6-100
6.31 OB 240 to 242: Special Func tions for Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 6-101
6.31.1 Shi ft Regis ters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-101
6.31.2 OB 240 : In itia lizi ng Shift Re gisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-105
6.31.3 OB 241: Processing Shi ft Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-108
6.31.4 OB 242 : De leti ng a S hift R egis ter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-109
Contents
CPU 928B Programming Guid e
6 - 2 C79000-B8576-C898-01
6.32 OB 250/251: Close d-loop Control/ PID Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-110
6.32.1 Functional Descripti on of the PID Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-110
6.32.2 P ID Al gorith m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-112
6.32.3 OB 250: Initializi ng the P ID Alg orithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-118
6.32.4 OB 251: Processing the PID Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-119
Format of con tro ll er i nputs a nd ou tpu ts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-120
General notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-121
Contr oller parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-122
Par a me ter ch ang es. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-123
Abbrevi ations for PID controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-123
N ormalized fi xe d point numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-124
6.33 OB 254, OB 255: Trans ferring a Data Block to the DB RAM . . . . . . . . . . . . . . . . . . . 6-125
6
Contents
CPU 928B Programm ing Guide
C79000-B8576-C898-01 6 - 3
6Integrated Special Functions
Thi s C h apte r tell s yo u wh ic h in te g ral spec ia l fun ct io ns the syst em
prog ram con ta in s, where yo u c an u se th e se fun ct ion s an d ho w yo u
must c al l a n d assig n param et ers to the speci al fun c tion OBs.
In ad d itio n, you will l ea rn ho w t o det ec t e rro rs i n proc essin g a spec ia l
function and how do deal with these in the program.
6
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 5
6.1 Introduction
T he CPU 928B operati ng s yste m provides you with a n umber of
special functions, that y ou can call with a conditional (JC OBx) or
unco nd i ti on a l (JU OBx ) blo c k ca ll . Org an izat ion blo c ks OB 40 to
OB 255 are reserved for these special functi ons.
These functi ons are known as integrated spec ia l funct io ns, sin c e t hey
are a fix ed part o f th e syste m prog ram. Yo u can call th e se spec ia l
function s, you c an not, however, read or modify th em.
The table below gives you an overview of the special f unctions
available.
Block F unctio n see section /
page
O B 110
O B 111
O B 112
O B 113
Access to the condition code byte
Clear ACCU 1, 2, 3 and 4
Roll up ACCU
Roll down ACCU
6.2/ 6 - 11
6.3/ 6 - 13
6.6/ 6 - 14
"
O B 120
O B 121
O B 122
O B 123
"Disable all i n terrupts" on / off
"Disable sing le time in terru pts" on/of f
"Delay all interrupts" on/off
"Delay single tim e interrupts" on/off
6.5/ 6 - 16
6.6/ 6 - 19
6.7/ 6 - 22
6.8/ 6 - 25
O B 150
O B 151 Set/r ead the syst em time
Set/read time for clock-driven tim e interrupt 6.9/ 6 - 28
6.10 / 6 - 33
OB 152 Read out cycle time 6.11/ 6 - 40
OB 153 Set/read time for delay interrupt
(from Version -3UB12) 6.12 / 6 - 48
O B 160 to 163 Loop counter 6.13/ 6 - 51
O B 170 Rea d bl ock stack (BSTACK) 6.14/ 6 - 53
O B 180
O B 181
O B 182
Variable data block access
Test data block (DB/DX)
Copy d ata ar ea
6.15 / 6 - 58
6.16 / 6 - 62
6.17 / 6 - 65
O B 190, 192
O B 191, 193 Tra nsfe r flags to data b locks
Trans fer data fields to flag area 6.18/ 6 - 68
6.19 / 6 - 71
O B 2001), 202 1)
O B 203, 2041), 205 Function s for mu ltiproces sor comm un ication 6.20/ 6 - 77
O B 216 to 218 Accessing pages 6.21/ 6 - 78
Table 6-1 Overview of the special functi ons avai lable with the CPU 928B
Introduction
CPU 928B Programming Guide
6 - 6 C79000-B8576-C898-01
Block F unctio n see section /
page
T able 6-1 continued:
OB 220 Sign extension 6.22/6 - 90
O B 221 2)
O B 222
O B 223
O B 224 2)
O B 226
O B 227
O B 228
Set the cycl e mo nitoring time
Restart the cycle monit oring time
Compare restart types in multiprocessor operati on
Transfer a blo c k of IPC fla g s i n mult iprocessor ope rat io n
Read a word from the system program
Read the checksum of the sy stem program
Read status infor mation of a program processing l evel
6. 23 /6 - 91
6. 24 /6 - 92
6. 25 /6 - 93
6. 26 /6 - 94
6. 27 /6 - 95
6. 28 /6 - 96
6. 29 /6 - 98
O B 230 to 2371) Fun ctions for standar d function b locks 6.30 /6 - 1 00
O B 240
O B 241
O B 242
Initialize shif t re gist er
Pro ce ss sh ift reg ist er
Clear shift register
6.31.2/6 - 105
6.31.3/6 - 108
6.31.4/6 - 109
O B 2501)
O B 2511) I n iti alize PID controller
Pro ce ss PID co n troll er 6. 32.3/ 6 - 118
6.32.4/6 - 119
O B 254, 2551) Copy /duplicate a DB or DX data block 6.33/6 - 125
1) Special functions with pseudo operation boundaries (executed in several steps)
2) Instead of these special function organization blocks, assign parameters in data block DX 0 (see Chapter 7).
6
Introduction
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 7
Interfaces
The follo wi ng o pera ti ons an d param et ers are avai la ble as in t erfac es
when prog rammi n g th e use o f spe ci al fun c ti ons:
Block call
•• Conditional/unconditional block call JC ... / JU ...
Parameters
•• Parameters for selecting presets using ACCU 1 and possibly
AC CU 2 and /or memory registers.
In th is descri pt ion , th e term parameters ref ers t o al l da ta t hat th e
CPU need s to c arry ou t the spec ia l funct ion s c o rre ct ly. Befo re you
call the se spec ia l fu nct ion s i n you r STE P 5 program, you must
load this data into the accumulators or into the mem ory registers
as indicated.
ACCU abbreviations
T he abbreviations used in referen ce to the parameter assignment of
spec ia l funct ion OB s a re as fo ll ows:
ACCU 1: ACCU 1, 32 bits
ACCU-1-L: ACCU 1, low word, 16 bits
ACCU-1-LL: ACCU 1, low word, low byte, 8 bits
ACCU-1-LH: ACCU 1, low word, high byte, 8 bits
Hi g h w ord L ow word
High byte Low byte High byte Low byte
31 24 23 16 15 8 7 0
Introduction
CPU 928B Programming Guide
6 - 8 C79000-B8576-C898-01
Err ors duri ng special
fu nctio n processi ng
If an e rro r o cc urs du rin g t he proc essin g of th e specia l fun ctio ns, th e
sy stem program reacts in a specific manner.
In terms of th e s yste m program reacti on to errors, the special
functions can be divided into two groups.
Error OB, ACCU identifiers
Gro up 1 incl udes all the special functions for which an error
organization block (error OB) is called in the event of an error. You
can program th e CPUs react ion i n th es e e rror OBs. Thes e e r ror OB s
are OB 19, OB 30 and OB 31. In ACCU 1 and for some special
fu nct ions also in ACCU 2 (see Section 5.6.1 an d 5.6.2), ident ifiers are
tra ns fer red to t h e e rror OB t ha t de f in e the error i n g reat er d e tail .
If the CPU en cou n te rs for e x ampl e an i nc o rre ct param eter wh e n
proc essin g o ne o f th e se spec ia l fu nct ion s, i t dete ct s a ru ntim e error
and calls OB 31. On the other hand, if f or exam ple the called special
fu nct io n does not ex ist, the CPU detects an operation cod e error and
atte mpts t o ca ll OB 30. Wi th so m e o f t he se specia l funct io n s, if t he re
is a re f eren c e to a da ta blo c k in the c al l para me ters a nd t h e d a ta block
is not loaded, then the CPU attempts to call OB 1 9.
If th e error OB s 30 or 31 are not l oa ded o r co n tain an STP ope rati on,
the CPU goes into the stop mode. LZF or BCF is m arked in the
c ontrol bits in the ISTACK. The accumu la tors of t he error processin g
levels co ntain error identifiers that describe the error in greater detail.
If OB 19, OB 30 or OB 31 is loaded (and does not contain an STP
operat ion ), the user progra m i s co ntinu ed a t th e ne x t o perati on a fte r
the OB has been processed. In this case, the accumulators rem ain
unchanged.
6
Introduction
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 9
RL O, CC 0/CC 1
In c onn ection with some of th e special functio ns, errors specific to the
special functi on affect the condition codes CC 0/CC 1.
If an e rro r occ urs du rin g t he proces sin g of th e se spec ia l fu nct io ns, th e
RLO is normally set (RLO = 1). When using these special functions,
you can use a JC operati on (conditional jump) in yo ur STEP 5
program to evaluate the RLO and to react to an error.
The proc ess in g of so me specia l fun ct ion s also aff ec ts th e con di ti on
co d es CC 0 and CC 1. I n you r STE P 5 program, you ca n sc an the se
con dit io n co des w it h co m parison o perat io ns a n d on c e a gai n reac t to
an error.
T he foll owin g descripti ons of the individual special function OBs
i ndicate whic h of these reactions apply to the particu lar special
function OB.
Note
C alling a special functi on OB with the operation JC OB > 39 or
JU OB > 39 is not a "genuine" block change, but is handled like a
STEP 5 operati on without a block operand. N o interrupts are
i nserted (when "interrupts at block boun daries" is set).
Special functions with
pseu d o operatio n
boundaries
Some o f th e spec ia l fu n ctio n s a re c arried out in s ev era l ste ps and
contain w ha t a re k nown as pseudo operation boundaries.
Thi s means th a t t h e s pe ci al func ti o n is ex ec u te d in sev eral steps. If an
error (e.g. ZYK) or an int errupt (e. g. time or proc ess int errupt at
operation boundaries) occurs during the execution of a step, the
appropriate organization bloc k is inserted at the end o f this step at the
pseudo operation boundar y.
The special functions containing pseudo operation boundaries are
marked in the overview of the integrated special functions.
Introduction
CPU 928B Programming Guide
6 - 10 C79000-B8576-C898-01
6.2 OB 1 1 0: Ac ces s ing the C o nditio n C o de B y te
Function
Using the special f unction organization block OB 110, you can write
the co nte n ts of A C CU 1 t o the con diti o n co d e re gi st er, or mask i t wit h
"1" or "0".
Assignment of ACCU 1 for
access to the condition cod e
register
31 7654321 0
*) C 1 C 0 OV OS OR STA RLO ERAB
Word di sp l ays Bit displays
*) Bit s 8 to 31 are reserv ed for exten sion s and m ust be " 0" wh en th e c onditi on c od e regist er is writ ten to. The y m us t also b e ig nored
when reading out the condition code register.
Parameters 1. ACCU-2-L:
Function number
possible values: 1, 2 or 3
2. ACCU 1 :
New condition code byte or mask
Function
no. in
ACCU-2-L
C ontents of ACCU-1-L F u n c t i o n
before after
1
2
3
New
condition
code byte
Mask
Mask
New
condition
code byte
New
condition
code byte
1)
New
condition
code byte
1)
The contents of ACCU 1 are loaded in the condition
code register.
All the bits indicated as " 1" in the m ask in ACCU 1 are set
to "1" in the condition code register. T he n ew
condition code byte is loaded in ACCU 1.
All the bits indicated as " 1" in the m ask in ACCU 1 are set
to "0" in the condition code register. T he n ew
condition code byte is loaded in ACCU 1.
1) Restric ti on : OB 110 its e lf affects the c o n ditio n code bits. It sets: OR = 0, STA = 1 and ERAB = 0, regardless of the
valu e sp eci fied for these bits in ACCU 1 before the OB was called.
6
O B 110: Ac cessing the Condition Code Byte
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 11
Result
After execution of OB 110, the condition code byte will have been
c han ged i n ac cor dance wit h the func ti on and the co ntents of AC CU-1.
Po ssib le errors
•• Function number in ACCU-2-L not equal to 1, 2 or 3.
•• One of the bits no. 8 to no. 31 is set in ACCU 1.
If an error occurs, OB 31 (other runtime errors) is called. If OB 31 is
not loaded, the CP U goes t o th e STOP mode. In bo th cas es, the error
ide nt ifier 1A 49H is en tered in ACC U-1-L.
Example
With OB 110, you can test the operat io ns that ev al uate or a ffect the
con dit io n co d e register. It s a p pl icat io n i s, h o wev e r, n ot res tricted to
the operation test. The f ollowing exam ple shows you a f urther
possible application.
Call distributor
One of fou r subr outi ne s is t o be cal le d de pend in g on the c onte nt s of
flag byte FY 0. The four subroutines are assigned to bits F 0.0 to
F 0.3. Onl y one of t he se b it s ca n be s et a t an y one time .
:L FY0
:SLW 4 ;shift F 0.0 to F 0.3 four bits to the left
:L KB 1 ;loa d the fu nc tion n umbe r
:TAK
:JU OB110
:JS =M0 00 ;jum p if O S = 1
:JO =M0 01 ;jum p if O V = 1
:JM =M0 02 ;jum p if C C 0 = 1
:JP =M0 03 ;jum p if C C 1 = 1
:
: ;if no bit is set
:
:BEU
:
M000 : ;if F 0. 0 = 1
:
:BEU
M001 : ;if F 0. 1 = 1
:
:
M002 : ;if F 0. 2 = 1
:
:BEU
M003 : ;if F 0. 3 = 1
:
:BEU
O B 110: Ac cessing the Condition Code Byte
CPU 928B Programming Guide
6 - 12 C79000-B8576-C898-01
6.3 OB 111: Clear ACCUs 1, 2, 3 and 4
Function
Calling special function organization block OB 111 is a simple way of
clea rin g A C CUs 1 to 4. OB 111 o verw rit es al l fo ur regist ers wit h "0".
Parameters
none
Result
Accus 1 to 4 (32 bits each) are d eleted.
Po ssib le errors
none
6
OB 111: Clear A CCUs 1, 2, 3 and 4
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 13
6.4 OB 112/113: Roll Up ACCU and Roll Do w n ACCU
Function
OBs 112 and 113 roll the contents of the ACCUs either up or down.
•• OB 112 (roll up) shifts the contents of ACCU 1 to ACCU 2, the
contents of AC CU 2 to ACC U 3 etc.
•• OB 113 (rol l down ) s hi fts th e co nte nt s of the AC CU s in the
oppo site direction ; the co nte n ts of A C CU 1 t o ACCU 4, ACC U 4
t o ACCU 3 etc.
Parameters
none
Result
Fi gures 6-1 an d 6-2 show t he contents of the ACCUs before and after
c alling OB 112 and OB 113 .
Note
You can also shif t the contents of the ACCUs using the STEP 5
opera tions E NT (sup plementary operation set) and TA K (sys tem
operation) (see Sect ion 3.4.3.).
Po ssib le errors
none
O B 112/113: Roll Up ACCU and Roll Down A C C U
CPU 928B Programming Guide
6 - 14 C79000-B8576-C898-01
ACCU 4
ACCU 2
ACCU 3
ACCU 1
31 0 31 0
<ACCU 4>
<ACCU 2>
<ACCU 3>
<ACCU 1>
<ACCU 4>
<ACCU 2>
<ACCU 3>
<ACCU 1>
OB 112
roll ACCU contents
before after
Fig. 6-1 Effects of the "roll up" function
ACCU 4
ACCU 2
ACCU 3
ACCU 1
31 0 31 0
<ACCU 2>
<ACCU 4>
<ACCU 1>
<ACCU 3>
<ACCU 4>
<ACCU 2>
<ACCU 3>
<ACCU 1>
OB 113
roll ACCU contents
before after
Fig . 6-2 Ef fects of the "r oll down" funct ion
6
O B 112/113: Roll Up ACCU and Roll Down A C C U
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 15
6.5 OB 1 2 0: E na blin g/D is a bling o f In terr up ts
A STEP 5 program can be interrupted at block or operation
boundaries by progra ms wit h a higher priority. Th ese higher priority
progra m proc ess in g le vel s i nclu de the pro ce ss an d al l ti me in terrupts
( c yclic ti me interrupts, clock-driven time interrupt and delay
i nterrupt). The runti me of the in terrupted program is therefore
e xte nded by the runti me of the programs inserted b y the interrupts.
Usin g special fun ction organizatio n blocks OB 120, you can prevent
t he insertio n of higher priority progra m processi ng levels at one or
more consec u tive bloc k or o perati on bo u nd a ries (de pen ding on th e
setting in DX 0).
Function
T he special function organization OB 120 affects the reactio n to
i nterrupts:
Disabling in te rru pts mean s t h at no more i nte rru pts are reco g niz ed and
t he interrupts that h ave alrea dy been d etecte d (e. g. they are waiting for
a block bou nda r y) are cleared. If OB 2 (process interrupts) or an OB
for t ime-driven in terrupt processing have already started, they are
processed to th e end.
Enabling i n terru pts me ans th at al l inte r rupts are o nce agai n
reco gnized imme diately, and are inserted and processed at the next
block or operation bou nda r y.
Parameters
1. Double control wor d
OB 120 rec ords the interrupts to be disabled or d elayed in a
system-int ernal d ouble con trol word.
Bit no. 31 3 2 1 0
Double control word
O B 120: Enabling/Disabling of Interrupts
CPU 928B Programming Guide
6 - 16 C79000-B8576-C898-01
The bits of the doub le contro l wo rd are ass ig ned as follow s:
Control
wo rd bit no. Function
0 = ’1’ all time-driven interrupts in fixe d in terval delayed
1 = ’1’ t he cloc k-driven time interrupt is disabled
2 = ’1’ all process interrupts are disabled
3 = ’1’ the delay interrupt is disabled
4 to 31 reserved ; th ese bit s must be "0"!
2. Accus
2a) ACCU-2-L
Fu nc tio n No.
Permissible values 1,2 or 3 wit h:
1: The contents of ACCU 1 are loaded
in th e control wo rd.
2: All the bits in the mask in ACCU 1
marked wit h a ’1’ are se t to ’1’ in the
contr ol word. The new control wo rd i s
loaded in ACCU 1.
3: All the bits in the mask in ACCU 1
marked with ’1’ are set to ’0’ in the
contr ol word. The new control wo rd i s
loaded in ACCU 1.
2b) ACCU1
New control word or mask, depending on the desired function
6
OB 120: Enabling/Disabl ing of I nterrupts
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 17
Result
Call ing OB 120 has the foll owing results:
F unction no.
in
ACCU-2-L
C on tents of ACCU 1
before after
1
2
3
Contr o l wo r d
Mask
Mask
Control word
New
co ntr ol word
New
co ntr ol word
Po ssib le errors
•• Illegal function number in ACCU-2-L
•• One of the reserved bits in ACCU 1 (no. 3 to 31) is set to " 1" .
I n the event of an err or , OB 31 (other runtime errors) is calle d. I f
OB 31 is not loaded, the CPU goes to the STOP mode.
In both ca ses, an error I D is e n tere d in ACCU -1-L.
Notes
•• You can scan the status of a control word with the following
pro g ra m sequence:
1. Load the function nu mber 2 or 3 in ACCU-2-L
2. Load the value ’0’ in ACCU 1
3. Call special function OB 120
4. Read out ACCU 1
•• You ca n de te rm i ne t he st atu s of int errupt process in g by readi ng
out sys tem da ta word RS 131 .
- RS 131 Condition codeword " disable all interrupts"
•• Instead of OB 120, you can use the operations IA and RA to
disa ble and enable proce ss
inter rupts as foll ows :
IA co rre spond s to :L K B 2
:L KM 00000000 0000 0100
:JU OB 120
RA co rre spond s to :L KB 3
:L KM 00000000 0000 0100
:JU OB 120
O B 120: Enabling/Disabling of Interrupts
CPU 928B Programming Guide
6 - 18 C79000-B8576-C898-01
6.6 OB 1 2 1: E n a ble /D is ab le Ind ivid ua l Tim e -Dr iv en Inte rr up ts
Using the special f unction organization block OB 121, you can
preven t the in sertio n o f certain tim e-driven OBs (tim e-driven
i nterrupts wit h a fixed time interval) a t on e or mo r e consecut iv e
bloc k or operation boundaries. You can, for exa mple, preve nt a
particular progra m section being interrupted by an OB 18 (5 s) and an
OB 17 (2 s). On the other hand, all other programmed time-driven
i nterrupts are processed as usual.
Function
T he special function organization OB 121 affects the reactio n to
time-driven interrupts:
Disabling indivi dual time-driv en interrupts means that no more of the
speci fied ti me-driven interrupts are recogn ized and the in terrupts that
have already been detected (e.g. they are waiting f or a block
boundary) are cleared. If O B 2 (process interrupts) or an OB for
time-driven interrupt processing (for processi ng a time-driven
i nterrupt at a fi xed ti me interval) have already started, they are
processed to th e end.
Enabling indivi dual time-driven interrupts means that all interrupts
are once a gain reco gnized immediately, and are inserted and
processed at the nex t block or operatio n boun dary.
Parameters
1. Control w ord
OBs 121 records th e time-driven interrupts to be disabled or delayed
in a c ontrol word:
Bit no.: 15 3 2 1 0
C ontrol word
6
OB 121: Enable/Disable Individual Time-Driven Interrupts
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 19
The bits o f the control word are assigned as follows:
Bit no. Interrupt
0 to 2 Reserved; these bits must be "0"!
3 = ’1’
4 = ‘1‘
5 = ’1’
6 = ’1’
7 = ’1’
8 = ’1’
9 = ’1’
10 = ’1’
11 = ’1’
Time-driven interrupt wit h fixed time
intervals:
10 ms (O B 10)
20 ms (O B 11)
50 ms (O B 12)
100 ms (OB 13)
200 ms (OB 14)
500 ms (OB 15)
1 sec ( OB 16)
2 sec ( OB 17)
5 sec ( OB 18)
12 to 15 Reserved; these bits must be "0"!
2. Accus
2a) ACCU-2-L
Fu nc tio n No.
Permissible values: 1, 2 or 3 with:
1: The contents of ACCU 1 are loaded
in th e control wo rd.
2: All the bits in the mask in ACCU 1
marked wit h a ’1’ are se t to ’1’ in
the control word. The new control word
is loaded in AC CU 1.
3: All the bits in the mask in ACCU 1
marked with ’1’ are set to ’0’ in the
contr ol word. The new control word
is loaded in ACCU 1.
2b) ACCU 1
New control word or mask, depending on the desired function
O B 121: Enable/ Disable Individual Time-Driven Interrupts
CPU 928B Programming Guide
6 - 20 C79000-B8576-C898-01
Po ssib le error s:
•• Illegal f unction number in ACCU-2-L
•• One of the reserved bits in ACCU 1 is set to "1".
I n the event of an err or , OB 31 (other runtime errors) is calle d. I f
OB 31 is not loaded, the CPU goes to the STOP mode.
In both ca ses, an error I D is e n tere d in ACCU -1-L.
Notes
•• You can scan the status of a control word with the following
pro g ra m sequence:
1. Load the function nu mber 2 or 3 in ACCU-2-L
2. Load the value "0" in ACCU 1
3. Call special function OB 121
4. Read out ACCU 1
You can de te rmi ne t he st at us o f the ti me -dri ve n in t errupt processin g
by read i ng ou t system da ta wo rd RS 135.
- RS 135 Condi tion co deword "di sable in divid ual interrupts"
6
OB 121: Enable/Disable Individual Time-Driven Interrupts
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 21
6.7 OB 1 2 2: E na ble /D is ab le "De la y of A ll Int erru pt s "
A STEP 5 program can be interrupted at block or operations
boundaries b y a higher-priority program. Such h igh er-priority
program processing le vels i nclude the proce ss in terrupts and all time
i nterrupts (cyclic ti me interrupts, clock-driven ti me interrupt and
del ay i nt erru pt ). T he runt ime of t h e i nte rru pted prog ra m is th erefore
e xte nded by the runti me of the programs inserted b y the interrupts.
Usin g special function block OB 122, yo u can prevent the insertion o f
higher priority program processing lev els at one or more consecutive
block or operation boundaries (depend ing on the setting in DX 0).
Function
OB 122 affects the rea ct ion to interrupts as follows:
Enabling interrupt delay means all interrupts will co ntinue to be
reg is te re d an d a lready pen din g in te r rupts w il l re ma in regi st ered.
However, re gist ered in te rrupts w ill no t yet be pro cessed. All o perat ion
or block bo und ari es wil l be te mpo rarily d isa ble d for t he proc essin g
i nterrupts. If OB 2 (process i nterrupts) or an OB for time-driven
i nterrupt processing have already starte d, they are processed to the
end.
Disabling interrupt delay mea ns all registered interrupts will be
in se rte d and proc essed at t he ne xt blo ck or o pera ti on bo unda ry.
Note
If a specific time-d ri ve n inter r u pt OB is called fo r th e se co nd time
durin g the "Dela y inte r rupt" pha se, a collis io n of time int errupts
occurs.
Parameters
1. Double control wor d
OB 122 records the interrupts to be delayed in a s yste m-internal
doub l e control wo rd.
Bit no.: 31 3 2 1 0
D ouble control word
O B 122: Enable/Disable "Delay of All Interrupts"
CPU 928B Programming Guide
6 - 22 C79000-B8576-C898-01
The bits of the doub le contro l wo rd are ass ig ned as follow s:
Control
wo rd bit no. F u n c t i o n
0 = ’1’ all time-driven interrupts in fixe d interval are
delayed
1 = ’1’ t he cloc k-driven time interrupt is delayed
2 = ’1’ all process interrupts are de layed
3 = ’1’ t he de lay interrupt is delayed
4 to 31 reserved ; th ese bit s must be "0"!
2. Accus
2a) ACCU-2-L
Fu nc tio n No.
Permissible values: 1, 2 or 3 with:
1: The contents of ACCU 1 are loaded in
th e con trol word.
2: All the bits in the mask in ACCU 1
marked with "1" are set t o "1". Th e new
control word is loaded in ACCU 1.
3: All the bits in the mask in ACCU 1
marked with "0" are set t o "1" in t he
contr ol word. The new control wo rd i s
loaded in ACCU 1.
2b) ACCU 1
New control word or mask depending on the desired function.
6
O B 122: Enable/Di sable "Delay of All Interrupts"
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 23
Result
Call ing OB 122 has the foll owing results:
F unction no.
in
ACCU-2-L
C on tents of ACCU 1
before after
1
2
3
Contr o l wo r d
Mask
Mask
Control word
New
co ntr ol word
New
co ntr ol word
Po ssib le errors
•• Illegal function number in ACCU-2-L
•• One of the reserved bits in ACCU 1 (no. 4 to 31) is set to " 1" .
In th e ev en t o f error, OB 31 (other runtime errors) is called. If OB 31
is not loaded, th e CP U goes to th e S TOP mode.
In both cases, the error ID 1A48H is entered in ACCU-1-L.
Notes
•• You can scan the status of the control work with the f ollowing
pro g ra m sequence:
1. Load the function number 2 or 3 in ACCU-2-L
2. Load the value "0" in ACCU 1
3. Call special f unction OB 122
4. Read out ACCU 1
•• You ca n de te rm i ne t he st atu s of int errupt process in g by readi ng
out sys tem da ta word RS 132 .
- RS 132 Condition code word "delay all interrupts"
O B 122: Enable/Disable "Delay of All Interrupts"
CPU 928B Programming Guide
6 - 24 C79000-B8576-C898-01
6.8 OB 1 2 3: E na ble /D is ab le "De la y of Individ ua l T im e -D r iv en Inte rr upts"
Usi ng spe ci al fu ncti o n org ani za ti on bloc k OB 123, you c an preven t
the in se rtion o f c erta in t ime-driven OB s (t ime-d riven i n te rru pts wit h a
fixe d time int e rva l) at one or more consecutive block or operation
boundaries.
Function
OB 123 affects the reactio n to time-driven interrupts as follo ws:
Disabling delay o f individual time-driven interrupts means all
i nterrupts will cont inue to be registered an d already pending interrupts
wil l remain re gi st ered. Howe v er, re gi st ered i n te rrupts w il l no t yet be
proc essed. A l l ope ra ti on or bl oc k bou n daries wi ll be te mpora rily
disa bled for t he proc essin g i nterrupt s. If a t im e i n terru pt OB (f o r
processing a time interrupt with a fixed time base) has already been
started, it is processed to the en d.
Disabling delay o f indivi dual time-driv en interrupts means that with
i mmediate e ffect, all c yclic ti me-driven interrupts will again be
registered, inserted at the next block or operation bou nda ry
(depending on the setting in DX 0) and processed.
Note
If a specific time-driven interrupt OB is called for the second time
durin g the "Delay interrupt" phase, a collision of time interrupts
occurs.
Parameters
1. Control w ord
OB 123 records the interrupts to be disabled in a syste m-internal
co n trol w ord .
Bit no.: 15 3 2 1 0
C ontrol word
6
O B 123: Enable/Disable "Delay of Individual Tim e-Driven Inte rrupts"
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 25
The bits o f the control word are assigned as follows:
Bit no. Interrupt
0 to 2 Reserved; these bits must be "0"!
3 = ’1’
4 = ‘1‘
5 = ’1’
6 = ’1’
7 = ’1’
8 = ’1’
9 = ’1’
10 = ’1’
11 = ’1’
Time-driven interrupt wit h fixed time
intervals:
10 ms (O B 10)
20 ms (O B 11)
50 ms (O B 12)
100 ms (OB 13)
200 ms (OB 14)
500 ms (OB 15)
1 sec ( OB 16)
2 sec ( OB 17)
5 sec ( OB 18)
12 to 15 Reserved; these bits must be "0"!
2. Accus
2a) ACCU-2-L
Fu nc tio n No.
Permissible values: 1, 2 or 3 with:
1: The contents of ACCU 1 are loaded in
th e con trol word
2: All the bits in the mask in ACCU 1
marked with "1" are set t o "1". Th e new
control word is loaded in ACCU 1.
3: All the bits in the mask in ACCU 1
marked with "0" are set t o "1" in t he
contr ol word. The new control wo rd i s
loaded in ACCU 1.
2b) ACCU 1
New control word or mask depending on the desired function.
O B 123: Enable/Disable "Delay of Individual Tim e-Driven Inte rrupts"
CPU 928B Programming Guide
6 - 26 C79000-B8576-C898-01
Po ssib le errors
•• Illegal function number in ACCU-2-L
•• One of the reserved bits in ACCU 1 (no. 4 to 31) is set to ’1’
In th e ev en t o f error, OB 31 (other runtime errors) is called. If OB 31
is not loaded, th e CP U goes to th e S TOP mode.
In both cases, the error ID 1A4BH is entered in ACCU-1-L.
Notes
•• You can scan the status of the control word with the f ollowing
pro g ra m sequence:
1. Load the function nu mber 2 or 3 in ACCU-2-L
2. Load the value ’0’ in ACCU 1
3. Call special function OB 123
4. Read out ACCU 1
•• You ca n de te rm i ne t he st atu s of int errupt process in g by readi ng
out sys tem da ta word RS 137 .
- RS 137 Condition code word " delay individual
tim e- d r iven inter ru p t s"
6
O B 123: Enable/Disable "Delay of Individual Tim e-Driven Inte rrupts"
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 27
6.9 Settin g/R e a din g t he Syst em Time (O B 15 0)
Characteristics o f the
system time
•• The resoluti on is 10 ms for reading an d 1 sec for setting.
•• Leap years are taken int o accou nt.
•• You can select between a 24 hour clock and a 12 hour clock, " am "
(midnight to twelve o’clock), and " pm" (twelve o’clock to
midnight),
•• The weekday can be specified
•• Input and output in BCD.
•• The in t eg ral h ardw are cl oc k for th e s ys tem t im e is ba ck e d up by
the battery in the PL C rack. If you have set the sy stem time, it also
remains correct f ollowing a power down and WARM RESTART.
Function
Usi ng OB 150, yo u ca n set o r read th e date a nd t im e of t h e CPU 928B
in you r us er prog ram. T h e da te an d t im e a re k n o wn as th e "syste m
time".
Note
Before you can read out the sy stem time, i t mu st fir s t be set.
Parameters
1. Data Field for the T im e Parameters
When you set the system time, OB 150 takes the system tim e from a
data fie ld, wh e n yo u read the system time , OB 15 0 transfe rs the
cu rrent da ta to the data field . You c an set up this dat a fi eld in a data
block or i n on e of th e tw o flag areas (F or S flags).
The data f ield consists of f our words.
1a) Fo rmat of the data field for setting the hardware c lo ck
15 12 11 8 7 4 3 0Bit no.
Seconds
Format Hours Minutes
Day of month Weekday
Year Month
0
0
1st word
2nd word
3rd word
4th word
Set ting/Reading the System Tim e (O B 150)
CPU 928B Programming Guide
6 - 28 C79000-B8576-C898-01
1b) Format of the data f ield when reading the hardware clock
The ti me parame te rs h ave th e follo win g mea ni n g, permi tt ed ra ng e of
values and representation:
Pa ram ete r P er mitted range of values Representation
Seconds
1/100
seconds
Minutes
Hours
Weekday
Day of
month1)
Month
Year
00 to 59
00 to 99
00 to 59
00 to 23 or 01 to 12 depending
on selected format
0 t o 6 where Mo = 0,..., Su = 6
01 to 31 1)
01 to 12
00 to 99
BCD format
Format The format for the hour f ield is
as fol lo w s:
Bit 15 = 1: 24 hour f ormat
(bit 14 = 0)
Bit 15 = 0: 12 hour f ormat
(select "am" or
"pm" in bit 14)
B it 14 = 0: "am"
Bit 14 = 1: "pm"
--
1) The value you input is checked to ensure that the date is logically correct
t akin g into acc oun t l eap ye ars aft er O B 15 0 is calle d .
Da ta field in the flag area
If you set up the data f ield in a flag area, y ou m ust take into account
the f ollowing assignm ent of data f ield words to flag by tes. "x" is the
parameter "number o f the first data field word " (see followin g page)
that you must enter in ACCU-1-L when OB 150 is called.
Bit no. 15 8 7 0
1st data field word flag byte x flag byte x+4
2nd data field word flag byte x+1 flag byte x+5
3rd da ta field w o rd f l ag byte x +2 f la g byt e x+6
4th data f ield word flag byte x+3 flag byte x+7
15 12 11 8 7 4 3 0Bit no.
Seconds
Format Hours Minutes
Day of month Weekday
Year Month
1/100th second
0
1st word
2nd word
3rd word
4th word
6
Setting/Reading the System Time ( OB 150)
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 29
2. Accus
2a) ACCU-2-L
ACCU-2-L contains in formation on the desired function and the data
field used. It must have the f ollowing structure:
Function number,
permitted values: 1 = set system time
2 = Read system time
Address area type,
permitted values: 1 = DB data block
2 = DX d ata block
3 = F f l ag ar e a
4 = S flag area
Data block n umber,
permitted values: 3 to 255
(only for address area type 1 or 2;
irrelevant for address area types 3 or 4)
2b) ACCU-1-L
Number of the 1st data fie ld word,
possible val ue (depend ent on the address
area type): DB, DX: 0 to 2044
F flags : 0 to 248
(= no. of f lag byte ’x’)
S flags : 0 to 1016
(= no. of f lag ’x’)
Result
After OB 150 has been proc essed correctly, the condition code bits
OR, ERAB and OS = 0. All other condition code bits and ACCUs 1
a nd 2 r e ma in un change d.
Po ssib le error s:
I n the event of an err or , OB 19 or OB 31 is called. If OB 19 or OB 31
i s not loaded, th e CPU goes t o th e stop mo de.
In both ca ses, e rro r I Ds are e ntered in A CC U 1 an d AC CU 2 (see
foll owing ta b le).
Function no. Address area type Data block no.
15 12 11 8 7 0Bit no.
Set ting/Reading the System Tim e (O B 150)
CPU 928B Programming Guide
6 - 30 C79000-B8576-C898-01
ACCU-1-L ACCU-2-L Cause of error O B called
1A07H - Data block not loaded OB 1 9
1A4CH 0001H
0100H
0101H
0102H
0103H
0201H
0202H
0203H
0204H
0205H
0206H
0207H
0208H
0209H
020AH
Function no. = 0 or > 2
Address area type illegal
Data blo ck nu mber ille gal
"Number of the first data field word" illega l
Data block length in b lock header < 5 wor ds
Yea r specified in da ta fie ld illegal
Mon t h specified in da ta field i ll egal
Day of month specified in data field illegal
Weekday speci fied in data fiel d ille gal
Hour specified in data field illegal
Mi nute speci fied in data fiel d illegal
Se con d sp ecifi ed in data field illegal
1/100 second in data f ield not equal to 0
Data f ield word 3 / bit no. 0 to 3 ≠ 0
H our format no t the same as se tting in OB 151
O B 31
Note
If you select incorrect parameters when setting the s yste m time,
an d if th e time h as been s et correc tl y at leas t o nce, t h e er ror I Ds
are trans fe rre d , howev er, the pre vi ous ly se t system ti me is
retained.
Example
Table 6-2 OB 150 error IDs
"Setting the time"
You wa nt t o set the sy stem t ime as f ol lows :
"Thurs, 24.11.1991, 11:30, 0 seconds, 24 hour format"
It is assu me d th at t he tim e para mete rs wil l be s tore d in d ata bl ock
DB 10 from d ata word D W 0 on ward s. T he sys tem ti me s houl d be s et
accurate to the second by triggering a process interrupt (trigger bit,
e.g. I 1.0 - button in the vicinity of the PLC).
First, program data block DB 10 with the following values and load it in
the PL C. Y ou mus t in cl ude th e ST EP 5 o pera tion s for call in g OB 1 50 i n
OB 1 i n su ch a w ay t ha t th e oper atio ns for cal li ng O B 15 1 are on ly
execut ed i n the case o f a ri sing edg e of t he t ri gger bit :
Continued on the next page
6
Setting/Reading the System Time ( OB 150)
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 31
"Reading the system time":
You wa nt t o writ e th e curr en t sy stem t ime to d at a bl ock DB 10 fr om d ata
word DW 4. You must therefore call OB 150 with the following parameters:
:
:L KH 2 1 0 A Va lues for ACC U- 2-L:
: DB no . = 10
: Address area type = 1 for "data field in DB"
: Fun ct ion no . = 2 for "r ea d"
:
:L KF +4 ACCU-1-L
: Numbe r of 1 st dat a fi el d wo rd = 4
:JU OB 150 Call OB 150
:C DB 10 Open DB 10
: Evalu at e DB 1 0
After call in g OB 150 , the ac tual sys te m ti me i s stor ed i n the fo llow ing
form i n th e data blo ck DB 10 ("T hurs , 24.1 0.93 , 11:3 0, 2 0 seco nd s, 1 3
hundre dths , 24 h our fo rmat ") :
DW 4: KH= 2 0 1 3 Seconds = 20 (BCD)
1/100 seconds = 13 (BCD)
DW 5: KH= 9 1 3 0 For mat = 24 h ou r (b its 14 /15 = 01 ), hou rs = 1 1
(BC D) , Minu te s = 30 (BC D)
DW 6: KH= 2 4 3 0 Day of month = 24 (BCD)
Day of week = 3 = Thursday
DW 7: KH= 9 1 1 0 Year = 93 (BCD)
Month = 10 (BCD)
"Setting the time":
(continued)
DB 100: KH= 0 0 0 0 left byte = seconds (BCD), right byte = 0
1: KH= 9 1 3 0 91 = format (=80H) + hour (= 11 BCD)
30 minutes (BCD)
2: KH= 2 4 3 0 24 = day of the month (BCD)
30 = d ay o f week (3 = Thur sd ay) + bi t 0 to bit 3 = 0
3: KH= 9 1 1 0 93 = year (BCD)
10 = month (BCD)
The STEP 5 operations in OB 1 for calling for OB 150 are as follows:
: Signal edge of the input for setting the system
time has occurred
STELL:L KH1 1 0 A Values for ACCU-2-L:
: Addres s ar ea typ e = 1 for "d ata fiel d in D B"
: Function number = 1 for "set"
:
:L KF +0 ACCU-1 -L :
: Number of the 1st data field word = 0
:JU OB 150 Call OB 150
:
Set ting/Reading the System Tim e (O B 150)
CPU 928B Programming Guide
6 - 32 C79000-B8576-C898-01
6.1 0 OB 1 5 1: S e ttin g/R e a din g t he Time fo r Clock -D riv e n In te rrupts
Function
By calling OB 151 yo u can perform th e fol lowing :
•• p rogram t he CPU 928 B, to act iv ate the cl oc k- dri ven time
in te rrupt ("Time jo b" - OB 9, see Sec tion 4.5.2) at a
preset ti me :
- every minute
- every hour
- every da y
- every week
- every month
- every year
- onc e
•• rea d ou t th e current statu s of a t im ed j ob
•• cancel a previously generated ti med job
You ca n call OB 151 in the mo des R EST ART a nd R UN. Once
generated, a clock-controlled time interrupt is retained follo wing a
WARM RESTART (automatic or m anual). A COLD RESTART
clears an existing tim ed job.
If you generate a new tim ed job, a currently programmed tim ed job is
automati cally ca nc ell ed. T his me ans t ha t on ly one clock-controlled
time interrupt can be active.
Parameters
1. Data Field for Job Param eters
When you generate or cancel a timed job, OB 151 takes the required
job parameters from a data field.
When you read out the current st at us of a timed job, OB 151 transfers
th e cu rren t job param et ers to a d at a fi el d.
You can set up this data field in a data bloc k o r in one of the two flag
areas ( F or S fl ags) .
The data field con s i sts of fo ur wo rds an d has th e fo llow ing format for
both generating and reading out a timed job:
15 12 11 8 7 4 3 0Bit no.
Seconds
Format Hours Minutes
Day of month Weekday
Year Month
0
1st word
2nd word
3rd word
4th word
Job type
6
OB 151: Setting/Reading the Time for Clock-Driven Interrupts
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 33
T he parameters have the following meanings, permissible value
ranges an d represe n tations:
Parameter P erm issible ran ge of values Represent atio n
Job type 0 to 7 where:
0 = cancel job or no
job active
1 = every minute
2 = every hour
3 = every day
4 = every week
5 = every mo nth
6 = every year
7 = o nce
BCD forma t
Seconds
1/ 100 second
Minutes
Hours
Weekday
Day of
month1)
Month
Year
00 to 59
00 to 99
00 to 59
00 to 23 or 01 to 12 depen din g
on the s elected format
0 t o 6 w h ere Mo = 0,. .., Su = 6
01 to 31 1)
01 to 12
00 to 99
BCD forma t
Format 2) The format of the hour field is
as fol lows :
Bit 15 = 1: 24 hour fo rma t
(bit 14 = 0)
Bit 15 = 0: 12 hour fo rma t
(sel ec t "am" or
" pm" in bi t 1 4)
Bit 14 = 0: "am"
Bit 14 = 1: "p m"
--
1) After calling OB 150, the value speci fied is checked to ensure it is logically
co rrect taking into account leap years .
2) For the significance of "am" and "pm", see OB 150 in the previous section:
"Format" must agre e with the format set for the system time in OB 150.
Da ta field in the flag area
When you set up the data field in a f lag area, you m ust take into
account the following assignment of the data field words to the f lag
bytes. "x" is th e parameter "n umber of the first d ata fiel d word" that
you must enter in ACCU-1-L when OB 151 is called.
Bit no. 15 8 7 0
1st data field word flag by te x flag byte x+4
2nd data field word flag by te x+1 flag by te x+5
3rd data f ield word flag by te x+2 flag by te x+6
4th data field word flag byte x+3 flag by te x+7
O B 151: Setting/Reading t he Tim e for Clo ck- Driven Inte r rupts
CPU 928B Programming Guide
6 - 34 C79000-B8576-C898-01
2. Accus
2a) ACCU-2- L
ACCU-2-L contains in formation on the desired function and the data
field used. It must have the f ollowing structure:
Parameters in ACCU-2-L
Function number,
permitted values: 1 = generate job
2 = read job
Address area type,
permitted values: 1 = DB data block
2 = DX d ata block
3 = F f l ag ar e a
4 = S flag area
Data block n umber,
permi tted values: 3 to 25 5 (fo r ad d ress area type = 1 o r 2;
irrelevant for address area type 3 or 4
2b) ACCU-1-L
Number of the 1st data fie ld word,
possible values (dependent o n the
a ddress area type):
DB, DX: 0 to 2044
F flags: 0 t o 248
(= no. of f lag by te ’x’)
S flags: 0 to 1016
(= no. of f lag by te ’x’)
Note
It is pointless to generate a timed job cyclically (e.g. by m eans of
an un condit ional OB 151 c all wit h fun ction n umber 1 in OB 1).
Result
After OB 150 has been proc essed correctly, the condition code bits
OR, ERAB and OS = 0. All other condition code bits remain
unchange d, as do ACCU 1 a nd ACCU 2.
Function no. Address area type Data block no.
15 12 11 8 7 0Bit no.
6
OB 151: Setting/Reading the Time for Clock-Driven Interrupts
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 35
Note
If the job type "0" is se t in the data fiel d and all ot he r p ara me ters
are "F" or "FF" (hexadecimal) when you read out a timed job,
then n o tim ed job is active.
This status can occur as follows:
a) follo wing a CO LD RESTART, when no timed job is generated,
b) when a tim ed job programmed to be executed only once has
been executed
or
c) when y ou have cancelled a job.
Po ssib le error s:
I n the event of an err or , OB 19 or OB 31 is called. If OB 19 or OB 3 1
i s not loaded, th e CPU goes t o th e stop mo de.
In both ca ses, e rro r I Ds are e ntered in A CC U 1 an d AC CU 2 (see
foll owing ta b le).
ACCU-1-L ACCU-2- L C ause of error OB calle d
1A07H - Data block not loaded OB 1 9
1A4DH 0001H
0100H
0101H
0102H
0103H
0201H
0202H
0203H
0204H
0205H
0206H
0207H
0208H
0209H
020AH
Function no. = 0 or > 2
Address area type illegal
Data blo ck nu mber ille gal
"Number of the first data field word" illega l
Data block length in b lock header < 5 wor ds
Yea r specified in da ta fie ld illegal
Mon t h specified in da ta field i ll egal
Day of month specified in data field illegal
Weekday speci fied in data fiel d ille gal
Hour specified in data field illegal
Mi nute speci fied in data fiel d illegal
Se con d sp ecifi ed in data field illegal
1/100 second in data f ield not equal to 0
Job type in data field > 7
H our format no t the same as se tting in OB 150
O B 31
Note
If you assign incorrect parameters and a valid tim ed job has
already been ge nerated, the error i dentifiers are trans ferred as
indica ted ab o v e, h owever, the previously genera ted timed job
is retained.
Table 6-3 OB 151 error IDs
O B 151: Setting/Reading t he Tim e for Clo ck- Driven Inte r rupts
CPU 928B Programming Guide
6 - 36 C79000-B8576-C898-01
Im po rtant po ints
concerning time parameters
Depen ding on when you want to trigger a clock-driven time interrupt
(timed job) you must select the individual time parameters in certain
com bi nat io ns. Depend in g o n th e time you sel ec t for the cl o ck-driven
time i nterrupt, you m u st speci fy c ert ai n param et ers, while o the rs are
not evaluated by the system program and can therefore be ignored.
The follow i ng table indic ates whi ch time param e ters must be
speci fie d for which ti med job (XXX = must be specified,
--- = irrelevant).
T ime of interrupt Seconds Minu-
tes Hours Week-
day Day
of
month
Month Year
every minute
every hour
every day
every week
eve ry month
every year
once
XXX
XXX
XXX
XXX
XXX
XXX
XXX
---
XXX
XXX
XXX
XXX
XXX
XXX
---
---
XXX
XXX
XXX
XXX
XXX
---
---
---
XXX
---
---
---
---
---
---
---
XXX
XXX
XXX
---
---
---
---
---
XXX
XXX
---
---
---
---
---
---
XXX
Special feat ures
•• If you sele ct t he j ob type "every year" (= 6) an d se lect " February
29th" as the day of the month and m onth, then OB 9 will only be
c alle d every l eap ye ar .
•• If you select the job type " every month" (= 5) and select the value
"29" , "30" or " 31" then OB 9 will only be called in the months
containi ng these date s .
Examples
Tabl e 6-4 "Ti me job - Time parameter" assi gnments
Various timed jobs (24 hour format):
1. "Jo b at t he 2 9th se cond o f ev ery mi nute "
(12:44:29, 12:45:29 etc):
You m ust sp ecif y th e foll ow ing: j ob typ e = 1 (Fun ct ion no. in
AC CU-2 -L = 1 )
seconds = 29
2. "Jo b ev er y ho ur a t xx:1 4: 15":
You m ust sp ecif y th e foll ow ing: j ob typ e = 2 (Fun ct ion no. in
AC CU-2 -L = 1 )
seconds = 15
minutes = 14
Continued on the next page
6
OB 151: Setting/Reading the Time for Clock-Driven Interrupts
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 37
Various timed jobs (24 hour format):
(continued)
3. "J ob d ai ly a t 5: 32 :47"
You mu st s pe cify the f ollo wi ng: jo b type = 3 (Fun ct ion no . in
AC CU-2 -L = 1 )
seco nd s = 47
minu te s = 32
hours = 05
4. "Job every week at 10:50:00":
You mu st s pe cify the f ollo wi ng: jo b type = 4 (Fun ct ion no . in
ACCU-2-L = 1)
seco nd s = 00
minu te s = 50
hours = 10
weekda y= 01
5. "Job every month, on the 14th at 7:30:15":
You mu st s pe cify the f ollo wi ng: jo b type = 5 (Fun ct ion no . in
ACCU-2-L = 1)
seco nd s = 15
minu te s = 30
hours = 07
day of mon th = 14
6. "Job every year, on May 1st at 00:01:45":
You mu st s pe cify the f ollo wi ng: jo b type = 6 (Fun ct ion no . in
ACCU-2-L = 1)
seco nd s = 45
minu te s = 01
hours = 00
day of mon th = 01
mont h = 05
7. "J ob o n Dece mber 3 1st 19 99 a t 23 :5 5:00 ":
You mu st s pe cify the f ollo wi ng: jo b type = 7 (Fun ct ion no . in
AC CU-2 -L = 1 )
seco nd s = 00
minu te s = 55
hours = 23
day of mon th = 31
mont h = 12
year = 99
Continued on the nex page
O B 151: Setting/Reading t he Tim e for Clo ck- Driven Inte r rupts
CPU 928B Programming Guide
6 - 38 C79000-B8576-C898-01
Various timed jobs (24 hour format):
(continued)
8. "C an cel jo b" :
You must specify the following: job type = 0 (Function no. in
ACCU-2-L = 1)
9. "R ea d out ti me d job" :
You must specify the following: function no. in ACCU-2-L = 2
If no job i s ac tive , you re ceiv e th e foll owin g resu lt i n the da ta f ield :
Data f ield w ord 0: FFFF H
Data f ield w ord 1: FFFF H
Data f ield w ord 2: FFF0 H
Data f ield w ord 3: FFFF H
6
OB 151: Setting/Reading the Time for Clock-Driven Interrupts
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 39
6.11 O B 152: Cycle Statistics
A series of statistical data relating to the duration of the cycle can be
recorded in the CPU 928B ( c ycle statistics). Using OB 152, you can
initia lize th e cycle stat ist ics, r ead out th e sta tist ical da ta a nd enable
and disable the recordin g of statistical data.
Overview
The statistical data include the f ollowing:
•• t he duratio n of the previous cycle,
•• the time elapsed in the currently active cycle since the last cycle
boundary,
•• the minimum and maximu m cycl e tim e si nce the las t initialization
of th e cycle statist ics,
•• t he nu mber of c ycles since the last initialization of the cycle
statistics,
•• the average cycle tim e: a maximum of the last 256 cycles recorded
in t he st at isti cs are us ed t o calc ul at e the average v al u e.
Note
Only " norm al" cycles are recorded in the cycle statistics. If the
recordin g o f th e du rat io n o f th e current cycle wou l d fals ify the
cycle sta ti st ic s, e .g . by retrig g erin g o r restartin g th e cycle
monitoring time, these data are not included in the statistics. This
mea ns that "mavericks " do not affect the statistics.
This does, however, have the ef fect that if the cycle monitoring
time is repeatedly restarted, then only a fe w or eve n no data will
be recorded for the statistics (please see in this context the Notes
at the end o f Sectio n 6.11 "F al sify ing the statistical data").
En abl in g/di sabl in g the
statistics function
Foll ow i ng a C OLD R EST ART (au t omatic or m a n ual), the sta tist ic s
function is always disabled and the statistical data are deleted (the
cycle statistics are initialized). A WARM RESTART (automatic or
manual) does not affect the statistics f unction or the statistical data.
You can activate the statistics function in the RESTART or RUN
modes us ing OB 152.
O B 152: Cycle S t atisti c s
CPU 928B Programming Guide
6 - 40 C79000-B8576-C898-01
I f the s tatistics fu nctio n is enab led w ith OB 15 2 , the statis tical data a r e
updated at each cycle boundary and you can read them out by calling
O B 152.
If you no lon ger require th e st at ist ic s fun ct ion , you can di sa bl e th e
fu nction in the RES TART or RUN modes, onc e again using OB 152.
This reduces the cycle tim e load caused by the updating of the cycle
data at each cycle boundary.
You can also initialize the cycle statistics using OB 152 in the
RESTART or RUN modes. It may, f or example, be useful to initialize
the cycle statistics after evaluating the statistical data (possibly also
depend ent o n th e valu e of the cycle cou nter).
Statistical data
The stat istic al d at a are read o ut di rec tl y as ind iv idu al v al ues us in g
OB 152 or calculated when OB 152 is called. They are transferred by
OB 152 to ACCU-1-L or ACCU-2- L.
Yo u ca n dete rm i ne the follow i ng sta tistic al val ue s by cal ling OB 152:
Statistical
value Significance Format Unit Range of
values
LASTCYC Duration of the last co mpleted c ycle. Fixed
point
number
Milli-
seconds 0 to 13000
CURCYC T ime already elapsed in the current cycle. Fixed
point
number
Milli-
seconds 0 to 13000
MINCYC Duration of the shortest cycle since the last
in itialization of th e cy cle statis tics. Fixed
point
number
Milli-
seconds 0 to 13000
MAXCYC Duration of the longest cycle since the last
in itialization of th e cy cle statis tics. Fixed
point
number
Milli-
seconds 0 to 13000
AVERAGE Average of the cycle tim es of the last
(m aximu m 256) cycles 1) Fixed
point
number
Milli-
seconds 0 to 13000
CYCLE
COUNTER N umber of cycles recorded i n the statistics
since the la st initi alizat ion of the cy c le s tati stics. Hexa-
decimal
number
Number
of cycles 0 to
0FFFFH
1) see "calc ul atio n of the average v alue "
Ta ble 6-5 Cy cl e stati stics va riables - OB 152
6
OB 152: Cycle Statistics
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 41
Calculation of the average
value
T he a ver age value is c al cu la te d by O B 152 u sing t he fo ll owing
algorithm:
Each tim e the statistical data are updated, the value of LASTCYC is
ent ered i nto a n in te rna l system buffer each time the statistical data are
updated. This buffer can take a maxim um of 256 values. If the buf fer
is f ull, the oldest LASTCYC value is lost and the newest value is
ent ered. Duri ng t he u pdatin g o f the da ta , t h e sum o f th e LASTC YC
values in the buffer is f ormed so that it alway s contains the most
recent LA STCYC values (maximum 256).
When OB 152 is call ed , th e av era ge v alue i s forme d by di viding the
total by the number of LASTCYC values stored in the buffer. In
practical terms, this m eans that the average value is alm ost alway s
for me d fro m th e LA ST CYC va lues of the las t 25 6 cyc les.
Functions
When OB 152 is call ed , you can a ct iv ate th e following i nd i vi d ua l
fun c ti on s by mea ns o f a function nu mber:
Func-
tion no. Function
0 Di s abl e cycle st atistics
1 Read CU RCY C / LAST CYC
2 Read MINCYC / MAXCYC
3 Read AVER AGE VALUE / CYCLE COUNTER
8 In itial ize cycle sta tistics
15 Enable cycle statistics
T able 6-6 OB 153 functions
O B 152: Cycle S t atisti c s
CPU 928B Programming Guide
6 - 42 C79000-B8576-C898-01
Parameters
ACCU-1-L
AC CU-1-L c o nt ai n s the fu nc ti o n no .; it mu st ha v e t h e fo ll o win g
structure:
Function no.,
permitted values: see table 6-6
Bit nos. 4 to 15 must alway s be 0!
Result
After OB 152 is called, the condition codes OS, OR and ERAB = ’0’,
the RLO is also 0 except in the cases listed below. In addition to this,
the statistical values requested by some functions are transferred to
ACCU-1-L and ACCU-2- L with some functi ons (see table bel ow).
Function Results of the functions
ACCU-1-
LACCU-2-
LSignificance
of "RLO = 1"
Disable cycle statistics Unchanged --
Read CURCYC / LASTCYC CURCYC LAST-CYC CURCYC is incorrect,
t he data of the current
cycle are no t u sed i n th e
statistic s 1)
Read MINCYC / MAXCYC MINCYC MAXCYC --
Read AVERAGE VALUE / CYCLE
COUNTER AVERAGE
VALUE
CYCLE
COUNTER C YCLE COUNTER
overflow 2)
Initialize cy cle stat ist ics Unchanged --
Ena ble cycle statistics Unchanged --
1) Due to s tartin g /re startin g th e cycl e monit ori ng time , c ycl e error or WA RM RESTAR T
2) If RLO = 1 is set when you read out the cycle counter, then when the condition code is transferred, a system
intern al flag f or cycle ove rflo w is cleare d. This fl ag is then only se t again wh en the cycle co unte r o ve rflo ws again.
15 0Bit no. 4 3
Function no.0
Table 6-7 Results of the OB 152 functions
6
OB 152: Cycle Statistics
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 43
Po ssib le errors
An error occu rs if an in cor re ct fu nc ti on no . is tran sf e rred to
ACCU-1-L (only the numbers 0 t o 3, 8 and 15 are permissible).
I n the event of an err or , OB 31 (other runtime errors) is calle d. I f
OB 31 is not loaded, the CPU goes to the stop mode.
In both cases, the error ID 1A4EH is entered in ACCU-1-L and
0001H is en tered in ACC U-2-L.
Special Features
T his section explains sev eral special features of OB 152 during a
COL D RESTART, f ollowing a RESTART or when certain events
occur and you should take note of these points if you want to use
O B 152.
Reaction to a COLD
RESTART
T he statistical data are initialized during a CO LD REST ART. Calling
OB 152 in the first cycle following CO LD RESTART reestablishes
the initia liza tion data .
The f ollowing table shows how the statistical data are
•• initialized f ollowing a COL D RESTART
and
•• mo difi ed d u rin g th e first three cyc le s by th e syst em prog ram .
CURCYC
1) --- --- CU RCYC (1.) --- CURCYC (2.) --- CURCYC (3.)
LASTCYC 0 0 0 Cy cle ti me (1.) Cy cl e tim e (1.) Cy cl e tim e
(2.) Cycle time
(2.)
MINCYC 13 000 13 000 13 000 Cycle time (1.) Cy cle ti me
(1.) min. c.t. min. c.t.
MAXCYC 0 0 0 Cycl e time (1.) Cy cle time
(1.) max. c.t. max. c.t.
AVERAGE 0 0 0 Cy cle ti me (1.) Cy cle ti me
(1.) a ve r. c.t . aver. c.t.
CYCLE C.0001122
1) The val ue fo r CURCYC is alway s re ad o ut via OB 152, th e cy cle mo n itorin g tim er. Fo r th is reason , it is alre ad y
available during the first cycle.
COLD
RESTART
Initialization of
stat. data by
sy s tem pr og r am OB 20
OB 152:
"stat. on."
1 s t cycl e
Update
stat. data
by system 2nd cyc le
Update
stat. data
by sy s t em
program 3 r d cycl e
OB 152:
"read stat." OB 152 :
"read stat."
OB 152:
"r ead sta t."
O B 152: Cycle S t atisti c s
CPU 928B Programming Guide
6 - 44 C79000-B8576-C898-01
When the statistical data are initialized, not only the def aults listed in
the ta ble, bu t a lso the in te rna l system buf f er fo r th e av era ge a re
delete d and an internal flag for cycle counter over flow is reset.
Calling OB 152 in a start-up
OB
Depen din g on the type of restart, the OB 152 call t o read the statistical
data pro vi d es th e fol lo w in g v alu es in ACC U -1-L an d AC CU-2-L
(columns on a gray background).
CURCYC --- --- 0 CURCYC 0
LASTCYC 0 0 0 LASTCYC Cy cle time (n-1)
MINCYC 1 3 000 13 000 13 00 0 M INCYC incl. cyc. (n-1)
MAXCYC 0 0 0 MAXCYC incl. cyc. (n-1)
AVERAGE 0 0 0 AVERAGE incl. cyc. (n-1)
CYCLE C 0 0 0 CYCLE C. n-1
OB 20
Initialization of
stat. data by
sy s tem pr og r am
COLD RESTAR T
OB 152:
"stat on" OB 152:
"read stat." OB 152:
"r ead sta t."
OB 21/22
WARM RESTART in cycle n
6
OB 152: Cycle Statistics
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 45
Initializing the statistical data
by cal ling O B 15 2
The f ollowing table shows how the statistical data are changed when
t hey are initialized by calling OB 152 in the CYCLE. The colu mns
with a gray background contain the values transferred when the
st atistic al d ata are read .
CURCYC CURCYC(n-1) --- C URCYC (n) --- T --- CURCYC (n+1)
LASTCYC Cy cl e tim e (n-2) Cy cl e tim e (n-1) Cycle time (n-1) 00no 0
MINCYC incl. cyc. (n-2) incl. cyc. (n-1) incl. cyc. (n-1) 13 000 13 000 n o 13 000
MAXCYC incl. cyc. (n-2) incl. cyc. (n-1) incl. cyc. (n-1) 00no 0
AVERAGE incl. cyc. (n-2) incl. cyc. (n-1) incl. cyc. (n-1) 00no 0
CYCLE C. n-2 n-1 n-1 0 0 n o 0
When the statistical data are initialized, not only the def aults listed in
the table, but also the system internal buffer for forming the average
value is deleted and an internal f lag for cycle counter overflow is reset.
Afte r th e sta ti st ic al d at a are i nit ia lize d by c al li ng OB 152, t h e da ta are
only updated by the system program at the end of the first cycle after
the initia liza tion.
Cal ling O B 152 when th e
cycle statisti cs are disabled
If you d is able t he c yc le st at is ti cs by c al li n g OB 152, t h e s ta ti sti ca l
dat a of the last update are retaine d. If you t hen use OB 152 to read
t he statistical data, it supplies the data fr om the last update be fore the
statistics were disabled.
If you read the statistical data following a COL D RESTART, without
enabling the cycle statistics with an OB 152 call, OB 152 supplies the
initia liza tion data .
Cycle (n+1)
OB 152:
"read stat."
Update
(n) (n+1)
Update
T
OB 152:
"read stat." OB 152:
"init. stat." OB 152:
"read stat." OB 152:
"read stat."
O B 152: Cycle S t atisti c s
CPU 928B Programming Guide
6 - 46 C79000-B8576-C898-01
F alsif yi ng t he stat isti cal data
Certai n events can cause problems when recordi ng the cycle length of
the cu rren t cycl e and ca n le ad t o inc orrect va lu e s. I n t hese situ at ion s,
the statistical data for the cycle affected are not updated.
These events include the following:
•• WARM RESTART
•• Starting the cycle monitoring time by calling OB 221
•• Restartin g th e cycle m onitoring time by calling OB 222
•• Cy c le er rors
CURCYC CURCYC --- 1) --- CURCYC
(n+1)
LASTCYC Cycle time
(n-2) Cycle time
(n-1) Cycle time
(n-1)
no Cy cl e tim e
(n-1)
MINCYC i nc l. cy c . (n- 2) incl. cy c. (n-1) incl. cyc. (n-1) no incl. cyc. (n-1)
MAXCYC incl. cy c . (n-2) incl. cyc . (n- 1) incl . cyc. ( n-1) no incl. cyc. (n-1)
AVERAGE incl. cy c . (n-2) incl. cyc . (n-1) i ncl . cyc. (n-1 ) no incl. cyc. (n-1)
C Y CLE C n-2 n-1 n-1 no n-1
1) The value of CURCYC corre sp ond s to t he time T t hat has e lap se d since t he o c curren c e of the "pro blem" in the
current cycle. This i s not the length of the whole cycle. To indicate this situation, the RLO is set to "1" in addition
to the values transferred to ACCU-1-L and ACCU-2-L.
Cycle (n-1)
Update
(n) (n+1)
OB 152:
"read stat." OB 152:
"read stat." OB 152:
"read stat."
Interruption by:
WARM
RESTART
OB 221/222
cycl e er ror
Update
6
OB 152: Cycle Statistics
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 47
6.12 OB 153: Set/Read Time for Delayed Interrupt
Usin g OB 153, you can trans fer so-called "delay jobs" to the syste m
prog ram . A fte r a specified d el ay time "a d el aye d in ter rupt" is then
processed (refer to OB 6, Section 4.5.2).
Function
By calling OB 153, you can do the f ollowing:
•• define and start a delay time,
•• stop an activated dela y time (cancel delay job),
•• read how long the delay time still has to run.
A delay job can be activated in the START UP and RUN modes.
Life of a delay job
The dela yed interrupt triggered b y a dela y job is only acti vated by the
system program in the RUN mode (OB 6 call).
Jobs which becom e due in a m ode other than RUN are discarded by
the system program without any m essage.
A currentl y active (but not yet due) job is also discarded if the CPU
cha ng e s t o the STOP mode o r if t h e pow er i s s wit ch ed off .
Parameters
Accus
a) ACCU-2-L
Delay t ime in mil li sec onds (max . 65535)
Permit ted va lu e s:0001H to F FFFH
ACCU-2-L onl y needs to be supplied with the function nu mber ’1’
("define delay time") when OB 153 is called. The contents of
AC CU-2-L a re n o t eval u at ed i n the re ma in i ng OB 153 fun c ti ons.
b) ACCU-1-L
Function no.
Permit ted va lu e s: 1 = d e fi n e an d sta rt d e la y ti me
2 = stop delay time (= cancel jo b)
3 = read re maining delay time
O B 15 3 : S et/Read Time for De l ay e d I n ter r upt
CPU 928B Programming Guide
6 - 48 C79000-B8576-C898-01
Note
If a previously defined delay time is not yet elapsed when a
further delay ti me is defined, the previously de fined time is lost
and the new del ay tim e started.
Result
Afte r co rre ct proc es sin g o f OB 153, th e co n diti o n co de bits OR,
E RAB and OS = 0.
When OB 153 is c alled with the function no. ’2’ or ’3’, ACCU-1-L
contains the remaining tim e to run in m illiseconds.
If no delay job is active when OB 153 is called with function no. ’2’
or ’3’, AC C U-1-L co nta ins the valu e ’0’.
Po ssib le errors
The er ro rs li s ted in t he f ol lowin g t abl e can occur.
OB 31 (oth er runti me errors) is called . If O B 31 is n ot loaded , th e
CPU goes to th e S TOP m ode.
In bot h ca ses, e rror IDs are ent ered in A C CU -1-L an d A C CU-2-L (se e
t he table below).
ACCU-1-L ACCU-2-L Bedeutung
1A4FH 0001H
0002H Function no . = 0 or > 3
Ill eg a l delay time
Examples
Table 6-8 OB 153 error IDs
Define and start delay time:
When an A UT OMAT IC W AR M RE ST ART is p er form ed, af ter 5 se co nds a cert ain
STEP 5 operation sequence must be run through once. To do this, the
delay time is defined and started in start-up organization block OB 22.
The S TEP 5 oper atio ns in OB 22 for ca llin g OB 1 53:
:
:
:L KF +5000 Value for ACCU-2-L: 5000 ms
:L KF +1 Value for ACCU-1-L: function no. = 1 for
: "define and start delay time"
:JU OB 153 C al l OB 153
:
6
OB 153: Set/Read Time for Delayed Interrupt
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 49
Stop delay time (cancel job)
STEP 5 operations for calling OB 153:
:
:
:L KF +2 Value for ACCU-1-L: function no. = 2 for
: "stop delay time"
:JU OB 153 C al l OB 153
:
Read out remaining time of a delay job:
STEP 5 ope ra tion s fo r call in g OB 153 :
:
:
:L KF +3 Value for AC CU-1 -L: fu ncti on no. = 3 f or
: "rea d ou t rema in ing ti me"
:JU OB 153 Call OB 153
:
: ACCU-1-L contains the time the delay job still
has to run .
O B 15 3 : S et/Read Time for De l ay e d I n ter r upt
CPU 928B Programming Guide
6 - 50 C79000-B8576-C898-01
6.13 O B 160 to 163: Loop Counters
By us in g the se special functio n o peratio n blo cks, you c an implement
progra m loops with a partic ularly fast runtime.
Function
A syst em dat a word i s a ssign ed to e ac h of t he fou r spec ial fun ct ion
OBs as follo ws:
•• RS 60: OB 160
•• RS 61 : OB 161
•• RS 62 : OB 162
•• RS 63 : OB 163
Programming the
p ro gram lo op
You tran sfe r th e va lu e for t h e re qui re d n umber o f loo p repetit ion s t o
one of these system data words. When you then call the appropriate
spec ia l funct io n OB, th e l oop co unt er in th e syste m da ta w ord is
dec remented by 1. Th e lo op is repea te d unt il the lo op co unte r reac hes
the valu e ze r o.
Note
If th e loo p co u nt er i s alread y ze ro bef ore th e specia l funct io n OB
is called, it is decremented by 1; the loop is then run through
65,536 times.
Parameters
System data w ord RS 60 - 63
Loop c ounters
possible v alues : 0 - 65 535 decimal (0 to FFFFH)
6
O B 160 to 163: Loop Counters
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 51
Result
Loop counter in RLO is set (RLO = 1)
sys tem data word >0:
Loop counter in RLO is cleared (RLO = 0)
sy stem data word = 0:
The other bit and word condition codes are always cleared.
The accumulato rs a re not changed and not evaluat ed. This mean s that
the y are sti ll a vail able a t th e be gin n ing o f th e nex t l o op a n d do n ot
need to be set again.
Po ssib le errors
none
Example
For a further example, refer to Section 9.3 "TNW a nd TNB:
Tr ansferr ing M emory Fi elds" .
Programming a loop counter:
The re quir ed num ber of loo p repe titi on s is con ta ined in fl ag w or d x.
:
Initia lize :L K B0
the lo op: :L F Wx Loop co unte r
:!=F
:JC =M002
:T RS 62 Transfer loop counter
: to sy stem d ata word
:
:
"Loop .
program": M001 :
:.
:.
:.
:
Manage loo p: :JU OB162 Loop counter
:JC =M00 1 I f RLO = 1 th e
: loop is r un
: throu gh a ga in
Furthe r
prog ra m M 002 : .
:.
:.
:.
O B 160 to 163: Loop Counters
CPU 928B Programming Guide
6 - 52 C79000-B8576-C898-01
6.14 O B 170: Read Block Stack (BSTACK)
Starting with OB 1 or FB 0, the block stack contains all the blocks
that have been called in sequence and that have not yet been
comp letely processed.
Function
Using the special f unction organization block OB 170, you can read
t he entries currently in the BSTACK i nt o a data block. In this way,
you can find out how many entries are currently in the BSTACK and
how much space is still available for further entries.
For each entr y, you obtain the return a ddress (step a ddress coun ter =
SAC ), th e abso l ut e sta rt a ddress o f t he data bl ock v al id i n thi s blo c k
(DBA) and its length (number of data words = DBL).
Note
Bef ore you call OB 170, you m ust f irst open a data block (DB or
DX) with sufficient length. Four data words are required for
e ach BS TA CK e ntr y.
Parameters
Accus
a) ACCU-2-L
Number of the data word (DW n) from which the entries are to be
stored in the open DB (offset)
b) ACCU-1-L
Required number o f BSTAC K ele ments;
Possible values : 1 - 62
Example: if ACCU-1-L con tains the value "1 ", you obtain th e last
BSTACK entry, if it contains "2", you obtain the last
and one before l ast etc.
6
OB 170: Read B lock S tack (B ST A C K )
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 53
Result
After OB 170 has been called successfully
•• th e offset in the d at a bl o ck i s still co n ta in ed i n ACCU-2-L
•• the actual number of BSTACK eleme nts represented is in
AC CU-1-L 1)
•• The RLO is cleared.
•• The condition codes CC 0 and CC 1 can be analy zed.
•• All other bit and word condition codes are cleared.
1) Possible values: 0 - 62, where the represented numb er is less than or equal to
the req uire d n umbe r
0 = "no B STA CK entry exists" or "err or"
(Multiply the contents of ACCU-1-L by four to obtain the
number of data words written to the DB).
RL O, CC 0 and CC 1
settings
R LO C C 1 C C 0 Scan with M eanin g
0
0
0
1
0
0
1
1
1
0
0
1
JM
JZ
JP
JC
Exi st ing num b er of
BS TACK ele ments
< required number
Exi st ing num b er of
BS TACK ele ments
= required number
Exi st ing num b er of
BS TACK ele ments
> required number
Error
Storing the BSTACK
elem ent s in open dat a bl ocks
The contents o f the BSTAC K are stored in the data block as fo llows
when OB 170 is ca lled (se e als o Fig . 6-3):
A = BST ACK elemen t number (62 to 1)
(As soon as t he las t BST AC K el ement is ou tp ut you can dete rmin e the
remai ni n g space: A = 17 reserve = A - 1 = 16)
B = Depth if t he BST ACK element (1 to 62)
O B 170: Read Block Stac k (BST A CK)
CPU 928B Programming Guide
6 - 54 C79000-B8576-C898-01
Block header
AB
SAC
DBA
Length
AB
SAC
DBA
Length
DW0
DWn
DWn+1
DWn+2
DWn+3
DWn+4
DWn+5
DWn+6
DWN+7
older BSTACK entries
second last entry
in the BSTACK (B = 2)
last entry in the
BSTACK (B = 1)
Offset
F ig. 6-3 Storin g BSTACK en tries in a da ta blo ck
6
OB 170: Read B lock S tack (B ST A C K )
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 55
Po ssib le errors
•• N o data block opened
•• Opened data block does not exist or is n ot long enoug h to take the
required number of BSTACK entries
•• Illegal parameters in ACCU 1 and ACCU 2
If an e rro r occ urs, the R LO a n d th e co ndi ti o n co d es CC 0 and CC 1
are set (RLO, CC 0 and CC 1 = 1). The remaining bit an d word
conditi on codes are cleared. The contents of ACCU-1-L are set to "0 ".
Example
You want to read the last three BSTACK entries into data block DX 10.
You want the entries to be stored in DX 10 from data word DW 16 onwards
(see Figs. 6.4 and 6.5).
:CX DX 10 ;open DX 10
:L KY 0,16 ;BSTACK entries to be stored from DW 16 onwards
:L KY 0,3 ;you require the last three BSTACK entries
:JU OB 170
Six bl ocks a re e nter ed in th e BS TACK a s fo llow s:
Continued on the next pag
e
Element 56
Element 57
Element 58
Element 59
Element 60
Element 61
Element 62
Element 1
BSTACK
Depth 1 (last BSTACK entry)
Depth 2
Depth 3
(first BSTACK entry)
Fig . 6-4 Cont ent s o f the BS TACK in thi s e x am ple
O B 170: Read Block Stac k (BST A CK)
CPU 928B Programming Guide
6 - 56 C79000-B8576-C898-01
Continuation of the example:
After the sp ecia l fu nc tion O B is cal le d, D X 10 c onta ins th e fo ll owin g:
Block header
DW 0
DW 16
DW 17
DW 19
DW 20
DW 21
DW 22
DW 23
Offset
58 2
SAC
DBA
Length
57 1
SAC
DBA
Length
59 3
SAC
DBA
Length
Depth 1
Depth 2
Depth 3
DW 24
DW 25
DW 26
DW 27
DX 10
ACCU-2-L
ACCU-1-L
CC 0
CC 1
16 (Offset)
3 (No. of elements in DX 10)
RLO 0 (No errors)
0
1
(No. of BSTACK elements
number of elements)
DW 18
=
=
=
=
=greater then requested
Fig. 6-5 Contents of DX 10 i n thi s example after OB 170 i s called
6
OB 170: Read B lock S tack (B ST A C K )
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 57
6.15 O B 180: Accessing Variable Data Blocks
DBA/DBL reg ister
When a d ata blo ck i s o pen ed w i th t h e operations C DB an d CX DX,
t he DBA register (dat a bloc k start ad dress) is loaded with the address
of data word DW 0, stored in DB 0.
Access to data blocks with operations such as L DR 60 or
DO DW 240 e tc. a re alwa ys rel at ive to t he d ata block st art address.
In addition to the DBA register, the DBL register (data block lengt h)
is alway s loaded when a data block is called. This register contains the
length (in words) of the opened DB or DX data block without the
block header.
Note
A maxim um of up to 4091 data words can be entered in the DBL
register.
STEP 5 access to data words is only possible up to a maxim um
data w ord number of 255.
Applications of OB 180
Spec ia l fu n ctio n OB 180 a llo ws you to a cc ess struc tu red data in a n
ope ned d at a blo ck. You c an do th i s by sh iftin g the starting ad d re ss of
the data block entered in the DBA register to the end of the data block
with the help of OB 180. Simultaneo usly t o shifting the starting
address, OB 180 decrements the block length entered in the DBL
register accordingly. It is im portant that this is done so that the CPU
ca n mon itor lo ad and transfer operatio ns in the case o f later a ccesses
to the data block.
Example
The DB A re gi ster the a ddre ss of the me mory wor d
in whi ch D W 0 to DB 17 is st ored : DB A = 151BH
The nu mber o f da ta w or ds i s stor ed i n the DBL
regist er: DB L = 8 (D W 0 to D W 7)
Since acce ss to the da ta w or ds b y me an s of the
STEP 5 operations L DW, U D, DO DW etc. is
always relative to DBA, 3 is added to 151BH in
order to access, e.g. DW 3.
Data word DW 3 is stored under the address
151EH.
The DB L re gi ster is us ed t o chec k wh et her a
transf er o r load ope ra tion i s pe ndin g. T D W 7
is permissible but T DW 8 or L DW 8 are not.
O B 180: Accessing Variable Data B locks
CPU 928B Programming Guide
6 - 58 C79000-B8576-C898-01
•• Access to DBs with a length greater than 261 words (five words
header) over the whole length of the DB. Using OB 180, you can
move an "access window" of 256 data words over the lengt h of the
data block.
•• Hand lin g data str ucture s
A data block can be divided into several data records of the sam e
len gth and with the data arranged in the same order. This is k nown
as stru ct u ri n g th e da ta bloc k. A d at a blo ck structured in th i s w a y
mi gh t, fo r ex ample, c ont ai n the da ta of seve ral su b pro ce sses, wit h
a te mperature va lue in the first data word, a pressure i n th e second
and other values for the subprocess in the remai ning data words.
Using OB 180, you can access the data o f each subprocess using
the same opera ti o ns (e.g. L DD, S D, T DR etc .), by l oa din g th e
DBA register with the start address f or the subprocess.
In c o ntrast to oth er su bstitut ion mec han isms, (s ubst it u ti on =
indexed parameter assign m ent) you o btain simpl er and fa ste r
sub rou tines.
Function
Wi th OB 180, th e starting add re ss of the c u rrent d at a blo ck i s sh i ft ed
by a specified value. In doing so, account is taken of the fact that the
rem aining available length of the DB has to be reduced (the DBA and
DBL registers are loaded in c orrespondence to the sh ift).
Note
Before yo u ca ll OB 180, a d a ta blo ck (DB o r DX) wit h an
adequate length must already be open.
Parameters ACCU-1-L
offset (number of data words, by which you want to shift the data
b lock st art address),
possible val ues: 0 < ACCU-1-L < D BL
6
O B 180: Acc essing Variable Data Blocks
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 59
Result
After OB 180 has been called successfully
•• the value of the DBA register (= address of DW 0) is raised by the
v al ue of AC CU-1- L
•• the valu e of the D BL register is reduc ed b y t he val ue of AC CU-1-L
•• the RLO is cleared (RLO = 0)
•• all other bit and word condition codes are cleared
Po ssib le errors
•• N e ga tiv e length
•• No data block opened
•• Co ntents of AC CU-1-L ≥ DBL
In th e ev ent of an e rro r (ACCU-1-L ≥ DBL) the D BA and D BL
regis ters rem ai n un c han ged. T he R LO is set (R LO = 1). T he
rem aining bit and word condition codes are cleared.
If the DBL regi ster co n ta in s th e valu e "0" , OB 180 reco g n iz es th at n o
data blo ck is open. The RLO is set (RLO = 1), signalli ng an error.
Resetting DBA and DBL to
the initial value
Opening the data block again using the operations C DB or CX DX,
re-establishes the initi al setting.
Example
You wa nt t o shif t th e data b lock sta rt add ress ( DBA = 15 1B ) in D B 17
(DBL = 8) by two data words.
:C DB 17 open DB 17
:L KB 2 shift / offset as constant
:JU OB 180 cal l OB 1 80: DB A an d DB L are adju st ed
When you call OB 180, the data word stored at e.g. address 1520 can no
longer be addressed as DW 5, but must be addressed as DW 3 etc. (see
Fig. 6 -6).
O B 180: Accessing Variable Data B locks
CPU 928B Programming Guide
6 - 60 C79000-B8576-C898-01
Continuation of the example:
Because the DBL register is adjusted at the same time, e rror mo nitori ng
is gu arante ed: the op erat ion T DW 5 i s pe rmit te d, w hile T DW 6/LW 6
would cause an error.
If yo u ca ll OB 180 ag ain, t he D BA c an be incr ea sed agai n (and t he D BL i s
further reduced). The operation C DB 17 re-establishes the initial state
(DB A = 15 1B, DB L = 8) .
If DB 17 ha s a leng th of, for exa mp le, 25 8 da ta wor ds, yo u ca nnot acces s
DW 256 and DW 257 using STEP 5 operations. If you shift the DBA register
by tw o, y ou can add re ss d at a wo rds 25 6 an d 25 7 usin g "D W 254" a nd
"DW 255".
For m ore in form atio n abou t the DBA/ DB L re gist er s, r efer t o Ch ap ter 9.
eeee
f f f f
gggg
cccc
dddd
hhhh
1516
1517
151B
151C
151D
151E
151F
1520
1521
1522
DW 0
DW 1
DW 2
DW 3
DW 4
DW 5
Addr. (hex.) D B 17
DBA new
.
.
.
.
5 words
block header
DBLold
DBLnew
DBA old
15 0
Fig. 6-6 Shifting the DB start address
6
O B 180: Acc essing Variable Data Blocks
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 61
6.16 O B 181: Testing Data Blocks (DB/DX)
With the special f unction organization block OB 181 you can check
t he fo ll ow in g:
•• whether a particular DB or DX data block exists,
•• th e add ress o f the fi rst da ta wo rd of t he data blo ck ,
•• how many data words the data block contains,
•• t he memory type and area (user memory: RAM or EPROM,
DB-RAM).
Application of OB 181
The "test DB/DX" function is useful before the operations
TNB/ TNW , G DB /G X DX an d befo re cal li n g th e spec ia l fun ct ion
organization blocks OB 182, OB 254 and OB 255.
You can, f or exam ple, call OB 181 before transferring a group of data
words, to m ake sure that the destination data block is both valid and
long enough to take all the data words you wish to transf er.
Function
OB 181 checks that a specified data block exists and returns the
cha ra ct eristic param et ers of t he data bl ock a s a resul t.
Parameters ACCU-1-L
a) ACCU-1-LL:
b l ock num b er
possible val ues: 1 to 255
b) ACCU-1-LH:
block identifier
possible val ues: 1 = DB
2 = DX
O B 181: Te sting Data Bl o cks (DB/DX)
CPU 928B Programming Guide
6 - 62 C79000-B8576-C898-01
Result
•• If th e block d oes exis t in the CPU:
- ACCU-1-L: c ontains the address of the first data
wor d (D W 0),
- ACCU-2-L: contains the length of the data block in words
(withou t block header),
E xample: ACCU-2-L co nta ins the va lu e "7":
the data block consists of DW 0 to DW 6.
- RLO: = 0
- CC 0/CC 1: are affec te d ac co rdi n g to t he l oc at ion of th e
block (see following list),
- the re maining
bit and w o r d
condition code s: are clea re d .
•• If the data block d oes not exist i n the me mory or t he pa rame te r
a ssignm e nt is incorrect:
- ACCU 1 and 2: a re not changed
- RLO: = 1
- CC 0/CC 1: = 1
- the re maining
bit and w o r d
condition code s: are clea re d
RL O, CC1, CC 0
The follow i ng condition code b its are set accor ding to th e check
resu l t. The con diti o n co de bits ca n be e valu a te d by the o pera ti ons
listed in the "Scan" column of the table:
R L O CC 1 CC 0 S can Meaning
001 JMDB/DX
in user
submodule
DB/DX in
EPROM
(read-only)
DB/DX
exists
0 0 0 JZ DB/DX in RAM
(read/write)
0 1 0 JP DB /DX in DB
RAM
1 1 1 JC D B/DX does not exist or there is an error
6
OB 181: Testing Data B locks (DB/DX)
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 63
Po ssib le errors •• Incorr ect b lock number ( i llegal: 0: DB 0/DX 0 )
•• Incorrect bloc k identifier (permitted: 1 = DB, 2 = DX; illegal: 0,
3 to 255 )
•• memor y error
Examples
Re fer to Section 8.3.2 / Section 9.2 / Section 9.3.
O B 181: Te sting Data Bl o cks (DB/DX)
CPU 928B Programming Guide
6 - 64 C79000-B8576-C898-01
6.17 O B 182: Copying a Data Area
Function
OB 182 copies a data field of variable length fro m one data block to
another. You can use DB and DX data blocks as the source and
destination blocks. You can select the start of the field in the source
an d des tina tion da ta blo c k as requi red . OB 182 can copy a maximum
of 4091 data w ords. I t co ntain s pseudo operati on bounda ries.
Note
The source and desti nation blo ck can be identical; the data areas
of the so urce an d destin at io n c an overlap. T he original d at a of
the source area are copied unc hanged to the destin ation area
even if there is an overlap. (The area overlapping in the sour ce
is overwritten f ollowing the copy ing.) You can use this feature in
certain situations, for exam ple to shift a data area within a block.
Parameters
1. Data F ield with Parameters for Copyin g Functions
Bef ore you call OB 182, supply a data f ield with all the data required
for the copying. This data f ield can be set up in a DB or DX data
block, or in the F or S flag area.
The data f ield defines the source and destination data block, the field
st art add re ss in both blo c ks an d t he n umber of d at a words to be
transferred. It consists of 5 words.
15 8 7 0
Source DB type Source DB no.
No. of 1st data word in source DB to be transferred
Dest. DB type Dest. DB no.
No. of 1st data word to be written in dest. DB
Number of data words
Bit no.
1st word
2nd word
3rd word
4th word
5th word
6
OB 182: Copying a Data Area
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 65
T he range of values and meaning of the parameters is as fo llows:
Parameters P er missible value ra n ge
Data block type (source and destination) 1 = DB
2 = DX
Data b lock nu mber (source and
destination) 3...255
No. of the 1st data word (sou rce and
destination) 0...4090
Number of da ta w o rds 1...4091
Da ta field in the flag area
If you set up the data f ield in the flag area, you must take into account
the f ollowing assignm ent of data f ield words to flag by tes. "x" is the
paramet er "n o . of t he 1st data fi el d word " , t h at you mu st sto re in
AC CU-1-L when OB 182 is called.
Bit no. 15 8 7 0
1st data field word Flag byte x Flag by te x+1
2nd data field word Flag by te x+2 Flag byte x+3
3rd data field word Flag by te x+4 Flag byte x+5
4th data f ield word Flag by te x+6 Flag by te x+7
5th data f ield word Flag by te x+8 Flag by te x+9
2. Accus
2a) ACCU-2-L
Der ACCU-2-L enghält Angaben z um v erwe ndeten Datenfeld. Er
muß fol gende n Aufb au hab en:
Parameters in ACCU-2-L
Address area type,
permitted values: 1 = DB data block
2 = DX d ata block
3 = F f l ag ar e a
4 = S flag area
Data block no.,
permi tted values : 3 to 25 5 (in the ca se of address area type "1"
or "2" o nly; irrelev ant i n th e case of a d dre ss
area type "3 " or "4")
15 8 7 0Bit no.
Ad dre ss area type Data bl ock n o .
O B 182: Copying a Data A r e a
CPU 928B Programming Guide
6 - 66 C79000-B8576-C898-01
2b) ACCU-1-L
Number of the 1st data fie ld word,
permitted values (depending on
t he address area type):
DB, DX: 0...2043
F flags: 0...246
(= no. of f lag byte " x")
S fl ags: 0 ...1014
(= no. of f lag byte " x")
Result
After OB 182 is correctly executed, the condition code bits OR,
ERAB and OS = 0. All other condition code bits and ACCUs 1 and 2
a r e unchanged.
Reactions to errors
I n the event of an err or , OB 19 or OB 31 (other runtime errors) is
called. If OB 19 or OB 31 is n ot loaded the CPU goes to the STOP
mode.
In both ca ses , e rro r ide nt ifiers are transf erred to ACCU 1 an d
ACCU 2 (see f ollowing table).
ACCU-1-L ACCU-2-L Cause of error OB called
1A06H - Data block not loaded OB 19
1A34H 0001H
0100H
0101H
0102H
0200H
0201H
0202H
0203H
0210H
0211H
0212H
0213H
0220H
0221H
0222H
0223H
D ata fi eld wr i tten to incorrectly
Add re ss area t ype n ot perm it te d
Data block number not permitted
Nu mber of th e first da ta fie ld wo rd no t permitted
Source data block type not permitted
So urc e data bloc k nu m be r not permit te d
Number of 1st data word in the source DB to be
transferred not permitted
Length o f the source data block in the block header < 5
words
Destination data block t ype n ot permitted
Destinati on data block nu mber not permi tted
Number of the 1st data word to be written to in the
desti na ti o n DB no t permitt ed
Length of the des tination da ta b lock in the bloc k
heade r < 5 wo rds
Number of data w ord s to be tran sf e rred no t permi tt ed
(= 0 or > 4091)
S ource d ata bl ock too short
Destinati on data blo ck t oo s hort
Destination data block is in an EP ROM
O B 31
Table 6-9 OB 182 error IDs
6
OB 182: Copying a Data Area
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 67
6.18 O B 190/OB 192: Transferring Flags to a Data Block
Application
Wi th orga n iz at io n block s OB 19 0 and OB 192, yo u ca n tran sfe r a
selected number of flag b ytes to a data block.
T his can, for example, be an adv antage before block calls, i n error
organization blocks or when cyclic program execution is interrupted
by a time or process interrupt.
Usin g OB 191 and OB 193, you can then write these flag bytes back
from t he da ta blo ck.
Note
Use OB 190 a nd OB 191 to save and rea d back fl ag byte s, s in ce
the ti me requ ired is e x tremely short.
Be f ore you c al l OB 190/192, a d at a bl oc k (DB/DX) mu st a lrea d y
be open.
OBs 190/19 2 only transfer flag bytes from the F flag area to a
data block, they cannot transfer fl ag bytes from the S fla g area.
Function
After you cal l OB 190/192, th e flag bytes are writt en t o the open dat a
block f rom the specified data word address. OBs 190/192 take the f lag
area to be saved from ACCU 2.
OBs 190 and 192 are identical except for the way in which they
transfer the flag bytes:
OB 190 transfers the flags in byte s
OB 192 transfers the flags in words.
Thi s d ifference is sign ifi ca nt, w he n th e da ta tran sferred t o the data
block are intended for processing an d you are no t simply using the
da ta blo ck as a b uffe r.
O B 190/OB 192: T ransferring Flags to a Data Blo ck
CPU 928B Programming Guide
6 - 68 C79000-B8576-C898-01
The f ollowing diagram illustrates the difference.
Note
If you transfer an odd n umber of f la g b yt es , o nly half the last
data wo r d in the data b l ock is used. With OB 190, th e left date in
the des tination D B is unchanged, with OB 192 the right date is
unchanged.
Parameters
1. Specifyin g th e sou rce:
1a) ACCU-2-LH
First fla g by t e to be tran sf e rre d,
possible val ues: 0 to 255
1b) ACCU-2-LL
Last flag byte to be trans ferred,
possible val ues: 0 to 255
(The last fla g b yte must be ≥ the first flag byte)
Copy flags with OB 190:
0
2
4
DL DR
1
3
15 8 7 0
FY 0
FY 1
FY 2
FY 3
Data blockFlags
OB 192:
DL DR
0
2
4
1
3
15 8 7 0
Data block
DW 0
DW 1
DW 2
DW3
7
0
1
2
3
4
0
Fi g. 6- 7 Tra nsf e rring in byte s (OB 190) and wo rds (OB 192)
6
O B 190/OB 192: T ransferring Flags to a Data Blo ck
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 69
2. Specifyin g the destination
ACCU-1-L
Number of th e first data word to be written to in the open data blo ck:
The permitted values depend on the length of the data block in the
memory. Numbers greater than 255 may occur
Result
If the specia l fu n ct io n OBs 190/ 1 92 are pro ce ssed correctly, th e RLO
is cleared (RLO = 0). The ACCUs remain uncha nged.
If an error occurs, the RLO is set (RLO = 1), th e ACCUs remain
unchanged.
Po ssib le errors
•• N o DB or DX da ta block open ed
•• Incorrect flag area (last flag byte < first flag byte)
•• Data word number does not exist
•• DB or D X da ta block not long enoug h
O B 190/OB 192: T ransferring Flags to a Data Blo ck
CPU 928B Programming Guide
6 - 70 C79000-B8576-C898-01
6.19 O B 191/OB 193: Transferring Data Fields to a Flag Area
Application
Wi th the orga n iz atio n block s OB 19 1 and OB 193 you c an t ransfer
data f rom a data block to the flag area. With this function, you can, for
exa mple, w rite fla g byt es you have save d in a d at a blo ck bac k to t he
fla g area .
The only di fference bet ween OBs 191/193 an d OBs 190/1 92, is that
t he source and destinatio n are rev ersed:
Note
Bef o re yo u call OB 191/ 193, a d ata block o f s uffi cient lengt h
(DB/DX) must be opened.
OBs 19 1/1 93 tr ansfe r fr om the data bloc k only to the F flag area
and no t to the S flag area.
Function
Afte r OB 191/193 is call ed, da ta wo rds st artin g fro m th e da ta wo rd
a ddress speci fied are read out of the opened data block and transferred
to the flag ar ea.
OBs 191 and 193 are identical, except for the way in which they
t ransfer data.
OB 191 transfers data words in bytes
OB 193 transfers data words in words.
T he figure on the ne xt page illustrates this difference.
OB 190/192: Flag area Data block
OB 191/193: Flag area Data block
6
OB 191/O B 193: Transferring Data Field s to a Flag Area
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 71
15 8 7 0
Data block
DW 0
DW 1
DW 2
DW 3
Data block
DW 0
DW 1
DW 2
DW 3
DL DR
15 8 7 0
DL DR
01
23
45
6
10
23
45
6
Flags
OB 191
OB 193
(DR 0)
FY 0(DL 0)
FY 1
(DR 1)
FY 2(DL 1)
FY 3
70
0
1
2
3
Flags
(DR 0) FY 0
(DL 0) FY 1
(DR 1) FY 2
(DL 1) FY 3
70
0
1
2
3
Fi g. 6- 8 Transf e rring in b y te s (OB 191) and wo rds (OB 193)
O B 191/OB 193: T ransferring Data Fields to a Flag Area
CPU 928B Programming Guide
6 - 72 C79000-B8576-C898-01
Parameters
1. Specifyin g th e sou rce:
1a) ACCU-2-L
Number of t he first dat a word i n th e ope n data bloc k to be tran sferred
2. Specifying th e d estination :
2a) ACCU-1-LH
First flag by t e to be wri tten t o,
possible val ues: 0 to 255
2b) ACCU-1-LL
Last flag byte to be written to,
possible val ues: 0 to 255
(The last fla g b yte must be ≥ the first flag byte)
Result
If special fu n ct io n OBs 191/ 1 93 are pro ce ssed correctly, the RLO is
cleared (RLO = 0). The ACCUs remain uncha nge d.
I n the event of an error, the RLO is set (RLO = 1), the ACCUs
rem ain unchanged.
Po ssib le errors
•• N o DB or DX da ta block open
•• Incorrect flag area (last flag byte < first flag byte)
•• Data word number does not exist
•• DB or D X da ta block not long enoug h
6
OB 191/O B 193: Transferring Data Field s to a Flag Area
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 73
Ex ample 1
Before pro gr am b lock P B 12 i s ca lled , all the fl ags (FY 0 to F Y 255) mus t
be sav ed i n data blo ck DX 37 fro m ad dr ess 100 on ward s an d then w ritt en b ac k
to the flag area.
Saving : :CX D X 37 Call the d ata bloc k
:L KY 0,255 Flag area FY0 to FY255
:L KB 100 Number of the 1st data word in the
: destination DB
:JU OB 190 Save fla gs
Bloc k ch ange : : JU P B 12
Writ in g back : : (Dat a bl ock al read y ca lled )
:L KB 100 Number of the 1st data word in
: the so urce DB
:L KY 0,255 Flag area FY0 to FY255
:JU O B 191 Wr it e ba ck fla gs
Ex ample 2
Flags used b y th e cy cl ic u se r pr ogra m must not b e us ed b y a ti me or
proces s-dr iv en u ser pr ogra m. Eac h pr og ram proc es sing lev el mus t have a
partic ular s ecti on o f the fl ag a rea as sign ed t o it.
e.g.: Cyclic user program: FY0 ... . ... FY99
Time-driven user program: FY100 ... . ... FY199
Process interrupt-driven user program: FY200 ... . ... FY255
If, ho weve r, the cyc li c us er pro gram i s al read y usin g al l 256 fl ag b ytes
and th e ti me -dri ven us er p ro gram als o requ ires a ll 2 56 f la g by te s, t he
flags must b e sw appe d over w hen the pr oces sing l evel is ch ange d and the ol d
flags stored until the program returns to the original processing level.
The qu icke st way to sa ve a nd loa d th es e fl ags is wit h th e spec ia l fu ncti on
blocks OB 190 and OB 191. Fig. 6-9 illustrates how a flag area FYx to FYy
used b y bo th OB 1 an d OB 1 3 (100 ms ti me i nter ru pt) can be buf fe red in a
data block DBx.
Continued on the next page
O B 191/OB 193: T ransferring Data Fields to a Flag Area
CPU 928B Programming Guide
6 - 74 C79000-B8576-C898-01
Continuation of example 2:
STEP 5 program in OB 13:
:C DB 100
:L KY 0,255
:L KB 128
:JU OB 190
:L KB 128
:L KY 0,255
:JU OB 191
:
:
:C DB 100
:L KY 0,255
:L KB 128
:JU OB 190
:L KB 0
:L KY 0,255
:JU OB 191
:BE
OB 1
OB 13 OB 190
OB191
FY x -
FY x -
Save
the FYs
Write the
FYs back
DB z
DW a-b
DB z
DW a-b
FY y
FY y
Fig. 6-9 Saving the areas when the program proces sing level changes
6
OB 191/O B 193: Transferring Data Field s to a Flag Area
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 75
Fu rthe r appl icat io ns f or o rg aniz atio n bloc ks O B 19 0 to 1 93
- In the CPU 928B, operations involving the processing of single bits
(A, O, ON, A N, S , R, = ) th at acc ess th e fl ag a re a ar e fa r fast er tha n
compar able o pera tion s that a cces s da ta blo cks (c ompa re, fo r ex am ple the
operat ions " A F" "A D" or "S F" "S D").
You ca n sp ee d up you r prog ra m if you c opy data t o th e fl ag are a,
process them there and then return them to the data block.
- A high byt e and low by te i n a da ta b lo ck c an b e swap ped ov er w it hout
compli cate d prog ramm in g by c opyi ng t he dat a wo rd s to the f lag ar ea
using the ap prop riat e OBs an d th en t ra nsfe rrin g them bac k as
illust rate d by F ig. 6- 10.
- You ca n sh if t da ta f ie lds wi thin a d at a bl ock by spe cify in g a di ffer ent
data w ord bu t th e sa me DB nu mber for t rans ferr in g th e da ta bac k to
the DB .
OB 190 OB 193
DW x DW x
A B
C D
B A
D C
Flags
15 8 7 0
Data block
15 8 7 0
Data block
FY y
FY y+1
FY y+2
.
.
.
.
DW x+1
DW x+1
C
D
B
A
70
Fig. 6-10 Swapp ing the hi gh b yte and low b yte i n a DB usi ng OB 193/OB 190
O B 191/OB 193: T ransferring Data Fields to a Flag Area
CPU 928B Programming Guide
6 - 76 C79000-B8576-C898-01
6.20 O B 200 to OB 205: Multiprocessor Comm unication
The se special fun ct io n o rga ni za ti on blo cks a re de scribed in d e ta il in
Cha pter 10.
You can use the special function organization blocks OB 200 and
OB 202 to OB 205 to transfer data between CPUs in multiprocessor
oper a tion us ing the coor dina to r 9 2 3 C.
•• OB 200: initialize
T his special functi on organizati on block sets up a memory area in
the 923C co o rdi n at or. Th is me mory is a buffer for the data fields
t hat are transferred.
•• OB 202: send
Th is fun c ti on t ran sfers a d a ta field t o th e buffe r of the 923 C
coordinator and indic ates ho w many data field s can sti ll b e sen t.
•• OB 203: send test
T he special function OB 203 determines the number of free
memory fields in the buffer of the 923C coordinator.
•• OB 204: receive
This function trans fers a data field from the buffer o f the
923C coordinator and indicates how m any data fields can still be
received.
•• OB 205: receive te s t
T he special function OB 205 determines the number of occupied
memory fields in the buffer of the 923C coordinator.
6
OB 200 to O B 205: M ultip rocessor Com munication
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 77
6.21 O B 216 to OB 218: Pag e Access
What are pages?
To implem ent a large number of communications registers, within the
a ddress range of the S5 bus, an a ddress area with a le ngth of 1024
bytes (2048 bytes are reserved) is imaged 256 times on the memor y.
Because these 256 images are stored beside or behind each other like
individual " pages" , these mem ory areas are also referred to as a "page
memory".
In mult ipro ce ssor ope rat io n , a ll m odules i nvolve d can only access one
page o f this memory area at any o ne time, all th e remaining pages
must be disabled for both reading and writing.
A page is ad dressed via a pag e add ress reg ist er t h at ex i sts on all
modules operating wi th pag e s a nd t hat has a fixe d add ress o n th e S5
bus. You set the numbers (addresses) of the pages on each of these
modules u sing a DIL sw itch , so that e ach pag e ca n on ly ex ists on ce in
the PLC.
Befo re read in g or writi ng to a pag e, th e C PU specifies th e page
nu mber by writing to the page address register. All the mod ules that
operate accordin g to this procedure of the S5 bus receive this n umber
simultaneously ("broa d cast" ) an d sto re it in t h ei r memory. On ly the
page addressed in this way can be written to or read f rom in the page
memory of the S 5 bus, al l other page s a re disabled.
O B 216 to OB 218: Page Access
CPU 928B Programming Guide
6 - 78 C79000-B8576-C898-01
How to access pages
You can use organization blocks OB 216 to OB 218 and several
STEP 5 operati ons (see Chapter 9) to access the pages.
The organization blocks contain the f ollowing f unctions:
•• OB 216:
write a byte/word/double word to a page
•• OB 217:
reads a b yte/word/double word from a page
•• OB 218:
the CPU occu pies a page (used fo r co o rdi na ti on in mul ti p roc essor
operation)
You can us e these fu ncti o ns for t es t pur pose s an d for prog rammi n g
handling b locks or similar f un ctions.
Note
When ever pos sible, onl y pro g ra m acce ss t o pag es by ca ll in g
OB 216 to OB 218. You should only use the available STEP 5
operati ons if you have considerable experience of the s ystem.
Normally , you can execute all f unctions using the standard
function blocks "handling blocks" and the integrated f unction
orga niza ti o n blocks "mult iprocessor commu ni ca ti on" (OB 200,
OB 202 to OB 205), with which all page access is han dled
"automatically".
6
O B 216 t o OB 218: Pa ge Access
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 79
Address areas for
p eri ph erals on the S5 bus
Page length Address area occupied
102 4 addresses (byte or wo rd
addresses)
204 8 addresses (byte or wo rd
addresses)
F400H - F7FFH
F400 H - FBFFH
Bit
F000 0
F100
F200
F300
F400
FC00
FEFF
FF00
FFFF
.
Page no. 0
12
7
P area
O area
IPC flags on
Distributed peripherals
Address space of a page
coordinator
System area
(semaphores)
(or free)
3
Multiple memory area
Length: 1024 or 2048 bytes
Page address register
Page no. 255
on the coordinator
not occupied
Fig. 6-11 Location of the page address area on the S5 bus
O B 216 to OB 218: Page Access
CPU 928B Programming Guide
6 - 80 C79000-B8576-C898-01
You spec ify th e pag e to be us ed wh en yo u assig n para mete rs to t he
spec ia l funct ion organ iz atio n block s OB 216, OB 217 an d OB 218.
T he nu mber of the "currently active" page is then auto matically
en t ered in a memo ry loca ti on with th e ad d ress 0FE FFH (see Fi g .
6-11). All addresses then r e fer to t he page whose number is entered.
Note
You canno t read t h e pa ge a dd ress regi ste r w it h th e add ress
0FE FF H. At t his address, you can, ho wever, rea d out the bus
error register o n the coordin at or mod ul e 923C (see
S5-135U/155U Sys tem M anual).
Notes on assigning
parameters
When a by te/word/double word is written (OB 216) and read
(OB 217) to /fro m a pa ge, t h e bytes a re refe ren ced in t h e fo llo wing
order:
Byte
High byte
Low byte
7
Byte format
Word format
Double word format
Address n
Address n
Address n+1
Address n
Address n+1
Address n+2
Address n+3
0
H byte in H word
L byte in H word
H byte in L word
L byte in L word
Fi g. 6-1 2 Lo cat io n o f t he byt es whe n writing ( OB 216) / re a ding (OB 217) to/f ro m a page i n wor ds o r do ub le
words
6
O B 216 t o OB 218: Pa ge Access
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 81
6.21.1
O B 216: Writing to a Pag e
Function
The specia l funct io n o rga niz at io n block t ran sfers a byte , wo rd o r
do uble word from ACCU 1 (right-justifie d) to a particular page.
The addressin g of the page in single or multipr ocessor operation and
the transfer of the c omp lete data unit (1, 2 or 4 bytes) is one
program function and cannot be interr upt ed .
Parameters
Accus
a) ACCU-3-LH
Ide n ti fi er o f t he d at a to be tran sfe rre d,
possible val ues: 0 = byte
1 = word
2 = d ouble word
b) ACCU-3-LL
Current page number,
possible values: 0 to 255
c) ACCU-2-L
Destin ation address o n the page,
possible values: 0 to 2047
d) AC CU 1
Data to be written
(byte , wor d, double wo r d: right-j usti fi ed)
O B 216 to OB 218: Page Access
CPU 928B Programming Guide
6 - 82 C79000-B8576-C898-01
A CCU contents before writin g:
Result
•• If the data is written to the page correctly:
- ACCU 1 and ACCU 3: remain unchanged.
- ACCU-2-L: contains a value incremented b y 1,
2 or 4 (depending on the length of
the data t ra nsferred)
- RLO: = 1
- the re maining bit and
w ord condition codes: are clea re d
•• If th e data cannot be written to the page
- all ACCUs: r em a i n un changed
- RLO: = 0
- all rem aining bit and
word cond ition cod es: are cl ea red .
ACCU 4
ACCU 3
ACCU 2
ACCU 1
High byte Low byte Low byteHigh byte
High word Low word
xxxx
Length ID Page number
0 to 255
xx
Address (relative to start of page)
xx
31 2324 16
data (8 bits)
data (16 bits)
data (32 bits)
x
x
0 ... 2046 if length ID 1 (word)
0 ... 2047 if length ID 0 (byte)
0 ... 2044 if length ID 2 (double word)
0: byte (8 bits)
1: word (16 bits)
2: double word (32 bits)
87 015
Fi g. 6- 13 ACCU c ont e nt s be f or e c al li ng O B 216
6
O B 216 t o OB 218: Pa ge Access
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 83
Po ssib le errors
•• wro ng lengt h ID in AC CU-3-LH
•• destination address on the page is wrong or does not exist
•• specified page nu mber does not exist
6.21.2
O B 217: Reading from
a Page
Function
The specia l funct io n o rga niz at io n block t ran sfers a byte , wo rd o r
double word from a specific page to ACCU 1 (right-justif ied).
Addressing the page in the single and multiprocessor modes and
transferring the com plete da ta (1, 2 or 4 b ytes) form a single
program unit that mus t no t be int errupt ed .
Parameters
Accus
a) ACCU-3-LH
Ide n ti fi er o f t he d at a to be tran sfe rre d,
permitted values: 0 = byte
1 = word
2 = double word
b) ACCU-3-LL
Current page no.,
permitted val ues: 0 to 255
c) ACCU-2-L
Source address of the p age ,
permitted val ues: 0 to 2047
O B 216 to OB 218: Page Access
CPU 928B Programming Guide
6 - 84 C79000-B8576-C898-01
ACCU contents before reading:
Result
•• I f the OB re ad s from th e pa g e successfully,
- ACCU 1: (right-just if ied) contains the value
read (the remaining bits up to
maximum 32 are cleared),
- ACCU 3: rem a in s un c ha n ge d ,
- ACCU-2-L: contains a value incremented b y 1,
2 or 4 (depending on the length
of the data t ransferred),
- RLO: = 1,
- the re maining bit and
word cond ition cod es: are cleared.
High byte Low byte Low byteHigh byte
High word Low word
xxxx
Length ID Page number
0 to 255
xx
Address (relative to start of page)
xx
31 2324 16
data (8 bits)
data (16 bits)
data (32 bit)
x
x
0 + 1... 2047 + 1 for length ID 0 (byte)
0 + 2 ... 2046 + 2 for length ID 1 (word)
0 + 4 ... 2044 + 4 for length ID 2 (double word)
0: byte (8 bits)
1: word (16 bits)
2: double word (32 bits)
87 0
15
ACCU 4
ACCU 3
ACCU 2
ACCU 1
Fi g. 6- 14 ACCU c ont e nt s be f or e c al li ng O B 217
6
O B 216 t o OB 218: Pa ge Access
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 85
•• If the OB cannot r e ad fr om the p age,
- all ACCUs: r e m ain unchanged ,
- RLO: = 0,
- all oth er bit and wor d
condition co des: are cl eare d .
Po ssib le errors
•• wro ng lengt h ID in AC CU-3-LH
•• source address on the page is wrong or does not exist
•• specified page nu mber does not exist
6.21.3
OB 218: Reserving
a Page Th e spec ia l funct io n o rga n iz atio n block t ran sfers the num ber of th e
CPU to a particu lar page, prov iding the c ont ents of the memory
l oca tion addressed on this page are zero. As long as the CPU number
is entered in this location, the page is reserved for this CPU and
cannot be used b y other CPUs.
Organization block OB 218 is used to synchronize data trans fer and is
particularly important when large blocks of d ata must be transmitte d
as one unit. In the multiprocessor m ode, no more than 4 bytes are
transferred per bus allocati on. Reserving a page is t herefore
advantageous.
Addressing the page, reading and, if applicable, writin g the slot
identifier is one program unit that must not be interrupted.
Parameters
Accus
a) ACCU-2-LL
Number of the page to be reserved,
permitte d values: 0 to 255
b) ACCU-1-L
Destin ation address o n the page,
permitte d values: 0 to 2047
(The contents of ACCU 3 and 4 are irrelevant.)
O B 216 to OB 218: Page Access
CPU 928B Programming Guide
6 - 86 C79000-B8576-C898-01
Accu assignments before cal ling OB 218 :
Result
•• If the pa g e is re served successfully:
- all ACCUs: r e m ain unchanged
- RLO : = 1
- the re maining bit and
condition co des: are cl eare d .
•• If th e page cannot be reserved:
- all ACCUs: r em a i n un changed,
- RLO: = 0,
- all oth er bit and wor d
condition co des: are cl eare d .
Po ssib le errors
•• inc o r r ect leng th ID in A CCU - 3-LH
•• source address on the page is incorrect or does not exist
•• specified page nu mber does not exist.
High byte Low byte Low byteHigh byte
High word Low word
Page number
0 to 255
xx
ACCU 1
x
31 16 0
Address (relative to start of page)
0...2047
xx
ACCU 2
824 23 15 7
Fi g. 6- 15 ACCU c ont e nt s be f or e c al li ng O B 218
6
O B 216 t o OB 218: Pa ge Access
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 87
6.21.4
Pr og ram Ex a mple
Task
You wa nt t o writ e da ta wor ds 4 t o 11 v ia t he 9 23 C co ordi na tor fr om t he
DB 45 of a CPU 928B to the DX 45 (data words 0 to 7) of a second
CPU 92 8B. Yo u wa nt t o sync hr oniz e th e send er a nd rec eive r (in th e
multip roce ss or m ode) u sing O B 21 8.
Curren t pa ge on the co ordi na tor: no. 25 5
Coordi nati on loc atio n on t he pag e (r es erve d): addr. 53
Data t rans fe r ar ea o f the pa ge ( read in g an d wr it ing) : addr . 54 -6 9
STEP 5 operations in the SENDER:
:L KB 255 Page number
:L KB 53 Address of the coordination cell
:JU OB218 Transf er t he slo t ID t o th e cell on th e pa ge
:JC =M001 If RLO = 1 (transfer successful),
jump t o la be l
:BEU Else block end
M001 :C DB 45 Open the source data block
:L KY 2,255 2=length ID double word, page number
:L KB 54 St ar t ad dres s on p age
:EN T Writ e to ACC U 3
:L DD 4 Data words 4 and 5 (= 4 bytes)
:JU OB 216 Transfer the 1st double word
: Increment address by 4 (ACCU-2-L = 58)
:TAK Save the destination address
:
:L DD 6
:JU OB 216 Transfer the 2nd double word
:TAK
:
:L DD 8
:JU OB 216 Transfer the 3rd double word
:TAK
:
:L DD 10
:JU OB 216 Transfer the 4th double word
:
:L KY 0,255
:L KB 53 Addr ess with s lot ID
:ENT
:L KB 0 ACCU 1 = 0
:JU OB 216 Clear slot ID, release data transfer area
:BE
Continued on the next page
O B 216 to OB 218: Page Access
CPU 928B Programming Guide
6 - 88 C79000-B8576-C898-01
Continuation of the example:
STEP 5 operations in the RECEIVER:
:L KB 255 Page number
:L KB 53 Coordi na tion c ell
:JU OB 218 Page reserved by 2nd CPU
:JC =M002 If RLO = 1, jump to label
:BEU
:
M002 :CX DX 45 Destin atio n data b lock
:L KY 2,255
:L KB 54
:EN T Writ e to ACC U 3
:L KB0 Write to ACCU 2
:
:JU OB 217 Read 1st double word
: Increment the address by 4 (ACCU 2-L = 58)
:T DD 0 Transfer ACCU 1 to data word 0 and 1
:JU OB 217 Read 2nd double word
:T DD 2
:
:JU OB 217 Read 3rd double word
:T DD 4
:
:JU OB 217 Read 4th double word
:T DD 6
:
:L KY 0,255
:L KB 53 Addres s with s lot ID
:ENT
:L KB 0 ACCU 1 = 0
:JU OB 216 Clear slot ID, release data
: transfer area
:BE
6
O B 216 t o OB 218: Pa ge Access
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 89
6.2 2 OB 2 2 0: S ig n Ex tens ion
Application
A sign exten sion is nece ssary to ex ten d a ne gativ e 16-bit fixed poin t
num ber to a 32-bit fixed po in t num ber before performing a fixed
point-floating point c onversion (32 bits, operation FDG).
Function
Th i s spe ci al fun cti on e xte nd s th e sig n of a 16-bit fix ed po int number
i n ACCU-1- L to the more significant word (ACCU-1-H):
•• If bit 215 = 0 (positive number), the more signif icant word is
lo aded wit h KH = 0000.
•• If bit 215 = 1 (negative number), the more signif icant word is
lo ade d with KH = FFFF.
Parameters
ACCU-1-L
16-bit fixed point number
Result
ACCU-1-H is loaded into ACCU-1-L accord in g to th e sign o f the
fixe d-point number (see above).
Po ssib le errors
none
O B 220: Sign Ext e n sion
CPU 928B Programming Guide
6 - 90 C79000-B8576-C898-01
6.23 O B 221: Setting the Cycle M onitoring Time
Function
By calling this special f unction, you can m odify the cycle m onitoring
time and change the m aximum permitted cycle tim e. As standard, the
cycle monitoring time is set to 150 m s. Along with this call, the tim er
for the cycle time monitorin g is restarted. The maxi mu m permitted
cycle time for the cy cle in which OB 221 is called, is extended by the
newly selected valu e, calc ulated from the ti me when the special
fun c ti on c all to ok plac e. Th e cyc le mo n it o rin g time o f al l s ubsequent
cycles corresponds t o th e ne wly sel ecte d va lu e (= t he tim e valu e that
you transfer in ACCU 1).
Parameters
ACCU 1
a) ACCU-1-L
new cycle tim e (in milliseconds),
permitted values 1 ms - 13000 ms,
positive fix ed po int numb er (KF)
b) AC CU 1-H
ACCU-1-H must have the value " 0"
Result
T he ne w cycle mon itoring ti me is set a fter correct processing of
O B 221.
Po ssib le errors
The cycle monitoring time you have specified is not within the range
1 ms - 13000 ms.
The f unction is not executed. The system program recognizes a
runtime er ror and call s OB 31. T he o t he r react ion s t o th e error d e pen d
on ho w you h ave pro grammed OB 31 (see Se ction 5.6.2). If OB 31 is
not loaded, the CP U goes t o th e STOP mode.
In both cases, the error identif ier 1A3AH is enter ed in AC C U - 1 -L.
6
O B 221: Setting the Cycle Monitoring Tim e
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 91
6.2 4 OB 2 2 2: R e sta rting th e Cy c le Monit or ing Time
Function
The specia l fun ct ion OB 222 re tri gg e rs the cyc le m o n ito ri ng time , i .e.
the timer f or the monitoring is restarted. After you call this special
func ti on , the ma ximu m permi tt ed c y cl e t ime for t he c urrent cyc le is
extended by the selected value f rom the tim e of the call.
Parameters
none
Po ssib le errors
none
O B 222: Restarting the Cycle Monitoring Time
CPU 928B Programming Guide
6 - 92 C79000-B8576-C898-01
6.25 O B 223: Com paring Restart Types
Function
If you call OB 223 in multiprocessor operation , the system c hecks
whether the restart types of all CPUs inv olv ed are the s ame.
Note
O B 223 m ust only be called when all the CPUs have com pleted
their start up.
If sta rt-up synchronizat ion is active (DX 0) this is guaranteed by
cal ling OB 223 i n the RUN mode.
If sta rt-up synchronizat ion is inactive this must be achieved by
othe r me an s, e.g. delay ed OB 223 call .
Parameters
none
Result
Error messag es in the event of deviating restart types
Po ssib le erro rs
If th e rest art types of all t he C PUs partic ipa ti ng i n m ul ti pro cesso r
mode are no t the sa me , t he CPU in whi ch OB 223 is processed det ec ts
a run time error. OB 31 is th en ca lled.
If OB 31 i s n o t load e d, th e C PU g oe s t o the STOP mode with t h e LZF
error message. It s ST OP LED flashes slowly . The oth er CPUs also go
to the S TOP mode, thei r LE Ds show a steady light .
Er r or ID s
When OB 31 is called and the CPU is in the STOP m ode, the error ID
1A3BH is entered in ACCU-1-L.
6
O B 223: Comp aring Restart Type s
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 93
6.2 6 OB 2 2 4: T ra ns fer ring B lo ck s of Int e rp ro ce s s or
Co m mun icat ion Fla gs
Function
T he interprocessor commu nication (IPC) flags are transfe rre d at th e
end of the program c ycle. In the single processor mode, the IPC flags
are transferred completely as a block of data to the memory on the
coordinator or the CP and/or f rom this memory to the f lags of the
CPU. The S5 bus is al ways a vailable.
In multiprocessor operation, on the other han d, each CPU can onl y
use the bus when it is allocated by the coordinator. Each tim e the CPU
has access to the bus, only one byte is transferred. Foll owin g this, it is
onc e ag ai n the tu rn of th e ot h er C PUs. Set s o f data t h at belon g
tog et her but t h at are d ist ribu te d ov e r sev e ra l flag byte s are th erefore
separated.
I f you call organ izatio n bloc k OB 224, yo u can transfe r al l the IPC
fla gs specifi ed i n DB 1 of t h e CPU a s a bloc k of d a ta . A s lon g as a
CPU is transferring IPC flags, it cann ot be interrupted by another
CPU. Sinc e th e nex t CPU h a s t o wai t befo re it ca n trans fer its d a ta , t he
cyclic program execution is delay ed (cycle tim e!).
OB 224 ensur es the co nsistency of the IPC fl ag info rmation. It mu st
be called in the start-up program as follows:
•• i n all the CPUs inv olved in IPC flag transfer
and
•• in each restart type being used.
Parameters
none
Po ssib le errors
none
O B 224: T ransferring Blocks of Interprocessor
Com munication Flags
CPU 928B Programming Guide
6 - 94 C79000-B8576-C898-01
6.27 O B 226: Reading a Word from the System Program
Function
The syst em program of the CPU is 128 x 210 word s l o ng and is
located in a m em ory area that you cannot access with STEP 5
stat ements . Usin g OB 226, howeve r, you c an read individual da ta
words from this memory area.
Note
For using OB 226, please see the description of OB 227 and t he
releva nt programming example.
Parameters
ACCU 1
Address of the s yste m program me mor y location to be read
permi tt ed va lu es 0 to 0001 F FFF H
Result
- ACCU-1- L: contains the word read from the sy stem program
- ACCU-1- H: = 0
- ACCU 2 c ontai ns the previo us conten ts of ACCU 1
(i.e. th e ad dress); the previous contents of
A CCU 2 are lo st .
Po ssib le erro rs
none
6
O B 226: Reading a Word from the System Program
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 95
6.28 O B 227: Reading the Checksum of the System Program
Application
Duri n g cycl ic program execu t io n, yo u ca n chec k th e con te n ts of t h e
system progra m as follows:
•• read the individual m em ory cells of the system program f rom
ad dress 0H to a dd ress 1DF FFH usi ng OB 226,
•• add all t he me mory l ocati on s us ing fixed poin t addit io n
(operation +F), ig noring over flows,
•• read the checksum using OB 227 and
•• compare the total obtained by the f ixed point addition with the
checksum read out by OB 227.
Function
T he special functi on organizati on block OB 227 loads the checksum
of th e system prog ra m from th e memo ry area of the system int o
ACCU 1. The word it rea ds o ut corresponds to the total of all memor y
cells of the syste m progra m from address 0H to address 1D FFFH.
Parameters
none
Result
- ACCU 1: contains the read ou t ch ecksum righ t-just ified
(1 word); the remaining contents of ACCU 1
are clea re d
- ACCU 2: contains the previo us contents of ACCU 1;
the previous contents of ACCU 2 are lost.
Po ssib le erro rs
none
O B 227: Reading the Checksum of the System Program
CPU 928B Programming Guide
6 - 96 C79000-B8576-C898-01
Example
Che ckin g th e chec ksum o f th e sy st em p rogr am
Funct ion bl ock FB 1 11 is pr ogra mmed f or c heck in g th e ch ec ksum o f th e
sys te m prog ra m.
FB 11 1 ge ne rate s th e chec ks um o f th e cont ents o f al l sy st em p ro gram
memor y wo rd s an d co mp ares t his chec ks um v ia O B 227 with t he s ys tem
progr am c he cksu m st or ed i n the syst em mem ory. I f th e ch ec ksum s are not
identical, the FB terminates in a STOP operation.
FW 25 0 = ch ecks um
FD 25 2 = ad dres s co unte r
FB111
NAME: CHECKSUM
:
:
:L KH 0000
:T FW 250 clea r ch ec ksum f lags
:T FD 25 2 cl ear ad dr ess co unte r
:
M001 :J U OB 22 2 restar t th e cycl e mo ni tori ng tim e
:L FD 252 load the address of the memory cell to be read
:JU OB 226 read wor d
:L FW 250 load the checksum flags
:+F add
:T FW 250 stor e th e chec ks um f lags
:
:L FD 25 2 in crem en t the ad dres s co unte r
:L KF+1
:+D add doub le wor d
:T F D 252
:
:L DH 0001E000 if address counter is not equal to ’1E000H’
:>< D
:JC =M001 ju mp to labe l M001
:
:JU OB 227 read checksum if address counter equals ’1E000H’,
:
:L FW 250 load checksum flags
:!=F if e qual , bloc k en d
:BEC
:
:STP if not equal, stop operation
:BE
6
O B 227: Reading the Checksum of the Sy stem Program
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 97
6.29 O B 228: Reading Statu s Information of a Program Processing Level
Function
If a part icu lar even t occ urs, th e system program calls th e
co rrespo n di n g program pro ce ssin g level. The program process in g
level is then "activated".
Using org anizatio n bloc k OB 228, you ca n fin d out wh et h e r a specific
program process in g level is acti ve o r n ot at a partic ular ti me. T ransfer
t he nu mber of the program processing level whose stat us you want to
scan to ACCU 1. (The numbers are those entered under LEVEL in the
ISTACK).
When the block is called, it stores the status inf ormation of the
speci fied program level in AC CU-1- L. By ev aluatin g this
i nf or ma ti on , you c an mak e yo ur p r ogr a m e xe cu t io n dep e nd en t on th e
status of another program processing level.
Parameters
ACCU-1-L
Number of the program processing level
(see ISTACK, LEVE L)
possible values (hexadecimal): see follo wing table
Le vel no. in
ACCU-1-L Le vel name
02
04
06
08
0A
0C
0E
10
12
14
16
18
1A
1C
1E
20
22
24
COLD RESTA RT
CYCLE
TIME INTERRUPT 5 sec
TIME INTERRUPT 2 sec
TIME INTERRUPT 1 sec
TIME INTERRUPT 500 ms
TIME INTERRUPT 200 ms
TIME INTERRUPT 100 ms
TI ME INTERRUPT 50 ms
TI ME INTERRUPT 20 ms
TI ME INTERRUPT 10 ms
TIMED JOB
Not used
CONTROLLE R INT ER R UPT
Not used
Not used
Not used
PROCESS INTERRUPT
L evel no. in
ACCU-1-L L evel name
26
28
2A
2C
2E
30
32
34
36
38
3A
3C
3E
40
42
44
46
N o t used
N o t used
N o t used
Abort
Interface error
C ollision of time in terrupt
C ontroller error
Cycle error
N o t used
Operation code error
Runtime err or
Ad dressi ng error
Timeout
N o t used
N o t used
MANUAL
WARM RESTART
AUTOMATIC
WARM RESTART
O B 228: Reading Statu s Informat ion of a Program Processing Level
CPU 928B Programming Guide
6 - 98 C79000-B8576-C898-01
Result
- ACCU-1- L: contains the status information:
= 0 →Program processing l evel has not been
called
≠ 0 →Progra m processing level has been
activated
- ACCU-2- L: c ontains the previous conten ts of ACCU-1 - L;
the previous contents of ACCU-2-L are lost
Po ssib le errors
none
Example
You want to ignore a timeout during the COLD RES TA RT, howe ve r, n ot in
the re main in g pr ogra m proc es sing lev el s.
Call special function organization block OB 228 at the beginning of OB
23 to chec k whet her pr ogra m proc essi ng lev el C OL D RE STAR T (num be r 02 ) is
active or not when a QVZ (timeout) occurs. You can make the reactions to
the er ror de pend ent on the s tatu s in fo rmat ion yo u ob tain a s fo ll ows:
ACCU 1 = 0: COL D REST AR T no t ac ti ve QVZ has not occu rred i n
COLD RESTART, but in another
progra m pr oc essi ng l ev el
Error hand li ng p rogr am mus t be
executed
ACCU 1 ≠ 0: COL D RE ST ART acti va ted QVZ has occu rr ed i n COLD RESTART
QVZ ca n be i gnor ed
Using OB 2 28 , yo u ca n diff er enti ate be twee n va ri ous erro r situ at ions .
6
O B 228: Reading Statu s Informat ion of a Program Processing Level
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 99
6.30 O B 230 to 237: Functions for Standard Function Blocks
Th e specia l functio n o rga niz atio n blocks OB 230 to OB 237 a re
reserved for data handling functions and can onl y be called in the
standard function b locks FB 120 to FB 127.
Data handl ing blocks
These standard function blocks, the data handling blocks known
simply as " handling blocks" , control the data exchange via the page
area in the single and multiprocessor modes. They are used when data
or paramet ers a nd con trol i n form a ti o n are tran sfe rre d to o r fro m th e
c ommunicati ons processors (CPs).
Assign m ent aid
You can use the table below to find out which handling blocks call the
spec ia l funct ion organ iz atio n block s OB 230 t o OB 237.
Standard
function bloc k Special function
O rganization block Hand ling
block
FB 120
FB 121
FB 122
FB 123
FB 124
FB 125
FB 126
FB 127
SF -OB 23 0
SF -OB 23 1
SF -OB 23 2
SF -OB 23 3
SF -OB 23 4
SF -OB 23 5
SF -OB 23 6
SF -OB 23 7
SEND
RECEIVE
FETCH
CONTROL
RESET
SYNCHRON
SEND ALL
RECE IV E AL L
Using the handling blocks
The use of the handling blocks, that can be ordered as a software
produc t on diske tt e, is described in the manual "S5 135U
prog ramma bl e co n tro ll er, ha ndl in g blo ck s for t he R proc esso r and
CPU 928 /928 B" /5/ in Chapter 13).
O B 230 to 237: Functions for Standard Fu n ction Bl o ck s
CPU 928B Programming Guide
6 - 100 C79000-B8576-C898-01
6.31 O B 240 to 242: Special Functions for S hift Registers
6.31.1
Shift Registers This i nt rod u ctio n t ells yo u what yo u ca n use shi f t regi sters for and t he
points to note in doing so.
Application
You can us e shif t re gi st ers, e.g. in a ma n ufa ct uri ng pro cess, to
prog ram a ma te rial s fo ll ow -up o n th e prog ramma bl e con tro ll er. On
the CPU 928B, you have a m aximum of 64 software shift registers
available.
You can write data to the shift register and read data from it. This is
done u sin g "po inte rs" . Po i nt ers are flag byte s t h at con ta in t h e c ont ent s
of individual cells of a shift register.
Structure
A soft ware sh ift reg ister co nsists of rows of 8-bit wide me mor y cells
and can be between 2 and 256 mem ory cells long.
Location in the DB -RAM
The data of a shift register are l ocated in the data block RAM of the
CPU. Eac h shift register is assig ne d to a speci fi c da ta bloc k an d al so
has th e sam e nu m ber as th e d ata block (permi tted : 192 to 255). I f you
set up a shif t register with the number 210, the corresponding data is
i n data block DB 210.
T he DB-RAM has a capacity o f 46 Kb ytes (address KH 8000 to KH
DD7F). This area contains the data blocks (starting from KH 8000 in
as ce nd i ng o rd er) copied u sing OB 254 an d 255 a nd th e sh ift reg ist ers
you h a ve set up (st artin g from KH DD7F i n desc en din g o rde r). If t h e
m e mory area of the DB RAM is not suff ici ent for copying DBs or
setting up shi ft registers, the CPU recognizes a runtime error and calls
OB 31. The rea ct ion s t o th e error d e pend on ho w you ha ve
programmed OB 31 (see Sec tion 5.6.2).
The following schematics illustrate the principle of a software shift
register with three pointers and twelve m em ory cells.
6
OB 240 to 242: Special Function s for Shift Registe rs
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 101
Initializing
When you initialize a shift register (see Section 6.31.2), you specify
t he number of the flag byte for pointer 1 (= base poi nter). This is then
set perma nen tly on the first me mor y cell of the shift register. You then
po si tion all the other pointer s re la tive to th e bas e poi nte r ( you can use
bet wee n on e and a m a x imum o f si x pointers pe r shift reg is te r).
Shifting
Wh en you s hift a s hift r egis te r (like a har dw are shif t r e gis t er), the t ota l
contents of all the shift register cells are transf erred in by tes f rom one
memory cell to the ne xt (see Fig. 6-17). Ea ch t im e t he shift re gi ster
function is called, the information is shifted one memory cell
(co rre spo nd s to o n e cloc k pulse), an d th e poi n te rs are su p plie d w it h
new contents. As shown by the arrows, the information is shifted
thr ough the comp let e shift re gist er t o the la st memory ce ll fr om whe re
it returns to mem ory cell 1 (after 12 clock pulses for the shift register
il lustra ted in th e sche m a tic ).
Pointer 1 Pointer 2 Pointer 3
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
123456 789101112
Flag bit 0
Flag bit 1
Flag bit 2
Flag bit 3
Flag bit 4
Flag bit 5
Flag bit 6
Flag bit 7
Fig. 6-16 Schemati c showing the principle of a shift register with 3 poi nters and 12 memory cel ls
O B 240 to 242: Special Fun ctions for Shift Registers
CPU 928B Programming Guide
6 - 102 C79000-B8576-C898-01
Example
Figures 6-17 and 6-18 illustrate the shifting of information within a
shift regi st er w ith th ree po inte rs a nd twe lve me mory cel ls .
Before the special function is called, certain bits are set in the
pointers (flags) to identify the pointer information, as follows:
Set fl ag b it 0 o f po in ter 1 :S F 0.0
Set fl ag b it 3 o f po in ter 2 :S F 1.3
Set fl ag b it 2 o f po in ter 3 :S F 2.2
The sh ift re gist er f un ctio n is t hen ca lled :JU OB 241
After call in g th e sp ec ial fu ncti on, th e 8- bit wi de i nfor ma tion o f th e
memory cel ls is shif te d by o ne c ell, a s sh own be low:
Continued on the next page
Pointer 1 Pointer 2 Pointer 3
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
123456 789101112
Flag bit 0
Flag bit 1
Flag bit 2
Flag bit 3
Flag bit 4
Flag bit 5
Flag bit 6
Flag bit 7
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
01
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
01
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Fig. 6-17 Schematic showi ng the principle of a shift register wi th 3 pointers and 12 memory cells before the
first c lock pul se
Pointer 1 Pointer 2 Pointer 3
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
123456 789101112
Flag bit 0
Flag bit 1
Flag bit 2
Flag bit 3
Flag bit 4
Flag bit 5
Flag bit 6
Flag bit 7
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
01
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Fig. 6-18 Schemati c showing the pri nci ple of a shift register with 3 pointers and 12 memory cells after the
fir st clock pulse
6
OB 240 to 242: Special Function s for Shift Registe rs
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 103
O rganization blocks
If you want to use a shift register, there are three special function
organi zation blocks availa ble:
•• OB 240:
This funciton initializes a shi ft register.
•• OB 241:
This function processes a shi ft register.
•• OB 242:
This function deletes a shift register.
Continuation of the example:
You ca n no w eval uate t he i nf orma tion i n th e po in ters as fo llow s:
:L FY 0
:
etc.
Flag bits 0, 3 and 2 can be scanned at the base pointer: in this way,
you can evaluate all the information from the entries in all pointers at
the base pointer (in the example, this requires twelve clock pulses).
O B 240 to 242: Special Fun ctions for Shift Registers
CPU 928B Programming Guide
6 - 104 C79000-B8576-C898-01
6.31.2
OB 240: Initializi ng Shif t
Registers
Application
Before proc es sin g a sh ift regis te r, you mu st first in itia li ze i t. Th is is
done by calling OB 240 once (ideally in a restart organization block).
The param et ers that OB 240 requires to c re ate a s hi ft regi st er a re
c ontained i n a data block with the nu mber of the shi ft register to be
i nitialized. D B numbers between 192 an d 255 are permitted.
Function
A spe ci fi c memo ry area a t t h e e n d of t he DB -RAM is reserved an d
initialized with the inf ormation f rom the opened data block.
Parameters
opened data bloc k
pos sible v a lues : DB no . 192 t o 255
The data block has a fixed structure which y ou must not change. It
can have a m aximum length of 9 data words (DW 0 through DW 8).
Number of the 1st flag byte/base pointer
Shift register length (bytes) L
Interval n
2
3
5
4
6
Interval n
Interval n
Interval n
Interval n
DW 0
DW 1
DW 2
DW 3
DW 4
DW 5
DW 6
DW 7
0
0DW 8 or last data word
Fig. 6-19 Structure of the data bl ock for i nitializing a shi ft register
6
OB 240 to 242: Special Function s for Shift Registe rs
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 105
The individual data words must be assigned as follows:
Data word 0
Must always contain the value 0.
Data word 1
The shift register length L is the number (in by tes) of m emory
locations of the shif t register. It can be within the range between
2 ≤ L ≤ 256.
Data word 2
The nu mber of the first flag byte determines the base pointer and with
it t he blo c k of fl ag s a ssig ne d to t he poin t ers. The bl ock of fla gs
co n ta in s the tota l nu m ber o f pointers you hav e se lect ed. Yo u se lect
pointers by making entries in data words DW 3 to maximum D W 7,
using on e data wo rd per p oi nte r.
If, for example, you want to set up two further pointers, you then have
a to tal of t h ree point ers.
Make sure that you have enough flags available f or all pointers up to
the end of the b l ock of fl ag s.
D a ta w or d 3 to m a xi mum 7
You specify the ot her poi nters indirectly. T hey are d efined by their
distance (shift register cells = number of bytes) from the base pointer.
n2 = distance from pointer 2 to base pointer
n3 = distance from pointer 3 to base pointer
n4 = distance from pointer 4 to base pointer
etc. (1 to ma ximum 5 entries)
L as t data wo r d (DW 4 to max imu m DW 8)
(in the example DW 8). This m ust always contain the value zero.
If you only select two additional pointers, the " 0" is in data word
DW 5 etc.
All the inf ormation is specified as fixed point numbers.
O B 240 to 242: Special Fun ctions for Shift Registers
CPU 928B Programming Guide
6 - 106 C79000-B8576-C898-01
Note
The number of pointers (6 including the base pointer) must not
exceed the length of the shift register.
The distance of a pointer to the base pointer m ust not exceed the
length of the shif t register.
Dat a w ord DW 0 and the data wo rd after the last pointer
distance must always contain 0.
The data block must be open before OB 240 is ca lled.
The data block must have a number in the range
DB 192 to
DB 255.
Memory requirements
n = shif t register length/2 + 8 data words
are required for every shift register, i.e. the le ngth of t he DB RAM is
reduced by n data words. The data block RAM end address is shifted
to lower addresses. If you attemp t to initialize a shift r egister that
already e x ists, th e area a lready ass ig ned will be init ia li ze d agai n
provi ding the new and ol d shift registers both have th e same lengt h.
Otherwise the old area will be declared invalid and a new area will be
opened.
Po ssib le errors
•• illegal data block nu mber (<192)
•• no t enough memor y space in the DB RAM
•• formal error in the structure o f the data bloc k
•• ille gal le n gth spec ifi ed fo r th e shift regist er
•• errors in the poi nter paramet ers
In the event of an error, the CPU recognizes a runtim e error and calls
OB 31. What happens then depends on how you have programmed
OB 31 (s ee Sectio n 5.6. 2). If OB 31 i s n o t l o ad ed , the CPU go e s t o the
stop mode.
In both cases, e rro r IDs are e ntered in A CC U-1-L th at d es cribe th e
error in greate r de ta il.
6
OB 240 to 242: Special Function s for Shift Registe rs
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 107
6.31.3
O B 241: Processing
Shift Registers The special function organization block OB 241 processes a shift
register p roviding it has been initialized by OB 2 40.
In th e CPU 928B , yo u ca n call a maxi mu m o f 64 s hif t re gi st ers.
Application
Before yo u ca ll OB 241, ce rt ai n fla g bi ts are u sual ly set/ rese t in t he
pointers.
Each tim e OB 241 is called, the information is shifted byte by by te
from one m em ory cell to the next higher memory cell. The pointers
are the n su pplie d wit h new cont ents . By repea ted ly c al ling OB 241,
the information can be shif ted through the com plete shift register to
the la st me mo ry cell . F ro m here, it is th e n tran sfe rre d to mem ory
cell 1.
Function
Each t ime OB 241 i s proc essed , th e sh ift reg ist er a d dre sse d vi a
ACCU-1-L is shifted one position to the right.
Parameters
ACCU-1-L
Number of the shift register to be processed,
permissible values: 192 to 255
Result
After you call O B 241, the pointers (maximum 6 per shift register)
th a t c an be posit ion ed a s required with th e exce pti on of t he base
pointers contain the information o f the precedin g me mory cell. You
can then evalu ate thi s information.
Po ssib le errors
•• illegal shift register number in ACCU 1
•• shift re gist er not initialized.
In the event of an error, the CPU recognizes a runtim e error and calls
OB 31. What happens then depends on how you have programmed
OB 31 (s ee Sectio n 5.6. 2). If OB 31 i s n o t l o ad ed , the CPU go e s t o the
stop mode.
In both cases, e rro r IDs are e ntered in A CC U-1-L th at d es cribe th e
error in greate r de ta il.
O B 240 to 242: Special Fun ctions for Shift Registers
CPU 928B Programming Guide
6 - 108 C79000-B8576-C898-01
6.31.4
O B 242: Deleting a
Shift Register
Function
With this f unction, you can delete a shif t register in the data block
RAM. The entr y in the DB 0 ad dress list is cleared and the shift
regis te r is decl are d in val id i n th e DB RA M (reme mber: sh if t reg is te rs
st il l occupy memory space a f ter they ha ve bee n delet ed ).
Parameters
ACCU-1-L
Number of the shift register to be deleted,
possible values: 192 to 255
Result
After you call OB 242, th e shift register is dele te d an d ca n no lo nger
be used; if you want to work with it again, it m ust be reinitialized.
Po ssib le errors
•• illegal shift register number in ACCU 1
•• s hift re gi st er not i nitia li zed
In the event of an error, the CPU recognizes a runtim e error and calls
OB 31. What happens then depends on how yo u programmed OB 31
(see Sec tion 5.6.2). If OB 31 is not l oaded, the CPU goes to the stop
mode.
In both cases, e rro r IDs are e ntered in A CC U-1-L th at d es cribe th e
error in greate r de ta il.
6
OB 240 to 242: Special Function s for Shift Registe rs
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 109
6.32 O B 250/251: Closed-Loop Control/ PID Algorithm
You ca n work with o ne o r more PID co ntro llers in t he C PU 928B o f
th e S5-135U. E ach co ntroll er mus t be ini tializ ed i n the restart
org a niza ti o n block . A da ta bloc k is us ed t o tran sf e r the paramet ers.
The actual control algorithm is integrated in the system program and
you can sim ply call it as an organization block. A data block is used
as the data interface between the control algorithm and the user
program.
6.32.1
Functional Description of
the PID Controller
KRTITD
S3
0
1
Y
dY UL
LL
Auto
1
0
S2
0
W
X
XZ
0
1S1
XW
dYA (S3 set to 1)
YA (S3 set to 0)
ZInput of YH when S3 set to 0
Input of dYH when S3 set to 1
S4
P I D
algorithm
Manual input:
Fig . 6-20 Block diagram of the P ID cont rolle r
O B 250/251: Closed-Loop Control/ PID Algorithm
CPU 928B Programming Guide
6 - 110 C79000-B8576-C898-01
Index k
k times samplin g
Switch Setting Effect
S1
CONTROL
BIT 1 0
1
Th e sy s tem er ror X Wk is supplied to
the derivative unit.
The derivative unit can be supplied
w ith an other signal via XZ.
S2
CONTR OL
BIT 0 0
1
Manual operati on
Automatic
S3
CONTROL
BIT 3 0
1
Pos itio n algori th m
Ve loc ity al gorithm
S4
CONTROL
BIT 5 0
1
With feed forward control
Without feed forward co ntrol
ST EU control w o rd
You obt ain a fun ction co rrespo ndin g to the sw itc h se tting s of the
blo ck d i ag ram by ass ign ing paramet ers to t he PI D c on t rol le r, i. e. by
setting the control bits in the control word STEU. The continuous
con tro ll er i s in te nd e d for fas t c ont rol syst ems, e.g. in proc es s
engineering for pressure, temperature or flow rate control.
PI D algorit hm
The controller itself is based on a PID algorithm. Its output signal can
eit her be output as a manipulated variable (position algorithm) or as a
change of m a nip ulated va riable (velocity algori thm).
You can disable the individual P, I and D actions by setting their
paramet ers R, TI a n d TD to ze ro. Thi s all ows you t o impleme nt a ny
con tro ll er stru ct ure you requ i re, e .g . PI , PID or PD co ntro ll ers.
Differentiator
You can supply the derivative unit either with the system error XW or
a d isturbance or the inverte d actual value -x can be supplie d via the
XZ input.
Disturbance compensation
If you require a preco ntrol o f t he a ct ua tor w i th o ut d yna mi c beh avio u r
t o compensate for the i nflue nce of a disturbance, then a disturbance Z
measured in t he proc ess can be fed forwa rd t o th e con tro l al go rithm.
In manu a l o pera ti on , this is replace d by th e presel ec ted m a n ipula te d
variable YM.
6
O B 250/251: Clo sed-Loop Control/ PID A lgorithm
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 111
Inverted control direction
If you requ ire an in verted con tro l d i re ctio n, preset a ne g at iv e K value.
Lim iting the control
information
If the control information (dY or Y) reaches a limit, the I action is
aut omatic al ly d i sabl ed i n ord er to pre ven t de te rio ratio n o f th e
controller response.
You ca n su ppl y th e co ntro l progra m w i th preset fix ed va lu es o r wit h
a daptive (d yna mic) parameters (K, R, TI, TD). These are input via the
memory cells assigned to the ind ividual parameters.
6.32.2
PID Algorithm The PID controller is based on a velocity algorithm according to
wh ich th e co n trol i n cremen t d Y k is calculated at time t = k * TA,
according to the following formula:
dYk=K [ (XWk − XWk−1) R + TA
2TN (XWk + XWk−1) +
1
2
TV
TA (XUk − 2XUk−1 + XUk−2) + dDk−1
]
=K ( dPWkR + dIk + dDk )
dXXXk: c ha nge i n va ria bl e XXX at t ime t .
U can be either W or Z, depending on whether XW or XZ is supplied
to the derivative unit. The following applies:
If XW k is supplied: If XZ is supplied:
PWk = Wk - Xk
PWk = X Wk - XWk-1 PZk = X Zk - XZk-1
QWk = P Wk - PWk-1 QZk = P Zk - PZk-1
QWk = X Wk - 2XWk-1 + X Wk-2 QZk = X Zk - 2XZk-1 + XZk-2
O B 250/251: Closed-Loop Control/ PID Algorithm
CPU 928B Programming Guide
6 - 112 C79000-B8576-C898-01
dPWk= (XWk - XWk-1)R
dIk = TI ∗ XWk T I=TA
TN
dDk = 1
2 (TD ∗ QUk + dDk−1) TD = TV
TA
If you require th e man ipu la te d va riable Yk at the controller output at
time tk, i t is calculat ed according to the follow ing formula :
Yk = ∑
m=o
m=k
dYm
With most con troller struct ures, it is assumed that R = 1 if a P actio n
is required.
Usi ng th e va riable R, you c an a dj ust th e proportion al ac ti o n of t he
PID controller.
Dat a bl ocks for the PID
controller
Cont rol le r-spe ci fi c da ta a re i nput us ing a tran sfer data blo c k (see
Sections 6.32.3 and 6.32.4) for initia lization a nd processing of the PID
controller.
You must speci fy th ese data in t he transfer data blo ck x:
K, R, TI, TD, W, STEU, YH, ULV, LLV
T he transfer da ta block must contain d ata words 0 to 48, i.e. it is 49
data words long. The following table explains the signif icance of
the se da ta words.
6
O B 250/251: Clo sed-Loop Control/ PID A lgorithm
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 113
St ructure of the transfer data
block
Addr.
in DB Name I/O
1)
Nume-
rical
format
2)
PG
format
3)
Remarks
D W0 — — — — Reserve
DD 1 K I F L P KG Pro portiona l co o effic ie nt
K >0: Positive control direction, i.e.
change of actual value and
man ipulated variable in same direction
K <0: Negative control direction, floating point
numb er ra nge
DD 3 R I FL P KG R para me te r, u su ally e qua ls 1 for c ont rol le rs w ith P
action
DD 5 T I I F LP KG TI = TA/T N
DD 7 TD I FLP KG TD = TV/TA
DD 9 WkI FL P KG Setpoin t input here , w h en c o nt rol bit 6 = 1,
otherwise in word no. 1 9 (-1 ≤Wk <1 )
D W11 STEU I FLP KM Control word
DD 12 Y HkI FLP KG Man ual input here, whe n control bit 6 = 1; otherwise
in word no. 18 (-1 ≤YHk <1)
For velocity algorithms, you must speci fiy manipulated
variable increments here
DD14 ULV I FLP KG Upper limit value 4)
-1 ≤ ULV ≤ 1 (YAk max);
!! LLV < ULV !!
DD 16 LLV I FLP KG Lower limit v al ue 4)
-1 ≤ LLV ≤ 1 (Y Ak min)
DW18 YHkI NF KF Man ual input here, whe n control bit 6 = 0
(-1 ≤ YH < 1). For velocity algorithms, you must
specify manipulated variable increments here
DW19 WkI NF KF Setpo in t input here, when c o nt rol bit 6 = 0
(-1 ≤ Wk < 1)
DW 2 0 M ERK I B P KM Bit 0 = 1: pos itive limit exceeded ;
Bit 1 = 1: below negative limi t
DW 21 XkI NF KF Actual value input for control bit 7 = 0
(-1 ≤Xk <1)
DD 22 XkI FLP KG Actual value input for control bit 7 = 1
(-1 ≤Xk <1)
DW 24 ZkINF KF
Dist urbance (-1 ≤Zk <1 )
DD 25 ZkI FL P KG Distu rban ce i nput here, if
control bit 7 = 1 (-1 ≤Zk <1 )
Table 6-10 Transferring the data block for PID control
O B 250/251: Closed-Loop Control/ PID Algorithm
CPU 928B Programming Guide
6 - 114 C79000-B8576-C898-01
Addr.
in DB Name I/O
1)
Nume-
rical
format
2)
PG
format
3)
Remarks
Table 6-10 continued:
DD 27 Zk-1 I FLP K G Hi st or ica l value of the di sturbance
DW 29 XZkI NF KF Value supplied to the derivative unit via input XZ
(-1 ≤XZk <1); input here, i f control bit 7 = 0
DD 30 XZkFLP KG XZ input here, if control bit 7 = 1
(-1 ≤XZk <1)
DD 32 X Zk-1 I F LP K G Hi s tor i cal va lu e of XZk
DD 34 PZk-1 IFLP KGXZ
k-1 - XZk-2
DD 36 dDk-1 — FLP KG Derivative action
DD 38 X Wk-1 — FL P KG Hi st or ica l value of the sys tem er ror
DD 40 PWk-1 — FLP KG X Wk-1 - XWk-2
DW 42 — — — — Reserve
DD 44 Yk-1 — FL P KG Hi st or ica l value of the ca lculat ed man ip ulat ed
variable Yk-1 or dYk-1 b efore the limi ter
DD 46 Y AkF L P K G Output variabl e
DW 48 Y AkNF KF Output variabl e ULV ≤YA ≤ LLV
1) I = input, Q = output
2) FLP = floatin g p o int n um ber, NF = n orm aliz ed fixed po in t n um ber (see p ag e 6 - 103), BP = bit patte rn
3) Suggested format (KH, KM also permitted)
4) In norm aliz ed fix e d po int format, the uppe r and lo wer limit v alue mus t be e n tere d accordi ng to the followin g formulas :
DD 14 = BGOG: V alue as fix ed p oin t num b er =
DD 16 = BGUG: Value as fixed point number =
BGOG
BGUG
32767
32767
6
O B 250/251: Clo sed-Loop Control/ PID A lgorithm
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 115
Ex ample of limit values
- Limit values
Upper limit value = 0.1
Lower limit value = -0.1
- Entr ie s in the D B:
DD 14 : *10 00 000 +0 0
DD 16 : -10 00 000 +0 0
- Output variable is limited:
DW 48 : +-3 276
DD 15 : +-0 .1
Note:
For li mit va lues out si de 1 , the outp ut var iabl e is l imit ed in fl oati ng
point form at (DD 46) .
O B 250/251: Closed-Loop Control/ PID Algorithm
CPU 928B Programming Guide
6 - 116 C79000-B8576-C898-01
Bit assignm ent of the control
word STE U (data word
DW 11 in the transfer DB)
DW 11
Bit no. Name Meaning
11.0 AUTO = 1: Automatic operation
= 0: Manual operation
11.1 X Z_ INP =1 : Ano ther variable (not XWk), is supplied to the derivate un it
by the inpu t
= =: XWk is su pplied to th e de riv at e uni t. Th e XZ i nput
is i gnored.
11.2 DIS_CTR = 1: Whe n the controller is called (OB 251) all variables (DW 20 to
DW 48) except K, R, TI, TD, BGOG, BGUG, STEU, YHk, Wk,
Zk and Zk-1 are cleared once in the DB RAM. The controller is
disabled. The historical value of the disturbance is
updated.
= 0: control
11.3 VELO C = 1: Ve locity algor it hm
= 0: Position algorithm
11.4 1) M A N TY P E = 1 : If VELOC = 0 (p os i tion algor ithm ) the l as t m anip u lated varia b le
to b e outp ut is retained.
If VELOC is 1 (velocity algorithm ) the control increment
dYk = 0 is set.
= 0: If VEL OC = 0, then after switching to manual operation, the
value of the manipulated variable output YA is brought to the
selected manual value exponentially in four sampling steps.
Foll ow i ng this, o th e r manua l v a ri abl es are ac cept ed i mm edi at el y
at th e contr o l ler output .
If VELOC = 1, the manual values are switched through to the
controller ouptut immediately. In manual operation, the limits
are effec ti v e. In manu al operat ion t he fo ll ow i ng variabl es are
updated:
Xk, SWk-1 and P Wk-1
XZk, XZ k-1 and PZk-1, i f co ntrol bit 1 = 1
Zk and Zk-1, if control bit 5 = 0
The variable dDk-1 is set t o = 0 . The al go rithm is not ca lculated.
11.5 NO_Z = 1: n o feed f orward co n trol
= 0: with feedforward control
11.6 P GDG = 1: Wk, YHk input as f loating point number
= 0: Input as normalized f ixed point num ber
11.7 V AR_FLP = 1: T he variables Xk, XZk and Zk are input as floa ting point n umbers
= 0: Input of th e v a riabl es as no rma lized fixed po int n um bers
Ta ble 6- 1 1 Contro l word in t he tr ansfer DB
6
O B 250/251: Clo sed-Loop Control/ PID A lgorithm
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 117
DW 11
Bit no. Name Meaning
Table 6-11 continued:
11.8 BU MP = 1: No bu mpl ess cha ngeover fro m ma nua l to automat ic
= 0: Bumples s ch angeover from manual to automa tic
11.9 to 11.15 Irrelevan t
6.32.3
OB 250: Initializing the
PID Algorithm
Function
OB 250 initializes the PID algorithm and is called in the restart
O Bs 20/21/22.
Parameters
The param et ers re qui red fo r th e init ia li za ti on are con ta ined i n the
transfer data block (DB x).
Note
The transfe r data bloc k must be o pen befo re OB 250 is calle d.
For da ta t ran sfer, e ac h con tro ller requi re s i ts o wn DB x (x ≤254).
From this, the sy stem program automatically generates a f urther
DB x + 1 in the data block RAM, that the controller uses as a data
field in cyclic operatio n. T h is mean s t hat the correspon di n g DB
numbers must still be avai la ble. Da ta blo ck s DB x + 1 re pre sen t th e
data interfaces between the controller and the user or peripheral I/Os.
Po ssib le errors
Intern al ly, OB 250 u se s OB 254 or OB 255 (du pli ca ti on of da ta
block s). In t h e ev ent of a n erro r, the CPU recogn iz es a runtime e rror
and calls OB 31. If this is not programmed, the CPU goes to the stop
mode. The error IDs entered in ACCU 1 then refer to OB 250.
O B 250/251: Closed-Loop Control/ PID Algorithm
CPU 928B Programming Guide
6 - 118 C79000-B8576-C898-01
Note
If DB x + 1 is not kept f ree during the initialization, it will be
used as a contro l ler dat a fi eld withou t any war ning if it s length is
identical to that of a controller DB (49 data words); data words 20
thr ough 48 a r e cle are d. O th er wise th e CP U go es t o th e stop mo de.
Instead of DB data blocks, you can also use DX data blocks.
Initialization is the same as with DB data blocks.
6.32.4
OB 251: Processing the
PID Algorithm
Application
OB 251 is called during cyclic program execution and processes the
PID algorithm.
Call
The co n tro ller sho u ld be call ed a f te r the sam pling tim e ha s e la psed.
K eep to the follow ing order:
Step Action
1 Call data block DB x + 1
2 Lo ad input data X k, XZ k, Zk and YHk or a sub set of
these
3 Co nv ert input d at a to t he c orrec t form at and trans fer it
to D B x + 1
4 C all O B 2 5 1 (process P ID contr oller )
5 Load the output data YAk fr om DB x + 1
6 Co nv ert th e data a nd t ran sf er t o th e process I/Os
6
O B 250/251: Clo sed-Loop Control/ PID A lgorithm
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 119
F or ma t of control ler in pu ts
an d outputs
Int ernally, th e PID con trol a lg orithm uses t he floa ting po in t format for
num erical representation and can be supplied with floating point
val ue s. You c an a ls o su ppl y the PID co ntroll er a lg o rith m u sin g t he
norm alized f ixed point f ormat (see bits 6 and 7 in the control word
STEU). In this case, the controller automatically con verts the words to
the f loating point format with every call.
Adaptation o f words fro m the input and ou tput mo dules in the STEP 5
progra m i s faster if you use the no rmalized fixed poin t format (see
table a t the end of this sect ion).
Inputs
You can input W, YH, X, Z and XZ as floating point or normalized
fixe d poi nt nu mbers. Di fferent memory cells are reserved for eac h
variable in the data transfer block.
Input as norm alized fixed
point numbers
(For an explanation of the normalized fi xed poi nt nu mbers, see the
table a t the end of this sect ion).
Note
While keeping within the nominal input ran ges of the anal og
input mod u le s, do n o t forg et th a t t he bit pa tt ern for a certain i n put
valu e is different fro m when yo u use th e fu ll i nput ra n ge . T h is is
par t icularly im p or tant when you adjust the s etp oint. O therwi s e, it
is poss ible t hat a s et po i nt i npu t at th e PG c an n ot be reac hed
alt hou gh th e actual value is far higher than th e desired value.
If your an a lo g -to-di gi ta l co nverte r su pplie s neg ati ve n umbers as a
nu mber an d si gn, the 2’s co mplement of this number must be formed
bef ore it is transf erred to the controller DB. Following this, the binary
digit 15 must be set to 1.
If the nu mber -0 is possible as a number and sig n in th e fo llo w in g
format:
1000000000000000
in you r an al o g-t o-dig i ta l c onve rt er, the 2’s co mplemen t must n ot be
formed. The number must be trans ferred to the controller DB as +0:
0000000000000000
Output
The co n troller ou tput YA ex i sts in the DB as a n o rm al ized fi xe d poin t
number and a floating poi nt number. Ta kin g into account the input
and output m odu les used (an alo g-to-digi tal co nve rter,
digital-to-analog converter) the format must be converted f or
norm alized f ixed point inputs and outputs before and after the
c ontroller is called i n the STEP 5 user program before val ues are
t r ansf er red to or fr om th e controller DB.
O B 250/251: Closed-Loop Control/ PID Algorithm
CPU 928B Programming Guide
6 - 120 C79000-B8576-C898-01
G ener al notes
Using BUM P
If BUMP (cont rol bit 8) is set to zero, the changeover fro m manu al to
au t omatic o perat io n i s bumpless, i.e. the syste m error, ho we ver large
it may be, is corrected o nly by the I action. If, however, yo u have
selected TI = TA/TN = 0 (P or PD c ontroller) th e system error does
not c au se a ch an ge of the man i pulat ed v ariable w h en t h e c h an geo v er
ta kes pl ac e.
You can prevent this by setting BUMP = 1. This means that a system
erro r is cor re ct ed quic k ly when t h ere is a manu al -to - aut omat ic
c hangeo ver, irrespective of TI = 0. The manipulat ed variable j ump
t hat results corresponds t o th e value of th e system error, which mean s
th a t i t is not arbitrary in the sense of a disturbance of the controller
operation.
Displayi ng MERK, bits 0
and 1
Bit s 0 and 1 o f M E RK can be d is playe d if required to sho w t ha t th e
ma nipula te d variabl e (fo r vel oc ity alg orithm, th e co n trol increme nt)
lies betwee n th e upper a n d lo wer l imit s. Since t hese bits a re e valu a ted
by the algorithm f or disabling the I action, you cannot overwrite them.
Note
You must not r eload the contr oller da ta blocks DB x + 1 during
cy clic op eration.
Cascade control
If two or m o re co n troll ers a re c asca de d , remember the fo ll owing
points:
•• If the cascade is split, either all the controllers have to chan ge to
man ual operat io n si mu ltaneously to prevent any controller dri ft
due to the I action or at least the controller of the outer loop m ust
be operated manually to ensure that the last ma nipulated variable
corresponding to the setpoint of the inner loop is retained or
changed to a safe value.
•• If you wa nt t o close t h e c ascade , both l o ops sh oul d ope ra te a t t h e
same time in the automatic mode or at least the inner loop to
ensure that the manipulated variable of the outer loop is taken as
the setpoi n t.
Swit ching t o m anual mo d e
If the control system is disconnected from the controller and directly
a djusted at the actuat or following the cha ngeover to man ual operation,
the manipulated variable obtained must be supplied to the controller
via the m a n ual in put . T his ensu res that wh en you cha nge from man ual
to au to ma ti c operatio n, th e co n troller ou tput wil l c o rrespond to the
manipu late d va ria ble set d urin g ma nu a l operati on . In t he c as e of the
velocity algorithm, this will be the change in the manipulated variable.
6
O B 250/251: Clo sed-Loop Control/ PID A lgorithm
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 121
Contro ller param eters
P controller
The parameter for a P controller is K. This is the quotient of the
output and input value: K = Xout/Xin.
PI controll er
T he parameters for a PI controller are the proportional cooe fficient K
a nd th e reset time TN. The proportional coo efficient K is th e quotient
of the output and input value and determ ines the P action. The reset
time TN is the time required to respond to a ch iev e th e same chan ge in
the manipulated variable due to the I action as occurs due to the P
action.
PD controller
The param et ers for a PD cont ro l ler are the proportion al coo effic ie nt K
(see a bo ve) an d th e de riv at iv e ti me c onstan t TV. Th e deriv a ti ve t ime
constant is the time a P controller would require at a constant rate of
change of the input variable to bring about the same change in the
out put v ariable t hat is bro u ght abou t i mm ed i at el y by t h e D ac ti on o f a
PD controller. To determine the derivativ e time constant, a linear
change in the input variable is assumed and no t a jump function.
Xin Xout
t=0 tt=0 t
Xin Xout
t=0 tt=0 t TN
Xin Xout
t=0 tt=0 t TV
O B 250/251: Closed-Loop Control/ PID Algorithm
CPU 928B Programming Guide
6 - 122 C79000-B8576-C898-01
PI D controller
T he parameters for a PID controller are the proportional c ooefficient
K, t h e reset time TN a nd th e d e ri vat iv e ti me co nstan t TV. Th es e i n
tur n dete rmin e the P, I and D ac tions.
Param eter chan ges
The P action of the manipulated variable is obtained based on the
foll owi n g for mul a:
P action = KP * (XWk - XWk-1)
If KP o r R are ch ang ed d urin g aut omatic o perat ion , t h is on l y aff ects
subsequent chan ges of the s yste m error X Wk. The current value of the
manipulated variable is not affected by the parameter change. This
respo nse al lows for a bum ples s c ha nge .
I f, h ow ev er, you do no t w ant this respo n se, you can elimin ate it using
the following calculation, (example of a KP chan ge). This calculation
is only m ade once fo r each para mete r chang e:
Yk-1 = Yk-1 + XWk-1(KPnew - K P old)
If y o u use t he foll owing program in the c ase of a p aramet er cha nge,
the controller responds li ke an analog controller.
:L KPnew loa d K P new
:L KPold load K P old
:-G
:L DD38 XWk-1
:xG
:L DD44 Yk-1
:+G
:T DD44 = Yk-1
Ab br eviatio ns for P ID
controllers
dYkCalculated control increment
dZkDisturbance increment
FLP Floating point representation
k k * sampling
K Proporti onal cooe fficient
LL Lo wer limit (limi ter )
NF Normalized fixed poi nt representatio n
R R parameter
T A Sampling time
TD TV/TA
TI TA/TN
t Sampli ng instant = k * TA
TN Reset time
T V Der i vati ve time cons tant
UL Upper limit (limiter)
WkSetpoint
XkActual value
XWk System error
YkCalculate d manipulated variable
YAkV al ue of manipu la ted varia b le ( co ntr ol i ncr em ent or
manipulate d variable)
Zk Disturbance
6
O B 250/251: Clo sed-Loop Control/ PID A lgorithm
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 123
No rm al ized fixed point
numbers
One word is required to represent a normalized fixed point number in
a data block. The f ollowing exam ple illustrates the difference between
a fra ction represe n ted de cimall y, i n bin ary an d usi ng t he KF form a t on
the programmer.
F raction in Fixed poin t
number
Decimal
representation Binary representation
-0.999... .
-0.75
-0.5
-0.25
0
+0.25
+0.5
+0.75
+0.999... .
1000000000000001
1010000000000000
1100000000000000
1110000000000000
0000000000000000
0010000000000000
0100000000000000
0110000000000000
0111111111111111
-32767
-24576
-16384
-8192
0
+ 8192
+16384
+24576
+32767
Negative no rmalized fixed po in t nu mbers in a b inary r epr ese nt ation
are o btai ned by form ing the 2’s co mplement o f the positive
nor malized fixed point number.
Normalized f ixed point numbers (NF) can be converted to the values
represe nte d in t he program me r (K F) as fol lows:
NF * 32767 = KF
where -1 < NF <+1 and -32767 ≤ KF ≤ +32767
T able 6-12 Fr act ion
O B 250/251: Closed-Loop Control/ PID Algorithm
CPU 928B Programming Guide
6 - 124 C79000-B8576-C898-01
6.33 O B 254, OB 255: Transferring a Data Block to the DB RAM
Special function organ ization blocks OB 254 and OB 255 allow you
to transfer d a ta block s from th e us er mem ory t o the DB RAM (da ta
block memory) o f the C PU. T he speci al fun c tions OB 254 a nd 255 are
identical; OB 254 is used for DX data block s and O B 255 fo r DB data
blocks.
Application
Shif ting or duplicating a data block
Function
Shifting
Shifting a data block f rom the user memory to the DB RAM
A data block is shifted f rom the user memory to the DB RAM and
ret ains its original bloc k number. The new st art addr e ss of the data
b lock is en ter e d in the address list in DB 0.
Duplicating
A data block in the user mem ory or in the DB RAM is duplicated in
the DB RAM an d a ssigned a new block number. The star t addr ess of
the new data block is enter e d in the addr es s li st in DB 0 . The s tart
a ddress of the o ld block is retained in DB 0, i.e. the original data
block remains valid.
The start ad d ress is on l y en te red int o DB 0 aft er the t ra nsf er i s
com pl et ed a n d all id en ti f ie rs are en t ered correctly i n the bl ock h ea d er.
The duplicated block is only accepted as valid or existing by the
sys tem p rog ram after it has been complete ly transferred.
Note
Shifting DB0 into the DB-RAM is not possible since it already
exis ts in th e D B-RAM. Ho we ve r, you can duplicate DB 0.
6
OB 254, OB 255: T ransferring a Data Block to the DB R A M
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 125
Parameters
1. ACCU-1-L- L
Number of th e data bloc k to be shifte d or duplicated,
permitted values: 0 to 255
(0 only for DX or for
duplica ti ng DBs )
2. ACCU-1-H -L
With the value in ACCU-1-H, you speci fy whether you want to shift
or duplicate a block :
ACCU-1-H-L = 0:
t he data block DB (OB 255 call) or DX with the number spec ified i n
AC CU-1-L-L is shifted t o the D B RA M
ACCU-1-H-L = nu mber for new block,
permitted values: 1 to 255
t he data block DB (OB 255 call) or DX (OB 254 call) wit h the
number specified in ACCU-1-L-L is duplicated in the DB RAM and
e ntered in DB 0 with the nu mber stored in ACCU-1-H-L.
The values for ACCU-1-L-H and ACCU-1-H-H are not consi dered by
OB 254 a n d OB 255 and are th erefo re n o t sign ificant fo r as signing
paramet ers to t he OB s.
Po ssib le errors
•• The data block t o be shifte d does not exist (OB 19).
•• T he block already exists in the DB RAM (OB 31).
(t h erefo re o n ly ex ecut e the fun ctio n on ce, i de ally du ring the
start-up).
•• N ot eno ugh memory space in the DB RAM (OB 31).
In the event of an error, the f unction is not executed. The system
program detects a runtime error and calls O B 19 or OB 31. H ow the
CPU react s t o th e error de pe nds on the way i n whi ch OB 19 or OB 31
are programmed (see Section 5.6.2).
If OB 19 or OB 31 is not programmed, the CPU goes int o the st op
mode. In both cases, ACCU 1 contains an error identifier that defines
the error in greater detail .
O B 254, O B 255: Transferring a Data Block to the DB RAM
CPU 928B Programming Guide
6 - 126 C79000-B8576-C898-01
Example
It is ass um ed t hat th e da ta blo cks DB 3 an d DB 4 are defi ne d in t he u ser
memory. No DB should yet be present in the DB-RAM other than DB0. The
following table shows the memory configuration after calling OB 255
several times with the parameters listed in the table.
Order
of
call
Function ACCU -1- DB in memory after call
-H-H -H-L -L- H -L-L U ser mem. DB-RAM
1Shift no
sig-
nifi-
cance
0no
sig-
nifi-
cance
3 DB 4 DB 3
2 Dup l ica te 5 4 D B 4 DB 3,5
3 Duplica te 6 5 DB 4 DB 3,5,6
4 Shi ft 0 4 no DB DB 3,4,5,6
6
OB 254, OB 255: T ransferring a Data Block to the DB R A M
CPU 928B Programming G uide
C79000-B8576-C898-01 6 - 127
Contents of Chapter 7
7 .1 A p plicati on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 4
7.2 Structure of DX 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 5
7.2.1 Example of DX 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 7
7.3 Parameters for DX 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 8
7.4 Examples of Parameter Assign ment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 13
7.4.1 ST EP 5 Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 13
7.4.2 Parameter Assig nment using the P G Scree n Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 15
7
Extended Data Block DX 0
7
CPU 928B Programm ing Guide
C79000-B8576-C898-01 7 - 1
7Extended Data Block DX 0
The fol low i ng ch apter explain s ho w t o use the data bloc k DX 0 an d
how it is structured. You will f ind information about the meaning of
the v arious DX 0 pa tt erns a n d will learn ho w t o creat e an d ho w t o
as sign parame te rs via a scre en form fo r a DX 0 data blo c k base d on
examples.
7
CPU 928B Programming G uide
C79000-B8576-C898-01 7 - 3
7.1 Application
You can m atch some of the activitie s of the system prog r a m to your
own pa rti cu la r requ irements by selecting settings in DX 0 that differ
from the defaults (marked in the following table by " D" ).
The system program def aults (D) are set autom atically at each COLD
RESTART. Following this, DX 0 is evaluated. If you do not program
and load a DX 0 block, the defaults remain valid; otherwise, the
sett in gs you ha ve m ade in DX 0 beco me v alid.
You program DX 0 just as with other data blocks by assigning values
using STEP 5 statements, (see Sections 7.2 to 7.4.1) or (with PG
system software S5-DOS from Version 3.0 onwards) entering the
values as parameters in a special screen form o n your PG (see
Sec tion 7. 4.2) .
Note
Entries or changes to DX 0 only become e ffective when you perform
a COLD RESTART.
If a m odified DX 0 comes into effect during a COL D RESTART,
a ny parameters yo u do not modify are retained.
Application
CPU 928B Programming Guide
7 - 4 C79000-B8576-C898-01
7.2 Struc tu re of DX 0
DX 0 is made up of the following three parts:
•• t he start ID for DX 0 (DW 0, 1 and 2)
•• several fields of var ying le ngt hs (depending on the number of
para meters)
•• the end delimiter EEEE.
Start ID
ASCII characters MAS KX0 in D W 0 to D W 2
Field
A field in DX 0 consists of 1 to n data words, these contain the
following:
•• t he fi el d ID
•• t he fi el d le ngt h
and
•• the field parameters.
The field ID ex plains th e mean ing o f th e paramet ers that fo llow. Ea ch
field is assigned t o a specific system program part or to a specific
sys tem function ( e.g. fi eld ID "0 4" me ans cyclic progr am execution) .
F ield length
The field length in dicates the number of data words needed for the
parameters th at foll ow.
Parameters
Sec tio n 7.3 de sc ri bes the poss ible parameters.
Numerical values are specified in hexadecimal f ormat (K H).
End ID
This indicates the end of DX 0 with EEEEH in the last data word.
7
Structure of DX 0
CPU 928B Programming G uide
C79000-B8576-C898-01 7 - 5
F orma l structure:
1
B
0
4
4
3
D
3
8
4
5
5
Field ID 1 Field length 1
Field ID 2
Field ID n Field length n
Field length 2
Parameter
Parameter
Parameter
Parameter
Parameter
Parameter
ASCII
chars.:
Field 1
Field 2
Field n
End ID
15 8 70Bit no.
0
1
2
3
DW
DW m
EEE E
Parameter
MA
SK
X0
Fig. 7 -1 Structure of DX 0
Structure of DX 0
CPU 928B Programming Guide
7 - 6 C79000-B8576-C898-01
7.2.1
Example of DX 0
When assign ing parameters in DX 0, remember the following points:
•• You can en te r ind ivi du a l fi el ds in a ny order.
•• You do no t ne ed t o specify fie lds you a re not going t o us e.
•• If a field exists more than once, the f ield y ou enter last is valid.
•• You can enter individual parameters in any order.
•• You do n ot need t o specify para me te rs you a re n o t go i ng t o u se.
•• If a particular paramet er i s spe ci fi ed s ev eral times , the para mete r
last specifie d is v al id .
Start ID DW 0: KH = 4D41
DW 1: KH = 534B
DW 2: KH = 5830
Field ID/len gth DW 3: KH = 0101
Parameters ( occu pies 1 DW) DW 4: KH = 1001
Field ID/len gth DW 5: KH = 0402
Parameters ( occu pies 2 DW) DW 6: KH = 1000
DW 7: KH = 0040
End ID DW10: KH = EEEE
Fiel d 1
Fiel d 2
7
Structure of DX 0
CPU 928B Programming G uide
C79000-B8576-C898-01 7 - 7
7.3 Parameters for DX 0
F ield ID /
length Parameters
1st/2nd wor d Meanin g 1)
R ESTART and RUN:
02xx 2) 1000
1001
D AUTOMAT I C WARM REST A RT aft er POW ER UP
AUTOMATIC C O LD RESTART after POWER UP
2000
2001
D S yn chronizati on of RESTART in multiprocessor operation
No s ynchronizatio n of RESTART in multiprocessor operation
3000
3001
D A ddr es sing error monitoring
No addressing error monitoring
4000
4001
D WARM RESTART
RETENTIVE COL D RESTART
6000
6001
D Floa ting po int arithme ti c wit h 16-bit m a n tissa (optimized fo r
speed)
Flo a ti ng po int arithme tic with 24-bit ma n tissa (optimized fo r
accuracy)
B B00 yyyy Number of timers to be updated 3)
De fault : y y yy = 2 5 6 time rs, i.e .
ti mer 0 to 255
permitted: 0...256
Cyclic program execution
04xx 1000 yyyy Leng th of t he cycle moni toring tim e in m illiseconds;
default: yyyy = 150 ms,
permitted: 1≤ yyyy ≤ 32C8 (hex)
1 m s to 13000 ms (dec)
4000
4001
D Update of the process image of the IPC flags without semaphore
protection
Upat e of t he process ima ge o f th e IPC fl ags with semapho re
protec ti on (in the field, see Sec ti on 10.1.3)
Table 7-1 DX 0 parameters and thei r meani ng
Parameters f or D X 0
CPU 928B Programming Guide
7 - 8 C79000-B8576-C898-01
F ield ID /
length Parameters
1st/2nd wor d Meanin g 1)
Table 7-1 continued :
Interrupt-d riven program execution
06xx 4) Selection of the processi ng mo de 4)
2000
2001
D Process interrupt signal, level-triggered
Process interrupt signal, edge-triggered
Error handling
10xx
1000
1001
C ollision of time in terrupts
D System stop when the event occurs and OB 33 is not loaded
No system stop w h e n th e ev ent o cc urs an d OB 33 is no t loa de d
1200
1201
Contr olle r error handling
D System stop when the event occurs and OB 34 is not loaded
No system stop w h e n th e ev ent o cc urs an d OB 34 is no t loa de d
1400
1401
Cycle error handling
D System stop when the event occurs and OB 26 is not loaded
No system stop w h e n th e ev ent o cc urs an d OB 26 is no t loa de d
1800
1801
Operation code error handli ng
D System stop when the event occurs and OB 27/29/30 is not
loaded
No system stop w h e n th e ev ent o cc urs an d OB 27/2 9/ 30 is no t
loaded
1A00
1A01
Runtime error handling
D System stop when the event occurs and OB 19/31/32 is not
loaded
No system stop w h e n th e ev ent o cc urs an d OB 19/3 1/ 32 is no t
loaded
7
Parameters f or D X 0
CPU 928B Programming G uide
C79000-B8576-C898-01 7 - 9
Field ID/
length Parameters
1st/2nd wor d Meanin g 1)
Table 7-1 continued :
1C00
1C01
A ddress ing err or handling
D System stop when the event occurs and OB 25 is not loaded
No system stop w h e n th e ev ent o cc urs an d OB 25 is no t loa de d
1E00
1E01
Timeout error h andling
Sy stem stop when the event occurs and OB 23/24 is not loaded
D No syst em stop w h e n th e even t o cc urs an d OB 23/2 4 is no t
loaded
2000
2001
Interfa ce error ha ndling
Sy stem stop when the event occurs and OB 35 is not loaded
D No syst em stop w h e n th e even t o cc urs an d OB 35 is not loa de d
E EEE E nd de limi ter
1) D = Default with DX 0 not lo aded or block mis si ng
2) xx = field length (number of data words occupied by the parameters)
3) For updating timers, please read the explanation on the following page
4) For parame ters and t hei r sig n ifi can ce , see the t able on page 7-12.
Note
The current PG software (STEP 5/ST Vers. 6 or STEP 5/MT
Vers. 2) for generating DX 0 using a screen form does not transfer
the parameters for interface error handling (2000 or 2001) and for the
selection "Warm restart or retentive cold restart"
(4000 or 4001).
You can enter these parameters e.g. with the "output block" PG
function (do not forget to change the block length). You can n o
longer edit a DX 0 modified in this wa y using the output screen form
o f the current PG so ftware.
Parameters f or D X 0
CPU 928B Programming Guide
7 - 10 C79000-B8576-C898-01
Updating the tim e r s
•• As standard, the timers T 0 to T 255 are updated.
•• If you enter the value " 0" in DX 0, no timers are updated, e ven if
they a re in cl ude d in t he program. T h ere is th en a lso no e r ror
message output.
•• Upda ti n g is as fol low s:
Entry ’0’ ’1 ’ and
’2’ ’3’ and
’4’ ’5’ and
’6’ ’7’ and
’8’ ....
Updating no ne T0 to
T1 T0 to
T3 T0 to
T5 T0 to
T7 ....
Note
You can also assign parameters to the n umber o f ti mers in data block
DB 1 (see Section 10.1.6). However, we recommend that you
specify this para meter only in D X 0.
If you s et the n umber of timers b oth in DX 0 and in DB 1, th e
value you specify in DB 1 will be valid!
7
Parameters f or D X 0
CPU 928B Programming G uide
C79000-B8576-C898-01 7 - 11
Parameters f or int errupt
processing
You can us e t h e t abl e below t o find th e cor rect parame te r fo r yo ur
in t errupt proc ess ing and yo u ca n pro gra m DX 0 wit h th is parame te r.
Dependi ng on the para meter you select, s ome (or all ) interru pts wil l
be effective a t block boundaries and other (or al l) interrupts will be
effec ti ve a t operati on bounda ries, a ccording to the shad ing in the
symbols.
Note
If you enable interrupt processing at operation boundari es, the
operations "TNB " "TNW" ma y also be interrupted. This also applies
to a few of the special function organization blo cks, standard
function blocks and control ler function blocks.
1) The PG software for generating DX0 uses the "old" parameters. If you generate a DX0 with new parameters using
STEP 5 and want to displ ay it on the PG, an error message is displ ayed.
5s 2s 1s
122C D
1224
1220
121C
1216
1214
1212
1210
120E
120C
120A
1208
D = Default
Interrupts at block boundaries
Interrupts at operation boundaries
Cont.
int. Proc.
int
Delay
int.
10
ms
20
ms
50
ms
100
ms
200
ms
500
ms
Clock
int.
Time interrupts
1206
1204
Para-
meter/
(old)
1)
(100C)
(100A)
(1008)
(1006)
Parameters f or D X 0
CPU 928B Programming Guide
7 - 12 C79000-B8576-C898-01
7.4 Exa mple s of Pa ra mete r A s signm e nt
7.4.1
STEP 5 Program m i ng
Example A:
In mu ltip ro cess or o pe rati on , yo u wa nt to use th ree CPUs : CPU A, B a nd C .
CPU A and B operate closely together, often exchange data and process a
complex restart program. CPU C is largely independent and has a short,
time-critical program.
As st anda rd , al l CP Us in mu ltip roce ss or o pera ti on s tart c ycli c prog ram
execution together, i.e. the CPUs wait until all CPUs have completed
their restart procedures and then start cyclic program execution at the
same time.
Since CPU C runs a v ery short restart program independent of the other
CPUs, its restart procedure does not need to be synchronized. By
assigning parameters in DX 0, you can arrange for CPU C to start cyclic
program execution immediately after its restart, without waiting for CPU
A and B.
Programming DX 0 for CPU C:
DX 0 st ar t ID "MA SK X0" DW 0: KH= 4D41
DW 1: KH= 53 4B
DW 2: KH= 58 30
1st fi el d ID/l en gth D W 3: KH= 02 01
para me ter 1 DW 4: KH= 20 01
end de li mite r DW 5: KH= EE EE
Once you have loaded this DX 0 in the program memory, it becomes
effective after the next COLD RESTART. Since CPU C processes a very
short restart program and does not wait for A and B, its green LED is
lit immediately following the restart. The BASP signal (disable command
output) is, however, only cancelled when all three CPUs have completed
their restart. This means that CPU C cannot access the digital
peripherals.
7
Exam ples of Parameter Assignment
CPU 928B Programming G uide
C79000-B8576-C898-01 7 - 13
Example B:
Assign ing th e pa rame te rs t o DX 0 as sh own belo w achi eves t he f ol lowi ng:
- the add ress in g er ror mo nito ri ng i s di sa bled ,
- the timer updating is disabled,
- the cycle time is set to 4 sec.
DX 0 start ID "MASKX0 DW 0: KH = 4D41
DW 1: KH = 534B
DW 2: KH = 5830
1st field ID/length DW 3: KH = 0203
parameter DW 4: KH = 3001
parameter 1) DW 5: KH = BB 00
DW 6: KH = 0000
2nd field ID/length DW 7: KH = 0402
parameter 1) DW 8: KH = 10 00
DW 9: KF = +400 0
end delimiter DW10: KH = EEEE
This a ssig nm ent of p ar amet er s to DX 0 has the fo llow ing ef fect s on
prog ra m exec ut ion:
- The part of the process image not assigned to peripheral I/O modules
can be used as an additional flag area.
- The runtime of the system program is reduced, since no timers are
updated.
- A cycle error is only detected when the runtime of the user program
and the system program together exceeds 4 sec.
1) Parameters occupying two words must be identified with "2" when
specifying the field length.
Examples of Param eter A ssignment
CPU 928B Programming Guide
7 - 14 C79000-B8576-C898-01
7.4.2
Assi gn ing Param eters
usin g the PG Screen Form Fr o m sta ge IV of the PG s yste m software S5-DOS, screen forms are
ava il able for ass ig nin g param et ers to DX 0. The PG so f tw a re
generates the data block DX 0 automatically according to the
parameter defaults an d the parameters you have specified. T wo screen
forms are required for th is parameter assignment.
For the basic steps you require to select and complete PG screen
for ms , se e your STEP 5 manual.
Com pleting the DX 0 screen
forms
The PG sc ree n form for comple ti ng DX 0 is in t wo parts.
T he first DX 0 screen contains the first group of parameters ( Fig. 7-2):
RESTART AFTER POWER UP
SYNCHRONIZE MU LTIPROCESSOR RESTART
BLOCK TRANSFER OF IPC FLAGS
ADDRESS ERROR MONITORING
CYCLE TI ME MO NITO RI N G
N O . OF TIMER CELL S
ACCURACY OF FLOAT. POINT ARITHMETIC
DX 0 - PARAM. ASS. (S5 135U: CPU 928, R PROCESSOR)
256NO. OF TIMER CELLS ( R PROC: 0 - 128
CPU 928: 0 - 256 )
16 - BIT MANTISSAACCURACY OF FLOAT. POINT ARITHMETIC
#24-BIT MANTISSA ONLY BY CPU 928#
YESSYNCHRONIZE MULTIPROCESSOR RESTART
1RESTART AFTER POWER UP: ( 1 = WARM RESTART
2 = COLD RESTART )
NOBLOCK TRANSFER OF IPC FLAGS
YESADDRESSING ERROR MONITORING
15CYCLE TIME MONITORING (X 10 MS) ( R PROC.: 1 - 400
CPU 928: 1 - 600 )
SELECT CONTINUE
DX 0
F 1 F 2 F 3 F 4 F 5 F 6 F 7 F 8
Fig. 7-2 PG screen form for assi gni ng parameters to DX 0 /part 1
7
Exam ples of Parameter Assignment
CPU 928B Programming G uide
C79000-B8576-C898-01 7 - 15
Once you have selected all the parameters in the first screen form for
your appl ic at io n, you can di splay th e se con d scre en fo rm (F ig. 7-3 )
with the foll owing group of parameters:
ADDRESS. ER ROR, CYCLE ERROR
ACKNOWL. ERROR, TIMER ERR.
COMMAND CODE ERROR, CONTRO LLER ERROR
RUN TIME ERRO R
PROC ESS INT SERVI CI NG
INTERR UPTABI LI TY OF USER PROG R A M B Y
INTERRUPTS
The following flowchart explains how to complete the screen forms,
st ore th e paramet ers and lo a d th e gen erat ed d a ta blo ck DX 0.
DX 0 - PARAM. ASS. (S5 135U: CPU 928, R PROCESSOR)
SYSTEM STOP IF EVENT OCCURS AND ERROR OB IS MISSING
PROCESS INT. SERVICING
INTERRUPTABILITY OF USER PROGRAM BY INTERRUPTS:
1: ALL INTERRUPTS AT BLOCK BOUNDS
2: ALL INTERRUPTS AT OPERATION BOUNDS
3: ONLY PROCESS INTERRUPTS AT OPERATION BOUNDS
4: ONLY PROC: AND CONTROLLER. INT. AT OP. BOUNDS
X: (X=10 , . . . 17) TIME INT. FROM OB10 - OBX AND CONTROLLER/PROC
INTS. AT OP. BOUNDS #ONLY POSSIBLE WITH CPU 928#
MODE 1
YES
YES
YES
LEVEL - TRIGGERED
(OB 25)
(OB 23, 24)
(OB 27, 29, 30)
(OB 19, 31, 32)
ADDRESS. ERROR
ACKNOWL. ERROR
COMMAND CODE ERR.
RUNTIME ERROR
YES
NO
YES
YES
CYCLE ERROR
TIMER ERR.
CONTROLLER ERR
(OB 26)
(OB 33)
(OB 34)
SELECT CONTINUE
DX 0
F 1 F 2 F 3 F 4 F 5 F 6 F 7 F 8
Fig. 7-3 PG screen form for assi gni ng parameters to DX 0 / part 2
Examples of Param eter A ssignment
CPU 928B Programming Guide
7 - 16 C79000-B8576-C898-01
F lowchart for com pleting th e
DX 0 s creen forms.
Yo u will fi nd an ex a mple t o fill i n on t h e n e xt pag e .
You want to change parameters in form 1?
NO YES
Repeat the following procedure until you have made all the required
changes in the screen form:
Position the cursor before the parameter field. The display field
F3 at the bottom edge of the screen indicates whether you can
select between alternatives (SELECT displayed) or whether you
can change the parameter value (INPUT displayed).
You want to change parameters in form 2?
NO YES
Press F6 (CONTINUE); the 2nd screen is displayed.
Change the parameters as described above for the 1st
screen form.
Press the enter key; the PG software enters all the parameter settings
from both screen forms and generates data block DX 0.
DX0isstoredinthePG.YoucanloaditintotheCPUusingthe
programmer or you can store it on an EPROM submodule.
- Select input field:
- SELECT:
Press F3 until the required alternative is displayed.
- INPUT:
Press F3 once, the cursor jumps to the beginning
of the field. You can overwrite the field with a
permissible numerical range.
7
Exam ples of Parameter Assignment
CPU 928B Programming G uide
C79000-B8576-C898-01 7 - 17
Ex a mple of filling in t h e D X 0
screen fo rm
You w ant to ass ign pa rame te rs i n DX 0 to achi ev e th e fo ll owin g syst em
progr am r es pons e (d if fere nt fro m th e defa ults ).
- in multiprocessor operation, the CPU for which this DX 0 is
programmed does not wait until the other CPUs have completed their
rest ar t proc ed ure,
- the cy cle mo nito ring t ime is 100 ms,
- arithmetic operations are performed with 24-bit floating point
mantissa,
- if cycle errors occur, the CPU does not go to the STOP mode if OB 26
is not loaded,
- the user program is interrupted at operation boundaries by all
interrupts.
To obtain these reactions, complete the screen form as follows:
First DX 0 screen form:
- Select the "synchronize multiprocessor restart" parameter with
functi on k ey F3 as N O.
- For th e "c yc le t ime mo nito ri ng" para me ter, pre ss fun ctio n key F3 and
then type in the number 10 (= 100 ms).
- Select the "24-bit mantissa" for the "accuracy of floating point
arithm etic " para mete r with f unct ion ke y F3 .
- Press func ti on k ey F 6 (CON TI NUE) . Th e seco nd D X 0 sc reen i s th en
displayed.
Second DX 0 screen form:
- Select NO fo r th e "c yc le e rr or" para me ter with f unct ion ke y F3 .
- Enter the nu mber ’2’ i n th e "mod e" f ie ld o f th e "int erru pt abil it y of
user program by interrupts" parameter (= all interrupts at operation
boundaries).
- Confirm your entries by pressing the enter key. Data block DX 0 is
now ge nera te d by the P G so ft ware .
Finally, transfer DX 0 to memory or to an EPROM submodule.
Examples of Param eter A ssignment
CPU 928B Programming Guide
7 - 18 C79000-B8576-C898-01
Contents of Chapter 8
8.1 Structure of the Memory Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 4
8.2 Address Distribution in the CPU 928B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 5
8.2.1 Address Distribu tion of the System R AM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 6
8.2.2. Address Distributi on of t he Peripherals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 7
8 .3 U ser Memory Orga nizat ion in the C PU 92 8B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 9
8.3.1 Bl ock Hea ders in the User Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 10
8.3.2 Block Address Lists in Data Blo ck DB 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 1 1
8.3.3 RI / RJ Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 14
8.3.4 RS / RT Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 15
8.3.5 Bit Assignment of the System Dat a Words. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 18
8
Memory Assignment and
Organization
8
CPU 928B Programm ing Guide
C79000-B8576-C898-01 8 - 1
8Mem ory Assignment and
Organization
You can use this chapter as a reference section to check the
organ ization o f the CPU 928B memory. The chapter also includ es
i mportant i nformation for the user contai ned in some of the system
data wo r ds.
8
CPU 928B Programming G uide
C79000-B8576-C898-01 8 - 3
8.1 Structu re o f the Memory Area
The memory area of the CPU 92 8B is basically divided into the
following areas:
M emory area Length W idth
Use r m e mo ry: For OB s, F Bs, FXs, PB s, SBs, DBs, DXs ma x. 32x210 words 16 bits
DB-RAM: For data blocks, shift registers 23x210 words 16 bits
Flags: S 1024 byt es 8 bits
Interface data area: RI, RJ
Sys tem da ta ar e a: RS , RT
Counters: C
Timers: T
each 256 words
each 256 words
256 words
256 words
16 bits
16 bits
16 bits
16 bits
Flags: F 256 bytes 8 bits
Process input a nd
output image: PII, PIQ
eac h 128 bytes 8 bits
Peripheral I/O area,
divide d in to:
P peripherals
O peripherals
IM 3
IM 4
IPC flags
Coordinator module
Pages (CP, IP, 923C)
Dist ribute d I/Os
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
2048 bytes
768 bytes
8 bits
Refer to the memory map in the nex t section f or the exact
addres s es of the ar eas .
Note
With STEP 5, you should never access a m em ory cell within an
operand area (e.g. flags) directly usi ng the abso lute address of this
memory area, but always relat ive to the base ad dress of the
oper and area.
T he base addresses of all operan d areas are in the s ystem data
area (RS area - see "system data assignment").
Table 8-1 Structure of the memory area
St ructu re of the Memory Ar ea
CPU 928B Programming Guide
8 - 4 C79000-B8576-C898-01
8.2 A ddr ess D is tribution in the C PU 9 28B
Flags
PII/PIQ area
Peripheral I/Os
(digital/analog
CP/IP)
S5 bus
System transfer data (RI/RJ areas),
system data (RS/RT areas),
counters, timers
S flags
User memory
DB-RAM
EE00
EF00
F000
FFFF
RAM or EPROM
submodule, can be
plugged into the CPU
0
000
7
FFF
8
000
D
D7F
D
D80
E400
E
800
E7FF
DB 0 (block address lists)
E
3FF
System RAM, interna
l
to the CPU
(see also Fig. 8-2)
E
DFF
EEFF
EFFF
(see also Fig. 8-3)
B
it no.15 8 7 0
15
70
max. 32 x 2
10
words
10
words
23 x 2
Fig. 8-1 Address distribut ion in the CPU 928B - overview
8
Address Distribution in the CP U 928B
CPU 928B Programming G uide
C79000-B8576-C898-01 8 - 5
8.2.1
Address Distribution of
the System RAM
Flags
PII/PIQ area
EE00
EF00
EFFF
RJ: extended interface data area
RS: system data area
RT: extended system data area
Counters (256)
Timers (256)
E900
EA00
EB00
EC00
ED00
EDFF
E800 RI: interface data area
E400
8000
DD7F
DD80
DB-RAM
D B 0
S flags
E3FF
E7FF
E8FF
E9FF
EAFF
EBFF
ECFF
EEFF
Bit no. 15 8 7 0
15
70
Fig. 8-2 Address distributi on - system RA M
Address Distribution in the CPU 928B
CPU 928B Programming Guide
8 - 6 C79000-B8576-C898-01
8.2.2
Address Distribution of
the Peripherals
2048 bits extended peripherals
IM 3 area
IM 4 area
Digital peripherals (with process image),
1024 bits inputs / 1024 bits outputs
Digital or analog
peripherals (without process image),
1024 bits inputs / 1024 bits outputs
F000
F080
F100
F200
F300
F400
FC00
FDFF
FD00
FCFF
FF00
FFFF
Parea
Oarea
F07F
F08F
F1FF
F2FF
F3FF
FBFF
FEFF
FE00
Reserved
Distributed peripherals,
extended address volume
2048 bits IPC flags
(on coordinator module/CP)
Data transfer area
for CP (pages)
32 semaphores
(on coordinator module)
Bit no.
70
Page area
F ig. 8 -3 Ad dress di s trib ut io n - pe rip her al s (8 bits) on t he S5 bus
8
Address Distribution in the CP U 928B
CPU 928B Programming G uide
C79000-B8576-C898-01 8 - 7
Ad dr ess areas for the
peri pherals and their
programming
With STEP 5 operatio ns, you can access th e peripherals either d irectly
or via the process im age. Rem em ber that the process image only
exists fo r input and output bytes of the P per i ph erals with byte
addresses fro m 0 to 127.
Note
Us in g the interface modules IM 304, IM 307 and IM 308, you can
access distributed address areas using y our program. This allows
access to two new address areas similar to the O area. In contrast
to t h e O area , h o wev e r, ac ce ss to t hese are as is onl y poss ible
using abso lute addressing or using FB 196 of the "basi c
fun cti on s" soft w are packa ge (refe r to Catalo g ST59).
Area
(absolute ad d re ss ) Address Parameters
with
P peripherals with pr ocess image
L IB / T IB 0 to 127
L IW / T IW 0 to 126
L ID / T ID 0 to 124
A I/ AN I / O I / ON I 0.0 to 127.7
S I / R I / = I
L QB / T QB 0 t o 127
L QW / T QW 0 t o 126
L QD / T Q D 0 t o 124
A Q / AN Q / O Q / ON Q 0.0 to 127.7
S Q / R Q / = Q
When t he operation is p ro ces sed , only the
proces s image is changed . The new status o f t he
proces s image is on ly ou tput to the
peri ph era ls at the e nd of the cycle.
P perip h erals
L PY / T PY 0 t o 127
L PW / T PW 0 t o 126
T PY / T P Y 128 t o 255
T PW / T PW 128 to 254
The inputs and outputs are addressed
directly byte or w ord oriented.
Q peripherals
L OY / T O Y 0 t o 255
L OW / T OW 0 t o 254
The inputs and outputs are addressed
directly byte or w ord oriented.
PII
(process input
image)
PIQ
(process output
image)
Di gital peripherals
inputs/
outputs
Digital or analog
peripherals
inputs/outputs
EF00
EFFF
EF80
EF7F
F000
F07F
F080
F0FF
F100
F1FF
Extend ed
peripherals
inputs/outputs
Address Distribution in the CPU 928B
CPU 928B Programming Guide
8 - 8 C79000-B8576-C898-01
8.3 User Memory Organization in the CPU 928B
Depen din g on the me mor y submodule you are using, the user memory
con sists of the memory area from 0000H to 7FFFH. W h en you loa d
th e blo cks of t h e use r program, the y are st ore d in a ny ord er (add ress es
in as cending orde r ).
"Alte rnative loading" of th e
data blocks
There are alternative methods of loading DB/DX data blocks
depending on the setting in system data word RS 144:
T he de fa ult is that the data blo cks are first lo ade d in to the user
memory . Only when this has been f illed are the data blocks stored in
i nternal DB RAM (8000H to DD7FH). You can reverse this order by
setting bit 0 in RS 144 ("alternative loading").
Memory information
With the online f unction MEM CONF (m em ory configuration) you
can obtain the address (hexadeci mal) of the memor y cell containin g
the block end operation of the last block in the m em ory submodule
which then tells you the occupation of the RAM submodule.
Block management
When you correct blo cks, the "old" block is declared in valid in the
memory and a ne w blo ck is set up. This also applies when you delete
blocks; the blocks are not really deleted in the memory , but simply
dec la red inv al id. Gaps create d whe n blo ck s are dele te d are seen a s
free memory locations and used again when new blocks are loaded.
Compress memory
Usi ng t h e C OMPR ESS MEM OR Y onli ne fu nc ti on you c an c re ate
memo ry spac e for n ew blo ck s. Th is fun c ti on opti mi ze s th e memo ry
occupation by deleting blocks marked as invalid and shif ting valid
block s tog ethe r. T he sh ift ing i s se parate for the memory submodule
a nd internal RAM module (see Section 11.2.2).
8
User Memo ry Organization in the CPU 928B
CPU 928B Programming G uide
C79000-B8576-C898-01 8 - 9
8.3.1
Block Header s in the User
Memory Each block in the m em ory begins with a f ive word long header.
1st word: bl ock st art id ent ifier: 7070H
2 nd wo r d: hi gh byt e = b lock typ e
3rd word: the high by te of the 3rd word contains the identif iers for
the programmer, the low byte contains part of the
library number.
4th word: the fourth word contains the rest of the library nu mber.
5th word: the 5th word (low and high byte) contains the length of
the blo ck including the block header. This is speci fie d
in wor ds.
01H Data block DB
02H Sequence block SB
Program block PB
Function block FX
Function block FB
Data block DX
Organization block OB
04H
05H
08H
0CH
10H
00 address list in DB0
in the address list of DB0
01
The block is invalid, not entered in the
Block in the RAM is valid, and is entered
Low byte = block number
The block number (0 to 255) is in the low byte of the 2nd header word
and is coded in binary: 00 to FFH
Bit no. 15 14 13 12 11 10 9 8
User Memo ry Organization in the CPU 928B
CPU 928B Programming Guide
8 - 10 C79000-B8576-C898-01
8.3.2
Block A ddress Li sts in Data
Block DB 0 Data block DB 0 contains a list with the start addresses of all blocks
in the me mory submodule or in the DB RAM of th e CPU. The system
program generates this list after POWER UP and updates it
auto matically when you enter or ch ange blocks at the programmer.
Address list start addresses
A 256 words lon g address list is reserved in DB 0 for each block type
i. e. on e w ord i s re served for each bloc k. B lo c ks tha t a re no t lo ad e d or
have been deleted have the start address " 0" .
The start ad dre sses o f t he blo c k ad d ress li sts are al so e nt ere d in t he
sy stem data RS 32 to RS 38.
RS 32:Start address of the DX a ddress list
RS 33:Start address of the FX a ddress list
RS 34:St art add ress o f the DB ad dress li st
RS 35:St art add ress o f the SB ad dress li st
RS 36:St art add ress o f the PB ad dress li st
RS 37:St art add ress o f the FB add ress li st
RS 38:St art ad dress o f th e OB addre ss list (only 48 w o rds long )
Block sta rt addresses
The start a ddresses always refer to the first word after the block
header:
•• this is D W 0 of data b loc ks
•• t his is the first STEP 5 operatio n of a logic block
(in F B s, th is is th e "JU" o perat io n befo re t h e name an d t he
parameter list)
8
User Memo ry Organization in the CPU 928B
CPU 928B Programming G uide
C79000-B8576-C898-01 8 - 11
Stor in g block addresses in
DB 0:
n = start address of the PB address list (= contents of RS 36)
Examples of how to obtain a
block address
Address PB 0
Address PB 1
Address PB 2
Address PB 178
Address PB 179
If the value "0" is entered as
the address, the block is not loaded
DB0
n
n+1
n+2
n+178
n+179
15 0
Fig. 8-4 Block addresses in DB 0
St art ad dres s of F B 40
Soluti on a ):
:L RS 3 7 Base addr es s of t he F B ad dr ess list
:L KB 40 + FB number
:+F = Address of the memory cell con-
: taining the start address of FB 40
:LIR 1 Loa d th e star t addr ess of FB 40
in AC CU 1 .
: (If t he blo ck i s not load ed ,
: the start address = 0)
Soluti on b ):
:L RS 3 7 Base addr es s of t he F B ad dr ess list
:MAB Load the BR register with the base
address
:LRW + 40 Loa d the co nten ts o f the memo ry cel l
"base address + 40" in ACCU 1
User Memo ry Organization in the CPU 928B
CPU 928B Programming Guide
8 - 12 C79000-B8576-C898-01
De term in ing the st art addr es s an d le ng th o f da ta b lo ck D B 50
a) Using indirect memory access:
:L RS 34 Load the base address of the DB address list
:L KB 50 Calculate the address of the entry for DB 50
:+F and l oa d th e star t ad dr ess in A CC U 1
:LIR 1
:L KB 0 I f the bl ock does n ot e xist , jump to th e
:!=F NIV O labe l
:JC =NIVO
:ENT Load th e st ar t ad dres s of D B 50 i n AC CU 3 a nd
:TAK in ACCU 1
:L KF -1 Decrement the start address by 1 and
:+F loa d th e bl oc k le ngth i n AC CU 1
:LIR 1
.
.
NIVO : ...... . R eact io n if t he b lock d oes not ex ist
DB 0
0000
0000
010A
0000
15 0
0000
0000
.
.
.
.
15
0104
0105
0106
0107
0108
0109
010A
010B
010C
010D
User memory:
7070
0009
0
DW 0
DW 1
DW 2
DW 4
DB 50
header
.
DB 49
DB 50
DB 51
DB 0
DB 1
DB 2
.
.
.
.
.
RS 34
Fig. 8- 5 Example a): start address of DB 50
8
User Memo ry Organization in the CPU 928B
CPU 928B Programming G uide
C79000-B8576-C898-01 8 - 13
8.3.3
RI / RJ Area T he RI area is an area 256 words lon g in the internal s ystem RAM of
the CPU. It occ upies addresses E800H to E8FFH.
The RJ area is an area 256 words long in the internal system RAM of
the CPU. It occ upies addresses E900H to E9FFH.
You ca n us e t h e e n ti re RI area (RI 0 to R I 255) a n d th e enti re RJ area
(RJ 0 to RJ 255) for your o wn purposes.
Only a n ov e ra ll reset ca n cl ea r the R I / R J areas (z eros ent ered).
Continuation of the example (address and length of DB 50):
b) Using the special function organization block OB 181
"test data blocks (DB/DX)":
OB 181 (see Section 6.16) executes the same function as described in
example 2 / a). In addition to this function, it also determines whether
the d ata bl ock is i n the us er m emor y (RAM or EP ROM subm od ule) o r in the
DB RA M.
:L KY1, 50 Data blo ck D B 50
:JU OB 181 "Test data blocks (DB/DX)"
:JC =NIVO Jump if block does not exist
:JM =PROM Jump if in EPROM submodule
:JZ =ANWE Jump if in RAM submodule
:JP =DBRA Jump if in DB RAM
:JU = FE HL Jump t o er ror pr oces si ng
NIVO : Data block does not exist
:
:BEU
PROM : Data block is in the user memory
: (EPRO M subm od ule)
:BEU
ANWE : Data block is in the user memory
: (RAM su bmod ule)
:BEU
DBRA : Data block is in the DB RAM
:
:BEU
FEH L : Error pr oc essi ng
:
:BE
Resul t: ACCU -1-L : Star t ad dres s of D B 50
ACCU-2 -L: Leng th of DB 5 0
RLO = 1 if D B 50 doe s not ex ist
User Memo ry Organization in the CPU 928B
CPU 928B Programming Guide
8 - 14 C79000-B8576-C898-01
8.3.4
RS / R T Area The RS and RT areas con tain information for the s ystem programmer
a nd s ys tem in te r nal da ta .
The RS area is an area 256 words long in the internal system RAM of
t he CPU. It occupies the addresses EA00H to EAFFH.
Caution
Y ou can only write to system data words RS 1, RS 60 to
RS 63, RS 133 and RS 140.
- You can use RS 60 and RS 63 fo r your own purposes.
- RS 1 and RS 133 have a fixed function and i nflue nce the
processing of the program. You must only write valid
ide nti fiers to the m.
Y ou can only read th e other system data
- Writing to these sy stem data can affect the f unctional
capability of yo ur CPU an d con nected programmers.
The RT area is an area 256 words long in the internal system RAM
of the CPU. It occupies the ad dresses EB00H to EBFFH.
You ca n us e t he e n tire R T area (R T 0 t o RT 255) for yo ur own
purposes.
The R S / RT a re a can onl y be c le ared by a n ov e ra ll res et .
You can obtain the information of some of the s ystem data (the
int ern al co nf igu rati o n of t he C PU, the so ftware relea se, th e C P
id e nt ifi er etc .) u sin g t he SYSTEM PA RAME TE RS on l ine funct ion .
Foll owi ng figure s 8-6 and 8-7 you w ill find th e bit assignment o f
some system data that you can evaluate using STEP 5 operations or
wit h the PG (ref er to Secti o n 5.3. 1 for an explanati o n of t h e
abbreviations).
8
User Mem o ry Organization in the CPU 928B
CPU 928B Programming G uide
C79000-B8576-C898-01 8 - 15
Assignment of the system
data in the RS area
: reserved
Addr.
EA1D
RS
28
29
15
16
17
18
19
20
21
22
23
0
1
3
4
5
6
2
7
8
9
10
11
12
13
14
24
25
26
27
PLC software release
Name
Interrupt condition codeword (ICCW)
Interrupt condition code reset word (ICRW)
Interrupt condition code group word (ICMK)
Start-up error identifier condition code
Current ID number
End address of the user submodule
Base address of the system area
Length of the DB address list
Length of the SB address list
Length of the PB address list
Length of the FB address list
Length of the OB address list
Length of the FX address list
Length of the DX address list
Length of the address list DB (DB 0)
Base address of the output process interface modules
Base address of the process output image
Base address of the input process interface modules
Base address of the flag area
Base address of the timer area
Base address of the counter area
Base address of the interface area
Base address of the process input image
Submodule IDs
Cycle IDs Error IDs (H)
Overall reset IDs Error IDs (L)
Error IDs (F)
Slot identifier CPU identifier 2 (type)
Stop IDs Restart IDs
EA01
EA02
EA03
EA04
EA05
EA06
EA07
EA08
EA0A
EA0B
EA0C
EA0D
EA0E
EA0F
EA10
EA11
EA12
EA13
EA14
EA15
EA16
EA17
EA00
EA18
EA19
EA1A
EA1B
EA1C
EA09
Fig. 8-6 RS area memory map (part 1)
User Mem o ry Organization in the CPU 928B
CPU 928B Programming Guide
8 - 16 C79000-B8576-C898-01
EA1E
EA27
EA36
CPU identifier 1 PG interface software release
127
39
54
81
30
31
32
33
34
35
36
37
38
55
56
59
60
63
64
80
79
128
129
130
131
132
133
134
135
136
137
EA21
EA20
EA1F
EA22
EA23
EA24
EA25
EA26
EA89
EA37
EA38
EA3B
EA3C
EA3F
EA40
EA7F
EA80
EA81
EA82
EA83
EA84
EA85
EA86
EA87
EA88
EA50
EA4E
EA51
Length of the block header information
Counter for 1 hour (to 3599 sec, hex)
Reserved for handling block
Reserved for user purposes
Reserved for system program
Base address of the DX address list
Base address of the FX address list
Base address of the DB address list
Base address of the SB address list
Base address of the PB address list
Base address of the FB address list
Base address of the OB address list
"Closed loop control" ID
Condition codeword "disable all interrupts"
Condition codeword "delay all interrupts"
"Process image updating" ID
Condition codeword "disable individual time interrupts"
Condition codeword "delay individual time interrupts"
Additional error ID if bit FE-5 is set in RS 8
Reserved for system program
138
140
139 EA8B
EA8A
EA8CCondition codeword "write and delete blocks"
Alternative loading of data blocks
EA8D
EA8F
EA90
EA91
EAFF
141
143
144
145
255
Fig. 8-7 RS area memory map (part 2)
8
User Mem o ry Organization in the CPU 928B
CPU 928B Programming G uide
C79000-B8576-C898-01 8 - 17
8.3.5
Bit Assignment of the
System Data Words In terrupt condi tion co deword (system data RS 0):
RS 0
Interrupt condition code wor d
Address EA00H
H igh byt e
Bit no. Assignment
15 NAU
14 PEU
13 BAU
12 MP-STP
11 ZYK
10 QVZ
9ADF
8STP
Lo w byte
7BCF
6FE-3
5LZF
4REG
3STUEB
2STUEU
1WECK
0DOPP
The s yste m data RS 0 corresponds to the CAUSE OF INTERR. in the
ISTAC K. I f, e .g . a ru ntim e error o c curs du rin g th e prog ram ex ec u ti on ,
bit number 5 is set. Once the program processing l evel LZF has been
proc essed c omplete ly, bi t number 5 is re se t.
Table 8-2 Assignment of RS 0 (Interrupt condition c odeword)
User Mem o ry Organization in the CPU 928B
CPU 928B Programming Guide
8 - 18 C79000-B8576-C898-01
RS 1
Interrupt condition code reset wo rd ICRW
Address: EA01H
RS 1: Active interface, released for user
If you set bit number 9 or bit number 10 of the ICRW the next AD F
or QVZ is ignored and does not affect the execution of the program.
After a QVZ or ADF occurs, the s ystem program resets th e
co rrespon di n g bit.
H igh byt e
Bit no. Assignment
15
not used
14
13
12
11
10 QVZ
9ADF
8not used
Lo w byte
7
not used
6
5
4
3
2
1
0
Each program processin g level has its o wn ICRW.
Table 8-3 Assi gnment of RS 1 (Interrupt condition code reset word)
8
User Mem o ry Organization in the CPU 928B
CPU 928B Programming G uide
C79000-B8576-C898-01 8 - 19
Ex ample of UA LW
The following example tests whether a module can be addressed at a
certa in p er iphe ral ad dres s. If the mo dule doe s not exis t, ICR W prev ents
a timeout and a program written for the situation is executed. The
examp le a ls o te sts wh ethe r a pa rtic ul ar p erip he ral addr es s ha s been
entered in DB 1. If the address does not exist in DB 1, ICRW prevents an
addre ssin g erro r an d a sp ec ial prog ra m is exe cu ted.
FB 201
NAME:L
:JU FB 10
NAME: PERI TE ST Test wh ethe r a mo dule c an b e ad dr esse d at
PADR : PB 128 peripheral adddress 128
MASK : KM 00000100 00000000
:JN =M001
:.. Thi s prog ram se ctio n is p roce ssed i f th e modu le
:.. cannot be addressed
:..
M001 :
:JU FB 10
NAME: PERI TE ST Test wh ethe r a mo dule w ith peri ph eral
PADR : QB 4 address 4 is entered in DB 1
MASK : KM 00000010 00000000
:JN =M002
:.. Thi s prog ram se ctio n is p roce ssed ,
:.. if the pe riph er al a ddre ss
:.. is not en tere d
M002 :
:BE
FB 10
NAME:PERITEST
DECL :PADRI/Q/D/B/T/C: I BI/BY/W/D: BY
DEC L :MAS KI/Q/ D/ B/T/ C: D KM/KH/ KY /KS/ KF /KT/ KC/K G: KM
:L RS 1 Load an d sa ve ICR W
:T RS 60
:LW =MASK Set QVZ or ADF bit
:OW
:T RS 1 Write I CRW ba ck
:L =PADR S ingl e pe ri pher al a cc ess or acc ess to the
: process image
:L RS 1
:LW =MASK Mask QVZ or ADF bit
:AW
:L RS 60 Write old ICRW back, so that the next
:T RS 1 QVZ or ADR can be detected
:TAK
:BE
User Mem o ry Organization in the CPU 928B
CPU 928B Programming Guide
8 - 20 C79000-B8576-C898-01
RS 2
Interrupt condition code group w ord ICMK (RS 2):
Address: EA02H
Th e 16 bits o f the inte r rupt co n ditio n co de gro up wo rd correspo n d to
the possible cau ses o f e rro r list ed i n th e CA USE OF I NT ER R. i n the
ISTACK.
If one of these er ro rs o ccurs, the co rrespondin g bit is se t.
H igh byt e
Bit no. Assignment
15 NAU
14 PEU
13 BAU
12 MP-STP
11 ZYK
10 QVZ
9ADF
8STP
Lo w byte
7BCF
6FE-3
5LZF
4REG
3STUEB
2STUEU
1WECK
0DOPP
You can only read the interrupt code group word (ICMK in the
ISTACK).
Table 8-4 Assi gnment of RS 2 (Interrupt condition code group word)
8
User Mem o ry Organization in the CPU 928B
CPU 928B Programming G uide
C79000-B8576-C898-01 8 - 21
Ex ample of UA MK
If th e CP U goes to th e st op mod e as a res ult of an addr es sing e rror
(ADF), ICMK bit number 9 is set. If an operation code error (BCF) occurs
when proc es sing the A DF, bi t nu mber 7 is also s et i n th e ICMK .
Content of the ICMK (binary): 00000010 10000000
Representation (hexadecimal) in the ISTACK: 0280
While only the last error to occur is marked under CAUSE OF INTERR. in
the ISTACK, all the errors that have occurred are indicated in the ICMK
(ISTACK depth 05: in ICMK, 5 bits are set). If you convert the
hexad ecim al cod e to t he b in ary code , you can an alyz e th e cont en ts o f th e
ICMK. In this way, you can find out which error led to the stop mode.
The error bits are reset as soon as the corresponding error program
pro ce ssin g le vel ha s been com plet ely pr oc esse d an d is exi ted.
Interrupt codes of errors to which no program processing level is
assigned (e.g. NAU, PEU, STUEB, etc.) are cleared during RESTART.
User Mem o ry Organization in the CPU 928B
CPU 928B Programming Guide
8 - 22 C79000-B8576-C898-01
RS 5
S TO P and RESTART IDs
Address: EA05H
T he IDs correspond t o the contro l bits in lines 1 a nd 2 of t he I S TACK.
High byte: STO P IDs
Bit no. Assignment
15 PRI-STP
14 not used
13 FE-STP
12 BARB-END
11 PG-STP
10 STP-SCH
9STP-BEF
8MP-STP
Low b yte: RESTAR T IDs
7ANL
6not used
5NEUST
4MWA
3AWA
2not used
1NEU-ZUL
0MWA-ZUL
Table 8-5 Ass ignment of RS 5 (STOP and REST ART IDs)
8
User Mem o ry Organization in the CPU 928B
CPU 928B Programming G uide
C79000-B8576-C898-01 8 - 23
RS 6
CYCLE and Submodule/MP L IDs
Address: EA06H
T he IDs correspond t o the contro l bits in lines 3 a nd 4 of t he I S TACK.
High byte: CYCLE IDs
Bit no. Assignment
15 RUN
14 not used
13 EIN-PROZ
12 BARB
11 OB1-GEL
10 FB0-GEL
9OB-PROZA
8OB-WECKA
Low byte: Submodule/MPL IDs
732KW-RAM
616KW-RAM
58KW-RAM
4EPROM
3KM-AUS
2KM-EIN
1DIG-EIN
0DIG-AUS
Tab le 8-6 A s signment of RS 6 (Cycle and submodule/MP L ID s)
User Mem o ry Organization in the CPU 928B
CPU 928B Programming Guide
8 - 24 C79000-B8576-C898-01
RS 7
R ESE T IDs/Initialize erro r ID s
Address: EA07H
T he IDs correspond t o the contro l bits in lines 5 a nd 6 of t he I S TACK.
H igh byte: RES ET ID s
Bit no. Assignment
15 URGELOE
14 URL-IA
13 STP-VER
12 ANL-ABB
11 UA-PG
10 UA-SYS
9UA-PRFE
8UA-SCH
L ow byte: Initialize error ID s
7DX0-FE
6not used
5MOD-FE
4RAM-FE
3DB0-FE
2DB1-FE
1DB2-FE
0KOR-FE
Table 8-7 Assi gnment of RS 7 (RESET IDs/I nitialize error IDs)
8
User Mem o ry Organization in the CPU 928B
CPU 928B Programming G uide
C79000-B8576-C898-01 8 - 25
RS 8
E r ror I Ds H W/SW
Address: EA08H
Th e IDS co rrespo n d to the cont rol bit s in li ne s 7 a n d 8 of th e IST ACK.
Bit no. H igh b yt e: E rror IDs HW
15 NAU
14 PEU
13 BAU
12 STUE-FE
11 ZYK
10 QVZ
9ADF
8WECK-FE
Bit no. L ow byt e: E rror IDs SW
7BCF
6not used
5FE-5
4Powe r-d o wn error
3FE-3
2LZF
1REG-FE
0DOPP-FE
Table 8-8 Ass ignment of RS 8 (Error IDs HW/SW)
User Mem o ry Organization in the CPU 928B
CPU 928B Programming Guide
8 - 26 C79000-B8576-C898-01
RS 29
Slot ID/CPU/PLC type
Address: EA1DH
Bit no. H igh b yt e: E rror IDs HW
15
not used
14
13
12
11 CPU no. 4
10 CPU no. 3
9CPU no. 2
8CPU no. 1
Bit no. L ow byt e: E rror IDs SW
7
CPU type
6
5
4
3
PLC type
2
1
0
R S 29 (HIGH) :
Active interf ace, used by the handling blocks and in multiprocessor
c ommunicati on as we ll as by OB 218 and th e SED and SEE
operations.
RS 29 (LOW):
P LC type: 0 1 1 1 S5-135U
CPU type: 1 0 1 1 CPU 928B
Table 8-9 Assignment of RS 29 (S lot ID/CPU/PLC t ype)
8
User Mem o ry Organization in the CPU 928B
CPU 928B Programming G uide
C79000-B8576-C898-01 8 - 27
RS 80
Address: EA50H (high and low) :
This contains additional inf ormation to def ine the cause of the error
when bit 5 is set in RS 8 by the sy stem or when control bit FE 5 is
m a r ked in the IS TA CK outp u t .
Identifier in RS 80 Cause of error
2460H R eady signal c on tinuously a ctiv e on the S 5
bus
RS 130
Address EA82 (low) :
T he s ystem da ta RS 130 indi cates the foll owing stat uses of the
program processing level "closed loop control".
Bit no. 0 = 0 : program processing level "closed loop control"
activated
Bit no. 0 = 1 : program processing level "closed loop control"
suppressed
Before yo u ca ll a rest art org an i za tion bl oc k (OB 20, 21 o r 22) th e
system progra m evaluates data block DB 2 (if it exists). Depending on
the resul t o f t he e va lua ti on, RS 130 i s se t or re set by th e syst em
prog ram. F oll o win g th i s, th e s ys te m program cal ls a restart OB.
If RS 130 (LOW ) is reset, the closed loop controller is processed in
cyclic operatio n according to the controller list in DB 2.
User Mem o ry Organization in the CPU 928B
CPU 928B Programming Guide
8 - 28 C79000-B8576-C898-01
RS 131
C ondition codewo rd "disable all interrupts": see OB 12 0
(Section 6.5)
Address EA83 (low)
T he s ystem da ta RS 131 indi cates the foll owing stat uses of the
progra m processing levels "interrupt processing".
Bit no. L ow by te : Disable all interrupts
70
60
50
40
3Delay interrupt
2Pro ce ss inte r rupts
1Cl ock -driv en time int errupt
0Time interrupts at fixed intervals
Bit = 1 means: int errupt(s) is (a re) d isabled.
RS 132
C ondition codeword "delay all interrupts": see OB 1 22
(Section 6.7)
T he s ystem da ta RS 132 indi cates the foll owing stat uses of the
progra m processing levels "interrupt processing".
Bit no. Lo w byte : Dela y all interrupts
70
60
50
40
3Delay interrupt
2Pro ce ss inte r rupts
1Cl ock -driv en time int errupt
0Time interrupts at fixed intervals
Bit = 1 means: in terrupt(s ) is (are) d elaye d
Table 8-10 Assignment of RS 131 (Disable all interrupts)
Ta ble 8-11 Assignment of RS 132 (Delay all interrupts)
8
User Mem o ry Organization in the CPU 928B
CPU 928B Programming G uide
C79000-B8576-C898-01 8 - 29
RS 133
Process im age updatin g
Address EA85 (low)
Bit no. Low byte: P rocess image updating
7
not used
6
5
4
3KM-AUS
2KM-EIN
1DIGH-EIN
0DIGH-AUS
Bit no. 0 = 0 : next process image of the digital outputs will be
output
Bit no. 0 = 1 : next process image update of the digital outputs
will be suppressed
Bit no. 1 = 0 : next process image of the digital inputs will be
read in
Bit no. 1 = 1 : next process image update of the digital inputs
will be suppressed
Bit no. 2 = 0 : next process image of the IPC f lag inputs will be
read in
Bit no. 2 = 1 : next process image update of the IPC f lag inputs
will be suppressed
Bit no. 3 = 0 : next process image of the IPC f lag outputs will
be output
Bit no. 3 = 1 : next process image update of the IPC f lag
outputs will be suppressed
Note
If a bit is set, it prevents the process image update once, followi ng
this it is immediately r eset to " 0" by the system program.
Table 8-12 Assignment of R S 133 (Process image upda ting)
User Mem o ry Organization in the CPU 928B
CPU 928B Programming Guide
8 - 30 C79000-B8576-C898-01
RS 135
C ondition codewor d "disable individu al time inter ru pts": see
OB 121 (Section 6.6)
Address EA87
T he s ystem da ta RS 135 indi cates the foll owing stat uses of the
progra m processing levels "ti me-drive n interrupt processing".
Bit no. H igh byte: Disable individual time interrupts
15 0
14 0
13 0
12 0
11 Time interrupt 5 sec (OB 18)
10 Time interrupt 2 sec (OB 17)
9Time interrupt 1 sec (OB 16)
8Time interru pt 500 ms (OB 15)
Bit no. L ow byt e: Disable individ u al time interru pts
7Time interru pt 200 ms (OB 14)
6Time interru pt 100 ms (OB 13)
5Time interru pt 50 ms (OB 12)
4Time interru pt 20 ms (OB 11)
3Time interru pt 10 ms (OB 10)
20
10
00
Bit = 1 mea ns: this ti me interrupt is disabled.
Tab le 8-13 A ssignment of RS 1 35 (Disa ble indi v i du al time interr upts)
8
User Mem o ry Organization in the CPU 928B
CPU 928B Programming G uide
C79000-B8576-C898-01 8 - 31
RS 137
C ondition codewo rd "delay individu al time inter rup ts" :
see OB 123 (Section 6.8.)
Address EA89
T he s ystem da ta RS 137 indi cates the foll owing stat uses of the
program proces sing levels "time interrupt process ing":
Bit no. H igh byte: Delay individual tim e interrupts
15 0
14 0
13 0
12 0
11 Time interrupt 5 sec (OB 18)
10 Time interrupt 2 sec (OB 17)
9Time interrupt 1 sec (OB 16)
8Time interru pt 500 ms (OB 15)
Bit no. L ow byt e: De lay individu al time interrup ts
7Time interru pt 200 ms (OB 14)
6Time interru pt 100 ms (OB 13)
5Time interru pt 50 ms (OB 12)
4Time interru pt 20 ms (OB 11)
3Time interru pt 10 ms (OB 10)
20
10
00
Bit = 1 means: this tim e interrupt is delayed.
Tab le 8-14 A ssignment of RS 1 37 (Dela y indi vidu al time interr upts)
User Mem o ry Organization in the CPU 928B
CPU 928B Programming Guide
8 - 32 C79000-B8576-C898-01
RS 140
C ondition codewo rd "write and read block s"
Address EA8C
Sy stem data RS 140 indicates whether blocks have been overwritten,
newly loaded or deleted since the last OVERALL RESET of the CPU
or since the last tim e sy stem data RS 140 was cleared. The bits f or
cha ng e s a nd bloc k type are al lo ca te d to e ac h blo ck . Bef ore a ne w
monitoring section, system data RS 140 must be cleared. RS 140 is
also cleared during an overall reset.
Bit no. High b yt e: W rite/read IDs
15 Bl ock dele ted
14 Blo ck ne wly l oaded
13 Bl ock over wr i t ten
12
not used
11
10
9
8
Bit no. L ow byte: Write/r ead ID s
7not used
6DX
5DB
4FX
3FB
2SP
1PB
0OB
Table 8-15 Ass ignment of RS 140 (Write/read IDs)
8
User Mem o ry Organization in the CPU 928B
CPU 928B Programming G uide
C79000-B8576-C898-01 8 - 33
RS 144
"Alternative loading of da ta blocks into DB RA M"
Address EA90
In th e CPU 928B , a ll block s are first lo ade d by t he programmer int o
the user memory submodule as standard. Only when there is no more
memory space there, are the data blocks (DBs, DXs) and only the
data block s load ed into DB RA M.
You can influence the order of loading data blocks via bit no. 0 of
sys tem da ta wo r d RS 14 4:
Bit 0 = 0: Default " Standard behavior" :
Th e d a ta blo ck s are lo ade d into t he u ser m e mo ry
sub module first. Only when there is no more
space th ere, are they loa ded int o DB RAM.
Bit 0 = 1: Th e da ta block s are load e d in to DB RAM fi rst.
Only wh en there is no more space there, are they
lo aded into th e user m e m o ry sub mo dule.
The rem aining bits of RS 144 are not assigned.
Note
Code block s are lo ade d into t h e use r memo ry regardless of t he
setting in RS 144.
T he setting in RS 144 has no influence on operati ons and special
function OBs for generating and reloading blocks.
User Mem o ry Organization in the CPU 928B
CPU 928B Programming Guide
8 - 34 C79000-B8576-C898-01
Contents of Chapter 9
9 .1 Intr oduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 4
9.2 Access using the Address in ACCU 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 8
9.2.1 LIR/TIR: L oa din g to or Tran sfe rri ng from a 1 6-Bit Memory Area I ndi rectly . . . . . . . . 9 - 9
Registers 0 to 3 and 9 to 12: ACCU 1, 2, 3 an d 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 11
Re gi st er 6: Dat a Bl oc k Start Ad dress (DBA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 11
Re gis ter 8 : DBL = Data Block Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 14
Reg ister 15: SAC = Step Address C ounter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 15
9.2.2 Examples of using the Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 16
9.3 Transferring Fields of Memo ry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 18
9.3.1 Example of Transferring Memory Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 21
9.4 Operations with the Base Ad dress Re gister (BR Register) . . . . . . . . . . . . . . . . . . . . . . 9 - 26
9.4.1 Operati ons for T ra ns fer bet wee n Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 27
9.4.2 Accessing th e Local Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 28
9.4.3 Accessing th e Global Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 29
Testing and setti ng a bus y location in the gl obal area. . . . . . . . . . . . . . . . . . . . . . . . . 9 - 29
Loa d an d trans fer operatio ns for th e global memory organized in bytes. . . . . . . . . . 9 - 31
Loa d an d trans fer operatio ns for th e global memory organized in words . . . . . . . . . 9 - 32
9.4.4 Accessing th e Page Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 33
Opening a page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 34
Testing and setting a busy locatio n in the page area . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 34
Loa d an d trans fer operatio ns for th e pages organized in bytes. . . . . . . . . . . . . . . . . . 9 - 35
Loa d an d trans fer operatio ns for pages organized in words . . . . . . . . . . . . . . . . . . . . 9 - 37
9
Memory Access using
Absolute Addresses
9
CPU 928B Programm ing Guide
C79000-B8576-C898-01 9 - 1
9Mem ory Access using
Absolute Addresses
This chapter explains how to use STEP 5 operations and special
STEP 5 registers to a ddress data in certain memory areas using
abso l ut e add re sses.
9
CPU 928B Programming G uide
C79000-B8576-C898-01 9 - 3
9.1 Introduction
T he STEP 5 programming lan guage contains operations with whi ch
you can access the en tire memory area. T hese operatio ns belong to the
" sys tem op e r a tions".
Caution
If the operations described in this secti on are not used properly,
STEP 5 blocks and system data can be overwritten. This can
resu l t i n u nde sirabl e opera ti ng sta tuse s. Onl y experien ce d syst em
programmers should use operations that work with absolute
addresses.
Local memory
Loc al memo ry is th e m e mo ry are a av ai la bl e in e ac h CPU (user
su bmo d ule, DB-R AM, RI , RJ, R S, RT area, co u nt ers, time rs, fl ag s,
proce ss image).
Gl ob al me mor y
Gl obal memo r y only exists once for all CPUs and is a ddressed via the
S5 bus.
Memory organization
M emory areas ar e organized in bytes or words as fol lo w s:
•• bytes: each address addresses a b yte
•• words: each address addresses a 16-bit word
(= 2 bytes)
Introduction
CPU 928B Programming Guide
9 - 4 C79000-B8576-C898-01
0
15
Pages
7
1024 bytes/words
2048 bytes/words
0000H
F000H
F400H
FBFF FC00H
FFFFH
FEFFH
Select register
The global memory
is an external memory
shared by all CPUs in
a PLC via the S5 bus
The local memory
is internal and exists
in each CPU
7
15 0
0
000H
E
DFFH
E
E00H
E
FFFH
0
715 0
255
2
1
0
F ig. 9 -1 G lob a l and lo c a l memo ry
9
Introduction
CPU 928B Programming G uide
C79000-B8576-C898-01 9 - 5
Memory access
With the f ollowing operations, you can access local or global m em ory
are as us in g absol ut e ad d re sse s (see al so Fig . 9-2).
Access to the local and
global area
You can acccess both the local and global areas:
•• l oca l area (0000 to EFFF) and t he part of the globa l memo ry or-
ga n ized i n bytes (F000 to F3F F, FC00 t o FFFF):
TNB, TNW, LIR, TIR
•• t he part o f the local area organized in words (0000 to E3FF an d
E800 to EDFF):
LRW, TRW, LRD, TRD
Access only to the global area
You can ac ce ss th e fo ll owin g parts o f th e gl o bal area :
•• t he part of the global area organ ized in bytes (0000 to EFFF):
LY GB, LY GW, LY GD, TY GB, TY GW, TY GD, TSG
•• t he part o f the global area organ ized in words (0000 to E FFF):
LW GW, L W GD, TW GW, TW GD, TSG
Access to the page area
You can ac ce ss th e fo ll owin g part of the pa ge a rea:
•• t he part o f the global area organiz ed in b ytes (F400 t o FBFF,
= dual-port R AM area):
LY CB, LY CW, LY CD, TY CB, TY CW, TY CD, TSC
•• t he part o f the global area organized in words (F400 to FBFF,
= dual-port R AM area):
LW CW, LW CD, TW CW, TW CD, TSC
Introduction
CPU 928B Programming Guide
9 - 6 C79000-B8576-C898-01
no access possible
a) LIR, TIR, TNB, TNW b) LRW, TRW, LRD, TRD
access possible
c) LY GB, LY GW, LY GD
TY GB, TY GW, TY GD, (TSG) d) LW GW, LW GD
TW GW, TW GD, (TSG)
e) LY CB, LY CW, LY CD
TY CB, TY CW, TY CD, (TSC) f) LW CW, LW CD,
TW CW, TW CD, (TSC)
Fig. 9-2 Access to l ocal or global memory areas using absolute addresses (see also F ig. 9- 1)
9
Introduction
CPU 928B Programming G uide
C79000-B8576-C898-01 9 - 7
9.2 Access using the Address in ACCU 1
Application
Reg is te rs are me mory ce ll s u sed by th e CPU to e xe cute a STEP 5
program. Ev ery register is 16 bits wide. Using the system operations
LI R (l oa d a register indir ectly) and TI R ( t ra nsfer a regis ter indirec tly)
you can access the co ntents of the registers.
Operations
Operation Operand Function
LIR Register
no.
0 to 15
Lo ad t he sp ecified register with th e
content of a m em ory word addressed by
ACCU 1 (20-bit address).
TIR Register
no.
0 to 15
Load the c on tent of the sp ecified register
i n th e mem o ry word add re ssed by
ACCU 1 (20-bit address).
The me mo ry w ord i s e it h er in the loca l area (0000 t o EF FF) or in t h e
t he part of the global area organized in b ytes (F000 to F3FF, FC00 to
FFFF).
The foll owing p ages explain which registers y ou can us e with th e
operations.
Examples explain how to use the operations.
Table 9-1 Operati ons for i ndirect memory access using registers
Access u sing the Address in ACCU 1
CPU 928B Programming Guide
9 - 8 C79000-B8576-C898-01
9.2.1
LIR/TIR: Loading to or
Trans ferring from a 16-Bit
Memory Area Indirectly
Th e fol lowi ng t abl e s ho ws whi ch re gist er n umbers you c an u se w ith
t he CPU 928B for the LIR and TI R operations a nd ho w t hese are
assigned.
Register no. Register assignment (each 16 bits wide )
0ACCU-1-H (left word of ACCU1, bits 16 to 31)1)
1ACCU-1-L (right word of ACCU1, bits 0 to 15)1)
2ACCU-2-H
3ACCU-2-L
5Block stack poi nter (offset)
6DBA (d a ta b lock star t address re gi ster)
8DBL (data block length register)
9ACCU-3-H
10 ACCU-3-L
11 ACCU-4-H
12 ACCU-4-L
1) Loading the contents of an addressed memory register into regi ster
’0’or ’1 ove rwr ite s t he ad dre ss s tor ed in ACCU 1.
Registers 4, 7, 13, 14 an d 15 do not exist on the CPU 928B. LI R/TIR
operati ons with these register n umbers are treated as no operations
(NOP).
LIR and TIR wi th the page
area
The LIR and TIR operations are not suit able fo r acce ssing th e pa ge
area (ad dresses F400 to FBFF) in the S5-135U multiprocessor P LC.
Use instead the operations fro m Section 9.4.4 "Accessing th e Pag e
Me mory" or th e special fu nctio ns from Section 6.21 "Page Accesses ".
LI R/TIR: with 8-bit
memo ry areas
If you use the L IR and TIR operations to access mem ory areas that are
only 8 bits wide i.e ., for m e mory add resses from E400 to E7 FF and
≥ EE00 remember th at
•• t he TIR operati on trans fers only the low byte of the register. The
high byte of the register is lost.
and
•• th e LIR o perat io n ov erw rites th e hi g h byte o f t he regi ste rs wi th
FFH.
Table 9-2 16-bit register for LIR/TIR
9
Access using the Address in ACCU 1
CPU 928B Programming G uide
C79000-B8576-C898-01 9 - 9
Fi gures 9-3 and 9-4 illustrate the difference between LIR/TIR access
t o word and byte-oriented areas:
15 0 15 0
15 0
ACCU 1
ACCU 1
Register n
Register n
addressed
memory cell
addressed
memory cell
15 0
LIR n
TIR n
15 0
Fig. 9-3 LIR/TIR with 16- bi t memory areas (word-oriented)
15 0 15 0
15 0
ACCU 1
ACCU 1
Register
n
Register
n
addressed
memory cell
addressed
memory cell
15 0
LIR n
FF
xx
TIR n
70
Fig. 9-4 LIR/TIR with a- bit memory areas (byte-oriented)
Access u sing the Address in ACCU 1
CPU 928B Programming Guide
9 - 10 C79000-B8576-C898-01
Reg isters 0 to 3 and 9 to 12:
ACCU 1, 2, 3 and 4
Duri n g prog ra m ex ec u ti on, th e CPU uses th e ac cumu l at ors as buffers.
Using the TIR operation, you can transf er the contents of the
accumu lators into memor y cells with abso lute addresses. With the
LIR o peratio n, you can loa d th e co n tent s of memory cells with
absolu te addresses int o the accumulat ors. The absol ute ad dress of the
m e mory c ell is alway s in AC C U - 1-L.
Examples
Reg ister 6: Data Bl ock Star t
Address (DBA)
When you open a data block with the operations C DB and CX DX,
th e add ress of DW 0 o f thi s d ata block i s l oad ed i n register 6. Th e
block address list in DB 0 contains t his address.
The DBA register is set to "0" before each OB 1 or FB 0 call.
The DBA register rem ains the same if the following occurs:
•• a ju mp opera tion (JU/JC ) ca u ses program ex ecu tio n to c ont inu e in
a dif ferent b lock
or
•• a different program processing level is inserted.
You want to load the contents of the memory cell with the address A000
into flag word FW 100.
:L KH A000 load address A000 of the memory cell into ACCU 1
:LIR 1 load the contents of the memory cell in ACCU 1 into
: register 1 = load ACCU 1
:T FW 1 00 stor e the co nten ts o f addr ess A0 00 i n flag wor d FW 1 00
:BE
You want to transfer the contents of flag word 200 to the memory cell
wit h th e addr es s A000 .
:L FW 200 load flag word FW 200 into ACCU 1
:L KH A000 load address A000, the destination address,
: in ACC U 1 (f lag wo rd F W 20 0 to A CC U 2)
:TIR 3 transfer contents of register 3 = ACCU 2 into
: th e me mo ry c ell ad dres sed by ACC U 1
:BE
9
Access using the Address in ACCU 1
CPU 928B Programming G uide
C79000-B8576-C898-01 9 - 11
It changes if one of the foll ow i ng occur s :
•• another data block is opened
or
•• the program returns to a higher level block after a new data block
was ope ned in t he i n sert ed blo c k (s ee also Se ctio n 2.4.2, Ran g e of
Validity of Data Blocks).
Note
In th e IST ACK, t he a dd ress e ntered in t he DB A regi ste r appea rs
under the heading "DB-ADD" .
You no rm a lly ac ce ss data words w ith th e STE P 5 o peration s L/T DW,
L/T DR, L/ T DL, L/ T DD, A /O/ AN/ON/=/S/R Dx .y. You can o nly
use th es e operati on s up t o dat a w o rd DW 255. Howeve r, by
manipulating the DBA register, you can use them to access data
words > 255. This is also possible with special fu nction OB 180 (see
Sec tion 6. 15 ).
Examples
Example 1: Ef fe ct o f th e "CX DX 1 7" opera ti on o n th e DBA re gist er:
When DX 17 is called, the address of the memory word in which DW 0 is
sto re d is ent er ed in th e DBA re gi ster . In thi s ex ampl e, the DBA is
4152H.
Note: In the ISTACK, the address entered in the DBA regis ter appears
under t he h eading ’ DB-A DD’.
5 words
block header
KH = 0000
KH = 0001
1516H
1517H
1518H
1519H
151AH
151BH
151CH
151DH
DW 0
DW 1
DW 2
DBA
Addresses DX 17
.
.
.
F i g . 9 -5 Using th e DB A regi s ter
Access u sing the Address in ACCU 1
CPU 928B Programming Guide
9 - 12 C79000-B8576-C898-01
Note
If you m anipulate the DBA register as shown in example 1, the
DBL reg ister is not changed. T hi s mean s that tra nsfe r er r o r
mon it o ri n g ca n no l o ng e r be g u aran t eed.
By us in g the special fun ctio n OB 18 0 "va riable da ta blo ck
acc ess" y o u can al so shift the DBA r egis ter by a sele cted numbe r
of data w ords. Si nc e OB 180 a lso c h an g es the DBL regi ster at t he
s ame time , transfe r error monitoring re ma ins i n ef fect.
Example 2: By c hang ing re gist er 6, you ca n lo ad d at a wo rd D W 300 of
data bloc k DB 1 00.
FB 7
NAME : LIR/TIR6
:L RS 34 star t ad dres s of t he D B addr es s li st p lu s 10 0
:ADD BN+1 00 prod uc es t he a dd ress l ist entr y of D B 10 0
:LIR 1 st ar t ad dres s of D B 100 (DW 0) to ACCU 1
:ADD KF+2 00 st or e ad dres s of D W 20 0 in D B 100 in s ys tem data
:T RS 62 word R S 62
:L RS 20 load bas e ad dr ess of s ys tem da ta
:ADD KF+62 load address of RS 62 in ACCU 1
:LIR 6 load DBA register with the contents of the address
: of RS 62 , i. e. , th e da ta blo ck s ta rt i s se t to
DW 200
:L DW 100 load DW (200 + 100) = DW 300
:T FW 100 store DW 300 in flag word FW 100
:BE
Ex ample 3: Cha ng ing the DB A an d DBL regi st ers.
FB7
NAME :OB180
:C DB 100 DBA and DBL registers are loaded with the values
:L KF 200 of DB 100 and with the help of OB 180 the
:JU O B 18 0 DBA reg iste r is i ncre as ed b y 200 and th e DB L
: r egis ter re du ced by 200
:JC = ERRO err or o ut put, in ca se D B 10 0 cont ai ns
: less th an o r eq ua l to 200 d ata wo rds
:L DW 100 load DW 3 00 and
:T FW 100 sto re i n FW 1 00
:BEU
ERRO : program section for error handling
:
:BE
9
Access using the Address in ACCU 1
CPU 928B Programming G uide
C79000-B8576-C898-01 9 - 13
Register 8: DBL = Data
Block Len gth
In addition to the DBA register, a DBL register is loaded eve ry time a
data block is called. This contains the length (in words) of the data
b loc k call ed , without the block hea der. The DBL register is set to "0"
bef ore each OB 1 or FB 0 call.
T he DBL register remains th e s ame if the f ollowing occurs:
•• a ju mp opera tion (JU/JC ) ca u ses program ex ecu tio n to c ont inu e in
a dif ferent b lock
or
•• a different program processing level is inserted.
It changes if one of the foll ow i ng occur s :
•• another data block is opened
or
•• the program returns to a higher level block after a new data block
was ope ned in t he i nserted bloc k (s ee al so Se ction 2.4.2).
Access u sing the Address in ACCU 1
CPU 928B Programming Guide
9 - 14 C79000-B8576-C898-01
Example
Reg ister 15: S AC = Step
Address Counter
During STEP 5 program execution, register 15 contains the absolute
ad d ress o f th e opera tio n in t he program mem ory t o be proc es sed next .
Effect of the "CX DX 17" operation on the DBL:
When DX 17 is called, the number of existing data words is entered in
the DBL register. In this example the DBL is 8 (D W 0 to DW 7)
Note: In the ISTA CK, the numb er enter ed i n the DB L regist er a ppears u nder
the hea ding "DBL-RE G".
5 words
block header
eeee
ffff
gggg
aaaa
bbbb
cccc
dddd
hhhh
1516H
1517H
1518H
1519H
151AH
151BH
151CH
151DH
151EH
151FH
1520H
1521H
1522H
DW 0
DW 1
DW 2
DW 3
DW 4
DW 5
DW 6
DW 7
D
BA
DBL
Addresses DX17
Fi g . 9- 6 Using th e DBL re g ister
9
Access using the Address in ACCU 1
CPU 928B Programming G uide
C79000-B8576-C898-01 9 - 15
9.2.2
Exam p les of usin g th e
Registers
Ex ample 1: You w ant all th e da ta wor ds o f a da ta b lo ck t o co nt ain a
cons ta nt.
The pr ogra m show n be lo w wr it es t he c on stan t KH =A 5A5 to a ll dat a word s in
DB 50. After changing the STEP 5 operations shown in bold face, it can
also b e us ed to writ e any va lues req ui red to d if fere nt d at a bl oc ks ( DB
or DX) . No n- exis tent d ata bl ocks or da ta b lock s with no da ta w or ds a re
detected and cause a jump to the NIVO label.
The st art ad dres s (D BA ) an d leng th ( DB L) o f th e data blo ck are
determ ined b y th e sp ec ial fu ncti on O B 181 "tes t data blo ck (DB /D X)".
The program uses all four accumulators. In the figure, you can see the
occupa tion o f th e ac cu mula to rs d urin g the prog ra m as far a s th e LOOP
label. Wit hi n th e lo op , th e accu mula to r oc cupa ti on d oes no t ch an ge.
ACCU 1 initially contains the address of the last data word
(DBA + DBL - 1) and is red uc ed b y 1 ea ch t ime th e lo op i s run th roug h.
ACCU 2 contains the address of the first data word (DBA). The loop is
abando ned as soo n as t he c on tent s of A CCU 1 ar e less tha n the co nten ts
of ACCU 2.
The op er atio n TI R 10 tha t stor es the con tent s of ACC U- 3-L (t he con st ant)
under the ad dres s lo ca ted in ACC U-1- L is u sed to wri te t o the da ta
words.
:
:L KHA5A5 c onst an t to be wr it ten to
: all data words
:L KY 1, 50 type an d nu mber o f th e da ta blo ck
:ENT
:JU O B 18 1 spe cial fun ct ion OB " te st d at a bl ocks "
:JC =NIVO abandon if DB 50 does not exist
:TAK
:ENT
:+F
: ACCU 1 := a ddre ss o f last d ata word + 1
: ACCU 2 := a ddre ss o f the fi rst data w ord
: ACC U 3 := c onst ant
:!=F aband on if DB 50 cont ai ns
:JC = NIVO no data wor ds
:
LOOP :ADD BN-1 the constant contained in ACCU-3-L
:TIR 10 is writ ten to all dat a word s begi nnin g
: wit h the last d ata wo rd
:><F scan: 1st data word reached?
:JC =LOOP return to loop if 1st data word not reached
:
: conti nuat io n of the p rogr am ...
Continued on next page
Access u sing the Address in ACCU 1
CPU 928B Programming Guide
9 - 16 C79000-B8576-C898-01
Example 1 continued:
CONT : . ...a fter a ll d ata wo rds ha ve b een
: written to
:BEU
NIVO : . .. .if DB 50 does n ot e xi st
: or has no data words
:BE
Note: The section of program from the label LOOP can be used to write a
constant to any memory areas (e.g. flags, timers, counters).
TYPE/NO
constant
constant
TYPE/NO
ACCU 4
ACCU 3
ACCU 2
ACCU 1 constant
constant
ACCU 4
ACCU 3
ACCU 2
ACCU 1
L KHA5A5 L KY1.50 ENT JU OB181
JC =NIVO
TAK ENT +F
1
2
constant
constant
constant
DBL
DBL
DBL
DBA
DBA
DBA
DBA
constant
constant
DBA +.DBL
DBA
1
2
Sequence of events
Fig. 9-7 Occupati on of the accumulators during the program
Ex ample 2: Clearing all flag bytes (FY 0 to FY 255)
:L KB 0 c on stan t to b e wr it ten to
: all f lag byte s
:L RS 14 b as e ad dres s of t he f la g ar ea ( = addr es s
: of th e fi rst fl ag b yt e FY 0)
:ENT
:L KF + 256 + length of the flag area
:ENT = (address of the last flag byte FY 255) + 1
:+F
:
LOOP :ADD BN -1 write the constant contained in ACCU-3-L
:TIR 10 to all 256 fl ag b ytes , begi nn ing with
: fla g byte FY 25 5
:JC =L OO P
:
:
:
9
Access using the Address in ACCU 1
CPU 928B Programming G uide
C79000-B8576-C898-01 9 - 17
9.3 Trans f errin g Fie lds of Memor y
Application
You ca n use t he s ys te m operati ons TNB a nd T NW t o tra ns fer fie lds o f
memory (max. 255 b ytes wit h TNB, max. 255 words with TN W).
With the TNB and TNW operations you can access both the local
memory area and the part of the global m em ory area organized in
b ytes (F000 to F3FF, FC00 to FFFF).
Operations
Operation Operand Function
TNW 0 to 255 Field transfer 0 to 255 bytes
TXB -- Field transf er o to 255 words
Parameters
Field length
Operand = number of bytes (TNB) or n umber of words (TN W)
End address of the s our ce a re a
ACCU-2-L = End address of the source area
End address of the destination area
ACCU-1-L = End address of the destination area
The en t ire so urc e a n d de stin at ion a re as mu st be lo ca te d in one of t h e
memory areas listed in Table 9-4 and cann ot ov erlap.
Permissible memo r y areas
Addresses M em ory area
0000H to 1 FFFH
0000H to 3FFFH
0000H to 7FFFH
User me mo ry:
User s ubmodule (16 bits) 8 Kwords
User s ubmodule (16 bit) 16 Kwords
User s ubmodule (16 bit) 32 Kwords
T able 9-3 Ope ra tio ns f or field tran s fer
Ta ble 9- 4 Me mor y are as p e rmitt e d fo r TNW , TXB a nd TXW
T r a nsferring Fields of M emor y
CPU 928B Programming Guide
9 - 18 C79000-B8576-C898-01
Addresses M em ory area
T able 9-4 cont inued:
8000H to DD7FH
DD80H to E3FFH
E4 00H to E7 FFH
E8 00 H to ED FF H
EE00H to EFFFH
F0000H to F FFFH
System RA M :
DB-RAM (16 bits)
D B 0 (16 bits)
S flags (8 bits)
System da ta (1 6 bits: B A , BB , BS, B T,
tim ers and cou nte rs )
RA M (8 bits: fl ags , proce s s image )
I/Os (8 bi ts)/S5 bus
Sequence
T he field trans fer is made in descen din g order, i.e. it begins with th e
highest ad dress of the source area (= end address) and ends wit h the
lowest.
Use in the page area
The TNB and TNW operations are not suit able fo r acce ssing th e pa ge
area (ad dresses F400 to FBFF) in the S5-135U multiprocessor P LC.
Use instead the operations fro m Section 9.4.4 "Accessing th e Pag e
Me mory" or th e special fu nctio ns from Section 6.2.1 "Page Accesses ".
Special features
Pseudo operation boundaries
with TNB and T N W
The TNB and TNW operations are long-running STEP 5 operations
t hat contain so-called "pseudo operati on boundaries ". This means that
the data is transf erred in sub-fields of various sizes depending on the
source and desti natio n area. If an error (e.g. cycle error) or an
in t errupt (e.g . caus ed by a time o r pro ce ss-driv en i nte rru pt) o cc urs
during the trans fer of a sub-field, the appropriate organizati on block is
inserted at th e en d of th i s sub-f i eld . T hi s is, ho we ve r, o n ly possible if
DX 0 is programmed to al low interrupti ons at operation boun daries.
If one or mo re timeouts and /or addr ess ing errors occur dur ing the
transfer, all the sub-fields are transferred first and then before the next
operation is executed, the appropriate erro r or ganiza tion bloc k is
cal led on ce ( if Q VZ and ADF occ ur s imultaneously, on ly th e
QVZ -OB is c alle d). Th e error a d dre ss s pe ci fie d is always the address
at which a n er ror oc cu r red first. Since TNB a nd TN W operate with
dec reme nti ng a d dre sse s, whe n th ere is mo re than o n e error, th is is
alw ays the highest error ad dress in the are a in w h ich an erro r first
occ urred. OB 2, OB 10 to 18 o r an e rro r o rg a niza ti o n block c an be
inserted at th e pseud o operation bou n d aries.
9
Tra nsfe rring Fields of Mem o ry
CPU 928B Programming G uide
C79000-B8576-C898-01 9 - 19
TN B and T WN between 8 and
16 bit memory areas
70
Addresses
in
Byte 5
Byte 4
Byte 3
Byte 2
Byte 1
Source/
destination
Transfer of bytes 1 to 5:
Transfer of bytes 1 to 4:
L <source address>
L <destination address>
TNB 5
L <source address>
L <destination address>
TNW 2
15 7 0
Addresses
in ascending
Destination/source
address
Byte 4
Byte 2
Byte 5
Byte 3
Byte 1
8
ascending
order
address
order
Fig. 9-8 Transferring blocks of memory
T r a nsferring Fields of M emor y
CPU 928B Programming Guide
9 - 20 C79000-B8576-C898-01
9.3.1
Exam p le of Trans ferring
Memory Fields
a) Task
You wa nt t o copy a f ie ld o f maxi mum 40 95 d ata wo rds from a DB or DX data
block to a different DB or DX data block. The start of the field of data
is specified within the source and destination data block by an offset
valu e be twee n 0 an d 4095 .
The pr ogra m is s tore d in F B 10.
Before the copying function is started, the input parameters are
checke d. I n the even t of a n erro r, b it no. 7 = 1 is set in the o utpu t
parameter STAT and the type of error specified in bits no. 0 to no. 2 as
follows:
Continued on next page
KY (type, no.)
Source DB
KF (Offset )
Source DB
KY (type, no.)
Dest. DB
KF (Offset)
Dest. DB
KF (block length)
STNO
SOFF
DTNO
DOFF
LENG
FB10
STAT BY
Status
Fig. 9-9 Functi on block for transferri ng fi el ds of data
12345670
0 = no error
1 = error
Bit no.
Type of error
1 = source DB = destination DB
2 = offset or length > 4095
3 = source DB does not exist or illegal
4 = source DB too short
5 = destination DB does not exist or illegal
6 = destination DB in read-only memory (EPROM submodule)
7 = destination DB too short
9
Tra nsfe rring Fields of Mem o ry
CPU 928B Programming G uide
C79000-B8576-C898-01 9 - 21
Example 1 continued:
b) Program structure:
FB 10 is made up of five program sections with the following tasks:
- Input parameters
a) Check that the source and destination data block are not the same
type a nd s am e nu mber .
b) Check that the input parameters "source offset", "destination offset"
and "l engt h of f ield " are le ss t han 40 96.
- Sourc e da ta blo ck:
a) Check that the source data block exists and is long
enough.
b) Calc ulat e th e abso lute a ddre ss o f the la st d ata wo rd i n th e
dest in atio n fi eld.
- Desti nati on dat a bl oc k:
a) Check that the destination data block exists and is long enough and
whether it is in the random access memory (RAM submodule or DB-RAM).
b) Calc ulat e th e abso lute a ddre ss o f the la st d ata wo rd i n th e
dest in atio n fi eld.
- Transfer:
Execu te t he cop y fu nc tion w ith the he lp o f th e TNW oper at ion.
Blocks of data with more than 255 words are transferred in sub-fields
of 12 8 wo rd s (o pera ti on T NW 128 ).
Any remaining data is transferred by an additional TNW operation.
- Condi tion c ode:
Wri te t he out put pa ra mete r "sta tu s" acc or ding t o the re sult s of t he
che ck s carr ie d out.
c) Occupied memory cells
FW 242 End address of the data destination
FW 244 End address of the data source
FW 246 Len gth of the fie ld of da ta
FW 248 Offset in the destination data block
FW 250 Typ e an d numb er o f the de stin atio n data blo ck
FW 252 Off set in the sou rc e da ta blo ck
FW 254 Typ e an d numb er o f the so urce dat a bloc k
RS 60 Sub-field counter
Continued on next page
T r a nsferring Fields of M emor y
CPU 928B Programming Guide
9 - 22 C79000-B8576-C898-01
Example 1 continued:
b) Programming function block FB 10
Note:I f yo u want to co py f rom da ta w ord DW 0, th e pr ogra m sect ions s hown
in heavy print can be omitted. You do not specify an offset value.
FB10
SEGM EN T 1
NAME:D B-DB -T R DATA B LOCK -D ATA BLOC K TRAN SF ER
DECL : STNOI/Q /D /B/T /C: D KM/K H/ KY/K S/KF /K T/KC /K G: KY
DECL :SOFFI/Q/D/B/T/C: D KM/KH/KY/KS/KF/KT/KC/KG: KF
DECL :DTNOI/Q/D/B/T/C: D KM/KH/KY/KS/KF/KT/KC/KG: KY
DECL :DOFFI/Q/D/B/T/C: D KM/KH/KY/KS/KF/KT/KC/KG: KF
DECL :LENGI/Q/D/B/T/C: D KM/KH/KY/KS/KF/KT/KC/KG: KF
DECL :STAT I/Q/D/B/T/C: Q BI/BY/W/D: BY
:
: BEGIN NING O F IN PUT PA RAME TE RS
:LW = STNO TYP E (D B/DX ) AND NU MBER OF
:T FW 254 THE SOURCE DATA BLOCK
:LW = DTNO TYP E (D B/DX ) AND NU MBER OF
:T FW 250 THE DESTINATION DATA BLOCK
:!=F SOURCE DB = DESTINATION DB ?
:JC =F001 JUM P IF YES
:
:
:
:LW =SOFF OFFSET IN SOURCE
:T FW 252 DAT A BL OC K
:LW =DOFF OFFSET IN DESTINATION
:T FW 24 8 DAT A BLOCK
:OW
:LW = LAEN LEN GTH (NUM BE R OF D ATA WORD S)
:T FW 246 O F THE FIEL D TO B E TR AN SFER RE D
: (LENG TH O F FIEL D)
:OW OR SOURCE OFFSET, DESTINATION OFFSET
:L KH F000 LENGTH >= 4096 ?
:AW JUMP, IF YES
:JP = F002 END OF INPU T PARA ME TERS
:
:
:
:
:
:
Continued on next page
9
Tra nsfe rring Fields of Mem o ry
CPU 928B Programming G uide
C79000-B8576-C898-01 9 - 23
Example 1 continued:
: BEGINNI NG O F SOUR CE D AT A BL OC K
:L FW 254 TYPE AND NU MBER OF SO URCE D ATA BLOC K
:JU OB 18 1 TES T DATA BLO CK
:JC =F003 JUM P, I F BL OC K TE ST N EG ATIV E
:TAK A1: NUM BER OF DWs , A2 : ADDR ES S
:ENT A3: ADDRESS
:L F W 25 2 OFFSE T IN SOU RC E DA TA B LO CK
:ENT A3: NUMBER OF DWs, A4: ADDRESS
:L FW 246 LENGT H OF F IELD
:+ F OFF SET + LENG TH O F FIEL D
:<F NO. OF DWs <O FFSE T + FI ELD LE NGTH ?
:JC =F004 JUM P, I F YE S
:L KB 1 A2:
OFFSET
+ FIEL D LE N, A3: ADD RE SS
:-F
OFFSET
+ FIEL D LE NG TH - 1
:+F
OFFSET
+ FIEL D LE N - 1 + ADDR ES S
:T FW 244 END ADDRESS OF THE DATA SOURCE
: END OF SOUR CE DAT A BL OC K
:
:
:
:
:
:
:
: BEGINNI NG O F DEST INAT IO N DA TA BLO CK
:L FW 250 TYPE AND NU MBER OF DE STIN AT ION DATA B LOCK
:JU OB 18 1 TES T DATA BLO CK
:JC =F005 JUM P, I F BL OC K TE ST N EG ATIV E
:JM =F006 JUM P, I F BL OC K IN EPR OM
:TAK A1: NUM BER OF DWs , A2 : ADDR ES S
:ENT A3: ADDRESS
:L FW 248 OFFSET IN DESTINATION DATA BLOCK
:ENT A3: NUMBER OF DWs, A4: ADDRESS
:L FW 246 LENGT H OF F IELD
:+ F OFF SET + LENG TH O F FIEL D
:<F NO. OF DWs <
OFFSET +
FIEL D LE NG TH ?
:JC =F007 JUM P, I F YE S
:L KB 1 A2:
OFFSET +
FIEL D LE N, A3: ADD RESS
:-F
OFFSET +
FIEL D LE NG TH - 1
:+F
OFFSET +
FIEL D LE N - 1 + ADDR ES S
:T FW 242 END ADDRESS OF THE DATA DESTINATION
: END OF DEST IN ATIO N DA TA BLO CK
:
:
:
:
Continued on next page
T r a nsferring Fields of M emor y
CPU 928B Programming Guide
9 - 24 C79000-B8576-C898-01
Example 1 continued:
: BEGINNI NG O F TRAN SFER
:L KB 0 COMPA RI SON VA LU E
:L FY 246 FIELD LENGTH, HIGH BYTE
:!=F FIELD LENGTH >= 256 WORDS ?
:SLW 1 MULTIPL IED BY 2, NUMB ER OF SUB-
:T RS 60 FIE LDS EA CH WIT H 12 8 WORD S
:L FW 244 END ADDRESS OF THE DATA SOURCE
:L FW 242 END ADDRESS OF THE DATA DESTINATION
:JC =REST JUM P, I F FI EL D LE NGTH < 256 W ORDS
LOOP :TNW 128 T RA NSFE R A SUB- FI ELD
:ADD KF -128 REDUCE SOURCE END ADDRESS BY
:TAK LENGTH OF THE SUB-FIELD
:ADD KF -1 28 RED UCE DE ST INAT ION EN D AD DRES S
:TAK BY LE NG TH O F THE SUB- FI ELD
:JU OB 16 0 COU NT LOO P
:JC =LOOP JUM P, I F NO T ALL SUB-
: FIELD S HA VE BEE N TR AN SFER RE D
REST :DO FW 246 FIELD LENGTH, LOW BYTE
:TNW 0 T RA NSFE R RE MA INDE R OF F IELD
: END TRANSFER
:
:
:
:
:
: BEGINNI NG O F COND ITIO N CODE
:L KB 0 ID 00 (HEX): NO ERROR
END :T =STAT O UTPU T PARA ME TER ST AT US/E RROR
:BEU
F001 :L KB 12 9 ERR OR ID 81 ( HE X):
:JU =END SOURCE DB = DESTINATION DB
F002 :L KB 13 0 ERROR I D 82 (HE X) :
:JU =END
OFFSET OR
LENGTH >= 4096
F003 :L KB 13 1 ERROR I D 83 (HE X) :
:JU =END SOURCE DB ILLEGAL
F004 :L KB 13 2 ERR OR ID 84 ( HE X):
:JU =END SOURCE DB TOO SHORT
F005 :L KB 13 3 ERR OR ID 85 ( HE X):
:JU =END DESTINATION DB ILLEGAL
F006 :L KB 13 4 ERROR I D 86 (HE X) :
:JU =END DESTINATION DB IN READ-ONLY MEMORY
F007 :L KB 13 5 ERR OR ID 87 ( HE X):
:JU =END DESTINATION DB TOO SHORT
: END OF COND IT ION CODE
:BE
9
Tra nsfe rring Fields of Mem o ry
CPU 928B Programming G uide
C79000-B8576-C898-01 9 - 25
9.4 Operations with the Base Address Register (BR Register)
Application
T he BR register (base address register, 32 bits) is used by the load an d
transfer operati ons described from Section 9.3.3 onwards to address
the m emory. The absolu te address of the me mory cell to be acce ssed
is calculated as the sum of the contents of the BR register and a
constant as follows:
Absolute address = BR register contents + constant
Operations
Operation Operand Function
MBR
ABR
Constant
(0H to
F FFFFH)
Constant
(-32 768 to
+32 767)
L o ad the BR re gi ster with a
20-bit constant 1)
Add a 16-bit constant to the contents
of th e BR regi st er
1) Bits 220 to 231 of the BR register are set to "0".
Changing the BR register
•• The BR register is retained when the same program processin g
leve l i s continued in an other block cal led by t he j ump operatio n
(JU FB / JC FB).
•• The BR register is retained after n esting in a di fferent program
exe cu tion le ve l.
Wh en the system progr am calls another program processing level,
the BR register is set to "0".
MBR 0 to FFFFF
0.........0 BR
20-bit constant
ABR -32768 to +32767
BR
BR
16-bit constant
(fixed point number)
31 19 0
31 0
31 0
F ig. 9-10 Loading the BR register
Table 9-5 Loa d a nd ar it hmetic ope ra t io ns with t he BR reg is te r
O perations with the Ba se Add ress Register (BR Register)
CPU 928B Programming Guide
9 - 26 C79000-B8576-C898-01
Operations with the Base Address Register (BR Register)
9.4.1
Operations for Transfer
between Registers
Application
You ca n us e th e operati on s desc ribed i n this se ct ion for th e fa st
exchange of values between the rest ist ers ACC U 1, STEP ad dr ess
counter (SAC) a nd base ad dress register (BR).
Operations
Operation Operand Explanation
MAS
MAB
MSA
MSB
MBA
MBS
—
—
—
—
—
—
Transfer the contents of ACCU 1 (bit 20
to 214) to the SAC register (STEP
add r es s counte r )
Transfer the contents of ACCU 1 (bits
20 to 231) to th e BR re gist er (base
add ress re giste r)
Transfer the con tent s o f t he STEP
a ddress coun ter (SAC register) to
ACCU 1 1)
Transfer the con tent s o f t he SAC
register (STEP address counter) to the
B R register (base ad dress register) 1)
Transfer the co ntent s of t he BR register
(base addre ss regist er) to ACC U 1
Transfer the co ntent s of t he BR register
(bi ts 20 to 214, base ad dress reg is te r) to
t he S AC register (STEP address
counter)
1) Bits 215 to 231 are set to "0"
The f ollowing f igure illustrates how the registers are changed by the
operations.
Table 9-6 Operations for transfer between registers
9
O perations with the Base Address Register (BR Registe r)
CPU 928B Programming G uide
C79000-B8576-C898-01 9 - 27
9.4.2
Accessing the Local
Memory
Application
With the f ollowing operations, you can access the local mem ory
organized in words usin g an absolu te memor y address. The absolute
a ddress is the total of the B R register co ntents and the 16-bit constan t
co n ta in e d in t he o perat io n (-32768 to +32767).
Operations
Operation Operand Description
LRW
LRD
Constant
(-32768 to
+32767)
Constant
(-32768 to
+32767)
a dd the specified co nsta nt to content 1)
of th e BR regi st er and load the wo rd
a ddress ed in this way in ACCU-1-L
a dd the specified co nsta nt to content 1)
of th e BR regi st er and load the double
word addressed in this way in ACCU 1
TRW Constant
(-32768 to
+32767)
a dd the speci fied co nstant to content
of the BR register and transfer th e
content of ACCU-1-L to the word
a ddress ed in this way
MAS, MBS MSA, MSB
ACCU 1, BR
SAC
SAC
ACCU 1, BR
MAB, MBA
ACCU 1
BR
31 15 0
14 0
16
31 16 15 0
31 16 15 0
14 0
31 1615 0
xxx..............
00
..............
0
F ig. 9 -8 Regis te r - registe r transfe r op eratio ns
Table 9-7 Operati ons for accessi ng the local memory
O perations with the Base Add ress Register (BR Register)
CPU 928B Programming Guide
9 - 28 C79000-B8576-C898-01
Operation Operand Description
Tab le 9-7 cont in ued:
TRD Constant
(-32768 to
+32767)
a dd the speci fied co nstant to content
of the BR register and transfer th e
content of ACCU 1 to the double word
a ddress ed in this way
1) ACCU 2 new = ACCU 1old
Permi ssible address area
The absol ut e ad d re ss must be as fo ll ow s:
•• for LRW, TRW: bet ween 000H and E3FFH or E800H and
EDFFH
•• for LRD, TRD: betwee n 000H and E3FEH or E800H and
EDFEH
Error reaction
If the calculated address of the m em ory location is not in the
perm i ssible memo ry area, the CPU de tect s a runt ime error a nd ca lls
OB 31, p rovid ing i t is loaded. If OB 3 1 i s not loaded, th e CP U goes to
the stop mode.
In both cases, error IDs are entered in ACCU-1-L , that define the error
i n greater de tail (see Se ctio n 5.6.2).
9.4.3
Accessing the Global
Memory
Application
With the f ollowing operations, you can access the global m em ory
organized in bytes or word s using an absolute memory address. The
abso l ut e add re ss is th e to tal of th e B R regi ster co n te n ts and th e
constant c ontained in the op er ation (-32768 to 32767).
Testin g and setting a b usy
location in the global area
You ca n co n tro l the a cces s o f ind iv i dua l CPUs to c ommo n memory
areas using a busy location. Each m em ory area used by more than one
CPU has a busy location assigned to it that must be tested by each
CPU before it can ac cess this area. Th e busy l oc ation eit he r contains
the value "0 " or the slo t identifier of the CPU currently using the
memory area. This CPU releases t he memor y area b y w riting "0" to
the busy location again when it is finished. (Note th e explanations
for the operatio ns "set semaphore/SED" and "enable semap ho r e/ SEE"
i n Section 3.5.5.).
9
O perations with the Base Address Register (BR Registe r)
CPU 928B Programming G uide
C79000-B8576-C898-01 9 - 29
The CPU tests and sets a busy location using the TSG operation.
Operation Operand Explanation
TSG -32768 to
+32767 Add the specified constant to the
content of the BR register and test and
se t the location addresse d in t his way.
Sequence
The low by te of the word addressed by the contents of the BR register
+ the constant is used as the busy location. If the content of the low
by te is "0", the TSG operation enters the slot ID (from RS 29) into the
busy locati on.
Testing (= reading) and setting (= writing) the busy location is one
program unit that cannot be interrupted.
Result
You can evaluate the result of the test in condition codes CC 0 and
CC 1, as f ollows:
CC 1 CC 0 Explanation
0
1
0
0
0
1
Th e b usy locati on contains the value
"0"; the CPU enters its slot ID.
The CPU’s own slot ID is already
en ter ed in th e busy loca tion.
The busy location contains a different
slot ID.
Note
All CPUs that require synchronized access to a co mmon globa l
m e mory area mu st us e the TS G o per a tion.
Permi ssible address area
Th e absol ute addre ss must be betwe en 0000H a nd EF FFH.
Error reaction
If the calculated address of the m em ory location is not in the range
shown, the CPU detects a runtime error and calls OB 31, p roviding it
is loaded. If OB 31 is not loaded, the CPU goes to the stop mode.
In both cases, error IDs are entered in ACCU-1-L , that define the error
i n greater de tail (see Se ctio n 5.6.2).
O perations with the Base Add ress Register (BR Register)
CPU 928B Programming Guide
9 - 30 C79000-B8576-C898-01
Load and transfer
operatio ns for the global
mem o ry org ani zed in bytes
Operation Operand Description
LY GB
LY GW
LY GD
TY GB
TY GW
TY GD
-3276 8 to
+32767
-3276 8 to
+32767
-3276 8 to
+32767
-3276 8 to
+32767
-3276 8 to
+32767
-3276 8 to
+32767
a dd the speci fied co nstant to content
of the BR register and load the byte
addressed in t his way i n
ACCU-1-LL 1) 3)
a dd the speci fied co nstant to content
of th e BR regi st er and load the wo rd
addressed in this way in ACCU-1-L 2) 3)
a dd the speci fied co nstant to content
of th e BR regi st er and load the double
word addressed in this way in ACCU 13)
a dd the speci fied co nstant to content
of the BR register and transfer th e
content of ACCU-1-LL to the byte
a ddress ed in this way
a dd the speci fied co nstant to content
of the BR register and transfer th e
content of ACCU-1-L to the word
a ddress ed in this way
a dd the speci fied co nstant to content
of the BR register and transfer th e
content of ACCU 1 to the double
w or d addr e sse d in this wa y
1) ACCU-1-LH and ACCU-1-H are set to ’0’.
2) ACCU-1-H is set to ’0’.
3) ACCU 2 new : = ACCU 1old
Permi ssible address area
The absol ut e ad d re ss must be as fo ll ow s:
•• between 0 an d EFFFH (for LY GB, TY GB)
•• be tween 0 a nd E FFEH ( for LY GW, TY GW)
•• between 0 and EFFCH (for LY GD, TY GD)
Tab le 9-8 O pe rations for ac cess to the glo b a l memory organized in byte s
9
O perations with the Base Address Register (BR Registe r)
CPU 928B Programming G uide
C79000-B8576-C898-01 9 - 31
Error reaction
If the calculated address of the m em ory location is not in the range
shwon, the CPU detects a runtime error and calls OB 31, providing it
is loaded. If OB 31 is not loaded, the CPU goes to the stop mode.
In both cases, error IDs are entered in ACCU-1-L , that define the error
i n greater de tail (see Se ctio n 5.6.2).
Load and transfer
operatio ns for the global
mem o ry org ani zed in words
Operation Operand Description
LW GW
LW GD
TW GW
TW GD
-3276 8 to
+32767
-3276 8 to
+32767
-3276 8 to
+32767
-3276 8 to
+32767
a dd the speci fied co nstant to content
of th e BR regi st er and load the wo rd
a ddress ed in this way in ACCU-1-L 1) 2)
a dd the speci fied co nstant to content
of th e BR regi st er and load the double
word addressed in this way in ACCU 1 2)
a dd the speci fied co nstant to content
of the BR register and transfer th e
content of ACCU-1-L to the word
a ddress ed in this way
a dd the speci fied co nstant to content
of the BR register transfer the
content of ACCU 1 to the double
w or d addr e sse d in this wa y
1) ACCU-1-H is set to ’0’.
2) ACCU 2 new : = ACCU 1old
Permi ssible address area
The absol ut e ad d re ss must be as fo ll ow s:
•• for LW GW, TW GW: between 0 and EFFFH
•• for LW GD, TW GD: between 0 and EFFEH
Error reaction
If the calculated address of the m em ory location is not in the range
shown, the CPU detects a runtime error and calls OB 31, p roviding it
is loaded. If OB 31 is not loaded, the CPU goes to the stop mode.
In both cases, error IDs are entered in ACCU-1-L , that define the error
i n greater de tail (see Se ctio n 5.6.2).
Table 9-9 Operations for access to the gl obal memory organized in words
O perations with the Base Add ress Register (BR Register)
CPU 928B Programming Guide
9 - 32 C79000-B8576-C898-01
9.4.4
Accessing the Page Memory
Application
Usi ng t he foll owing operations, you can access pages organ ized in
bytes or words v ia a n absolut e memory address. The abso lute
a ddress is the total of the B R register co ntents and th e co nstant
co n ta in e d in t he o perat io n (-32768 to 32767).
Procedure of acce ssing
pages
The global area includes a "windo w" in th e address are a F4 00H to
FBFFH to allow access to one of maxi mum 256 memory areas
(= pages). A page occupies a maximu m of 2 K addresses and can be
organized in by tes or words. Bef ore each access to the page area, one
of the 256 pag e s must be sele cted by en t ering i ts pa g e number in t he
se lect registe r. Writ in g t o th e sel ect re g ister an d the subsequen t ac ce ss
to t h e pa ge a rea ca nn o t be i nterrupted.
Bef ore any access (load/transfer) to the page area, one of the 256
pages must be opened. To do this, you transf er the number of the page
to be opened t o ACCU-1-L; th is n umber is e nt ere d in t he CPU
int ern al page reg ist er w i th t h e AC R o peratio n. A l l su bs equ en t page
operations write the contents of the page register to the select register
of t he appropriate modules on the S5 bus b efore the page is accessed.
Changing the page register
•• The page register is retained when the same progra m
pr ocessing level is continued in another block c a ll ed by t he
ju mp o pera ti on (JU FB / JC FB).
•• When the page register is modi fied in a block, its va lue is
retained if the program jumps back to the calling block at the end
of the blo ck.
•• After another program processin g level has been inserted, the
system prog ram load s the s ame va lue in the page register as it had
before the other level was inserte d.
•• Wh en the system progr am call s another program processin g
level, the page register is set to " 0".
9
O perations with the Base Address Register (BR Registe r)
CPU 928B Programming G uide
C79000-B8576-C898-01 9 - 33
Opening a page
Operation Operand Explanation
ACR Ope n th e page w h ose n umber is
l ocated in AC C U - 1-L
permitted values: 0 to 255
Error reaction
The page nu m be r must be be tw e en 0 a n d 255. If t his is n o t th e case,
the CPU recognizes a runtime error and calls OB 31, providing it is
loaded. If OB 31 is not loaded, the CPU goes to the stop mode.
In both cases, error IDs are entered in ACCU-1-L , that define the error
i n greater de tail (see Se ctio n 5.6.2).
Testin g and setting a b usy
locati on i n th e p age area
You ca n co n tro l the a cces s o f ind iv i dua l CPUs to c ommo n memory
areas using a busy location. Each m em ory area used by more than one
CPU has a busy location assigned to it that must be tested by each
CPU before it can ac cess this area. Th e busy l oc ation eit he r contains
the value "0 " or the slo t identifier of the CPU currently using the
memory area. This CPU releases t he memor y area b y w riting "0" to
the busy location again when it is finished. (Note th e explanations
of th e ope ra ti o ns "set semaphore /SED" an d "e na ble se ma ph o re/SEE"
i n Section 3.5.5.).
The CPU tests and sets a busy location on the open page using the
TS C operatio n.
Operation Operand Explanation
TS C -32768 to
+32767 Add the specified constant to the
content of the BR register and test and
set the location on the opened page
addressed in this way.
Sequence
The low by te of the word addressed by the contents of the BR register
+ the constant is used as the busy location. If the content of the low
byt e is "0", the TSC operati on e nte rs th e sl ot I D (f rom RS 29) i nto t he
busy locati on.
Testing (= reading) and setting (= writing) the busy location is one
program unit that cannot be interrupted.
O perations with the Base Add ress Register (BR Register)
CPU 928B Programming Guide
9 - 34 C79000-B8576-C898-01
Result
You can ev al uat e t he resu lt o f th e TSC o perat io n i n co n diti o n co des
CC 0 and CC 1, as f ollows:
CC 1 CC 1 E xplanation
0
1
0
0
0
1
The busy location contains the value "0"; the
CPU enters its slot ID.
The CPUs own slot ID is already e ntered in
the busy location.
The busy location contains a dif ferent slot
ID.
Note
All CPUs requiring s yn chronized access to a com m on global
m e mory area (page a rea) must u se the TSC o peratio n.
Error reaction
The location must be on the corresponding module and on the
common page between F F400H and F FBFFH. If this is not the case,
the CPU recognizes a runtime error and calls OB 32, providing it is
loaded. If OB 32 is not loaded, the CPU goes to the stop mode.
In both cases, error IDs are entered in ACCU-1-L , that define the error
i n greater de tail (see Se ctio n 5.6.2).
Load and transfer
operations for the pages
organized in bytes
Operation Operand Explanation
LY CB
LY CW
LY CD
-32768 to
+32767
-32768 to
+32767
-32768 to
+32767
ad d th e spec ified con st ant to c on ten t of
th e BR regi st er and load the byte in the
opened page addressed in this way into
ACCU-1-LL 1) 3)
ad d th e spec ified con st ant to c on ten t of
th e BR regi st er and load the wo rd in
the opened page addressed in this way
int o ACCU- 1- L 2) 3)
ad d th e spec ified con st ant to c on ten t
of the BR register and load the double
word in the opened page addressed in
this way into ACCU 13)
Tab le 9-1 0 Operations for ac cess to the pages organi z ed in bytes
9
O perations with the Base Address Register (BR Registe r)
CPU 928B Programming G uide
C79000-B8576-C898-01 9 - 35
Operation Operand Explanation
Table 9-10 continued:
TY CB
TY CW
TY CD
-32768 to
+32767
-32768 to
+32767
-32768 to
+32767
ad d th e spec ified con st ant to c on ten t
of th e BR register and transfer the
conten t o f ACCU-1-LL to the byte
addressed in this way in the opened
page.
ad d th e spec ified con st ant to c on ten t
of th e BR register and transfer the
cont ent of ACC U-1-L t o the word
addressed in this way in the opened
page.
ad d th e spec ified con st ant to c on ten t
of th e BR register and transfer the
content of A CCU 1 to the doub le
word addressed in this way in the
opene d page.
1) ACCU-1-L H and ACCU-1-H are se t to ’0’ .
2) ACCU-1- H is set to ’0’.
3) ACCU 2 new : = ACCU 1old
Permi ssible address area
The absol ut e ad d re ss must be as fo ll ow s:
•• for LY CB, TY CB: between F400H and FBFFH
•• for LY CW, TY CW: between F400H and FBFEH
•• for LY CD, TY CD: between F400H and FBFCH
Error reaction
If the calculated byte address is not in the range shown, the CPU
recognizes a runtime error and calls OB 31, providing it is loaded. If
OB 31 is not loaded, the CPU goes to the stop mode.
In both cases, error IDs are entered in ACCU-1-L , that define the error
i n greater de tail (see Se ctio n 5.6.2).
O perations with the Base Add ress Register (BR Register)
CPU 928B Programming Guide
9 - 36 C79000-B8576-C898-01
Load and transfer
operations for pages
organized in wo rd s
Operation Operand Explanation
LW CW
LW CD
TW CW
TW CD
-32768 to
+32767
-32768 to
+32767
-32768 to
+32767
-32768 to
+32767
ad d th e spec ified con st ant to c on ten t
of the BR register and load the word
addressed in this way in the opened
page into ACCU-1-L 1)
ad d th e spec ified con st ant to c on ten t
of the BR register and load the double
word addressed in this way in the
opene d page into A CCU 1 2)
ad d th e spec ified con st ant to c on ten t
of th e BR register and transfer the
cont ent of ACC U-1-L t o the word
addressed in this way in the opened
page.
ad d th e spec ified con st ant to c on ten t
of the BR reg ister transfe r the
content of A CCU 1 to the doub le
word addressed in this way in the
opene d page.
1) ACCU-1- H is set to ’0’.
2) ACCU 2 new : = ACCU 1old
Permi ssible address area
The absol ut e ad d re ss must be as fo ll ow s:
•• for LW CW, T W CW: betwee n F400H and FBFFH
•• for LW CD, TW CD: between F400H and FBFEH
Error reaction
If the calculated address of the m em ory cell is not in the range shown,
the CPU recognizes a runtime error and calls OB 31, providing it is
loaded. If OB 31 is not loaded, the CPU goes to the stop mode.
In both cases, error IDs are entered in ACCU-1-L , that define the error
i n greater de tail (see Se ctio n 5.6.2).
Tab le 9-11 Operations for access to the pa ges organized in words
9
O perations with the Base Address Register (BR Registe r)
CPU 928B Programming G uide
C79000-B8576-C898-01 9 - 37
Contents of Chapter 10
10.1 Multiprocessor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 4
10.1.1 When to use t he Multiprocessor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 4
10.1.2 What Commun ica tion s Mec ha nism s are Available?. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 4
10.1.3 Exchanging Data via IPC Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 5
10.1.4 I/O Fl ag Assig nment a nd IPC Fl ag As sig nmen t in Mu lt iproc es so r Mode (DB 1) . . . . 10 - 9
10.1.5 How to Cre ate Data Bl ock D B 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 9
10.2 Multiprocessor Communication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 13
10.2.1 Intro ducti on. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 13
10.2.2 How the T r a ns mi tter a nd Rece iver are Identifie d. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 14
10.2.3 Why Da ta is B uffered. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 15
10.2.4 How th e Buffer is Processed and Managed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 16
10.2.5 System Start-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 19
10.2.6 Callin g Commun ic ation OB s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 20
10.2.7 How to Assign Parameters to C ommunication O Bs. . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 21
10.2.8 How to Evaluate the Output Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 22
10.3 Runtimes of the Communic ation OB s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 29
10.4 INITIALIZE Functi on (OB 200) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 31
10.4.1 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 31
10.4.2 Call Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 33
10.4.3 Input Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 33
10.4.4 Output Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 36
10.5 SEND Fu nction (OB 202) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 38
10.5.1 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 38
10.5.2 Call Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 38
10.5.3 Input Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 38
10.5.4 Output Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 40
10
Multiprocessor Mode and
Communication
10
CPU 928B Programm ing Guide
C79000-B8576-C898-01 10 - 1
10.6 SEND TEST Fun ct ion (OB 203) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 43
10.6.1 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 43
10.6.2 Call Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 43
10.6.3 Input Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 43
10.6.4 Output Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 43
10.7 RE CE IVE Function (OB 204) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 45
10.7.1 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 45
10.7.2 Call Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 45
10.7.3 Input Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 45
10.7.4 Output Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 46
10.8 RE CE IVE TEST Fu nctio n (O B 205) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 49
10.8.1 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 49
10.8.2 Call Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 49
10.8.3 Input Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 49
10.8.4 Output Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 49
10.9 Appli ca tions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 51
10.9.1 Callin g the Spec ial Function OB usi ng Fun ction B locks . . . . . . . . . . . . . . . . . . . . . . . 10 - 51
P rogramming fu nct ion blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 52
10.9.2 T ra ns ferring Dat a Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 58
P rogramming FB 110 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 58
Application of FB 110 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 62
10.9.3 Exte ndi ng t he IPC Flag Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 64
The problem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 64
Th e solution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 - 6 5
Data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10- 6 5
Structure of th e co nnection l ist. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 6 6
Program structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 68
P rogramming fu nct ion blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 70
Application exa mple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 75
Contents
CPU 928B Programming Guid e
10 - 2 C79000-B8576-C898-01
10M ultiprocessor Mode and
Communication
At th e begin n ing of this ch a pter, you will se e w he n you c an use th e
mul ti processor mod e an d wh ic h d at a e x ch an g e is poss ible i n th is
mode. The chapter provides you with inf ormation about program ming
for multiprocessor operation (Secti on 10.1).
The second part of the chapter provides y ou with detailed instructions
and examples of exchanging larger amounts of data in the
multiprocessor mode (multiprocessor communication Sections 10.2 to
10.9).
10
CPU 928B Programming G uide
C79000-B8576-C898-01 10 - 3
10.1 M ultiprocessor Mo de
Def init ions of term s
You are in mul ti p roc essor mo de a s so o n as you plug i n a co ord i nato r
modul e, regardles s of h ow many CPUs o r C P/I Ps are pl ugg e d in .
10.1.1
W hen to use the
Mu ltip ro cessor M od e •• If you r u ser progra m i s to o la rge for o ne CPU and th e re i s n ot
eno ugh memory, d istribute your prog ra m on s ev eral CPUs.
•• When a particular part of yo ur syste m has to be processed
especiall y fast, separate the appropriate program part fro m the
total program and run it on its own fast CPU.
•• When yo u r system co n sists of several part s th at you can separate
easily and control independently , let CPU 1 process system part 1,
CPU 2 pro cess system part 2, etc.
For more information on multiprocessing, read the information in your
system manual. This will help you to decide wh ich CPUs are best suited
for your problem.
10.1.2
What Communications
Mechanisms are Available? •• "I nterp rocessor commun i catio n fl ags" are available for cyclic
exchange of binary data between C PUs (C PU 948, CPU 946/ 947,
CPU 928B, CPU 928 and CPU 922) or between CPUs and
c ommunications processors (CPs).
•• For the exchange of large amounts of data (e.g., entire data blocks)
bet ween the CPU 948, CPU 946/947, CPU 928B, CPU 928 and
CPU 922 yo u are su ppo rted by t he " special functions for
multiprocessing" OB 200 to OB 205 (for more informati on refer
to Section 10.2).
Multiprocessor Mode
CPU 928B Programming Guide
10 - 4 C79000-B8576-C898-01
10.1.3
Exc h ang in g Data via IPC
Flags Interprocessor c ommunication (I PC) flags are available for cyclic
exchange o f binary data. They are used mainly for transmitting
in formation by te by byte.
Dat a is transfe rred as fol lo ws:
CPU(s) ↔CPU(s)
CPU(s) ↔C ommunica tions processor(s)
The system program transfers IPC f lags once per cycle. For data
tra ns fe r bet w ee n CPUs, the IPC fla gs are buf f ered physica ll y on t h e
coordinator.
IPC flag s are byt es th at a re t ran sf erred. You d efine t he m in DB 1 for
each CPU as IPC input or output flags. If, f or example, you have
define d flag byte 50 o n the CPU 1 as an I PC output flag byte, its
si gna l sta te is trans fe r red cyc li ca ll y vi a the co ord i nato r to the CPU on
which the flag byte FY 50 is def ined as an IPC input flag byte (see
Sec tio n 10.1.5).
Note
T her e is no error message when the IPC f lag by te exists
physically but is only written by one CPU and never read out and
vice-versa.
Mem ory area
With the CP U 94 8 the memo ry area fo r th e IPC flag s i n the
coo rdi n ator an d th e CPs co vers th e ad d re sse s F 200H to F F2FFH.
On a CPU/c ommunicati ons processor there are 256 available IP C flag
bytes.
Jum per sett ings
To avoid double assignments y ou m ust group the 256 available IPC
fla g bytes on t he C OR o r CP m odules. Fi el ds o f 32 bytes ca n be
enabled or disabled ( your system manual c ontains information about
setting the jumpers).
10
Multiprocessor Mode
CPU 928B Programming G uide
C79000-B8576-C898-01 10 - 5
Example
Note
- The onl y flag bytes that you can speci fy as IPC flags are the ones
enabled o n the coor di nat or or o n the CP(s).
- A flag byte that is de fined on one or more CPUs as an IPC input
flag byte must be de fined as an IPC outpu t flag byte on one other
CPU or CP. An IPC output flag byte is only allowed on one CPU,
but this may be used as an IPC input flag in all other CPUs in the
rack.
- I f you have flag bytes that you have not de fined as IPC flags in a
CPU, you can use them as normal flags!
You cannot use S flags as IPC flags!
CPU 1
IPC output flags:
FY 96 to FY 119
IPC input flags:
FY 120 to FY 125
CPU 2
Coordinator
IPC output flags:
FY 120 to FY 125
IPC input flags:
FY 96 to FY 119
Write
Read
Write
Read
Enabled area
per jumpers:
IPC flag bytes
FY 96 to FY 127
Fig. 10-1 Transferring I PC flags in the multiprocessor mode
Multiprocessor Mode
CPU 928B Programming Guide
10 - 6 C79000-B8576-C898-01
Data exchange bet ween
CP Us and com m unication
processors
If you want to exchange data between one CPU and one CP, y ou must
enable the necessary number of IPC f lags on the CP. You have 256
bytes available that you can divide in to groups of 32 bytes.
I f you want to transfer data fro m one CPU to several CPs, the areas you
enable in the CPs and the coordinator must no t o ve rl ap, otherwise th e
sa me address is assigned twice.
If you want to use IPC f lags simultaneously on th e coordina tor and in
one or m o re CPs , you must al so preven t dou ble a ddressing a s foll ows :
Divide the IPC flags amo ng the coor dinator and the CP s in grou ps of
32 b y tes . Remove jumper s on t he coord inator to ma sk the IP C fl ag
by tes that you want to use in the CP (refer to the System Manual).
You can define a specific flag byte as an IPC output flag in one CPU
only. However, you can de fine a specific flag byte as in IPC input flag in
severa l CPU s.
Example
CPU 1
Enabled area:
IPC flag bytes
FY 96 to FY 127
Enabled area:
IPC flag bytes
FY 192 to FY 223
CP 1
CP 2
CP 1
CP 2
CP 1
CP 2
IPC output flags:
CP 1: FY 96 to FY 119
CP 2: FY 201 to FY 205
IPC input flags:
CP 1: FY 120 to FY 125
CP 2: FY 195 to FY 200
Fig. 10-2 Example of I PC fl ag areas on the CPs
10
Multiprocessor Mode
CPU 928B Programming G uide
C79000-B8576-C898-01 10 - 7
Transmitting IPC flags in
multiprocessor operation
At the e nd of each progra m cycle, al ong with the updatin g of the
proc ess im ag e , t he C PU t ra n sm i ts th e I PC flags specifie d in DB 1
w hen the coor dinato r signals the CP U that it can access the S5 bus.
The coord in ato r al locates the b us enable s ignal to each CPU in
se qu e nc e. Wh en a C PU has ac ce ss to t he S5 bu s, it ca n tran smit o n ly
one byt e. Bec ause of this interl eaved tr an smis sion, r ela ted ( byte
grou ps) I PC flag i nform a tio n ca n be separated a n d su bs equen tly
proc e s sed with ol d or in co r r ect va lu es.
If you want t o tran sfe r inf ormatio n th a t t ak e s u p m o re th an one byt e,
you ca n prevent corruption of data b y setting a parameter in extended
data block DX 0. This parameter uses semaphores to ensure that all
IPC flag s specified in DB 1 a re tran sf erred i n groups (see Chapt er 7).
Whil e one C PU is trans mi tt in g IPC flag s, an o the r CPU ca nn o t
i nterrupt it. Because the next CPU has to wait to trans mit its data,
cyclic program processing of this CPU is delay ed accor dingly.
Multiprocessor
communication
For trans ferrin g data blocks or more exactl y fields of data wit h a size
of max. 64 byte (= 32 data words), the following spe cial functions are
int eg rated i n th e CPU:
•• OB 200: INITIALIZE: preassi gn
•• OB 202: SEND: send a data field
•• OB 203: SEND TEST: te st sen d ing c apacit y
•• OB 204: RECEIVE: receive a data f ield
•• OB 205: RECEIVE TEST: test receiving capacity
Multiprocessor Mode
CPU 928B Programming Guide
10 - 8 C79000-B8576-C898-01
10.1.4
I/O Flag Assignment and
IPC Flag Assignment in
Multiprocessor Mode (DB 1)
The I/O area of the programmable controller is available only once on
t he S5 bus. The I/O area encompasses the addresses F000H to
FFFFH.
In mult ipro ce ssor m od e, al l CPUs in t h e pro gramm able con t ro l ler
access this I/O area " simultaneously". To avoid data being
overwritten, the I/O area must be divided between the individual
CPUs.
For this purpose, you mu st pro g ra m DB 1 for every CPU. In DB 1
you de fine the inputs and outputs (byte addresses 0 to 127) and IPC
flag inputs and outputs each CPU is to work with.
If th e CPU do e s no t u se any I / O or IPC fl ag s, an (empty) DB 1 m u st
still be available in multiprocessor mode.
Note
Only the input and output bytes def ined in DB 1 will be taken into
account during updatin g of the process I/O i mage by each CPU.
10.1.5
How to Create Data Block
DB 1
Inputting o r changing DB 1
•• Create/modify DB 1 on the PG usin g the DB 1 screen form
or
•• by editing DB 1 as a data block on the PG and then transferring it
to th e CP U .
Note
The CPU evaluates the entere d or changed DB 1 only after a cold
restart!
Using the DB 1 screen form
1. Select the editor for the DB 1 screen form on your PG
(refer to Fig. 10-3).
2 . Enter the required valu es for "d igi tal inp uts" etc . as decimal
numbers.
10
Multiprocessor Mode
CPU 928B Programming G uide
C79000-B8576-C898-01 10 - 9
3. Enter the values by pressing the enter key on the PG.
The PG then generates DB 1.
4. Tra n sfer DB 1 to the CPU or l o ad i t i n to a n EPROM su bm odule.
Note
You can specify the timer field length in DX 0 and/or in the DB 1
screen form. We rec ommend that you specify this parameter only
i n DX 0 (see Chapter 7).
Ex ample of the D B 1 s c reen
form
Editing DB 1 as a data block
1. Write the DB 1 start ID in data words 0, 1 and 2:
DW 0: KH = 4D41 (’M’ ’A’)
DW 1: KH = 534B (’S’ ’K’)
DW 2: KH = 3031 (’0’ ’1’)
DB 1
0, 1, 2, 3, 7, 10,
2, 4, 12,
0,
50, 51, 60,
70, 72,100,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
I/O assignment:
Digital inputs:
Digital outputs:
IPC flag inputs:
IPC flag outputs:
Timer field length:
F ig. 10-3 PG screen for m for gener ating DB 1
Multiprocessor Mode
CPU 928B Programming Guide
10 - 10 C79000-B8576-C898-01
2. Type in the individual operand areas (from data word 3 onwards).
Be fore each operand are a, you must specify an ID. The possible ID
words are as follows:
ID word for digital inputs KH = DE00
ID word for digital outputs KH = DA00
ID word for IPC inpu t flags KH = CE00
ID word for IPC output flags KH = CA00
After each ID word, use fixed-point format to list the numbers o f the
inputs and outputs used.
3. Complete th e entries with the DB 1 en d ID "KH = EEEE" a nd
transfer DB 1 to the CPU.
Note
You can make the DB 1 entries in a ny order. Re me mber that the
process image of the inputs and outputs is updated in the reverse
order to which you store the addresses in DB 1 (i.e. th e last
e ntry is updated first).
Multiple entries of the sa me bytes (e.g., for test purposes) are
possible. The system program makes multiple updates of the process
images o f bytes that are entered more than once.
Ex ample of edi ting DB 1
DB1 FD : CP U948 ST.S 5D
0: KH = 4 D41; DW 0-2:
1: KH = 534B; Start ID
2: KH = 3031; for DB 1
3: KH = DE00; ID word for digital inputs
4: KF = +00000; Input byte 0
5: KF = +00001; Input byte 1
6: KF = +00002; Input byte 2
7: KF = +00003; Input byte 3
8: KF = +00007; .
9: KF = +00010; Input byte 10
10: KH = DA00; ID word for digital outputs
11: KF = +00000; Output byte 0
12: KF = + 0000 2; O utpu t byte 2
13: KF = +00004; .
14: KF = + 0001 2; O utpu t byte 12
15: KH = CE00; ID word for IPC flag inputs
16: KF = +00050; Flag byte 50
17: KF = +00051; .
18: KF = +00060; Flag byte 60
19: KH = CA00; ID word for IPC flag outputs
20: KF = +00070; Flag byte 70
21: KF = +00072; .
22: KF = +00100; Flag byte 100
23: KH = EEEE; End ID
24:
10
Multiprocessor Mode
CPU 928B Programming G uide
C79000-B8576-C898-01 10 - 11
Ente ring DB 1
Th e syst em program ado pts DB 1 du rin g a col d rest art. Th e system
program checks to see if the inputs and outputs or IPC f lags indicated
in DB 1 e x ist in thei r co rrespo ndi ng modules . I f the y are no t present
t here, a DB 1 error causes the CPU to go into the STOP mode and the
STOP LED fla sh es slo wl y. Th e C PU no lo n ge r proc ess es you r
program.
After you program DB 1 and the CPU accepts it during a col d restart,
the following r ules apply:
•• On ly the inputs and outputs indicated in DB 1 can access peripheral
modules via the process images (L.../T... ...IB, ...IW, ...ID, ...QB,
...QW, ...QD operations and logic operations with inputs and outputs).
Access to process image addresses not entered in DB 1 cause
addressing errors.
•• You can load peripheral bytes directly by bypassing the process
i mage using the L PY, L PW, L OY, L OW operations for all
acknowledging inputs, regardless of entries in DB 1.
•• You can transfer direct ly (T PY, T PW) to bytes 0 to 127 only for the
outputs indicated in DB 1. This is because the process image is also
written to duri ng dire ct transfer. Writing to I/O addresses not entere d
in DB 1 causes an addressing error.
•• T ransfer without a process image :
Direc t tran sf e r to byte ad d ress es >127 is possible r egardless of
th e en tr ies in DB 1.
Direc t tran sf e r of byte a dd res ses o f th e ex ten de d I /Os (T OY,
T OW) is also possible regardless of the entries in DB 1.
Multiprocessor Mode
CPU 928B Programming Guide
10 - 12 C79000-B8576-C898-01
10.2 M ultiprocessor Comm unication
Definition
Multiprocessor communication means the exchange of lar ger
a mou nts of data (data blocks) between CPUs operating in the
multiprocessor m ode. The COR 923C coordinator is necessary for
mu l tiproc ess or commun ication .
10.2.1
Introduction To t ran sfer da ta blo cks, o r to be more prec is e, blocks o f d at a wit h a
ma x imum l eng th of 64 bytes (= 32 dat a w o rds), yo u ca n us e t h e
following special f unctions that are integrated in the CPU:
•• OB 200: INITIALIZE: preassign
•• OB 202: SEND: send a field of data
•• OB 203: SEND TEST: te st sen d ing c apacit y
•• OB 204: RECEIVE: receive a data f ield
•• OB 205: RECEIVE TEST: test receiving capacity
Th e spec ia l function OB s, OB 200 a nd OB 202 to OB 205 are si mply
called "com muni cation OBs" in the fo llow ing s e ctions.
Required knowledge
To us e th ese funct ions , you only r eq u ir e ba sic knowl edge of th e
STEP 5 programming language a nd the way in whi ch S IMATIC S5
prog ram ma ble con tro llers operate. Yo u can o btai n th i s bas ic
information from the publications listed in " Further Reading".
Basic sequence
To transf er data, you must activate the SEND f unction on the
transmitting CPU and the RECEIVE f unction on the receiving CPU.
The data words of a DB or DX data block located in the transm itting
CPU are transported via the coordinator 923C to the receivi ng CPU
one after the other and written to the D B or DX da ta block wi th the
same nu mber an d under the same data word ad dress; i.e. this
represe n ts a "1: 1" copy ope rati o n.
Length of data fields
transferre d
The amount of data that can be transf erred with the SEND and
RECEIVE functions is normally 32 words.
If the block length (without header) is not a multiple of 32 words, the
last fiel d of data to be trans ferred is an exception and is less than 32
words lo ng.
10
Multiprocessor Com munication
CPU 928B Programming G uide
C79000-B8576-C898-01 10 - 13
The data block in the receiving CPU can be longer or shorter than the
data block to be sent. It is, however, i mportant that the data words
tra nsfe r re d by th e SEND fu n ct io n ex i st in t he recei vin g block ;
otherwise the RECEIVE function signals an error.
Example:
10.2.2
Ho w the Transm itter and
Receiver are Identified Ea ch fi el d of d a ta ex c ha n ged betw ee n th e CPUs is ma rke d with a
nu mber to indicate the source an d destinati on CPU.
T he CPUs are numbered so that the le ftmost CPU has the n umber 1
and e ac h su bs equ en t CPU to t he rig h t ha s a n u mber i n creased by 1.
Example
S5-135U/155U:
Data to be
sent in the
transmitting
CPU:
Data
received
in the
receiving
CPU:
Dat a bl ock:
Data word address
DB 17
DW 32 to D W 63
DB 17
DW 32 to DW 63
C
O
R
C
C
P
U
1
C
P
U
2
C
P
U
3
C
PC
PIM
..
..
IQII Q
Fig. 10-4 Sen der/receiver iden tificatio n
Multiprocessor Comm unicati o n
CPU 928B Programming Guide
10 - 14 C79000-B8576-C898-01
10.2.3
W hy Data is Buffered Ge nerally, th e multiprocessor mode is used t o distribute tasks on
several CPUs. Since the tasks are not identical and the performance of
t he CPUs invol ved can be di fferen t, the program execu tion of the
individual CPs in the m ultiprocessor mode is always asynchronous.
Thi s means th a t t h e d a ta se nt by a CPU ca nno t alw ays be recei ve d
i mmediatel y by another CPU.
For this reason, the data to be trans ferred is buffered on the
c oordinator 923 C. The number of the CPU executing the task and the
nu mber of the sender when receiving a nd the receiver when sending
def ine the source or the destination of a data field.
Example
Data transfer from CPU 3 to CPU 2:
1st step:
CPU 3 buffers its data on the coordinator.
2nd step:
When CPU 2 is ready to receive, it copies the data from the coordinator
buffer to the destination DB.
C
O
R
C
C
P
U
1
C
P
U
2
C
P
U
3
C
PC
PIM
..
..
I
SEND, parameter of receiving CPU = 2
QII Q
C
O
R
C
C
P
U
1
C
P
U
2
C
P
U
3
C
P
C
PI
M
..
..
I
RECEIVE, parameter of transmitting CPU = 3
QII Q
10
Multiprocessor Com munication
CPU 928B Programming G uide
C79000-B8576-C898-01 10 - 15
10.2.4
Ho w the Buffer i s
Pro cessed and Man aged
Principle
T he bu ffer is based on the FIFO principle (first i n - first out, queue
pri nci pl e). The da ta i s rec ei v ed i n the ord er i n wh ic h it is sent . T h is
applies to each individual link (identi fied b y the transmitting and
rec ei vi ng CPU) a n d is in d epend en t of ot h er l in k s.
D ata protection
The buffer is battery-backed; this m eans that the " automatic warm
restart foll owin g a power down " is possible without any restrictions.
A loss of power during a data trans fer d oes not cause any loss of data
in the programmable controller.
Management
T he c oordinator 923 C has a me mory capacity of 48 d ata fields eac h
with a fixed length of 32 words. The INITIALIZE f unction assigns
these fields to individual CPU links.
Each memory field can r eceiv e exactly one field of data. The l ength
of the data can be from 1 data word to 32 data words. A data fi el d is
entered in a m emory field by a SEND f unction and read out again by
a RE CEI VE functio n.
The n umber o f me mory fields assigned to a link is directly related to the
parameters for the trans mitting capacity (SEND, SEND TEST fun ction)
and receiving capacity (RECEIVE, RECEIVE TEST function).
The transmitting capac i ty indicat es how man y of the memory field s
reserved for a link are free at any particular time.
The receivin g capacity indicates how m any of the memory fields
reserved for a link are occupied at any particular time.
The sum of the transm itting and receiving capacity is always equal to
the nu mber of memor y fields reserved for a lin k.
Multiprocessor Comm unicati o n
CPU 928B Programming Guide
10 - 16 C79000-B8576-C898-01
Example
Occupation of the buffer by a link
The l ink be twee n CP U 3 an d CPU 2 is i niti aliz ed . Th e li nk is as sign ed
seven mem or y fi elds i n th e buff er o f the coor di nato r. F ol lowi ng thi s,
the data transfer shown below would be possible.
Sending/receiving n data fields means that the corresponding functions
are c alle d n ti mes on e af te r th e ot he r.
To simplify the representation, at any one time, data can either be sent
or re ce ived in th is exa mple .
It is , ho weve r, pos si ble an d usef ul t o tran smit (CP U 3) and recei ve ( CPU
2) si mult an eous ly ( "P aral le l pr oces si ng i n a mu ltip roce ss or p ro gram mabl e
controller"). In the example, fields H and I are received while fields K
and L are sent.
The example illustrates the queue organization of the buffer: the fields
of da ta s en t fi rst (A ,B,C .. .) a re r ec eive d fi rs t (A ,B,C .. .).
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
Transmitter: CPU 3
initialize
0
0
send
field A send 4 fields
B, C, D, E send 4 fields
F, G, H, I send 2 fields
K, L
Time
receive
fields A, B receive
fields C, D,
E, F, G
receive
fields H, I receive
fields K, L
Transmitting capacity
(no. of free
memory fields)
Receiving capacity
(no. of free
memory fields)
62
5
77
1
4
3722
55
Receiver: CPU 2
Fig. 10-5 Example of the occupation of the COR buffe r
10
Multiprocessor Com munication
CPU 928B Programming G uide
C79000-B8576-C898-01 10 - 17
Summary
Buf fering data on the coordinator COR 923C allows the asynchronous
ope ratio n of transmitti n g and recei vi n g CPUs and c ompensates for
t heir di fferent processing spee ds.
Since the capacity of the buf fer is lim ited, the receiver should check
"often" and "regularly" whether there are data in the buf fer
(RECEIVE TEST f unction, receiving capacity > 0) and should
attem p t to fe tch s tore d data (REC EIVE function ) . Ideally, the
RECEIVE function sh oul d be repeated until th e receivi ng capacity is
zero. This m eans that the transm itted data are not buffered f or a longer
period of time an d that the receiv er always has the curren t data. This
also means that me mory fields remain free (the trans mitting capacity
is i ncrease d) and prevents the sender from bein g blocke d (i.e. wh en
the transmitting capacity is zero).
Note
A rec eivi ng ca pa city of z ero represe nts th e id ea l state (i. e. al l
trans mitted data have been fetc he d b y the receiver), on t he ot her
hand a transm itting capacity of zero indicates incorrect
planning, as fo l low s:
- the SEND fun ct ion i s c al le d to o o ft en,
- the RECEIVE f unction is not called often enough
or
- there ar e no t enough me mory fiel ds as s ig ned to the li nk .
The capacity of the buffer is insufficient to compensate tem po-
rary imbalances in the frequenc y with which the CPUs trans-
mit and re ceive da ta.
Multiprocessor Comm unicati o n
CPU 928B Programming Guide
10 - 18 C79000-B8576-C898-01
10.2.5
System Start-Up If you require multiprocessor communication, then all CPUs in volved
m u st go thr ough the same STOP-RUN transition (= RESTART), i.e.
al l th e CPUs g o throu g h a COLD R EST A R T or a ll C PUs go th ro ug h a
WARM RESTART.
You must make sure that the restart of at least all the CPUs involved
in the communicat ion is uniform i n th e follow ing ways :
•• direct opera ti o n (fro nt sw i tc h , prog rammer ),
•• parameter assignment (DX 0)
and/or
•• programming (usin g the special function organization block OB 223
"stop if non-un iform restarts occur in the multiprocessor mo de ")
C OLD RESTAR T
In organization block OB 20 (COLD RESTART) only on e CPU must
se t up the buff er (i n the COR 92 3C) us in g th e INITI ALI Z E fu nc tion.
Any existing data is lost.
Foll ow i ng th is , i .e. during t h e RE STAR T, you c an c al l th e SEND,
SEND TEST, RE C EI VE, R EC EIVE TE ST fu nct io n s i n th e ind iv i dua l
CPUs. With appropriate progr amming, you must make sure tha t t his
only occurs a fter the buffer in the coordinator has been correctly
initialized.
On co m pletio n of th e R ESTART , i .e . in the RUN mo d e, the us er
program is pr oces se d fr om the beginnin g, i.e. from the first operation
in OB 1 or F B 0.
WARM RESTART
You mu s t not use the INITIALIZ E function in the organization
blo cks OB 21 (MA NUAL WA R M R ESTAR T) and OB 22
(AUTOMATI C WAR M RESTART). Calling the SEND, SEND
TEST, RECEIVE, RECEIVE TEST f unctions can cause problem s
( r ef e r t o the f o llow ing section s ).
On completion of the WARM RESTART, i.e. in the RUN mode, the
user program is not processed from the start, but from the p oint at
w hich it w as interru p te d. The point of interruption can, for exa mple,
be w i th i n th e SEND fun ct io n .
10
Multiprocessor Com munication
CPU 928B Programming G uide
C79000-B8576-C898-01 10 - 19
10.2.6
Calling Communication OBs
Proceed as foll ows:
1. Call the INITIALIZE f unction only in the cold restart
organizati on block OB 20 on one CPU.
2. Cal l th e SEND, SEND T EST, R E CE IVE, RE CEI VE TE ST
functions e ither only within the cyclic program or only w ithin the
time-driven program.
Double call
Depe ndi ng o n the a ssign m ent of para me te rs i n DX 0 ("in te rru pts at
ope rat io n bou n d arie s"), an d th e type o f program execu t io n (W AR M
RESTART, interr upt handling, e.g. OB 26 for cycle time error) it is
possible that one of the functions INITIALIZE, SEND, SEND TEST,
RECEIVE and RECEIVE TEST can be interrupt ed.
If a user interfa ce inserted at the point of interruption also contains one of
the functions SEND, SEND TEST, RECEIVE and RECEIVE TEST an
il leg al ca ll (double call) is rec ogni zed and an error is signalled (error
number 67, Section 10. 2.8).
Parallel processing
Once y ou have com pleted the assignment of the buffer (INITIALIZE
functio n), you can execute the functions SEND, SEND TEST,
RECEIVE and RECEIVE TEST in any combination and with any
parameter assign ment in all the CPUs simultane ousl y and parallel to
each other.
Ta kin g a sin gle l in k (e.g. fro m CPU 2 to C PU 3) it is possible to
execute the S END function ( CPU 2) and the RECEIVE funct ion
(CPU 3) s imul ta neo usly. Whil e CPU 2 i s s end ing dat a fiel ds to t h e
coo rdin at or, CPU 3 can alre ad y rec ei v e (f et ch ) buff e red d at a fi el ds
from t he coord ina tor.
Areas occupied
T he communication OBs do not require a working area (for bufferin g
variables) and do no t call data blocks. They d o, o f course, access areas
con ta ini ng para me te rs, alt h ou g h onl y th e paramet ers mark e d as ou t put
parameters are mo d ified .
Multiprocessor Comm unicati o n
CPU 928B Programming Guide
10 - 20 C79000-B8576-C898-01
Results bits
The resul ts bi ts (CC 1/CC 0, RLO e tc .) are in flu e nc ed by the
communication OBs. For more detailed inform ation ref er to
Sec tio n 10.2.8.
Changes in the ACCUs
•• CPU 922, CPU 928,
CPU 928B: T he contents of ACCU 1 to ACCU 4 and the
contents o f the registers are not a ffected by
the communication OBs.
•• CPU 946/947,
CPU 948: The contents of all reg isters and ACCU 1, 2
and 3 remain the same, only the contents o f
ACCU 4 are affected.
10.2.7
Ho w to Assig n Param e ters
to Communication OBs The communication OBs have the following types o f para meter:
•• input parameters,
•• output paramet ers
and
•• call parameters.
Input and ou tput parameters are located in a maximum 10 b yte long
d ata field in th e F flag area. Th e dat a fi el d is div id ed i n to a n area fo r
input param eter s a nd an area for output parameters.
Input paramet er s
The input parameters specify how a f unction is handled. All or part of
the param et ers are read o ut by c omm uni ca ti on OB s and ev alu at ed, no
w rite access take s place.
O utput parameters
T he output parameters cont ain all the in for matio n that the calli ng
progra m needs about the result of a job, e.g. error bits.
Some or a ll of the ou t put p ar a m e ter s ar e wri tten to by the
communicati on OBs, this area is not read.
Note
You can assign a fla g area with 10 flag b yt es fo r all
communications functions. The functions themselves require
di fferent n u mbers o f bytes. R e fer to the description o f the single
functions (Section 10.4ff).
10
Multiprocessor Com munication
CPU 928B Programming G uide
C79000-B8576-C898-01 10 - 21
Call parameters
For al l c omm uni ca tion OB s the nu m ber o f th e first flag byte i n th e
data field ( = pointer to data fiel d) i n ACC U- 1-L i s transfe r red as t he
call parameter. Permitted val ues are 0 to 246.
Example
10.2.8
Ho w to Eval uate the
Output Parameters Among ot her things, the outp ut par ame ters indicate whether or not a
function could be executed and if not they indicate the reason for the
termination of the function.
Condition codes
The INITIALIZE, SEND, SEND TEST, RECEIVE and RECEIVE
TEST functions a ffect the condition codes (see progra mming instructions
for your CPUs, general notes on the STEP 5 operations):
•• the OV and OS bits (word condition codes) are alway s cleared,
•• the OR, STA, ERAB bits (bit condition codes) are always cleared,
•• RLO, CC 1 and CC 0 indicate whether a function has been executed
correctly and c o mpletely.
Data field with parameters for the RECEIVE function
(OB 204)
FY x + 0: tran sm itti ng C PU in put pa rame te r
FY x + 1: — not used
FY x + 2: cond it ion code b yte output par am eter
FY x + 3: rece iv ing capa ci ty outp ut p ar amet er
FY x + 4: bloc k ID output par am eter
FY x + 5: bloc k numb er outp ut par amet er
FY x + 6: address of the first output parameter
FY x + 7: rece iv ed d ata wo rd outp ut p ar amet er
FY x + 8: address of the last output parameter
FY x + 9: rece iv ed d ata wo rd outp ut p ar amet er
This example illustrates that the number of the first F flag byte in the
data fiel d must not b e hi gh er t han FY 246 , si nc e ot herw is e th e para mete r
field of up to 10 bytes would exceed the limits of the flag area
(FY 255).
Multiprocessor Comm unicati o n
CPU 928B Programming Guide
10 - 22 C79000-B8576-C898-01
C ondition code s Evaluation Meaning
R LO CC 1 CC 0
0 0 0 JC= Function executed
c ompletely and correctly
1 0 0 JC= F unction a b or ted,
pointer to data field
i llegal (>246)
F u nct io n ab or ted
owi ng to an initia lizati on
conflict
101JC= and
JM= F u nctio n ab or ted
owing to an error
(error number 1 to 9)
110JC= and
JP= F u nct io n ab or ted
owi ng to a warning
(warni ng number 1 or 2)
In the following sections, it is assumed that the pointer to the data
field con ta ins a correct value. The first b yte of the output parameter
provides detailed information about the cause of termination.
Condition code byte
Bit no.76543210
WE I 0 Number
W = 1: Warning
E = 1: Error
I = 1: Initialization conflict
Number: - of a warning
- of an error
- of an initialization con flict
Table 10-1 Condition codes of the communicat ion OBs
10
Multiprocessor Com munication
CPU 928B Programming G uide
C79000-B8576-C898-01 10 - 23
The first b yte in the field of the output parameters (condition code
by te) also indicates whether or not a function has been correctly and
completely executed. This by te contains detailed inform ation about
the cause of term ination of a function.
Assu ming that at least the pointer to the data field contains a correct
value, this byte is always relevant.
If the function has been executed correctly and completely, all the bits
are cl ea red (= 0), an d al l oth er o u tpu t para me te rs a re relev a nt.
If the function is aborted with a warning (bit number 7 = 1), only the
condition code for the transmitting/receiving capacity is relevant,
other output parameters (if they exist) are uncha nged.
If the fu n ction is aborted owin g to an erro r (bit number 6 = 1) or an
in i ti aliz atio n con fli ct (bit num be r 5 = 1), al l o t he r o ut put parame te rs
rem ain unchanged.
Evaluat ion of the code byte
The id e ntifi ers ’W’, ’E ’ an d ’I ’ ind ic at e th e sig nifi ca nce of t h e
numbers.
Apart from this bit-by- bit eval u atio n , i t is a ls o poss ible t o in te r pre t t he
who le c ondition code b yte as a fixed point number wit hout sign. If
yo u interpret the co ndi tion code b yte as a byte, the groups of nu mbers
have the following significance:
N umb e r group S ign ificance
0
33 to 42
65 t o 73
129 to 130
Functi on executed correct ly a nd completely
F u n ction ab or ted owin g to an initializatio n
conflict
Funct ion abo rte d owi ng to a n error
Function aborted owing to a warning
Errors are detected and indicated in the ascending order of the error
nu mbers. This means that several errors may have occurred although
(currently) only one is indicated. The other errors are then indicated by
further calls.
Table 10-2 C ode byte for the communication OBs/number gr oups
Multiprocessor Comm unicati o n
CPU 928B Programming Guide
10 - 24 C79000-B8576-C898-01
Example
Initialization conf lict
A n initia liza tion conf lic t can only occur with the INIT IA L IZATIO N
function. If a co nflict occurs, you must modi fy th e progra m or the
parameters.
Initial izat io n conf lict n umbers (eval uatio n of t he c ond i tion c ode byte
as a byte):
Cond.
code
byte
Significance
33 T h e pa g e s requ i re d for m ult i proc es so r c omm u ni c at i on
(num be rs 252 to 255) are not o r not all av ailable.
34 The pages required for multiprocessor communicatio n
(numbers 252 to 255) are de f ec ti ve.
35 The parameter "automatic/manual" is illegal.
The following errors are possible :
- the "automatic/ manual " ID is less than 1,
- the "automatic/ manual " ID is greater than 2.
36 The para mete r " number o f CPUs" is illegal.
The foll ow i ng errors are poss ible:
- t h e nu mbe r of C PUs is less t h an 2,
- t h e nu mbe r of C PUs is great er than 4.
37 The parameter "block ID " is illegal.
The following errors are possible :
- the block ID is less than 1,
- the block ID is greater than 2.
38 The parameter "block nu mber" is incorrect, since it is a data
block with a special significance.
The following errors are possible :
- i f block ID = 1 DB 0, DB 1, DB 2
- if block ID = 2 : DX 0, DX 1, DX 2
39 The parameter "block nu mber " is incorrect, since the data
block does not exist.
40 The parameter "start address o f the assignment list " is to o
high or the data block is too short.
The SEND function indicates an error and is not
execu ted. I f yo u th en mak e prog ram an d/or
parameter modifications and the SEND function
again indicates an error with a higher number
than prev io usly , yo u can as sume tha t you have
corrected one of several errors.
Table 10-3 Cond ition code byte: Initialization conflict numbers
10
Multiprocessor Com munication
CPU 928B Programming G uide
C79000-B8576-C898-01 10 - 25
Cond.
code
byte
Significance
Table 10-3 continued:
41 The assignment list in the data block is not correctly
structured.
42 The sum of the assigned m em ory f ields is greater than 48.
Errors
If an e rro r occ urs, you must ch an ge th e prog ra m/ paramet ers.
Error n umbers (evaluati on of the condition code byte as a b yte):
Cond.
code
byte
Significance
65 The parameter "r eceiving CPU" ( SEND, SEND TEST)
is illegal. The following errors are possible:
- The number of the receiving CPU is greater than 4,
- the number of the receiving CPU is less than 1,
- the number of the receiving CPU is the same as the
CPU’s ow n number.
66 The parameter "transmitting CPU" (RECEIVE, RECEIVE
TES T) is illegal. The follo wing errors are possible:
- The n u mber of the transmitting CPU is gre ater than 4,
- the nu mber of the transmitting CPU is less than 1,
- the nu mber o f the transmitting CPU is the sa me as the
CPU’s own nu mber.
67 The special function organization bl ock call is wro ng
(SEND, RECEIVE, SEND TEST, RECEIVE TEST). The
fo llowi n g errors are possible:
- Secondary error, since the INITIALIZE function could
not be called or was term in ated by an initialization
conflict.
- Double call: the call for this function (SEND, SEND
T ES T , R E C E I V E or RECEIVE TEST) is illegal,
since one of these functions IN ITI ALIZE, SEND,
SEND TEST, RECEIVE or RECEIVE TEST has
a lrea d y been c al le d in th is CPU in a lo we r
processing level (i.e. cyclic program exec ution).
- The CPU’s own nu mber is in correct (s ystem data
corrupted); following power down/power up the CPU
number is generated again by the syste m program.
T able 10 -4 C ondition code byte : Error n u m ber s
Multiprocessor Comm unicati o n
CPU 928B Programming Guide
10 - 26 C79000-B8576-C898-01
Cond.
code
byte
Significance
Table 10-4 continued:
68 The m anagement data (queue managem ent) of the
selected links are incorrect; set up the buf fer in the
coordinator 923C again using the INITIALIZE f unction
(SEND, RECEI VE, SEND TEST, R ECE IVE T E ST).
69 The parameter "block ID " (SEND) or the block ID provi ded
by the sender (RECEIVE) is illegal. The following errors are
possible:
- The block ID is less than 1,
- the block ID is greater than 2.
70 The parameter "block nu mber" (SEND) or the block n u mber
supplied by the sender (RECEIVE) is illegal, since it is a data
block with a special significance. The following errors are
possible:
- I f the block ID = 1 : DB 0, DB 1, DB 2
- i f the block ID = 2 : DX 0, DX 1, DX 2
71 The parameter "block nu mber" (SEND) or the block n u mber
provided by the sender (RECEIVE) is incorrect. The
specified data block does not exist.
72 The parameter "field nu mber" (SEND) is incorrect.
The data block is too short or the field number too high.
73 The data block is not large enough to receive the data field
transmitted by the sender (RECEIVE).
10
Multiprocessor Com munication
CPU 928B Programming G uide
C79000-B8576-C898-01 10 - 27
Warning
The f unction could not be executed; the f unction call must be
repeated, e.g. in t he n ext cycle.
Warning numbers (evaluation of the condition code byte as a by te):
Cond.
code
byte
Significance
129 T he SEND function cann ot trans fer data, since the
transmitting capacity was already zero when the
function was called.
130 The RECEIVE function cannot accept data, since the
receiving capacity was already zero when the function
was called.
Table 10-5 Condit ion code bytes: Warning numbers
Multiprocessor Comm unicati o n
CPU 928B Programming Guide
10 - 28 C79000-B8576-C898-01
10 .3 Ru nt im e s of th e Co m mun ic ation OB s
The " runtim e" is the processing time of the special f unction
organization blocks; the time f rom calling a block to its termination
can be m uch greater if it is interrupted by higher priority activities
(e.g . updat in g t im ers, et c.).
Special function OB
Block
name C PU 922 C PU 928 C PU 928 B CPU 946/
947 C PU 948
OB 200 /
initialize 230 ms 130 ms 130 ms 128 ms 90 ms
OB 202 /
send 806 µs (294 µs
basic time
+ 16 µs/word);
118 µs if a
w ar n i ng occurs
666 µs (250 µs
basic time
+ 13 µs/word);
115 µs if a
w a r ning occur s
696 µs (280 µ s
basic time
+ 13 µs/word);
145 µs if a
warning occurs
762 µs (426 µ s
basic time
+ 21 µs/
double word);
243 µs if a
w ar n ing occur s
542 µs ( 220 µs
basic ti me
+ 19 µs/
d oubl e w ord );
110 µs if a
w ar n i ng occurs
OB 203/ sen d t est 72 µs50 µs80 µs 207µs115 µs
OB 204/ receive 825 µs (281 µs
basic ti me
+ 17 µs/word);
115 µs if a
w ar n i ng occurs
660 µs (244 µs
basic ti me
+ 13 µs/word);
98 µs i f a
w a r ning occur s
690 µs (274 µs
basic time
+ 13 µs/word);
128 µs i f a
warning occurs
772 µs (42 1 µs
basi c time
+ 22 µs/
double word);
243 µs if a
w ar n ing occur s
506 µs ( 218 µs
basic ti me
+ 18 µs/
d oubl e w ord );
132 µs if a
w ar n i ng occurs
OB 205 /
receive test 70 µs48 µs78 µs 223 µs120 µs
Th e runt imes li sted in T abl e 10-6 assume th at of four C PUs inserted
in a rack, only the CPU whose runtimes are being measured accesses
t he SIMAT IC S5 bus. If other CPUs use the bus intensi vely, the
runti me increases particularly for the send/receive functions.
Table 10-6 Runtimes of the communication OBs
10
Runtim es of the Com municati on O B s
CPU 928B Programming G uide
C79000-B8576-C898-01 10 - 29
Transfer time
An im portant fact o r of a l in k (e.g. fro m CPU 1 to C PU 2) is the to t al
data transf er tim e. This is m ade up of the f ollowing components:
•• time required to se n d (see run t ime),
•• le n gth of ti me the d ata a re bu f fered (o n th e COR 923C coordi nato r)
and
•• the time required to receive data (see runtime)
T he length of time that the data are "in transit" is largel y
dependent on the len gth of tim e that the data is buffered an d
therefore on the str ucture of the user program (see "Bu ffering
D a ta").
Runtimes of the Comm unication O B s
CPU 928B Programming Guide
10 - 30 C79000-B8576-C898-01
10.4 INITIALIZE Function (OB 200)
10.4.1
Function To t ransf er da ta from o ne C PU t o ano ther CPU, th e data mus t be
temporarily buffered. The INITIALIZE function sets up a buffer on
the COR 923C coordinator.
The memory is initialized in fields with a f ixed length of 32 words.
Each m emory field accepts one data field with a length between 1 data
word and 32 data w ords. A data field is entered in a memory field by a
SEND function and read out by a RECEIVE function.
If you are using two CPUs, there are tw o links (transfer directions,
"channels"):
If you are using three CPUs, there are six links:
CPU 1 CPU 2
CPU 2
CPU 3
CPU 1
10
INIT IALI ZE F unction ( O B 200)
CPU 928B Programming G uide
C79000-B8576-C898-01 10 - 31
If you are u sing fou r CPUs, t he re are tw elve links:
The INITIALIZE function specifies how the total o f 48 available
memory fields are assigned to the max imum twelve links.
This means that each possible link, specified by the para meters
"transmitting CPU" and "receiving CPU" has a certain memory capacity
available.
Note
Before you can call the SEND / RECEIVE / SEND TEST /
RECEIVE TEST func tions, one CPU must have alrea dy called the
INITIALIZE function and executed it completely and without errors.
If the INITIALIZE function is called several times, one af ter the
oth er, th e last assign me nt mad e is vali d . Whi le a CPU is pro ce ssing
the INITIALIZE f unction, no other m ultiprocessor communication
functions including the INITIALIZE f unction can be called on other
CPUs.
CPU 3 CPU 4
CPU 1 CPU 2
INIT IALI ZE F unction ( O B 200)
CPU 928B Programming Guide
10 - 32 C79000-B8576-C898-01
10.4.2
Call Param eters
St ructu re of the (parameter)
data field
Be fore calling OB 200, you must supply the input parameters in the
data f ield. OB 200 requires eight F flag bytes in the data field f or
i nput and output parameters:
FY x + 0: Mode (automatic/
manual ) inp ut p arameter
FY x + 1: Number of CPUs i nput parameter
F Y x + 2: Block ID input p arameter
F Y x + 3: Block number input param e ter
FY x + 4: Start address of the i nput parameter
F Y x + 5: as signment lis t
FY x + 6: Condit ion c ode byt e outpu t parameter
FY x + 7: Total capacity output parameter
ACCU-1-L
Whe n OB 200 is called, you transfer th e flag byte n umber at which
the parameter data field begins to ACCU-1-L:
ACCU-1-LH: 0
ACCU-1-LL: 0 to 246
10.4.3
Inpu t Parameters
Mo de (au tom atic/ m anu a l)
M ode = 1: automati c
Mode = 2: manual
M o de = 0 or 3 to 255 : ill egal , causes an
in itialization con flict
Num ber of CPUs
This para me te r is on l y relev ant when you h ave select ed the
" automa tic" mode. Wi th the "au tom atic" s e tting, t he memory fi elds
a r e divi de d evenly acc ordi ng to the number of CPUs.
Number of
CPUs Number of
links M e m o ry fields pe r
link
2
3
4
2
6
12
24
8
4
0; 1; 5 to 255 Illegal, causes an initialization conflict
10
INIT IALI ZE F unction ( O B 200)
CPU 928B Programming G uide
C79000-B8576-C898-01 10 - 33
Block ID, block number,
address assignm ent list
The param et ers are onl y relev an t if you selec t the "ma nua l" mo de.
Yo u must th e n crea te a n ass ig nme nt l ist in a d a ta block i n whic h the
48 a vailable memor y fields (or less) are assigned to the maximum 12
links. This function is particularly useful when so me CPUs transfer
more data t ha n o thers.
T he CPUs not involved in the multiprocessor communication do not
need and should not have memory f ields assigned to them .
T he parameters
•• block ID,
•• b l ock num b er
and
•• st art ad d ress of t he a ssignment li st
speci fy where the assignment list is stored.
Block ID
ID = 1: DB data block
ID = 2: DX data block
ID = 0 or 3 to 255 : illegal, causes an
in itialization con flict
B lock nu mber
For th e block n umber, you speci fy t he numbe r of th e DB o r DX d a ta
block in which the assignment list is stored.
Start address of th e
assignm ent list
Along with the block ID and number, this specifies the area (or m ore
precisely, the start address of the area) in the data block in which the
assi gn ment li st is stored.
As the address of the assig nment list, speci fy th e data wor d number at
which the assignment list begins in f lag by tes FY x+4 (high by te) and
FY x+5 (lo w byte).
INIT IALI ZE F unction ( O B 200)
CPU 928B Programming Guide
10 - 34 C79000-B8576-C898-01
Assign m ent lis t
With the assignment list, you specify how many of the existing 48
memory fields are to be assigned to the links.
The list is n ot chan g ed by the system program. It has the following
structure.
Data word Format Value Significance
DW n + 0
DW n + 1
DW n + 2
DW n + 3
KS
KY
KY
KY
S1
2 , a
3 , b
4 , c
T ran smitte r = CPU 1
Re ce iv er = CPU 2
Re ce iv er = CPU 3
Re ce iv er = CPU 4
DW n + 4
DW n + 5
DW n + 6
DW n + 7
KS
KY
KY
KY
S2
1 , d
3 , e
4 , f
T ran smitte r = CPU 2
Re ce iv er = CPU 1
Re ce iv er = CPU 3
Re ce iv er = CPU 4
DW n + 8
DW n + 9
DW n + 10
DW n + 11
KS
KY
KY
KY
S3
1 , g
2 , h
4 , i
T ran smitte r = CPU 3
Re ce iv er = CPU 1
Re ce iv er = CPU 2
Re ce iv er = CPU 4
DW n + 12
DW n + 13
DW n + 14
DW n + 15
KS
KY
KY
KY
S4
1 , k
2 , l
3 , m
T ran smitte r = CPU 4
Re ce iv er = CPU 1
Re ce iv er = CPU 2
Re ce iv er = CPU 3
Instead o f the lower case letters a to m (in bold face) nu mbers between 0
and 48 must be inserted depending on the number o f assigned memory
fields. Th e su m of these n umb ers m u st not exceed 48.
Note
You must keep to the structure shown in Table 10-7 even i f you have
less than four CPUs .
Table 10-7 Assignment list for OB 200 ( initialize)
10
INIT IALI ZE F unction ( O B 200)
CPU 928B Programming G uide
C79000-B8576-C898-01 10 - 35
Example
10.4.4
Output Parameters
Condition code byte
T his byt e i nforms you wheth er the INI TIALIZ E fun ct ion was
e xecuted correctly and comple tely.
Initialization conf lict
The initialization co n flicts listed are recognized and indicated by the
function in the ascending order of their n u mbers.
If an initialization conflict occurs, you must change the
progra m/parameters.
All the numbers l isted in the followi ng table can occur in the
conditio n co de byte.
You have three CPUs in your rack, CPU 2 sends a lot of data to the other
two CPUs. The other two CPUs, however, only send a small amount of data
back to C PU 2 a s ac kn owle dg emen ts i n a lo gica l hand shak e. The re is no
dat a exchan ge between CPU 1 and CPU 3.
The assignment list is stored in data block DB 40 from DW 0 onwards and
has the following parameters:
DB40 FD: CPU928ST.S5D
0: KS = S 1; T rans mitt er : CP U 1
1: KY = 2,2; Receiver: CPU 2/2 fields
2: KY = 3,0; Recei ver: CPU 3/ no f ield
3: KY = 4,0; Recei ve r: CPU 4 (d oe s not ex ist) /n o fiel d
4: KS = S 2; T rans mitt er : CPU 2
5: KY = 1,22; Receive r: CPU 1/ 22 fie lds
6: KY = 3,22;Receiver: CPU 3/22 fields
7: KY = 4,0; Rec ei ver: CPU 4 (d oe s not ex ist) /n o fiel d
8: KS = S 3; T rans mitt er : CPU 3
9: KY = 1,0; Recei ver: CPU 1/ no f ield
10: KY = 2,2;Receiver: CPU 2/2 fields
11: KY = 4,0; Rec eive r: CPU 4 (d oes no t ex ist) /no fi el d
12: KS = S 4; T rans mitt er : CPU 4 (doe s not exis t)
13: KY = 1,0; Rec eive r: CPU 1/no fie ld
14: KY = 2,0; Receiver: CPU 2/no field
15: KY = 3,0; Receiver: CPU 3/no field
16:
INIT IALI ZE F unction ( O B 200)
CPU 928B Programming Guide
10 - 36 C79000-B8576-C898-01
Cond.
code
byte
Significance
33 T h e pa g e s requ i re d for m ult i proc es so r c omm u ni c at i on
(num be rs 252 to 255) are not o r not all av ailable.
34 The pages required for multiprocessor communicatio n
(numbers 252 to 255) are de f ec ti ve.
35 The parameter "automatic/manual" is illegal.
The following errors are possible :
- the "automatic/ manual " ID is less than 1,
- the "automatic/ manual " ID is greater than 2.
36 The para mete r " number o f CPUs" is illegal.
The foll ow i ng errors are poss ible:
- t h e nu mbe r of C PUs is less t h an 2,
- t h e nu mbe r of C PUs is great er than 4.
37 The parameter "block ID " is illegal.
The following errors are possible :
- the block ID is less than 1,
- the block ID is greater than 2.
38 The parameter "block nu mber" is incorrect, since it is a data
block with a special significance.
The following errors are possible :
- i f block ID = 1 DB 0, DB 1, DB 2
- if block ID = 2 : DX 0, DX 1, DX 2
39 The parameter "block nu mber " is incorrect, since the data
block does not exist.
40 The parameter "start address o f the assignment list " is to o
high or the data block is too short.
41 The assignment list in the data block is not correctly
structured.
42 The sum of the assigned m em ory f ields is greater than 48.
Errors
The "erro r" numbe r gro up ca nnot occur with t he I NITIALIZ E
function.
Warning
The "warn ing" numbe r group cannot occu r with the I NITIALI ZE
function.
Total capacity
Thi s para mete r specifies ho w man y of the 48 av ai lable memory fiel d s
a re a ssi gn ed to links.
In the "automatic" mode, this para meter always has the value 48. In the
"manual " mode, it can have a value less than 48. This means that existin g
memory capacity is not used.
10
INIT IALI ZE F unction ( O B 200)
CPU 928B Programming G uide
C79000-B8576-C898-01 10 - 37
10.5 S END F unction (OB 202)
10.5.1
Function T he SEND function transfers a data field t o the buffer of the
COR 923C co o rdi n at or. It a lso i n di ca te s h o w man y dat a fields can
still be sent or buffered.
10.5.2
Call Param eters
St ructu re of the (parameter)
data field
Be fore calling O B 202 you must speci fy the input para meters in the data
field. OB 202 requires six F flag bytes in the data field for input and
output para meters:
F Y x + 0: receiving CPU inp ut parameter
F Y x + 1: block ID inp ut p arameter
F Y x + 2: block number inp ut parameter
FY x + 3: field n umber input parameter
FY x + 4: con ditio n code byte output parameter
FY x + 5: trans mitting capacity output parameter
ACCU-1-L
When OB 202 is called, transfer t he flag byte at which the parameter
data field begins to ACCU-1-L:
ACCU-1-LH: 0
ACCU-1-LL: 0 to 246
10.5.3
Inp ut Par am e ter s
Receiving CP U
CPU number of the receiver (d estination); the permitted value is between
1 and 4 but must be di fferent from the CPU’s o wn n u mber.
SE ND F unction (OB 202)
CPU 928B Programming Guide
10 - 38 C79000-B8576-C898-01
Block ID
ID = 1: DB data block
ID = 2: DX data block
ID = 0 or 3 to 255: illegal, causes an
error message
Block numb e r
The block number, along with the block ID a nd the field nu mb er
spec ifi es the area from w hic h the d at a t o be s en t is take n (an d wh ere it
is to be stored in the receiving CPU).
Remem ber that certain data blocks have a special significance, for
exa mple, DB 0, DB 1 or DX 0 (see programming i nstruct io n s for you r
CPUs). These data blocks must therefo re n o t be use d fo r the d ata
transfer described here!
If you a tt em pt t o us e t h ese bloc k nu m be rs, t h e fun ct ion is aborted wit h
an error message.
F ield num b er
T he fiel d number indicates the area in which the data to be sent is
located.
F ield
number Data area
F irst data wor d L ast data w ord
0
1
2
3
4
5
6
7
8
9
:
:
D W 0
DW 32
DW 64
DW 96
DW 128
DW 160
DW 192
DW 224
DW 256
DW 288
:
:
DW 31
DW 63
DW 95
DW 1 27
DW 1 59
DW 1 91
DW 2 23
DW 2 55
DW 2 87
DW 3 19
:
:
10
SE ND Function (O B 202)
CPU 928B Programming G uide
C79000-B8576-C898-01 10 - 39
The followin g situations are possible:
•• DB is longer than sourc e area:
If th e da ta block is suff ici en tly long, you ob t ain a 32- w o r d long
area per field as sho wn in the table above.
•• DB is too sho rt:
If the end of the data block is within the selected field, in the last
field an area with a length between 1 and 32 words will be
transferred.
•• Field is outside the DB:
If the first data word address of a f ield is not within the length of
th e data blo c k, th e SEND funct io n detec ts an d i ndi cate s a n error.
Example
10.5.4
Output Parameters
Condition code byte
This byte i n forms you whether the SEND function was executed
correctly and completely.
Initialization conf lict
Has no significance with the SEND function.
Data bloc k with a l en gth of 80 word s: DW 0 to
DW 74 , 5 wo rds are re quir ed for the b lock
header.
Field no.: First Last Length:
data word: data word:
0 DW 0 DW 31 32 words
1 DW 32 DW 63 32 words
2 DW 64 DW 74 11 words
3 and
hig he r Inco rrec t pa rame ter as si gnme nt
SE ND F unction (OB 202)
CPU 928B Programming Guide
10 - 40 C79000-B8576-C898-01
Errors
When t h e SE ND fu nc ti o n is ca ll ed , t h e foll o win g erro r nu m be rs
(evaluation of the condition code byte) can occur:
Condition
code byte Significance
6 5 T h e pa r a m eter "r eceiving CPU" is illegal.
The following errors are possible:
- Th e nu mber of the receiving CPU is gr eat er than 4
- The number of the receiving CPU is less than 1
- Th e nu mber of th e receiving CPU is the same as
the CPU’s own number.
67 The special f unction organization block call is wrong.
The following errors are possible:
- Se con d ary erro r, sinc e the INIT IAL I ZE fun c ti on
could not be called or was terminated by an
initialization con flict.
- Double call: the call for this function, SEND, SEND
TEST, RECEIVE or RECEIVE TEST is illegal,
sinc e on e of t he f uncti ons INI TI ALIZE, S EN D,
SEND TEST, RECEIVE or RECEIVE TEST has
alr ead y b een c all e d i n t h is C P U in a l o wer pr o ces si n g
level (e.g. cyclic program processing).
- The CPU’s own number is incorrect (system data
corrupted)
following power down/power up the CPU number
is generated again by the system program.
68 The mana gemen t data (queue manage ment) of the
s elec te d li nk s are inco rrec t; se t up t he bu ffe r in
the coordinator 923C again using the INITIALIZE
function.
69 The parameter "block ID" is illegal.
The following errors are possible:
- The block ID is less than 1,
- the block ID is greater than 2.
70 The parameter "block number" is illegal, since it is a data
block with a special significance.
The following errors are possible:
- I f the block ID = 1 : DB 0, DB 1, DB 2
- I f the block ID = 2 : DX 0, DX 1, DX 2
71 The parameter "block number" is incorrect.
The specified data block does not exist.
72 The parameter "field n u mber" is incorrect. The data
block is too short or the field n u mber too high.
10
SE ND Function (O B 202)
CPU 928B Programming G uide
C79000-B8576-C898-01 10 - 41
Warning
The f unction could be executed; the function call must be repeated,
e .g. i n th e next cy cle.
The f ollowing warning numbers (evaluation of the condition code
byte) can occur:
Condition
code byte Significance
129 Th e SEND func ti o n ca nn o t tran sfe r data , sin ce t he
trans mittin g capacity was already zero when the
func ti on was calle d.
Tran sm ittin g capacity
The " transmitting capacity" indicates how m any data fields can still
be sent and buf fered.
SE ND F unction (OB 202)
CPU 928B Programming Guide
10 - 42 C79000-B8576-C898-01
10.6 S END T EST Function (OB 203)
10.6.1
Function The SEND TE ST fu nct io n d et erm i nes th e nu m be r o f free mem o ry
fiel ds in the b uff e r of the COR 923 C coor dina to r.
Depe nd i ng o n t hi s n umber m, th e SEND fun ct ion can be cal le d m
time s to transfer m d ata fields.
10.6.2
Call Param eters
St ructu re of the (parameter)
data field
Be fore calling OB 203, you must speci fy th e input parameters in the
data f ield. OB 203 requires 4 F flag by tes in the data f ield for input
a nd output parameters:
F Y x + 0: receiving CPU inp ut parameter
F Y x + 1: — not used
FY x + 2: con ditio n code byte output parameter
FY x + 3: trans mitting capacity output parameter
ACCU-1-L
When OB 203 is ca ll ed, tran sf e r th e flag byte n umber at whi ch t he
parameter data field begins to ACCU-1-L:
ACCU-1-LH: 0
ACCU-1-LL: 0 to 246
10.6.3
Inp ut Par am e ter s
Receiving CP U
T he CPU’s own number and th e number of the receivi ng CPU
identify the li nk for which th e transmitting capacity is determined.
10.6.4
Output Parameters
Condition code byte
This byte indicates whether the SEND TEST function was executed
correctly and completely.
10
SEND TEST Function (OB 203)
CPU 928B Programming G uide
C79000-B8576-C898-01 10 - 43
Initialization conf lict
Has no significance for the SEND TEST function.
Errors
When c al li ng th e SEND T EST fu ncti on, the follow ing e r ror n umbers
(evaluation of the condition code byte) can occur:
Condition
code byte Significance
6 5 T h e pa r a m eter "r eceiving CPU" is illegal.
The following errors are possible:
- Th e nu mber of the receiving CPU is gr eat er than 4,
- The number of the receiving CPU is less than 1,
- Th e nu mber of th e receiving CPU is the same as
the CPU’s own number.
67 The special f unction organization block call is wrong.
The following errors are possible:
- Se con d ary erro r, sinc e the INIT IAL I ZE fun c ti on
could not be called or was terminated by an
initialization con flict.
- Double call: the call for this function, SEND, SEND
TEST, RECEIVE or RECEIVE TEST is illegal,
sinc e on e of t he f uncti ons INI TI ALIZE, S EN D,
SEND TEST, RECEIVE or RECEIVE TEST has
alr ead y b een c all e d i n t h is C P U in a l o wer pr o ces si n g
level (e.g. cyclic program processing).
- The CPU’s own number is incorrect (system data
corrupted);
following power down/power up the CPU number
is generated again by the system program.
68 The mana gemen t data (queue manage ment) of the
s elec te d li nk s are inco rrec t; se t up t he bu ffe r in
the coordinator 923C again using the INITIALIZE
function.
Warning
The "warning" number group cannot occur with the SEND TEST
function.
Tran sm ittin g capacity
The "transmitting capacity" parameter indicates how many data fields
can be sent and buf fered.
SE ND TE ST Function (OB 203)
CPU 928B Programming Guide
10 - 44 C79000-B8576-C898-01
10.7 R E CEIVE Function (O B 204)
10.7.1
Function The RECEIVE f unction takes a data f ield from the buffer of the
COR 923C co ordinat or. It a lso i n dica te s h o w man y data fi el ds are stil l
buffered and can still be received.
The RECEIVE f unction should be called in a loop until all the
buff ered da ta fie lds ha ve been rec ei v ed.
10.7.2
Call Param eters
St ructu re of the (parameter)
data field
Be fore calling OB 204, you must speci fy th e input parameters in the
data f ield. OB 204 requires 10 F f lag bytes in the data f ield f or input
a nd output parameters:
F Y x + 0: transmitting CPU input parameter
F Y x + 1: — not used
FY x + 2: con ditio n code byte ou tput parameter
FY x + 3: receiving capacity ou tput parameter
FY x + 4: block ID ou tput parameter
FY x + 5: block nu mber output parameter
FY x + 6: address of the first ou tput parameter
FY x + 7: receive d data word output parameter
FY x + 8: address of th e last output parameter
F Y x + 9: received da ta wo rd
ACCU-1-L
When c al li ng OB 204, t ran sfer t h e fl ag byte number at whi ch t he
parameter data field begins to ACCU-1-L:
ACCU-1-LH: 0
ACCU-1-LL: 0 to 246
10.7.3
Inp ut Par am e ter s
Transmitting CPU
The receive block receives data supplied by the transmitting CPU.
Specify the n umber o f the transmitting CPU. The permitted value is
between 1 and 4, but must be di fferent fro m the C PU’s own nu mber.
10
RE CEIVE F unction (OB 204)
CPU 928B Programming G uide
C79000-B8576-C898-01 10 - 45
10.7.4
Output Parameters
Condition code byte
This byte info rms you wh ether the RECEIV E function was executed
correctly and co mpletel y .
Initialization conf lict
Has no significance with the RECEIVE function.
Errors
When c al li ng th e REC EIVE fun ctio n t he fo ll ow i ng error n u mbe rs
(evaluation of the condition code byte) can occur:
Condition
code byte Significance
66 The parameter "transmitting CPU" is illegal.
The following errors are possible:
- Th e nu mber of th e transmitting CPU is gr eat er
tha n 4,
- Th e nu mber of th e tr ansmitting CPU is less than 1 ,
- Th e nu mber of the tr ansmitting CPU is the same
as the CPU’s own number.
67 The special f unction organization block call is wrong.
The following errors are possible:
- Se con d ary erro r, sinc e the INIT IAL I ZE fun c ti on
could not be called or was terminated by an
initialization con flict.
- Double call: the call for this function, SEND, SEND
TEST, RECEIVE or RECEIVE TEST is illegal,
sinc e on e of t he f uncti ons INI TI ALIZE, S EN D,
SEND TEST, RECEIVE or RECEIVE TEST has
alr ead y b een c all e d i n t h is C P U in a l o wer pr o ces si n g
level (e.g. cyclic program processing).
- The CPU’s own number is incorrect (system data
corrupted)
following power down/power up the CPU number
is generated again by the system program.
68 The mana gemen t data (queue manage ment) of the
s elec te d li nk s are inco rrec t; se t up t he bu ffe r in
the coordinator 923C again using the INITIALIZE
function.
69 The block identifiers supplied by the transmitter are
illegal.
The following errors are possible:
- The block ID is less than 1,
- The block ID is greater than 2.
RE CEIVE F unction ( OB 204)
CPU 928B Programming Guide
10 - 46 C79000-B8576-C898-01
Condition
code byte Significance
Error numbers continued:
70 The block nu mber supplied by the transmitter is illegal,
since it is a data block with a special significance.
The following errors are possible:
- I f the block ID = 1 : DB 0, DB 1, DB 2
- I f the block ID = 2 : DX 0, DX 1, DX 2
71 The blo ck number provided by the transmitter is
incorrect. The specified data block does not exist.
73 The data block is too small to receive the data field
supplied by the tr ansmitter.
Warning
The f unction could not be executed; the f unction call must be
repeated, e.g. in t he n ext cycle.
The f ollowing warning number (evaluation of the condition code
byte) can occur:
Condition
code byte Significance
130 The RECEIVE function cannot receive data, since
the receiving capacity was already zero when the
function was called.
Receivin g capacity
The " receiving capacity" parameter indicates how many data f ields
are sti ll buffered and can still be received.
10
RE CEIVE F unction (OB 204)
CPU 928B Programming G uide
C79000-B8576-C898-01 10 - 47
Block ID:
ID = 1: DB data block
ID = 2: DX data block
ID = 0 or 3 to 255: illegal, causes an
error message
Block numb e r
Block number o f the DB/DX in which th e received data are stored
(and f rom which they are taken by the SEND function in the
transmitting CPU).
Remember that the receive data blocks must be in a random access
memory, using read-only memories (EPROM) might possibl y serve a
practical purpose for tra n s mit data blocks only.
Address of the first
received data word
Dat a word n umber wi th i n th e DB/ DX in which t h e first
transferred/received data word was stored.
Address of the last
received data word
Dat a word n umber wi th i n th e DB/ DX in which t h e l as t
transferred/received data word was stored.
Note
Th e di f feren ce bet wee n the add ress es of t h e fi rst a n d la st da ta
word transf erred is a maxim um of 31, since a m aximum of 32
data words can be transferred per function call.
RE CEIVE F unction ( OB 204)
CPU 928B Programming Guide
10 - 48 C79000-B8576-C898-01
10.8 R E CEIVE TEST Function (OB 205)
10.8.1
Function T he RECE IVE TEST function determines the nu mber of occupie d
memor y fields in the buffer of the COR 923C coordinator. Depending
on this n umber m, t he R EC E IVE func ti o n can be c al le d m t imes to
receive m data fields.
10.8.2
Call Param eters
St ructu re of the (parameter)
data field
Be fore calling OB 205, you must speci fy th e input parameters in the
data f ield. OB 205 requires 4 F flag by tes in the data f ield for input
a nd output parameters:
F Y x + 0: transmitting CPU input parameter
F Y x + 1: — not used
FY x + 2: con ditio n code byte ou tput parameter
FY x + 3: receiving capacity ou tput parameter
ACCU-1-L
When c al li ng OB 204, t ran sfer t h e fl ag byte number at whi ch t he
parameter data field begins to ACCU-1-L:
ACCU-1-LH: 0
ACCU-1-LL: 0 to 246
10.8.3
Inp ut Par am e ter s
Transmitting CPU
The CPU’s o wn n u mber and the nu mber of the tran smitting CPU identi fy
the link for which the receiving capacity is determined.
10.8.4
Output Parameters
Condition code byte
This byte indicates whether the RECEIVE TEST function was executed
correctly and completely.
Initialization conf lict
Has no significance with the RECEIVE TEST function.
10
RE CEIVE T EST F unction ( OB 205)
CPU 928B Programming G uide
C79000-B8576-C898-01 10 - 49
Errors
When c al lin g the REC EI VE TEST fun ctio n, t he foll ow i ng error
nu mbers (evaluation of the co ndition code byte) ca n occ ur:
Condition
code byte Significance
66 The parameter "transmitting CPU" is illegal.
The following errors are possible:
- Th e nu mber of th e transmitting CPU is gr eat er
tha n 4,
- Th e nu mber of th e tr ansmitting CPU is less than 1 ,
- Th e nu mber of the tr ansmitting CPU is the same
as the CPU’s own number.
67 The special f unction organization block call is wrong.
The following errors are possible:
- Se con d ary erro r, sinc e the INIT IAL I ZE fun c ti on
could not be called or was terminated by an
initialization con flict.
- Double call: the call for this function, SEND, SEND
TEST, RECEIVE or RECEIVE TEST is illegal,
sinc e on e of t he f uncti ons INI TI ALIZE, S EN D,
SEND TEST, RECEIVE or RECEIVE TEST has
alr ead y b een c all e d i n t h is C P U in a l o wer pr o ces si n g
level (e.g. cyclic program processing).
- The CPU’s own number is incorrect (system data
corrupted);
following power down/power up the CPU number
is generated again by the system program.
68 The mana gemen t data (queue manage ment) of the
s elec te d li nk s are inco rrec t; se t up t he bu ffe r in
the coordinator COR 923C again using the
INITIALIZE function.
Warning
The "warning" number group cannot occur with the RECEIVE TEST
function.
Receivin g capacity
The "receiving capacity" para meter indicates how man y data fields can
be received and buffered.
RE CEIVE T EST F unction ( OB 205)
CPU 928B Programming Guide
10 - 50 C79000-B8576-C898-01
10.9 Applications
Based on exam ples, this section explains how to program
mu l tiproc ess or commun ication .
Note
If you use the fun ction blocks listed belo w and service interrupt s o n
your CPU (e.g. with OB 2) remember to save the "scratchpad flags"
at the start of interrupt servicing and to write the m back when the
interrupt is c o mpleted.
This also appl ies to the setting "interrupts at block boundaries" , since
the call of the special function organization blocks represents a block
boundary.
10.9.1
Calling the Special
Fun ctio n OB usi ng
Fun ctio n Blo cks
The follo wing five function blocks (FB 200 and FB 202 to FB 205)
contain the call for the corresponding special function organization block
for multiprocessor communication (OB 200 and OB 202 to OB 205).
The n umbers of the function blocks are not fixed and can be changed.
The parameters o f the special function OBs are transferred as actual
parameters when the function blocks are called. The dire ct call of the
special function organization blocks is faster, ho wever, is more d ifficult
to read owing to the absence o f formal parameters
F B no. FB name F unction
FB 200
FB 202
FB 203
FB 204
FB 205
INITIAL
SEND
SEND-TST
RECEIVE
RECV-TST
Set up buffer
Send a data f ield
Test sending capaci ty
Receive a data f ield
Test receiving capacity
The flag area from FY 246 to maximum FY 255 is used by the function
blocks as a para meter field for the special function organization blocks.
T he exact significance of the input and output parameters is explained
i n the descripti on of the special function organization bloc ks.
10
Applications
CPU 928B Programming G uide
C79000-B8576-C898-01 10 - 51
Note
Th e following ex a mples of applications involve finished applications
that you can program by copying them.
Pro gr am min g functi on
blocks
FB 200: initializing the links
FB 200
INITIAL
(1) A UMA INIC (5 )
(2) N UMC TCAP (6 )
(3) T NAS
(4) S TAS
Parameter
name Significance Parameter
type Data
type Parameter
field
AUMA
NUMC
TNAS
STAS
INIC
TCAP
Automatic/manual
Number of CPUs
Ty p e ( H b yte ) and number (L byte)
of the data block containing the
assign m ent list
Start ad d ress of th e assignm e nt list
Initialization conflict
Total capacity
I
I
I
I
Q
Q
BY
BY
W
W
BY
BY
FY 246
FY 247
FW 248
FW 250
FY 252
FY 253
Continued on the next page
Applications
CPU 928B Programming Guide
10 - 52 C79000-B8576-C898-01
FB 200 continued
FB 200 LEN=45
SEGMENT 1 0000
NAME:INITIAL
DECL :AUMA I/Q/D/B/T/C: I BI/BY/W/D:BY
DECL :NUMC I/Q/D/B/T/C: I BI/BY/W/D:BY
DECL :TNAS I/Q/D/B/T/C: I BI/BY/W/D:W
DECL :STAS I/Q/D/B/T/C: I BI/BY/W/D:W
DECL :INIC I/Q/D/B/T/C: Q BI/BY/W/D:BY
DECL :TCAP I/Q/D/B/T/C: Q BI/BY/W/D:BY
0017 :L =AUMA Automatic/manual
0018 :T FY 246
0019 :L =NUMC Number of CPUs
001A :T FY 247
001B :L =TNAS DB type, DB no.
001C :T FY 248
001D :L =STAS Start address of the assignment
001E :T FW 250 list
001F :
0020 :L KB 246 SF OB:
0021 :JU OB 200 "Initialize"
0022 :
0023 :L FY 252 Initialization conflict
0024 :T =INIC
0025 :L FY 253 Total capacity
0026 :T =TCAP
0027 :BE
10
Applications
CPU 928B Programming G uide
C79000-B8576-C898-01 10 - 53
FB 202: Sending a data field
FB 202
SEND
(1) R CPU ERWA (4 )
(2) T NDB TCAP (5 )
(3) F INO
Parameter
name Significance Parameter
type D ata
type Parameter
field
RCPU
TNDB
FINO
ERWA
TCAP
Receiving CPU
Ty p e ( H b yte ) and number (L byte)
o f the sour ce data block
Field number
Error/warning
Transmitting capacity
I
I
I
Q
Q
BY
W
BY
BY
BY
FY 246
FW 247
FY 249
FY 250
FY 251
FB 202 LEN=40
SEGMENT 1 0000
NAME:SEND
DECL :RCPU I/Q/D/B/T/C: I BI/BY/W/D:BY
DECL :TNDB I/Q/D/B/T/C: I BI/BY/W/D:W
DECL :FINO I/Q/D/B/T/C: I BI/BY/W/D:BY
DECL :ERWA I/Q/D/B/T/C: Q BI/BY/W/D:BY
DECL :TCAP I/Q/D/B/T/C: Q BI/BY/W/D:BY
0014 :L =RCPU Receiving CPU
0015 :T FY 246
0016 :L =TNDB DB type, DB no.
0017 :T FW 247
0018 :L =FINO Field number
0019 :T FY 249
001A :
001B :L KB 246 SF OB:
001C : JU OB 202 "Send a data field"
001D :
001E :L FY 250 Error/warning
001F :T =ERWA
0020 :L FY 251 Transmitting capacity
0021 :T =TCAP
Applications
CPU 928B Programming Guide
10 - 54 C79000-B8576-C898-01
FB 203: Testing the transmitting capacity
FB 203
SEND-TST
(1) R CPU ERRO (2 )
TCAP (3)
Parameter
name Significance Parameter
type Data
type Parameter
field
RCPU
ERRO
TCAP
Receiving CPU
Error
Transmitting capacity
I
Q
Q
BY
BY
BY
FY 246
FY 248
FY 249
FB 203 LEN=30
SEGMENT 1 0000
NAME:SEND-TST
DECL :RCPU I/Q/D/B/T/C: I BI/BY/W/D:BY
DECL :ERRO I/Q/D/B/T/C: Q BI/BY/W/D:BY
DECL :TCAP I/Q/D/B/T/C: Q BI/BY/W/D:BY
000E :L =RCPU Receiving CPU
000F :T FY 246
0010 :
0011 :L KB 246 SF OB:
0012 : JU OB 203 "Test transmitting capacity"
0013 :
0014 :L FY 248 Error
0015 :T =ERRO
0016 :L FY 249 Transmitting capacity
0017 :T =TCAP
0018 :BE
10
Applications
CPU 928B Programming G uide
C79000-B8576-C898-01 10 - 55
FB 204: Receiving a data field
FB 204
RECEIVE
(1) T CPU ERWA (2 )
RCAP (3)
TNDB (4)
STAA (5)
ENDA (6)
Parameter
name Significance Parameter
type Data
type Parameter
field
TCPU
ERWA
RCAP
TNDB
STAA
ENDA
Transmitting CPU
Error/warning
Receiving capacity
Ty p e ( H b yte ) and number (L byte) of the
destination data block
Address of the first receive d data word
(start address)
Address of the last received data word
(end address)
I
Q
Q
Q
Q
Q
BY
BY
BY
W
W
W
FY 246
FY 248
FY 249
FW 250
FW 252
FW 254
Continued on the next page
Applications
CPU 928B Programming Guide
10 - 56 C79000-B8576-C898-01
FB 204 continued:
FB 204 LEN=45
SEGMENT 1 0000
NAME:RECEIVE
DECL :TCPU I/Q/D/B/T/C: I BI/BY/W/D:BY
DECL :ERWA I/Q/D/B/T/C: Q BI/BY/W/D:BY
DECL :RCAP I/Q/D/B/T/C: Q BI/BY/W/D:BY
DECL :TNDB I/Q/D/B/T/C: Q BI/BY/W/D:W
DECL :STAA I/Q/D/B/T/C: Q BI/BY/W/D:W
DECL :ENDA I/Q/D/B/T/C: Q BI/BY/W/D:W
0017 :L =TCPU Transmitting CPU
0018 :T FY 246
0019 :
001A :L KB 246 SF OB:
001B :JU OB 204 "Receive a data field"
001C :
001D :L FY 248 Error/warning
001E :T =ERWA
001F :L FY 249 Receiving capacity
0020 :T =RCAP
0021 :L FW 250 DB type, DB no.
0022 :T =TNDB
0023 :L FW 252 Start address
0024 :T =STAA
0025 :L FW 254 End address
0026 :T =ENDA
0027 :BE
FB 205: Testing the receiving capacity
FB 205
RECV-TST
(1) T CPU ERRO (2 )
RCAP (3)
Parameter
name Significance Parameter
type Data
type Parameter
field
TCPU
ERRO
RCAP
Transmitting CPU
Error
Receiving capacity
I
Q
Q
BY
BY
BY
FY 246
FY 248
FY 249
10
Applications
CPU 928B Programming G uide
C79000-B8576-C898-01 10 - 57
10.9.2
Trans fer ring Data Bl ocks In this example, the function block TRAN DAT (FB 110) transfers a
selectable number of data fields from a data block in one CPU t o the
dat a bloc k o f th e same type a n d same num be r in a d ifferent C PU.
T he FB nu mber (FB 110) has been selected at random and you can
use ot her n umbers.
Prog rammi n g FB 110 i s d es cribed fi rst fol lowed by t he a ppl ic at ion of
FB 110.
Programming FB 110
FB 205 continued:
FB 205 LEN=30
SEGMENT 1 0000
NAME:RECV-TST
DECL :TCPU I/Q/D/B/T/C: I BI/BY/W/D:BY
DECL :ERRO I/Q/D/B/T/C: Q BI/BY/W/D:BY
DECL :RCAP I/Q/D/B/T/C: Q BI/BY/W/D:BY
000E :L =TCPU Transmitting CPU
000F :T FY 246
0010 :
0011 :L KB 246 SF OB:
0012 : JU OB 205 "Test receiving capacity"
0013 :
0014 :L FY 248 Error
0015 :T =ERRO
0016 :L FY 249 Receiving capacity
0017 :T =RCAP
0018 :BE
FB 110: Transferring a data block
Task
The d ata ar ea t o be t rans fe rred is st ipul ated b y th e in pu t pa ra mete r
FIRB (= number of the first data field to be transferred) and NUMB (=
number of data fields to be transferred). A data field normally consists
of 32 data words. Depending on the data block length, the last data
field may be less than 32 data words.
The tr ansf er is tr igge red by a positiv e-go ing edge at the star t input
STAR. If t he outpu t pa rameter REST is zero after t he trans fer, this me ans
that t he f unction bloc k TRANDA T was ab le t o send a ll the d ata fields
(accor ding to the NUMB parameter).
Continued on the next page
Applications
CPU 928B Programming Guide
10 - 58 C79000-B8576-C898-01
FB 110 continued:
If, h owev er , th e RE ST out pu t pa rame te r ha s a va lue grea te r th an zer o,
this mean s that the f unct io n bl ock mu st b e ca ll ed a gain , for ex ampl e in
the next cycle. This means that you or the user program can only change
the s et p ar amet ers (i .e. th e va lues o f al l pa ra mete rs) wh en t he RES T
parameter indicates zero showing that the data transfer is complete.
You can call the function block TRANDAT several times with different
parameters. In this case, various data areas are transferred
simultaneously (interleaved in each other). The special function
organization blocks for multiprocessor communication OB 202 to OB 205
can also be used "directly". This possibly is illustrated in the
application example.
If the SEN D functi on ( OB 202) is not c orre ctly exe cuted wi th t he TRAND AT
functi on b lock, th e er ror numb er is en tere d in the output para meter ER RO,
the RL O = ’1’ and the output p arameter RES T is set to ’0’.
The TRANDAT function block uses flag bytes FY 246 to FY 251 as
scratchpad flags. All other variables whose value is significant as long
as th e ou tp ut p aram et er R ES T = ’0’ co ntin ue t o have mem or y as si gned to
them using the mechanism of formal/actual parameters. This is necessary
to al low va riou s da ta blo ck s to be tr ansf erre d simu ltan eo usly .
Implementation
FB 110
TRAN-DAT
(1) S TAR ERRO (6 )
(2) R CPU REST (7 )
(3) T NDB CUBN (8)
(4) N UMB EDGF (9 )
(5) F IRB
Continued on the next page
10
Applications
CPU 928B Programming G uide
C79000-B8576-C898-01 10 - 59
FB 110 continued:
Parameter
name Significance Parameter
type Data
type
STAR
RCPU
TNDB
NUMB
FIRB
ERRO
REST
CUBN 1)
EDGF 1)
Start the transfer of the data block on a positive-going edge
Receiving CPU
Type (H b yte) a nd number (L b yte) of the data block to be
transferred.
Number of da ta fi elds to be tra nsferred.
Number of the first data fiel d to be trans ferred.
Error
Number of da ta fields still to be transf e rred.
Current field number
Edge flag
I
I
I
I
I
Q
Q
Q
Q
BI
BY
W
BY
BY
BY
BY
BY
BI
1) In ternal s cratc h pad f l ag, not intend ed fo r e valuatio n
FB 110 LEN=89
SEGMENT 1 0000
NAME:TRAN-DAT
DECL :STAR I/Q/D/B/T/C: I BI/BY/W/D:BI
DECL :RCPU I/Q/D/B/T/C: I BI/BY/W/D:BY
DECL :TNDB I/Q/D/B/T/C: I BI/BY/W/D:W
DECL :NUMB I/Q/D/B/T/C: I BI/BY/W/D:BY
DECL :FIRB I/Q/D/B/T/C: I BI/BY/W/D:BY
DECL :ERRO I/Q/D/B/T/C: Q BI/BY/W/D:BY
DECL :REST I/Q/D/B/T/C: Q BI/BY/W/D:BY
DECL :CUBN I/Q/D/B/T/C: Q BI/BY/W/D:BY
DECL :EDGF I/Q/D/B/T/C: Q BI/BY/W/D:BI
0020 :L =RCPU Assign parameter field for
0021 :T FY 246 SF OB 202
0022 :L =TNDB
0023 :T FW 247
0024 :
Continued on the next page
Applications
CPU 928B Programming Guide
10 - 60 C79000-B8576-C898-01
FB 110 continued:
0025 :L =REST First send any remaining
0026 :L KB 0 data fields
0027 :><F
0028 :JC =TRAN
0029 :
002A :AN =STAR Positive edge at start
002B :RB =EDGF input ?
002C :ON =STAR
002D :O =EDGF
002E :JC =GOOD
002F :S =EDGF
0030 :
0031 :L =NUMB Initialize the global flags
0032 : T =RES T afte r post ive ed ge a t
0033 :L =FIRB START input
0034 :T =CUBN
0035 :
0036 :L =REST As long as REST ><0,
0038 LOOP :L KF+0 cont inue t o at temp t to
0039 :!=F send data fields
003A :JC =GOOD
003 B TR AN:L =CUB N
003C :T FY 249
003D :L KB 246 SF OB:
003E : JU OB 202 "Send a data field"
003F :L FY 250
0040 :JM =ERRO Abort if error
0041 :JP =GOOD Abort if trans-cap. = 0
0042 :L =CUBN Increment
0043 :I 1 field number
0044 :T =CUBN
0045 :L =REST Decrement number of
0046 :D 1 remaining data fields
0047 :T =REST
0048 :JU =LOOP
0049 :
004A GOOD :A F 0.0 Regular end of program:
004B :AN F 0.0
004C :L KB 0 RLO = 0, ERRO = 0
004D :T =ERRO
004E :BE
004F :
0050 ERRO :T =ERRO Program end if error:
0051 :L KB 0
005 2 :T =REST RLO = 1, ERR O co ntai ns err or
0053 :BE number
10
Applications
CPU 928B Programming G uide
C79000-B8576-C898-01 10 - 61
Application of FB 110
Application of FB 110
Task
You wa nt C PU 1 to tran sfer dat a blocks DB 3 (data fields 2 to 5) and D B 4
(data fiel ds 1 to 3) t o CPU 2 during t he c yclic us er progr am. The RECE IVE
functi on ( OB 204) is a lso call ed in th e cy clic use r progra m.
Implementation
Function CPU 1 CPU 2
called in: cal led in:
Initialization (OB 200)
Send organization (FB 1)
Receive organization (FB 2)
O B 20
OB 1
–
–
–
OB 1
exists: exists:
Send DB
Rece ive DB
DB 3; DB 4
–
–
DB 3; DB 4
The use r prog ra m in fun ctio n bl ock FB 1 of CPU 1 co nt ains two cal ls for
the f unct io n bl ock TR ANDA T in e ach ca se w ith di ffer ent se ts o f
parameters.
The transfer of the first data block DB 3 begins after a positive edge
after input I 2.0. A positive edge at input I 2.1 starts the transfer of
the second data block.
FB 1 LEN=yy
SEGMENT 1 0000
NAME:S-ORG
0000 :L KB 2 To CPU 2 ..
0001 :T FY 0
0002 :L KY 1,3 .. from data block DB 3
0003 :T FW 1
0004 :L KB 4 .. four data fields
0005 :T FY 3
0006 :L KB 2 .. send from 2nd data field
0007 :T FY 4
0008 :
Continued on the next page
Applications
CPU 928B Programming Guide
10 - 62 C79000-B8576-C898-01
Application example continued:
0009 :JU FB 110
000 A NA ME :T RAN- DA T
000B STAR : I 2.0
000 C RC PU : FY 0
000 D TN DB : FW 1
000 E NU MB : FY 3
000 F FI RB : FY 4
001 0 ER RO : FY 5
001 1 RE ST : FY 6
001 2 CU BN : FY 7
0013 EDGF : F 8.0
0014 :
0015 :
001 6 :JC =HAL T Abor t af ter er ro r
0017 :
0018 :L KB 2 To CPU 2 ..
0019 :T FY 10
001A :L KY 1,4 .. from data block DB 4
001B :T FW 11
001C :L KB 3 .. three data fields
001D :T FY 13
001E :L KB 1 .. send from 2nd data field
001F :T FY 14
0020 :
0021 :JU FB 110
002 3 NA ME :T RAN- DA T
0024 STAR : I 2.1
002 5 RC PU : FY 10
002 6 TN DB : FW 11
002 7 NU MB : FY 13
002 8 FI RB : FY 14
002 9 ER RO : FY 5
002 A RE ST : FY1 6
002 B CU BN : FY1 7
002C EDGF : F 8.1
002D :
002E :
002 F :JC =HAL T Abor t af ter er ro r
0030 :BEU
0031 :
0032 HALT :
0033 : The error handling takes place
0034 : here (e.g. stop, message output
0035 : on the printer, ...)
0036 :
00xx :BE
Continued on the next page
10
Applications
CPU 928B Programming G uide
C79000-B8576-C898-01 10 - 63
10.9.3
Extend ing the IPC
Flag Area
T he pr ob lem
In the S5-1 3 5U/ 155U progra mm able con t ro l le rs , e ac h of t h e 256 fla g
by tes of a CPU can become an input or output IPC f lag by making an
entry in data block DB 1. This, however, reduces the number of
"n ormal " fla g byt es. To t ransfer a d at a reco rd (seve ra l byt es) o t he r
mec hanis ms are also required (semaphore variable or DX 0 parameter
assignment "trans fer IPC flags as a block") are necessary to prevent
the receiver from receiving a fragme nted data record.
Application example continued:
In CPU 2, the RECE IVE function (OB 204 ) ca lled by FB 2 ent ers each
transm itte d data f ield into th e approp riat e data b lock. It may take
severa l cy cles bef ore a data b lock has bee n comple tely rec eive d.
FB 2 LEN=yy
SEGMENT 1 0000
NAME:RECV-DAT
0000 :L KB 1 Receive data from CPU 1
0001 :T FY 246
0002 :
0003 SCHL :L KB 246 SF OB:
0004 : JU OB 204 "Receive"
0005 :JM =ERRO Abort if error
0006 : L FY 2 49 The RE CEIV E func tion i s
0007 :L KB 0 called until there are no
0008 : >< F fu rthe r of d ata fiel ds in
0009 : JC =LOO P the bu ffer , i.e. the
000A : receiving capacity = 0.
000B :BEU
000C ERRO :
000D : The error handling takes place
000E : here (e.g. stop, message output
000F : on printer, ...)
00xx :BE
Applications
CPU 928B Programming Guide
10 - 64 C79000-B8576-C898-01
T he sol uti on
Consecutive data words of a DB or DX data block are defined f rom
DW 0 onwards as "IPC data words". Each link is assigned its own
data block and is tota lly independent of the other links.
At the beginning of the cycle block, the IPC data words are received with
the aid of the special function organization blocks for multiprocessor
communication. This is followed by the "regular" c yclic progra m, that
evaluates the received data and generates the data to be sent. At the en d
o f the cycle, this data is then sent with the aid o f the special organization
blocks for multiprocessor communication. It can therefore be received by
the other CPUs at the beginning of their cycles.
The f ollowing applies f or each of the m axim um 12 possible links
reg ardless of t h e othe r lin ks :
•• The transmitting CPU is only active when the receiving CPU has
read out all the "old" data f rom the COR 923C buffer.
•• The rec ei vi ng CPU is onl y ac ti ve when t h e t ransmit ti ng CPU h a s
writt en a ll the "new " da ta i n th e COR 923C buffer.
This means that the receiving CPU can either receive a complete new
data record or the old data record remains unchanged: no mixin g of
" old" and "new" data.
Data structu r e
Which data words (for the data word area below) are to be tran sferred
fro m which CPU to which CPU is described in the link list (see the table
on the following page). This is located in an additional data block that
must exist in all the CPUs involved .
The data word areas always begin fro m data word DW 0, and their
lengths are specified in data fields. Remember the following points:
•• A com plete data f ield consists of 32 data words.
•• If the last data f ield is " truncated", i.e. it contains between 1 and
31 data words, less data words are transferred.
•• If a send data blo ck is longer than the nu mber of fields of data spe-
cified in the link list, the excess data words can be used in the cor-
responding CPU.
•• If a re ce ive da ta blo c k is lon ge r th a n th e re ce ive d data w ord area,
the ex ce ss da ta wo rds can be u sed in t h e c o rre spondin g CPU.
10
Applications
CPU 928B Programming G uide
C79000-B8576-C898-01 10 - 65
Structure of the
link list
SUB-LIST 1 SUB-LIST 2
Link DB type DB
number No. of data
fields
from CPU 1
to ... DW 0 S 1 DW 16 S 1
... CPU 2 DW 1 ... ... DW 17 2...
... CPU 3 DW 2 ... ... DW 18 3...
... CPU 4 DW 3 ... ... DW 19 4...
from CPU 2
to ... DW 4 S 2 DW 20 S 2
... CPU 1 DW 5 ... ... DW 21 1...
... CPU 3 D W 6 1 1) 10 1) DW 22 3 2 1)
... CPU 4 DW 7 ... ... DW 23 4...
from CPU 3
to ... DW 8 S 3 DW 24 S 3
... CPU 1 DW 9 ... ... DW 25 1...
... CPU 2 DW 10 ... ... DW 26 2...
... CPU 4 DW 11 ... ... DW 27 4...
from CPU 4
to ... DW 12 S 4 D W 28 S 4
... CPU 1 DW 13 ... ... DW 29 1...
... CPU 2 DW 14 ... ... DW 30 2...
... CPU 3 DW 15 ... ... DW 31 3...
2 15 2 0 2 15 2 0
1) Ref e r to the examp le on the follow ing pag e
Ta ble 10-8 Link list fo r ext ending the IPC fl ag ar ea
Applications
CPU 928B Programming Guide
10 - 66 C79000-B8576-C898-01
The link consists o f two similarly structured sub-lists, each with 16 data
words. For each of the four sender CPUs (S 1, S2, S3, S4) three entri es are
required to describe a link.
•• Numbe r of data fi el ds
T he n umber of data fiel ds speci fies the size (= the number of data
words) of the data word area to be trans ferred. (If li nks do not
exist or you d o not require them, en ter 0 for the number of data
fie lds, and for th e DB type and DB number.)
•• DB type
Type o f data bl ock c ont ai ni n g th e data w o rd area t o be t ra n sferred .
•• DB number
Nu mber of the data block contai nin g the data word area to be trans-
ferred.
As shown in the table, these entries can be read in and co mpleted in lines.
I f, for example, you want to transfer the first two data fields in data block
DB 10 fro m CPU 2 (S2) to CPU 3, make the following entries:
CPU 2 (S 2) sends ..
Sub - lis t 2 is identical to the assignmen t ( "manual" mo d e ) r equired fo r
th e INITIALIZE func tion (OB 200). W ithin t he d ata block, sub-list 2
must occ u py da ta w o rds 0 to 15 an d sub-list 2 data w o rds 16 to 31.
You must not alter the entries shown in bold f ace.
DW 22 3 2 DW 6 1 10
..to CPU 3 2 data f ields f rom DB 10
10
Applications
CPU 928B Programming G uide
C79000-B8576-C898-01 10 - 67
Program structure
During restart, on e of the CPUs calls t he INITI ALIZE functio n
(OB 200) to re serve ex ac tl y th e sa me n umber of coo rdi n at or memory
fields per link as data f ields to be transm itted on this link.
To send and receive data word areas, each CPU use s two fun ction
blocks:
FB no. N am e Function
FB 100
FB 101
SEND-DAT
RECV-DAT
S end dat a word ar e as
t o the other C P Us
Rece iv e data word areas
from the other CPUs
These FB numbers have been selected at random and you can use
others.
The function blocks S END-DAT and RECV-DAT read the link list to
determine which data word areas are to be sent fro m or received by
which data blocks. The whole data word area is always sent or received.
I f this is not possible owing to insufficient tran smitting or receivin g
capacity, the send or receive function is not executed.
Note
This example (IPC flag extension usin g function blocks S END-DAT
and RECV-D AT) can only run correctly when the special function
organization bl ocks for multipro cessor co mmunication OB 202 t o
OB 205 are not called in any of the CPUs .
Th e function blocks SEND-DAT and RECV-DAT contain the
special function organization blocks for multiprocessor
communication OB 202 to OB 205. You cannot call these
organization bl ocks outside SEND-DAT/RECV-D AT.
Applications
CPU 928B Programming Guide
10 - 68 C79000-B8576-C898-01
OB 20
Restart OB to reserve
the buffer on the
923C coordinator JU OB 200
BE
Cyclic user program
extended by the calls for
the RECV-DAT and SEND-DAT
function blocks.
OB 1
C
JU DB xxx
FB 101
C
JU DB xxx
FB 100
BE
FB 100
FB 101
Function block: SEND-DAT
Send data blocks
Function block: RECV-DAT
Receive data blocks
Data block containing
the link list
Maximum three input and
three output blocks
DB xxx
BE
BE
KS = S1
KY = 1,... evalu-
ated
by ...
DB yyy
or/and
DX zzz
.
.
.
.
.
.
.
.
.
.
.
.
OB 200 must
only be called
in one processor.
1)
1)
Fig. 10-6 Ov erview of the blocks require d in each CPU
10
Applications
CPU 928B Programming G uide
C79000-B8576-C898-01 10 - 69
Pro gr am min g functi on
blocks
FB 100: Sending data word areas
Befor e yo u call FB 10 0, t he dat a bl oc k co ntai ni ng t he l in k li st mus t be
open. The f unct ion bl ock SE ND-D AT r eq uire s th e numb er o f the CP U on
which it is called in order to evaluate the information contained in the
lin k li st.
If th e SE ND fun ctio n (OB 20 2) i s no t exec uted c orre ctly i n th e func tion
block, the error or warning number is transferred to the output
parameter ERWA and RLO is set to 1.
If th e in pu t pa rame te r CP UN (CP U nu mb er) is i ll egal , ER WA has t he v alue
16 (bit no. 4 = 1).
The f unct io n bl ock SE ND-D AT use s fl ag byt es F Y 239 to F Y 251 as
scratchpad flags.
FB 100
SEND-DAT
(1) C PUN ERWA (2 )
Parameter
name Significance Parameter
type Data
type
CPUN
ERWA
Number of the CPU on which FB 100 is called.
T he numbers 1 to 4 are permitted.
Error/warning (see SEND function/
O B 202)
D
Q
KF
BY
FB 100 LEN=90
SEGMENT 1 0000
NAME:SEND-DAT
DECL :CPUN I/Q/D/B/T/C: D KM/KH/KY/KS/KF/KT/KC/KG:KF
DECL :ERWA I/Q/D/B/T/C: Q BI/BY/W/D: BY
000B :LW =CPUN CPUN = CPUN - 1
000C :L KB 1 Error if:
000D :-F
000E :JM =ERWA CPU no. <1
000F :L KB 3
0010 :>F
0011 :JC =ERWA CPU no. >4
0012 :TAK
Continued on the next page
Applications
CPU 928B Programming Guide
10 - 70 C79000-B8576-C898-01
FB 100 continued:
0013 :
0014 :SLW 2 CPUN = CPUN * 4
0015 :T FY 245 Bas e addres s
0016 :
0017 :L KB 1
0018 :T FY 244 Link co unter
0019 :
001A L OOP :L FY 245 Bas e addres s
001B :L FY 244 + cou nter
001C :+F
001D :T FW 240
001E :ADD BN+16 + offset
001F :T FW 242
0020 :
0021 :DO FW 242
0022 :L DR 0 Number of reser ved
0023 :T FY 239 fields = 0 ?
0024 :L KB 0
0025 :!=F
0026 :JC =EMPT
0027 :
0028 :B FW 242
0029 :L DL 0 No. of the rece ivin g CPU
002A :T FY 246
002B :L KB 246 SF OB:
002C :JU OB 20 3 "Test send ing capacity"
002D :L FY 248 Abort if error
002E :JC =OBER
002F :
0030 :L FY 249 Transmitting capacity >< no.
0031 :L FY 239 of reserved fields?
0032 :><F
0033 :JC =EMPT
0034 :
0035 :L KB 0 Field counter
0036 :T FY 249
0037 :
0038 :B FY 240
0039 :L DW 0 Type and number of
003A :T FW 247 the source DB
003B :
003C TRAN :L KB 246 SF OB:
003D : JU OB 202 Send a data field
003E :L FY 250 Abort if error/warning
003F :JC =OBER
0040 :
0041 : L FY 2 49 Field no. = fiel d no . + 1
0042 :I 1
0043 : T FY 2 49 All da ta f ie lds tran sf erre d ?
0044 :L FY 239
0045 :<F
0046 :JC =TRAN
0047 :
Continued on the next page
10
Applications
CPU 928B Programming G uide
C79000-B8576-C898-01 10 - 71
FB 100 continued:
0048 E MPT :L FY 244 Inc rement
0049 :I 1 link co unter
004A :T FY 244
004B :L KB 4 All li nks
004C :<F process ed ?
004D :JM =LOOP
004E :L KB 0 Regular program end :
004F :T =ERWA RLO = 0, ER WA = 0
0050 :BEU
0051 :
0052 E RWA :L KB 16 Program end if erro r:
0053 O BER :T =ERWA RLO = 1 , ERWA c onta ins
0054 :BE error/w arni ng numbe r
FB 101: Receive data word areas
Befor e yo u call FB 10 1, t he dat a bl oc k co ntai ni ng t he l in k li st mus t
already be open. The function block RECV-DAT requires the number of the
CPU i n wh ic h it is ca lled i n or der to eva luat e the info rm atio n cont aine d
in th e li nk lis t.
If th e RE CEIVE fu ncti on (OB 2 04) is n ot c orrectly process ed w ithin th e
funct ion block, t he c orrespon ding err or o r warnin g number is transfer red
to th e ou tput par amet er ERWA and the RLO is set t o 1. If the input
param eter CPUN is ill egal, ER WA has t he v alue 16 (bit no. 4 = 1).
The RECV-DAT function block uses flag bytes FY 242 to FY 255 as
scratchpad flags.
FB 101
RECV-DAT
(1) CPUN ERW A (2)
Parameter
name Significance Parameter
type Data
type
CPUN
ERWA
Number of the CPU, on which FB 101 is cal led.
Th e nu m bers 1 t o 4 are perm i tt ed.
Error/warni ng (s ee REC EIVE func ti on /
OB 204 )
D
Q
KF
BY
Continued on the next page
Applications
CPU 928B Programming Guide
10 - 72 C79000-B8576-C898-01
FB 101 continued:
FB 101 LEN=88
SEGMEN T 1 0000
NAME:RECV-DAT
DECL :CPUN I/Q/D/B/T/C: D KM/KH/KY/KS/KF/KT/KC/KG:KF
DECL :ERWA I/Q/ D/B/T/C: Q BI/BY/ W/D: BY
000B :LW =CPUN Error if:
000C :L KB 1
000D :<F
000E :JC =ERWA CPU no. <1
000F :LW =CPUN
0010 :L KB 4
0011 :>F
0012 :JC =ERWA CPU no. >4
0013 :
0014 :L KB 1 Link counter
0015 :T FY 242
0016 :
0017 :L KB 16
0018 :T FW 244 Pointer to sub-list 2
0019 :
001A SRCH :L FW 244 Search sub-list 2 until
001B :I 1 the next entry for the
001C :T FW 244 receiving CPU with the
001D : DO FW 2 44 number ’C PUN’ is fo und.
001E :L DL 0
001F :LW =CPUN
0020 :><F
0021 :JC =SRCH
0022 :
0023 :DO FW 244
0024 :L DR 0 Number of reserved
0025 :T FY 243 memory fields = 0 ?
0026 :L KB 0
0027 :!=F
0028 :JC =EMPT
0029 :
002A :L FW 244 Determine the number of the
002B : L KM 0 0000 00 0 00 0011 00 tran smit ti ng C PU f ro m th e
002D :AW pointer to sub-list 2.
002E :SRW2
002F :I 1
0030 :T FY 246
0031 :
0032 :L KB 246 SF OB:
0033 : JU OB 205 "Test receiving capacity"
0034 :L FY 248
0035 : JC = OB ER Abor t if e rr or
0036 :
Continued on the next page
10
Applications
CPU 928B Programming G uide
C79000-B8576-C898-01 10 - 73
FB 101 continued:
0037 :L FY 249 Receivi ng capac ity = nu mber
0038 :L FY 243 of rese rved
0039 :><F memory fiel ds ?
003A :JC = EMPT
003B :
003C R ECV :L KB 246 SF OB:
003D :JU OB 204 "Receive a data field"
003E :L FY 248
003F :JM =OBER Abort if error/warning
0040 :L FY 249 if receiving capacity = 0
0041 :L KB 0 process next link
0042 :><F
0043 :JC =RECV
0044 :
0045 EMPT :L FY 242 Increment
0046 :I 1 link counter
0047 :T FY 242
0048 :L KB 4 All links
0049 :<F processed ?
004A :JM = SRCH
004B : L KB 0 Re gu lar prog ra m en d:
004C :T =ERWA RLO = 0, ERWA = 0
004D :BEU
004E :
004F ERWA :L KB 1 6 Pr og ram end if err or :
0050 OBER :T =ERW A RL O = 1, ERW A cont ai ns
0051 :BE error/warning number
Applications
CPU 928B Programming Guide
10 - 74 C79000-B8576-C898-01
Application example
Application of FB 100/101
Task
You w ant to excha nge data bet ween thr ee C PUs:
- From CPU 1 to CPU 2: da ta b lock D B 3, D W 0 to D W 127 (= 4 d ata fiel ds )
- From CPU 1 to CPU 3: data block DX 4, DW 0 to DW 63 (= 2 data fields)
- From CPU 2 to CPU 1
and CPU 3: data block DB 5, DW 0 to DW 95 (= 3 data fields)
Funct ion bl ock FB 1 i s th e inte rfac e for the cy clic use r prog ra m on all
three CPUs. CPU 1 calls the INITIALIZE function (OB 200) during the cold
restart. The link list is in data block DB 100.
Continued on the next page
DB 5, 3 data fields
DB 3,
4 data
fields
DB 5,
3 data
fields
DX 4, 2 data fields
CPU 2 CPU 3
CPU 1
F ig. 10-7 Data exchange between 3 CPUs
10
Applications
CPU 928B Programming G uide
C79000-B8576-C898-01 10 - 75
Application example continued:
Implementation
1. Lo ad ing bl oc ks
The following blocks must be loaded in the individual CPUs:
Function CPU 1 C PU 2 C PU 3
Restart OB
User program
FB: SEND-DAT
FB: RECV-DAT
Link li st
Input DB
Output DB
OB 20
FB 1
FB 100
FB 101
DB 100
DB 5
DB 3; DX 4
—
FB 1
FB 100
FB 101
D B 100
DB 3
DB 5
—
FB 1
FB 100
FB 101
D B 100
DB 5; DX 4
—
2. Cr eati ng the lin k list
The l ink li st i s cr ea ted an d en tere d in d ata bl ock DB 1 00 :
DB100 LEN=37
PAGE 1
– – Sub-list 1 – –
0: KS = ’S 1’; Send fro m CPU 1 to ..
1: KY = 001,003; .. CPU 2 (DB 3)
2: KY = 002,004; .. CPU 3 (DX 4)
3: KY = 00 0,00 0;
4: KS = S2 ; Send from CP U 2 to . .
5: KY = 001,005; .. CPU 1 (DB 5)
6: KY = 001,005; .. CPU 3 (DB 5)
7: KY = 00 0,00 0;
8: KS = ’S 3’;
9: KY = 00 0,00 0;
10: KY = 00 0,00 0;
11: KY = 00 0,00 0;
12: KS = ’S 4’;
13: KY = 00 0,00 0;
14: KY = 00 0,00 0;
15: KY = 00 0,00 0;
Continued on the next page
Applications
CPU 928B Programming Guide
10 - 76 C79000-B8576-C898-01
Application example continued:
– – Sub-list 1 – –
16: KS = ’S 1’ ; Send f rom CP U 1 to ..
17: KY = 00 2, 004; .. CPU 2 (fo ur d at a fi el ds)
18: KY = 00 3, 002; .. CPU 3 (tw o da ta fie ld s)
19: KY = 00 4,00 0;
20: KS = S2 ’; Send f rom CP U 2 to ..
21: KY = 001,003; .. CPU 1 (three data fields)
22: KY = 003,003; .. CPU 3 (three data fields)
23: KY = 00 4,00 0;
24: KS = ’S 3’;
25: KY = 00 1,00 0;
26: KY = 00 2,00 0;
27: KY = 00 4,00 0;
28: KS = ’S 4’;
29: KY = 00 1,00 0;
30: KY = 00 2,00 0;
31: KY = 00 3,00 0;
Data words DW 16 to DW 31 contain the assignment list required for the
manua l IN IT IALI ZATI ON fun ct ion (OB 20 0).
3. Pr ogra m OB 2 00 c al l in t he s tart -u p bl ock OB 20 for CP U 1
OB 200 is called by the OB 20 shown below in CPU 1 during the restart.
OB 20 LEN= yy ABS
SEGMENT 1
0000 :L KB 2 Manual initialization of
0001 :T FY 246 the pages
0002 :
0003 :L KY 1,100 The assignment list is entered
0005 :T FW 248 in DB 100 from data word 16
0006 :L KF+16 onwards
0008 :T FW 250
0009 :
000A :L KB 246 SF OB:
000B :JU OB 200 "Initialize"
000C :
000D :AN F 252.5 Block end if there is no
000E :BEC initialization conflict
000F :
001 0 : The er ro r hand li ng rou tine
0011 : is inserted here if an
0012 : initialization clonflict
0013 : occurs (e.g. stop, output
0014 : message on printer, or ...)
00xx :BE
Continued on the next page
10
Applications
CPU 928B Programming G uide
C79000-B8576-C898-01 10 - 77
Application example continued:
4. Pr ogra m call s fo r the fu ncti on b lo cks in F B 1 of the C PUs:
The user program on each CPU is extended by the RECV-DAT and SEND-DAT
call. Function block FB 1 shown below is for CPU 1. For the other CPUs,
the input parameter CPUN (CPU number) must be modified.
FB 1 LAN=yy
SEGMENT 1 0000
NAME:EM-SE
0000
0000 :C DB100 Link list DB 100
000 1 :JU FB 10 1 Rece ive th e inpu t
0002 : data blocks
000 3 NA ME :R ECV- DA T
0004 CPUN : KF+1
000 5 ER WA : FY0
0006 :JC =ERWA Abort if error/warning
0007 :
0008 :
0009 : Here, the cy clic use r prog ra m
000A : that reads data from the inpu
000B : data blocks and enters data in
000 C : the ou tp ut dat a bl ocks i s
000D : inserted.
000E :
000F :
0010 :C DB 100 Link list DB 100
0011 :JU FB100 Send the output
0012 : data blocks
001 2 NA ME :S END- DA T
0013 CPUN : KF+1
0014 ERWA : FY0
0015 :JC =ERWA Abort if error/warning
0016 :BEU
0017 :
0018 ERWA : Run an error handling routine
0019 : following an error/warning (here,
001A : the error handling routine is
001B : inserted, e.g. stop, output error
001C : message on printer or screen,
or ..)
00xx :BE
Applications
CPU 928B Programming Guide
10 - 78 C79000-B8576-C898-01
Contents of Chapter 11
11.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 4
11.2 PG F u nction s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 5
11.2.1 Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 6
Memor y configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 6
Output address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 7
11.2.2 M emo ry Fun ctions an d Transfer Fu n ction s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 7
Overall reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 7
Compress me mory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 - 7
Tr ansf e r b lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 8
Delete b lock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 9
11.2.3 Program T e st. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 - 9
Start/stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 9
Status b lock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 1 0
Program test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 1 1
Status variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 16
Force . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 17
Force variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 17
11.3 A ctivities at Checkp oint s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 - 18
11.4 Serial Link PG - PLC via 1st or 2nd Serial Inter face. . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 19
11.5 Parallel Operation of Two Serial PG Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 20
11.5.1 Inst allation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 22
11.5.2 Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 22
11.5.3 Sequence in Certain Operating Situations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 24
Parall el operat ion with short-running functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 24
Parallel operatio n wit h long-running functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 25
Parallel operation with cyclic functio ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 25
11
PG Interfaces and Functions
11
CPU 928B Programm ing Guide
C79000-B8576-C898-01 11 - 1
11P G Interfaces and Functions
This chapter explains how to connect your PG to the CPU 928B and
the fun c ti ons pro v ided by t he PG s oftware w it h whi ch yo u ca n te st
yo ur STEP 5 program.
If you only use the standard PG interf ace (1st serial PG interface) y ou
do not n eed to read Sec ti on 11.5. This se ct ion tell s you abo ut further
int erfac es wit h whi ch yo u ca n co n n ec t a PG t o your CPU. It also
contains points to note if you use PG functions on both interf aces.
11
CPU 928B Programming G uide
C79000-B8576-C898-01 11 - 3
11.1 Overview
You ca n lo ad a n d te st you r u ser pro gra m usi n g the on l ine function s of
t he STEP 5 software.
To use these f unctions, the CPU must be connected to the PG. The
followi ng inter fa ces are available for this link:
•• lin k vi a the seri al stan d ard int erfac e "PG - PLC ",
•• lin k via th e 2nd serial i nte rf a ce o f th e CPU 928B .
T he PG functions can operate si multaneousl y on the two serial
interfaces. PG functions provide the following support for installing
and testing your STEP 5 program:
Function Section
Info
Size of the inter n al RAM and
free user me mory "M emo ry configuration"
List of loaded blocks "Output DIR"
Di splay con tents of memory
w ord s/b yt es and I/O b yte s "Output address"
Me mo ry ma nagemen t
Delete the w hole mem o ry " Ove r a ll reset"
Create more me mo ry spac e "Compre ss memo ry
Manage blocks "Tr ansfer /delete blocks "
Program test
Start/stop CPU "Start/stop"
Test the operation sequence in a
block "Status b lock"
T est sin gl e progra m step s "Pro g ram te st"
Di splay sig n al stat e of process
variables "Status variables"
Ou tpu t sig nals i n the stop m ode "Force"
Display/chan ge process variables "Force variables"
Table 1 1-1 F unctio ns f or inst allatio n an d testin g
Overview
CPU 928B Programming Guide
11 - 4 C79000-B8576-C898-01
11 .2 P G Func tions
Note
The terms used in this section f or the PG functions m ay in some
cases di ffer from the terms in your PG software.
Please refer to your STEP 5 manual.
Cal ling and using functio ns
How to c all and u se th e in divid ual PG fun ction s i s des cribed in t he
STEP 5 manual.
Execution
The PG functions are executed at de fined points in th e progra mmable
con tro ll er. There are poin ts in t he syst em program (= syste m
c hec kpoints) and points in the user program (= user checkp oints).
System checkpoints
In the STOP mode there is the system checkpoint "stop" that is ca lled
regularly.
In the RUN mo de t h ere is th e system ch ec k poi nt "cycle" that is called
at th e end of th e progra m processing level CYCLE be fore the process
image is updated.
If the CPU is in t he WA IT state, th e system chec k po i nt "w ait sta te" is
called regularly.
There is also a ti me-dependent s yste m checkpoint "asynchronous".
This system checkpoint is inserted asy nchronously during program
execution.
User checkpoints
In the te st fun ct ion s STATUS an d PR OG RA M TEST, us er
che ck poi n ts are us ed . A us er che ck po in t is call ed when a c omman d is
execut ed that is ma rked accordi ngly b y th e P G.
11
PG F unctions
CPU 928B Programming G uide
C79000-B8576-C898-01 11 - 5
WA IT STATE
So far you have come across the modes STOP, RESTART and RUN.
When using the online function PROGRAM TEST, the CPU has a
fou rth mode , th e WA IT ST A TE . Wh e n the CPU is in t he W A I T
STATE, you can call further online functions.
Features of the wait state
•• The user program is not processed in the wait state.
•• LEDS o n the front panel: RUN-LED: off
STOP-LED: off
BASP-LED: on
•• Al l the ti mers are "frozen", i.e. no timers are runni ng (i.e. the
timers are not changed). All syste m ti mers such as for closed loop
con trol a n d time-d riv e n pro ce ssin g are also stopped.
Onc e the CPU ex it s t h e WAIT ST A TE th e ti me r s start runn in g
again.
•• Causes of interrupts, for example PEU, BAU, MPSTP or the stop
swit ch a re regi stered in th e WA I T STA T E, ho we ve r, the re is n o
reaction.
Interrupts
If caus es of inte rru pts are re gist ered in t he WAIT STA T E, the
appropriate program processing levels are called i mmediately after the
WAIT STATE is exited.
If NAU occurs, the WAIT STATE is exite d and the PROGRAM
TE ST onl in e fun ct io n i s abo rte d . F ollo win g POW E R ON, BAR BEND
is marked in the control bits. You can only exit the stop m ode with
COLD RES T ART.
11.2.1
Information
Memory configuration
The "Memory con figuration" programmer function shows you the
high est u sa ble ad d ress of t he R AM s ubmod u le ("0" is d ispl ayed i n the
cas e of E PROM) and the la st address of the me mory s ubmod ule
occupied by blocks of the user program.
PG Fu n ctions
CPU 928B Programming Guide
11 - 6 C79000-B8576-C898-01
Output address
With t he "o utput a d dre ss" fu nct io n, yo u ca n display th e con te nts of
memory and I/O addresses in hexadecimal f ormat. You can access all
ad d ress es (RAM, S5 bus, are as with no modu l es assign ed). I n the
process image area no ADF is triggered, in the I/O area there is no
QVZ.
In the area s ad dressed as byt es (f l ag s, pro ce ss image) th e h i gh byte i s
represe nte d as ’FF’.
In the I/O area, the high byte is output as " 00" in the case of
acknowledging addresses. If a n I/O module does not acknowled ge, the
high byt e is display ed a s "FF".
11.2.2
Memory Functions and
Transfer Functions
Ov erall reset
With the function "delete all blocks" you can carry out an overall reset
of th e CPU fro m th e PG . T he o v eral l reset i s carried o ut
unconditi onall y (refer to Section 4.3.2).
If the CPU is in REST A R T or R UN w h en "De le te a ll block s" is
call ed , a transi ti on t o th e Sto p stat e is exec u ted first. Organ iz at ion
block OB 28 is called here if it is loaded.
Note
Ov eral l re se t is n o t pe rmissible as lo ng as "P rog ram te st " is activ e!
Compress memory
Thi s fu ncti o n optim iz es th e memo ry spac e o c cu pie d by bl oc k s. T h e
spac e ta ken up by bloc k s mark ed a s i nva li d is ov e rwri tt en by th e valid
blocks of the user program (the block is rewritten to a different
me mory are a). Fo l lo win g thi s, th e blo ck s a re lo ca te d fro m the
beginning of the memor y, one after the other wit hout gaps between
them.
Thi s f unc tion is perf ormed separately in the R AM submodule an d in
the DB RAM a nd is ex ecuted at th e sy stem ch eck points "cycle" and
"stop".
With the CPU 928B, the COMPRESS MEMORY f unction is always
possible in the STOP mode, even if the BST ACK is not empty.
11
PG F unctions
CPU 928B Programming G uide
C79000-B8576-C898-01 11 - 7
Caution
Aft er C OM PR ESSING mem o ry in th e STOP mode, you c an o n ly
rest art wit h a C OLD RESTA RT. T h e IST ACK and B STAC K a re
not updated.
Power down during
compressing
If there is a power do wn d urin g the co mpres sin g functi on, n o furthe r
block is rewritten. I f you call the COMPRESS MEMORY function
again f ollowing the return of power, the f unction is continued.
Errors in the block memory
The COMPRESS MEMORY function detects the foll owing errors in
the block memo ry :
•• wr ong b l ock l ength
•• corrupted pattern "7070" in the block header
•• invalid block type (with OBs invalid block number).
The functio n is then terminated and a message is displaye d at the PG.
Yo u must th e n perfo rm an o v erall re se t. Th e fun ct ion c an o n ly be
ca ll ed a g ai n fol low ing t he overall re se t.
Note
You cannot use the COMPRESS MEMORY function as long as
the PROGRAM TEST is active.
Transfer block
With this f unction y ou can transf er new or existing logic and data
blo ck s to t he u se r me mory of th e C PU or t o th e in te rnal DB-RA M o f
t he CPU.
If a blo ck already exists in the user me mory of the CPU, it is declared
invalid and the new block becomes valid. A block will only be
declared invalid when it is not being processed.
PG Fu n ctions
CPU 928B Programming Guide
11 - 8 C79000-B8576-C898-01
Delete block
With t hi s fun ct ion you d e cl are a l o gic or data block i n the u ser
memory as invalid. A block will only be declared invalid when it is
not being processed.
T he space occ upied by these blocks can be used for other blocks via
the "Compress memory" funct io n.
11.2.3
Program Test
Start/stop
When yo u use th e STA RT and STOP PG func ti on s, o peratin g th e PG
c orresponds to manua l operati on.
You can put th e program ma bl e co n tro ll er i nt o th e STOP mod e by
cal ling the STOP function wh ile t he controller is in the RUN mo d e.
You will see the followin g display for the CPU connected to the PG:
STOP-LED: on
BASP-LED: off
P G-STP is marked in the control bit d isplay. In multiprocessor
operati on, the MP-STP control bit is set for the other CPUs.
You ex it t he SOFT STOP sta tu s wit h a COLD RESTART o r WA RM
RESTART. In the single processor m ode, the CPU exits the stop
mode. In multiprocessor operation, the restart type is registered
i nitially (the NEUST or MWA control bit is set). Ho wever, the CPU
stays in the soft STOP mo de until all CPUs are initialized for
multiprocessing. With the next operation "s ystem start" you can start
th e prog ramma ble co ntro ll er. This correspon ds to operation v i a the
c oord inator (switch to RUN).
You can call the START PG function in the m ultiprocessor m ode to
se lect th e restart type you w a nt for all t he C PUs you are u si ng . After
that, yo u c an start the prog ramma bl e con troll er w i th t he last CPU.
•• COL D RESTART PG f unction:
M A NU AL COLD RESTAR T of the CP U i s execut ed .
•• WARM RES TART P G functi on:
Depending on the setting in DX 0, MANUAL WARM RESTART
or RETENTIVE MANUAL COL D RESTART is executed.
11
PG F unctions
CPU 928B Programming G uide
C79000-B8576-C898-01 11 - 9
Statu s bl ock
You ca n call the "stat us " PG fu ncti on to t est rel at ed o pera ti ona l
sequences (STEP 5 operati ons) in one block at any l ocation i n the user
program.
T he current signal status of operands, the accumulat or contents, an d
the R LO a re ou tput on th e PG screen for every exe cu ted operatio n in
t he bloc k (i.e., step mode). You can also use this function to test the
parameter assignment of functi on blocks (i.e., field operation):
The signal status of the actu al operands is displayed.
Ca lling the functi on an d
specifying a b reakpoint
When you call the " status" f unction on a PG and enter the type and
nu mber of the block you wa nt to test (possibly including the nesting
se que nce and se arch k e y), you e nter a breakpo in t .
Whe n the "stat us" func ti on is cal le d duri ng pr ogra m proce ssing in the
RUN m ode, program processing continues u nti l it reach es th e
ope rat io n ma rked by the spec ifie d breakpo in t in t he c orrect nest in g
sequence. Then the system program executes each of the monitored
operations up to the operatio n boundary, outputtin g the processing
resu l ts to t he PG .
Ca lling the functi on in the
STOP
mode
You can auch activate the STATUS f unction in the STOP mode. You
can then carry out either a COLD RESTART or a MANUAL WARM
RES TA RT. Th e CP U execu tes t he p rog ra m up to the marked
operati on. The data for the desired operatio n are then output. This
mea ns that the "Status" fu nctio n is also suitable for, e.g., testing the
user program in restart or in the first cycle.
Note
Th e resu lts o f operatio n proc es sin g a re no t outpu t in e ach of t he
program cycles.
Nesting and inte rruptions
A seque n ce of opera ti o ns marke d by a break point is comple te d even if
a di f ferent pro gra m exec u ti on l ev e l (e.g ., a n error OB or in te rru pt OB)
is act iv ate d and proces sed . With this yo u can see whethe r da ta has
been changed by nested program sections.
If an i nt erru pt ion i n a n e ste d prog ram ex e cu tio n le ve l puts the CPU
int o the STOP mode , d a ta is o ut put u p to t h e o pera ti on t hat w as
executed before th e program exec uti on levels changed. The data of
the rem aining operations is padded with zeros (the SAC is also 0).
If th e CPU ch an ges from one operat ing mod e to a n other (e. g., R UN -
STOP - MANUAL WARM RE STA R T), the functi on re ma in s a ctive.
"Sta tu s" is te rmina te d by pressin g t he a bort key on th e progra mmer.
PG Fu n ctions
CPU 928B Programming Guide
11 - 10 C79000-B8576-C898-01
Program test
You can call the "p rogr am te s t" fun ction to te s t i nd ividu al prog ram
steps an ywhe re i n your u ser pro gra m. When yo u do th is, you s to p
prog ram processing and a ll ow the CPU to proces s o n e opera ti on a f te r
th e o ther. The PG o utput s t he c u rre nt signa l status of o pera nds, th e
accumulator conten ts, a nd the RLO for each operation execu ted.
Ca lling the functi on an d
specifying the first
breakpoint
To call the "program test" function, specify the type and number of
the block (if necessary with nesting sequence) you want to test. At the
P G, mark the first operation, whose data are to be output. This is how
you s pe cif y th e first break poin t.
BAR B is marked in the control bits. Command ou tput is disabled
(B ASP LED = o n).
Caution
If you set Test mode on the coordinator, enter the block type and
block number (if necessary, with nesting sequence) of the block
t o be tested. At th e PG, mark the first operation whose data are to
be output.
Th i s i s h ow you s peci f y the first bre akpoi n t.
BAR B is marked in the control bits. Command ou tput is disabled
(B ASP LED = o n).
Ca lling in RES TA R T and in
RUN
When you specify the first breakpoint during p rogram processin g,
the CPU continues processing the program until it reaches the
operation marked by the specified breakpoint. The operation is
e xecuted up to the operation boundary. (Th e DO FW and DO DW
operations are processed including the substituted operation.)
The CPU then goes to the WAIT STATE. The data of the marked and
las t executed oper ation a re output ther e.
Ca lling test funct ions in SO F T
STOP
You can al so ca ll t he "prog ram t est" func ti on and specify a n init ia l
break po int when the C PU is in t he soft STOP mode. Th e CPU
remai ns in t h e s oft STOP mode, and you can e xec ut e eith er a C OLD
RESTAR T or a MANUAL WAR M REST ART. The CPU processes
th e program up to t he marked operatio n a nd i t proce eds as ou t line d
above.
11
PG F unctions
CPU 928B Programming G uide
C79000-B8576-C898-01 11 - 11
Executing the funct ion and
specifying anothe r
breakpoint
Initial situation : the CPU is in t he W A IT STA T E.
To continue the function, you have two possibilities:
1. Speci fy the next operation as the following breakpoint:
Move the cursor down to the nex t operati on to speci fy the following
breakpoint.
The CPU continues by processing this operation up to the operation
boundary. Then the CPU outputs the data and waits for further
instructions from the PG.
However, if a nested program
exec ution level interrupts operation processing at the following
breakpoint, the CPU processes the nested program first. Then
the CPU returns to the 2nd breakpoint that you specified.
Note
You cannot specify a following breakpoint when the CPU is in
the STOP mo de .
2. Specify a new breakpoint:
At the PG, specify any ot her operatio n in the same bloc k
or in a di fferent block. The CPU continues program processing
unti l i t re ach es th e ne w breakpo in t . T he o perat ion i s proc es sed
fully. The CPU then goes to the WAIT STATE and outputs
the data there.
Yo u can al so run t he progra m t hrough a w hole c ycle (cyclic t est), by
setting the breakpoint at the same operation as previously in the
WAIT STATE. R emember, ho wever, that the operation must not be
in a program l oop. In t hi s c ase, th e lo op is run t hro u gh o n ce ; and th e
program execution does not go beyond the end of the cycle.
Note
You c an c al l ot h er fu nc ti ons , su c h as OUTPUT DI R, STAT US
VARIABLES or FORCE VARIABL ES in the WAIT STATE.
Once program execution is continued after exiting the WAIT
STAT E, the ti me rs and syst em t imers co ntin u e to run un t il th e
n ext breakpoint is reached.
PG Fu n ctions
CPU 928B Programming Guide
11 - 12 C79000-B8576-C898-01
Cancelling the
breakpoint
If a specified breakpoint has not yet been reached, you can cancel it
by pressin g the break key on the PG. The CPU then changes to the
WAIT STA T E. You c an t h en se le ct a n ew break poi nt o r ca ll
PROGR AM TEST END.
Aborti ng t he function
If you c al l t he PR OG RAM T EST END funct io n d u rin g pro g ram
execution, in the WAIT STATE and in the STOP MODE, you can
terminate the fun ction. T he CPU goes to t he STOP mode (or remains
in t h e ST OP mode ). Th e STOP LED fla sh es slo wl y. B ARBE ND is
marked in the control bits. Following this you m ust perform a COL D
RESTART.
If an i nterfac e error (brea k on t he PG cable) o r NAU oc curs d urin g the
PROGRAM TEST f unction, the f unction is terminated as described
above.
Nesting
W h en the P ROGRAM TES T function is acti ve , other p rogram
processing levels can be inserted after the WAIT STATE is exited.
When the operatio n is processed at the breakpoi nt and if a di fferen t
prog ram processing le vel is ca ll ed a t th is poin t (e .g . a n error OB , a
process interrupt or a ti me-drive n interrupt) this is inserte d and
completely processed only when the W AIT STATE is exited again.
Note
T he data are read at the operatio n boun dary and output there.
Program processing levels which may have been inserted a fter
thi s poin t are no t yet pro cessed.
T he sequen ce o f the "program test" functi on is ill ustrated in Fi g. 11-1.
11
PG F unctions
CPU 928B Programming G uide
C79000-B8576-C898-01 11 - 13
If reque sts suc h as PEU, MP-ST P, sto p sw i tc h et c. occu r d u ri ng the
WAI T STAT E, th ese a re o n ly re gistered . Th es e can beco me act iv e
imm e d iat ely after the CP U exits the WAIT ST AT E: A program
processing level is inserted or an interrupt leads to the STOP mode.
The reacti on depends on the order in whic h the events occurred.
Simultaneous requests have an order of priority .
Note
When t he C PU i s i n the WAIT ST ATE a nd t h e i nsertio n o f a
prog ram pro ce ssi n g le ve l is requested , yo u ca n se t a brea kpo in t at
an o perat io n i n th e in se rt ed progra m s ec ti on . This al lows you, for
exam ple, to monitor the QVZ error OB im mediately after an
operation that triggers a QVZ.
Execute ope-
ration and
read data
Execute ope-
ration and
read data
< <<<<<
< <<<<<
1st breakpoint
WAIT STATE (output data)
WAIT STATE (output data)
Process interrupt, timed
interrupt, error OB
Process interrupt, timed
interrupt, error OB
Next
breakpoint
Fig. 11-1 Sequence of "program test"
PG Fu n ctions
CPU 928B Programming Guide
11 - 14 C79000-B8576-C898-01
Interruptions
•• Program processi ng (RESTART/ RUN) → STOP mode:
If an interrupti on occurs during program processi ng (e.g.,
multiprocessor stop, I/O not rea dy/STOP, error OB not
program m ed etc.) be fore th e program rea ches the spe cified
bre ak poi n t, th e CPU go es int o th e STOP mod e i mm ed i at el y. I f
you execute a COL D RESTART or a MANUAL WARM
RESTA R T , the "program t est" fu nc ti o n is sti ll i n effec t an d the
breakpoint is stil l set .
•• Program processing at breakpoint (RESTART/RUN) → STOP
mode:
If stop conditions occur at the breakpoint or following breakpoint
d uring program processing, the CPU goes directly into the soft
STOP mode and outputs the data.
If yo u d o no t spec ify a new break poi nt wh il e the CPU is in t he
STOP mode, the "program test" function is still in e ffect a fter the
restart.
•• Wait state → STOP
C auses of interrupts occurring in the WAIT STATE (e.g. MP-STP,
PEU, I/O n o t re ad y, sto p sw it ch) or resul ti ng fro m t h e prev i ous
operation (error causing the CPU to stop) are registered, however,
the CPU re ma ins in t he WA IT STA T E. Th e cau ses o f inte r ru pts
only bri ng a bout a transiti o n to the STOP mo d e afte r you h a ve
speci fied a new breakpoi nt in the WAI T STATE and the CPU has
e xited the WAI T STATE. The specifie d breakpoin t is not reach ed.
If y ou then carry out a RESTART (COL D RESTART or
MANUAL WARM RESTAR T) the new brea kpoin t remains set.
Note
If y o u switch the CP U to stop usi ng the s top swi tch wh i le i t is in
the WAIT STATE, it only goes into the STOP mode af ter exiting
the WAIT STATE.
If ca us es of i n te rrupts bri ng t h e CPU t o th e STOP mod e du rin g
th e PR OG RA M TE ST, th e PROGRA M TEST functio n (a n d any
bre akpo in t you may have specifi ed) remai n ac ti ve a fter th e re sta rt.
11
PG F unctions
CPU 928B Programming G uide
C79000-B8576-C898-01 11 - 15
Statu s variables
Usin g the "status variables " function, you can display the current
sig nal states of certain operands (process variables).
The function ac tivates sys tem checkp oint s in the CY CLE, in the
STOP MODE a n d in t he WAIT STA T E.
When a ch ec kpoi nt is reached, the PG displays the present si gnal
status of the desired process variable. You can speci fy all process
variables (in pu ts, out put s, fl ags, ti me rs, co unt ers an d da ta words). No
a ddressing error (AD F) is triggered in t he process i mage area when
ac ce ssi n g an a dd res s fo r which t h ere is no I / O av a il able.
The f unction during program
execution
If the function is activate d in the RESTART or RUN modes, progra m
execution is continued until the system checkpoint "cycle" is reached.
The signal states of the operands are then scanned and output at the
e nd of t he cycl e. Inp u ts are re ad from the process image. Provid i ng
the f unction is not aborted, the signal states are updated during
program execution. In this case the signal states are not scanned at
ever y syst em check point.
If the system checkpoint " cycle" is not reached, the signal states are
not output (e.g. in a continuous loop in the user program ).
T he function in the STOP
mode
If the STAT US VAR IAB L ES fun ct io n is acti v e i n the STOP mode,
the signal stat es of the operands ar e output as th ey stand at the sy stem
checkpoint "stop" . The important point to note here is that the inputs
are scanned directly (not fr om th e proces s ima ge) and ou tput. This
fea ture, for example, al lows you to c h eck whe th er an i npu t sig n al
actu a ll y reac hes th e CPU. Ev e n in multi p roc essor o peration , you c an
speci fy all inputs regardless of the assig nme nt in DB 1. The outputs
are read from the process i mage.
T he function in the WAIT
STATE
Yo u can al so call the STA TUS VA R I AB LES fun c ti on whe n th e CPU
is in the WAIT STATE caused by the PROGRAM TEST function.
The signal states of the operands are scanned at the system checkpoint
"wait state" and output. As in the stop m ode, the inputs are scanned
directly an d t he o u tputs are re ad fro m t h e p roc ess image.
Changing the operatin g
st ate/ terminating t he f un ction
When t he C PU ch an ges fro m on e mod e to a no the r (e.g. RUN →
STOP → M A NUAL WARM RESTART), the fun ction rem ains
ac ti vat ed . ST A TUS VARI AB LE S i s term i nat ed by pre ssi n g the bre ak
key on the pr ogr a mmer.
Note
The variables are not output in every program cycle.
PG Fu n ctions
CPU 928B Programming Guide
11 - 16 C79000-B8576-C898-01
Force
Using the FORCE function you can set the output bytes of the
program mable co ntro ll er t o a partic ula r signal state di rectly (avoi ding
the process im age) or you can recognize process interface m odules
(dig it al periph era ls 0 to 127) that do no t ac know l edg e (messag e on t he
P G). You can check an d directly control the process devices
(ac tu at o rs e.g. mot or, va lv e ) su ppl ie d wit h sig nals by t he outputs.
Note
The "force" function is only permitted in the stop mode.
Function sequence
When you call the f unction in the STOP mode, the command output
disable f unction is cancelled (BASP = inactive). The whole di gita l
peripheral area (F000H to F07FH) is cleared, and the value "0 " is
written to each address. You cannot interrupt this f unction while the
periph erals are be in g c le ared.
Th e peripheral o u tpu ts are forc ed i n byt es directl y an d wit hou t
af fecting the process output im age.
In mult ipro ce ssor ope rat io n , you can force all peripheral outputs
(reg ard le ss o f t he peri phe ra l ass ign ment i n DB 1).
When the function is active (message "End of force fct" on the PG),
you can perform a COL D RESTART or a MANUAL WARM
RESTART. If the CPU once again changes to the STOP mode, you
ca n u se th e force fu ncti o n ag ai n . T he process int erf ac e out pu t m odules
are not cleared in this case.
T ermi nating the functio n
You t ermi nate the fu nction b y pressing the break key o n the PG. The
command output disable function is once again activated
(B ASP LED = o n).
Force variables
Using the PG function FORCE VARIABLES, you can change the
values of operands (process variables) once. You can do this in any
CPU mod e. Yo u ca n spec ify al l proce ss va ria bl es . I f you a tt empt t o
access an address in the range of the process im age for which there is
no I/O, no ADF is triggered.
The mod ificat ion becom e s effe ctive a sync hr onous ly to the sy s tem
c hec kpoints, i.e. not till th e en d of the cycle. Remember that the
forced values can be overwritten later (e.g. by the user program or
when th e process image is updated).
Note
The PG forc es th e I , Q a n d F pro c ess v ariables i n bytes an d the
DW, T a nd C var i ables in wor ds .
If you force several operands, the modi fied b ytes (for DW, T
and C the words) are change d in the CPU memor y, distributed
over several function call s.
11
PG F unctions
CPU 928B Programming G uide
C79000-B8576-C898-01 11 - 17
11.3 A ctivities at Ch eckpoints
The table b elow shows you which activities of the PG fun ctions ar e
execut ed at the ch eckp oint s.
Act ivities of the onli ne
functions
S ystem checkpoin t User
check-
point
"Stop" "Cycle" "Wait
state " "Asyn-
chronous
"
Input o f th e address:
writ e da ta 1)
Blo c k in put:
decl are block as valid
Delete block
Compress memor y:
s hif t bl ock s 1) 2)
START/STOP
OVERALL RE SET
STATUS: read and output data
STATUS VARIABLES: read
and output data
P RO GRAM TEST:
preset breakpoints
read and output data
FORCE (process inter face modules)1)
FO RCE V ARIABLE 1)
*
*
*
*
3)
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1) Ac tiv ities di s trib uted ov e r m o re than 1 system ch e ckp o in t
2) Maximum one block pe r system ch eckpoin t
3) After compressing the memory in STOP, only COLD RESTART permitted.
T able 11 -2 Activities a t che ckpoint s
Ac tivities at Checkpoints
CPU 928B Programming Guide
11 - 18 C79000-B8576-C898-01
11.4 S erial Link PG - P LC via 1st or 2nd Serial Interface
For th e seri al li n k PG - PLC t h ere are the fol low ing po ssibi li ti es :
•• Direct link to the CPU via the standard cable.
•• Link to the PG via the coordinator COR 923C. In this case the PG
is con ne ct ed v i a t h e c able to th e co o rdin at or. Th is me ans th at the
1st serial interface is no longer av ailable.
•• Link to the PG via a PG multiplexer 757. The permitted cables can
be foun d i n the S5-135U/ 155U Syst em Ma nu a l (/2/ in Cha pter 13).
•• Link to the PG via SINEC H1/L2/L1 and " swing cable"; the
CO R 923C or PG multiplexer can be connected i n the link.
11
Serial Link PG - PL C via 1st or 2nd Serial Interface
CPU 928B Programming G uide
C79000-B8576-C898-01 11 - 19
11.5 P arallel Operation of Two Serial PG Interfaces
You ca n us e th e sec on d interf ace on t he CPU 928B (SI 2) as a PG
interface in e x actl y th e same way as the first i nt erface.
To be able to link your PG via this interface, you must also order the
PG interf ace module in addition to your CPU 928B (the order num ber
is li sted in th e S5-135U/ 1 55U Syst em M a nu a l /2/).
A ll the PG fun ctions are available on both interfa ces. The following
se ctio ns c on tai n on l y th e in f ormatio n th a t you requ ire if yo u work
with PGs or OPs o n bot h interfaces simultaneously.
PG
SI1
SI2 PG
Interface
submodule P
G
Fig. 11- 2 Using the second interface as a PG i nterface
Parallel Op eration of Two Serial PG Interfaces
CPU 928B Programming Guide
11 - 20 C79000-B8576-C898-01
Examples of confi g u rations
CPU 928B CP 143
SINEC H1
SI1 PG connected via SINEC H1 and COR C
SI2
"swing cable"
PG connected directly
F ig . 11-3 First example of a co nfig uratio n
CPU 928B
OP PG
SI 2 PG connected directly
(for programming)
SI 1 OP connected directly
(for operating and monitorin
g)
Fig. 11- 4 Second exampl e of a configuration
11
Pa rallel O perati on of Two Serial P G I nterfa ces
CPU 928B Programming G uide
C79000-B8576-C898-01 11 - 21
11.5.1
Installation To us e the s econd inte rfa ce of the CPU 9 2 8 B as a P G in ter fa ce,
follow the steps outl ined b elow :
Step Action
1 In sta ll the P G sub m o dule in the CPU 928 B.
2 Conn ect th e PG to t he seria l in ter fa ce SI2.
11.5.2
Operation If you use the second interface as a PG interface then initially the full
range of f unctions of the standard PG interf ace is available on each
interface. This rem ains true, providing the individual f unctions do not
influence each other, i.e., called sequentially one af ter the other.
To understand the exceptions to this, the PG fun ctions can be divided
int o thr e e gr oups:
Group Name
Short-running functions Functions that execute a job and then are
terminated.
(e.g. " transf er" , "delete" etc.)
Long-running functions Functions that process a fixed number of
jobs:
- "force ",
- "program test".
Cyclic functions Functions that execute a job repeatedly
until y ou term inate them :
- "status block",
- "status variables ",
- "force variables ".
Caution
With long-running and cyclic f unctions you must coordinate the
activation of these f unctions on both PGs.
Parallel Op eration of Two Serial PG Interfaces
CPU 928B Programming Guide
11 - 22 C79000-B8576-C898-01
The table b elow lists the pairs of fu nctions th at you c annot wor k wit h
simultaneously.
F unction a ctive
on the first PG: You must not activate this
function on the second PG
"Forc e" Any func tion
"Prog ram te st " Any fun c ti on
A "st at us" func ti on " "Fo r ce "
A "status " functi on" "Progr am test"
A "status" fun ction" " Ov erall rese t"
"Stat us" o n lo ng running block s
or blocks which are not processed Any fun c ti on
If you attem pt to start one of the illegal functions, the second PG
displays an error messag e, e.g.: "AS function disabled: function
active".
T he same error message or "Overflow in data exchange with PG"
appea rs if th e CPU 928B is cu rren tl y processin g func ti ons of t h e othe r
P G, which prevent your PG accessing the CPU wit hin the monitoring
time. Your input is then rejected. Repeat your input once the functions
a r e complete d on the other P G.
Note
Owing to the different performances and range of functions, time
monit o rin g and the respon se to e rro rs i s n ot i d en ti ca l in a ll PGs
a nd OPs.
If you activate the function " mem ory configuration"
si mult an e ousl y o n bo t h PG s, t h e displays may be in co rre ct .
Caution
If you input, correct or delete blocks online on both PGs
simultaneously, you must make sure that the blocks are not
protected by t he o the r PG bef ore you acce ss th em .
"Status" of a block which is not processed or "status" in the STOP
mode blocks the other interface for all functions.
Tabl e 11-3 F unct io ns whic h ca nnot r un s im ul ta ne ous ly o n b ot h PG s
11
Pa rallel O perati on of Two Serial P G I nterfa ces
CPU 928B Programming G uide
C79000-B8576-C898-01 11 - 23
11.5.3
Sequence in Certain
Operat ing Situations
Parallel operation with
shor t-ru nn in g fun ction s
If you work with PGs on both interfaces simultaneously, both PGs
wan t to e x ec ut e th ei r fun c ti on s in d epen d en t ly o f ea ch o t he r. As lo n g
as they stagg er the jobs they send to the CPU, the jobs will be
processed in the order in which they arrive.
The situation may, however, arise that the CPU 928B either receives
two jobs simultaneously or receives a job from the second PG while a
j ob from the first PG is still active.
Since si multaneous processing is not possible, the jobs are processed
one after the other; the second job is, however, delayed by such a
short time that it is hardly noticeable for the user.
W hen jo bs a re sent simul taneously, th e se que nce is as follows:
From this seque nce, you can see that both PGs can operat e
i ndepen dently from each other, but that the one nevertheless affects
t he other.
It is possible that both PGs process the same block si multaneousl y or
that a block cu r re ntl y be in g processed by o n e PG is de leted by th e
other PG.
With this conf iguration, you must always take into account the way in
which input at one PG af fects the other PG.
Input at keyboard of PG 1
Interpretation of input 1 in PG 1
Job1transferredtotheCPU
Job 1 processed in the CPU
Results of job 1 transferred to PG 1
Results of job 1 interpreted
Results of job 1 displayed
on PG 1
CPU 928B
User on PG 1
Job2transferredtotheCPU
Job 2 processed in the CPU
Results of job 2 transferred to PG 2
Results of job 2 interpreted at PG 2
Results of job 2 displayed on PG 2
Input at keyboard of PG 2
Interpretation of input 2 in PG 2
*
*
*
*
User on PG 2
Here PG 2 must wait
until the CPU
processed job 1.
Fig. 11-5 Handling simultaneous jobs
Parallel Op eration of Two Serial PG Interfaces
CPU 928B Programming Guide
11 - 24 C79000-B8576-C898-01
Parallel operation with
lo n g-runn in g fu n c tion s
The long-runn ing functions "force" and ""progra m test" cannot
i nterrupt other functions and ca nnot be interrupted b y other functi ons.
T hey can therefore n ot be executed parallel to other functions,
i.e. they are treated as a standard job "en bloc".
Parallel operation with
cyclic fun ction s
Cyc lic fun ctio n s c an be ex e cute d bot h paral le l to o the r cycl ic a nd t o
short-runni ng functio ns. The fo llowin g exa mple sho ws the standar d
sequence of the "status variables" function.
PG 1 informs the CPU
of the variables
to be output.
PG 1 requests the
current data.
PG 1 requests the
current data.
PG 1 requests the
current data.
PG 1 requests the
current data.
PG 1 must wait until
the CPU is free.
Job sent by PG 2 is processed
PG 2 must wait until
the CPU is free.
PG 2 sends a job
PG 2 job is complete
CPU 928B
User on PG 1 User on PG 2
Fi g. 11- 6 Typi cal se quenc e of a c yc lic funct ion and pa r alle l short -r unni ng f u nctio n
11
Pa rallel O perati on of Two Serial P G I nterfa ces
CPU 928B Programming G uide
C79000-B8576-C898-01 11 - 25
To allow a second PG to send a job t o th e CPU, the status function is
i nterrupted between t wo requests and then continued on c ompletion of
the in se rte d job. Sinc e th e inte r rupti n g funct ion requ ires CPU
facilities, the whole CPU system f acilities m ust be divided between
the two f unctions, e.g. the updating of the data output by the " status
variables " function takes so mewhat lon ger.
With both PGs working simultaneously , the sequence shown in Figure
1 1 .7 results.
This also applies when cyclic f unctions are active on both PGs; the
t wo P Gs then a ccess the P LC a lternat ely.
Parallel Op eration of Two Serial PG Interfaces
CPU 928B Programming Guide
11 - 26 C79000-B8576-C898-01
PG 1 informs the CPU
of the variables
to be output.
PG 1 requests the
current data.
PG 1 requests the
current data.
PG 1 requests the
current data.
PG 1 requests the
current data.
First job of PG 2 is processed
Second job sent by PG 2 is processe
d
PG 2 sends the first job
PG 2 sends second job
First job of PG 2 complete
Second job of PG 2 complete
PG 1 must wait until
the CPU is free.
PG 2 must wait until
the CPU is free.
PG 1 must wait until
the CPU is free.
CPU 928B
User on PG 1 User on PG 2
Fig. 11-7 Sequence of two parallel cyclic functions
11
Pa rallel O perati on of Two Serial P G I nterfa ces
CPU 928B Programming G uide
C79000-B8576-C898-01 11 - 27
Special feat ure with cyclic
functions on both PG s
If the interrupting function blocks the CPU 948 ("status" in a block
that is not executed) the interrupted function is also blocked. It can
only be resumed when t he i nterrupting fu nction is terminate d.
When working simultaneo usly with two PGs, the following sequence
results:
G eneral not es
If "sta tu s variabl es " , "fo rce va ria bl es " (w ith the sta tus di spla y ) or
" sta tus" is outp ut on one in ter f a ce and "comp ress memo ry", "d elete
block" or "trans fer block" o n the other, the status display can be
corrupted.
PG 1 informs the CPU
of the variables
to be output.
PG 1 requests the
current data.
(PG signals: status
processing active)
PG 1 requests the
current data.
PG 1 requests the
current data.
PG 1 must wait until
the CPU is free.
PG 2 must wait until
the CPU is free.
Job sent by PG 2 is processed
(PG signals: status processing active)
(PG signals: statement
not processed)
PG2 sends a new job
(e.g. "Status PB 9").
PG 2 job complete
PG 1 receives new data
PG 2 aborts the STATUS function;
The CPU processes the abort request
CPU 928B
User on PG 1 User on PG 2
Fig. 11-8 Sequence when a function blocks the CPU 928B
Parallel Op eration of Two Serial PG Interfaces
CPU 928B Programming Guide
11 - 28 C79000-B8576-C898-01
Contents of Chapter 12
Appen dix 1: Tec hn ica l Da ta of th e C PUs i n the S5-135 U. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 4
Appen d ix 2: Erro r Id e ntifi ers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 7
Error IDs in Syste m Data Words RS3 and RS4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 7
Error IDs in ACCU 1 and ACCU2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 10
Appendix 3: STEP 5 Operations n ot Co ntained i n the CPU 928B . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 16
Appendix 4: Id entifiers for the Program Processing Lev els . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 17
Appendix 5: Example "ISTACK Evaluatio n". . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 18
12
Appendix
12
CPU 928B Programm ing Guide
C79000-A8576-C898-01 12 - 1
12
Appendix
Th i s c ha pte r gi ves you addi tiona l in form a tio n on t he CPU 928B, su ch
as runtime comparison bet ween the CPU 922, CPU 928 and
CPU 928B, error IDs and level IDs and other information and
exp lan ations us eful fo r error diagnos tics
12
CPU 928B Programming G uide
C79000-A8576-C898-01 12 - 3
Ap pe ndix 1 : Tec h nic a l D ata of th e CPU s in t he S5 - 135 U
O peration / processing CPU 9 22 CPU 92 8 CPU 928B
Typical operation exec ution times for bit operations:
with
F, I, Q
D
formal operands
22 µs
37 µs
46 µs
1 µs
34 µs
25 µs
0.57 µs
3. 4 µs
2. 4 µs
Typi cal operatio n executio n t imes for word operati ons:
- load operations
L FY (byte)
L FW (word)
L FD (do uble word)
15 µs
15 µs
20 µs
12 µs
12 µs
16 µs
0.81 µs
0.94 µs
1. 6 µs
- fixed point arithmetic
- fl oating point arithmetic 26 ... 50 µs
51 ... 86 µs13 ... 24 µs
29 ... 69 µs0.94 ... 10 µs
9.1 ... 23 µs
Cyclic program execution (single processor mode)
Basic time calling OB 1/FB 0: 107/119 µs 147/149 µs 170/172 µs
Additional tim e for updating the
process im age dependent on the
numb er of I /O b yt es (n)
where 0 < n ≤128 33 µs
+ n * 6 µs18 µs
+ n * 1.58 µs18 µs
+ n * 2.13 µs
A dditional time for trans fer of
IPC flags depending on the
n umber of IPC flags (n)
where 0 < n ≤ 256 35 µs
+ n * 6.5 µs19 µs
+ n * 1.84 µs
n ≤ 128:
18 µs
+ n * 2.38 µs
n > 1 28:
36 µs
+ n * 2.38 µs
Additional tim e for tim er
processing depending on the
timer field length (TFL)
TFL =0 every 2.5 ms
50 µs every 10 ms
5 µs every 10 ms
1 µs
TFL #0
n = n umb er of c urr en tly
acti v e t imers (time base : 10 ms)
60 µs
+ TFL * 1.56 µs
+ n * 1.24 µs
200 µs
+ n * 0.35 µs
(where
0 <n ≤ 128)
400 µs +
n * 0.35 µs
(where
128 < n ≤ 256)
20 µs
+ ZBL * 1 µs
( n o diff er enc e
b e tween ac tive
and inacti ve
timers)
Appendix 1: Technical Data of the CPUs in the S 5-135U
CPU 928B Programming Guide
12 - 4 C79000-A8576-C898-01
O perat ion / pro cessin g CPU 92 2 CPU 9 28 C PU 9 28B
Interrupt-driven program processing
E xt ens ion of t he cycl e time by
insertin g an empty OB 2
(w ithout STEP 5 operations)
at an operatio n boun dary 367 µs330 µs 492 µs
Response time 300 µs280 µs 297 µs
Time-driven program processing
E xt ens ion of t he cycl e time by
in serting an empty OB 13
(w ithout STEP 5 operations)
at an operatio n boun dary 375 µs
340 µs fo r the
first time
i nterrupt OB
180 µs for
ea ch further
i nterrupt OB
due at the
same time
440 µs for the
first time
in terr u p t OB
200 µs for
each fu r ther
in terr u p t OB
due at the
same time
Clock pu ls e f or calling th e time-driven
program
(Time in ter ru pt OB 10 to OB 18 ) 100 ms 10, 20, 50, 100,
200, 500 ms,
1, 2, 5 sec
10, 20, 50, 100,
2 0 0 , 500 ms,
1, 2, 5 sec
R esolution times for clock-driv en time
interrupt (OB 9) – – every m inute,
every hour,
every da y,
every month,
every year,
once
R esolution time for delay interrupt (OB 6) ––1 ms
Cycle time monit or ing
default
selectabl e be tween
triggerable
150 ms
1 ... 4000 ms
yes
150 ms
1 ... 6000 ms
yes
150 ms
1 ... 13000 ms
yes
12
Appendix 1: Technical Data of the CPUs in the S5-135U
CPU 928B Programming G uide
C79000-A8576-C898-01 12 - 5
O peration / processing CPU 9 22 CPU 92 8 CPU 928B
S ize of the memo ry
S ize of the us er m emory
(in Kbytes) per s ub modu le 64 64 64
Size of the memory for dat a bl oc ks
(DB -R AM, in Kbytes) a ppro x. 22. 2 approx. 46.6 approx. 46.6
Tim ers and cou nte rs , fla gs
Number of timers an d counters 128 ea ch 256 each 256 each
Number of flags 2048 flags 2048 flags 2048 flags
+ 8192 S fla gs
Definition of terms
Basic t im e
Th e basic time is th e part of t h e c ycl ic system run t ime re qui red
wit hou t upda ti ng t h e proce ss ima g e, wit ho ut tran sfe rring IPC fla g s
a nd without interrupts or errors.
Respons e ti me
The response time is the time from activating the program processing
level PROCESS INTERRUPT for processing the first operation in
OB 2. I t is a prerequisite that OB 2 can be called immediately after
recognizing the process interrupt. The response time is extended if th e
program waits until the next ope ration or block boundary
Appendix 1: Technical Data of the CPUs in the S 5-135U
CPU 928B Programming Guide
12 - 6 C79000-A8576-C898-01
Ap pe ndix 2 : E rror Ide nt ifier s
Err or IDs in System
Data RS 3 and RS 4
RS 3 RS 4 Explanation
Structure of the block address lists
(Evalu atio n of DB 0)
8001H
8002H
8003H
8004H
8005H
yyyyH
yyyyH
yyyyH
yyyyH
yyyyH
Wrong block len gt h
yyyy = addressof the block with the wrong length
Calculated end addres s of the block in the memory is wrong
yyyy = block address
Illegal block ID
yyyy = addressof the block with wrong ID
Organizati on blo ck numb er to o high (permitted: OB 1 to OB 39)
yyyy = address of the block with wrong number
Data blo ck n um ber 0 (pe rmitted: D B 1 to DB 255)
yyyy = address of the block with the wrong number
Structure of th e address lists for updating the process image
(Evalu atio n of DB 1)
0410H
0411H
0412H
0413H
0414H
0415H
0419H
041AH
041BH
041CH
yyyyH
yyyyH
yyyyH
yyyyH
yyyyH
yyyyH
yyyyH
yyyyH
yyyyH
yyyyH
Illegal iD:
- header ID missing or incorrect (correct KS MASK01)
- ID illegal (permitted KH DE00, DA00, CE00, CA00, BB00 )
- end ID missing or incorrect (correct KH EEEE)
yyyy = illegal ID
"Digital iput s" , number of addresses illegal (per mitte d 0 ... 128)
yyyy = illegal number of addresses
"Di gi ta l ou t pu t s" , nu m be r o f add re sse s ill eg a l (permit te d 0 ... 128 )
yyyy = illegal number of addresses
"IP C input flags " , nu mber of addresses illegal (permitt ed 0 ... 256)
yyyy = illegal number of addr esses
"IPC o utput flag s", number of addresses illegal (permitte d 0 ... 256)
yyyy = illegal number of addresses
Ille gal number of ti mers (permitt ed: 256)
yyyy = illegal number of ti mers
Timeout in the digital inputs
yyyy = address of the non-acknowledged input byte
Time ou t in the digi tal ioutputs
yy yy = addre ss of t he non- a ck nowl edged out put byt e
Tim eout in IPC input f lags
yyyy = address of the non-acknowledged IPC f lag byte
Tim eout in IPC output f lags
yyyy = address of the non-acknowledged IPC f lag byte
12
Appendix 2: Error Identifiers
CPU 928B Programming G uide
C79000-A8576-C898-01 12 - 7
RS 3 RS 4 Explanation
Ev aluation of DB 2
0421H
0422H
0423H
0424H
0425H
0426H
DByyH
FByyH
FByyH
FByyH
DByyH
-
Data
yy = numb er of t he non- loa ded dat a b l ock
Function block not loaded
yy = number of the no n-lo aded function block
Function block not recognized
yy = num ber o f th e no n-recognized func ti on block
Function block loaded with wrong PG software
yy = num ber o f th e function blo ck
W rong clos ed loop controller data block length
yy = numb er of t he dat a b l ock
Th e re i s n ot e noug h space in t he DB R AM to shift th e cl os ed l oop
c ontro ller DB from the user EPROM to the DB RA M
Ev aluation of DX 0
0431H
0432H
0434H
0435H
yyyyH
yyyyH
yyyyH
yyyyH
Ille gal ID
-head er ID missing or inc orrect (correct KS MAS KX0)
-fiel d ID ille gal
-end ID missing or incorrect (correct KH EEEE)
yy yy = illega l ID
Ille gal parameter
yyyy = illegal parameter
Ille gal number of ti mers (permitt ed: 0...256)
yy yy = wr ong nu m b er of time r s
Illegal cycle monit oring time (permitt ed: 1ms to 13000ms)
yyyy = incorrect t ime
Ev aluation of DX 2
0451H
0452H
0453H
0454H
0455H
0456H
0457H
0458H
0459H
0045AH
-
yyyyH
yyyyH
xx00H
xxyyH
xxyyH
yyyyH
xx00H
xxyyH
xx00H
DX 2 length ( without block header)< 4 words is not permitte d
DX 2 lengt h (without block header) is too short for th e link type
yyyy = length of DX 2
Type of link illegal
yy y y = li nk typ e
Data iD for static parameter set illegal (not 44H, 58H)
xx = data ID
Bloc k for static parameter set illegal
xx = ID / yy = DB n um b er
Sta tic pa ramete r set doe s no t ex ist
xx = ID / yy = DB n um b er
Static parameter set too short
yyyy = number of th e non-existent DW
Data ID for dynamic parameter set illegal (not 44H, 58H, 00H)
xx = data ID
Block for dy namic param e ter set illegal
xx = ID / yy = DB n umber
Data ID for send mail box / job m ail box illegal (not 44H, 58H,00H)
xx = data ID
Appendix 2: Error Identifiers
CPU 928B Programming Guide
12 - 8 C79000-A8576-C898-01
RS 3 RS 4 Explanation
Evaluation of DX 2 (continued)
045BH
045CH
045DH
045EH
045FH
0460H
0461H
xxyyH
xx00H
xxyyH
xx00H
xxyyH
xxyyH
yyyyH
Block f or send m ail box 7 job m ail box illegal
xx = ID / yy = DB n um b er
Data ID for receive mail box illegal (no t 44H, 58H, 00H)
xx = data ID
Block for rece iv e mail b ox i ll ega l
xx = ID / yy = DB n um b er
Data ID for coordination byte illegal (not 44H, 58H, 4DH)
xx = ID
Block f or coordination by te illegal
xx = ID / yy = DB n um b er
Block f or coordination by te does not exist
xx = ID / yy = DB n um b er
Data word f or coordination byte does not exist
yyyy = number of non-ex istent DW
12
Appendix 2: Error Identifiers
CPU 928B Programming G uide
C79000-A8576-C898-01 12 - 9
Err or IDs in ACCU 1
and ACCU 2
ACCU-
1-L ACCU-
2-L Explanation OB
called
R EG- FE (closed loop controller error)
0801H
0802H
0803H
0804H
0805H
0806H
0880H
DByyH
DByyH
FByyH
FByyH
FByyH
DByyH
00yyH
Sampling time error
yy = number of the affected controller data block
Controller data block not loaded
yy = number of the data blo ck not loaded
Controller function blo ck not loaded
yy = nu mber of the funct ion blo ck not loa ded
Controller function block not regcognized
yy = number of the function block not recognized
Controller function blo ck loaded with wrong PG software
yy = fu nction bl ock num ber
Wrong controller d ata block length
yy = data block number
Timeout (QVZ) during co ntroller p rocessing
yy = number of the I/O byte that caused the QVZ
O B 34
WE CK-FE (collision of timed interrupts)
1001H 0016H
0014H
0012H
0010H
000EH
000CH
000AH
0008H
0006H
Collisio n of ti me d interrupts - OB 10 ( 10 ms)
Collisio n of ti me d interrupts - OB 11 ( 20 ms)
Collisio n of ti me d interrupts - OB 12 ( 50 ms)
Collision of ti med interrupts - OB 13 (100 ms)
Collision of ti med interrupts - OB 14 (200 ms)
Collision of ti med interrupts - OB 15 (500 ms)
Collision of ti med in terrupts - OB 16 ( 1 sec)
Collision of ti med in terrupts - OB 17 ( 2 sec)
Collision of ti med in terrupts - OB 18 ( 5 sec)
O B 33
BCF (opera tion cod e error)/substitution error
1801H
1802H
1803H
1804H
1805H
1806H
–
–
–
–
–
–
Substitution error with the DO RS operation
Substitution error with the DO DW, DO FW operations
Substitution error with the DO= , DI= operations
Substitution error with the L= , = T operations
Substitution error with the A=, AN=, O=, ON=,
S= und RB= ope rations
Substitution error with the RD=, LD=, FR=, SFD=,
SR=, SP=, SSU= and SEC= operations
O B 27
Appendix 2: Error Identifiers
CPU 928B Programming Guide
12 - 10 C79000-A8576-C898-01
ACCU-
1-L ACCU-
2-L Explanation OB
called
BCF (operation cod e error)
1811H
1812H
1813H
1814H
1815H
–
–
–
–
–
Operation with illegal opcode
Illegal opcode for an operation in which the hig h byte
of the first operation word contains the value 68H
Illegal opcode for an operation in which the hig h byte
of the first operation word contains the value 78H
Illegal opcode for an operation in which the hig h byte
of the first operation word contains the value 70H
Illegal opcode for an operation in which the hig h byte
of the first operation word contains the value 60H
O B 29
B C F (operation code error)/param e ter e rror
1821H
182BH
182CH
182DH
182EH
182FH
1830H
1831H
1832H
1833H
1834H
1835H
1836H
1837H
1838H
1839H
183AH
183BH
183CH
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Ill egal para me te r wit h th e follow ing:
C DB 0, 1, 2
JU(C) OB 0
JU(C ) OB >39: special funct ion does n ot e xist
CX DX 0, CX DX 1 a nd CX DX 2
L FW /T FW / L PW /T PW /L OW / T OW / L DD / T DD / DO FW : 255
L IW/T IW/L QW/T QW 127
L FD / T FD 253, 254, 255
L ID/T ID/L QD/T QD 125, 126, 127
RLD/RRD/SSD/SLD 33-255
SLW/ S RW/LIR/ TI R 1 6-25 5
SED/SEE 32-255
A=/AN=/O=/ON=/S=/RB=/==/RD=/FR=/SP=/SR=/
SEC =/SSU=/S FD=/L=/LD=/LW=/T= 0, 127-255
DO=/LDW= 0, 126- 255
A S/ O S/S S/= S/A N S/ON S/ R S byte n umber > 1023
A S/O S/S S/= S/AN S/ON S/R S bit number > 7
L SY/T SY parameter > 1023
L SW/T SW p ara meter > 102 2
L SD/T SD parameter >1020
G DB/GX DX Par ameter 0, 1 o r 2 (DB or DX 0, 1, 2 cannot
be gen erat ed )
O B 30
LZ F (runtime errors)/block not loaded
1A01H
1A02H
1A03H
1A04H
1A05H
1A06H
1A07H
–
–
–
–
–
–
–
Block no t lo ad ed f or C DB op era tio n
Block no t lo ad ed f or CX DX op era tio n
Block not loaded for JU(C ) FB, OB 1 to OB 39,
PB, SB opera tio n
Block no t lo ad ed f or D OU/DOC FX op er atio n
Block not loaded for OB 254 or 255 operation
Bloc k n ot loa ded for OB 182 operation
Block not loaded for OB 150/OB 151 opera tion
O B 19
12
Appendix 2: Error Identifiers
CPU 928B Programming G uide
C79000-A8576-C898-01 12 - 11
ACCU-
1-L ACCU-
2-L Explanation OB
called
L Z F (runtim e rror)/load or transfer error
1A11H
1A12H
1A13H
1A14H
1A15H
1A16H
1A17H
1A18H
1A19H
–
–
–
–
–
–
–
–
–
Access to a no n-defined data word w ith A/ AN D, O/ON D, S/R D,
= D
Transfer error with TDR to a non-de fine d data word
Transfer error with T DL to a non-defined data word
Trans error with TDW to a non-de fined data word
Transfer error with TDD to a no n-defined data word
Load error with LDR to a non-defined data word
Load error with LDL to a non-de fined data word
Load error with LDW to a non-de fined data word
Load error with LDD to a non-de fine d data word
O B 32
L ZF (run time error)/other ru ntim e errors
1A21H
1A22H
1A23H
1A25H
1A29H
1A2AH
1A2BH
1A2CH
1A31H
1A32H
1A33H
1A34H
1A34H
1A34H
1A34H
1A34H
1A34H
1A34H
1A34H
1A34H
1A34H
1A34H
1A34H
–
–
–
–
–
–
–
–
–
–
–
0001H
0100H
0101H
0102H
0200H
0201H
0202H
0203H
0210H
0211H
0212H
0213H
E rr o r in dicated for .../by ... :
G DB, GX DX: data bloc k already e xists
G DB, GX DX: illegal number of data words
(< 1 or > 4091)
G DB, GX DX: not enough space in the RAM
DI: illegal parameter in AC CU 1 (< 1 or > 125)
Bracket stack under of overflow a fter ’A(’, ’O(, ’)’
C DB, CX DX: block length in data block header too short
(length <5 words)
Function block loaded with wrong PG software
ACR: i llegal pag e n umber in ACC U-1-L (> 255)
OB 254 or OB 255 (shift) or OB 250:
destination data block already exists in DB RAM
O B 254 or OB 255 (duplicate):
destination data block already exists in DB RAM
OB 254 or OB 255 or OB250:
not eno ugh space in the DB RAM
OB 182: data field written to illegally
OB 182: ad dress area type illegal
OB 182: dat a block n umber illegal
OB 182: "number of the first parameter word" illegal
OB 182: "source data block type " illegal
OB 182: "source data block number" illegal
OB 182: "nu mber of the first data word in the source
to be transferred" illegal
OB 182: a value < 5 words is entered i n t he block header
as the length of the source data block
OB 182: "destination data block type" illegal
OB 182: "destination data block number" illegal
OB 182: "nu mber of the first destination data word
to be transferred" illegal
OB 182: a value < 5 words is entered in the block header
as the length of the destination data block
O B 31
Appendix 2: Error Identifiers
CPU 928B Programming Guide
12 - 12 C79000-A8576-C898-01
ACCU-
1-L ACCU-
2-L Explanation OB
called
L Z F (runtim e error)/other runtim e errors (continued)
1A34H
1A34H
1A34H
1A34H
1A35H
1A36H
1A3AH
1A3BH
1A41H
1A42H
1A43H
1A44H
1A45H
1A46H
1A47H
1A48H
1A49H
1A4AH
1A4BH
1A4CH
1A4CH
1A4CH
1A4CH
1A4CH
1A4CH
1A4CH
1A4CH
1A4CH
1A4CH
1A4CH
1A4CH
1A4CH
1A4CH
1A4CH
1A4DH
1A4DH
1A4DH
0220H
0221H
0222H
0223H
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0001H
0100H
0101H
0102H
0103H
0201H
0202H
0203H
0204H
0205H
0206H
0207H
0208H
0209H
020AH
0001H
0100H
0101H
E rr o r in dicated for .../by ... :
OB 182: "number of data words to be transferred" illegal
(=0 or > 4091)
OB 182: source data block too short
OB 182: destination data block too short
OB 182: destination data block in EPROM
OB 250: nu mber of the transfer block illegal
OB 250: di fferent length in DB x and DB x+1 or DX x
and D X x+ 1
OB 221: illegal value for the new c ycle time (c ycle time
<1 ms or > 1 3 0 00 ms )
OB 223: different start-up types for the CPUs in volved i n
mu ltiprocesso r operation
OB 240, OB 241 or OB 242:
illegal shift regis ter or data block numb er
(no. < 192 or > 255 )
OB 241: shift register not initialized
OB 240: not enough space in the DB RAM
OB 240: Data word DW 0 dof the data block does not
contain the value ’0’
OB 240: illegal shift register length in DW 1
(not betwee n 2 an d 256)
OB 240: illegal pointer position or number o f pointers > 5
OB 120: illegal value in ACCU 1 or ACCU-2-L
OB 122: illegal value in ACCU 1
OB 110: illegal value in ACCU 1 or ACCU-2-L
OB 121: illegal value in ACCU 1 or ACCU-2-L
OB 123: illegal value in ACCU 1
OB 150: function number illegal (= 0 or > 2)
O B 150 : add ress area type il legal
OB 150: data block numb er ill egal
OB 150: "number of the first data field word" illegal
OB 150: a value < 5 words is entered i n t he block header
as the lengt h o f the data block
OB 150: year specified in dat a field illegal
OB 150: month specified in data field illegal
OB 150: day of mo nth specified in data field illegal
OB 150: weekday specifi ed in data field illegal
OB 150: hour specifi ed in data field illegal
OB 150: minute specified in data field illegal
OB 150: second specified in data field illegal
OB 150: "1/100 second" specified in data field not
equal to 0
OB 150: dat a field word 3 /bits 0 to 3 not equal to 0
OB 150: hour format does not match setting in OB 151
OB 151: function number illegal (= 0 or > 2)
OB 151: address area type illegal
OB 151: data block number illegal
O B 31
12
Appendix 2: Error Identifiers
CPU 928B Programming G uide
C79000-A8576-C898-01 12 - 13
ACCU-
1-L ACCU-
2-L Explanation OB
called
L ZF (runtime error)/oth er runtime errors (continued )
1A4DH
1A4DH
1A4DH
1A4DH
1A4DH
1A4DH
1A4DH
1A4DH
1A4DH
1A4DH
1A4DH
1A4DH
1A4EH
1A4FH
1A4FH
1A50H
1A51H
1A52H
1A53H
1A54H
1A55H
1A56H
1A57H
0102H
0103H
0201H
0202H
0203H
0204H
0205H
0206H
0207H
0208H
0209H
020AH
0001H
0001H
0002H
–
–
–
–
–
–
–
–
E rr o r in dicated for .../by ... :
OB 151: "number of the first data field word" illegal
OB 151: a value < 5 words is entered i n t he block header
as the lengt h o f the data block
OB 151: year specified in the dat a field illegal
OB 151: month specified in the data field illegal
OB 151: day of mo nth specified in the data field illegal
OB 151: weekday specifi ed in the data field illegal
OB 151: hour specifi ed in the d ata field illegal
OB 151: minute specified in the data field illegal
OB 151: secondspecified in the data field illegal
OB 151: "1/100 second " specified in data field is not equal to 0
OB 151: job type in data field illegal (> 7)
OB 151: hour format does not match setting in OB 150
OB 152: function number illegal (not 0 to 3 or
8 to 15)
OB 153: function number illegal (=0 or <0)
OB 153: delay time illegal
LRW, TRW: the calculated memory address < BR + constant>
is not in the range "0 .. EDFF H" (see Chap 9)
LRD, TRD: the calculated memory address < BR + constant>
is not in the range "0 .. EDFEH" (see Chap. 9)
TSG, LY GB, LW GW, TY GB, TW GW:
the calculated linear address < BR + constant>
is not in the range "0 .. EFFFH"
LY GW, LW GD, TY G W, TW GD:
the calculated linear address < BR + constant>
is not in the range "0 .. EFFEH"
LY GD, TY GD:
the calculated linear address < BR + constant>
is not in the range "0 .. EFFCH"
TSC, LY CB, LW CD, TY CW, T W CD:
the calculated page addre ss < BR + constant>
is not in the range "F400H .. EBFFH"
LY CW, LW CD, TY CW, TW CD:
the calculated page addre ss < BR + constant>
is not in the range "F400H .. F FFEH"
LY CD, TY CD:
the calculated page addre ss < BR + constant>
is not in the range "F400H .. FBFCH"
O B 31
Appendix 2: Error Identifiers
CPU 928B Programming Guide
12 - 14 C79000-A8576-C898-01
ACCU-
1-L ACCU-
2-L Explanation OB
called
L Z F (runtim e error)/other runtim e errors (continued)
1A58H
1A59H
–
–
E r ror in d i cat ed fo r .../by ... :
TNW/TNB: the source block is not completely in one of
the following areas:
0000 .. 7FF F user me mory (see Chapter 9)
8000 .. DD7F da ta blo c kR AM
DD80.. E3FF DB 0
E400 .. E7FF S flags
E800 .. EDF F system data (RI, RJ, RS, RT, C, T)
EE00 .. EFFF flags, process ima ge
F000 .. FFFF peripherals
TNW/TNB: the destination block is not completely in one o f
the following areas:
0000 .. 7FF F user memory (see Chapter 9)
8000 .. DD7F data block RAM
DD80.. E3F F DB 0
E400 .. E7F F S flags
E800 .. EDFF sy st em d at a (R I, RJ, R S, RT , C , T)
EE00 .. EFFF flags, process image
F000 .. FFFF peripherals
O B 31
QVZ (timeout)
1E23H yyyyH T imeout (QVZ) in t he user program when accessing the
peripherals
yyyy = QVZ address
O B 23
1E25H
1E26H
1E27H
1E28H
yyyyH
yyyyH
yyyyH
yyyyH
Timeout outputting the process im age of the digital
outputs
yy yy = addre ss of t he non- a ck nowl edged out put byt e
Timeout updating the process im age of the digital
inputs
yyyy = address of the non-acknowledged input byte
Timeout updating the IPC input f lags
yyyy = address of the non-acknowledged IPC f lag byte
Timeout updating the IPC output flags
yyyy = address of the non-acknowledged IPC f lag byte
O B 24
A D F (adressin g error )
1E40H yyyyH Adressing error (A DF ) i n th e us er program
yy yy = ADF addr es s O B 25
12
Appendix 2: Error Identifiers
CPU 928B Programming G uide
C79000-A8576-C898-01 12 - 15
A pp e nd i x 3 : S TE P 5 Operations not Contained in the CPU 928B
Pleas e n ote t hat th e fol lowing ST EP 5 o perations belon gin g to th e
CPU 946/947 and CPU 948 cannot be proc essed in the CPU 928B.
Operation Function
BAS
BAF
TB I, Q, F, C, T, D, RI, RJ,
RS, RT
TBN I, Q, F, C, T, D, RI, RJ,
RS, RT
SU I, Q, F, C, T, D, RI, RJ,
RS, RT
RU I, Q, F, C, T, D, RI, RJ,
RS, RT
LIM
SIM
UBE
STW
IAE
RAE
RAI
IAI
Blo ck command output
Release command output
Test bit for signal status ’ 1’
Test bit for signal stauts ’ 0’
Set bit un cond it ionally
Reset bit un conditio nal ly
Load interrupt mask
Set in ter r u p t m ask
Interrupt block end
Stop operation in t im e-d riven
int errupt processing
Disable ad dressing errpr
interrupt
Enable addressing error
interrupt
enable requested interrupt
processing
Di sa ble reque st ed i nt erru pt
processing
Appendix 3: STEP 5 Operations not Co ntained in the CP U 928B
CPU 928B Programming Guide
12 - 16 C79000-A8576-C898-01
Appendix 4: Identifiers fo r the P rogram Processing Levels
Th e ide ntfie rs co rrespon d to t he i den tifi ers en te red in the IST ACK
under LEVEL (hexadeci mal).
Identifier Level
0002H
0004H
0006H
0008H
000AH
000CH
000EH
0010H
0012H
0014H
0016H
0018H
001AH
001CH
001EH
0020H
0022H
0024H
0026H
0028H
002AH
002CH
002EH
0030H
0032H
0034H
0036H
0038H
003AH
003CH
003EH
0040H
0042H
0044H
0046H
Co l d restart
Cycle
Tim e- d r iven inter ru p t 5 se c
Tim e- d r iven inter ru p t 2 se c
Tim e- d r iven inter ru p t 1 se c
Time-driven interrupt 500 ms
Time-driven interrupt 200 ms
Time-driven interrupt 100 ms
Tim e- d r iven inter ru p t 50 ms
Tim e- d r iven inter ru p t 20 ms
Tim e- d r iven inter ru p t 10 ms
Timed job
N o t used
Close d lo op co ntrol
N o t used
Dela y interrupt
N o t used
Process interrupt
N o t used
Retentive m anual cold restart
Reten tive automatic cold r estart
Abort
Interface error
C ollision of timed interrupts
C losed loop controller error
Cycle error
N o t used
Operation code error
Runtime err or
Ad dressi ng error
Timeout
N o t used
N o t used
Ma nual war m restart
A utomatic wa rm rest art
12
Appendix 4: Identifiers for the Program Processing Levels
CPU 928B Programming G uide
C79000-A8576-C898-01 12 - 17
Appendix 5: Exam ple "ISTACK Evaluation"
Thi s (simplifie d) e x ample illu st ra tes h o w t o ev al u at e the I ST ACK.
For more detailed inf ormation, you should also refer to Section 5.3
"Control Bits and the Interrupt Stack".
Ready to start?
The C PU h as in te r rupted cyc li c program pro ce ssing a n d ha s c h an g ed
to the stop mod e.
Error analysis
To find the cause o f the interruption, select the programmer online
function "output ISTACK".
T he control bits then appear on the PG screen as shown belo w:
Th e "X "s i n t h e c o ntro l b i ts i n dic ate t h e c ur ren t o pe rat in g stat us o f t h e C PU
( >> ST P < < ) , and certai n characteristics of the CPU are marked (OB 1
loaded, single processor m ode, 16 K W user memory etc.). In the top
line the cause of the stoppage is indicated as STP-BEF. It is assumed
that you have not progra mmed an STP operation in your STEP 5 user
program. This means that the stoppage was caused by a stop operation
fro m the system program because an error OB was not loaded. The
identifier LZF is marked in the bottom line.
CONTROL BITS
>>STP<< STP-6
ANL-6
RUN-6 EINPROZ BARB OB1GEL FB0GEL OBPROZA OBWECKA
ANL-2 NEUZU MWA-ZULNEUSTA
X
X
X
X
XX
X
X
X
X
X
MWA AWA
FE-STP BARBEND PG-STP STP-SCH STP-BEF MP-STP
>>ANL<<
>>RUN<<
32KWRAM 16KWRAM
URL-IA
FE-22
FE-6 FE-5 FE-4 FE-3 L Z F REG-FE DOPP-FE
PEU BAU ZYK QVZ ADF WECK-FESTUE-FE
MOF-FE RAM-FE DB0-FE DB1-FE DB2-FE KOR-FE
STP-VER ANL-ABB UA-PG UA-SYS UA-PRFE UA-SCH
8KWRAM KM-AUS KM-EIN DIG-EIN DIG-AUSEPROM
URGELOE
DX0-FE
NAU
BCF
Appendix 5: Exam ple "ISTA C K Evaluatio n"
CPU 928B Programming Guide
12 - 18 C79000-A8576-C898-01
It is possible that the syste m progra m has detected a runtime error and
that the corresponding error organization block is not progra mmed. Since
there are various runtime errors, and you cannot possibly know which o f
them has occurred, the information shown in the control bits is not yet
su fficient for reliable diagnosis.
You ca n no w di splay th e actual ISTAC K:
The ISTACK at de pth 01 represents the program processing level that
was last active before the transition to the stop mode. From the identifier
003A ( after LE VEL ) yo u can see that thi s is the ISTACK of the
program proce ssing leve l RUNTI ME ERROR. The error i denti fier
00001A01 is en ter e d i n ACCU 1. This tells you that the runtime error
was caused by calling a data block that was not loaded using the
ope rat io n "C DB " . Si nc e th e cor respond i ng e r ror, OB 19, do es n ot
e xist in our user program, the system program aborte d progra m
ex e cu tio n (ST P). T he i nterrupt dis pl ay mas k word ICMK al so
co n ta ins the ca use o f i nt erru pt . T he i den ti fie r 0120 corresponds to the
bit pattern "0000 0001 0010 0000 ". Bit 25 (LZ F ) an d Bi t 2 8 (STP) are
set.
You must now fin d out w hic h block a nd w hi ch operatio n c ause d th e
runtime error.
INTERRUPT STACK
DEPTH: 01
OP REG: SAC: 0000 DB-ADD:
DB-NO.:
DBL-REG.: -NO.:
BA-ADD:0000
0000
0000
0000
0000
0001 SAC-NO.:
REL-SAC:
UAMK: ICRW:
0006
0120
226
003A
BST-STP:
LEVEL:
ACCU1: ACCU2: ACCU3: ACCU4:0000 0A01 0000 0000 0000 0000 0000 0000
CONDITION CODE: CC1 CC0 OVFL OVFLS OR
STATUS
NAU PEU
STP BCF S-6 LZF REG-FE
BAU MPSTP ZYK QVZ
RLO
CAUSE OF INTERR.:
ADF X
STUEB STUEU WECK DOPP
ERAB
12
Appendix 5: Exa mple "IST A C K E valuation"
CPU 928B Programming G uide
C79000-A8576-C898-01 12 - 19
You can now m ove on in the ISTACK to depth 02:
The identifier 0004 (a fter LEVEL) tells you that this is the ISTAC K of
the interrupted progra m processing level CYCLE. The STEP address
counter (SAC) indic ates th e addr ess 0037H. The operatio n that
caused the error is stored at this absolute address in the user m em ory.
Its code is specified as 2006 (OP-REG). From the listing of the
machine codes in the operations list, you can see that this is the STEP 5
operation
’ADB 6’.
T he interrupt occurred in organization block OB 1. Within OB 1, the
operation that caused the error is at the relati ve address 0004
(REL-SAC). A s you have al ready e stablished , this o pe rat io n le d to a
runtime error (see ICMK, bit 25, and CAUSE OF INTERR.).
You ca n no w di splay th e in correct o perati on o n t he screen usin g the
SE ARCH onlin e function. Enter th e appropriate block (OB 1) and t he
rel ativ e ad dre ss of t h e operation.
INTERRUPT STACK
DEPTH 02
OP REG: SAC: 0037 DB-ADD:
DB-NO.:
DBL-REG.: -NO.:
BA-ADD:0000
0000
0000
0000
2006
0001 OB-NO.:
REL-SAC:
ICMK: ICRW:
0004
0020
1
0004
BST-STP:
LEVEL:
CONDITION CODE: CC1 CC0 OVFL OVFLS OR
STATUS
NAU PEU
STP BCF S-6 LZF REG-FE
BAU MPSTP ZYK QVZ
VKE
CAUSE OF INTERR.:
ADF X
STUEB STUEU WECK DOPP
ERAB
ACCU1: ACCU2: ACCU3: ACCU4:0001 1001 0000 0101 0000 0000 0000 0000
Appendix 5: Exam ple "ISTA C K Evaluatio n"
CPU 928B Programming Guide
12 - 20 C79000-A8576-C898-01
Follow i ng th e sea rch , you ca n se e th e o perati on "C DB 6", t hat
cause d the interruptio n; there is no data block with the nu mber 6 in
the user me mory.
! F1!F2!F3!F4!F5!F6!F7!F8!
! DISP SYMB!!!! !LIB.NO.!!!
OUTPU T DEVICE: PC BLOCK: OB1 SEARCH: 4H
REL-SA C
OB 1
SEGMENT 1 0000
0004 : C DB 6 opera tion t hat caus ed the err or
0005 :
0006 :
0007 :
0008 :BE
12
Appendix 5: Exa mple "IST A C K E valuation"
CPU 928B Programming G uide
C79000-A8576-C898-01 12 - 21
13
Further Reading
13
CPU 928B Programm ing Guide
C79000-A8576-C898-01 13 - 1
Further Reading
/1/ S5-135U/155U
CPU 922/CPU 928/CPU 928B/CPU 948
Pocket Guide
Or der no. 6ES5 997-3UA22
/2/ S5-135U/155U System Manual
Or der no. 6ES5 998-0SH21
/3/ STE P 5 Man u al
Or der no. C79000-G8 576- C140
/4/ GR APH 5: Graphi c pro gramming of
sequential controls under th e
S5-DOS SIMATI C S5 operatin g system
Order no. 6ES5 998-1SA01
/ 5 / S ta nd a r d Fun c ti on Bl ocks
Da ta Ha ndl ing Blo cks CPU 922, C PU 928, CP U 928B
S5-135U, S5-155U Program mable Co ntroll ers
/6/ SINEC
Manual
CP 143 with COM 143
Order no. 6GK1970-1AB43-0AB0
/7/ Hans Berger:
Auto mating wit h the SIMATIC S5-135U
SIEMENS AG
Or der no. A19100- L531- F505- X-7600
13
Further Reading
CPU 928B Programming G uide
C79000-A8576-C898-01 13 - 3
/8/ Programmable Controllers
Basic Concepts
SIEMENS AG
Or der no. E80850- C293-X-A2
/9/ Catalog ST 59: Programmers
SIMAT IC S5
/10/ Ca talo g ST 54.1: Program ma ble Con troll ers
S5-135U, S5-155U and S5-15 5H
/11/ Catal og ST 57: Stan dard Functi on Bl ocks
a nd Driver Programs for
Programma bl e Co n tro llers of t he U Series
SIMAT IC S5
/12/ SCL Manua l
Or der no. C79000-G8 576- C162
/13/ R64 Controller Structure
/14/ S5-135U
Co mm uni ca ti on CPU 928B
Order No.: 6ES5 998-0CN21
Further Readi n g
CPU 928B Programming Guide
13 - 4 C79000-A8576-C898-01
Contents of Chapter 14
List of Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 3
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 - 5
List of Tables an d Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 1 1
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 1 1
L i st of F igure s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 17
14
Index and Lists
14
CPU 928B Programm ing Guide
C79000-T8576-C898-01 14 - 1
Abbreviations
(An explanation of the IST ACK abbreviati ons can be found in Section 5.4)
ACCU-1 (2, 3, 4)-L low word i n ac cumul ator 1 (2, 3, 4), 16 bi t
ACCU-1 (2, 3, 4)-H high word in accumul at or 1 (2, 3, 4), 16 bit
ACCU-1 (2 , 3, 4)-LL l ow byte o f low word in accumul at or 1 (2, 3, 4), 8 bi t
ACCU-1 (2, 3, 4)-LH high byte of low word i n ac cumulator 1 (2, 3, 4), 8 bit
AD F ad dressing error
A N ZW condi tion co de wor d
BASP disable command o utput (signal on S5 bus)
BCD b inary coded deci ma l
BR base address reg ister
BSTACK blo c k stack
CC 1, CC 0 condition code bits for dig ita l oper ation s
COR coordinat or module
CP commun ication s proc ess or
CPU central processing unit
CS F co ntr ol s yste m fl owc hart
DB data block
DBA data bloc k start address (in register 6)
DBL data block length (in register 8)
D X extend ed da ta b lock
E PR OM erasabl e prog ra mma ble read o n ly memory
ERAB first sca n (bit code)
EU ex p ansion unit
FB functi on block
F X exte nded function bloc k
I M i nterface mod ule
INT (system)interrupt
IP i nt el li gen t peripheral mod ule
ISTACK interrupt stack
List of A bbreviations
14
List of Abbreviati ons
CPU 928B Programming G uide
C79000-T8576-C898-01 14 - 3
KB c al l for a non- ex i s te nt l ogi c bl ock
KDB o pen in g a non -existe nt DB /DX da ta blo c k
LAD lad der diagram
LED l ig h t-e mi tting diode
NAU p ower fa ilure
OB organizati on block
OR or (bit code)
O S overflow l atching (wo rd code)
O V overflow (wor d code)
P AFE parameter assignment error byte
P ARE parity error
P B program bloc k
PEU power failure on expansion unit
P G progr a mmer
P I proce ss ima ge
PII process image of the inputs
P IQ pr o ces s i ma ge of t he o utp uts
PLC program mable co ntroller
QVZ timeout
RAM random-a c ce ss memo ry
RLO result of lo gic operatio n
SAC s tep addr ess coun ter
SB se qu ence blo ck
SPU operating system proce ssor
STA status (bit code)
STL statem ent list
STS sto p st ateme nt
SUF substitution error
STUEB BSTACK overflow
STUE U IST ACK ove rfl ow
TR AF transf e r or load er ror
ZY K cycle error
List of Abbreviations
CPU 928B Programming Guide
14 - 4 C79000-T8576-C898-01
Index
A
Ac cumulat ors (ACCUs) 3-15, 6-15
A c tu a l oper ands
o f function bloc ks 2-31
Addressing 1-16
AD F (addressi ng error) 5-29, 5-53
Arith metic operations 3-56
Ass ign me nt list 2-7, 2-26
AUTOMAT I C COLD R ESTAR T
S e e COLD RES TART
AUTOMAT I C WAR M REST A RT
See WARM RESTART
B
Basi c levels 4-8, 4-10
Basi c operati ons 2-4, 3-19
BAS P LED 4-6
BASP s ignal 4-27
BC F (operatio n code error)
ope rati on co de e rror 5-29, 5-39, 5-41
par ameter err or 5-29, 5-39, 5-42
s ubstit ution error 5-29, 5-3 9 - 5-40
Bina r y numbers 2-8
Blockad dress li st 3-8, 8-12
bloc k ID 2-38
body 2-14, 2-26, 2-38
ca lls 2-17, 3-8, 3-32
form a l operan ds (block parame ters ) 2-29
header 2-14, 2-38
number 2-13, 2-38, 3-33
preheader 2-15, 2-37
Bl oc k operatio ns 3-32
Blocks
n esti ng bl oc ks 3-8
BR register 9-26
BSTACK (block stack)
evaluate 5-9
output 5-8
read 6-53
C
CC 1 and C C 0
See results codes
Cloc k-dr i v en time in ter rupt s
interruptions 4-34
special features 4-34
Closed lo op co ntroll er st ruc tu re R64 4-38
Closed-loop control 6-110 - 6-124
Communicati on OBs 10-20
conditi on co de byte 10-23
parameters 10-21
runtimes 10-29
Communicati on processors (CPs) 10-7
Co mpariso n operations 3-32
CO MPR ESS MEMOR Y 2-16
Control bits 5-5, 5-10 - 5-28
Controller
processing closed loop
c ontroller interrupts 4-38
CONTROLLER
INTERRUPT 4 -8, 4-10, 4-28, 4-38
interrupt points 4-39
Conv ersi o n ope ra tio ns 3-62
Correcting block s 2-16
Counter valu e 3-28
Counters C 1-15
CSF (control system flowchart) 2-4
Current data block 1-16
CYCLE 3-11, 4-28
cyclic processi ng 3 -4, 3-11
interrupt points 4-30
us er i nt erface OB 1 4-29
Cycle bou nda ry 6-40
Cycle statistics 6-42
Cycl e time 6-40
Cycle statistics 6-40
Cyclic processing 1-6, 1-18, 4-28
D
Dat a area 6-68
Dat a block DB 0 2-43, 3-8
Data block DB 1 2-43
Data block DB 2 2-43
Dat a bl o ck DB1
create 10-9
Data b lock DX 0 2-43
Data b lock DX 1 2-43
Da ta bloc k RAM (DB RAM) 1-12, 3-10, 6-101
Dat a bl o cks
general 1-15
Data blo ck s (DB/DX)
acc ess ing data blocks 6-58 - 6-61
general 2-14, 2-37
generating 3-33
programming 2-39
14
Index
CPU 928B Programming G uide
C79000-T8576-C898-01 14 - 5
structure 2-37
validity 2-40
Dat a word 1-15, 2-37, 2-41
D BA (d at a block start addr ess) 9-11
D BL (da ta b lock le ngt h) 9-14
Deci mal numbers 2-8
Decrementing 3-65
Default
syste m reaction 1-9
De fault s, modifying 1-9
Defi niti o n of t h e "9th track " 4-22
DE LAY INTERRUPT
interruptions 4-32
special features 4-32
De lay time 4-28
Delaye d interrupt 6-48
Di sp lay gen era ti on opera tion 3-33
E
EPRO M submo dul e 3-10
ERAB
See results codes
Error handl in g
using organization blocks 5-29 - 5-31
Error IDs 5- 7
Error information 5-5 - 5-9
Erro r levels 4-8, 4-10
Error OBs 2-21
Executive operat ions 3-58 - 3-70
F
F flags 1-14, 10-21
Fix e d point n umbers 2-9
Fl oatin g point numbers 2-8
Formal operands 2-27, 3-51
Function block F B 0 2-36
Function blocks (FB/FX)
general 2-14, 2-25
programming 2-27
sta nda rd function blocks 2-25, 2-35
structure 2-26
G
Global me mor y
access 9-29
general 9-4
GRAPH 5 2-5
H
Handling blocks 6-100
I
I/Os address distribution 8-7
modules 1-13
O area 1 - 13
P area 1 -13
ICMK 8-21
ICRW 8-19
Incrementing 3-65
Interface
second serial in ter f a ce 5-36
to s yste m progr am 1-9, 1-12, 2-19
Interproces sor commu nicatio n flags
da ta e xc hange vi a IPCs 10 -5
gen era l 3-13, 10-5
jumper settin gs 10-5
I nterrupt condi ti on codeword 8-18
I nterrupt events 3-14
In t errupt-driv e n pro ce ssin g 1-7
IPC flags
trans ferring blocks of IPC flags 6-94
IS TACK (interrupt stack)
code bits 5-19
contents 5-18
error information 5-5 - 5-9
inform a ti on in I STA CK 5-19
output 5-6, 5-10
J
Jump operations 3-58
L
LAD (ladder diagram) 2-4
LED RUN 4-5
LED STOP 4-5
L ibr ar y num ber 2- 3 8
Loa d operations 3 -21, 3-54
Loca l me mory
access 9-28
general 9-4
Logi c oper ations 3-50
binary 3-19
Index
CPU 928B Programming Guide
14 - 6 C79000-T8576-C898-01
digital 3-50
LZF (runtime errors) 5-43, 5-45
M
Mantissa
See f loating point number
MANU AL WARM RESTART
See WARM RESTART
M emory acce ss
general 9-4
via the BR register 9-26
M emor y or gani zation 9- 4
Mod e of op erati on of a CPU 1-6 - 1 -7-6
Multiprocessor communi cation
applicatio n exa mples 10-51
as signmen t lis t 10-35
buffering data 10-15
d ata amount 10-13
initializing 10-31
modes 10-33
rec ei ve da ta 1 0-45
se nd da ta 10-38
sequence 10-13
Multiprocesso r mode
d ata ex change bet ween CPUs
a nd CPs 10-7
Multiprocesso r ope rati o n
c ommun ic ations mec hanis ms 10-4
I /O assignment 10-9
rest art types 6-93
N
Nesting
program processing levels 4-9
Nestin g depth 3-9
N o opera ti on 3-33
Normalize d fixed point numbers 6-120, 6-124
O
O area
See I/Os
Operand areas 1-13
Operand substitu ti on 3-67
Operati ng mo des 4-4, 11-6
Operati on code 2-6
OR See results codes
Organization block (OB)
general 2-17
Organization bloc ks (OB)
as us er i nterfac es 2-19
Organization bloc ks (OBs)
c ontrol of th e start-up procedure 2-21
error OBs 2-21
general 2-13
special functions OBs 2-23
OS (overflow latchi ng)
See results codes
OV (overflow)
See results codes
P
P areaSee I/Os
Page ar ea/page me mor y 9-9, 9-33
busy loc atio n 9-34
Pagesaccessing pages 9-33
Parallel operation of serial
PG int erfac es 11-20 - 11-28
cyclic functions 11-25
long-running functions 11-22, 11-25
sh ort -running funct ions 11-22, 11-24
Parameter 2-6
Parameters for DX 0 1-9, 7-4, 7-8 - 7-12
P G fun ctions 11-4
P G in ter fa ce modu le 1 1-20
PG screen form
for ge nerat ing DB 1 10-10
P ID c ontrol ler 6 -110
Priority 1-7, 4-10
Process image
outputs ( P IQ) 1-6, 1-13
inputs (PII) 1-6, 1-13
general 1-13, 3-13
updating 4-27
Process interrupt 4-8, 4-10, 4-28
Process interrupt signals
level-triggered 4-40
Process interrupts
disabling 3-71, 4-42
edge-triggered 4-41
enabling 3- 71, 4-42
interrupts 4-40
multiple interr upts 4-40
processing 4-39
Processing operations 3-65
Program
progr am organization 3-5 - 3-9
14
Index
CPU 928B Programming G uide
C79000-T8576-C898-01 14 - 7
system program 1-8, 6-95 - 6-97
user program 1-10
Program blocks (PB) 2-13, 2-17
Program processing le vels
general 6-16, 6-22
le ve l nu mber 6-98
Programming
general 1-17
progr a mming la ngua ge
GRA PH 5 1-20
SCL 1-20
STEP 5 1-20
Prog rammi n g la ngu ag e SCL 1-20
Prog rammi n g too ls 1-20
Q
QVZ (timeout error) 5-29, 5-53
R
RAM s ub modu le 3-10
REG -FE (co nt roller error) 5-30, 5-58
Response ti me 4-44
RESTART
errors during res tart 5-32
errors in restart 5-38 - 5-62
rest art types 6-93
Results co des
ERAB 3-16, 3-20
CC 1 and CC 0 3- 18, 3-60
OR 3-17
OS 3-17
OV 3-17
RLO 2-7, 3-17, 3-20
S TA 3-17, 3-20
RLO See results codes
RS/R T area 8-15
RUNerrors in RUN 5-38 - 5-62
general 4-4, 4-27 - 4-44
S
S flags 1-14
Scra tc hpa d fl ags 10-51
Semaphores 3-71 - 3-78
Sequence blocks 2-17 - 2-24
Sequence blocks (SB) 2-13
Serial link PG - PLC 11-19
Se t/reset operations 3-20, 3-51
Sh ift operatio ns 3-60
Shift reg ister 6-101
Sp ec ia l fun ct ion s
errors during special function
processing 6-9
general 6-6
interfaces 6-8
S pecia l functions O Bs 6-6
ST A (status)
See re sults co des
St andard functi on bl oc ks
See also function blocks
START-UP 3-11
general 3-11
STEP 5 opera ti ons 3-15
STEP 5 programmin g la ngua ge 2-4 - 2-16
S TL (statement list) 2-4
STOP 4-4
Stop opera ti ons 3-33
Struct ure o f the memory area 8-4, 8-6
Stru ct ured pro g ra mm in g 2 -5
Suitability of the C PU 928B 1-4
Supplementary operatio ns 2-4
Syst em check poi nt 1 1 -5
Syst em da t a 8- 1 5
Syst em da t a wo r d s
bit assignme nt 8-1 8
Sys te m d a ta w ords RS 3 and RS 4 5-6, 5-33
System operat io ns 2-4, 3-58
System program 1-8
System program defau lts 1-9
Syst em RA M 8-6
Syst em time 6- 28
T
TI ME INTER RUPT 4-8, 4-10, 4-28
Time interrupts
at fixed intervals 4-28
clock-controlled 4-27
interrupt points 4-36
interruptions 4-36
Time-con trolled processing 1-7
Time-driven program execution
clo ck-controlle d (time in terrupt) 4-27
clo ck-d riven tim e interrupt 4-31
delay in terrupt 4-31
in f ixed tim e bases (time
interrupts) 4-28, 4-35
tim e in terrupts 4-31
Timed job, generate 6-33
Ti mer and counter ope rati ons 3-26, 3-52
Index
CPU 928B Programming Guide
14 - 8 C79000-T8576-C898-01
T imer valu e 3-27
T imers T 1-15
Tr ansfer opera tions 3- 21, 3-54
Transferring fields of memory 9-18 - 9-25
U
Use r checkpoints 11-5
User interface
for cl ock-drive n ti me interr upt 4-34
for closed l oop controller interrupt 4-38
for cyclic p r ogram e xecut ion 4-29
for de lay interr upt 4-31
for process interrupt 4-39
for r e st art 4-22
for time int errupts 4-35
Use r memory 1-12
organization 8-9 - 8-14
User program 1-8, 1-10
processing 3 -4, 3-11
See program
storing 1-12
tasks 1-10
W
WECK-FE (collision of
t ime interrupts) 4-34, 4-36, 5- 29, 5-57
Z
ZYK-FE ( c ycle t ime e xce ed ed) 5-56
14
Index
CPU 928B Programming G uide
C79000-T8576-C898-01 14 - 9
List of Tables
Table 2 -1 O ver view of the organizat ion b locks fo r progra m execut ion . . . . . . . . . . . . . . . . . . . . . 2 - 2 0
Table 2 -2 O ver view of the organizat ion b locks for star t-up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 2 1
Table 2-3 Overview of the organizatio n blocks for error han dling . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 21
Table 2-4 Overview of organizatio n blocks for special functions . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 23
Table 2-5 Permitted formal operands for function blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 29
Table 2-6 Permitted actual operands for function blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 31
Table 2-7 Data formats permitted in a d ata block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 39
Table 3 -1 Res ul t condition codes of STE P 5 oper a tions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 18
Table 3-2 Bina ry logic operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 19
Table 3-3 Set/reset operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 20
Table 3-4 Load and transfer operati ons/part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 21
Table 3-5 Load and transfer operati ons/part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 22
Table 3-6 Timer and counter operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 26
Table 3-7 Arith metic operati ons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 31
Table 3-8 Co mpariso n operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 32
Table 3-9 Block operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 32
Table 3-10 NOP/display/stop operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 33
Table 3-11 Bi na ry logic operations with formal operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 50
Table 3-12 Digital logic operat ions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 50
List of Tables and Figures
14
List of Tables and Fi gures
CPU 928B Programming G uide
C79000-T8576-C898-01 14 - 11
Table 3-13 Set/rese t operati ons with formal operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 51
Table 3-14 Timer and counter operations wit h formal operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 52
Table 3-15 Load and transfer operati ons wit h formal operands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 54
Table 3-16 Load and transfer operati ons with special operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 55
Table 3-17 Arithmetic operation ENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 56
Table 3-18 Supplementary arithmetic operatio ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 57
Table 3-19 J ump operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 58
Table 3-20 Shi ft op erat ions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 60
Table 3-21 Co nversion operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 62
Table 3-22 De cre me nt/increment operatio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 65
Table 3-23 Processing operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 65
Table 3-24 Disabling/enabling process interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 71
Table 3-25 Disable/enable semaphore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 72
Table 4 -1 Meaning of the LE Ds "RUN " and "S TOP" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 5
Table 4-2 Comparison of th e differen t restart types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 21
Table 4-3 Assignment "Time in terrupt ti me - called OB" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 35
Table 4 -4 Collision of time in terrup t identifier s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 3 7
Table 5-1 Meaning of the control bits in the >>STP<< line. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 12
Table 5 -2 Meaning of the con tr ol bits in the >>ANL< < line. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 1 3
Table 5-3 Meani ng of the control bits in the >> RUN<< li ne. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 14
Table 5 -4 Meaning of the con tr ol bits in line s 4 a nd 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 14
Table 5 -5 Meaning of the con tr ol bits in line s 6 t o 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 16
Table 5 -6 Meaning of the I STACK IDs conce rning the poin t of error . . . . . . . . . . . . . . . . . . . . . . 5 - 1 9
List of Tables and Figu res
CPU 928B Programming Guide
14 - 12 C79000-T8576-C898-01
Table 5-7 ISTACK IDs CAUSE OF INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 22
Table 5 -8 The organiz ation b l o cks call ed in case of err ors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 2 9
Table 5-9 Causes of error and causes of interrupt in RESTART. . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 32
Table 5-10 IDs for DB 0 errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 33
Table 5-11 IDs for DB 1 errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 34
Table 5-12 IDs for DB 2 errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 35
Table 5-13 IDs for DX 0 errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 36
Table 5-14 IDs for DX 2 errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 36
Table 5-15 C auses of erro r and causes o f inte rrupt in RESTAR T and RUN, which lead
direct to STOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 38
Table 5-16 C auses of erro r and causes o f inte rrupt in RESTAR T and RUN, which lead
direct to STOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 39
Table 5-17 BCF subst itution error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 40
Table 5-18 BCF operat ion code err or . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 41
Table 5-19 BC F parameter error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 42
Table 5-20 LZF - calling a block that is not loaded . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 44
Table 5-21 LZF-loa d/transfer error (TR AF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 45
Table 5-22 LZF-other runti me errors/part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 46
Table 5-23 LZF-other runti me errors/part 2 (OB 182 iden ti fier) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 47
Table 5-24 LZF-other runti me errors/part 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 48
Table 5-25 LZF-other run time errors/part 4 (O B 150 identifiers) . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 49
Table 5-26 LZF-other run ti me errors/part 5 (ide ntifiers of OB 151, OB 152 and OB 153) . . . . . . . 5 - 50
Table 5-27 LZF-other run time errors/part 6 (ident ifi ers of d ifferent system operat ions) . . . . . . . . . 5 - 51
Table 5-28 QVZ fla gs wh en cal ling OB 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 54
Table 5-29 WECK-FE i dentifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 57
Table 5-30 REG-FE identifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 59
14
List of Tables and Fi gures
CPU 928B Programming G uide
C79000-T8576-C898-01 14 - 13
Table 6-1 Overview of the special functions av ai lable with the CPU 928B . . . . . . . . . . . . . . . . . . . 6 - 6
Table 6-2 OB 150 error IDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 31
Table 6-3 OB 151 error IDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 36
Table 6 -4 "Tim e job - Time parameter" as signment s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 3 7
Table 6-5 Cycle statistics variables - OB 152. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 41
Table 6-6 OB 153 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 42
Table 6-7 Results o f the OB 152 fu nctio ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 43
Table 6-8 OB 153 error IDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 49
Table 6-9 OB 182 error IDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 67
Table 6-10 Transferring the d ata block for PID control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 114
Table 6-11 Co ntrol word in the transfer DB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 117
Table 6-12 Norma lize d fixed point number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 124
Table 7-1 DX 0 paramet ers a nd their meaning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 8
Table 8-1 Structure of the memory area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 4
Table 8 -2 Assignment of RS 0 ( I nterrupt condit ion cod eword). . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 1 8
Table 8 -3 Assignment of RS 1 ( I nterrupt condit ion cod e rese t wo rd). . . . . . . . . . . . . . . . . . . . . . . 8 - 1 9
Table 8 -4 Assignment of RS 2 ( I nterrupt condit ion cod e group word) . . . . . . . . . . . . . . . . . . . . . . 8 - 2 1
Table 8 -5 Assignment of RS 5 ( STO P and RESTAR T I Ds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 2 3
Table 8 -6 Assignment of RS 6 ( C ycle and submo dule/MPL I Ds). . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 2 4
Table 8-7 Assignment of RS 7 (RESET IDs/Initialize error IDs) . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 25
Table 8 -8 Assignment of RS 8 ( E r ror ID s HW/S W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 26
Table 8-9 Assign ment of RS 29 (Slo t ID/CPU/P LC type). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 27
Table 8-10 Assignme nt of RS 131 (Disable all interrupts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 29
List of Tables and Figu res
CPU 928B Programming Guide
14 - 14 C79000-T8576-C898-01
Table 8-11 Assign me nt of RS 132 (Delay al l in terrupts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 29
Table 8-12 Ass ign me nt of RS 133 (Process image upd ating) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 30
Table 8-13 Assignme nt of RS 135 (Disable in dividual time interrupts) . . . . . . . . . . . . . . . . . . . . . . 8 - 31
Table 8-14 Assign me nt of RS 137 (Delay ind ividua l time interrupts). . . . . . . . . . . . . . . . . . . . . . . . 8 - 32
Table 8-15 Assignme nt of RS 140 (Write/read IDs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 33
Table 9-1 Operations for indirect memor y access using registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 8
Table 9-2 16-bit register for LIR /TIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 9
Table 9-3 Operations for field trans fer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 18
Table 9-4 Memory areas permitted for TN W, TXB a nd TXW . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 18
Table 9 -5 Load and arithme tic oper a tions with the BR r e gister. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 2 6
Table 9-6 Operations for transfer between registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 27
Table 9-7 Operations for accessing the local memor y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 28
Table 9-8 Operations for access to the gl obal me mory organized in bytes . . . . . . . . . . . . . . . . . . . 9 - 31
Table 9-9 Operations for access to the gl obal me mory organized in words . . . . . . . . . . . . . . . . . . 9 - 32
Table 9-10 Operati ons for access t o th e pages org anize d in bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 35
Table 9-11 Operati ons for access t o th e pages org anize d in wor ds . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 37
Table 10-1 Co nditi on codes of the communication OBs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 23
Table 10-2 Co de byte for th e communication OBs/n umb er groups. . . . . . . . . . . . . . . . . . . . . . . . 10 - 24
Table 10-3 Co nditi on code byte: Ini tializatio n conflict numbers. . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 25
Table 10-4 Condi tion code byte : Err or nu mbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 26
Table 10-5 Condi tion code bytes: Warning numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 28
Table 10-6 Ru ntimes of the commu nic atio n OBs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 29
14
List of Tables and Fi gures
CPU 928B Programming G uide
C79000-T8576-C898-01 14 - 15
Table 10-7 Ass ign me nt list for O B 200 (initi alize) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 35
Table 10-8 Link list for extending the IPC flag area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 66
Table 11-1 Fun ctions for inst allati on and testin g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 4
Table 11-2 Activities a t chec kpo ints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 18
Table 11-3 Fun ctions which can not run s imultan eously on bo th PGs . . . . . . . . . . . . . . . . . . . . . . 11 - 23
List of Tables and Figu res
CPU 928B Programming Guide
14 - 16 C79000-T8576-C898-01
List of Figures
Fig. 1-1 Tasks of th e system program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 8
Fig. 1-2 Structure of a STEP 5 user program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 11
F i g . 2 -1 M ethods of representation in the S TEP 5 p rogramming language . . . . . . . . . . . . . . . . . . 2 - 5
Fig. 2-2 Example of block storage in th e user memor y. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 16
Fig. 2-3 Block calls that enable processing of a program block . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 18
Fig. 2-4 Structure of a function block (FB/FX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 26
F i g . 2 -5 R ange of validity of an opene d d ata block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 4 2
Fig. 3-1 Principle of cyclic program execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 4
Fig. 3-2 Example of the organization o f the user program according
to th e program st ruc tur e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 6
Fig. 3-3 Example of the organization o f the user program according
to th e structure of the con tr olled system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 7
F i g . 3 -4 Nest ed logic b lock calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 8
Fig. 3-5 Example of block nesting depth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 9
Fig. 3-6 Load and transfer operations in a b yte-oriented memor y area. . . . . . . . . . . . . . . . . . . . . 3 - 23
Fig. 3-7 Load a nd transfer operations in a word-oriented memory area . . . . . . . . . . . . . . . . . . . . 3 - 24
F i g . 3 -8 C oor dina tion of access to the global memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 7 3
Fig. 4-1 Front panel of the CPU 928B with display and operating elem ents . . . . . . . . . . . . . . . . . 4 - 4
Fig. 4-2 Operating states and progra m processing le vels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 7
Fig. 4-3: Principle of lev el c ha nge and ISTACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 9
F i g . 4 -4 C hange of level a s a re sult of a double cal l err or. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 1 1
F i g . 4 -5 Dou ble call of er ror level BC D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 1 2
F i g . 4 -6 C yclic p rogram exe cution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 2 9
14
List of Tables and Fi gures
CPU 928B Programming G uide
C79000-T8576-C898-01 14 - 17
Fig. 4-7 Process interrupt, level triggered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 41
Fig. 4-8 Process interrupt, edge-triggered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 41
Fig. 4-9 Interrupt-driven program e xecution at bloc k boundaries. . . . . . . . . . . . . . . . . . . . . . . . . 4 - 43
Fig. 5-1 Example of the first screen form page "OUTPUT ISTACK": control bits . . . . . . . . . . . 5 - 11
Fig. 5-2 E xample of a screen page "OUTPUT ISTACK" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 18
Fig. 5-3 Example 1 of evaluating th e ISTACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 25
Fig 5-4 Example 2 of evaluating the ISTACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 26
Fig. 5-5 Example 2 of evaluating th e ISTACK: 1st ISTACK level . . . . . . . . . . . . . . . . . . . . . . . 5 - 27
Fig. 5-6 Example 2 of evaluating th e ISTACK: 2nd ISTACK lev el. . . . . . . . . . . . . . . . . . . . . . . 5 - 28
F i g . 6 -1 Eff ect s of the "ro l l up" funct ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 1 5
F i g . 6 -2 Eff ect s of the "ro l l do wn " function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 1 5
Fig. 6-3 Storing BST ACK entries in a data block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 55
F i g . 6 -4 C ontent s of the B STAC K i n this examp le . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 56
F i g . 6 -5 C ontent s of DX 1 0 in this example after OB 1 70 is called . . . . . . . . . . . . . . . . . . . . . . . 6 - 5 7
F i g . 6 -6 Shift ing the DB start address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 61
F i g . 6 -7 Transf e rring in bytes (OB 1 90 ) and words (OB 1 92) . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 69
F i g . 6 -8 Transf e rring in bytes (OB 1 91 ) and words (OB 1 93) . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 72
F i g . 6 -9 Sa vi ng the ar eas when th e program proces sing level ch anges. . . . . . . . . . . . . . . . . . . . . 6 - 7 5
Fig. 6-10 Swapping the high b yte and lo w byte in a DB using OB 193/OB 190 . . . . . . . . . . . . . . 6 - 76
F i g . 6 -11 L ocati on of the page address area on the S 5 b us . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 8 0
Fig . 6-12 Loc atio n of th e bytes whe n writ ing (OB 216) /
reading (OB 217) to/from a page in words or double words . . . . . . . . . . . . . . . . . . . . . 6 - 81
F i g . 6 -13 A C CU con tents bef o re c alling OB 216 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 8 3
F i g . 6 -14 A C CU con tents bef o re c alling OB 217 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 8 5
List of Tables and Figu res
CPU 928B Programming Guide
14 - 18 C79000-T8576-C898-01
F i g . 6 -15 A C CU con tents bef o re c alling OB 218 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 8 7
Fi g. 6- 16 Sch e ma ti c s ho w i ng t h e prin c iple of a shift regist er w i th 3 po in t ers a n d
12 memory cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 102
Fi g. 6- 17 Sch e ma ti c s ho w i ng t h e prin c iple of a shift regist er w i th 3 po in t ers a n d
12 memory c ells be fore the first clock p ul se . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 1 0 3
Fi g. 6- 18 Sch e ma ti c s ho w i ng t h e prin c iple of a shift regist er w i th 3 po in t ers a n d
12 memory c ells after th e fir s t clock pulse. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 1 0 3
Fig. 6-19 Structure of the data block for initializin g a shift register . . . . . . . . . . . . . . . . . . . . . . 6 - 105
Fig. 6-20 Block diagram of t he PID controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 110
Fig. 7-1 Structure of DX 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 6
F i g . 7 -2 PG s cre en f orm fo r assigning p arameters to DX 0 /part 1. . . . . . . . . . . . . . . . . . . . . . . . 7 - 1 5
F i g . 7 -3 PG s cre en f orm fo r assigning p arameters to DX 0 /part 2. . . . . . . . . . . . . . . . . . . . . . . . 7 - 1 6
Fig. 8-1 Address distribution in the CPU 928B - overvie w. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 5
Fig. 8-2 Address distribution - system RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 6
Fig. 8-3 Address distributi on - peripherals (8 bits) on the S5 bus. . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 7
F i g . 8 -4 B lock ad dr esses in DB 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 12
Fig. 8-5 E xample a): start address of DB 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 13
Fig. 8-6 RS area me mory map (part 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 16
Fig. 8-7 RS area me mory map (part 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 17
F i g . 9 -1 G lob al and local memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 5
Fig. 9-2 Ac cess to local or global me mory areas usin g absolute addresses (see also Fig. 9-1) . . . 9 - 7
Fig. 9-3 LIR/TIR with 16-bit memory areas (wor d-orient ed) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 10
Fig. 9-4 LIR/TIR with a-bit memor y areas (byte-oriented). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 10
Fig. 9-5 Using the DBA register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 12
Fig. 9-6 Using the DBL register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 15
14
List of Tables and Fi gures
CPU 928B Programming G uide
C79000-T8576-C898-01 14 - 19
F i g . 9 -7 Occupation of the accumulators during the progra m. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 1 7
F i g . 9 -8 Transf e rring blocks of memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 2 0
Fig. 9-9 Function block for trans ferring blocks of data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 21
F i g . 9 -10 L oading the BR regis ter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 26
Fig. 9-11 Register - register transfer operat ions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 28
F i g . 1 0-1 T ran sfer rin g IPC flags in the mu l tiproc ess or mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 6
Fig. 10-2 Example of IPC flag areas on the CPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 7
F i g . 1 0-3 PG scre en f orm fo r gene rating D B 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 - 1 0
F i g . 1 0-4 Sender/receiver ident ification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 - 1 4
Fig. 10-5 Example of the occupation of the COR buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 17
F i g . 1 0-6 Overview of the blocks req u i red in each CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 6 9
Fig. 10-7 Data exchange between 3 CPUs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 75
Fig. 11-1 Sequence of "program test" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 14
F i g . 1 1-2 U sing the se cond inte rface as a PG int erface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 - 2 0
Fig. 11-3 First example of a confi guration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 21
F i g . 1 1-4 S econd exampl e of a configur ation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 - 2 1
F i g . 1 1-5 H andling s imu ltaneou s jobs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 - 2 4
Fig. 11-6 Typical sequence of a cycli c fu nct ion and parallel sh ort-running function. . . . . . . . . 11 - 25
Fig. 11-7 Sequence of two parallel cyclic functio ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 27
Fig. 11-8 Sequence when a function blocks the CPU 928B . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 28
List of Tables and Figu res
CPU 928B Programming Guide
14 - 20 C79000-T8576-C898-01
Sie mens AG
AUT E 1163
Östliche Rheinbrückenstraße 50
D-76181 Karlsruhe
Federal Republic of Germany
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