U621708 128K x 8 SRAM Features Description S 131072 x 8 bit static CMOS RAM S 70 ns Access Time S Common data inputs and The U621708 is a static RAM manufactured using a CMOS process technology with the following operating modes: - Read - Standby - Write - Data Retention The memory array is based on a 6-Transistor cell. The circuit is activated by the rising edge of E2 (at E1 = L), or the falling edge of E1 (at E2 = H). The address and control inputs open simultaneously. According to the information of W and G, the data inputs, or outputs, are active. During the active state (E1 = L and E2 = H) each address change leads to a new Read cycle. In a Read cycle, the data outputs are activated by the falling edge of G, afterwards the data word will be data outputs S Three-state outputs S Typ. operating supply current S S S S S S S S 70 ns: 15 mA Standby current < 1 mA at 85C TTL/CMOS-compatible Power supply voltage 5 V Operating temperature range 0 C to 70 C -40 C to 85 C QS 9000 Quality Standard ESD protection > 750 V (MIL STD 883C M3015.7) Latch-up immunity >100 mA Package: PDIP32 (600 mil) SOP32 (450 mil) TSOP I 32 sTSOP I 32 Pin Configuration Pin Description n.c. 1 32 VCC A11 1 32 G A16 2 31 A15 A9 2 31 A10 A14 3 30 E2 A8 3 30 E1 A12 4 29 W A13 4 29 DQ7 A7 5 28 A13 W 5 28 DQ6 A6 6 27 A8 E2 6 27 DQ5 A5 7 26 A9 A15 7 26 DQ4 A4 8 A11 VCC 8 9 TSOP 25 sTSOP DQ3 A3 PDIP 25 SOP A2 24 G n.c. 9 10 23 A10 A16 A1 11 22 E1 A0 12 21 DQ0 13 DQ1 DQ2 VSS available at the outputs DQ0-DQ7. After the address change, the data outputs go High-Z until the new information is available. The data outputs have no preferred state. If the memory is driven by CMOS levels in the active state, and if there is no change of the address, data input and control signals W or G, the operating current (IO = 0 mA) drops to the value of the operating current in the Standby mode. The Read cycle is finished by the falling edge of E2 or W, or by the rising edge of E1, respectively. Data retention is guaranteed down to 2 V. With the exception of E1 and E2, all inputs consist of NOR gates, so that no pull-up/pull-down resistors are required. Signal Name Signal Description A0 - A16 Address Inputs DQ0 - DQ7 Data In/Out E1 E2 Chip Enable 1 Chip Enable 2 G Output Enable Write Enable 24 VSS 10 23 DQ2 A14 11 22 DQ1 W VCC Power Supply Voltage DQ7 A12 12 21 DQ0 VSS Ground 20 DQ6 A7 13 20 A0 n.c. not connected 14 19 DQ5 A6 14 19 A1 15 18 DQ4 A5 15 18 A2 16 17 16 17 A3 Top View September 1, 2004 DQ3 A4 Top View 1 U621708 Row Decoder Memory Cell Array 1024 Rows x 128 x 8 Columns Column Decoder DQ0 Sense Amplifier/ Write Control Logic Address Change Detector Clock Generator DQ1 Common Data I/O A10 A11 A12 A13 A14 A9 A15 Column Address Inputs A0 A1 A2 A3 A4 A5 A6 A7 A8 A16 Row Address Inputs Block Diagram DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 VCC VSS E1 E2 W G Truth Table Operating Mode E1 E2 W G DQ0 - DQ7 * L * * High-Z H * * * High-Z Internal Read L H H H High-Z Read L H H L Data Outputs Low-Z Write L H L * Data Inputs High-Z Standby/not selected * H or L 2 September 1, 2004 U621708 Characteristics All voltages are referenced to V SS = 0 V (ground). All characteristics are valid in the power supply voltage range and in the operating temperature range specified. Dynamic measurements are based on a rise and fall time of 5 ns, measured between 10 % and 90 % of V I, as well as input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V, with the exception of the tdis-times and ten-times, in which cases transition is measured 200 mV from steady-state voltage. Absolute Maximum Ratings a Symbol Min. Max. Unit VCC -0.5 7 V Input Voltage VI -0.5 VCC + 0.5 b V Output Voltage VO -0.5 VCC + 0.5 b V Power Dissipation PD - 1 W Ta 0 -40 70 85 C Tstg -65 150 C 200 mA Power Supply Voltage Operating Temperature C-Type K-Type Storage Temperature Output Short-Circuit Current at VCC = 5 V and VO = 0 V c a b c Stresses greater than those listed under Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability Maximum voltage is 7 V Not more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s. Recommended Operating Conditions Symbol Power Supply Voltage Input Low Voltage * Input High Voltage d | IOS | Conditions Min. Max. Unit VCC 4.5 5.5 V VIL -0.3 0.8 V VIH 2.2 VCC + 0.3 V -2 V at Pulse Width 10 ns September 1, 2004 3 U621708 Electrical Characteristics Symbol Conditions Min. Max. Unit VCC VIL VIH = 5.5 V = 0.8 V = 2.2 V 30 mA VCC = 5.5 V = V CC - 0.2 V 1 mA ICC(SB)1 VCC = 5.5 V = 2.2 V 10 mA VE1= VE2 Output High Voltage VOH Output Low Voltage VOL VCC IOH VCC IOL = 4.5 V = -4.0 mA = 4.5 V = 8.0 mA VCC VIH VCC VIL = 5.5 V = 5.5 V = 5.5 V = 0V VCC VOH VCC VOL = = = = VCC VOH VCC VOL = 5.5 V = 5.5 V = 5.5 V = 0V Supply Current - Operating Mode ICC(OP) Supply Current - Standby Mode (CMOS level) ICC(SB) Supply Current - Standby Mode (TTL level) Input High Leakage Current IIH Input Low Leakage Current IIL Output High Current IOH Output Low Current IOL Output Leakage Current High at Three-State Outputs IOHZ Low at Three-State Outputs IOLZ VE1= VE2 4 4.5 V 2.4 V 4.5 V 0.4 V 2.4 V 0.4 V 2 A -2 A -4 8 mA 2 -2 mA A A September 1, 2004 U621708 Switching Characteristics Read Cycle Symbol 70 Unit Alt. IEC Min. Read Cycle Time tRC tcR 70 Address Access Time to Data Valid tAA ta(A) 70 ns Chip Enable Access Time to Data Valid tACE ta(E) 70 ns G LOW to Data Valid tOE ta(G) 25 ns E1 HIGH or E2 LOW to Output in High-Z tHZCE tdis(E) 15 ns G HIGH to Output in High-Z tHZOE tdis(G) 15 ns E1 LOW or E2 HIGH to Output in Low-Z tLZCE ten(E) 10 ns G LOW to Output in Low-Z tLZOE ten(G) 5 ns Output Hold Time from Address Change tOH tv(A) 10 ns E1 LOW or E2 HIGH to Power-Up Time tPU 0 ns E1 HIGH or E2 LOW to Power-Down Time tPD Switching Characteristics Write Cycle Max. ns 70 Symbol ns 70 Unit Alt. IEC Min. Write Cycle Time tWC tcW 70 ns Write Pulse Width tWP tw(W) 35 ns Write Setup Time tWP tsu(W) 35 ns Address Setup Time tAS tsu(A) 0 ns Address Valid to End of Write tAW tsu(A-WH) 35 ns Chip Enable Setup Time tCW tsu(E) 40 ns Pulse Width Chip Enable to End of Write tCW tw(E) 40 ns Data Setup Time tDS tsu(D) 25 ns Data Hold Time tDH th(D) 0 ns Address Hold from End of Write tAH th(A) 0 ns W LOW to Output in High-Z tHZWE tdis(W) 20 ns G HIGH to Output in High-Z tHZOE tdis(G) 15 ns W HIGH to Output in Low-Z tLZWE ten(W) 5 ns G LOW to Output in Low-Z tLZOE ten(G) 5 ns W to Chip Enable Setup Time tWE tsu(W-E) 10 ns September 1, 2004 5 Max. U621708 Data Retention Mode Data Retention Characteristics Symbol Alt. Conditions IEC Min. 2 Data Retention Supply Voltage VCC(DR) Data Retention Supply Current ICC(DR) VCC(DR) = 3 V VE1 =VE2 = V CC(DR) - 0.2 V tCDR tsu(DR) tR trec See Data Retention Waveforms (below) Data Retention Setup Time Operating Recovery Time Typ. Max. Unit 5.5 V 0.6 mA 0 ns tcR ns Data Retention Mode E1 - controlled VCC 4.5 V VCC(DR) 2 V 2.2 V tsu(DR) Data Retention 2.2 V E1 trec 0V VE2(DR) VCC(DR) - 0.2 V or V E2(DR) 0.2 V VCC(DR) - 0.2 V VE1(DR) V CC(DR) + 0.3 V Data Retention Mode E2 - controlled VCC 4.5 V VCC(DR) 2 V tDR E2 Data Retention trec 0.8 V 0.8 V 0V VE1(DR) VCC(DR) - 0.2 V or VE1(DR) 0.2 V VE2(DR) 0.2 V 6 September 1, 2004 U621708 Test Configuration for Functional Check 5V VCC DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 481 VO 30 pF e E1 E2 W G e Simultaneous measurement of all 8 output pins VIL Input level according to the relevant test measurement VIH A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 255 VSS In measurement of tdis(E),tdis(W), ten(E), ten(W), ten(G) the capacitance is 5 pF. Capacitance Input Capacitance Output Capacitance Conditions VCC VI f Ta Symbol = 5.0 V = VSS = 1 MHz = 25 C Min. Max. Unit CI 7 pF Co 7 pF All pins not under test must be connected with ground by capacitors. Ordering Code Example U621708 S K 07 Type Package D = PDIP32 (600 mil) S = SOP32 (450 mil) T = TSOP I 32 T1 = sTSOP I 32 f Leadfree Option blank = Standard Package G1 = Leadfree Green Package f Access Time 07 = 70 ns Operating Temperature Range C = 0 to 70 C K = -40 to 85 C on special request Device Marking (example) Product specification Assembly location and trace code ZMD U621708SK 07 C 0425 1 ZZ G1 Internal Code September 1, 2004 Date of manufacture (The first 2 digits indicating the year, and the last 2 digits the calendar week.) Leadfree Green Package 7 U621708 Read Cycle 1: Ai-controlled (during Read Cycle : E1 = G = VIL, W = E2 = VIH) tcR Ai Address Valid ta(A) DQi Output Data Valid Previous Data Valid Output tv(A) Read Cycle 2: G-, E1, E2-controlled (during Read Cycle: W = V IH) tcR Ai E1 Addresses Valid ta(E) tsu(A) ten(E) tsu(A) G DQi tdis(E) ten(E) E2 Output tdis(E) ta(E) ta(G) tdis(G) ten(G) High-Z Output Data Valid tPD* tPU * ICC(OP) ICC(SB) 50 % 50 % * The same applies to E1 Write Cycle1: W-controlled tcW Ai Addresses Valid th(A) tsu(E) E1 tsu(E) E2 W tsu(W-E) tsu(W-E) tw(W) tsu(A) tsu(D) DQi Input DQi tdis(W) th(D) Input Data Valid ten(W) High-Z Output G 8 September 1, 2004 U621708 Write Cycle 2: E1-controlled tcW Ai tsu(A) E1 Addresses Valid tw(E) th(A) tsu(E) E2 tsu(W) W Input DQi th(D) tsu(D) DQi ten(E) Input Data Valid tdis(W) High-Z Output tdis(G) G Write Cycle 3 (E2-controlled) tcW Ai E1 Addresses Valid tsu(E) tsu(A) E2 tw(E) tsu(W) W DQi Input DQi th(A) tsu(D) ten(E) th(D) Input Data Valid tdis(W) High-Z tdis(G) Output G undefined L- to H-level H- to L-level The information describes the type of component and shall not be considered as assured characteristics.Terms of delivery and rights to change design reserved. September 1, 2004 9 U621708 LIFE SUPPORT POLICY ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the ZMD product could create a situation where personal injury or death may occur. Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose. LIMITED WARRANTY The information in this document has been carefully checked and is believed to be reliable. However Zentrum Mikroelektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it. The information in this document describes the type of component and shall not be considered as assured characteristics. ZMD does not guarantee that the use of any information contained herein will not infringe upon the patent, trademark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This document does not in any way extent ZMD's warranty on any product beyond that set forth in its standard terms and conditions of sale. ZMD reserves terms of delivery and reserves the right to make changes in the products or specifications, or both, presented in this publication at any time and without notice. September 1, 2004 Zentrum Mikroelektronik Dresden AG Grenzstrae 28 * D-01109 Dresden * P. O. B. 80 01 34 * D-01101 Dresden * Germany Phone: +49 351 8822 306 * Fax: +49 351 8822 337 * Email: memory@zmd.de * http://www.zmd.de