CLC006
CLC006 Serial Digital Cable Driver with Adjustable Outputs
Literature Number: SNLS015F
CLC006
August 22, 2011
Serial Digital Cable Driver with Adjustable Outputs
General Description
National’s Comlinear CLC006 is a monolithic, high-speed ca-
ble driver designed for the SMPTE 259M serial digital video
data transmission standard. The CLC006 drives 75Ω trans-
mission lines (Belden 8281 or equivalent) at data rates up to
400 Mbps. Controlled output rise and fall times (650 ps typi-
cal) minimize transition-induced jitter. The output voltage
swing, typically 1.65V, set by an accurate, low-drift internal
bandgap reference, delivers an 800 mV swing to back-
matched and terminated 75Ω cable. Output swing is ad-
justable from 0.7 VP-P to 2 VP-P using external resistors.
The CLC006’s class AB output stage consumes less power
than other designs, 185 mW with both outputs terminated,
and requires no external bias resistors. The differential inputs
accept a wide range of digital signals from 200 mVP-P to ECL
levels within the specified common-mode limits. All this make
the CLC006 an excellent general purpose high speed driver
for digital applications.
The CLC006 is powered from a single +5V or −5.2V supply
and comes in an 8-pin SOIC package.
Key Specifications
■650 ps rise and fall times
■Data rates to 400 Mbps
■200 mV differential input
■Low residual jitter (25 pspp)
Features
■No external pull-down resistors
■Adjustable output amplitude
■Differential input and output
■Low power dissipation
■Single +5V or −5.2V supply
■Replaces GS9008 in most applications
Applications
■Digital routers and distribution amplifiers
■Coaxial cable driver for digital transmission line
■Twisted pair driver
■Serial digital video interfaces for the commercial and
broadcast industry
■SMPTE, Sonet/SDH, and ATM compatible driver
■Buffer applications
Typical Application
10008402
© 2011 National Semiconductor Corporation 100084 www.national.com
CLC006 Serial Digital Cable Driver with Adjustable Outputs
270 Mbps Eye Pattern
10008401
Connection Diagram (8-Pin SOIC)
10008403
Order Number CLC006BM
See NS Package Number M08A
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CLC006
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage 6V
Output Current 30 mA
Maximum Junction Temperature +125°C
Storage Temperature Range −65°C to +150°C
Lead Temperature
(Soldering 10 Seconds) +300°C
ESD Rating (Human Body Model) 1000V
Package Thermal Resistance
θJA 8–pin SOIC
θJC 8–pin SOIC
+160°C/W
+105°C/W
Reliability Information MTTF 254 Mhr
Recommended Operating
Conditions
Supply Voltage Range (VCC – VEE) +4.5V to +5.5V
Electrical Characteristics
(VCC = 0V, VEE = −5V; unless otherwise specified).
Parameter Condition Typ +25°C Min/Max
+25°C
Min/Max
0°C to
+70°C
Min/Max
−40°C to
+85°C
Units
STATIC DC PERFORMANCE
Supply Current, Loaded 150Ω @ 270 Mbps (Note
5)37 — — — mA
Supply Current, Unloaded (Note 3) 34 28/45 26/47 26/47 mA
Output HIGH Voltage (VOH)(Note 3) −1.7 −2.0/1.4 −2.0/1.4 −2.0/1.4 V
Output LOW Voltage (VOL)(Note 3) −3.3 −3.6/3.0 −3.6/3.0 −3.6/3.0 V
Input Bias Current 10 30 50 50 μA
Output Swing REXT = ∞(Note 3)1.65 1.55/1.75 1.53/1.77 1.51/1.79 V
Output Swing REXT = 10 kΩ1.30 — — — V
Common Mode Input Range Upper Limit −0.7 −0.8 −0.8 −0.8 V
Common Mode Input Range Lower Limit −2.6 −2.5 −2.5 –2.5 V
Minimum Differential Input Swing 200 200 200 200 mV
Power Supply Rejection Ratio (Note 3) 26 20 20 20 dB
AC PERFORMANCE
Output Rise and Fall Time (Note 3, Note 4, Note 5) 650 425/825 400/850 400/850 ps
Overshoot 5 %
Propagation Delay 1.0 ns
Duty Cycle Distortion 50 ps
Residual Jitter 25 — — — pspp
MISCELLANEOUS PERFORMANCE
Input Capacitance 1.0 pF
Output Resistance 10 Ω
Output Inductance 6 nH
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Min/Max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined
from tested parameters.
Note 3: Spec is 100% tested at +25°C
Note 4: Measured between the 20% and 80% levels of the waveform.
Note 5: Measured with both outputs driving 150Ω, AC coupled at 270 Mbps.
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CLC006
Operation
INPUT INTERFACING
The CLC006 has high impedance, emitter-follower buffered,
differential inputs. Single-ended signals may also be input.
Transmission lines supplying input signals must be properly
terminated close to the CLC006. Either A.C. or D.C. coupling
as in Figure 2 or Figure 3 may be used.Figures 2, 4 and Figure
5 show how Thevenin-equivalent resistor networks are used
to provide input termination and biasing. The input D.C. com-
mon-mode voltage range is 0.8V to 2.5V below the positive
power supply (VCC). Input signals plus bias should be kept
within the specified common-mode range. For an 800 mVP-P
input signal, typical input bias levels range from 1.2V to 2.1V
below the positive supply.
Load Type Resistor to VCC (R1) Resistor to VEE (R2)
ECL, 50Ω, 5V, VT=2V 82.5Ω 124Ω
ECL, 50Ω, 5.2V, VT=2V 80.6Ω 133Ω
ECL, 75Ω, 5V, VT=2V 124Ω 187Ω
ECL, 75Ω, 5.2V, VT=2V 121Ω 196Ω
800 mVP-P, 50Ω, 5V, VT=1.6V 75.0Ω 154Ω
800 mVP-P, 75Ω, 5V, VT=1.6V 110Ω 232Ω
800 mVP-P, 2.2KΩ, 5Ω, VT=1.6V 3240Ω 6810Ω
10008404
FIGURE 1. Input Stage
10008405
FIGURE 2. AC Coupled Input
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CLC006
10008406
FIGURE 3. DC Coupled Input
10008407
FIGURE 4. Single Ended 50Ω ECL input
10008408
FIGURE 5. Differential 50Ω ECL Input
OUTPUT INTERFACING
The CLC006’s class AB output stage, Figure 6, requires no
standing current in the output transistors and therefore re-
quires no biasing or pull-down resistors. Advantages of this
arrangement are lower power dissipation and fewer external
components. The output may be either D.C. or A.C. coupled
to the load. A bandgap voltage reference sets output voltage
levels which are compatible with F100K and 10K ECL when
correctly terminated. The outputs do not have the same out-
put voltage temperature coefficient as 10K. Therefore, noise
margins will be reduced over the full temperature range when
driving 10K ECL. Noise margins will not be affected when in-
terfacing to F100K since F100K is fully voltage and tempera-
ture compensated.
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CLC006
10008409
FIGURE 6. Output Stage
10008410
FIGURE 7. Differential Input DC Coupled Output
OUTPUT AMPLITUDE ADJUSTMENT
The high and low output levels of the CLC006 are set by a
circuit shown simplified in Figure 8. Output high and low levels
may be set independently with external resistor networks
connected between REXT-H (pin 3), REXT-L (pin 4) and the
power supplies. The resistor networks affect the high and low
output levels by changing the internally generated bias volt-
ages, VH and VL. The nominal high and low output levels are
VCC−1.7V and VCC−3.3V, respectively, when the pins REXT-H
and REXT-L are left unconnected. Though the internal compo-
nents which determine output voltage levels have accurate
ratios, their absolute values may be controlled only within
about ±15% of nominal. Even so, without external adjustment,
output voltages are well controlled. A final design should ac-
commodate the variation in externally set output voltages due
to the CLC006’s part-to-part and external component toler-
ances.
Output voltage swing may be reduced with the circuit shown
in Figure 9. A single resistance chosen with the aid of the
graph, Figure 10, is connected between pins 3 and 4. Output
voltage swing may be increased with the circuit of Figure 11.
Figure 12 is used to estimate a value for resistor R. Note that
both of these circuits and the accompanying graphs assume
that the CLC006 is loaded with the standard 150Ω. Be aware
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CLC006
that output loading will affect the output swing and the high
and low levels. It may be necessary to empirically select re-
sistances used to set output levels when the D.C. loading on
the CLC006 differs appreciably from 150Ω.
10008411
FIGURE 8. Equivalent Bias Generation Circuit
10008412
FIGURE 9. Differential Input Reduced Output
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CLC006
10008413
FIGURE 10. Resistance Pins 3 to 4 vs Output Voltage Reduced Output @ 150Ω Load
10008414
FIGURE 11. Differential Input Increased Output
10008415
FIGURE 12. Resistance Pins 3 to 4 vs Output Voltage Increased Output @ 150Ω Load
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CLC006
OUTPUT RISE AND FALL TIMES
Output load capacitance can significantly affect output rise
and fall times. The effect of load capacitance, stray or other-
wise, may be reduced by placing the output back-match
resistor close to the output pin and by minimizing all intercon-
necting trace lengths. Figure 13 shows the effect on risetime
of parallel load capacitance across a 150Ω load.
10008416
FIGURE 13. Rise Time vs CL
PCB Layout Recommendations
Printed circuit board layout affects the performance of the
CLC006. The following guidelines will aid in achieving satis-
factory device performance.
•Use a ground plane or power/ground plane sandwich
design for optimum performance.
•Bypass device power with a 0.01 µF monolithic ceramic
capacitor in parallel with a 6.8 µF tantalum electrolytic
capacitor located no more than 0.1” (2.5 mm) from the
device power pins.
•Provide short, symmetrical ground return paths for:
—inputs,
—supply bypass capacitors and
—the output load.
•Provide short, grounded guard traces located
—under the centerline of the package,
—0.1” (2.5 mm) from the package pins
—on both top and bottom of the board with connecting
vias.
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CLC006
Physical Dimensions inches (millimeters) unless otherwise noted
Order Number CLC006BM
NS Package Number M08A
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CLC006
Notes
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CLC006
Notes
CLC006 Serial Digital Cable Driver with Adjustable Outputs
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