August 2009 Doc ID 15791 Rev 3 1/40
40
STMPE321
3-channel capacitive touchkey controller
Features
■Up to 3 GPIOs
■Up to 3 capacitive touchkey inputs
■Operating voltage 1.65 - 1.95 V
■Interrupt output pin
■I2C interface (1.8 V operation, 3.3 V tolerant)
■8 kV HBM ESD protection
■40 fF resolution, 128-step capacitance
measurement
■Advanced data filtering (AFS)
■Environment tracking calibration (ETC)
■Individually adjustable touch variance (TVR)
settings for all channels
■Adjustable environmental variance (EVR) for
optimal calibration
■Capacitive key sensing capability in 27 µA
sleep mode
Applications
■Mobile phones and smartphones
■Portable media players
■Game consoles
Description
The STMPE321 is a 3-channel capacitive
touchkey controller. Capacitance measurement is
implemented in fully optimized hardware.
All 3 I/Os can be configured via an I2C bus to
function as either capacitive touchkey, or as
GPIOs (general purpose I/O).
QFN12
(2.2 x 1.5 mm)
Table 1. Device summary
Order code Package Packing
STMPE321QTR QFN12 (2.2 x 1.5 mm) Tape and reel
www.st.com
Contents STMPE321
2/40 Doc ID 15791 Rev 3
Contents
1 STMPE321 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 STMPE321 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Pin assignment and function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 STMPE321 typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Capacitance compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Calibration algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.1 Noise filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.2 Data filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3I
2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 Register map and function description . . . . . . . . . . . . . . . . . . . . . . . . . 12
5 System and identification registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6 Interrupt controller module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7 GPIO controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8 Capacitive touch module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
10 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10.1 Capacitive sensing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
11 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
STMPE321 STMPE321 functional overview
Doc ID 15791 Rev 3 3/40
1 STMPE321 functional overview
The STMPE321 consists of the following blocks:
●GPIO controller
●Impedance sensor
●Touchkey controller
●I2C interface
1.1 STMPE321 block diagram
Figure 1. Functional block diagram
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Impedance
sensor
IO
controller Touch 0-2
GPIO 0-2
GND
VCC
Touchkey
controller
A
Ref
Host
interface
SCLK
SDA
INT
RST
STMPE321 functional overview STMPE321
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1.2 Pin assignment and function
Figure 2. QFN12 pin assignment (top view)
Table 2. Pin assignment and function
Pin number Pin name Description
1 GPIO_2 / touch 2 GPIO 2
2 GPIO_1 / touch 1 GPIO 1
3 GPIO_0 / touch 0 GPIO 0
4NC-
5SDAI
2C data
6SCLI
2C clock
7GNDGND
8 VCC Supply voltage
9 ARef Reference capacitor for touch sensor
10 NC -
11 INT INT output (open drain)
12 RST RESET (active low)
This pin is internally pulled up to VCC
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STMPE321 STMPE321 functional overview
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1.3 STMPE321 typical application
The STMPE321 is capable of supporting capacitive sensors of up to 3 channels.
Figure 3. Typical application diagram
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Capacitance compensation STMPE321
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2 Capacitance compensation
The STMPE321 is capable to measuring up to 5.1pF in capacitance difference between the
reference point (Zref) and the individual channels. In the case where PCB connection
between the sensor pads and the device is too long, the "REFERENCE DELAY" register is
able to shift the reference by up to 5.1pF, allowing the TOUCH channels to measure added
capacitance 5.1pF with offset of 5.1pF, as shown in following diagram.
In the case where this is still not enough to compensate for the capacitance on sensor lines
(due to very long sensor trace), an external capacitor of up to 30 pF could be connected at
the A_Ref pin.
This would further shift up the dynamic range of the capacitance measurement.
Figure 4. Capacitance compensation
The sensed capacitance is accessible to the host through the IMPEDANCE registers.
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STMPE321 Capacitance compensation
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2.1 Calibration algorithm
The STMPE321 maintains 2 parameters for each touch channel: TVR and CALIBRATED
IMPEDANCE. CALIBRATED IMPEDANCE is an internal reference which, if the currently
measured IMPEDANCE exceeds the CALIBRATED IMPEDANCE by a magnitude of TVR, is
considered a “TOUCH”.
If the IMPEDANCE is higher than the CALIBRATED IMPEDANCE, but the magnitude does
not exceed CALIBRATED IMPEDANCE by TVR, it is not considered a TOUCH. In this case,
2 scenarios are possible:
1. Environmental changes have caused the IMPEDANCE to increase
2. Finger is near the sensing pad, but not near enough
In case 1, the change in IMPEDANCE is expected to be small, as environmental changes
are normally gradual. A value "EVR" is maintained to specify the maximum IMPEDANCE
change that is still considered an environmental change.
‘IMP’ and ‘CALIBRATED IMP’ used in this table is not the direct register read-out.
IMP = 127 - impedance register readout
CALIBRATED IMP = 127 - calibrated impedance register readout.
The ETC WAIT register states a period of time for which all TOUCH inputs must remain "NO
TOUCH" for the next calibration to be carried out.
The CAL INTERVAL states the period of time between successive calibrations when there
are prolonged NO TOUCH conditions.
Table 3. Calibration action under different scenarios
Scenario Touch sensing and calibration action
IMP>CALIBRATED IMP + TVR TOUCH,
no calibration
IMP<CALIBRATED IMP + TVR
IMP>CALIBRATED IMP + EVR
NO TOUCH,
no calibration
IMP<CALIBRATED IMP + TVR
IMP<CALIBRATED IMP + EVR
IMP>CALIBRATED IMP
NO TOUCH,
new CALIBRATED IMP = previous CALIBRATED
IMP + change in IMP
IMP>CALIBRATED IMP CALIBRATED IMP + change in IMP
IMP<CALIBRATED IMP NO TOUCH,
new CALIBRATED IMP = new IMP
Capacitance compensation STMPE321
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2.1.1 Noise filtering
When the STMPE321 is operating in the vicinity of highly emissive circuits (DC-DC
converters, PWM controllers/drives etc.), the sensor inputs can be affected by high-
frequency noise. In this situation, the time-integrating function can be used to distinguish
between a real touch, or an emission-related false touch.
The INTEGRATION TIME and STRENGTH THRES registers are used to configure the time-
integrating function of the STMPE321.
2.1.2 Data filtering
The output from the calibration unit provides an instantaneous TOUCH or NO TOUCH
status. This output is directed to the filtering stage where the TOUCH is integrated across a
programmable period of time. The output of the integration stage is a “STRENGTH" (in the
STRENGTH register) that indicates the number of times a TOUCH is detected across the
integration period.
The STRENGTH is then compared to the value in STRENGTH THRESHOLD register. If
STRENGTH exceeds the STRENGTH THRESHOLD, it is considered a final, filtered
TOUCH status.
In the data filtering stage, 3 modes of operation are supported:
Mode 1: Only the touch channel with highest STRENGTH is taken
Mode 2: All touch channels with STRENGTH > STRENGTH THRESHOLD are taken
Mode 3: The 2 touch channels with the highest STRENGTH are taken.
These modes are selected using the FEATURE SELECTOR register. The final, filtered data
is accessible through the Touch Byte register.
STMPE321 Capacitance compensation
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2.2 Power management
The STMPE321 operates in 3 states, as described below:
Figure 5. STMPE321 operating states
On RESET, the STMPE321 enters the ACTIVE state immediately.
Upon a fixed period of inactivity, the device enters a SLEEP state. Any touch activity
occurring during a SLEEP state causes the device to return to an ACTIVE state.
In SLEEP mode:
-Calibration continues if the F2A bit is set in the CONTROL register
-Calibration stops if the F2A bit is NOT set in the CONTROL register
If no touch activity is expected, the host may set the device to a HIBERNATE state to save
power.
If any key is touched and held, the I2C command to enter SLEEP or HIBERNATE is put on
hold until the key is released.
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I2C interface STMPE321
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3 I2C interface
The following features are supported by the I2C interface:
●I2C slave device
●Compliance with Philips I2C specification version 2.1
●Standard (up to 100 kbps) and fast (up to 400 kbps) modes.
●7-bit and 10-bit device addressing modes
●General call
●Start/Restart/Stop
●I2C address is 0x58 (0xB0/0xB1 for write/read, including the LSB)
Start condition
A Start condition is identified by a falling edge of SDATA while SCLK is stable at high state.
A Start condition must precede any data/command transfer. The device continuously
monitors for a Start condition and does not respond to any transaction unless one is
encountered.
Stop condition
A Stop condition is identified by a rising edge of SDATA while SCLK is stable at high state.
A Stop condition terminates communication between the slave device and bus master. A
read command that is followed by NoAck can be followed by a Stop condition to force the
slave device into idle mode. When the slave device is in idle mode, it is ready to receive the
next I2C transaction. A Stop condition at the end of a write command stops the write
operation to the registers.
Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter
releases the SDATA after sending eight bits of data. During the ninth bit, the receiver pulls
the SDATA low to acknowledge the receipt of the eight bits of data. The receiver may leave
the SDATA in high state if it does not acknowledge the receipt of the data.
Data Input
The device samples the data input on SDATA on the rising edge of the SCLK. The SDATA
signal must be stable during the rising edge of SCLK and the SDATA signal must change
only when SCLK is driven low.
Memory addressing
For the bus master to communicate to the slave device, the bus master must initiate a Start
condition, followed by the slave device address. Accompanying the slave device address,
there is a Read/WRITE bit (R/W). The bit is set to 1 for a read operation, and 0 for a write
operation.
If a match occurs on the slave device address, the corresponding device gives an
acknowledgement on the SDA during the 9th bit time. If there is no match, it deselects itself
from the bus by not responding to the transaction.
STMPE321 I2C interface
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Table 4. Operation modes
Figure 6. Read and write modes (random and sequential)
Mode Byte Programming sequence
Read ≥1
Start, Device address, R/W = 0, Register address to be read
Restart, Device address, R/W = 1, Data Read, STOP
If no Stop is issued, the Data Read can be continuously performed. If
the register address falls within the range that allows an address auto-
increment, then the register address auto-increments internally after
every byte of data being read. For those register addresses that fall
within a non-incremental address range, the address is kept static
throughout the entire write operations. Refer to the memory map table
for the address ranges that are auto and non-increment. An example
of such a non-increment address is FIFO.
Write ≥1
Start, Device address, R/W = 0, Register address to be written, Data
Write, Stop
If no Stop is issued, the Data Write can be continuously performed. If
the register address falls within the range that allows address auto-
increment, then the register address auto-increments internally after
every byte of data being written in. For those register addresses that
fall within a non-incremental address range, the address is kept static
throughout the entire write operations. Refer to the memory map table
for the address ranges that are auto and non-increment.
Start
R/W=0
Ack
Device
Address
Reg
Address
Ack
Restart
Device
Address
Ack
R/W=1
Data
Read
No Ack
Stop
One byte
Read
Start
R/W=0
Ack
Device
Address
Reg
Address
Ack
Restart
Device
Address
Ack
R/W=1
Data
Read
Ack
More than one byte
Read
Ack
No Ack
Stop
Data
Read + 1
Data
Read + 2
Start
R/W=0
Ack
Device
Address
Reg
Address
Ack
Data
to be
written
Ack
Stop
One byte
Write
More than one byte
Read
Start
R/W=0
Ack
Device
Address
Reg
Address
Ack
Data to
Write
Ack
Stop
Data to
Write + 2
Ack
Ack
Data to
Write + 1
Master
Slave
Register map and function description STMPE321
12/40 Doc ID 15791 Rev 3
4 Register map and function description
This section lists and describes the registers in the STMPE321 device starting with a
register map, and then provides detailed descriptions of the register types.
Table 5. Register summary map table
Address Register name Bit Type Reset value Function
0x00 CHIP_ID_0 8 R 0x03 Device identification
0x01 CHIP_ID_1 8 R 0x21 Device identification
0x02 ID_VER 8 R 0x03 Revision number
0x03 SYS_CFG_1 8 R/W 0x00 System configuration 1
0x04 SYS_CFG_2 8 R/W 0xEF System configuration 2
0x08 INT_CTRL 8 R/W 0x01 Interrupt control register
0x09 INT_EN 8 R/W 0x01 Interrupt enable register
0x0A INT_STA 8 R 0x09 Interrupt status register
0x0B GPIO_INT_EN_lsb 8 R/W 0x00 GPIO interrupt enable register
0x0C GPIO_INT_EN_msb 8 R/W 0x00 GPIO interrupt enable register
0x0D GPIO_INT_STA_lsb 8 R/W 0x00 GPIO interrupt status register
0x0E GPIO_INT_STA_msb 8 R/W 0x00 GPIO interrupt status register
0x10 GPIO_MR 8 R/W 0x00 GPIO monitor pin
0x12 GPIO_SET 8 R/W 0x00 GPIO set pin state register
0x14 GPIO_DIR 8 R/W 0x00 GPIO set pin direction register
0x16 GPIO_FUNCT 8 R/W 0x00 GPIO function register
0x18 TOUCH_FIFO 64 R 0x00 Fifo access for touch data buffer
0x20 FEATURE_SEL 8 R/W 0x04 Feature selection
0x21 ETC_WAIT 8 R/W 0x27 Wait time
0x22 CAL_INTERVAL 8 R/W 0x30 Calibration interval
0x23 INTEGRATION_ TIME 8 R/W 0x0F Integration time
0x25 CTRL 8 R/W 0x00 Control
0x26 INT_MASK 8 R/W 0x08 Interrupt mask
0x27 INT_CLR 8 R/W 0x00 Interrupt clear
0x28 FILTER_PERIOD 8 R/W 0x00 Filter period
0x29 FILTER_THRESHOLD 8 R/W 0x00 Filter threshold
0x2A REF_DLY 8 R/W 0x00 Reference delay
0x30 -
0x32 TVR [0-2] 8 R/W 0x08 Touch variance setting
0x40 EVR 8 R/W 0x04 Environmental variance
STMPE321 Register map and function description
Doc ID 15791 Rev 3 13/40
0x50-0x52 STRENGTH_THRES
[0-2] 8 R/W 0x01 Setting of strength threshold for each
channel
0x60 -
0x62 STRENGTH [0-2] 8 R 0x00 Strength
0x70 -
0x72 CAL_IMPEDANCE [0-2] 8 R 0x00 Calibrated impedance
0x80 -
0x82 IMPEDANCE [0-2] 8 R 0x00 Impedance
0x92 INT_PENDING 8 R/W 0x00 Status of GINT interrupt sources
Table 5. Register summary map table (continued)
Address Register name Bit Type Reset value Function
System and identification registers STMPE321
14/40 Doc ID 15791 Rev 3
5 System and identification registers
CHIP_ID_x Device identification
Address: 0x00, 0x01
Type: R
Reset: 0x03, 0x21
Description: 16(8+8)-bit device identification
Table 6. System and identification registers map
Address Register name Bit Type Reset Function
0x00 CHIP_ID_0 8 R 0x03 Device
identification
0x01 CHIP_ID_1 8 R 0x21 Device
identification
0x02 ID_VER 8 R 0x03 Revision number
0x03 SYS_CFG_1 8 R/W 0x00 System
configuration 1
0x04 SYS_CFG_2 8 R/W 0xEF System
configuration 2
STMPE321 System and identification registers
Doc ID 15791 Rev 3 15/40
ID_VER Revision number
Address: 0x02
Type: R
Reset: 0x03
Description: 8-bit revision number
SYS_CFG_1 System configuration 1
Address: 0x03
Type: R/W
Reset: 0x00
Description: The reset control register enables the reset of the device
76543 2 1 0
RESERVED SLEEP WARM_RESET SOFT_RESET HIBERNATE
[7:4] RESERVED
[3] SLEEP:
Write ‘1’ to enable sleep mode. Hardware resets this bit to ‘0’ after it successfully enters sleep
mode.
[2] WARM_RESET:
Write ‘1’ to initiate a warm reset. Register content remains, state machine reset.
[1] SOFT_RESET:
Write ‘1’ to initiate a soft reset. All registers content and state machines reset.
[0] HIBERNATE: Force the device into hibernation mode.
Write ‘1’ to enter hibernate mode. Hardware resets this bit to ‘0’ after it successfully enters
hibernate mode.
System and identification registers STMPE321
16/40 Doc ID 15791 Rev 3
SYS_CFG_2 System configuration 2
Address: 0x04
Type: R/W
Reset: 0xEF
Description: This register enables the switching off of the clock supply
76543 2 1 0
SENSOR
CLOCK 2
SENSOR
CLOCK 1
SENSOR
CLOCK 0 RESERVED GPIO CLOCK
DISABLE
FIFO CLOCK
DISABLE
TOUCH CLOCK
DISABLE
[7:5] SENSOR CLOCK: See description in Table 7.
[4] RESERVED
[3] RESERVED
[2] GPIO CLOCK DISABLE:
Write ‘1’ to disable the clock to GPIO unit.
[1] FIFO CLOCK DISABLE:
Write ‘1’ to disable the clock to FIFO unit. This must be set to ‘0’ if touch interrupt is required.
[0] TOUCH CLOCK DISABLE:
Write ‘1’ to disable the clock to TOUCH unit.
Table 7. Sensor clock setting
Mode Divider Sensor clock
[2:0] Active Calibration
Operational
(6.5 MHz)
1 000 12.8 kHz 100 kHz
2 001 6.4 kHz 50 kHz
4 010 3.2 kHz 25 kHz
8 011 1.6 kHz 12.5 kHz
16 1xx 800 Hz 6.25 kHz
Autosleep
(200 kHz)
1 000 400 Hz 3.2 kHz
2 001 200 Hz 1.6 kHz
4 010 100 Hz 800 Hz
8 011 50 Hz 400 Hz
16 1xx 25 Hz 200 Hz
STMPE321 Interrupt controller module
Doc ID 15791 Rev 3 17/40
6 Interrupt controller module
Figure 7. Interrupt controller module block diagram
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Interrupt
enable
Interrupt
status
GPIO
interrupt
status
GPIO
interrupt
enable
AND
AND
INT
INT
pending
INT MASK
Interrupt controller module STMPE321
18/40 Doc ID 15791 Rev 3
INT_CTRL Interrupt control register
Address: 0x08
Type: R/W
Reset: 0x01
Description: This register is used to enable control of the polarity, edge/level and enabling of the
interrupt system device.
76543210
RESERVED POLARITY TYPE INT_EN
[7:3] RESERVED
[2] POLARITY:
'0' for active low
'1' for active high
For active low operation, the INT pin should be externally pulled high. The INT pin is pulled to
GND when there is a pending interrupt.
For active high operation, the INT pin should be externally pulled to GND. In this mode, the INT
pin is pulled to VCC by the device when there is a pending interrupt.
[1] TYPE:
'0' for level trigger
'1' for edge trigger (pulse width is 200 nS)
[0] INT_EN:
'0' to disable all interrupts
'1' to enable all interrupts
STMPE321 Interrupt controller module
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INT_EN Interrupt enable register
Address: 0x09
Type: R/W
Reset: 0x01
Description: This register is used to enable the interruption from a system related interrupt source
to the host. Writing ‘1’ in this register enables the corresponding interrupt event to
generate interrupt signal at the INT pin. Note that even if the interrupt is not enabled,
an interrupt event is still reflected in the interrupt status register.
76543 2 1 0
GPIO RESERVED GEN FIFO POR
[7] GPIO:
One or more level transition in enabled GPIOs
[6:3] RESERVED
Must be set to ‘0’ at all times.
[2] GEN:
System INT (A2I, I2A, EOC)
[1] FIFO:
Data available in FIFO. This interrupt can be cleared only if FIFO is empty.
[0] POR:
Power-on reset
Interrupt controller module STMPE321
20/40 Doc ID 15791 Rev 3
INT_STA Interrupt status register
Address: 0x0A
Type: R/W
Reset: 0x09
Description: This register is used to enable the interruption from a system related interrupt source
to the host. Regardless of whether or not the IESYSIOR bits are enabled, the
ISSYSIOR bits are still updated. Writing ‘1’ clears a bit in this register. Writing ‘0’ has
no effect.
76543 2 1 0
GPIO RESERVED GEN FIFO POR
[7] GPIO:
One or more level transition in enabled GPIOs
[6:3] RESERVED:
Some of these bits might be set to '1' by hardware during normal operation. The content of
these bit is for internal operation and are not required for normal use of device.
[2] GEN:
System INT (A2I, IA2, EOC)
[1] FIFO:
Data available in FIFO
[0] POR:
Power-on reset
STMPE321 Interrupt controller module
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GPIO_INT_EN GPIO interrupt enable registerI
Address: 0x0B, 0x0C
Type: R/W
Reset: 0x00
Description: The GPIO interrupt enable register is used to enable the interruption from a particular
GPIO interrupt source to the host. The IEg[2:0] bits and the interrupt enable mask bits
correspond to the GPIO[2:0] pins.
GPIO_INT_STA GPIO interrupt status register
Address: 0x0D, 0x0E
Type: R/W
Reset: 0x00
Description: The GPIO interrupt status register LSB monitors the status of the interruption from a
particular GPIO pin interrupt source to the host. Regardless of whether or not the
IEGPIOR bits are enabled, the INT_STA_GPIO_LSB bits are still updated. The
ISG[2:0] bits are the interrupt status bits correspond to the GPIO[2:0] pins.
76543 2 1 0
RESERVED IEG
[7:3] RESERVED
[2:0] IEG[2:0]
Interrupt enable GPIO mask (where x = 2 to 0)
Writing a ‘1’ to the IE[x] bit enables the interruption to the host.
76543 2 1 0
ISG
[7:0] ISG[x]:
Interrupt status GPIO (where x = 2 to 0)
Read:
Interrupt status of the GPIO[x]. Writing ‘1’ clears a bit. Writing ‘0’ has no effect.
GPIO controller STMPE321
22/40 Doc ID 15791 Rev 3
7 GPIO controller
A total of 3 GPIOs are available in the STMPE321. The GPIO controller contains the
registers that allow the host system to configure each of the pins into either a GPIO or Touch
input. Unused GPIOs should be configured as outputs to minimize power consumption.
A group of registers is used to control the exact function of each of the 3 GPIOs. The
registers and their respective addresses are listed in Table 8.
All GPIO registers are named GPxx, where:
Xxx represents the functional group
For LSB registers:
For MSB registers:
Table 8. GPIO controller registers summary map
Address Register name Description Auto-increment
0x10 GPIO_MR_LSB GPIO monitor pin state
register Ye s
0x11 GPIO_MR_MSB
0x12 GPIO_SET_LSB GPIO set pin state
register Ye s
0x13 GPIO_SET_MSB
0x14 GPIO_DIR_LSB GPIO set pin direction
register Ye s
0x15 GPIO_DIR_MSB
0x16 GPIO_FUNCT_LSB GPIO function register Yes
0x17 GPIO_FUNCT_MSB
76543 2 1 0
RESERVED IO-2 IO-1 IO-0
76543 2 1 0
RESERVED
STMPE321 GPIO controller
Doc ID 15791 Rev 3 23/40
The function of each bit is shown inTa bl e 9 :
Table 9. GPIO control bits function
Register name Function
GPIO monitor pin state Reading this bit yields the current state of the bit. Writing has no
effect.
GPIO set pin state Writing '1' to this bit causes the corresponding GPIO to go to '1' state
Writing '0' to this bit causes the corresponding GPIO to go to '0' state
GPIO set pin direction '0' sets the corresponding GPIO to input state, and '1' sets it to output
state. All bits are '0' on reset.
GPIO function '1' sets the corresponding GPIO to function as GPIO, and '0' sets it to
touchkey mode.
Capacitive touch module registers STMPE321
24/40 Doc ID 15791 Rev 3
8 Capacitive touch module registers
TOUCH_FIFO Touch FIFO
Address: 0x19, 0x18
Type: R
Reset: 0x00
Description: TOUCH_FIFO is the access port for the internal 4-level FIFO used for buffering the
touch events. While it is possible to access each byte in the data structure directly, it is
recommended that the FIFO is accessed only via the 0x18 address.
The FIFO must be accessed in multiples of 2 bytes (LSB, MSB). For the STMPE321,
MSB is reserved and LSB contains a snapshot of the recent touch event.
Where Tn is touch status of touch sensing channel n.
Table 10. TOUCH_FIFO summary table
Address Function
0x18 FIFO-0, LSB
0x19 FIFO-0, MSB
0x1A FIFO-1, LSB
0x1B FIFO-1, MSB
0x1C FIFO-2, LSB
0x1D FIFO-2, MSB
0x1E FIFO-3, LSB
0x1F FIFO-3, MSB
76543 2 1 0
T7 T6 T5 T4 T3 T2 T1 T0
STMPE321 Capacitive touch module registers
Doc ID 15791 Rev 3 25/40
FEATURE_SELECT Feature select
Address: 0x20
Type: R/W
Reset: 0x04
Description: Controls AFS (advanced filtering system and second level filtering feature)
ETC_WAIT Wait time setting
Address: 0x21
Type: R/W
Reset: 0x27
Description: Sets the wait time between the calibration and the last button touch
76543 2 1 0
RESERVED AFS[1:0] Filter EN
[7:3] RESERVED
[2:1] AFS[1:0]:
“00’: reserved
“01’ AFS mode 1 (only 1 strongest key)
‘10’: AFS mode 2 (all keys that are above threshold)
‘11’: AFS mode 3 (the 2 strongest keys)
[0] Filter EN:
Write '1' to enable filter
76543 2 1 0
ETC_WAIT[7:0]
[7:0] ETC_WAIT[7:0]:
ETC wait time = ETC_Wait[7:0] *64 + sensor clock period
A "non-touch" condition must persist for this wait time, before an ETC operation is carried out
Range: 5 mS - 20 s
Capacitive touch module registers STMPE321
26/40 Doc ID 15791 Rev 3
CAL_INTERVAL Calibration interval
Address: 0x22
Type: R/W
Reset: 0x30
Description: Calibration interval
INTEGRATION TIME Integration time
Address: 0x23
Type: R/W
Reset: 0x0F
Description: Integration time
76543 2 1 0
CAL_INTERVAL
[7:0] CALIBRATION INTERVAL:
Interval between calibration = calibration interval [7:0] * sensor clock period * 50
Range: 4 ms - 16 s
76543 2 1 0
INTEGRATION_TIME[7:0]
[7:0] Integration time in AFS mode
Total period of integration = sensor clock period * integration time [7:0]
78 µs - 320 ms
STMPE321 Capacitive touch module registers
Doc ID 15791 Rev 3 27/40
CTRL Control
Address: 0x25
Type: R/W
Reset: 0x00
Description: Control
76543 2 1 0
RESERVED F2A HDC_U HDC_C HOLD
[7:4] RESERVED
[3] F2A:
Write '1' to force device to remain in ACTIVE state at all times
[2] HDC_U:
Write '1' to perform unconditional host driven calibration
Cleared to '0' when calibration is completed
Only applicable HOLD is '1'
[1] HDC_C:
Write '1' to perform conditional host driven calibration
Calibration is performed if and only if no touch is detected
Cleared to '0' when calibration is completed
Only applicable HOLD is '1'
[0] HOLD:
'0' to enable ETC
'1' to disable ETC
Capacitive touch module registers STMPE321
28/40 Doc ID 15791 Rev 3
INT_MASK Interrupt mask
Address: 0x26
Type: R/W
Reset: 0x08
Description: Writing '1' to this register disables the corresponding interrupt source.
INT_CLR Interrupt clear
Address: 0x27
Type: R/W
Reset: 0x00
Description: Writing '1' to this register clears the corresponding interrupt source in INT_PENDING
register.
76543 2 1 0
RESERVED EOC RESERVED
[7:4] RESERVED
[3] EOC:
End of calibration
This interrupt occurs on both automatic and forced calibration
[2:0] RESERVED
76543 2 1 0
RESERVED EOC RESERVED
[7:4] RESERVED
[3] EOC:
End of calibration
This interrupt occurs on both automatic and forced calibration
[2:0] RESERVED
STMPE321 Capacitive touch module registers
Doc ID 15791 Rev 3 29/40
FILTER_PERIOD Filter period
Address: 0x28
Type: R/W
Reset: 0x00
Description: Filter period.
FILTER_THRESHOLD Filter threshold
Address: 0x29
Type: R/W
Reset: 0x00
Description: Filter threshold.
REFERENCE_DELAY Reference delay
Address: 0x2A
Type: R/W
Reset: 0x00
Description: Shifting of capacitive sensor dynamic range. The capacitance value set into this
register is in effect, equivalent to capacitor connected to the A_Ref pin.
76543 2 1 0
FILTER_COUNT
[7:0] FILTER_COUNT:
Additional filter to stabilize touch output in AFS mode.
AFS touch output is monitored for Filter Count [7:0] times every integration time. For each time
a "touch status" is detected, an internal "Filter Counter" is incremented once. This counter
value is then compared with Filter Threshold (register 0x29).
76543 2 1 0
FILTER_THRESHOLD
[7:0] FILTER_THRESHOLD:
An internal "Filter Counter" is compared with Filter Threshold [7:0] to determine if a valid touch
has occurred.
76543 2 1 0
RESERVED REFERENCE_DELAY
[7] RESERVED
[6:0] REFERENCE_DELAY:
Valid range = 0-127
Each step represents capacitance value of 0.04 pF
Warm reset is required after this value is updated
Capacitive touch module registers STMPE321
30/40 Doc ID 15791 Rev 3
TVR Touch variance setting
Address: 0x30 - 0x32
Type: R/W
Reset: 0x08
Description: Touch variance setting
EVR Environmental variance
Address: 0x40
Type: R/W
Reset: 0x04
Description: Environmental variance setting.
STRENGTH_THRESHOLD Strength threshold
Address: 0x50 - 0x52
Type: R/W
Reset: 0x01
Description: Strength threshold.
76543 2 1 0
RESERVED TVR
[7] RESERVED
[6:0] TVR:
Setting TVR between 0-99
A high TVR value decreases sensitivity of the sensor, but increases its tolerance to ambient
noise
A small TVR value increases the sensitivity
76543 2 1 0
RESERVED TVR
[7] RESERVED
[6] EVR:
EVR is used to detect "Non-Touch" condition
76543 2 1 0
STRENGTH_THRESHOLD
[7:0] STRENGTH_THRESHOLD:
Setting threshold to be used in AFS mode to determine valid touch
STMPE321 Capacitive touch module registers
Doc ID 15791 Rev 3 31/40
STRENGTH Strength
Address: 0x60 - 0x62
Type: R
Reset: 0x00
Description: The number of times a sensed capacitance exceeds the calibrated reference
impedance
76543210
STRENGTH
[7:0] STRENGTH:
Read-only field
Counts the number of times a sensed impedance exceeds calibrated reference impedance
and integration time. Maximum strength equals Integration Time [7:0]
Capacitive touch module registers STMPE321
32/40 Doc ID 15791 Rev 3
CALIBRATED_IMPEDANCE Calibrated impedance
Address: 0x70 - 0x72
Type: R
Reset: 0x00
Description: Calibrated impedance is a reference value maintained by the device.
IMPEDANCE Impedance
Address: 0x80 - 0x82
Type: R
Reset: 0x00
Description: Impedance is the instantaneous impedance value seen at the input pin of each
capacitive sensing pin.
TINT_PENDING Interrupt pending
Address: 0x92
Type: R
Reset: 0x00
Description: Reflects the status of each interrupt source.
76543210
CAL_IMPEDANCE
[7:0] CALIBRATED IMPEDANCE:
Calibrated reference impedance
76543210
IMPEDANCE
[7:0] IMPEDANCE:
Currently sensed impedance. This impedance reading decreases with the increase of the
capacitance at the sensing channel.
When this register reads 0x7F, reference capacitance should be reduced.
When this register reads 0x00, reference capacitance should be increased.
76543210
RESERVED EOC RESERVED
[7:4] RESERVED
[3] EOC:
End of calibration
[2:0] RESERVED
STMPE321 Maximum ratings
Doc ID 15791 Rev 3 33/40
9 Maximum ratings
Stressing the device above the rating listed in the “absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only, and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 11. Absolute maximum ratings
Symbol Parameter
Value
Unit
Min Typ Max
VCC Power supply −−
2.5 V
VESD ESD protection on each GPIO/touch pin −−
8kV
Electrical specifications STMPE321
34/40 Doc ID 15791 Rev 3
10 Electrical specifications
10.1 Capacitive sensing characteristics
Table 12. DC electrical characteristics (-40 - 85 °C unless otherwise stated)
Symbol Parameter Test condition
Value
Unit
Min Typ Max
VCC Core supply voltage 1.65 - 1.95 V
Ihibernate HIBERNATE current No touch sensing
capability -1.83.0µA
Isleep SLEEP current Touch sensing active,
no touch -2743µA
Iactive ACTIVE current 100% touch activity - 280 470 µA
VIL Input voltage low state VCC=1.8 V -0.3V - 0.2VCC V
VIH Input voltage high state VCC=1.8 V 0.8Vcc - VCC+0.3V V
VOL Output voltage low state VCC=1.8 V,
IOUT=4mA -0.3V - 0.25VCC V
VOH
Output voltage high
state
VCC=1.8OUTV,
IOUT =4mA 0.75Vcc - VCC+0.3V V
VOL
(I2C) Output voltage low state IOL=4 mA -0.3V - 0.25VCC V
Ileakage
Input leakage (GPIO) GPIO as input,
VIN = 2.0 V --0.5µA
Input leakage
(SCL, SDA, RST) VIN = VCC = 1.95 V - - 0.5 µA
Table 13. Capacitive sensing characteristics
Symbol Parameter Test condition
Value
Unit
Min Typ Max
Res
Capacitive
measurement
resolution
Aref = not connected - 40 - fF
DR Dynamic range Aref = not connected - 5.1 - pF
L Linearity of sensor
Aref = not connected
Maximum deviation
calculated from full scale
capacitance
measurement data
-10 -%
STMPE321 Package mechanical data
Doc ID 15791 Rev 3 35/40
11 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 8. Package outline for QFN12 (2.2 x 1.5 x 0.5 mm) - 0.40 mm pitch
1. Drawing not to scale.
2. Dimensions are in millimeters.
8118749_QFN12
Package mechanical data STMPE321
36/40 Doc ID 15791 Rev 3
Figure 9. Footprint recommendations for QFN12 (2.2 x 1.5 x 0.5 mm) - 0.40 mm
pitch
1. Drawing not to scale.
2. Dimensions are in millimeters.
Table 14. Mechanical data for QFN12 (2.2 x 1.5 x 0.5 mm) - 0.40 mm pitch
Symbol
Millimeters
Min Typ Max
A 0.50 −0.60
A1 0 −−
b 0.15 −0.25
D −1.50 −
E −2.20 −
e −0.40 −
L 0.35 −0.45
STMPE321 Package mechanical data
Doc ID 15791 Rev 3 37/40
Figure 10. Carrier tape for QFN12 (2.2 x 1.5 x 0.5 mm) - 0.40 mm pitch
785978-J
Package mechanical data STMPE321
38/40 Doc ID 15791 Rev 3
Figure 11. Reel information for QFN12 (2.2 x 1.5 x 0.5 mm) - 0.40 mm pitch
1. Drawing not to scale.
2. Dimensions are in millimeters
7875978
STMPE321 Revision history
Doc ID 15791 Rev 3 39/40
12 Revision history
Table 15. Document revision history
Date Revision Changes
19-Jun-2009 1 Initial release.
29-Jul-2009 2
Deleted “internal regulator” from the Features section.
Modified: Figure 1, Chapter 2, Figure 4. Chapter 4 and
Chapter 5, Chapter 1.3 and Chapter 7.
12-Aug-2009 3 Modified: Figure 4.
STMPE321
40/40 Doc ID 15791 Rev 3
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