U62H1708SA55 - ZMD AG - Product.Network

1 November 01, 2001

U62H1708

Preliminary

F131072 x 8 bit static CMOS RAM

F35 and 55 ns Access Time

FCommon data inputs and

data outputs

FThree-state outputs

FTyp. operating supply current

35 ns: 45mA

55 ns: 30mA

FStandby current <100µA at 125°C

FTTL/CMOS-compatible

FPower supply voltage 5 V

FOperating temperature range

-40 °C to 85 °C

-40 °C to 125 °C

FCECC 90000 Qua lity Standard

FESD protection > 2000 V

(MIL STD 883C M3015.7)

FLatch-up im mun ity >100 mA

FPackage: SOP32 (300/330 mil)

The U62H1708 is a static RAM

manufactured using a CMOS pro-

cess technology with the following

operating modes:

- Read - Standby

- Write - Data Retention

The memory array is based on a

6-Transistor cell.

The circuit is activated by the rising

edge of E2 (at E1 = L), or the falling

edge of E1 (at E2 = H). The

address and control inputs open

simultaneously. According to the

information of W and G, the data

inputs, or outputs, are active.

During the act ive state (E1 = L and

E2 = H) each address change

leads to a new Read or Write cycl e.

In a Read cycle, the data outputs

are activated by the falling edge of

G, afterwards the data wo rd will be

available at the outputs DQ0-DQ7.

After the address chan ge, the data

outputs go High-Z until the new

information is available. The data

outputs have no preferred state. If

the memory is driven by CMOS

levels in the active state, and if

there is no change of the address,

data input and cont rol signals W or

G, the operating current (IO = 0 mA)

drops to the value of the operating

current in the Standby mode. The

Read cycle is finished by th e falling

edge of E2 or W, or by the rising

edge of E1, respectively.

Data retention is guaranteed down

to 2 V. With the exception of E1

and E2, all inputs consist of NOR

gates, so that no pull-up/pull-down

resistors are requ ired.

Automotive Fast 128K x 8 SRAM

Pin Configuration

Top View

Sign al Name Signal Descript ion

A0 - A16 Address Inputs

DQ0 - DQ7 Data In/Out

E1 Chip Enable 1

E2 Chip Enable 2

GOutput Enable

WWrite Enable

VCC Power Supply Voltage

VSS Ground

n.c. not connected

Pin Descript ion

n.c. VCC32

2A16 A1531

4A12 W

5A7 A1328

3A14 E230

6A6 A827

7A5 A926

8A4 A1125

12A0 DQ721

9A3 G

A2 A1023

11A1 E1

13DQ0 DQ620

14DQ1 DQ519

SOP

DQ4

DQ3

DQ2

VSS

DescriptionFeatures

2 November 01, 200 1

U62H1708 Preliminary

*H or L

Oper ating Mode E1 E2 W GDQ0 - DQ7

Standby /not selected *L** High-Z

H*** High-Z

Internal Read L H H H High-Z

Read L H H L Data Outputs Low-Z

Wri te L H L * Data Inputs High-Z

Truth Table

Block Diagra m

Maximum Ratings Symbol Min. Max. Unit

Power Supply Voltage VCC -0.5 7 V

Input Voltage VI-0.5 VCC + 0.5 V

Outpu t Vol tage VO-0.5 VCC + 0.5 V

Power Dissipa tion PD-1W

Operating Temperature K-Type

A-Type Ta-40

-40 85

125 °C

Storage Temperature Tstg -65 150 °C

Outpu t Short-Circuit Current

at VCC = 5 V and VO = 0 V** | I OS |200mA

Characteristics

**Not more than 1 ou tput should be shorted at the same time. Duration of the short circuit should not exceed 30 s.

All voltages are referenced to VSS = 0 V (ground).

All ch arac teristics are v alid in the power su pply voltage range and in the operat ing temperature range specified.

Dynam ic measurements are based on a rise and fall tim e of ≤ 5 ns, measured between 10 % and 90 % of VI, as well as

input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and out put signals is 1.5 V,

with the ex ception of the tdis-times and ten-times, in which cases transiti on is measure d ±200 mV from steady-state vol tag e.

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

VCC VSS W GE1

Row Address

Inputs

Column Address

Inputs

Address

Change

Detector

Column Decoder Row Decoder

Sense Amplifier/

Write Control Logic

Common Data I/O

Memory Cell

Array

1024 Rows x

128 x 8 Columns

A10

A11

A12

A13

A14

A15

A16

Clock

Generator

3 November 01, 2001

U62H1708

Preliminary

Recommended

Operating Conditions Symbol Conditions Min. Max. Unit

Power Supply Vol tage VCC 4.5 5.5 V

Input Low V ol tage*VIL -0.3 0.8 V

Input High Voltage VIH 2.2 VCC + 0.3 V

Electrical Characteristics Symbol Conditions Min. Max. Unit

Supply Current - Operating Mode

Supply Current - S tandby Mode

(CMOS lev e l)

Supply Current - S tandby Mode

(TTL level)

ICC(OP)

ICC(SB)

ICC(SB)1

VCC

VIL

VIH

tcW

VCC

VE1= VE2

VCC

VE1= VE2

K-Type

A-Type

= 5.5 V

= 0.8 V

= 2.2 V

= 35 ns

= 55 ns

= 70 ns

= 5.5 V

= VCC - 0.2 V

= 5.5 V

= 2.2 V

100

µA

Out put High Voltage

Out put Low Vo ltage

VOH

VOL

VCC

IOH

VCC

IOL

= 4.5 V

=-4.0 mA

= 4.5 V

= 8.0 mA

2.4

0.4

Input High Leakage Current

Input Low Leakage Current

IIH

IIL

VCC

VIH

VCC

VIL

= 5.5 V

= 0 V -2

2µA

µA

Out put High Current

Out put Low Current

IOH

IOL

VCC

VOH

VCC

VOL

= 4.5 V

=2.4 V

= 4.5 V

= 0.4 V 8

-4 mA

Out put Leakag e Current

High at Three-State Outputs

Low at Three-State Outputs

IOHZ

IOLZ

VCC

VOH

VCC

VOL

= 5.5 V

=0 V -2

2µA

µA

* -2 V at Puls e Wid th 10 ns

4 November 01, 200 1

U62H1708 Preliminary

Switching Characteristics

Read Cycle

Symbol 35 55 Unit

Alt. IEC Min. Max. Min. Max.

Read Cycle T ime tRC tcR 35 55 ns

Addre ss Access Time to Data Vali d tAA ta(A) 35 55 ns

Chip Enable Access Time to Data Valid tACE ta(E) 35 55 ns

G LO W to D a ta Vali d tOE ta(G) 15 25 ns

E1 HIGH or E2 LOW to O utput in High-Z tHZCE tdis(E) 12 15 ns

G HIGH to Output in High-Z tHZOE tdis(G) 12 15 ns

E1 LOW or E2 HIGH to Outp ut in Low-Z tLZCE ten(E) 33ns

G LOW to Output in Low-Z tLZOE ten(G) 00ns

Outpu t Hold Time from Address Change tOH tv(A) 33ns

E1 LOW or E2 HIGH to Power-Up Time tPU 00ns

E1 HI GH or E2 LOW to Power-Down Time tPD 35 55 ns

Switching Characteristics

Write Cycle

Symbol 35 55 Unit

Alt. IEC Min. Max. Min. Max.

Writ e Cycle T ime tWC tcW 35 55 ns

Write Pulse Width tWP tw(W) 20 35 ns

Write Setup Time tWP tsu(W) 20 35 ns

Address Setup Ti me tAS tsu(A) 00ns

Address Val id to End of Write tAW tsu(A-WH) 20 40 ns

Chip Enab le Setup Time tCW tsu(E) 25 40 ns

Pulse Width Chip Enable to End of Write tCW tw(E) 25 40 ns

Data Setup Time tDS tsu(D) 15 25 ns

Data Hold Time tDH th(D) 00ns

Address H old from End of Write tAH th(A) 00ns

W LOW to Output in High-Z tHZWE tdis(W) 15 20 ns

G HIG H to Ou tp ut i n H i gh -Z tHZOE tdis(G) 12 15 ns

W HIGH to Output in Low-Z tLZWE ten(W) 00ns

G LOW to Output in Low-Z tLZOE ten(G) 00ns

5 November 01, 2001

U62H1708

Preliminary

Data Retention

Characteristics Symbol Conditions Min. Typ. Max. Unit

Alt. IEC

Data Retention Supply Vol tage VCC(DR) 25.5V

Data Retention Supply Current ICC(DR) VCC(DR) = 3 V

VE1 =VE2 = V CC(DR) - 0.2 V 60 µA

Data Retention Setup Time tCDR tsu(DR) See Data Retention

Waveforms (below) 0ns

Operating Rec overy Time tRtrec tcR ns

Data Retention Mode E1 - cont ro l led

Data Retention

4.5 V

tsu(DR) trec

VCC

VCC(DR) ≥ 2 V

0 V

2.2 V

Data Retentio n Mode E2 - con t r olled

VE2(DR) ≥ VCC(DR) - 0.2 V or VE2(DR) ≤ 0.2 V

VCC(DR) - 0.2 V ≤ VE1(DR) ≤ VCC(DR) + 0.3 V

0.8 V

4.5 V

0 V

VCC

VE1(DR) ≥ VCC(DR) - 0.2 V or VE1(DR) ≤ 0.2 V

VE2(DR) ≤ 0.2 V

trec

tDR

VCC(DR) ≥ 2 V

Data Retention E2

Data Retention Mode

6 November 01, 200 1

U62H1708 Preliminary

Capacitance Conditions Symbol Min. Max. Unit

Input Capacit ance VCC

= 5.0 V

= VSS

= 1 MHz

= 25 °C

CI7pF

Output Capacitance Co7pF

IC Code Numbers

U62H1708 SA35

Type

Package

S = SOP32 300 mil

S1 = SOP32 330 m il

Oper ating Temp eratu re Rang e

K = -40 to 85 °C

A = -40 to 125 °C

Access Time

35 = 35 ns

55 = 55 ns

The date of manufacture is given by the last 4 digits of the mark, the first 2 digits indicating the year,

and the last 2 digits the calendar week.

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

Test Configuration for Functional Check

VIH

VIL

VSS

VCC

5 V

481

255

1) In measurement of tdis(E),tdis(W), ten(E), ten(W), ten(G) the capacitance is 5 pF.

Input level according to the

relev ant test measurement

Simultaneous measure-

ment of all 8 output pins

A10

A11

A12

A13

A14

A15

A16

All pins not under test must be connec t ed with ground by capacitors.

30 pF1

7 November 01, 2001

U62H1708

Preliminary

Previous Data Valid Output Data Valid

Address Valid

Read Cycle 1: Ai-con trolled (during Read Cycle : E1 = G = VIL, W = E2 = VIH)

Read Cycle 2: G-, E1, E2-con t rol led (durin g R ea d C ycl e : W = VIH)

ta(A)

tcR

tv(A)

DQi

Output

tcR

High-Z

Ad dr e s se s Val i d

DQi

Output

tdis(E)

tsu(A) ta(E)

tsu(A)

ten(E)

ten(G)

ta(G)

ta(E) tdis(E)

tdis(G)

Ou tp ut Data Vali d

tPD*

tPU*

ICC(OP)

ICC(SB)

* The same applies to E1

50 % 50 %

Write Cycl e1: W-controlled

th(D)

DQi

Output

tcW

tsu(E) th(A)

tw(W)

tsu(A)

tsu(E)

tsu(D)

tdis(W) ten(W)

Ad dr e s se s Valid

High-Z

Input Input Data Valid

8 November 01, 200 1

U62H1708 Preliminary

Write Cycle 2: E1-controlled

tsu(A)

th(D)

DQi

Input

DQi

Output

tcW

tw(E) th(A)

tsu(W)

tsu(E)

tsu(D)

tdis(W)

ten(E)

Addresses Valid

In p ut Data Valid

High-Z

Inp ut Data Valid

th(D)

tsu(W)

tw(E)

tsu(D)

tcW

Addresses Vali d

tsu(A)

tsu(E) th(A)

ten(E) tdis(W)

DQi

Input

DQi

Output

Write Cycle 3 (E2-controlled )

tdis(G)

The information describes the type of component and shall not be considered as assured characteristics.Terms of

delivery and rights to change design reserved.

L - to H-leve l

undefined H- to L-level

Zentrum Mikroelektronik Dresden AG

Grenzstra ße 28 • D-01109 Dresden • P. O. B. 80 01 34 • D-01101 Dresden • Germany

Phone: +49 351 8822 306 • Fax: +49 351 8822 337 • Email: sales@zmd.de • http://www.zmd.de

November 01, 2001

U62H1708

Preliminary

LIFE SUPPOR T POLICY

ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical

implant into the body, or ot her applications i nten ded to sup port or sustain life, or fo r any other ap plication in which

the failure of the ZMD product could create a situation where personal injury or death may occur.

Components used in life-support devices or syste ms must be expressly authorized by ZMD for such purpose.

LIMITED WARRANTY

The information in this document has been carefully checked and is believed to be reliable. However Zentrum

Mikroelektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said information

and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or relia nce upon it.

The information in this docum ent describes the type of com pon ent and s hal l not be considered as as sured c harac-

teristics.

ZMD does not guaran tee that the use of any information contained herein will not infringe upon the patent, trade-

mark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This

document does not in any way extent ZMD’s warrant y on any product beyond that set forth i n its st andard terms and

conditions of sale.

ZMD reserves terms of delivery and reserves the right to m ake cha nges in the products or s pecifications, or both,

presented in this publication at any time and without notice.