LT5518
1
5518f
■ High Input Impedance Version of the LT5528
■ Direct Conversion to 1.5GHz – 2.4GHz
■ High OIP3: 22.8dBm at 2GHz
■ Low Output Noise Floor at 20MHz Offset:
No RF: –158.2dBm/Hz
P
OUT = 4dBm: –152.5dBm/Hz
■ 4-Ch W-CDMA ACPR: –64dBc at 2.14GHz
■ Integrated LO Buffer and LO Quadrature Phase
Generator
■ 50Ω AC-Coupled Single-Ended LO and RF Ports
■ Low Carrier Leakage: –49dBm at 2GHz
■ High Image Rejection: 40dB at 2GHz
■ 16-Lead QFN 4mm × 4mm Package
■ Infrastructure Tx for DCS, PCS and UMTS Bands
■ Image Reject Up-Converters for DCS, PCS and UMTS
Bands
■ Low Noise Variable Phase-Shifter for 1.5GHz to
2.4GHz Local Oscillator Signals
1.5GHz–2.4GHz
High Linearity Direct
Quadrature Modulator
The LT®5518 is a direct I/Q modulator designed for high
performance wireless applications, including wireless
infrastructure. It allows direct modulation of an RF signal
using differential baseband I and Q signals. It supports PHS,
GSM, EDGE, TD-SCDMA, CDMA, CDMA2000, W-CDMA
and other systems. It may also be confi gured as an image
reject up-converting mixer, by applying 90° phase-shifted
signals to the I and Q inputs. The high impedance I/Q
baseband inputs consist of voltage-to-current converters
that in turn drive double-balanced mixers. The outputs of
these mixers are summed and applied to an on-chip RF
transformer, which converts the differential mixer signals
to a 50Ω single-ended output. The balanced I and Q
baseband input ports are intended for DC coupling from a
source with a common mode voltage level of about 2.1V.
The LO path consists of an LO buffer with single-ended
input, and precision quadrature generators that produce
the LO drive for the mixers. The supply voltage range is
4.5V to 5.25V.
1.5GHz to 2.4GHz Direct Conversion Transmitter Application
with LO Feedthrough and Image Calibration Loop
RF OUTPUT POWER PER CARRIER (dBm)
–34 –30 –26 –22 –18 –14 –10
ACPR, ALTCPR (dBc)
NOISE FLOOR AT 30MHz OFFSET (dBm/Hz)
–65
–60
–55
5518 TA01b
–70
–75
–85
–80
–145
–140
–135
–150
–155
–165
–160
4-CH ACPR
4-CH NOISE
1-CH NOISE
4-CH ALTCPR
1-CH ALTCPR
1-CH ACPR
DOWNLINK TEST MODEL 64 DPCH
90°
0°
LT5518
BASEBAND
GENERATOR
CAL
LO FEEDTHROUGH
CAL OUT
IMAGE CAL OUT
PA
VCO/SYNTHESIZER
RF = 1.5GHz
TO 2.4GHz
EN
2, 4, 6, 9, 10, 12, 15, 17
100nF
×2
5V
V-I
V-I
I-CHANNEL
Q-CHANNEL BALUN
14
16
1
7
5
8, 13
VCC
11
3
5518 TA01a
I-DAC
Q-DAC
ADC
W-CDMA ACPR, AltCPR and Noise vs RF Output
Power at 2140MHz for 1 and 4 Channels
APPLICATIO S
U
FEATURES DESCRIPTIO
U
TYPICAL APPLICATIO
U
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
LT5518
2
5518f
16
17
15 14 13
5 6 7 8
TOP VIEW
EXPOSED PAD (PIN 17) IS GND
MUST BE SOLDERED TO THE PCB
9
10
11
12
4
3
2
1EN
GND
LO
GND
GND
RF
GND
GND
BBMI
GND
BBPI
VCC
BBMQ
GND
BBPQ
VCC
Supply Voltage .........................................................5.5V
Common Mode Level of BBPI, BBMI and
BBPQ, BBMQ .......................................................2.5V
Operating Ambient Temperature
(Note 2) .............................................. –40°C to 85°C
Storage Temperature Range .................. –65°C to 125°C
Voltage on Any Pin
Not to Exceed ...................... –500mV to VCC + 500mV
ORDER PART
NUMBER
UF PART
MARKING
TJMAX = 125°C, θJA = 37°C/W
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges.
5518
LT5518EUF
(Note 1)
V
CC = 5V, EN = High, TA = 25°C, fLO = 2GHz, fRF = 2.002GHz, PLO = 0dBm.
BBPI, BBMI, BBPQ, BBMQ inputs 2.06VDC, Baseband Input Frequency = 2MHz, I and Q 90° shifted (upper sideband selection).
PRF, OUT = –10dBm, unless otherwise noted. (Note 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
RF Output (RF)
fRF RF Frequency Range –3dB Bandwidth 1.5 to 2.4 GHz
RF Frequency Range –1dB Bandwidth 1.7 to 2.2 GHz
S22, ON RF Output Return Loss EN = High (Note 6) –14 dB
S22, OFF RF Output Return Loss EN = Low (Note 6) –12 dB
NFloor RF Output Noise Floor No Input Signal (Note 8) –158.2 dBm/Hz
P
OUT = 4dBm (Note 9) –152.5 dBm/Hz
P
OUT = 4dBm (Note 10) –151.1 dBm/Hz
GP Conversion Power Gain POUT/PIN, I&Q 10.6 dB
GV Conversion Voltage Gain 20 • log(VOUT, 50Ω/VIN, DIFF, I or Q) –4 dB
POUT Absolute Output Power 1VP-P, DIFF CW Signal, I and Q 0 dBm
G3LO vs LO 3 • LO Conversion Gain Difference (Note 17) –28 dB
OP1dB Output 1dB Compression (Note 7) 8.5 dBm
OIP2 Output 2nd Order Intercept (Notes 13, 14) 49 dBm
OIP3 Output 3rd Order Intercept (Notes 13, 15) 22.8 dBm
IR Image Rejection (Note 16) –40 dBc
LOFT Carrier Leakage EN = High, PLO = 0dBm (Note 16) –49 dBm
(LO Feedthrough) EN = Low, PLO = 0dBm (Note 16) –58 dBm
LO Input (LO)
fLO LO Frequency Range 1.5 to 2.4 GHz
PLO LO Input Power –10 0 5 dBm
S11, ON LO Input Return Loss EN = High (Note 6) –18 dB
S11, OFF LO Input Return Loss EN = Low (Note 6) –5 dB
NFLO LO Input Referred Noise Figure (Note 5) at 2GHz 14 dB
GLO LO to RF Small Signal Gain (Note 5) at 2GHz 23.8 dB
IIP3LO LO Input Linearity (Note 5) at 2GHz –9 dBm
ELECTRICAL CHARACTERISTICS
ABSOLUTE AXI U RATI GS
W
WW
U
PACKAGE/ORDER I FOR ATIO
UUW
LT5518
3
5518f
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: Specifi cations over the –40°C to 85°C temperature range are
assured by design, characterization and correlation with statistical process
controls.
Note 3: Tests are performed as shown in the confi guration of Figure 8.
Note 4: On each of the four baseband inputs BBPI, BBMI, BBPQ and
BBMQ.
Note 5: V(BBPI) – V(BBMI) = 1VDC, V(BBPQ) – V(BBMQ) = 1VDC.
Note 6: Maximum value within –1dB bandwidth.
Note 7: An external coupling capacitor is used in the RF output line.
Note 8: At 20MHz offset from the LO signal frequency.
Note 9: At 20MHz offset from the CW signal frequency.
Note 10: At 5MHz offset from the CW signal frequency.
Note 11: RF power is within 10% of fi nal value.
Note 12: RF power is at least 30dB lower than in the ON state.
Note 13: Baseband is driven by 2MHz and 2.1MHz tones. Drive level is set
in such a way that the two resulting RF output tones are –10dBm each.
Note 14: IM2 measured at LO frequency + 4.1MHz.
Note 15: IM3 measured at LO frequency + 1.9MHz and LO frequency +
2.2MHz.
Note 16: Amplitude average of the characterization data set without image
or LO feedthrough nulling (unadjusted).
Note 17: The difference in conversion gain between the spurious signal at
f = 3 • LO – BB versus the conversion gain at the desired signal at f = LO +
BB for BB = 2MHz and LO = 2GHz.
Note 18: Common mode current range where the common mode (CM)
feedback loop biases the part properly. The common mode current is the
sum of the current fl owing into the BBPI (or BBPQ) pin and the current
fl owing into the BBMI (or BBMQ) pin.
V
CC = 5V, EN = High, TA = 25°C, fLO = 2GHz, fRF = 2.002GHz, PLO = 0dBm.
BBPI, BBMI, BBPQ, BBMQ inputs 2.06VDC, Baseband Input Frequency = 2MHz, I and Q 90° shifted (upper sideband selection).
PRF, OUT = –10dBm, unless otherwise noted. (Note 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Baseband Inputs (BBPI, BBMI, BBPQ, BBMQ)
BWBB Baseband Bandwidth –3dB Bandwidth 400 MHz
VCMBB DC Common Mode Voltage (Note 4) 2.06 V
RIN, DIFF Differential Input Resistance Between BBPI and BBMI (or BBPQ and BBMQ) 2.9 kΩ
RIN, CM Common Mode Input Resistance BBPX and BBMX Shorted Together 105 Ω
ICM, COMP Common Mode Compliance Current Range BBPX and BBMX Shorted Together (Note 18) –730 to 480 µA
PLO2BB Carrier Feedthrough on BB POUT = 0 (Note 4) –40 dBm
IP1dB Input 1dB Compression Point Differential Peak-to-Peak (Note 7) 2.7 VP-P, DIFF
ΔGI/Q I/Q Absolute Gain Imbalance 0.06 dB
ΔφI/Q I/Q Absolute Phase Imbalance 1 deg
Power Supply (VCC)
VCC Supply Voltage 4.5 5 5.25 V
ICC, ON Supply Current EN = High 128 145 mA
ICC, OFF Supply Current, Sleep Mode EN = 0V 0.05 50 µA
tON Turn-On Time EN = Low to High (Note 11) 0.2 µs
tOFF Turn-Off Time EN = High to Low (Note 12) 1.3 µs
Enable (EN), Low = Off, High = On
Enable Input High Voltage EN = High 1.0 V
Input High Current EN = 5V 240 µA
Sleep Input Low Voltage EN = Low 0.5 V
ELECTRICAL CHARACTERISTICS
LT5518
4
5518f
SUPPLY VOLTAGE (V)
4.5
SUPPLY CURRENT (mA)
120
130
5.5
5518 G01
110
100 5.0
140
LO FREQUENCY (GHz)
1.3
5
0
–5
–10
–15 2.52.3
5518 G02
1.7 1.91.5 2.1 2.7
LO FREQUENCY (GHz)
1.3 2.52.3
5518 G03
1.7 1.91.5 2.1 2.7
RF OUTPUT POWER (dBm)
5V, TA = –40°C
5V, TA = 25°C
5V, TA = 85°C
4.5V, TA = 25°C
5.5V, TA = 25°C
VOLTAGE GAIN (dB), OP1dB (dBm)
15
10
5
0
–5
–10
–15
4.5V
5.5V
5V
LO FREQUENCY (GHz)
1.3
VOLTAGE GAIN (dB), OP1dB (dBm)
15
10
5
0
–5
–10
–15 1.9 2.3
5518 G04
1.5 1.7 2.1 2.5 2.7
LO/NOISE FREQUENCY (GHz) LO/NOISE FREQUENCY (GHz)
1.3 1.9 2.3
5518 G05
1.5 1.7 2.1 2.5 2.7
GAIN
OP1dB
GAIN
OP1dB
4.5V
5.5V
5V
OIP3 (dBm)
26
24
22
20
18
16
14
12
10
8
6
–146
–148
–150
–152
–154
–156
–158
–160
–162
–164
–166
TA = –40°C
TA = 85°C
TA = 25°C
NOISE FLOOR
NOISE FLOOR (dBm/Hz)
OIP3
1.3 1.9 2.3
5518 G06
1.5 1.7 2.1 2.5 2.7
LO FREQUENCY (GHz)
1.3 1.9 2.3
5518 G07
1.5 1.7 2.1 2.5 2.7
OIP3 (dBm)
26
24
22
20
18
16
14
12
10
8
6
–146
–148
–150
–152
–154
–156
–158
–160
–162
–164
–166
NOISE FLOOR
NOISE FLOOR (dBm/Hz)
OIP3
–40
–45
–50
–55
–60
LO FT (dBm)
2 • LO FREQUENCY (GHz)
2.6
P(2 • LO) (dBm)
–25
–30
–35
–40
–45
–50
–55 3.8 4.6
5518 G08
3.0 3.4 4.2 5.0 5.4
5V, TA = –40°C
5V, TA = 25°C
5V, TA = 85°C
4.5V, TA = 25°C
5.5V, TA = 25°C
5V, TA = –40°C
5V, TA = 25°C
5V, TA = 85°C
4.5V, TA = 25°C
5.5V, TA = 25°C
3 • LO FREQUENCY (GHz)
3.9
P(3 • LO) (dBm)
7.5
5518 G09
5.1 6.3
–30
–35
–40
–45
–50
–55
–60
–65
–70
4.5 5.7 6.9 8.1
5V, TA = –40°C
5V, TA = 25°C
5V, TA = 85°C
4.5V, TA = 25°C
5.5V, TA = 25°C
4.5V
5.5V
5V
NO BASEBAND SIGNAL
fLO = 2.14GHz (FIXED) FOR NOISE
NO BASEBAND SIGNAL
fLO = 2.14GHz (FIXED) FOR NOISE
fBB, 1 = 2MHz
fBB, 2 = 2.1MHz
fBB, 1 = 2MHz
fBB, 2 = 2.1MHz
TA = 85°C
TA = 25°C
TA = –40°C
Output IP3 and Noise Floor vs LO
Frequency and Temperature
Output IP3 and Noise Floor vs LO
Frequency and Supply Voltage
LO Feedthrough to RF Output vs
LO Frequency
2 • LO Leakage to RF Output vs
2 • LO Frequency
3 • LO Leakage to RF Output vs
3 • LO Frequency
Supply Current vs Supply Voltage
RF Output Power vs LO Frequency
at 1VP-P Differential Baseband Drive
Voltage Gain and Output 1dB
Compression vs LO Frequency
and Temperature
Voltage Gain and Output 1dB
Compression vs LO Frequency
and Supply Voltage
VCC = 5V, EN = High, TA = 25°C, fLO = 2.14GHz,
PLO = 0dBm. BBPI, BBMI, BBPQ, BBMQ inputs 2.06VDC, Baseband Input Frequency fBB = 2MHz, I and Q 90° shifted without image or
LO feedthrough nulling. fRF = fBB + fLO (upper sideband selection). PRF, OUT = –10dBm (–10dBm/tone for 2-tone measurements), unless
otherwise noted. (Note 3)
TYPICAL PERFOR A CE CHARACTERISTICS
UW
LT5518
5
5518f
IMAGE REJECTION (dBc)
–25
–30
–35
–40
–45
–50
–55
5V, TA = –40°C
5V, TA = 25°C
5V, TA = 85°C
4.5V, TA = 25°C
5.5V, TA = 25°C
LO FREQUENCY (GHz)
1.3 2.52.3
5518 G10
ABSOLUTE I/Q GAIN IMBALANCE (dB)
02
0.1
0
1.7 1.91.5 2.1 2.7
5V, TA = –40°C
5V, TA = 25°C
5V, TA = 85°C
4.5V, TA = 25°C
5.5V, TA = 25°C
LO FREQUENCY (GHz)
1.3 2.52.3
5518 G11
1.7 1.91.5 2.1 2.7
ABSOLUTE I/Q PHASE IMBALANCE (DEG)
5
4
3
2
1
0
5V, TA = –40°C
5V, TA = 25°C
5V, TA = 85°C
4.5V, TA = 25°C
5.5V, TA = 25°C
LO FREQUENCY (GHz)
1.3 2.52.3
5518 G12
1.7 1.91.5 2.1 2.7
LO INPUT POWER (dBm)
–20
VOLTAGE GAIN (dB)
4
5518 G13
–12 –4
–2
–4
–6
–8
–10
–12
–14
–16
–18
–16 –8 0 8
LO INPUT POWER (dBm)
–20
OIP3 (dBm)
4
5518 G14
–12 –4
24
22
20
18
16
14
12
10
8
6
4–16 –8 0 8
5V, TA = –40°C
5V, TA = 25°C
5V, TA = 85°C
4.5V, TA = 25°C
5.5V, TA = 25°C
5V, TA = –40°C
5V, TA = 25°C
5V, TA = 85°C
4.5V, TA = 25°C
5.5V, TA = 25°C
RF HD3
HD2
5518 G15
TA = –40°C
TA = 85°C
TA = 25°C
HD2 = MAX POWER AT
fLO + 2 • fBB OR fLO – 2 • fBB
HD3 = MAX POWER AT
fLO + 3 • fBB OR fLO – 3 • fBB
I AND Q BASEBAND VOLTAGE (VP-P, DIFF)
0
HD2, HD3 (dBc)
RF CW OUTPUT POWER (dBm)
–10
–20
–30
–40
–50
–60
–70
10
0
–10
–20
–30
–40
–50
12
RF HD3
HD2
34
5518 G16
5
I AND Q BASEBAND VOLTAGE (VP-P, DIFF)
0
HD2, HD3 (dBc)
RF CW OUTPUT POWER (dBm)
–10
–20
–30
–40
–50
–60
–70
10
0
–10
–20
–30
–40
–50
12345
4.5V
5.5V
5V
I AND Q BASEBAND VOLTAGE (VP-P, DIFF)
0
LO FT (dBm), IR (dBc)
–25
–30
–35
–40
–45
–50
–55
LO FT (dBm), IR (dBc)
–25
–30
–35
–40
–45
–50
–55
12
LO FT
IR
34
5518 G17
5
TA = –40°C
TA = 85°C
TA = 25°C
I AND Q BASEBAND VOLTAGE (VP-P, DIFF)
012
LO FT
IR
34
5518 G18
5
HD2 = MAX POWER AT
fLO + 2 • fBB OR fLO – 2 • fBB
HD3 = MAX POWER AT
fLO + 3 • fBB OR fLO – 3 • fBB
4.5V
5.5V
5V
Image Rejection vs LO Frequency
Absolute I/Q Gain Imbalance
vs LO Frequency
Absolute I/Q Phase Imbalance
vs LO Frequency
Voltage Gain vs LO Power Output IP3 vs LO Power
RF CW Output Power, HD2 and HD3 vs
Baseband Voltage and Temperature
RF CW Output Power, HD2 and
HD3 vs Baseband Voltage and
Supply Voltage
LO Feedthrough to RF Output and
Image Rejection vs Baseband
Voltage and Temperature
LO Feedthrough to RF Output and
Image Rejection vs Baseband
Voltage and Supply Voltage
VCC = 5V, EN = High, TA = 25°C, fLO = 2.14GHz,
PLO = 0dBm. BBPI, BBMI, BBPQ, BBMQ inputs 2.06VDC, Baseband Input Frequency fBB = 2MHz, I and Q 90° shifted without image
or LO feedthrough nulling. fRF = fBB + fLO (upper sideband selection). PRF, OUT = –10dBm (–10dBm/tone for 2-tone measurements),
unless otherwise noted. (Note 3)
TYPICAL PERFOR A CE CHARACTERISTICS
UW
LT5518
6
5518f
Output IP2 vs LO Frequency
LO and RF Port Return Loss
vs RF Frequency
EN (Pin 1): Enable Input. When the enable pin voltage is
higher than 1V, the IC is turned on. When the input voltage
is less than 0.5V, the IC is turned off.
GND (Pins 2, 4, 6, 9, 10, 12, 15): Ground. Pins 6, 9, 15
and 17 (exposed pad) are connected to each other internally.
Pins 2 and 4 are connected to each other internally and
function as the ground return for the LO signal. Pins 10
and 12 are connected to each other internally and function
as the ground return for the on-chip RF balun. For best RF
performance, pins 2, 4, 6, 9, 10, 12, 15 and the Exposed
Pad (Pin 17) should be connected to the printed circuit
board ground plane.
LO (Pin 3): LO Input. The LO input is an AC-coupled single-
ended input with approximately 50Ω input impedance at
RF frequencies. Externally applied DC voltage should be
within the range –0.5V to VCC + 0.5V in order to avoid
turning on ESD protection diodes.
BBPQ, BBMQ (Pins 7, 5): Baseband Inputs for the Q-Chan-
nel, with 2.9kΩ Differential Input Impedance. Internally
biased at about 2.06V. Applied common mode voltage
must stay below 2.5V.
VCC (Pins 8, 13): Power Supply. Pins 8 and 13 are con-
nected to each other internally. It is recommended to use
0.1µF capacitors for decoupling to ground on each of
these pins.
RF (Pin 11): RF Output. The RF output is an AC-coupled
single-ended output with approximately 50Ω output im-
pedance at RF frequencies. Externally applied DC voltage
should be within the range –0.5V to VCC + 0.5V in order
to avoid turning on ESD protection diodes.
BBPI, BBMI (Pins 14, 16): Baseband Inputs for the I-Chan-
nel, with 2.9kΩ Differential Input Impedance. Internally
biased at about 2.06V. Applied common mode voltage
must stay below 2.5V.
Exposed Pad (Pin 17): Ground. This pin must be soldered
to the printed circuit board ground plane.
LO FREQUENCY (GHz)
1.3
OIP2 (dBm)
65
60
55
50
45
40
35 1.9 2.3
5518 G19
1.5 1.7 2.1 2.5 2.7
fBB,1 = 2MHz
fBB,2 = 2.1MHz
fIM2 = fBB,1+ fBB,2 + fLO
5V, TA = –40°C
5V, TA = 25°C
5V, TA = 85°C
4.5V, TA = 25°C
5.5V, TA = 25°C
RF FREQUENCY (GHz)
1.3
S11 (dB)
0
–10
–20
–30
–40
–50
1.9 2.3
5518 G20
1.5 1.7 2.1 2.5 2.7
LO PORT, EN = LOW
RF PORT, EN = HIGH,
PLO = 0dBm RF PORT,
EN = LOW
LO PORT,
EN = HIGH
RF PORT, EN =
HIGH, NO LO
VCC = 5V, EN = High, TA = 25°C, fLO = 2.14GHz,
PLO = 0dBm. BBPI, BBMI, BBPQ, BBMQ inputs 2.06VDC, Baseband Input Frequency fBB = 2MHz, I and Q 90° shifted without image
or LO feedthrough nulling. fRF = fBB + fLO (upper sideband selection). PRF, OUT = –10dBm (–10dBm/tone for 2-tone measurements),
unless otherwise noted. (Note 3)
TYPICAL PERFOR A CE CHARACTERISTICS
UW
PI FU CTIO S
UUU
LT5518
7
5518f
The LT5518 consists of I and Q input differential voltage-
to-current converters, I and Q up-conversion mixers, an
RF output balun, an LO quadrature phase generator and
LO buffers.
External I and Q baseband signals are applied to the dif-
ferential baseband input pins, BBPI, BBMI, and BBPQ,
BBMQ. These voltage signals are converted to currents and
translated to RF frequency by means of double-balanced
up-converting mixers. The mixer outputs are combined
Figure 1. Simplifi ed Circuit Schematic of the LT5518 (Only I-Half is Drawn)
in an RF output balun, which also transforms the output
impedance to 50Ω. The center frequency of the resulting
RF signal is equal to the LO signal frequency. The LO in-
put drives a phase shifter which splits the LO signal into
in-phase and quadrature LO signals. These LO signals
are then applied to on-chip buffers which drive the up-
conversion mixers. Both the LO input and RF output are
single-ended, 50Ω-matched and AC coupled.
90°
0°
LT5518
V-I
V-I
BALUN
VCC
RF
LO
5518 BD
11
EN
1
396
GND
42
5
7
16
14
8 13
BBPI
BBMI
BBPQ
BBMQ
1715
GND
1210
RF
VCC = 5V
BBPI
BBMI
C
GND
LOMI
LOPI
FROM
Q
5518 F01
BALUN
CM
VREF = 500mV
200Ω
200Ω
1.8pF
1.8pF 1.3k
1.3k
LT5518
BLOCK DIAGRA
W
APPLICATIO S I FOR ATIO
WUUU
LT5518
8
5518f
Baseband Interface
The baseband inputs (BBPI, BBMI), (BBPQ, BBMQ) pres-
ent a differential input impedance of about 2.9kΩ. At each
of the four baseband inputs, a lowpass fi lter using 200Ω
and 1.8pF to ground is incorporated (see Figure 1), which
limits the baseband bandwidth to approximately 250MHz
(–1dB point). The common mode voltage is about 2.06V
and is slightly temperature dependent. At TA = –40oC, the
common mode voltage is about 2.19V and at TA = 85oC
it is about 1.92V.
If the I/Q signals are DC-coupled to the LT5518, it is
important that the applied common mode voltage level
of the I and Q inputs is about 2.06V in order to properly
bias the LT5518. Some I/Q test generators allow setting
the common mode voltage independently. In this case, the
common mode voltage of those generators must be set
to 1.03V to match the LT5518 internal bias, because for
DC signals, there is no –6dB source-load voltage division
(see Figure 2).
Figure 2. DC Voltage Levels for a Generator Programmed at
1.03VDC for a 50Ω Load and for the LT5518 as a Load
DAC’s differential output current to minimize the LO to RF
feedthrough. Resistors R3A, R3B, R4A and R4B translate
the DAC’s output common mode level from about 0.5VDC
to the LT5518’s input at about 2.06VDC. For these resis-
tors, 1% accuracy is recommended. For different ambi-
ent temperatures, the LT5518 input common mode level
varies with a temperature coeffi cient of about –2.7mV/°C.
The internal common mode feedback loop will correct
these level changes in order to bias the LT5518 at the
correct operating point. Resistors R3 and R4 are chosen
high enough that the LT5518 common mode compliance
current value will not be exceeded at the inputs of the
LT5518 as a result of temperature shifts. Capacitors C4A
and C4B minimize the input signal attenuation caused by
the network R3A, R3B, R4A and R4B. This results in a
gain difference between low frequency and high frequency
baseband signals. The high frequency baseband –3dB
corner point is approximately given by:
f
–3dB = 1/[2π • C4A • (R3A||R4A||(RIN, DIFF/2)]
In this example, f–3dB = 58kHz.
This corner point should be set signifi cantly lower than the
minimum baseband signal frequency by choosing large
enough capacitors C4A and C4B. For signal frequencies
signifi cantly lower than f–3dB, the gain is reduced by ap-
proximately
G
DC = 20 • log [R3A||(RIN, DIFF/2)]/[R3A||(RIN, DIFF/2)
+ R4A]
In this example, GDC = –11dB.
Inserting the network of R3A, R3B, R4A, R4B, C4A and
C4B has the following consequences:
• Reduced LO feedthrough adjustment range. LO to RF
feedthrough can be reduced by adjusting the differential
DC offset voltage applied to the I and/or Q inputs. Be-
cause of the DC gain reduction, the range of adjustment
is reduced. The resolution of the offset adjustment is
improved by the same gain reduction factor.
• DC notch for uneven number of channels. The interface
drawn in Figure 3 might not be practical for an uneven
number of channels, since the gain at DC is lower and
will appear in the center of (one of) the channel(s). In
that case, a DC-coupled level shifting circuit is required,
or the LT5528 might be a better solution.
5518 F02
1.5k50Ω
LT5518GENERATOR
2.06VDC
2.06VDC
2.06VDC
+
–
+
–
50Ω
50Ω
GENERATOR
2.06VDC
1.03VDC
+
–
The LT5518 should be driven differentially; otherwise, the
even-order distortion products will degrade the overall
linearity severely. Typically, a DAC will be the signal source
for the LT5518. A reconstruction fi lter should be placed
between the DAC output and the LT5518’s baseband
inputs. DC coupling between the DAC outputs and the
LT5518 baseband inputs is recommended. Active level
shifters may be required to adapt the common mode level
of the DAC outputs to the common mode input voltage
of the LT5518. It is also possible to achieve a DC level
shift with passive components, depending on the appli-
cation. For example, if fl at frequency response to DC is
not required, then the interface circuit of Figure 3 may be
used. This fi gure shows a commonly used 0mA – 20mA
DAC output followed by a passive 5th order lowpass
fi lter. The DC-coupled interface allows adjustment of the
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LT5518
9
5518f
• Introduction of a (low frequency) time constant dur-
ing startup. For TDMA-like systems the time constant
introduced by C4A and C4B can cause some delay
during start-up. The associated time constant is ap-
proximately given by TD = RIN, CM • (C4A + C4B). In
this example it will result in a delay of about TD = 105
• 6.6n = 693ns.
The maximum sinusoidal single sideband RF output power
is about 5.5dBm for a full 0mA to 20mA DAC swing.
This maximum RF output level is usually limited by the
compliance voltage range of the DAC (VCOMPL) which is
assumed here to be 1.25V. When the DAC output voltage
swing is larger than this compliance voltage, the baseband
signal will distort and linearity requirements usually will
not be met. The following situations can cause the DAC’s
compliance voltage limit to be exceeded:
1. Too high DAC load impedance. If the DC impedance to
ground is higher than VCOMPL/IMAX = 1.25/0.02 = 62.5Ω,
the compliance voltage is exceeded for a full DAC swing. In
Figure 3, two 100Ω resistors in parallel are used, resulting
in a DC impedance to ground of 50Ω.
2. Too much DC offset. In some DACs, an additional DC
offset current can be set. For example, if the maximum
offset current is set to IMAX/8 = 2.5mA, then the maxi-
mum DC DAC load impedance to ground is reduced to
VCOMPL/IMAX • (1 + 1/8) = 1.25/0.0225 = 55Ω.
3. DC shift caused by R3A, R3B, R4A and R4B if used. The
DC shift network consisting of R3A, R3B, R4A and R4B
Figure 3. LT5518 5th Order Filtered Baseband Interface with Common DAC (Only I-Channel is Shown)
will increase the voltage on the DAC output by dumping
an extra current into resistors R1A, R1B, R2A and R2B.
This current is about (VCC – VDAC)/(R3A + R4A) = (5
– 0.5)/(3.01k + 5.63k) = 0.52mA. Maximum impedance
to ground will then be VCOMPL/(IMAX + ILS) = 1.25/0.02052
= 60.9Ω.
4. Refl ection of out-of-band baseband signal power. DAC
output signal components higher than the cut-off frequency
of the lowpass fi lter will not see R2A and R2B as load
resistors and therefore will see only R1A, R1B and the
fi lter components as a load. Therefore, it is important to
start the lowpass fi lter with a capacitor (C1), in order to
shunt the DAC higher frequency components and thereby,
limit the required extra voltage headroom.
The LT5518’s output 1dB compression point is about
8.5dBm, and with the interface network described above,
a common DAC cannot drive the part into compression.
However, it is possible to increase the driving capability
by using a negative supply voltage. For example, if a –1V
supply is available, resistors R1A, R1B, R2A and R2B
can be made 200Ω each and connected with one side to
the –1V supply instead of ground. Typically, the voltage
compliance range of the DAC is –1V to 1.25V, so the DAC’s
output voltage will stay within this range. Almost 6dB extra
voltage swing is available, thus enabling the DAC to drive
the LT5518 beyond its 1dB compression point. Resistors
R3A, R3B, R4A, R4B and the lowpass fi lter components
must be adjusted for this case.
GND
C2
BBPI
BBMI
L1A
L1B
C1 C3
C4A
3.3nF
R4A
3.01k
R4B
3.01k
C4B
3.3nF
R1A
100Ω
0.53VDC
0.53VDC 2.1VDC
2.1VDC
R1B
100Ω
R2A
100Ω
R2B
100Ω
R3A
5.63k
R3B
5.63k
DAC
0mA TO 20mA
0mA TO 20mA
L2A
L2B
RF = 5.5dBm, MAX
5V VCC C
GND
LOMI
LOPI
FROM
Q
5518 F03
BALUN
CM
VREF = 500mV
200Ω
200Ω
1.8pF
1.8pF 1.3k
1.3k
LT5518
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LT5518
10
5518f
Some DACs use an output common mode voltage of 3.3V.
In that case, the interface circuit drawn in Figure 4 may be
used. The performance is very similar to the performance
of the DAC interface drawn in Figure 3, since the source
and load impedances of the lowpass ladder fi lter are both
200Ω differential and the current drive is the same. There
are some small differences:
• The baseband drive capability cannot be improved using
an extra supply voltage, since the compliance range of
the DACs in Figure 4 is typically 3.3V – 0.5V to 3.3V +
0.5V, so its range has already been fully used.
• GDC and f–3dB are a little different, since R3A (and R3B)
is 4.99k instead of 5.6k to accommodate the proper
DC level shift.
LO Section
The internal LO input amplifi er performs single-ended to
differential conversion of the LO input signal. Figure 5
shows the equivalent circuit schematic of the LO input.
The internal, differential LO signal is split into in-phase
and quadrature (90° phase shifted) signals that drive LO
buffer sections. These buffers drive the double balanced I
and Q mixers. The phase relationship between the LO input
and the internal in-phase LO and quadrature LO signals
is fi xed, and is independent of start-up conditions. The
phase shifters are designed to deliver accurate quadrature
signals for an LO frequency near 2GHz. For frequencies
signifi cantly below 1.8GHz or above 2.4GHz, the quadra-
ture accuracy will diminish, causing the image rejection
to degrade. The LO pin input impedance is about 50Ω,
and the recommended LO input power is 0dBm. For lower
LO input power, the gain, OIP2, OIP3 and dynamic range
will degrade, especially below –5dBm and at TA = 85°C.
For high LO input power (e.g. 5dBm), the LO feedthrough
will increase, without improvement in linearity or gain.
Harmonics present on the LO signal can degrade the image
rejection, because they introduce a small excess phase shift
in the internal phase splitter. For the second (at 4GHz) and
third harmonics (at 6GHz) at –20dBc level, the introduced
signal at the image frequency is about –55dBc or lower,
corresponding to an excess phase shift much less than 1
degree. For the second and third harmonics at –10dBc,
still the introduced signal at the image frequency is about
–46dBc. Higher harmonics than the third will have less
impact. The LO return loss typically will be better than
14dB over the 1.7GHz to 2.4GHz range. Table 1 shows
the LO port input impedance vs frequency.
Figure 5. Equivalent Circuit Schematic of the LO Input
LO
INPUT
20pF
ZIN ≈ 57Ω
5518 F05
VCC
C2 GND
3.3V
BBPI
BBMI
L1A
L1B
C1 C3
C4A
3.3nF
R4A
3.01k
R4B
3.01k
C4B
3.3nF
3.3VDC
3.3VDC 2.1VDC
2.1VDC
R3A
4.99k
R3B
4.99k
DAC
0mA TO
20mA
0mA TO
20mA
L2A
L2B
RF = 5.5dBm, MAX
5V VCC C
GND
LOMI
LOPI
FROM
Q
5518 F04
BALUN
CM
VREF = 500mV
200Ω
200Ω
1.8pF
1.8pF 1.3k
1.3k
LT5518
Figure 4. LT5518 5th Order Filtered Baseband Interface with 3.3VCM DAC (Only I-Channel is Shown).
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LT5518
11
5518f
Table 1. LO Port Input Impedance vs Frequency for EN = High
Frequency Input Impedance S11
MHz Ω Mag Angle
1000 44.5 + j18.2 0.197 95
1400 60.3 + j6.8 0.112 30
1600 62.8 – j0.6 0.113 –2.4
1800 62.4 – j9.0 0.136 –32
2000 56.7 – j15.6 0.157 –58
2200 50.9 – j16.5 0.161 –77
2400 46.6 – j15.2 0.159 –94
2600 42.9 – j13.9 0.165 –109
The input impedance of the LO port is different if the part
is in shut-down mode. The LO input impedance for EN =
Low is given in Table 2.
Table 2. LO Port Input Impedance vs Frequency for EN = Low
Frequency Input Impedance S11
MHz Ω Mag Angle
1000 42.1 + j43.7 0.439 75
1400 121 + j34.9 0.454 15
1600 134 – j31.6 0.483 –11
1800 91.3 – j68.5 0.510 –33
2000 56.4 – j66.3 0.532 –53
2200 37.7 – j54.9 0.544 –70
2400 27.9 – j43.6 0.550 –87
2600 22.1 – j33.9 0.553 –104
RF Section
After up-conversion, the RF outputs of the I and Q mixers are
combined. An on-chip balun performs internal differential
to single-ended output conversion, while transforming the
output signal impedance to 50Ω. Table 3 shows the RF
port output impedance vs frequency.
Table 3. RF Port Output Impedance vs Frequency for EN = High
and PLO = 0dBm
Frequency Input Impedance S22
MHz Ω Mag Angle
1000 21.3 + j9.7 0.421 153
1400 29.8 + j20.3 0.348 121
1600 39.1 + j23.5 0.280 100
1800 50.8 + j18.4 0.180 77.1
2000 52.1 + j5.4 0.057 65.5
2200 43.2 – j0.1 0.073 –179
2400 36.0 + j2.0 0.164 171
2600 32.1 + j5.6 0.228 159
Figure 6. Equivalent Circuit Schematic of the RF Output
RF
OUTPUT
20pF
21pF 3nH
52.5Ω
5518 F06
VCC
The RF output S22 with no LO power applied is given in
Table 4.
Table 4. RF Port Output Impedance vs Frequency for EN = High
and No LO Power Applied
Frequency Input Impedance S22
MHz Ω Mag Angle
1000 21.7 + j9.9 0.416 153
1400 32.3 + j19.5 0.312 119
1600 42.2 + j18.5 0.214 102
1800 46.8 + j9.6 0.104 103
2000 41.8 + j3.7 0.098 154
2200 36.1 + j4.3 0.170 160
2400 32.8 + j7.4 0.226 152
2600 31.2 + j10.5 0.264 144
For EN = Low the S22 is given in Table 5.
Table 5. RF Port Output Impedance vs Frequency for EN = Low
Frequency Input Impedance S22
MHz Ω Mag Angle
1000 20.9+j9.6 0.428 154
1400 28.5 + j20.2 0.365 123
1600 36.7 + j24.5 0.311 103
1800 48.7 + j23.1 0.229 80.2
2000 55.7 + j11.0 0.116 56.7
2200 48.9 + j0.6 0.013 158.9
2400 39.8 – j0.02 0.115 –179
2600 34.2 + j3.2 0.193 167
To improve S22 for lower frequencies, a shunt capacitor
can be added to the RF output. At higher frequencies, a
shunt inductor can improve the S22. Figure 6 shows the
equivalent circuit schematic of the RF output.
Note that an ESD diode is connected internally from
the RF output to ground. For strong output RF signal
levels (higher than 3dBm) this ESD diode can degrade
the linearity performance if the 50Ω termination imped-
ance is connected directly to ground. To prevent this, a
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LT5518
12
5518f
coupling capacitor can be inserted in the RF output line.
This is strongly recommended during a 1dB compression
measurement.
Enable Interface
Figure 7 shows a simplifi ed schematic of the EN pin inter-
face. The voltage necessary to turn on the LT5518 is 1.0V.
To disable (shutdown) the chip, the Enable voltage must
be below 0.5V. If the EN pin is not connected, the chip is
disabled. This EN = Low condition is guaranteed by the
75kΩ on-chip pull-down resistor. It is important that the
voltage at the EN pin does not exceed VCC by more than
0.5V. If this should occur, the full chip supply current could
be sourced through the EN pin ESD protection diodes.
Damage to the chip may result.
Figure 9. Demo Board Circuit Schematic
BBIPBBIM
J1
16 15 14 13
VCC
VCC EN
9
10
11
12
4
3
2
1
5678
5518 F09
17
BBQM
BBQP
C4
100nF
J6
RF
OUT
J3
LO
IN
J4
GND
E3
E2
E1
J5
GND
E4 C6
3.3nF
C3
100nF
J2
BBMI
LT5518
BBPI VCC
BBMQ GND
GND
BBPQ VCC
GND
GND
RF
GND
GND
LO
GND
EN
GND
100
R7
R10
3.01k R9
5.62k
R2
5.62k
R1
5.62k
R8
5.62k
R11
3.01k
R13
52.3Ω
C2
3.3nF
R4
3.01k
R6
52.3Ω
C5
3.3nF
R12
52.3Ω
R3
3.01k
C1
3.3nF
R5
52.3Ω
BOARD NUMBER: DC831A
Figure 10. Component Side Silk Screen of Demo Board
Evaluation and Demo Boards
Figure 8 shows the schematic of the evaluation board that
was used for the measurements summarized in the Elec-
trical Characteristics tables and the Typical Performance
Characteristic plots.
Figure 9 shows the demo board schematic. Resistors R3,
R4, R10 and R11 may be replaced by shorting wires if a
fl at frequency response to DC is required. A good ground
connection is required for the exposed pad of the LT5518
package. If this is not done properly, the RF performance
will degrade. The exposed pad also provides heat sink-
ing for the part and minimizes the possibility of the chip
overheating. R7 (optional) limits the Enable pin current in
the event that the Enable pin is pulled high while the VCC
inputs are low. In Figures 10, 11 and 12 the silk screen
and the demo board PCB layouts are shown. If improved
LO and Image suppression is required, an LO feedthrough
calibration and an Image suppression calibration can be
performed.
Figure 7. EN Pin Interface
EN
75k
5518 F07
VCC
25k
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Figure 8. Evaluation Board Circuit Schematic
BBIPBBIM
J1
16 15 14 13
VCC
VCC EN
9
10
11
12
4
3
2
1
5678
5518 F08
17
BBQM
BBQP
C1
100nF J6
RF
OUT
J3
LO
IN
J4
GND
J5
C2
100nF
J2
BBMI
LT5518
BBPI VCC
BBMQ GND
GND
BBPQ VCC
GND
GND
RF
GND
GND
LO
GND
EN
GND
100
R1
BOARD NUMBER: DC729A
LT5518
13
5518f
Figure 12. Bottom Side Layout of Demo Board
Figure 13. 1.5GHz to 2.4GHz Direct Conversion Transmitter
Application with LO Feedthrough and Image Calibration Loop
90°
0°
LT5518
BASEBAND
GENERATOR
CAL
LO FEEDTHROUGH CAL OUT
IMAGE CAL OUT
PA
VCO/SYNTHESIZER
RF = 1.5GHz
TO 2.4GHz
EN
2, 4, 6, 9, 10, 12, 15, 17
100nF
×2
5V
V-I
V-I
I-CHANNEL
Q-CHANNEL BALUN
14
16
1
7
5
8, 13
VCC
11
3
5518 F13
I-DAC
Q-DAC
ADC
Application Measurements
The LT5518 is recommended for base-station applications
using various modulation formats. Figure 13 shows a
typical application. The CAL box in Figure 13 allows for
LO feedthrough and Image suppression calibration. Fig-
ure 14 shows the ACPR performance for W-CDMA using
one or four channel modulation. Figures 15, 16 and 17
illustrate the 1, 2 and 4-channel W-CDMA measurement.
To calculate ACPR, a correction is made for the spectrum
analyzer noise fl oor.
If the output power is high, the ACPR will be limited by the
linearity performance of the part. If the output power is
low, the ACPR will be limited by the noise performance of
the part. In the middle, an optimum ACPR is obtained.
Because of the LT5518’s very high dynamic range, the test
equipment can limit the accuracy of the ACPR measure-
ment. Consult the factory for advice on ACPR measure-
ment, if needed.
The ACPR performance is sensitive to the amplitude match
of the BBIP and BBIM (or BBQP and BBQM) input voltage.
This is because a difference in AC voltage amplitude will
give rise to a difference in amplitude between the even-order
harmonic products generated in the internal V-I converter.
As a result, they will not cancel out entirely. Therefore, it
APPLICATIO S I FOR ATIO
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Figure 11. Component Side Layout of Demo Board
LT5518
14
5518f
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
RF FREQUENCY (MHz)
2125
5518 F16
2130 2135 2140 2145 2150 2155
POWER IN 30kHz BW (dBm)
DOWNLINK TEST
MODEL 64 DPCH
UNCORRECTED
SPECTRUM
CORRECTED
SPECTRUM
SYSTEM NOISE FLOOR
RF OUTPUT POWER PER CARRIER (dBm)
–34 –30 –26 –22 –18 –14 –10
)cBd( RPCTLA ,RP
C
A
)
z
H
/
m
Bd
( TESF
F
O
z
H
M03 T
A
ROOLF ESION
–65
–60
–55
5518 F14
–70
–75
–85
–80
–145
–140
–135
–150
–155
–165
–160
4-CH ACPR
4-CH NOISE
1-CH NOISE
4-CH ALTCPR
1-CH ALTCPR
1-CH ACPR
DOWNLINK TEST MODEL 64 DPCH
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
TEMPERATURE (°C)
–40
5518 F18
–200 20406080
LO FT (dBm), IR (dB)
LO FEEDTHROUGH
IMAGE REJECTION
CALIBRATED WITH PRF = –30dBm
–40
–50
–60
–70
–80
–90
–110
–100
–120
–130
RF FREQUENCY (MHz)
2115
5518 F17
2125 2135 2145 2155 2165
POWER IN 30kHz BW (dBm)
DOWNLINK
TEST
MODEL 64
DPCH
UNCORRECTED
SPECTRUM
CORRECTED
SPECTRUM
SYSTEM NOISE FLOOR
RF FREQUENCY (MHz)
2127.5
POWER IN 30kHz BW (dBm)
2147.52142.5
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
5518 F15
2137.52132.5 2152.5
DOWNLINK TEST
MODEL 64 DPCH
CORRECTED
SPECTRUM
UNCORRECTED
SPECTRUM
SYSTEM NOISE FLOOR
is important to keep the amplitudes at the BBIP and BBIM
inputs (or BBQP and BBQM) as equal as possible.
When the temperature is changed after calibration, the LO
feedthrough and the Image Rejection performance will
change. This is illustrated in Figure 18. The LO feedthrough
and Image Rejection can also change as function of the
baseband drive level, as is depicted in Figure 19. The RF
output power, IM2 and IM3 vs two-tone baseband drive
level are given in Figure 20.
Figure 14. W-CDMA ACPR, ALTCPR and Noise vs
RF Output Power at 2140MHz for 1 and 4 Channels
Figure 15. 1-Channel W-CDMA Spectrum
Figure 16. 2-Channel W-CDMA
Spectrum
Figure 18. LO Feedthrough and
Image Rejection vs Temperature
after Calibration at 25°C
Figure 17. 4-Channel W-CDMA
Spectrum
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5518f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However,
no responsibility is assumed for its use. Linear Technology Corporation makes no representation that
the interconnection of its circuits as described herein will not infringe on existing patent rights.
UF Package
16-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1692)
Figure 19. Image Rejection and LO Feedthrough
vs Baseband Drive Voltage After Calibration at 25°C
and VBBI = 0.2VP-P, DIFF
fBBI = 2MHz, 2.1MHz, 0°
fBBQ = 2MHz, 2.1MHz, 90°
PLO = 0dBm
fRF = fBB + fLO
fLO = 2.14GHz
IM2 = POWER AT fLO + 4.1MHz
IM3 = MAX POWER AT
fLO + 1.9MHz or fLO + 2.2MHz
VCC = 5V
EN = HIGH
I AND Q BASEBAND VOLTAGE (VP-P, DIFF, EACH TONE)
0.1
–90
–80
–40
HD2, HD3 (dBc)
–70
–60
–50
–30
–20
–10
0
10
110
5518 F20
TA = –40°C
TA = 85°C
TA = 25°C
RF
IM3
IM2
Figure 20. RF Two-Tone Power, IM2 and
IM3 at 2140MHz vs Baseband Voltage
I AND Q BASEBAND VOLTAGE (VP-P, DIFF)
0
PRF, LO FT (dBm), IR (dBc)
20
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90 4
5518 F19
1235
TA = –40°C
TA = 85°C
TA = 25°C
LO FT
IR
PRF
fBBI = 2MHz, 0°
fBBQ = 2MHz, 90°
PLO = 0dBm
fRF = fBB + fLO
fLO = 2.14GHz
VCC = 5V
EN = HIGH
APPLICATIO S I FOR ATIO
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PACKAGE DESCRIPTIO
U
4.00 ± 0.10
(4 SIDES)
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGC)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.55 ± 0.20
1615
1
2
BOTTOM VIEW—EXPOSED PAD
2.15 ± 0.10
(4-SIDES)
0.75 ± 0.05 R = 0.115
TYP
0.30 ± 0.05
0.65 BSC
0.200 REF
0.00 – 0.05
(UF16) QFN 10-04
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.72 ±0.05
0.30 ±0.05
0.65 BSC
2.15 ± 0.05
(4 SIDES)
2.90 ± 0.05
4.35 ± 0.05
PACKAGE OUTLINE
PIN 1 NOTCH R = 0.20 TYP
OR 0.35 × 45° CHAMFER
LT5518
16
5518f
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2005
LT/TP 0205 1K • PRINTED IN USA
PART NUMBER DESCRIPTION COMMENTS
Infrastructure
LT5511 High Linearity Up-Converting Mixer RF Output to 3GHz, 17dBm IIP3, Integrated LO Buffer
LT5512 DC-3GHz High Signal Level Down-Converting Mixer DC to 3GHz, 17dBm IIP3, Integrated LO Buffer
LT5514 Ultralow Distortion, IF Amplifi er/ADC Driver with 850MHz Bandwidth, 47dBm OIP3 at 100MHz,
Digitally Controlled Gain 10.5dB to 33dB Gain Control Range
LT5515 1.5GHz to 2.5GHz Direct Conversion Quadrature Demodulator 20dBm IIP3, Integrated LO Quadrature Generator
LT5516 0.8GHz to 1.5GHz Direct Conversion Quadrature Demodulator 21.5dBm IIP3, Integrated LO Quadrature Generator
LT5517 40MHz to 900MHz Quadrature Demodulator 21dBm IIP3, Integrated LO Quadrature Generator
LT5519 0.7GHz to 1.4GHz High Linearity Up-Converting Mixer 17.1dBm IIP3 at 1GHz, Integrated RF Output Transformer with 50Ω
Matching, Single-Ended LO and RF Ports Operation
LT5520 1.3GHz to 2.3GHz High Linearity Up-Converting Mixer 15.9dBm IIP3 at 1.9GHz, Integrated RF Output Transformer with
50Ω Matching, Single-Ended LO and RF Ports Operation
LT5521 10MHz to 3700MHz High Linearity Up-Converting Mixer 24.2dBm IIP3 at 1.95GHz, NF = 12.5dB, 3.15V to 5.25V Supply,
Single-Ended LO Port Operation
LT5522 600MHz to 2.7GHz High Signal Level Down-Converting Mixer 4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz, NF = 12.5dB, 50Ω
Single-Ended RF and LO Ports
LT5524 Low Power, Low Distortion ADC Driver with 450MHz Bandwidth, 40dBm OIP3, 4.5dB to 27dB Gain Control
Digitally Programmable Gain
LT5525 High Linearity, Low Power Downconverting Mixer Single-Ended 50Ω RF and LO Ports, 17.6dBm IIP3 at 1900MHz,
I
CC = 28mA
LT5526 High Linearity, Low Power Downconverting Mixer 3V to 5.3V Supply, 16.5dBm IIP3, 100kHz to 2GHz RF, NF = 11dB,
I
CC = 28mA
LT5528 1.5GHz – 2.4GHz High Linearity Direct Quadrature Modulator 4.5V to 5.25V Supply, 22dBm OIP3 at 2GHz, NFloor = 159dBm/Hz,
50Ω Single-Ended BB, RF and LO Ports
RF Power Detectors
LT5504 800MHz to 2.7GHz RF Measuring Receiver 80dB Dynamic Range, Temperature Compensated,
2.7V to 5.25V Supply
LTC®5505 RF Power Detectors with >40dB Dynamic Range 300MHz to 3GHz, Temperature Compensated, 2.7V to 6V Supply
LTC5507 100kHz to 1000MHz RF Power Detector 100kHz to 1GHz, Temperature Compensated, 2.7V to 6V Supply
LTC5508 300MHz to 7GHz RF Power Detector 44dB Dynamic Range, Temperature Compensated, SC70 Package
LTC5509 300MHz to 3GHz RF Power Detector 36dB Dynamic Range, Low Power Consumption, SC70 Package
LTC5530 300MHz to 7GHz Precision RF Power Detector Precision VOUT Offset Control, Shutdown, Adjustable Gain
LTC5531 300MHz to 7GHz Precision RF Power Detector Precision VOUT Offset Control, Shutdown, Adjustable Offset
LTC5532 300MHz to 7GHz Precision RF Power Detector Precision VOUT Offset Control, Adjustable Gain and Offset
LT5534 50MHz to 3GHz RF Power Detector with 60dB Dynamic Range ±1dB Output Variation Overtemperature, 38ns Response Time
Low Voltage RF Building Block
LT5546 500MHz Quadrature Demodulator with VGA 17MHz Baseband Bandwidth, 40MHz to 500MHz IF,
and 17MHz Baseband Bandwidth 1.8V to 5.25V Supply, –7dB to 56dB Linear Power Gain
Wide Bandwidth ADCs
LT1749 12-Bit, 80Msps 500MHz BW S/H, 71.8dB SNR
LT1750 14-Bit, 80Msps 500MHz BW S/H, 75.5dB SNR
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