Quad, 14-Bit, 50 MSPS
Serial LVDS 1.8 V ADC
Data Sheet AD9259
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2006–2011 Analog Devices, Inc. All rights reserved.
FEATURES
4 ADCs integrated into 1 package
98 mW ADC power per channel at 50 MSPS
SNR = 73 dB (to Nyquist)
ENOB = 12 bits
SFDR = 84 dBc (to Nyquist)
Excellent linearity
DNL = ±0.5 LSB (typical)
INL = ±1.5 LSB (typical)
Serial LVDS (ANSI-644, default)
Low power, reduced signal option (similar to IEEE 1596.3)
Data and frame clock outputs
315 MHz full-power analog bandwidth
2 V p-p input voltage range
1.8 V supply operation
Serial port control
Full-chip and individual-channel power-down modes
Flexible bit orientation
Built-in and custom digital test pattern generation
Programmable clock and data alignment
Programmable output resolution
Standby mode
APPLICATIONS
Medical imaging and nondestructive ultrasound
Portable ultrasound and digital beam-forming systems
Quadrature radio receivers
Diversity radio receivers
Tape drives
Optical networking
Test equipment
GENERAL DESCRIPTION
The AD9259 is a quad, 14-bit, 50 MSPS analog-to-digital con-
verter (ADC) with an on-chip sample-and-hold circuit designed
for low cost, low power, small size, and ease of use. The product
operates at a conversion rate of up to 50 MSPS and is optimized for
outstanding dynamic performance and low power in applications
where a small package size is critical.
The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
FUNCTIONAL BLOCK DIAGRAM
SERIAL
LVDS
REF
SELECT
+
–
AD9259
AGND
VIN – A
VIN + A
VIN – B
VIN + B
VIN – D
VIN + D
VIN – C
VIN + C
SENSE
VREF
A
V
DD DRVDD
14
14
14
14
PD
W
N
REFT
REFB
D – A
D + A
D – B
D + B
D – D
D + D
D – C
D + C
FCO–
FCO+
DCO+
DCO–
CLK+
DRGND
CLK–
SERIAL PORT
INTERFACE
CSB SCLK/DTP
SDIO/ODMRBIAS
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
PIPELINE
ADC
PIPELINE
ADC
PIPELINE
ADC
PIPELINE
ADC
DATA RATE
MULTIPLIER
0.5V
05965-001
T/H
T/H
T/H
T/H
Figure 1.
The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock output (DCO) for
capturing data on the output and a frame clock output (FCO)
for signaling a new output byte are provided. Individual-channel
power-down is supported and typically consumes less than 2 mW
when all channels are disabled.
The ADC contains several features designed to maximize
flexibility and minimize system cost, such as programmable
clock and data alignment and programmable digital test pattern
generation. The available digital test patterns include built-in
deterministic and pseudorandom patterns, along with custom user-
defined test patterns entered via the serial port interface (SPI).
The AD9259 is available in a RoHS-compliant, 48-lead LFCSP. It is
specified over the industrial temperature range of −40°C to +85°C.
PRODUCT HIGHLIGHTS
1. Small Footprint. Four ADCs are contained in a small, space-
saving package.
2. Low power of 98 mW/channel at 50 MSPS.
3. Ease of Use. A data clock output (DCO) operates at
frequencies of up to 350 MHz and supports double data
rate (DDR) operation.
4. User Flexibility. The SPI control offers a wide range of flexible
features to meet specific system requirements.
5. Pin-Compatible Family. This includes the AD9287 (8-bit),
AD9219 (10-bit), and AD9228 (12-bit).
AD9259 Data Sheet
Rev. E | Page 2 of 52
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 3
Specifications ..................................................................................... 4
AC Specifications .......................................................................... 5
Digital Specifications ................................................................... 6
Switching Specifications .............................................................. 7
Timing Diagrams .......................................................................... 8
Absolute Maximum Ratings .......................................................... 10
Thermal Impedance ................................................................... 10
ESD Caution ................................................................................ 10
Pin Configuration and Function Descriptions ........................... 11
Equivalent Circuits ......................................................................... 13
Typical Performance Characteristics ........................................... 15
Theory of Operation ...................................................................... 19
Analog Input Considerations ................................................... 19
Clock Input Considerations ...................................................... 21
Serial Port Interface (SPI) .............................................................. 29
Hardware Interface ..................................................................... 29
Memory Map .................................................................................. 31
Reading the Memory Map Table .............................................. 31
Reserved Locations .................................................................... 31
Default Values ............................................................................. 31
Logic Levels ................................................................................. 31
Evaluation Board ............................................................................ 35
Power Supplies ............................................................................ 35
Input Signals................................................................................ 35
Output Signals ............................................................................ 35
Default Operation and Jumper Selection Settings ................. 36
Alternative Analog Input Drive Configuration...................... 37
Outline Dimensions ....................................................................... 51
Ordering Guide .......................................................................... 51
Data Sheet AD9259
Rev. E | Page 3 of 52
REVISION HISTORY
12/11—Rev. D to Rev. E
Changes to Output Signals Section and Figure 60 ...................... 35
Change to Default Operation and Jumper Selection Settings
Section .............................................................................................. 36
Change to Figure 63 ........................................................................ 39
Added Endnote 2 in Ordering Guide ........................................... 51
4/10—Rev. C to Rev. D
Changes to Table 16 ........................................................................ 33
Updated Outline Dimensions ........................................................ 51
Changes to Ordering Guide ........................................................... 51
11/09—Rev. B to Rev. C
Added EPAD Note to Figure 5 ...................................................... 11
Changes to Input Signals Section and Figure 60 ......................... 35
Updated Outline Dimensions ........................................................ 51
Changes to Ordering Guide ........................................................... 51
7/07—Rev. A to Rev. B
Change to General Description ....................................................... 1
Changes to Figure 2 and Figure 4 .................................................... 7
Changes to the Hardware Interface Section ................................ 29
Changes to Table 17 ........................................................................ 48
5/07—Rev. 0 to Rev. A
Changes to Effective Number of Bits (ENOB) ..................................... 4
Changes to Logic Output (SDIO/ODM) .............................................. 5
Added Endnote 3 to Table 3..................................................................... 5
Change to Pipeline Latency ..................................................................... 6
Changes to Figure 2 to Figure 4 ............................................................... 7
Changes to Figure 10 ............................................................................... 12
Changes to Figure 15 to Figure 17, Figure 22, and Figure 31 .......... 14
Changes to Figure 21 and Figure 22 Captions .................................... 15
Changes to Figure 41 ............................................................................... 19
Changes to Clock Duty Cycle Considerations Section ..................... 20
Changes to Power Dissipation and Power-Down Mode Section ... 21
Changes to Figure 50 to Figure 52 Captions ....................................... 23
Change to Table 8 ..................................................................................... 23
Changes to Table 9 Endnote .................................................................. 24
Changes to Digital Outputs and Timing Section ............................... 25
Added Table 10 ......................................................................................... 25
Changes to RBIAS Pin Section .............................................................. 26
Deleted Figure 53 and Figure 54 ........................................................... 26
Changes to Figure 56 ............................................................................... 27
Changes to Hardware Interface Section .............................................. 28
Added Figure 57 ....................................................................................... 29
Changes to Table 15 ................................................................................. 29
Changes to Reading the Memory Map Table Section ...................... 30
Change to Output Signals Section ........................................................ 34
Changes to Figure 60 ............................................................................... 34
Changes to Default Operation and
Jumper Selection Settings Section ................................................... 35
Changes to Alternative Analog Input Drive
Configuration Section ........................................................................ 36
Changes to Figure 63 ............................................................................... 38
Changes to Table 17 ................................................................................. 46
Changes to Ordering Guide ................................................................... 50
6/06—Revision 0: Initial Version
AD9259 Data Sheet
Rev. E | Page 4 of 52
SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 1.
Parameter1 Temperature Min Typ Max Unit
RESOLUTION 14 Bits
ACCURACY
No Missing Codes Full Guaranteed
Offset Error Full ±1 ±8 mV
Offset Matching Full ±2 ±8 mV
Gain Error Full ±0.5 ±2 % FS
Gain Matching Full ±0.3 ±0.7 % FS
Differential Nonlinearity (DNL) Full ±0.5 ±1.0 LSB
Integral Nonlinearity (INL) Full ±1.5 ±3.5 LSB
TEMPERATURE DRIFT
Offset Error Full ±2 ppm/°C
Gain Error Full ±17 ppm/°C
Reference Voltage (1 V Mode) Full ±21 ppm/°C
REFERENCE
Output Voltage Error (VREF = 1 V) Full ±5 ±30 mV
Load Regulation at 1.0 mA (VREF = 1 V) Full 3 mV
Input Resistance Full 6 kΩ
ANALOG INPUTS
Differential Input Voltage (VREF = 1 V) Full 2 V p-p
Common-Mode Voltage Full AVDD/2 V
Differential Input Capacitance Full 7 pF
Analog Bandwidth, Full Power Full 315 MHz
POWER SUPPLY
AVDD Full 1.7 1.8 1.9 V
DRVDD Full 1.7 1.8 1.9 V
IAVDD Full 185 192.5 mA
IDRVDD Full 32.5 34.7 mA
Total Power Dissipation (Including Output Drivers) Full 392 409 mW
Power-Down Dissipation Full 2 4 mW
Standby Dissipation2 Full 72 mW
CROSSTALK Full −100 dB
CROSSTALK (Overrange Condition)3 Full −100 dB
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, at www.analog.com for definitions and for details on how these tests were
completed.
2 Can be controlled via the SPI.
3 Overrange condition is specific with 6 dB of the full-scale input range.
Data Sheet AD9259
Rev. E | Page 5 of 52
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 2.
Parameter1 Temperature Min Typ Max Unit
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 2.4 MHz Full 73.5 dB
fIN = 19.7 MHz Full 71.0 73.0 dB
fIN = 70 MHz Full 72.8 dB
SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD)
fIN = 2.4 MHz Full 72.7 dB
fIN = 19.7 MHz Full 70.2 72.2 dB
fIN = 70 MHz Full 72.0 dB
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 2.4 MHz Full 11.92 Bits
fIN = 19.7 MHz Full 11.5 11.85 Bits
fIN = 70 MHz Full 11.8 Bits
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 2.4 MHz Full 84 dBc
fIN = 19.7 MHz Full 73 84 dBc
fIN = 70 MHz Full 78 dBc
WORST HARMONIC (Second or Third)
fIN = 2.4 MHz Full −88 dBc
fIN = 19.7 MHz Full −84 −73 dBc
fIN = 70 MHz Full −78 dBc
WORST OTHER (Excluding Second or Third)
fIN = 2.4 MHz Full −90 dBc
fIN = 19.7 MHz Full −90 −80 dBc
fIN = 70 MHz Full −88 dBc
TWO-TONE INTERMODULATION DISTORTION (IMD)—AIN1
AND AIN2 = −7.0 dBFS
fIN1 = 15 MHz, fIN2 = 16 MHz 25°C 80.0 dBc
fIN1 = 70 MHz, fIN2 = 71 MHz 25°C 80.0 dBc
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, at www.analog.com for definitions and for details on how these tests were
completed.
AD9259 Data Sheet
Rev. E | Page 6 of 52
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 3.
Parameter1 Temperature Min Typ Max Unit
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance CMOS/LVDS/LVPECL
Differential Input Voltage2 Full 250 mV p-p
Input Common-Mode Voltage Full 1.2 V
Input Resistance (Differential) 25°C 20 kΩ
Input Capacitance
25°C
1.5
LOGIC INPUTS (PDWN, SCLK/DTP)
Logic 1 Voltage Full 1.2 3.6 V
Logic 0 Voltage Full 0.3 V
Input Resistance 25°C 30 kΩ
Input Capacitance 25°C 0.5 pF
LOGIC INPUT (CSB)
Logic 1 Voltage Full 1.2 3.6 V
Logic 0 Voltage Full 0.3 V
Input Resistance 25°C 70 kΩ
Input Capacitance 25°C 0.5 pF
LOGIC INPUT (SDIO/ODM)
Logic 1 Voltage Full 1.2 DRVDD + 0.3 V
Logic 0 Voltage
Full
0
0.3
Input Resistance 25°C 30 kΩ
Input Capacitance 25°C 2 pF
LOGIC OUTPUT (SDIO/ODM)3
Logic 1 Voltage (IOH = 800 μA) Full 1.79 V
Logic 0 Voltage (IOL = 50 μA) Full 0.05 V
DIGITAL OUTPUTS (D + x, D − x), (ANSI-644)
Logic Compliance LVDS
Differential Output Voltage (VOD) Full 247 454 mV
Output Offset Voltage (VOS) Full 1.125 1.375 V
Output Coding (Default) Offset binary
DIGITAL OUTPUTS (D + x, D − x),
(Low Power, Reduced Signal Option)
Logic Compliance LVDS
Differential Output Voltage (VOD) Full 150 250 mV
Output Offset Voltage (V
OS
)
Full
1.10
1.30
Output Coding (Default) Offset binary
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, at www.analog.com for definitions and for details on how these tests were
completed.
2 This is specified for LVDS and LVPECL only.
3 This is specified for 13 SDIO pins sharing the same connection.
Data Sheet AD9259
Rev. E | Page 7 of 52
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 4.
Parameter1, 2 Temp Min Typ Max Unit
CLOCK3
Maximum Clock Rate Full 50 MSPS
Minimum Clock Rate Full 10 MSPS
Clock Pulse Width High (tEH) Full 10 ns
Clock Pulse Width Low (tEL) Full 10 ns
OUTPUT PARAMETERS3
Propagation Delay (tPD) Full 2.0 2.7 3.5 ns
Rise Time (tR) (20% to 80%) Full 300 ps
Fall Time (tF) (20% to 80%) Full 300 ps
FCO Propagation Delay (tFCO) Full 2.0 2.7 3.5 ns
DCO Propagation Delay (tCPD)4 Full tFCO +
(tSAMPLE/28)
ns
DCO to Data Delay (tDATA )4 Full (tSAMPLE/28) − 300 (tSAMPLE/28) (tSAMPLE/28) + 300 ps
DCO to FCO Delay (tFRAME)4 Full (tSAMPLE/28) − 300 (tSAMPLE/28) (tSAMPLE/28) + 300 ps
Data to Data Skew
(tDATA-MAX − tDATA-MIN)
Full ±50 ±150 ps
Wake-Up Time (Standby) 25°C 600 ns
Wake-Up Time (Power-Down) 25°C 375 μs
Pipeline Latency Full 8 CLK
cycles
APERTURE
Aperture Delay (tA) 25°C 500 ps
Aperture Uncertainty (Jitter) 25°C <1 ps rms
Out-of-Range Recovery Time 25°C 2 CLK
cycles
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, at www.analog.com for definitions and for details on how these tests were
completed.
2 Measured on standard FR-4 material.
3 Can be adjusted via the SPI.
4 tSAMPLE/28 is based on the number of bits multiplied by 2; delays are based on half duty cycles.
AD9259 Data Sheet
Rev. E | Page 8 of 52
TIMING DIAGRAMS
DCO–
DCO+
D – x
D + x
FCO–
FCO+
VIN ± x
CLK–
CLK+
MSB
N – 9
D12
N – 9
D11
N – 9
D10
N – 9
D9
N – 9
D8
N – 9
D7
N – 9
D6
N – 9
D5
N – 9
D4
N – 9
D3
N – 9
D2
N – 9
D0
N – 9
D1
N – 9
D12
N – 8
MSB
N – 8
N – 1
t
A
N
t
DATA
t
FRAME
t
FCO
t
PD
t
CPD
t
EH
t
EL
05965-039
Figure 2. 14-Bit Data Serial Stream, MSB First (Default)
DCO–
DCO+
D – x
D + x
FCO–
FCO+
V
IN ± x
CLK–
CLK+
MSB
N – 9
D10
N – 9
D9
N – 9
D8
N – 9
D7
N – 9
D6
N – 9
D5
N – 9
D4
N – 9
D3
N – 9
D2
N – 9
D1
N – 9
D0
N – 9
D10
N – 8
MSB
N – 8
N – 1
N
t
DATA
t
FRAME
t
FCO
t
PD
t
CPD
t
EH
t
A
t
EL
05965-040
Figure 3. 12-Bit Data Serial Stream, MSB First
Data Sheet AD9259
Rev. E | Page 9 of 52
05965-041
DCO–
DCO+
D – x
D + x
FCO–
FCO+
VIN ± x
CLK–
CLK+
LSB
N – 9
D0
N – 9
D1
N – 9
D2
N – 9
D3
N – 9
D4
N – 9
D5
N – 9
D6
N – 9
D7
N – 9
D8
N – 9
D9
N – 9
D10
N – 9
D11
N – 9
D12
N – 9
LSB
N – 8
D0
N – 8
N – 1
t
A
N
t
DATA
t
FRAME
t
FCO
t
PD
t
CPD
t
EH
t
EL
Figure 4. 14-Bit Data Serial Stream, LSB First
AD9259 Data Sheet
Rev. E | Page 10 of 52
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
ELECTRICAL
AVDD to AGND −0.3 V to +2.0 V
DRVDD to DRGND −0.3 V to +2.0 V
AGND to DRGND −0.3 V to +0.3 V
AVDD to DRVDD −2.0 V to +2.0 V
Digital Outputs1 to DRGND −0.3 V to +2.0 V
CLK+, CLK− to AGND −0.3 V to +3.9 V
VIN + x, VIN – x to AGND
−0.3 V to +2.0 V
SDIO/ODM to AGND −0.3 V to +2.0 V
PDWN, SCLK/DTP, CSB to AGND −0.3 V to +3.9 V
REFT, REFB, RBIAS to AGND −0.3 V to +2.0 V
VREF, SENSE to AGND −0.3 V to +2.0 V
ENVIRONMENTAL
Operating Temperature
Range (Ambient)
−40°C to +85°C
Maximum Junction
Temperature
150°C
Lead Temperature
(Soldering, 10 sec)
300°C
Storage Temperature
Range (Ambient)
−65°C to +150°C
1 Digital outputs include D + x, D − x, DCO+, DCO−, FCO+, FCO−.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL IMPEDANCE
Table 6.
Air Flow Velocity (m/sec) θJA1 θJB θJC Unit
0.0 24 °C/W
1.0 21 12.6 1.2 °C/W
2.5 19 °C/W
1 θJA for a 4-layer PCB with solid ground plane (simulated). Exposed pad
soldered to PCB.
ESD CAUTION
Data Sheet AD9259
Rev. E | Page 11 of 52
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VIN + A
VIN – A
AVDD
VIN + D
VIN – D
DRVDD
NOTES
1. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE
ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO
GROUND FOR PROPER OPERATIONAL.
DRGND
CLK+
CLK–
AVDD
DRVDD
DRGND
AVDD
AVDD
CSB
SCLK/DTP
SDIO/ODM
PDWN
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
D + A
D – A
D + B
D – B
D + C
D – C
D + D
D – D
DCO+
DCO–
FCO+
FCO–
VIN + B
VIN – B
VIN + C
VIN –
C
AVDD
REFT
REFB
VREF
SENSE
AVDD
AVDD
RBIAS
11
12
10
9
8
7
6
5
4
3
2
1
25
24
26
27
28
29
30
31
32
33
34
35
36
22
21
23
20
19
18
17
16
15
14
13
37
38
39
40
41
42
43
44
45
46
47
48
PIN 1
INDICATOR
EXPOSED PADDLE, PIN 0
(BOTTOM OF PACKAGE)
AD9259
TOP VIEW
05965-003
Figure 5.Pin Configuration
Table 7. Pin Function Descriptions
Pin No. Mnemonic Description
0 AGND Analog Ground (Exposed Paddle)
1, 2, 5, 6, 9, 10, 27, 32,
35, 36, 39, 45, 46
AVDD 1.8 V Analog Supply
11, 26 DRGND Digital Output Driver Ground
12, 25 DRVDD 1.8 V Digital Output Driver Supply
3 VIN − D ADC D Analog Input Complement
4 VIN + D ADC D Analog Input True
7 CLK− Input Clock Complement
8 CLK+ Input Clock True
13 D − D ADC D Digital Output Complement
14 D + D ADC D Digital Output True
15 D − C ADC C Digital Output Complement
16 D + C ADC C Digital Output True
17 D − B ADC B Digital Output Complement
18 D + B ADC B Digital Output True
19 D − A ADC A Digital Output Complement
20 D + A ADC A Digital Output True
21 FCO− Frame Clock Output Complement
22 FCO+ Frame Clock Output True
23 DCO− Data Clock Output Complement
24 DCO+ Data Clock Output True
28 SCLK/DTP Serial Clock/Digital Test Pattern
29 SDIO/ODM Serial Data I/O/Output Driver Mode
AD9259 Data Sheet
Rev. E | Page 12 of 52
Pin No. Mnemonic Description
30
CSB Chip Select Bar
31 PDWN Power-Down
33
VIN + A ADC A Analog Input True
34
VIN − A ADC A Analog Input Complement
37
VIN − B
ADC B Analog Input Complement
38
VIN + B ADC B Analog Input True
40
RBIAS External resistor sets the internal ADC core bias current
41
SENSE Reference Mode Selection
42
VREF Voltage Reference Input/Output
43
REFB Differential Reference (Negative)
44
REFT Differential Reference (Positive)
47
VIN + C ADC C Analog Input True
48
VIN − C ADC C Analog Input Complement
Data Sheet AD9259
Rev. E | Page 13 of 52
EQUIVALENT CIRCUITS
VIN ± x
05965-030
Figure 6. Equivalent Analog Input Circuit
10Ω
10kΩ
10kΩ
CLK– 10Ω
1.25V
CLK+
05965-032
Figure 7. Equivalent Clock Input Circuit
SDIO/ODM 350Ω
30kΩ
05965-035
Figure 8. Equivalent SDIO/ODM Input Circuit
DRVDD
DRGND
D– D+
V
V
V
V
05965-005
Figure 9. Equivalent Digital Output Circuit
SCLK/DTP
AND PDW N 30kΩ
1kΩ
05965-033
Figure 10. Equivalent SCLK/DTP and PDWN Input Circuit
100Ω
RBIAS
05965-031
Figure 11. Equivalent RBIAS Circuit
AD9259 Data Sheet
Rev. E | Page 14 of 52
CSB
70kΩ 1kΩ
AVDD
05965-034
Figure 12. Equivalent CSB Input Circuit
SENSE 1kΩ
05965-036
Figure 13. Equivalent SENSE Circuit
VREF
6kΩ
05965-037
Figure 14. Equivalent VREF Circuit
Data Sheet AD9259
Rev. E | Page 15 of 52
TYPICAL PERFORMANCE CHARACTERISTICS
010
515 20 25
0
–120
–80
–100
–60
–20
–40
AMPLITUDE (dBFS)
FREQUENCY (MHz)
AIN = –0.5d BFS
SNR = 73. 8dB
ENO B = 11.97 BI TS
SF DR = 83.4d Bc
05965-052
Figure 15. Single-Tone 32k FFT with fIN = 2.4 MHz, fSAMPLE = 50 MSPS
010515 20 25
0
–120
–80
–100
–60
–20
–40
AMPLITUDE (dBFS)
FREQUENCY (MHz)
AIN = –0.5d BFS
SNR = 72. 94dB
ENO B = 11.82 BI TS
SF DR = 78.60d Bc
05965-085
Figure 16. Single-Tone 32k FFT with fIN = 70 MHz, fSAMPLE = 50 MSPS
010515 20 25
0
–120
–80
–100
–60
–20
–40
AMPLITUDE (dBFS)
FREQUENCY (MHz)
AIN = –0.5d BFS
SNR = 71. 96dB
ENO B = 11.66 BI TS
SF DR = 76.68d Bc
05965-053
Figure 17. Single-Tone 32k FFT with fIN = 120 MHz, fSAMPLE = 50 MSPS
AMPLITUDE (dBFS)
–120
0
–20
–40
–60
–80
–100
0 5 10 15 20 25
FREQUENCY (MHz)
AIN = –0.5dBFS
SNR
=67.31dB
ENOB =10.89 BITS
SFDR =77.38dBc
05965-054
Figure 18. Single-Tone 32k FFT with fIN = 170 MHz, fSAMPLE = 50 MSPS
AMPLITUDE (dBFS)
–120
0
–20
–40
–60
–80
–100
0 5 10 15 20 25
FREQUENCY (MHz)
AIN = –0.5dBFS
SNR =66.87dB
ENOB =10.82 BITS
SFDR =74.97dBc
05965-051
Figure 19. Single-Tone 32k FFT with fIN = 190 MHz, fSAMPLE = 50 MSPS
AMPLITUDE (dBFS)
–120
0
–20
–40
–60
–80
–100
0 5 10 15 20 25
FREQUENCY (MHz)
AIN = –0.5dBFS
SNR =65.62dB
ENOB =10.61 BITS
SFDR =68.11dBc
05965-050
Figure 20. Single-Tone 32k FFT with fIN = 250 MHz, fSAMPLE = 50 MSPS
AD9259 Data Sheet
Rev. E | Page 16 of 52
10 252015 3530 4540 50
90
60
70
65
75
85
80
SNR/ S FDR (d B)
ENCODE (MSPS)
2V p-p, SNR
2V p-p, SFDR
05965-059
Figure 21. SNR/SFDR vs. Encode, fIN = 10.3 MHz, fSAMPLE = 50 MSPS
10 252015 3530 4540 50
90
60
70
65
75
85
80
SNR/ S FDR (d B)
ENCODE (MSPS)
2V p-p, SNR
2V p-p, SFDR
05965-060
Figure 22. SNR/SFDR vs. Encode, fIN = 35 MHz, fSAMPLE = 50 MSPS
SNR/ S FDR (d B)
ANALOG INPUT LEVEL (dBFS)
0
10
20
30
40
50
60
70
80
90
100
–60 –50 –40 –30 –20 –10 0
f
IN = 10.3MHz
f
SAMPLE = 50MSPS
2V p-p, SFDR
2V p-p, SNR
80dB
REFERENCE
05965-066
Figure 23. SNR/SFDR vs. Analog Input Level, fIN = 10.3 MHz, fSAMPLE = 50 MSPS
SNR/ S FDR (d B)
ANALOG INPUT LEVEL (dBFS)
0
10
20
30
40
50
60
70
80
90
100
–60 –50 –40 –30 –20 –10 0
f
IN = 35MHz
f
SAMPLE = 50MSPS
2V p-p, SFDR
2V p-p, SNR
80dB
REFERENCE
05965-065
Figure 24. SNR/SFDR vs. Analog Input Level, fIN = 35 MHz, fSAMPLE = 50 MSPS
AMPLITUDE (dBFS)
–120
0
–20
–40
–60
–80
–100
0 5 10 15 20 25
FREQUENCY (MHz)
AIN1 AND AIN2 = –
7dBFS
SFDR =87.76dBc
IMD2 = 90.18dBc
IMD3 = 87.27dBc
05965-056
Figure 25. Two-Tone 32k FFT with fIN1 = 15 MHz and fIN2 = 16 MHz,
fSAMPLE = 50 MSPS
AMPLITUDE (dBFS)
–120
0
–20
–40
–60
–80
–100
0 5 10 15 20 25
FREQUENCY (MHz)
AIN1 AND AIN2 = –7dBFS
SFDR =80.37dBc
IMD2 = 79.75dBc
IMD3 = 84.50dBc
05965-055
Figure 26. Two-Tone 32k FFT with fIN1 = 70 MHz and fIN2 = 71 MHz,
fSAMPLE = 50 MSPS
Data Sheet AD9259
Rev. E | Page 17 of 52
SNR/ S FDR (d B)
50
55
60
65
70
75
80
85
90
110 100 1000
ANALOG INPUT FRE QUENCY ( M Hz )
2V p-p, SFDR (dBc)
2V p-p, SNR (dB)
05965-071
Figure 27. SNR/SFDR vs. Analog Input Frequency, fSAMPLE = 50 MSPS
SI NAD/SF DR ( dB)
TEMPERATURE (°C)
–40 –20 806040200
60
65
70
75
80
85
90
2V p-p, SINAD
2V p-p, SFDR
05965-072
Figure 28. SINAD/SFDR vs. Temperature, fIN = 10.3 MHz, fSAMPLE = 50 MSPS
02000 4000 6000 8000 10000 12000 14000 16000
2.0
–2.0
–1.5
–1.0
0
–0.5
0.5
1.0
1.5
INL (LSB)
CODE
05965-073
Figure 29. INL, fIN = 2.4 MHz, fSAMPLE = 50 MSPS
02000 4000 6000 8000 10000 12000 14000 16000
0.5
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
DNL ( LSB)
CODE
05965-074
Figure 30. DNL, fIN = 2.4 MHz, fSAMPLE = 50 MSPS
–45.0
–46.0
–45.5
–46.5
–47.0
–47.5
–48.010 15 20 25 35 4530 40 50
CMRR (dB)
FREQUENCY (MHz)
05965-075
Figure 31. CMRR vs. Frequency, fSAMPLE = 50 MSPS
NUMBER OF HITS (Millions)
05965-086
0.2
0.4
0.6
0.8
1.0
1.2
0N – 3 N – 2 N + 3N + 2N + 1NN – 1 CODE
1.006 LSB rms
Figure 32. Input-Referred Noise Histogram, fSAMPLE = 50 MSPS
AD9259 Data Sheet
Rev. E | Page 18 of 52
AMPLITUDE (dBFS)
–120
0
–20
–40
–60
–80
–100
0 5 10 15 20 25
FREQUENCY (MHz)
NPR = 63. 89dB
NOTCH = 18. 0M Hz
NOTCH WIDT H = 3.0MHz
05965-076
Figure 33. Noise Power Ratio (NPR), fSAMPLE = 50 MSPS
FUNDAM E NTAL LEV E L (d B)
05965-077
–10
0
–3
–2
–1
–4
–5
–6
–7
–8
–9
050 100 150 200 250 300 350 400 450 500
FREQUENCY (MHz)
–3dB CUTOFF = 315M Hz
Figure 34. Full-Power Bandwidth vs. Frequency, fSAMPLE = 50 MSPS
Data Sheet AD9259
Rev. E | Page 19 of 52
THEORY OF OPERATION
The AD9259 architecture consists of a pipelined ADC divided into
three sections: a 4-bit first stage followed by eight 1.5-bit stages and
a final 3-bit flash. Each stage provides sufficient overlap to correct
for flash errors in the preceding stage. The quantized outputs from
each stage are combined into a final 14-bit result in the digital
correction logic. The pipelined architecture permits the first stage
to operate with a new input sample while the remaining stages
operate with preceding samples. Sampling occurs on the rising
edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched-capacitor DAC
and an interstage residue amplifier (for example, a multiplying
digital-to-analog converter (MDAC)). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction of
flash errors. The last stage simply consists of a flash ADC.
The output staging block aligns the data, corrects errors, and
passes the data to the output buffers. The data is then serialized
and aligned to the frame and data clocks.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9259 is a differential switched-
capacitor circuit designed for processing differential input
signals. This circuit can support a wide common-mode range
while maintaining excellent performance. By using an input
common-mode voltage of midsupply, users can minimize
signal-dependent errors and achieve optimum performance.
S S
H
C
PAR
C
SAMPLE
C
SAMPLE
C
PAR
VIN – x
H
S S
H
VIN + x
H
05965-006
Figure 35. Switched-Capacitor Input Circuit
The clock signal alternately switches the input circuit between
sample mode and hold mode (see Figure 35). When the input
circuit is switched to sample mode, the signal source must be
capable of charging the sample capacitors and settling within
one-half of a clock cycle. A small resistor in series with each
input can help reduce the peak transient current injected from
the output stage of the driving source. In addition, low-Q inductors
or ferrite beads can be placed on each leg of the input to reduce
high differential capacitance at the analog inputs and therefore
achieve the maximum bandwidth of the ADC. Such use of
low-Q inductors or ferrite beads is required when driving the
converter front end at high IF frequencies. Either a shunt
capacitor or two single-ended capacitors can be placed on the
inputs to provide a matching passive network. This ultimately
creates a low-pass filter at the input to limit unwanted
broadband noise. See the AN-742 Application Note, the AN-827
Application Note, and the Analog Dialogue article “Transformer-
Coupled Front-End for Wideband A/D Converters” (Volume
39, April 2005) for more information at www.analog.com. In
general, the precise values depend on the application.
The analog inputs of the AD9259 are not internally dc-biased.
Therefore, in ac-coupled applications, the user must provide
this bias externally. Setting the device so that VCM = AVDD/2 is
recommended for optimum performance, but the device can
function over a wider range with reasonable performance, as
shown in Figure 36 and Figure 37.
SNR/ S FDR (d B)
ANALOG INPUT COMMON-MODE VOLTAGE (V)
50
55
60
65
70
75
80
85
90
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
SFDR (dBc)
SNR (dB)
05965-078
f
IN
= 2.3M Hz
f
SAMPLE
= 50MSPS
Figure 36. SNR/SFDR vs. Common-Mode Voltage,
fIN = 2.3 MHz, fSAMPLE = 50 MSPS
SNR/ S FDR (d B)
ANALOG INPUT COMMON-MODE VOLTAGE (V)
50
55
60
65
70
75
80
85
90
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
SFDR (dBc)
SNR (
dB)
05965-079
fIN
= 30MHz
fSAMPLE
= 50MSPS
Figure 37. SNR/SFDR vs. Common-Mode Voltage,
fIN = 30 MHz, fSAMPLE = 50 MSPS
AD9259 Data Sheet
Rev. E | Page 20 of 52
For best dynamic performance, the source impedances driving
VIN + x and VIN − x should be matched such that common-
mode settling errors are symmetrical. These errors are reduced
by the common-mode rejection of the ADC. An internal
reference buffer creates the positive and negative reference
voltages, REFT and REFB, respectively, that define the span of
the ADC core. The output common-mode of the reference buffer
is set to midsupply, and the REFT and REFB voltages and span
are defined as
REFT = 1/2 (AVDD + VREF)
REFB = 1/2 (AVDD − VREF)
Span = 2 × (REFT − REFB) = 2 × VREF
It can be seen from these equations that the REFT and REFB
voltages are symmetrical about the midsupply voltage and, by
definition, the input span is twice the value of the VREF voltage.
Maximum SNR performance is achieved by setting the ADC to
the largest span in a differential configuration. In the case of the
AD9259, the largest input span available is 2 V p-p.
Differential Input Configurations
There are several ways to drive the AD9259 either actively or
passively; however, optimum performance is achieved by driving
the analog input differentially. For example, using the AD8332
differential driver to drive the AD9259 provides excellent perfor-
mance and a flexible interface to the ADC (see Figure 41) for
baseband applications. This configuration is commonly used
for medical ultrasound systems.
For applications where SNR is a key parameter, differential
transformer coupling is the recommended input configuration
(see Figure 38 and Figure 39), because the noise performance of
most amplifiers is not adequate to achieve the true performance
of the AD9259.
Regardless of the configuration, the value of the shunt capacitor,
C, is dependent on the input frequency and may need to be
reduced or removed.
2V p-p
R
R
1
C
DIFF
C
1
C
DIFF
IS OPTIONAL.
49.9Ω
0.1μF
1kΩ
1kΩ
AGND
AVDD
A
DT1-1WT
1:1 Z RATIO
VIN – x
ADC
AD9259
VIN + x
C
05965-008
Figure 38. Differential Transformer-Coupled Configuration
for Baseband Applications
ADC
AD9259
2V p-p
2.2pF 1kΩ
0.1μF
1kΩ
1kΩ
AVDD
A
DT1-1WT
1:1 Z RATIO
16nH 16nH
0.1μF
16nH
33Ω
33Ω
499Ω
65Ω
VIN + x
VIN – x
05965-047
Figure 39. Differential Transformer-Coupled Configuration
for IF Applications
Single-Ended Input Configuration
A single-ended input may provide adequate performance in cost-
sensitive applications. In this configuration, SFDR and distortion
performance degrade due to the large input common-mode swing.
If the application requires a single-ended input configuration,
ensure that the source impedances on each input are well matched
in order to achieve the best possible performance. A full-scale
input of 2 V p-p can be applied to the ADC’s VIN + x pin while
the VIN − x pin is terminated. Figure 40 details a typical single-
ended input configuration.
2
V p-p
R
R
49.9Ω0.1µF
0.1µF
AVDD
1kΩ25Ω
1kΩ
1kΩ
A
V
DD
VIN – x
ADC
AD9259
VIN + x
1
C
DIFF
C
C
05965-009
1
C
DIFF
IS OPTIONAL.
Figure 40. Single-Ended Input Configuration
AD8332
1kΩ
187Ω
187Ω
0.1μ
F
0.1μF
0.1μF
1V p-
p
0.1μF
LNA
120nH
VGA
VOH
VIP
INH
22pF
LMD
VIN
LOP
LON
VOL
18nF 274Ω
VIN – x
ADC
AD9259
VIN + x
05965-007
LPF
+
68pF
33Ω
33Ω
AVDD
AVDD
680nH
680nH
10kΩ
10kΩ
10kΩ
10kΩ
Figure 41. Differential Input Configuration Using the AD8332 with Two-Pole, 16 MHz Low-Pass Filter
Data Sheet AD9259
Rev. E | Page 21 of 52
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9259 sample clock inputs
(CLK+ and CLK−) should be clocked with a differential signal.
This signal is typically ac-coupled to the CLK+ and CLK− pins
via a transformer or capacitors. These pins are biased internally
and require no additional biasing.
Figure 42 shows a preferred method for clocking the AD9259. The
low jitter clock source is converted from a single-ended signal
to a differential signal using an RF transformer. The back-to-
back Schottky diodes across the secondary transformer limit
clock excursions into the AD9259 to approximately 0.8 V p-p
differential. This helps prevent the large voltage swings of the
clock from feeding through to other portions of the AD9259,
and it preserves the fast rise and fall times of the signal, which
are critical to low jitter performance.
0.1µF
0.1µF
0.1µF0.1µF
SCHOTTKY
DIODES:
HSM2812
CLK+
50Ω 100Ω
CLK–
CLK+
ADC
AD9259
Mini-Circuits®
ADT1-1WT, 1: 1Z
XFMR
05965-024
Figure 42. Transformer-Coupled Differential Clock
Another option is to ac-couple a differential PECL signal to the
sample clock input pins as shown in Figure 43. The AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515 of clock drivers
offers excellent jitter performance.
100Ω
0.1µF
0.1µF
0.1µF
0.1µF
240Ω240Ω
50Ω
1
50Ω
1
CLK
CLK
1
50Ω RESISTORS ARE OPTIONAL.
CLK–
CLK+
ADC
AD9259
05965-025
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
PECL DRIVER
CLK+
CLK–
Figure 43. Differential PECL Sample Clock
100Ω
0.1µF
0.1µF
0.1µF
0.1µF
50Ω*
LVDS DRIVER
50Ω
1
CLK
CLK
1
50Ω RESISTORS ARE OPTIONAL
CLK–
CLK+
ADC
AD9259
05965-026
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
CLK+
CLK–
Figure 44. Differential LVDS Sample Clock
In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
CLK+ should be driven directly from a CMOS gate, and the
CLK− pin should be bypassed to ground with a 0.1 μF capacitor
in parallel with a 39 kΩ resistor (see Figure 45). Although the
CLK+ input circuit supply is AVDD (1.8 V), this input is
designed to withstand input voltages of up to 3.3 V and
therefore offers several selections for the drive logic voltage.
0.1µF
0.1µF
0.1µF
39kΩ
CMOS DRIVER
50Ω1
OPTIONAL
100Ω
0.1µF CLK
CLK
150Ω RESISTOR IS OPTIONAL.
CLK–
CLK+
ADC
AD9259
05965-027
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
CLK+
Figure 45. Single-Ended 1.8 V CMOS Sample Clock
0.1µF
0.1µF
0.1µF
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
CMOS DRIVER
50Ω
1
OPTIONAL
100Ω
CLK
CLK
1
50Ω RESISTOR IS OPTIONAL.
0.1µF CLK–
CLK+
ADC
AD9259
05965-028
CLK+
Figure 46. Single-Ended 3.3 V CMOS Sample Clock
Clock Duty Cycle Considerations
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to the clock duty cycle. Commonly, a 5% tolerance is
required on the clock duty cycle to maintain dynamic performance
characteristics. The AD9259 contains a duty cycle stabilizer (DCS)
that retimes the nonsampling edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows a wide range
of clock input duty cycles without affecting the performance of
the AD9259. When the DCS is on, noise and distortion perfor-
mance are nearly flat for a wide range of duty cycles. However,
some applications may require the DCS function to be off. If so,
keep in mind that the dynamic range performance can be
affected when operated in this mode. See the Memory Map
section for more details on using this feature.
Jitter in the rising edge of the input is an important concern, and it
is not reduced by the internal stabilization circuit. The duty
cycle control loop does not function for clock rates of less than
20 MHz nominal. The loop has a time constant associated with
it that must be considered in applications where the clock rate
can change dynamically. This requires a wait time of 1.5 µs to
5 µs after a dynamic clock frequency increase (or decrease)
before the DCS loop is relocked to the input signal. During the
period that the loop is not locked, the DCS loop is bypassed and
the internal device timing is dependent on the duty cycle of the
input clock signal. In such applications, it may be appropriate to
disable the duty cycle stabilizer. In all other applications, enabling
the DCS circuit is recommended to maximize ac performance.
AD9259 Data Sheet
Rev. E | Page 22 of 52
Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency (fA)
due only to aperture jitter (tJ) can be calculated by
SNR Degradation = 20 × log 10(1/2 × π × fA × tJ)
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter. IF undersampling applications
are particularly sensitive to jitter (see Figure 47).
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9259.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators are
the best clock sources. If the clock is generated from another
type of source (by gating, dividing, or another method), it
should be retimed by the original clock during the last step.
Refer to the AN-501 Application Note and to the AN-756
Application Note for more in-depth information about jitter
performance as it relates to ADCs at www.analog.com.
110 100 1000
16 BITS
14 BITS
12 BITS
30
40
50
60
70
80
90
100
110
120
130
0.125ps
0.25ps
0.5ps
1.0ps
2.0ps
ANALOG INPUT FREQUENCY (MHz)
10 BITS
RMS CLOCK JIT TER REQUI RE M E NT
SNR (dB)
05965-038
Figure 47. Ideal SNR vs. Input Frequency and Jitter
Power Dissipation and Power-Down Mode
As shown in Figure 48, the power dissipated by the AD9259 is
proportional to its sample rate. The digital power dissipation
does not vary significantly because it is determined primarily by
the DRVDD supply and bias current of the LVDS output drivers.
10 2015 30 3525 5040 45
CURRENT ( mA)
ENCODE (MSPS)
250
300
350
450
500
400
0
20
40
100
140
120
200
180
160
60
80
POWER (mW)
DRVDD CURRENT
TOTAL POWER
AVDD CURRENT
05965-089
Figure 48. Supply Current vs. fSAMPLE for fIN = 10.3 MHz, fSAMPLE = 50 MSPS
Data Sheet AD9259
Rev. E | Page 23 of 52
By asserting the PDWN pin high, the AD9259 is placed into
power-down mode. In this state, the ADC typically dissipates
3 mW. During power-down, the LVDS output drivers are placed
into a high impedance state. If any of the SPI features are changed
before the power-down feature is enabled, the chip continues to
function after PDWN is pulled low without requiring a reset. The
AD9259 returns to normal operating mode when the PDWN pin
is pulled low. This pin is both 1.8 V and 3.3 V tolerant.
In power-down mode, low power dissipation is achieved by
shutting down the reference, reference buffer, PLL, and biasing
networks. The decoupling capacitors on REFT and REFB are
discharged when entering power-down mode and must be
recharged when returning to normal operation. As a result, the
wake-up time is related to the time spent in the power-down
mode: shorter cycles result in proportionally shorter wake-up
times. With the recommended 0.1 μF and 2.2 μF decoupling
capacitors on REFT and REFB, approximately 1 sec is required
to fully discharge the reference buffer decoupling capacitors and
approximately 375 μs is required to restore full operation.
There are several other power-down options available when
using the SPI. The user can individually power down each
channel or put the entire device into standby mode. The latter
option allows the user to keep the internal PLL powered when
fast wake-up times (~600 ns) are required. See the Memory
Map section for more details on using these features.
Digital Outputs and Timing
The AD9259 differential outputs conform to the ANSI-644 LVDS
standard on default power-up. This can be changed to a low power,
reduced signal option (similar to the IEEE 1596.3 standard) via the
SDIO/ODM pin or SPI. The LVDS standard can further reduce the
overall power dissipation of the device by approximately 17 mW.
See the SDIO/ODM Pin section or Table 16 in the Memory Map
section for more information. The LVDS driver current is derived
on-chip and sets the output current at each output equal to a
nominal 3.5 mA. A 100 Ω differential termination resistor
placed at the LVDS receiver inputs results in a nominal
350 mV swing at the receiver.
The AD9259 LVDS outputs facilitate interfacing with LVDS
receivers in custom ASICs and FPGAs for superior switching
performance in noisy environments. Single point-to-point net
topologies are recommended with a 100 Ω termination resistor
placed as close to the receiver as possible. If there is no far-end
receiver termination or there is poor differential trace routing,
timing errors may result. To avoid such timing errors, it is
recommended that the trace length be less than 24 inches and
that the differential output traces be close together and at equal
lengths. An example of the FCO and data stream with proper
trace length and position is shown in Figure 49.
CH1 500mV/DIV = DCO
CH2 500mV/DIV = DATA
CH3 500mV/DIV = FCO
2.5ns/DIV
05965-045
Figure 49. LVDS Output Timing Example in ANSI-644 Mode (Default)
An example of the LVDS output using the ANSI-644 standard
(default) data eye and a time interval error (TIE) jitter histogram
with trace lengths less than 24 inches on standard FR-4 material is
shown in Figure 50. Figure 51 shows an example of trace lengths
exceeding 24 inches on standard FR-4 material. Notice that the
TIE jitter histogram reflects the decrease of the data eye opening
as the edge deviates from the ideal position. It is the user’s respon-
sibility to determine if the waveforms meet the timing budget of
the design when the trace lengths exceed 24 inches. Additional SPI
options allow the user to further increase the internal termination
(increasing the current) of all four outputs to drive longer trace
lengths (see Figure 52). Even though this produces sharper rise
and fall times on the data edges and is less prone to bit errors, the
power dissipation of the DRVDD supply increases when this
option is used. In addition, notice in Figure 52 that the histogram
is improved compared with that shown in Figure 51. See the
Memory Map section for more details.
AD9259 Data Sheet
Rev. E | Page 24 of 52
100
50
0
–100ps 0ps 100ps
TIE JITTER HISTOGRAM (Hits)
500
–500
0
–1.0ns –0.5ns 0ns 0.5ns 1.0ns
EYE DIAGRAM VOLTAGE (V)
EYE: ALL BITS ULS: 10000/ 15600
05965-043
0
Figure 50. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
Less than 24 Inches on Standard FR-4, External 100 Ω Far Termination Only
200
–200
0
–1.0ns –0.5ns 0ns 0.5ns 1.0ns
EYE DIAGRAM VOLTAGE (V)
EYE: ALL BITS ULS: 9600/15600
100
50
0
–150ps –100ps –50ps 0ps 50ps 100ps 150ps
TIE JITTER HISTOGRAM (Hits)
05965-044
Figure 51. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
Greater than 24 Inches on Standard FR-4, External 100 Ω Far Termination Only
100
50
0
–150ps –100ps –50ps 0ps 50ps 100ps 150ps
TIE JITTER HISTOGRAM (Hits)
200
400
–200
–400
0
–1.0ns –0.5ns 0ns 0.5ns 1.0ns
EYE DIAGRAM VOLTAGE (V)
EYE: ALL BITS ULS: 9599/15599
05965-042
Figure 52. Data Eye for LVDS Outputs in ANSI-644 Mode with 100 Ω Internal
Termination on and Trace Lengths Greater than 24 Inches on Standard FR-4,
External 100 Ω Far Termination Only
The format of the output data is offset binary by default. An
example of the output coding format can be found in Table 8.
To change the output data format to twos complement, see the
Memory Map section.
Table 8. Digital Output Coding
Code
(VIN + x) − (VIN − x),
Input Span = 2 V p-p (V)
Digital Output Offset Binary
(D13 ... D0)
16383 +1.00 11 1111 1111 1111
8192 0.00 10 0000 0000 0000
8191 −0.000122 01 1111 1111 1111
0 −1.00 00 0000 0000 0000
Data from each ADC is serialized and provided on a separate
channel. The data rate for each serial stream is equal to 14 bits
times the sample clock rate, with a maximum of 700 Mbps
(14 bits × 50 MSPS = 700 Mbps). The lowest typical conversion
rate is 10 MSPS. However, if lower sample rates are required for
a specific application, the PLL can be set up via the SPI to allow
encode rates as low as 5 MSPS. See the Memory Map section for
details on enabling this feature.
Data Sheet AD9259
Rev. E | Page 25 of 52
Two output clocks are provided to assist in capturing data from
the AD9259. The DCO is used to clock the output data and is
equal to seven times the sample clock (CLK) rate. Data is
clocked out of the AD9259 and must be captured on the rising
and falling edges of the DCO that supports double data rate
(DDR) capturing. The FCO is used to signal the start of a new
output byte and is equal to the sample clock rate. See the timing
diagram shown in Figure 2 for more information.
Table 9. Flexible Output Test Modes
Output Test Mode
Bit Sequence Pattern Name Digital Output Word 1 Digital Output Word 2
Subject to Data
Format Select
0000 Off (default) N/A N/A N/A
0001 Midscale short 1000 0000 (8-bit)
10 0000 0000 (10-bit)
1000 0000 0000 (12-bit)
10 0000 0000 0000 (14-bit)
Same Yes
0010 +Full-scale short 1111 1111 (8-bit)
11 1111 1111 (10-bit)
1111 1111 1111 (12-bit)
11 1111 1111 1111 (14-bit)
Same Yes
0011
−Full-scale short
0000 0000 (8-bit)
00 0000 0000 (10-bit)
0000 0000 0000 (12-bit)
00 0000 0000 0000 (14-bit)
Same
Yes
0100 Checkerboard 1010 1010 (8-bit)
10 1010 1010 (10-bit)
1010 1010 1010 (12-bit)
10 1010 1010 1010 (14-bit)
0101 0101 (8-bit)
01 0101 0101 (10-bit)
0101 0101 0101 (12-bit)
01 0101 0101 0101 (14-bit)
No
0101 PN sequence long1 N/A N/A Yes
0110 PN sequence short1 N/A N/A Yes
0111 One-/zero-word toggle 1111 1111 (8-bit)
11 1111 1111 (10-bit)
1111 1111 1111 (12-bit)
11 1111 1111 1111 (14-bit)
0000 0000 (8-bit)
00 0000 0000 (10-bit)
0000 0000 0000 (12-bit)
00 0000 0000 0000 (14-bit)
No
1000 User input Register 0x19 to Register 0x1A Register 0x1B to Register 0x1C No
1001 1-/0-bit toggle 1010 1010 (8-bit)
10 1010 1010 (10-bit)
1010 1010 1010 (12-bit)
10 1010 1010 1010 (14-bit)
N/A No
1010 1× sync 0000 1111 (8-bit)
00 0001 1111 (10-bit)
0000 0011 1111 (12-bit)
00 0000 0111 1111 (14-bit)
N/A No
1011 One bit high 1000 0000 (8-bit)
10 0000 0000 (10-bit)
1000 0000 0000 (12-bit)
10 0000 0000 0000 (14-bit)
N/A No
1100 Mixed frequency 1010 0011 (8-bit)
10 0110 0011 (10-bit)
1010 0011 0011 (12-bit)
10 1000 0110 0111 (14-bit)
N/A No
1 All test mode options except PN sequence short and PN sequence long can support 8- to 14-bit word lengths in order to verify data capture to the receiver.
AD9259 Data Sheet
Rev. E | Page 26 of 52
When the SPI is used, the DCO phase can be adjusted in 60°
increments relative to the data edge. This enables the user to
refine system timing margins if required. The default DCO+
and DCO− timing, as shown in Figure 2, is 90° relative to the
output data edge.
An 8-, 10-, or 12-bit serial stream can also be initiated from the
SPI. This allows the user to implement and test compatibility with
lower resolution systems. When changing the resolution to an
8-, 10-, or 12-bit serial stream, the data stream is shortened. See
Figure 3 for a 12-bit example.
When the SPI is used, all of the data outputs can also be
inverted from their nominal state. This is not to be confused
with inverting the serial stream to an LSB-first mode. In default
mode, as shown in Figure 2, the MSB is first in the data output
serial stream. However, this can be inverted so that the LSB is
first in the data output serial stream (see Figure 4).
There are 12 digital output test pattern options available that
can be initiated through the SPI. This is a useful feature when
validating receiver capture and timing. Refer to Table 9 for the
output bit sequencing options available. Some test patterns have
two serial sequential words and can be alternated in various
ways, depending on the test pattern chosen. Note that some
patterns do not adhere to the data format select option. In
addition, custom user-defined test patterns can be assigned in
the 0x19, 0x1A, 0x1B, and 0x1C register addresses. All test mode
options except PN sequence short and PN sequence long can
support 8- to 14-bit word lengths to verify data capture to the
receiver.
The PN sequence short pattern produces a pseudorandom bit
sequence that repeats itself every 29 − 1 or 511 bits. A description
of the PN sequence and how it is generated can be found in
Section 5.1 of the ITU-T 0.150 (05/96) standard. The only
difference is that the starting value must be a specific value
instead of all 1s (see Table 10 for the initial values).
The PN sequence long pattern produces a pseudorandom bit
sequence that repeats itself every 223 − 1 or 8,388,607 bits. A
description of the PN sequence and how it is generated can be
found in Section 5.6 of the ITU-T 0.150 (05/96) standard. The
only differences are that the starting value must be a specific
value instead of all 1s (see Table 10 for the initial values) and the
AD9259 inverts the bit stream with relation to the ITU standard.
Table 10. PN Sequence
Sequence
Initial
Value
First Three Output Samples
(MSB First)
PN Sequence Short 0x0df 0x37e4, 0x3533, 0x0063
PN Sequence Long 0x26e028 0x191f, 0x35c2, 0x2359
Consult the Memory Map section for information on how
to change these additional digital output timing features
through the SPI.
SDIO/ODM Pin
The SDIO/ODM pin is for use in applications that do not require
SPI mode operation. This pin can enable a low power, reduced
signal option (similar to the IEEE 1596.3 reduced range link
output standard) if it and the CSB pin are tied to AVDD during
device power-up. This option should only be used when the
digital output trace lengths are less than 2 inches from the LVDS
receiver. When this option is used, the FCO, DCO, and outputs
function normally, but the LVDS signal swing of all channels is
reduced from 350 mV p-p to 200 mV p-p, allowing the user to
further reduce the power on the DRVDD supply.
For applications where this pin is not used, it should be tied low.
In this case, the device pin can be left open, and the 30 kΩ internal
pull-down resistor pulls this pin low. This pin is only 1.8 V tolerant.
If applications require this pin to be driven from a 3.3 V logic level,
insert a 1 kΩ resistor in series with this pin to limit the current.
Table 11. Output Driver Mode Pin Settings
Selected ODM ODM Voltage
Resulting
Output Standard
Resulting
FCO and DCO
Normal
Operation
10 kΩ to AGND ANSI-644
(default)
ANSI-644
(default)
ODM AVDD Low power,
reduced
signal option
Low power,
reduced
signal option
Data Sheet AD9259
Rev. E | Page 27 of 52
SCLK/DTP Pin
The SCLK/DTP pin is for use in applications that do not require
SPI mode operation. This pin can enable a single digital test
pattern if it and the CSB pin are held high during device power-
up. When SCLK/DTP is tied to AVDD, the ADC channel
outputs shift out the following pattern: 10 0000 0000 0000. The
FCO and DCO function normally while all channels shift out the
repeatable test pattern. This pattern allows the user to perform
timing alignment adjustments among the FCO, DCO, and output
data. For normal operation, this pin should be tied to AGND
through a 10 kΩ resistor. This pin is both 1.8 V and 3.3 V tolerant.
Table 12. Digital Test Pattern Pin Settings
Selected DTP DTP Voltage
Resulting
D + x and D − x
Resulting
FCO and DCO
Normal
Operation
10 kΩ to AGND
Normal
operation
Normal operation
DTP AVDD 10 0000 0000
0000
Normal operation
Additional and custom test patterns can also be observed when
commanded from the SPI port. Consult the Memory Map
section for information about the options available.
CSB Pin
The CSB pin should be tied to AVDD for applications that do
not require SPI mode operation. By tying CSB high, all SCLK
and SDIO information is ignored. This pin is both 1.8 V and
3.3 V tolerant.
RBIAS Pin
To set the internal core bias current of the ADC, place a resistor
(nominally equal to 10.0 kΩ) to ground at the RBIAS pin. The
resistor current is derived on-chip and sets the AVDD current of
the ADC to a nominal 185 mA at 50 MSPS. Therefore, it is
imperative that at least a 1% tolerance on this resistor be used to
achieve consistent performance.
Voltage Reference
A stable, accurate 0.5 V voltage reference is built into the
AD9259. This is gained up internally by a factor of 2, setting
VREF to 1.0 V, which results in a full-scale differential input span
of 2 V p-p. The VREF is set internally by default; however, the
VREF pin can be driven externally with a 1.0 V reference to
improve accuracy.
When applying the decoupling capacitors to the VREF, REFT,
and REFB pins, use ceramic low ESR capacitors. These capacitors
should be close to the ADC pins and on the same layer of the
PCB as the AD9259. The recommended capacitor values and
configurations for the AD9259 reference pin are shown in
Figure 53.
Table 13. Reference Settings
Selected Mode SENSE Voltage Resulting VREF (V)
Resulting
Differential
Span (V p-p)
External
Reference
AVDD N/A 2 × external
reference
Internal,
2 V p-p FSR
AGND to 0.2 V 1.0 2.0
AD9259 Data Sheet
Rev. E | Page 28 of 52
Internal Reference Operation
A comparator within the AD9259 detects the potential at the
SENSE pin and configures the reference. If SENSE is grounded,
the reference amplifier switch is connected to the internal
resistor divider (see Figure 53), setting VREF to 1 V.
The REFT and REFB pins establish the input span of the ADC
core from the reference configuration. The analog input full-
scale range of the ADC equals twice the voltage of the reference
pin for either an internal or an external reference configuration.
If the reference of the AD9259 is used to drive multiple
converters to improve gain matching, the loading of the refer-
ence by the other converters must be considered. Figure 55
depicts how the internal reference voltage is affected by loading.
1µF 0.1µF
VREF
SENSE
0.5V
REFT
0.1µF
0.1µF 2.2µF
0.1µF
REFB
SELECT
LOGIC
ADC
CORE +
VI N – x
VI N + x
05965-010
Figure 53. Internal Reference Configuration
1µF
1
0.1µF
1
VREF
SENSE
AVDD
0.5V
REFT
0.1µF
0.1µF 2.2µF
0.1µF
REFB
SELECT
LOGIC
ADC
CORE +
VIN – x
VIN + x
05965-046
EXTERNAL
REFERENCE
1
OPTIONAL.
Figure 54. External Reference Operation
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or to improve thermal drift
characteristics. Figure 56 shows the typical drift characteristics
of the internal reference in 1 V mode.
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. The external
reference is loaded with an equivalent 6 kΩ load. An internal
reference buffer generates the positive and negative full-scale
references, REFT and REFB, for the ADC core. Therefore, the
external reference must be limited to a nominal 1.0 V.
01.00.5 2.01.5 3.02.5 3.5
V
REF
ERRO R ( %)
CURRENT LOAD ( mA)
05965-083
–30
–5
–10
–15
–20
–25
5
0
Figure 55. VREF Accuracy vs. Load
0.02
–0.18
–40 806040200–20
TEMPERATURE (°C)
V
REF
ERRO R ( %)
0
–0.02
–0.04
–0.06
–0.08
–0.10
–0.12
–0.14
–0.16
05965-084
Figure 56. Typical VREF Drift
Data Sheet AD9259
Rev. E | Page 29 of 52
SERIAL PORT INTERFACE (SPI)
The AD9259 serial port interface allows the user to configure
the converter for specific functions or operations through a
structured register space provided in the ADC. This may
provide the user with additional flexibility and customization,
depending on the application. Addresses are accessed via the
serial port and can be written to or read from via the port. Memory
is organized into bytes that can be further divided into fields, as
documented in the Memory Map section. Detailed operational
information can be found in the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI at www.analog.com.
There are three pins that define the SPI: SCLK, SDIO, and CSB
(see Table 14). The SCLK pin is used to synchronize the read
and write data presented to the ADC. The SDIO pin is a dual-
purpose pin that allows data to be sent to and read from the
internal ADC memory map registers. The CSB pin is an active
low control that enables or disables the read and write cycles.
Table 14. Serial Port Pins
Pin
Function
SCLK Serial Clock. The serial shift clock input. SCLK is used to
synchronize serial interface reads and writes.
SDIO
Serial Data Input/Output. A dual-purpose pin. The typical
role for this pin is as an input or output, depending on
the instruction sent and the relative position in the
timing frame.
CSB
Chip Select Bar (Active Low). This control gates the read
and write cycles.
The falling edge of the CSB in conjunction with the rising edge of
the SCLK determines the start of the framing sequence. During an
instruction phase, a 16-bit instruction is transmitted, followed by
one or more data bytes, which is determined by Bit Field W0 and
Bit Field W1. An example of the serial timing and its definitions
can be found in Figure 58 and Table 15. During normal operation,
CSB is used to signal to the device that SPI commands are to be
received and processed. When CSB is brought low, the device
processes SCLK and SDIO to obtain instructions. Normally,
CSB remains low until the communication cycle is complete.
However, if connected to a slow device, CSB can be brought
high between bytes, allowing older microcontrollers enough
time to transfer data into shift registers. CSB can be stalled
when transferring one, two, or three bytes of data. When W0
and W1 are set to 11, the device enters streaming mode and
continues to process data, either reading or writing, until
CSB is taken high to end the communication cycle. This allows
complete memory transfers without requiring additional instruc-
tions. Regardless of the mode, if CSB is taken high in the middle
of a byte transfer, the SPI state machine is reset and the device
waits for a new instruction.
In addition to the operation modes, the SPI port configuration
influences how the AD9259 operates. For applications that do
not require a control port, the CSB line can be tied and held high.
This places the remainder of the SPI pins into their secondary
modes, as defined in the SDIO/ODM Pin and SCLK/DTP Pin
sections. CSB can also be tied low to enable 2-wire mode. When
CSB is tied low, SCLK and SDIO are the only pins required for
communication. Although the device is synchronized during
power-up, the user should ensure that the serial port remains
synchronized with the CSB line when using this mode. When
operating in 2-wire mode, it is recommended to use a 1-, 2-,
or 3-byte transfer exclusively. Without an active CSB line,
streaming mode can be entered but not exited.
In addition to word length, the instruction phase determines if
the serial frame is a read or write operation, allowing the serial
port to be used to both program the chip and read the contents
of the on-chip memory. If the instruction is a readback operation,
performing a readback causes the SDIO pin to change from an
input to an output at the appropriate point in the serial frame.
Data can be sent in MSB- or LSB-first mode. MSB-first mode
is the default at power-up and can be changed by adjusting the
configuration register. For more information about this and
other features, see the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI at www.analog.com.
HARDWARE INTERFACE
The pins described in Table 14 compose the physical interface
between the user’s programming device and the serial port of
the AD9259. The SCLK and CSB pins function as inputs when
using the SPI. The SDIO pin is bidirectional, functioning as an
input during write phases and as an output during readback.
If multiple SDIO pins share a common connection, care should
be taken to ensure that proper VOH levels are met. Assuming the
same load for each AD9259, Figure 57 shows the number of
SDIO pins that can be connected together and the resulting VOH
level. This interface is flexible enough to be controlled by either
serial PROMS or PIC microcontrollers, providing the user with
an alternative method, other than a full SPI controller, to
program the ADC (see the AN-812 Application Note).
AD9259 Data Sheet
Rev. E | Page 30 of 52
05965-093
NUMBER OF SDIO PINS CONNECTED TOGETHER
VOH (V)
1.715
1.720
1.725
1.730
1.735
1.740
1.745
1.750
1.755
1.760
1.765
1.770
1.775
1.780
1.785
1.790
1.795
1.800
0302010 40 50 60 70 80 90 100
Figure 57. SDIO Pin Loading
If the user chooses not to use the SPI, these dual-function pins
serve their secondary functions when the CSB is strapped to
AVDD during device power-up. See the Theory of Operation
section for details on which pin-strappable functions are
supported on the SPI pins.
For users who wish to operate the ADC without using the
SPI, remove any connections from the CSB, SCLK/DTP, and
SDIO/ODM pins. By disconnecting these pins from the control
bus, the ADC can function in its most basic operation. Each
of these pins has an internal termination that floats to its
respective level.
DON’T CARE
DON’T CAREDON’T CARE
DON’T CARE
SDIO
SCLK
CSB
t
S
t
DH
t
HI
t
CLK
t
LO
t
DS
t
H
R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0
05965-012
Figure 58. Serial Timing Details
Table 15. Serial Timing Definitions
Parameter Timing (Minimum, ns) Description
tDS 5 Setup time between the data and the rising edge of SCLK
tDH 2 Hold time between the data and the rising edge of SCLK
tCLK 40 Period of the clock
tS 5 Setup time between CSB and SCLK
tH 2 Hold time between CSB and SCLK
tHI 16 Minimum period that SCLK should be in a logic high state
tLO 16 Minimum period that SCLK should be in a logic low state
tEN_SDIO 10 Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK
falling edge (not shown in Figure 58)
tDIS_SDIO 10 Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK
rising edge (not shown in Figure 58)
Data Sheet AD9259
Rev. E | Page 31 of 52
MEMORY MAP
READING THE MEMORY MAP TABLE
Each row in the memory map register table (Table 16) has eight
address locations. The memory map is divided into three sections:
the chip configuration register map (Address 0x00 to Address 0x02),
the device index and transfer register map (Address 0x05 and
Address 0xFF), and the ADC functions register map (Address 0x08
to Address 0x22).
The leftmost column of the memory map indicates the register
address number, and the default value is shown in the second
rightmost column. The (MSB) Bit 7 column is the start of the
default hexadecimal value given. For example, Address 0x09, the
clock register, has a default value of 0x01, meaning that Bit 7 = 0,
Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and
Bit 0 = 1, or 0000 0001 in binary. This setting is the default for
the duty cycle stabilizer in the on condition. By writing a 0 to Bit 6
of this address followed by a 0x01 in Register 0xFF (transfer bit),
the duty cycle stabilizer turns off. It is important to follow each
writing sequence with a transfer bit to update the SPI registers. For
more information on this and other functions, consult the AN-877
Application Note, Interfacing to High Speed ADCs via SPI at
www.analog.com.
RESERVED LOCATIONS
Undefined memory locations should not be written to except
when writing the default values suggested in this data sheet.
Addresses that have values marked as 0 should be considered
reserved and have a 0 written into their registers during power-up.
DEFAULT VALUES
When the AD9259 comes out of a reset, critical registers are
preloaded with default values. These values are indicated in
Table 16, where an X refers to an undefined feature.
LOGIC LEVELS
An explanation of various registers follows: “Bit is set” is
synonymous with “bit is set to Logic 1” or “writing Logic 1 for
the bit.” Similarly, “clear a bit” is synonymous with “bit is set to
Logic 0” or “writing Logic 0 for the bit.”
AD9259 Data Sheet
Rev. E | Page 32 of 52
Table 16. Memory Map Register
Addr.
(Hex) Register Name
(MSB)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
(LSB)
Bit 0
Default
Value
(Hex)
Default Notes/
Comments
Chip Configuration Registers
00 chip_port_config 0
LSB first
1 = on
0 = off
(default)
Soft
reset
1 = on
0 = off
(default)
1 1
Soft
reset
1 = on
0 = off
(default)
LSB first
1 = on
0 = off
(default)
0 0x18
The nibbles
should be
mirrored so that
LSB- or MSB-first
mode is set cor-
rectly regardless
of shift mode.
01
chip_id
8-bit Chip ID Bits [7:0]
(AD9259 = 0x04), (default)
0x04
Default is unique
chip ID. This is a
read-only
register.
02 chip_grade X Child ID [6:4]
(identify device variants of Chip ID)
100 = 50 MSPS
X X X X Child ID used to
differentiate
graded devices.
This is a read-
only register.
Device Index and Transfer Registers
05 device_index_A X X Clock
channel
DCO
1 = on
0 = off
(default)
Clock
channel
FCO
1 = on
0 = off
(default)
Data
Channel
D
1 = on
(default)
0 = off
Data
Channel
C
1 = on
(default)
0 = off
Data
Channel
B
1 = on
(default)
0 = off
Data
Channel
A
1 = on
(default)
0 = off
0x0F Bits are set to
determine which
on-chip device
receives the next
write command.
FF device_update X X X X X X X SW
transfer
1 = on
0 = off
(default)
0x00 Synchronously
transfers data
from the master
shift register to
the slave.
ADC Functions
08 modes X X X X X
Internal power-down mode
000 = chip run (default)
001 = full power-down
010 = standby
011 = reset
0x00
Determines
various generic
modes of chip
operation.
09 clock X X X X X X X Duty
cycle
stabilizer
1 = on
(default)
0 = off
0x01 Turns the
internal duty
cycle stabilizer
on and off.
0D test_io User test mode
00 = off (default)
01 = on, single alternate
10 = on, single once
11 = on, alternate once
Reset PN
long gen
1 = on
0 = off
(default)
Reset
PN short
gen
1 = on
0 = off
(default)
Output test mode—see Table 9 in the
Digital Outputs and Timing section
0000 = off (default)
0001 = midscale short
0010 = +FS short
0011 = −FS short
0100 = checkerboard output
0101 = PN 23 sequence
0110 = PN 9 sequence
0111 = 1-/0-word toggle
1000 = user input
1001 = 1-/0-bit toggle
1010 = 1× sync
1011 = one bit high
1100 = mixed bit frequency
(format determined by output_mode)
0x00 When this reg-
ister is set, the
test data is placed
on the output
pins in place of
normal data.
Data Sheet AD9259
Rev. E | Page 33 of 52
Addr.
(Hex) Register Name
(MSB)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
(LSB)
Bit 0
Default
Value
(Hex)
Default Notes/
Comments
14 output_mode X 0 = LVDS
ANSI-644
(default)
1 = LVDS
low power
(IEEE
1596.3
similar)
X X X Output
invert
1 = on
0 = off
(default)
00 = offset binary
(default)
01 = twos
complement
0x00 Configures the
outputs and the
format of the
data.
15 output_adjust X X Output driver
termination
00 = none (default)
01 = 200 Ω
10 = 100 Ω
11 = 100 Ω
X X X X 0x00 Determines
LVDS or other
output properties.
Primarily func-
tions to set the
LVDS span and
common-mode
levels in place of
an external
resistor.
16 output_phase X X X X 0011 = output clock phase adjust
(0000 through 1010)
0000 = 0° relative to data edge
0001 = 60° relative to data edge
0010 = 120° relative to data edge
0011 = 180° relative to data edge (default)
0101 = 300° relative to data edge
0110 = 360° relative to data edge
1000 = 480° relative to data edge
1001 = 540° relative to data edge
1010 = 600° relative to data edge
1011 to 1111 = 660° relative to data edge
0x03 On devices that
utilize global
clock divide,
determines
which phase of
the divider
output is used to
supply the
output clock.
Internal latching
is unaffected.
19 user_patt1_lsb B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined
pattern, 1 LSB.
1A user_patt1_msb B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined
pattern, 1 MSB.
1B user_patt2_lsb B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined
pattern, 2 LSB.
1C user_patt2_msb B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined
pattern, 2 MSB.
21 serial_control LSB first
1 = on
0 = off
(default)
X X X <10
MSPS,
low
encode
rate
mode
1 = on
0 = off
(default)
000 = 14 bits (default, normal bit
stream)
001 = 8 bits
010 = 10 bits
011 = 12 bits
100 = 14 bits
0x00 Serial stream
control. Default
causes MSB first
and the native
bit stream
(global).
22 serial_ch_stat X X X X X X Channel
output
reset
1 = on
0 = off
(default)
Channel
power-
down
1 = on
0 = off
(default)
0x00 Used to power
down individual
sections of a
converter (local).
AD9259 Data Sheet
Rev. E | Page 34 of 52
Power and Ground Recommendations
When connecting power to the AD9259, it is recommended
that two separate 1.8 V supplies be used: one for analog (AVDD)
and one for digital (DRVDD). If only one supply is available, it
should be routed to the AVDD first and then tapped off and
isolated with a ferrite bead or a filter choke preceded by
decoupling capacitors for the DRVDD. The user can employ
several different decoupling capacitors to cover both high and
low frequencies. These should be located close to the point of
entry at the PC board level and close to the parts, with minimal
trace lengths.
A single PC board ground plane should be sufficient when
using the AD9259. With proper decoupling and smart parti-
tioning of the PC board’s analog, digital, and clock sections,
optimum performance can be easily achieved.
Exposed Paddle Thermal Heat Slug Recommendations
It is required that the exposed paddle on the underside of the
ADC be connected to analog ground (AGND) to achieve the
best electrical and thermal performance of the AD9259. An
exposed continuous copper plane on the PCB should mate to
the AD9259 exposed paddle, Pin 0. The copper plane should
have several vias to achieve the lowest possible resistive thermal
path for heat dissipation to flow through the bottom of the PCB.
These vias should be solder-filled or plugged.
To maximize the coverage and adhesion between the ADC and
PCB, partition the continuous copper plane by overlaying a
silkscreen on the PCB into several uniform sections. This provides
several tie points between the ADC and PCB during the reflow
process, whereas using one continuous plane with no partitions
only guarantees one tie point. See Figure 59 for a PCB layout
example. For detailed information on packaging and the PCB
layout of chip scale packages, see the AN-772 Application Note,
A Design and Manufacturing Guide for the Lead Frame Chip
Scale Package (LFCSP) at www.analog.com.
SILKSCREEN PARTITION
PIN 1 INDI CATOR
05965-013
Figure 59. Typical PCB Layout
Data Sheet AD9259
Rev. E | Page 35 of 52
EVALUATION BOARD
The AD9259 evaluation board provides all of the support cir-
cuitry required to operate the ADC in its various modes and
configurations. The converter can be driven differentially using a
transformer (default) or a AD8332 driver. The ADC can also be
driven in a single-ended fashion. Separate power pins are provided
to isolate the DUT from the drive circuitry of the AD8332. Each
input configuration can be selected by changing the connection
of various jumpers (see Figure 62 to Figure 66). Figure 60 shows
the typical bench characterization setup used to evaluate the ac
performance of the AD9259. It is critical that the signal sources
used for the analog input and clock have very low phase noise
(<1 ps rms jitter) to realize the optimum performance of the
converter. Proper filtering of the analog input signal to remove
harmonics and lower the integrated or broadband noise at the
input is also necessary to achieve the specified noise performance.
See Figure 62 to Figure 70 for the complete schematics and
layout diagrams demonstrating the routing and grounding
techniques that should be applied at the system level.
POWER SUPPLIES
This evaluation board has a wall-mountable switching power
supply that provides a 6 V, 2 A maximum output. Connect the
supply to the rated 100 V ac to 240 V ac wall outlet at 47 Hz to
63 Hz. The other end of the supply is a 2.1 mm inner diameter
jack that connects to the PCB at P503. Once on the PC board,
the 6 V supply is fused and conditioned before connecting to
three low dropout linear regulators that supply the proper bias
to each of the various sections on the board.
When operating the evaluation board in a nondefault condition,
L504 to L507 can be removed to disconnect the switching
power supply. This enables the user to bias each section of the
board individually. Use P501 to connect a different supply for
each section. At least one 1.8 V supply is needed for AVDD_DUT
and DRVDD_DUT; however, it is recommended that separate
supplies be used for analog and digital signals and that each
supply have a current capability of 1 A. To operate the evaluation
board using the VGA option, a separate 5.0 V analog supply
(AVDD_5 V) is needed. To operate the evaluation board using
the SPI and alternate clock options, a separate 3.3 V analog
supply (AVDD_3.3 V) is needed in addition to the other
supplies.
INPUT SIGNALS
When connecting the clock and analog source to the evaluation
board, use clean signal generators with low phase noise, such as
Rohde & Schwarz SMA or HP8644 signal generators or the
equivalent, as well as a 1 m, shielded, RG-58, 50 Ω coaxial cable.
Enter the desired frequency and amplitude from the ADC speci-
fications tables. Typically, most Analog Devices, Inc., evaluation
boards can accept approximately 2.8 V p-p or 13 dBm sine wave
input for the clock. When connecting the analog input source, it
is recommended to use a multipole, narrow-band, band-pass
filter with 50 Ω terminations. Good choices of such band-pass
filters are available from TTE, Allen Avionics, and K&L
Microwave, Inc. The filter should be connected directly to the
evaluation board if possible.
OUTPUT SIGNALS
The default setup uses the Analog Devices HSC-ADC-FIFO5-
INTZ to interface with the Analog Devices standard dual-
channel FIFO data capture board (HCS-ADC-EVALCZ). Two
of the eight channels can be evaluated at the same time. For
more information on the channel settings and optional settings
of these boards, visit www.analog.com/FIFO.
ROHDE & S CHWARZ,
SMA,
2V p-p SIGNAL
SYNTHESIZER
ROHDE & S CHWARZ,
SMA,
2V p-p SIGNAL
SYNTHESIZER
BAND-PASS
FILTER XFMR
INPUT
CLK
CH A TO CH D
14-BIT
SERIAL
LVDS
USB
CONNECTION
AD9259
EVALUAT ION BOARD
HSC-ADC-EVALCZ
FIFO DATA
CAPTURE
BOARD
PC
RUNNING
ADC
ANALYZER
AND SPI
USER
SOFTWARE
1.8V – +– +
AVDD_DUT
AVDD_3.3V
DRVDD_DUT
GND
GND
– +
5.0V
GND
AVDD_5V
1.8V
6V DC
2A MAX
WALL OUTLET
100V TO 240V AC
47Hz TO 63Hz
SWITCHING
POWER
SUPPLY
– +
GND
3.3V – +
VCC
GND
3.3V
SPI SPISPI
05965-014
INTERPOSER
BOARD
SPI
Figure 60. Evaluation Board Connection
AD9259 Data Sheet
Rev. E | Page 36 of 52
DEFAULT OPERATION AND JUMPER SELECTION
SETTINGS
The following is a list of the default and optional settings or
modes allowed on the AD9259 Rev. A evaluation board.
POWER: Connect the switching power supply that is
provided in the evaluation kit between a rated 100 V ac to
240 V ac wall outlet at 47 Hz to 63 Hz and P503.
AIN: The evaluation board is set up for a transformer-
coupled analog input with an optimum 50 Ω impedance
match of 200 MHz of bandwidth (see Figure 61). For more
bandwidth response, the differential capacitor across the
analog inputs can be changed or removed. The common
mode of the analog inputs is developed from the center
tap of the transformer or AVDD_DUT/2.
0
AMPLITUDE (dBFS)
FREQUENCY (MHz)
05965-088
0
–16
–14
–12
–10
–8
–6
–4
–2
50 100 150 200 250 300 350 400 450 500
–3dB CUTOFF = 200MHz
Figure 61. Evaluation Board Full-Power Bandwidth
VREF: VREF is set to 1.0 V by tying the SENSE pin to
ground, R237. This causes the ADC to operate in 2.0 V p-p
full-scale range. A separate external reference option using
the ADR510 is also included on the evaluation board.
Populate R231 and R235 and remove C214. Proper use of the
VREF options is noted in the Voltage Reference section.
RBIAS: RBIAS has a default setting of 10 kΩ (R201) to
ground and is used to set the ADC core bias current.
CLOCK: The default clock input circuitry is derived from a
simple transformer-coupled circuit using a high bandwidth
1:1 impedance ratio transformer (T201) that adds a very
low amount of jitter to the clock path. The clock input is
50 Ω terminated and ac-coupled to handle single-ended
sine wave types of inputs. The transformer converts the
single-ended input to a differential signal that is clipped
before entering the ADC clock inputs.
A differential LVPECL clock can also be used to clock the
ADC input using the AD9515 (U202). Populate R225 and
R227 with 0 Ω resistors and remove R217 and R218 to
disconnect the default clock path inputs. In addition, populate
C207 and C208 with a 0.1 μF capacitor and remove C210 and
C211 to disconnect the default clock path outputs. The
AD9515 has many pin-strappable options that are set to a
default mode of operation. Consult the AD9515 data sheet
for more information about these and other options.
In addition, an on-board oscillator is available on the OSC201
and can act as the primary clock source. The setup is quick
and involves installing R212 with a 0 Ω resistor and setting
the enable jumper (J205) to the on position. If the user wishes
to employ a different oscillator, two oscillator footprint options
are available (OSC201) to check the ADC performance.
PDWN: To enable the power-down feature, short J201 to
AVDD on t he PDWN pin.
SCLK/DTP: To enable the digital test pattern on the digital
outputs of the ADC, use J204. If J204 is tied to AVDD during
device power-up, Test Pattern 10 0000 0000 0000 is enabled.
See the SCLK/DTP Pin section for details.
SDIO/ODM: To enable the low power, reduced signal option
(similar to the IEEE 1595.3 reduced range link LVDS output
standard), use J203. If J203 is tied to AVDD during device
power-up, it enables the LVDS outputs in a low power,
reduced signal option from the default ANSI-644 standard.
This option changes the signal swing from 350 mV p-p to
200 mV p-p, reducing the power of the DRVDD supply. See
the SDIO/ODM Pin section for more details.
CSB: To enable processing of the SPI information on the
SDIO and SCLK pins, tie J202 low in the always enable
mode. To ignore the SDIO and SCLK information, tie J202
to AVDD.
Non-SPI Mode: For users who wish to operate the DUT
without using SPI, remove Jumpers J202, J203, and J204.
This disconnects the CSB, SCLK/DTP, and SDIO/ODM
pins from the control bus, allowing the DUT to operate in its
simplest mode. Each of these pins has internal termination
and will float to its respective level.
D + x, D − x: If an alternative data capture method to the setup
shown in Figure 60 is used, optional receiver terminations,
R206 to R211, can be installed next to the high speed back-
plane connector.
Data Sheet AD9259
Rev. E | Page 37 of 52
ALTERNATIVE ANALOG INPUT DRIVE
CONFIGURATION
The following is a brief description of the alternative analog input
drive configuration using the AD8332 dual VGA. If this drive
option is in use, some components may need to be populated, in
which case all the necessary components are listed in Table 17. For
more details on the AD8332 dual VGA, including how it works
and its optional pin settings, consult the AD8332 data sheet.
To configure the analog input to drive the VGA instead of the
default transformer option, the following components need to
be removed and/or changed.
• Remove R102, R115, R128, R141, R161, R162, R163, R164,
T101, T102, T103, and T104 in the default analog input path.
• Populate R101, R114, R127, and R140 with 0 Ω resistors in
the analog input path.
• Populate R105, R113, R118, R124, R131, R137, R151, and
R160 with 0 Ω resistors in the analog input path to connect
the AD8332.
• Populate R152, R153, R154, R155, R156, R157, R158, R159,
C103, C105, C110, C112, C117, C119, C124, and C126
with 10 kΩ resistors to provide an input common-mode
level to the ADC analog inputs.
• Remove R305, R306, R313, R314, R405, R406, R412, and
R424 to configure the AD8332.
In this configuration, L301 to L308 and L401 to L408 are
populated with 0 Ω resistors to allow signal connection and
use of a filter if additional requirements are necessary.
AD9259 Data Sheet
Rev. E | Page 38 of 52
CHANNEL A
P101
AIN
AIN
VG A INPUT CONNECTION
VG A INPUT CONNECTION
VG A INPUT CONNECTION
VG A INPUT CONNECTION
1
2
3
6
5
4
T101
CM1
CM1 FB103
10Ω
FB102
10Ω
FB101
10Ω
C104
2.2pF
VIN_A
VIN_A
P102
DNP
CM1
INH1
CH_A
AVDD_DUT
CH_A
R104
0Ω
AVDD_DUT
AVDD_DUT
C106
DNP
C107
0.1µF
C103
DNP
C105
DNP
C101
0.1µF
C102
0.1µF
E101
R161
499Ω
R152
DNP
R113
DNP
R105
DNP
R110
33Ω
R107
DNP
R106
DNP
R112
1kΩ
R111
1kΩ
R108
33Ω
R101
DNP
R102
64.9Ω
R103
0Ω
R109
1kΩ
CHANNEL B
P103
AIN
1
2
3
6
5
4
T102
CM2
CM2 FB106
10Ω
FB105
10Ω
FB104
10Ω
C111
2.2pF
VIN_B
VIN_B
P104
DNP CM2
INH2 CH_B
AVDD_DUT
CH_B
R116
0Ω
AVDD_DUT
AVDD_DUT
C113
DNP
C114
0.1µF
C110
DNP
C112
DNP
C108
0.1µF
C109
0.1µF
E102
R162
499Ω
R153
DNP
R124
DNP
R118
DNP
R122
33Ω
R120
DNP
R119
DNP
R126
1kΩ
R125
1kΩ
R121
33Ω
R114
DNP
R115
64.9Ω
R117
0Ω
R123
1kΩ
CHANNEL C
P105
AIN
1
2
3
6
5
4
T103
CM3
CM3 FB109
10Ω
FB108
10Ω
FB107
10Ω
C118
2.2pF
VIN_C
VIN_C
P106
DNP
CM3
INH3
CH_C
AVDD_DUT
CH_C
R130
0Ω
AVDD_DUT
AVDD_DUT
C120
DNP
C121
0.1µF
C117
DNP
C119
DNP
C115
0.1µF
C116
0.1µF
E103
R163
499Ω
R154
DNP
R137
DNP
R131
DNP
R136
33Ω
R133
DNP
R132
DNP
R139
1kΩ
R138
1kΩ
R134
33Ω
R127
DNP
R128
64.9Ω
R129
0Ω
R135
1kΩ
CHANNEL D
P107
AIN
1
2
3
6
5
4
T104
CM4
CM4 FB112
10Ω
FB111
10Ω
R143
0Ω
C125
2.2pF
VIN_D
VIN_D
P108
DNP CM4
INH4 CH_D
AVDD_DUT
CH_D
FB110
10Ω
AVDD_DUT
AVDD_DUT
C127
DNP
C128
0.1µF
C124
DNP
C126
DNP R159
DNP
C122
0.1µF
C123
0.1µF
E104
R164
499Ω
R155
DNP
R160
DNP
R151
DNP
R147
33Ω
R145
DNP
R144
DNP
R150
1kΩ
R149
1kΩ
R146
33Ω
R140
DNP
R141
64.9Ω
R142
0Ω
R148
1kΩ
R156
DNP
R157
DNP
AIN
AIN
AIN
R158
DNP
DNP: DO NOT POPUL ATE
05965-015
Figure 62. Evaluation Board Schematic, DUT Analog Inputs
Data Sheet AD9259
Rev. E | Page 39 of 52
CSB
C217
0.1µF
C220
0.1µF
C221
0.1µF
C218
0.1µF
C219
0.1µF
C223
0.1µF
C222
0.1µF
AVDD_3.3V
CLK
CLKB
GND
GND_PAD
OUT0
OUT0B
OUT1
OUT1B
RSET
S0
S1
S10
S2
S3
S4
S5
S6
S7
S8
S9
SYNCB
VREF
VS
SIGNAL = DNC;27,28
INPUT
ENCODE
ENC
ENC
DNP
CLOCK CIRCUIT
OPTIONAL CLOCK DRIVE CIRCUIT
DISABLE
ENABLE
OPTIONAL CLOCK
OSCILLATOR
C224
0.1µF R214
10kΩ
R215
10kΩ
14
78
1
3
5
12
10
OSC201
VFAC3H-L
C207
0.1µF
DNP
C208
0.1µF
DNP
C209
0.1µF
DNP
C215
0.1µF
DNP
C211
0.1µF
C210
0.1µF
E202
1
E201
P201
P203
AVDD_3.3V
12
6
7
25
8
16
9
15
10
14
11
13
18
19
23
22
32
1
31
33
U202
SIGNAL = AVDD_3.3V; 4,
17,20, 21, 24, 26, 29, 30
AD9515
3
2
1
CR201
HSMS2812
R220
DNP
R240
243Ω
R243
100Ω
R241
243Ω
R242
100Ω
6
5
43
2
1
T201
1
2J205
C205
0.1µF
C216
0.1µF
R213
49.9kΩ
R216
0Ω
R221
10kΩ
R212
0Ω
DNP
R219
DNP
S0S1S2S3S4S5S6S7S8S9S10
OPT_CLK
OPT_CLK
CLK
AVDD_3.3V
OPT_CLK
OPT_CLK
CLK
CLK
LVPECL OUTPUT
LVDS OUTPUT
CLK
AVDD_3.3V
1
1
E203
AVDD_3.3V
VCC
GNDOUT
OE
OE'
GND'
VCC'
OUT'
R244
DNP
R245
0Ω
S4
S0
S5
S3
S2
S1
AVDD_3.3V
AVDD_3.3V
AVDD_3.3V
AVDD_3.3V
AVDD_3.3V
AVDD_3.3V
R246
DNP
R247
0Ω
R248
DNP
R249
0Ω
R250
DNP
R251
0Ω
R252
DNP
R253
0Ω
R254
DNP
R255
0Ω
R256
DNP
R257
0Ω
S10
S6
S9
S8
S7
AVDD_3.3V
AVDD_3.3V
AVDD_3.3V
AVDD_3.3V
AVDD_3.3V
R258
DNP
R259
0Ω
R260
DNP
R261
0Ω
R262
DNP
R263
0Ω
R264
DNP
R265
0Ω
A1
A2
A3
A4
A5
A6
A7
A8
A9
GNDAB1
GNDAB10
GNDAB2
GNDAB3
GNDAB4
GNDAB5
GNDAB6
GNDAB7
GNDAB8
GNDAB9
GNDCD1
GNDCD10
GNDCD2
GNDCD3
GNDCD4
GNDCD5
GNDCD6
GNDCD7
GNDCD8
GNDCD9
HEADER 6469169-1
R205 TO R211
OPTIONAL OUTPUT
TERMINATIONS
DIGITAL OUTPUTS
CSB3__CHB
SDI_CHB
SDO_CHA
CSB2_CHA
CSB1_CHA
SDI_CHA
SCLK_CHA
R206
DNP
R211
DNP
R210
DNP
R209
DNP
R208
DNP
P202
R207
DNP
SCLK_CHB
DCO
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
C10
50
49
48
47
46
45
44
43
42
41
20
19
18
17
16
15
14
13
12
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1 11
CHD
CHC
CHB
CHA
FCO
DCO
CHD
CHC
CHB
CHA
FCO
SDO_CHB
CSB4_CHB
40
60
1
9
21
22
4
5
25
6
26
8
31
32
33
34
35
36
37
38
29
10
30
2
23
3
24
28
51
52
53
54
55
56
57
58
39
59
7
27
ODM ENABLE
CLK
AVDD
CLK+
CLK–
D + A
D + B
D + C
D + D
D – A
D – B
D – C
D – D
DCO+
DCO–
DRVDD
DRGND
FCO+
FCO–
PDWN
RBIAS
REFB
REFT
SCLK/DTP
SDIO/ODM
SENSE
VIN + A
VIN + B
VIN + C
VIN + D
VIN – A
VIN – B
VIN – C
VIN – D
VREF
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
DRGND
DRVDD
REFERENCE
DECOUPLING
C204
0.1µF
C203
0.1µF
C202
2.2µF
C201
0.1µF
R205
10kΩ
R203
100kΩ
R204
100kΩ
3
2
1J201
1
8
730
20
18
16
14
19
17
15
13
24
23
11
12
22
21
10
2
25
26
27
32
35
36
39
45
46
5
6
9
31
40
43
44
28
29
41
33
38
47
4
34
37
48
3
42
U201
AD9259 LFCSP
R202
100kΩ
CSB_DUT
1
2
3
J202
SDIO_ODM
1
2
3
J203
SCLK_DTP
3
2
1J204
DRVDD_DUTDRVDD_DUT
R201
10kΩ
AVDD_DUT
CHA
CHB
CHC
CHD
CHA
CHB
CHC
DCO
DCO
FCO
FCO
AVDD_DUT
AVDD_DUT
AVDD_DUT
AVDD_DUT
AVDD_DUT
VSENSE_DUT
VIN_A
VIN_B
VIN_C
VIN_A
VIN_B
VREF_DUT
AVDD_DUT
AVDD_DUT
CLK
CHD
AVDD_DUT
AVDD_DUT
AVDD_DUT
AVDD_DUT
AVDD_DUT
VIN_D
VIN_C
VIN_D
GND
GND
AVDD_DUT
PWDN ENABLE
ALWAYS ENABLE SPI
DTP ENABLE
U203
CW
VREF = 1V
VREF = EXTERNAL
VREF = 0.5V
REMOVE C214 WHEN USING EXTERNAL VREF
VREF = 0.5V(1+R232/R233)
VREF SELECT
REFERENCE CIRCUIT
C212
0.1µF
R229
4.99kΩ
C214
1µF
C213
0.1µF
R230
10kΩ
R231
DNP
DNP
VSENSE_DUT
R228
470kΩDNP
DNP
R234
DNP
R235
DNP
R236
DNP
R237
0Ω
DNP
AVDD_DUT
VREF_DUT
AVDD_DUT
TRIM/NC
V–
V+
ADR510
1V
R232
DNP
R233
DNP
R217
0Ω
R218
0Ω
R225
0Ω
DNP
R226
49.9Ω
DNP
R227
0Ω
DNPR238
DNP
R239
10kΩ
C206
0.1µF
R223
0Ω
R224
0Ω
R222
4.12kΩ
2
3
5
NC = NO CONNECT
R266
100kΩ - DNP
R267
100kΩ - DNP
CLIP SINE OUT (DEFAULT)
DNP: DO NOT POPULATE
OPTIONAL
EXT REF
05965-016
Figure 63. Evaluation Board Schematic, DUT, VREF, Clock Inputs, and Digital Output Interface
AD9259 Data Sheet
Rev. E | Page 40 of 52
CW
PO WER DO WN ENABLE
(0V TO 1V = DISABLE POWER)
EXTERNAL V ARIABL E GAIN DRIVE
VARI ABLE G AIN CI RCUIT
(0V TO 1.0V DC)
R319
10kΩ
1 2
JP301
GND
VG
R320
39kΩ
VG
AVDD_5V
HILO PIN
HI GAIN RANGE = 2.25V T O 5. 0V
LO GAIN RANG E = 0V TO 1.0V
R315
10kΩ
L310
120nH
C322
0.018µF
C317
0.018µF
R316
274ΩR317
274Ω
C312
0.1µF
C325
0.1µF
C313
0.1µF
C314
0.1µF
L309
120nH
C318
22pF
C321
0.1µF
C320
0.1µF
C316
0.1µF R318
10kΩ
C323
22pF
C319
0.1µF C324
0.1µF
INH4 INH3
AVDD_5V
AVDD_5V
C326
10µF
C315
10µF
OP TIONAL V GA DRIV E CIRCUI T F OR CHANNEL C AND CHANNE L D
C311
0.1µF
R312
10kΩ
R313
10kΩ
DNP
C303
DNP
L304
0Ω
R303
DNP
L308
0Ω
24
17
20
23
18
22
19
21
R304
DNP
L306
0Ω
L305
0Ω
L302
0ΩL303
0Ω
L307
0Ω
C308
0.1µF
C307
0.1µF
C306
0.1µF
C305
0.1µF
R310
187Ω
R309
187Ω
R308
187Ω
R307
187Ω
C302
DNP
L301
0Ω
C301
DNP
R305
374Ω
R306
374Ω
CH_C
CH_D
CH_D
CH_C
AVDD_5V
AVDD_5V
AVDD_5V
C304
DNP
R301
DNPR302
DNP
31 10
26
25
14
27
3
6
4
5
1
8
32 9
15
16 VG
28 13
29 12
30 11
2
7
COM1 COM2
ENBL
ENBVGAIN
HILO
INH1
INH2
LMD1
LMD2
LON1
LON2
LOP1 LOP2
MODE
NC
RCLMP
VCM1 VCM2
VIN1 VIN2
VIP1 VIP2
VOH1
VOH2
VOL1
VOL2
VPS1
VPS2
VPSV
AD8332
COMM
COMM
R311
10kΩ
DNP
R314
10kΩ
DNP
C310
0.1µF
C309
1000pF
RCLAM P P IN
HILO PIN = LO = ±50mV
HILO P IN = H = ±75mV
MODE PIN
POSITIVE GAIN SLOPE = 0V TO 1.0V
NEGATIVE GAIN SLOPE = 2.25V TO 5.0V
U301
POPULATE L301 TO L308 WITH
0ΩRESISTORS OR DESIGN
YOUR OWN FILTER.
DNP: DO NOT POPUL ATE
05965-017
Figure 64. Evaluation Board Schematic, Optional DUT Analog Input Drive and SPI Interface Circuit
Data Sheet AD9259
Rev. E | Page 41 of 52
MODE PIN
POSITIVE GAIN SLOPE = 0V TO 1.0V
NEGATIV E GAI N S LOP E = 2.25V-5.0V
HILO PIN
HI G AIN RANGE = 2.25V- 5.0V
LO GAIN RANGE = 0V TO 1.0V
R414
10kΩ
L410
120nH
C420
0.018µF
C415
0.018µF
R415
274Ω
C410
0.1µF
C425
0.1µF
C423
0.1µF
C424
0.1µF
L409
120nH
C418
22pF
C417
0.1µF
C416
0.1µF
C414
0.1µF R417
10kΩ
C421
22pF
C419
0.1µF C422
0.1µF
INH2 INH1
AVDD_5V
AVDD_5V
C426
10µF
C413
10µF
OPTIONAL V GA DRIV E CIRCUIT FOR CHANNEL A AND CHANNEL B
C409
0.1µF
R411
10kΩ
R412
10kΩ
DNP
C403
DNP
L404
0Ω
R403
DNP
L408
0Ω
24
17
20
23
18
22
19
21
R404
DNP
L406
0Ω
L405
0Ω
L402
0Ω L403
0Ω
L407
0Ω
C408
0.1µF
C407
0.1µF
C406
0.1µF
C405
0.1µF
R410
187Ω
R409
187Ω
R408
187Ω
R407
187Ω
C402
DNP
L401
0Ω
C401
DNP
R405
374Ω
R406
374Ω
CH_A
CH_B
CH_B
CH_A
AVDD_5V
AVDD_5V
AVDD_5V
C404
DNP
R401
DNP R402
DNP
31 10
26
25
14
27
3
6
4
5
1
8
32 9
15
16 VG
28 13
29 12
30 11
2
7
COM1 COM2
ENBL
ENBV GAIN
HILO
INH1
INH2
LMD1
LMD2
LON1
LON2
LOP1 LOP2
MODE
NC
RCLMP
VCM1 VCM2
VIN1 VIN2
VIP1 VIP2
VOH1
VOH2
VOL1
VOL2
VPS1
VPS2
VPSV
AD8332
U401
COMM
COMM
R413
10kΩ
DNP
R424
10kΩ
DNP
C412
0.1µF
C411
1000pF
RCLAMP P IN
HILO PIN = LO = ±50mV
HIL O PI N = H = ± 75mV
POWER DO WN ENABLE
(0V TO 1V = DISABLE POWER)
R416
274Ω
POPULATE L401 T O L408 WITH
0ΩRESISTORS OR DESIGN
YOUR OWN FILTER.
Y1
VCC
Y2A2
GND
A1
SPI CIRCUITRY FROM FIFO
SDIO_ODM
AVDD_DUT
R431
1kΩ
R432
1kΩ
R433
1kΩ
AVDD_3.3V
1
2
3 4
5
6
NC7WZ07
U403
R425
10kΩ
AVDD_DUT
RESET/REPROGRAM
1
23
4
S401
+3.3V = NORMAL OPERATI ON = AVDD_3.3V
+5V = P ROGRAM M ING = AV DD_5V
AVDD_5V
AVDD_3.3V
J402
C427
0.1µF
R418
4.75kΩ
PIC12F629
R419
261Ω
4
3
1
2
5
6
8
7
U402
CR401
GP0
GP1
GP2
GP4
GP5
VDD VSS
MCLR/
GP3
REMOVE WHEN USING
OR PROGRAM M ING P IC (U402)
R427
0Ω
R420
0Ω
R428
0Ω
R426
0Ω
SDO_CHA
SDI_CHA
SCLK_CHA
CSB1_CHA
C429
0.1µF
SCLK_DTP
CSB_DUT
AVDD_DUT
Y1
VCC
Y2A2
GND
A1
1
2
3 4
5
6
U404
R430
10kΩ R429
10kΩ
NC7WZ16
C428
0.1µF
PIC P ROGRAM M ING HE ADE R
MCLR/GP3
GP0
GP1
PICVCC
MCLR/GP3
GP0
GP1
PICVCC
9
7
5
3
1
10
8
6
4
2
J401
E401
R421
0Ω, DNP
R423
0Ω, DNP
R422
0Ω, DNP
OPTIONAL
DNP: DO NOT P OPULATE
05965-018
Figure 65. Evaluation Board Schematic, Optional DUT Analog Input Drive and SPI Interface Circuit (Continued)
AD9259 Data Sheet
Rev. E | Page 42 of 52
MOUNTING HOLES
CONNE CTED T O G ROUND
H2
H3H1
H4
P1
P2
P3
P4
P5
P6
P7
P8
OPTIONAL POWER INPUT
+5.0V
+1.8V
+1.8V
+3.3V
1
2
3
4
5
6
7
8
P501
3.3V_AVDD
5V_AVDD
L502
10µH
DUT_AVDD
DUT_DRVDD
C509
0.1µF
C508
10µF
L503
10µH
L501
10µH DRVDD_DUT
AVDD_DUT
0.1µF
C505
0.1µF
C507
C503
0.1µF
AVDD_5V
10µF
C504
C502
10µF
10µF
C506
AVDD_3.3V
10µH
L508
DECO UP LING CAPACITORS
AVDD_3.3V
0.1µF
C524 0.1µF
C525
C521
0.1µF
C531
0.1µF
C530
0.1µF
C529
0.1µF
C522
0.1µF
C528
0.1µF
C527
0.1µF
C526
0.1µF
0.1µF
C517
0.1µF
C516
C518
0.1µF C520
0.1µF
C519
0.1µF C523
0.1µF
DRVDD_DUT
AVDD_DUT
AVDD_5V
SMDC110F
POWER SUPPLY INPUT
6V, 2V MAXIMUM
1
3
2
P503
C501
10µF
F501
D502
3A
SHOT_RECT
DO-214AB
D501
S2A_RECT
2A
DO-214AA
21
34
FER501
CHOKE_COIL CR501
R501
261Ω
PWR_IN
+
GND
INPUT OUTPUT1
GND
INPUT OUTPUT1
OUTPUT4
OUTPUT4
GND
INPUT
GND
INPUT
DNP: DO NOT POPUL ATE
4
2
3
1
ADP3339AKC-5
U504
4
23
1
ADP3339AKC-3.3
U502
1
3 2
4
U501
ADP3339AKC-1.8
1
3 2
4
U503
ADP3339AKC-1.8
L505
10µH
10µH
L504
C515
1µF
C513
1µF
C512
1µF
C514
1µF
PWR_IN
PWR_IN
DUT_AVDD
DUT_DRVDD 5V_AVDD
3.3V_AVDD
PWR_IN
PWR_IN
C532
1µF
C534
1µF C535
1µF
C533
1µF
L507
10µH
L506
10µH
OUTPUT1
OUTPUT1
OUTPUT4
OUTPUT4
05965-019
Figure 66. Evaluation Board Schematic, Power Supply Inputs
Data Sheet AD9259
Rev. E | Page 43 of 52
05965-020
Figure 67. Evaluation Board Layout, Primary Side
AD9259 Data Sheet
Rev. E | Page 44 of 52
05965-021
Figure 68. Evaluation Board Layout, Ground Plane
Data Sheet AD9259
Rev. E | Page 45 of 52
05965-022
Figure 69. Evaluation Board Layout, Power Plane
AD9259 Data Sheet
Rev. E | Page 46 of 52
05965-023
Figure 70. Evaluation Board Layout, Secondary Side (Mirrored Image)
Data Sheet AD9259
Rev. E | Page 47 of 52
Table 17. Evaluation Board Bill of Materials (BOM)1
Item Qty. Reference Designator Device Package Value Manufacturer
Manufacturer’s
Part Number
1 1 AD9259LFCSP_REVA PCB PCB PCB
2 75 C101, C102, C107,
C108, C109, C114,
C115, C116, C121,
C122, C123, C128,
C201, C203, C204,
C205, C206, C210,
C211, C212, C213,
C216, C217, C218,
C219, C220, C221,
C222, C223, C224,
C310, C311, C312,
C313, C314, C316,
C319, C320, C321,
C324, C325, C409,
C410, C412, C414,
C416, C417, C419,
C422, C423, C424,
C425, C427, C428,
C429, C503, C505,
C507, C509, C516,
C517, C518, C519,
C520, C521, C522,
C523, C524, C525,
C526, C527, C528,
C529, C530, C531
Capacitor 402 0.1 μF, ceramic,
X5R, 10 V, 10% tol
Murata GRM155R71C104KA88D
3 4 C104, C111, C118,
C125
Capacitor 402 2.2 pF, ceramic,
COG, 0.25 pF tol,
50 V
Murata GRM1555C1H2R2GZ01B
4 4 C315, C326, C413,
C426
Capacitor 805 10 μF, 6.3 V ±10%
ceramic, X5R
Murata GRM219R60J106KE19D
5 1 C202 Capacitor 603 2.2 μF, ceramic,
X5R, 6.3 V, 10% tol
Murata GRM188C70J225KE20D
6 2 C309, C411 Capacitor 402 1000 pF, ceramic,
X7R, 25 V, 10% tol
Murata GRM155R71H102KA01D
7
4
C317, C322, C415,
C420
Capacitor
402
0.018 μF, ceramic,
X7R, 16 V, 10% tol
AVX
0402YC183KAT2A
8 4 C318, C323, C418,
C421
Capacitor 402 22 pF, ceramic,
NPO, 5% tol, 50 V
Murata GRM1555C1H220JZ01D
9 1 C501 Capacitor 1206 10 μF, tantalum,
16 V, 20% tol
Rohm TCA1C106M8R
10 9 C214, C512, C513,
C514, C515, C532,
C533, C534, C535
Capacitor 603 1 μF, ceramic, X5R,
6.3 V, 10% tol
Murata GRM188R61C105KA93D
11 8 C305, C306, C307,
C308, C405, C406,
C407, C408
Capacitor 805 0.1 μF, ceramic,
X7R, 50 V, 10% tol
Murata GRM21BR71H104KA01L
12 4 C502, C504, C506,
C508
Capacitor 603 10 μF, ceramic,
X5R, 6.3 V, 20% tol
Murata GRM188R60J106M
13 1 CR201 Diode SOT-23 30 V, 20 mA, dual
Schottky
Agilent
Technologies
HSMS2812-TRIG
14 2 CR401, CR501 LED 603 Green, 4 V, 5 m
candela
Panasonic LNJ314G8TRA
15 1 D502 Diode DO-214AB 3 A, 30 V, SMC Micro
Commercial Co.
SK33-TP
16 1 D501 Diode DO-214AA 2 A, 50 V, SMC Micro
Commercial Co.
S2A-TP
AD9259 Data Sheet
Rev. E | Page 48 of 52
Item Qty. Reference Designator Device Package Value Manufacturer
Manufacturer’s
Part Number
17 1 F501 Fuse 1210 6.0 V, 2.2 A trip-
current resettable
fuse
Tyco/Raychem NANOSMDC110F-2
18 1 FER501 Choke coil 2020 10 μH, 5 A, 50 V,
190 Ω @ 100 MHz
Murata DLW5BSN191SQ2L
19 12 FB101, FB102, FB103,
FB104, FB105, FB106,
FB107, FB108, FB109,
FB110, FB111, FB112
Ferrite bead 603 10 Ω, test freq
100 MHz, 25% tol,
500 mA
Murata BLM18BA100SN1B
20 1 JP301 Connector 2-pin 100 mil header
jumper, 2-pin
Samtec TSW-102-07-G-S
21 2 J205, J402 Connector 3-pin 100 mil header
jumper, 3-pin
Samtec TSW-103-07-G-S
22 4 J201 to J204 Connector 12-pin 100 mil header
male, 4 × 3 triple
row straight
Samtec TSW-104-08-G-T
23 1 J401 Connector 10-pin 100 mil header,
male, 2 × 5 double
row straight
Samtec TSW-105-08-G-D
24 8 L501, L502, L503, L504,
L505, L506, L507, L508
Ferrite bead 1210 10 μH, bead core
3.2 × 2.5 × 1.6
SMD, 2 A
Murata BLM31PG500SN1L
25 4 L309, L310, L409, L410 Inductor 402 120 nH, test freq
100 MHz, 5% tol,
150 mA
Murata LQG15HNR12J02B
26 16 L301, L302, L303, L304,
L305, L306, L307, L308,
L401, L402, L403, L404,
L405, L406, L407, L408
Resistor 805 0 Ω, 1/8 W, 5% tol NIC
Components
NRC10ZOTRF
27 1 OSC201 Oscillator SMT Clock oscillator,
50.00 MHz, 3.3 V
Valpey Fisher VFAC3H-L-50MHz
28 5 P101, P103, P105,
P107, P201
Connector SMA Side-mount SMA
for 0.063" board
thickness
Johnson
Components
142-0710-851
29 1 P202 Connector Header 1469169-1, right
angle 2-pair,
25 mm, header
assembly
Tyco 6469169-1
30 1 P503 Connector 0.1", PCMT SC1153, power
supply connector
Switchcraft RAPC722X
31 15 R201, R205, R214,
R215, R221, R239,
R312, R315, R318,
R411, R414, R417,
R425, R429, R430
Resistor 402 10 kΩ, 1/16 W,
5% tol
NIC
Components
NRC04J103TRF
32 14 R103, R117, R129,
R142, R216, R217,
R218, R223, R224,
R237, R420, R426,
R427, R428
Resistor 402 0 Ω, 1/16 W,
5% tol
NIC
Components
NRC04Z0TRF
33 4 R102, R115, R128,
R141
Resistor 402 64.9 Ω, 1/16 W,
1% tol
NIC
Components
NRC04F64R9TRF
34 4 R104, R116, R130,
R143
Resistor 603 0 Ω, 1/10 W,
5% tol
NIC
Components
NRC06Z0TRF
Data Sheet AD9259
Rev. E | Page 49 of 52
Item Qty. Reference Designator Device Package Value Manufacturer
Manufacturer’s
Part Number
35 15 R109, R111, R112,
R123, R125, R126,
R135, R138, R139,
R148, R149, R150,
R431, R432, R433
Resistor 402 1 kΩ, 1/16 W,
1% tol
NIC
Components
NRC04F1001TRF
36 8 R108, R110, R121,
R122, R134, R136,
R146, R147
Resistor 402 33 Ω, 1/16 W,
5% tol
NIC
Components
NRC04J330TRF
37
4
R161, R162, R163,
R164
Resistor
402
499 Ω, 1/16 W,
1% tol
NIC
Components
NRC04F4990TRF
38 3 R202, R203, R204 Resistor 402 100 kΩ, 1/16 W,
1% tol
NIC
Components
NRC04F1003TRF
39 1 R222 Resistor 402 4.12 kΩ, 1/16 W,
1% tol
NIC
Components
NRC04F4121TRF
40 1 R213 Resistor 402 49.9 Ω, 1/16 W,
0.5% tol
Susumu RR0510R-49R9-D
41 1 R229 Resistor 402 4.99 kΩ, 1/16 W,
5% tol
NIC
Components
NRC04F4991TRF
42 2 R230, R319 Potentiometer 3-lead 10 kΩ, cermet
trimmer
potentiometer,
18-turn top adjust,
10%, 1/2 W
BC
Components
CT94EW103
43 1 R228 Resistor 402 470 kΩ, 1/16 W,
5% tol
NIC
Components
NRC04J474TRF
44 1 R320 Resistor 402 39 kΩ, 1/16 W,
5% tol
NIC
Components
NRC04J393TRF
45 8 R307, R308, R309,
R310, R407, R408,
R409, R410
Resistor 402 187 Ω, 1/16 W,
1% tol
NIC
Components
NRC04F1870TRF
46 4 R305, R306, R405,
R406
Resistor 402 374 Ω, 1/16 W,
1% tol
NIC
Components
NRC04F3740TRF
47 4 R316, R317, R415,
R416
Resistor 402 274 Ω, 1/16 W,
1% tol
NIC
Components
NRC04F2740TRF
48 11 R245, R247, R249,
R251, R253, R255,
R257, R259, R261,
R263, R265
Resistor 201 0 Ω, 1/20 W, 5% tol Panasonic ERJ-1GE0R00C
49 1 R418 Resistor 402 4.75 kΩ, 1/16 W,
1% tol
NIC
Components
NRC04J472TRF
50 1 R419 Resistor 402 261 Ω, 1/16 W,
1% tol
NIC
Components
NRC04F2610TRF
51 1 R501 Resistor 603 261 Ω, 1/16 W,
1% tol
NIC
Components
NRC06F2610TRF
52 2 R240, R241 Resistor 402 243 Ω, 1/16 W,
1% tol
NIC
Components
NRC04F2430TRF
53 2 R242, R243 Resistor 402 100 Ω, 1/16 W,
1% tol
NIC
Components
NRC04F1000TRF
54 1 S401 Switch SMD Light touch,
100GE, 5 mm
Panasonic EVQ-PLDA15
55 5 T101, T102, T103,
T104, T201
Transformer CD542 ADT1-1WT, 1:1
impedance ratio
transformer
Mini-Circuits ADT1-1WT+
56 2 U501, U503 IC SOT-223 ADP3339AKC-1.8,
1.5 A, 1.8 V LDO
regulator
Analog Devices ADP3339AKCZ-1.8
AD9259 Data Sheet
Rev. E | Page 50 of 52
Item Qty. Reference Designator Device Package Value Manufacturer
Manufacturer’s
Part Number
57 2 U301, U401 IC LFCSP,
CP-32
AD8332ACP,
ultralow noise
precision dual VGA
Analog Devices AD8332ACPZ
58 1 U504 IC SOT-223 ADP3339AKC-5 Analog Devices ADP3339AKCZ-5
59 1 U502 IC SOT-223 ADP3339AKC-3.3 Analog Devices ADP3339AKCZ-3.3
60 1 U201 IC LFCSP,
CP-48-1
AD9259BCPZ-50,
quad, 14-bit, 50
MSPS serial LVDS
1.8 V ADC
Analog Devices AD9259BCPZ-50
61 1 U203 IC SOT-23 ADR510ARTZ, 1.0 V,
precision low
noise shunt
voltage reference
Analog Devices ADR510ARTZ
62 1 U202 IC LFCSP
CP-32-2
AD9515BCPZ Analog Devices AD9515BCPZ
63 1 U403 IC SC70,
MAA06A
NC7WZ07 Fairchild NC7WZ07P6X_NL
64 1 U404 IC SC70,
MAA06A
NC7WZ16 Fairchild NC7WZ16P6X_NL
65
1
U402
IC
8-SOIC
Flash prog
mem 1k × 14,
RAM size 64 × 8,
20 MHz speed,
PIC12F controller
series
Microchip
PIC12F629-I/SN
1 This BOM is RoHS compliant.
Data Sheet AD9259
Rev. E | Page 51 of 52
OUTLINE DIMENSIONS
*COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
WITH EXCEPTION TO EXPOSED PAD DIMENSION.
FORPROPERCONNECTIONOF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
1
48
12
13
37
36
24
25
*5.55
5.50 SQ
5.45
0.50
0.40
0.30
0.30
0.23
0.18
0.80 MAX
0.65 TYP
5.50 REF
COPLANARITY
0.08
EXPOSED
PAD
(BOTTOM VIEW)
0.20 REF
1.00
0.85
0.80 0.05 MAX
0.02 NOM
SEATING
PLANE
12° MAX
TOP VIEW
0.60 MAX
0.60 MAX
PIN 1
INDICATOR 0.50
REF
PIN 1
INDICATOR
0.22 MIN
7.10
7.00 SQ
6.90
6.85
6.75 SQ
6.65
02-23-2010-C
Figure 71. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
7 mm × 7 mm Body, Very Thin Quad
(CP-48-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Notes
Temperature
Range Package Description
Package
Option
AD9259ABCPZ-50 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-48-8
AD9259ABCPZRL7-50 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7” Tape and Reel CP-48-8
AD9259-50EBZ 2 Evaluation Board
1 Z = RoHS Compliant Part.
2 Interposer board (HSC-ADC-FIFO5-INTZ) is required to connect to HSC-ADC-EVALCZ data capture board.
AD9259 Data Sheet
Rev. E | Page 52 of 52
NOTES
©2006–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05965-0-1/11(E)