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March 2016
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN53600 / FAN53610 • Rev. 1.4
FAN53600 / FAN53610 — 3MHz, 600mA / 1A Synchronous Buck Regulator
FAN53600 / FAN53610
3 MHz, 600 mA / 1A Synchronous Buck Regulator
Features
600 mA or 1 A Output Current Capability
26 µA Typical Quiescent Current
3 MHz Fixed-Frequency Operation
Best-in-Class Load Transient Response
Best-in-Class Efficiency
2.3 V to 5.5 V Input Voltage Range
Low Ripple Light-Load PFM Mode
Forced PWM and External Clock Synchronization
Internal Soft-Start
Input Under-Voltage Lockout (UVLO)
Thermal Shutdown and Overload Protection
Optional Output Discharge
6-Bump WLCSP, 0.4 mm Pitch
Applications
3G, 4G, WiFi®, WiMAX™, and WiBro® Data Cards
Tablets
DSC, DVC
Netbooks®, Ultra-Mobile PCs
All trademarks are the property of their respective owners.
Description
The FAN53600/10 is a 3 MHz step-down switching voltage
regulator, available in 600 mA or 1 A options, that delivers a
fixed output from an input voltage supply of 2.3 V to 5.5 V.
Using a proprietary architecture with synchronous
rectification, the FAN53600/10 is capable of delivering a
peak efficiency of 97%.
The regulator operates at a nominal fixed frequency of
3 MHz, which reduces the value of the external components
to as low as 1 µH for the output inductor and 10 µF for the
output capacitor. In addition, the Pulse-Width Modulation
(PWM) modulator can be synchronized to an external
frequency source.
At moderate and light-loads, Pulse Frequency Modulation
(PFM) is used to operate the device in Power-Save Mode
with a typical quiescent current of 26 µA. Even with such a
low quiescent current, the part exhibits excellent transient
response during large load swings. At higher loads, the
system automatically switches to fixed-frequency control,
operating at 3 MHz. In Shutdown Mode, the supply current
drops below 1 µA, reducing power consumption. For
applications that require minimum ripple or fixed frequency,
PFM Mode can be disabled using the MODE pin.
The FAN53600/10 is available in 6-bump, 0.4 mm pitch,
Wafer-Level Chip-Scale Package (WLCSP).
Figure 1. Typical Application
Ordering Information
Part Number
Output
Voltage(1)
Max. Output
Current
Active
Discharge(2)
Package
Temperature
Range
Packing
FAN53600AUC28X
2.8 V
600 mA
Yes
WLCSP-6,
0.4 mm Pitch
–40 to +85°C
Tape and
Reel
FAN53610AUC29X
2.9 V
1 A
Yes
FAN53610AUC30X
3.0 V
1 A
Yes
FAN53600AUC33X
3.3 V
600 mA
Yes
FAN53610AUC33X
3.3 V
1 A
Yes
Notes:
1. Other voltage options available on request. Contact a Fairchild representative.
2. All voltage and output current options are available with or without active discharge. Contact a Fairchild representative.
SW
MODE
GND
EN
L
1
C
IN
2
.
2
F
C
2
B
2
A
2
C
1
B
1
A
1
FB
F
C
OUT
VIN
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN53600 / FAN53610 • Rev. 1.4 2
FAN53600 / FAN53610 — 3 MHz, 600 mA / 1 A Synchronous Buck Regulator
Pin Configurations
C1
B1
A1
C2
B2
A2
MODE
SW
FB
VIN
EN
GND
C1
B1
A1
C2
B2
A2 MODE
SW
FB
VIN
EN
GND
Figure 2. Bumps Facing Down
Figure 3. Bumps Facing Up
Pin Definitions
Pin #
Name
Description
A1
MODE
MODE. Logic 1 on this pin forces the IC to stay in PWM Mode. Logic 0 allows the IC to automatically
switch to PFM Mode during light loads. The regulator also synchronizes its switching frequency to
two times the frequency provided on this pin. Do not leave this pin floating.
B1
SW
Switching Node. Connect to output inductor.
C1
FB
Feedback. Connect to output voltage.
C2
GND
Ground. Power and IC ground. All signals are referenced to this pin.
B2
EN
Enable. The device is in Shutdown Mode when voltage to this pin is <0.4 V and enabled when
>1.2 V. Do not leave this pin floating.
A2
VIN
Input Voltage. Connect to input power source.
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN53600 / FAN53610 • Rev. 1.4 3
FAN53600 / FAN53610 — 3 MHz, 600 mA / 1 A Synchronous Buck Regulator
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above
the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended
exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings
are stress ratings only.
Symbol
Parameter
Min.
Max.
Unit
VIN
Input Voltage
–0.3
7.0
V
VSW
Voltage on SW Pin
–0.3
VIN + 0.3(3)
V
VCTRL
EN and MODE Pin Voltage
–0.3
VIN + 0.3(3)
V
Other Pins
–0.3
VIN + 0.3(3)
V
ESD
Electrostatic Discharge
Protection Level
Human Body Model per JESD22-A114
2.0
kV
Charged Device Model per JESD22-C101
1.5
TJ
Junction Temperature
–40
+150
°C
TSTG
Storage Temperature
–65
+150
°C
TL
Lead Soldering Temperature, 10 Seconds
+260
°C
Note:
3. Lesser of 7 V or VIN+0.3 V.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating
conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding
them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Min.
Typ.
Max.
Unit
VCC
Supply Voltage Range
2.3
5.5
V
IOUT
Output Current
FAN53600
0
600
mA
FAN53610
0
1
A
L
Inductor
1
µH
CIN
Input Capacitor
2.2
µF
COUT
Output Capacitor
10
µF
TA
Operating Ambient Temperature
–40
+85
°C
TJ
Operating Junction Temperature
–40
+125
°C
Thermal Properties
Junction-to-ambient thermal resistance is a function of application and board layout. This data is measured with four-layer 2s2p
boards (no vias) in accordance to JEDEC standard JESD51. Special attention must be paid not to exceed junction temperature
TJ(max) at a given ambient temperature TA.
Symbol
Parameter
Typical
Unit
JA
Junction-to-Ambient Thermal Resistance
125
°C/W
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN53600 / FAN53610 • Rev. 1.4 4
FAN53600 / FAN53610 — 3 MHz, 600 mA / 1 A Synchronous Buck Regulator
Electrical Characteristics(5)
Minimum and maximum values are at VIN = VEN = 2.3 V to 5.5 V, VMODE = 0 V (AUTO Mode), and TA = -40°C to +85°C; circuit of
Figure 1, unless otherwise noted. Typical values are at TA = 25°C, VIN = VEN = 3.6 V.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
Power Supplies
IQ
Quiescent Current
No Load, Not Switching
26
µA
PWM Mode
3
mA
I(SD)
Shutdown Supply Current
VIN = 3.6 V, EN = GND
0.25
1.00
µA
VUVLO
Under-Voltage Lockout Threshold
Rising VIN
2.15
2.27
V
VUVHYST
Under-Voltage Lockout Hysteresis
200
mV
Logic Inputs: EN and MODE Pins
VIH
Enable HIGH-Level Input Voltage
1.2
V
VIL
Enable LOW-Level Input Voltage
0.4
V
VLHYST
Logic Input Hysteresis Voltage
100
mV
IIN
Enable Input Leakage Current
Pin to VIN or GND
0.01
1.00
µA
Switching and Synchronization
fSW
Oscillator Frequency(4)
VIN = 3.6 V, TA = 25°C
2.7
3.0
3.3
MHz
fSYNC
MODE Synchronization Range(4)
Square Wave at MODE Input
1.3
1.5
1.7
MHz
Regulation
VO
Output Voltage
Accuracy
2.800 V
ILOAD = 0 to 600 mA, VIN = 3.8 V
2.702
2.898
V
ILOAD = 0 to 600 mA, VIN = 5.0 V
2.702
2.898
2.900 V
ILOAD = 0 to 1000 mA, VIN = 3.8 V
2.797
3.003
ILOAD = 0 to 1000 mA, VIN = 5.0 V
2.790
3.010
3.000 V
ILOAD = 0 to 1000 mA, VIN = 3.8 V
2.891
3.110
ILOAD = 0 to 1000 mA, VIN = 5.0 V
2.891
3.110
3.300 V
ILOAD = 0 to 1000 mA, VIN = 3.8 V
3.171
3.430
ILOAD = 0 to 1000 mA, VIN = 5.0 V
3.192
3.409
tSS
Soft-Start
VIN = 3.8 V, ILOAD = 10 mA, From
EN Rising Edge
180
300
µs
Output Driver
RDS(on)
PMOS On Resistance
VIN = VGS = 3.6 V
175
m
NMOS On Resistance
VIN = VGS = 3.6 V
165
m
ILIM(OL)
PMOS Peak Current Limit
FAN53600
VIN = 3.6 V,
TA = 25°C
900
1100
1250
mA
FAN53610
1500
1750
2000
mA
RDIS
Output Discharge Resistance
EN = GND
230
TTSD
Thermal Shutdown
CCM Only
150
°C
THYS
Thermal Shutdown Hysteresis
15
°C
Notes:
4. Close-Loop Switching frequency may be limited by the effect of tOFF minimum (see Operation Description section).
5. The Electrical Characteristics table reflects open-loop data. Refer to Operation Description and Typical Characteristics
Sections for closed loop data
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN53600 / FAN53610 • Rev. 1.4 5
FAN53600 / FAN53610 — 3 MHz, 600 mA / 1 A Synchronous Buck Regulator
Typical Performance Characteristics
Unless otherwise noted, V IN = VEN = 3.6 V, VMODE = 0 V (AUTO Mode), and TA = 25°C.
Figure 4. Efficiency vs. Load Current and Input
Voltage, V
OUT
=3.3 V, Dotted for Decreasing Load
Figure 5. Efficiency vs. Load Current and
Temperature V
IN
=5 V, V
OUT
=3.3 V, Dotted for FPWM
Figure 6. Efficiency vs. Load Current and Input
Voltage, V
OUT
=2.9 V, Dotted for Decreasing Load
Figure 7. Efficiency vs. Load Current and
Temperature, V
OUT
=2.9 V, Dotted for FPWM
80%
83%
86%
89%
92%
95%
98%
0200 400 600 800 1000
Efficiency
Load Current (mA)
3.6 VIN
4.2 VIN
5.0 VIN
5.5 VIN
70%
75%
80%
85%
90%
95%
100%
0200 400 600 800 1000
Efficiency
Load Current (mA)
- 40C, AUTO
+25C, AUTO
+85C, AUTO
- 40C, PWM
+25C, PWM
+85C, PWM
80%
83%
86%
89%
92%
95%
98%
0200 400 600 800 1000
Efficiency
Load Current (mA)
3.2 VIN
3.6 VIN
4.2 VIN
5.0 VIN
70%
75%
80%
85%
90%
95%
100%
0200 400 600 800 1000
Efficiency
Load Current (mA)
- 40C, AUTO
+25C, AUTO
+85C, AUTO
- 40C, PWM
+25C, PWM
+85C, PWM
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN53600 / FAN53610 • Rev. 1.4 6
FAN53600 / FAN53610 — 3 MHz, 600 mA / 1 A Synchronous Buck Regulator
Typical Performance Characteristics (Continued)
Unless otherwise noted, V IN = VEN = 3.6 V, VMODE = 0 V (AUTO Mode), and TA = 25°C.
Figure 8. ∆V
OUT
(%) vs. Load Current and Input
Voltage, V
OUT
=2.9 V, Normalized to 3.6 V
IN
, 500 mA
Load, FPWM, Dotted for Auto Mode
Figure 9. ∆V
OUT
(%) vs. Load Current and Input
Voltage, V
OUT
=3.3 V, Normalized to 3.6 V
IN
, 500 mA
Load, FPWM, Dotted for Auto Mode
Figure 10. PFM / PWM /100% Duty Cycle Boundary
vs. Input Voltage, V
OUT
=2.9 V
Figure 11. PFM / PWM /100% Duty Cycle Boundary
vs. Input Voltage, V
OUT
=3.3 V
Figure 12. Quiescent Current vs. Input Voltage and
Temperature, V
OUT
=2.9 V, EN=V
IN
Solid, Dotted for
EN=1.8 V
Figure 13. Quiescent Current vs. Input Voltage and
Temperature, V
OUT
=2.9 V, Mode=EN=V
IN
(FPWM)
-3
-2
-1
0
1
2
3
0200 400 600 800 1000
Output Regulation (%)
Load Current (mA)
3.2VIN, AUTO
3.6VIN, AUTO
4.2VIN, AUTO
5.0VIN, AUTO
3.2VIN, PWM
3.6VIN, PWM
4.2VIN, PWM
5.0VIN, PWM
-3
-2
-1
0
1
2
3
0200 400 600 800 1000
Output Regulation (%)
Load Current (mA)
3.6VIN, AUTO
4.2VIN, AUTO
5.0VIN, AUTO
5.5VIN, AUTO
3.6VIN, PWM
4.2VIN, PWM
5.0VIN, PWM
5.5VIN, PWM
0
100
200
300
400
500
2.9 3.4 3.9 4.4 4.9 5.4
Load Current (mA)
Input Voltage (V)
PWM
PFM
100% d.c.
0
100
200
300
400
500
3.3 3.8 4.3 4.8 5.3
Load Current (mA)
Input Voltage (V)
PWM
PFM
100% d.c.
10
15
20
25
30
35
40
2.5 3.0 3.5 4.0 4.5 5.0 5.5
Input Current (A)
Input Voltage (V)
- 40C, EN=VIN
+25C, EN=VIN
+85C, EN=VIN
- 40C, EN=1.8V
+25C, EN=1.8V
+85C, EN=1.8V
0
5
10
15
20
25
2.5 3.0 3.5 4.0 4.5 5.0 5.5
Input Current (mA)
Input Voltage (V)
-40C
+25C
+85C
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN53600 / FAN53610 • Rev. 1.4 7
FAN53600 / FAN53610 — 3 MHz, 600 mA / 1 A Synchronous Buck Regulator
Typical Performance Characteristics (Continued)
Unless otherwise noted, V IN = VEN = 3.6 V, VMODE = 0 V (AUTO Mode), and TA = 25°C.
Figure 14. Output Ripple vs. Load Current and Input
Voltage, V
OUT
=2.9 V, FPWM, Dotted for Auto Mode
Figure 15. Output Ripple vs. Load Current and Input
Voltage, V
OUT
=3.3 V, FPWM, Dotted for Auto Mode
Figure 16. Frequency vs. Load Current and Input
Voltage, V
OUT
=2.9 V, Auto Mode, Dotted for FPWM
Figure 17. Frequency vs. Load Current and Input
Voltage, V
OUT
=3.3 V, Auto Mode, Dotted for FPWM
Figure 18. Load Transient, V
IN
=5 V, V
OUT
=3.3 V,
10-200-10 mA, 100 ns Edge
Figure 19. Load Transient, V
IN
=5 V, V
OUT
=3.3 V, 200-
800-200 mA, 100 ns Edge
0
500
1,000
1,500
2,000
2,500
3,000
3,500
0200 400 600 800 1000
Switching Frequency (KHz)
Load Current (mA)
3.2VIN, AUTO
3.6VIN, AUTO
5.0VIN, AUTO
3.2VIN, PWM
3.6VIN, PWM
5.0VIN, PWM
0
500
1,000
1,500
2,000
2,500
3,000
3,500
0200 400 600 800 1000
Switching Frequency (KHz)
Load Current (mA)
3.6VIN, AUTO
3.6VIN, AUTO
5.0VIN, AUTO
3.6VIN, PWM
4.2VIN, PWM
5.0VIN, PWM
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN53600 / FAN53610 • Rev. 1.4 8
FAN53600 / FAN53610 — 3 MHz, 600 mA / 1 A Synchronous Buck Regulator
Typical Performance Characteristics (Continued)
Unless otherwise noted, V IN = VEN = 3.6 V, VMODE = 0 V (AUTO Mode), and TA = 25°C.
Figure 20. Load Transient, V
IN
=5 V, V
OUT
=2.9 V,
10-200-10 mA, 100 ns Edge
Figure 21. Load Transient, V
IN
=5 V, V
OUT
=2.9 V,
200-800-200 mA, 100 ns Edge
Figure 22. Line Transient, 3.3-3.9-3.3 V
IN
, 10 µs Edge,
V
OUT
=2.9 V, 58 mA Load
Figure 23. Line Transient, 3.3-3.9-3.3 V
IN
, 10 µs Edge,
V
OUT
=2.9 V, 600 mA Load
Figure 24. Combined Line / Load Transient,
V
OUT
=2.9 V, 3.9-3.3-3.9 V
IN
, 10 µs Edge, 58-500-58 mA
Load, 100 ns Edge
Figure 25. Startup, V
OUT
=2.9 V, 50 Ω Load
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN53600 / FAN53610 • Rev. 1.4 9
FAN53600 / FAN53610 — 3 MHz, 600 mA / 1 A Synchronous Buck Regulator
Typical Performance Characteristics (Continued)
Unless otherwise noted, V IN = VEN = 3.6 V, VMODE = 0 V (AUTO Mode), and TA = 25°C.
Figure 26. Startup, V
OUT
=2.9 V, 4.7 Ω Load
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN53600 / FAN53610 • Rev. 1.4 10
FAN53600 / FAN53610 — 3 MHz, 600 mA / 1 A Synchronous Buck Regulator
Operation Description
The FAN53600/10 is a 3 MHz, step-down switching voltage
regulator, available in 600 mA or 1 A options, that delivers a
fixed output from an input voltage supply of 2.3 V to 5.5 V.
Using a proprietary architecture with synchronous
rectification, the FAN53600/10 is capable of delivering a
peak efficiency of 97%.
The regulator operates at a nominal fixed frequency of
3 MHz, which reduces the value of the external components
to as low as 1 µH for the output inductor and 10 µF for the
output capacitor. In addition, the PWM modulator can be
synchronized to an external frequency source.
Control Scheme
The FAN53600/10 uses a proprietary, non-linear, fixed-
frequency PWM modulator to deliver a fast load transient
response, while maintaining a constant switching frequency
over a wide range of operating conditions. The regulator
performance is independent of the output capacitor ESR,
allowing the use of ceramic output capacitors. Although this
type of operation normally results in a switching frequency
that varies with input voltage and load current, an internal
frequency loop holds the switching frequency constant over
a large range of input voltages and load currents.
For very light loads, the FAN53600/10 operates in
Discontinuous Conduction Mode (DCM), single-pulse, PFM
Mode; which produces low output ripple compared with other
PFM architectures. Transition between PWM and PFM is
seamless, allowing for a smooth transition between DCM
and CCM modes.
Combined with exceptional transient response
characteristics, the very low quiescent current of the
controller (26 µA) maintains high efficiency at very light
loads, while preserving fast transient response for
applications requiring tight output regulation.
100% Duty Cycle Operation
When VIN approaches VOUT, the regulator increases its duty
cycle until 100% duty cycle is reached. As the duty cycle
approaches 100%, the switching frequency declines due to
the minimum off-time (tOFF(MIN)) of about 40 ns imposed by
the control circuit. When 100% duty cycle is reached, VOUT
follows VIN with a drop-out voltage (VDROPOUT) determined by
the total resistance between VIN and VOUT as calculated by:
L)ON(DSLOADDROPOUT DCRR PMOSIV
(1)
Enable and Soft-Start
When EN is LOW, all circuits are off and the IC draws
~250 nA of current. When EN is HIGH and VIN is above its
UVLO threshold, the regulator begins a soft-start cycle. The
output ramp during soft-start is a fixed slew rate of 50 mV/s
from VOUT = 0 to 1 V, then 12.5 mV/s until the output
reaches its setpoint. Regardless of the state of the MODE
pin, PFM Mode is enabled to prevent current from being
discharged from COUT if soft-start begins when COUT is
charged.
All voltage options can be ordered with a feature that actively
discharges FB to ground through a 230 path when EN is
LOW. Raising EN above its threshold voltage activates the
part and starts the soft-start cycle. During soft-start, the
internal reference is ramped using an exponential RC shape
to prevent overshoot of the output voltage. Current limiting
minimizes inrush during soft-start.
The IC may fail to start if heavy load is applied during startup
and/or if excessive COUT is used. This is due to the current-
limit fault response, which protects the IC in the event of an
over-current condition present during soft-start.
The current required to charge COUT during soft-start,
commonly referred to as ―displacement current,‖ is given as:
dt
dV
CI OUTDISP
(2)
where the
dt
dV
term refers to the soft-start slew rate above.
To prevent shutdown during soft-start, the following condition
must be met:
)(
DCMAXLOADDISP III
(3)
where IMAX(DC) is the maximum load current the IC is
guaranteed to support.
Startup into Large COUT
Multiple soft-start cycles are required for no-load startup if
COUT is greater than 15 F. Large COUT requires light initial
load to ensure the FAN53600/10 starts appropriately. The IC
shuts down for 1.3 ms when IDISP exceeds ILIMIT for more
than 200 s of current limit. The IC then begins a new soft-
start cycle. Since COUT retains its charge when the IC is off,
the IC reaches regulation after multiple soft-start attempts.
MODE Pin
Logic 1 on this pin forces the IC to stay in PWM Mode. Logic
0 allows the IC to automatically switch to PFM during light
loads. If the MODE pin is toggled, with a frequency between
1.3 MHz and 1.7 MHz, the converter synchronizes its
switching frequency to two times the frequency on the
MODE pin.
The MODE pin is internally buffered with a Schmitt trigger,
which allows the MODE pin to be driven with slow rise and
fall times. An asymmetric duty cycle for frequency
synchronization is also permitted as long as the minimum
time below VIL(MAX) or above VIH(MAX) is 100 ns.
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN53600 / FAN53610 • Rev. 1.4 11
FAN53600 / FAN53610 — 3 MHz, 600 mA / 1 A Synchronous Buck Regulator
Current Limit, Fault Shutdown, and Restart
A heavy load or short circuit on the output causes the current
in the inductor to increase until a maximum current threshold
is reached in the high-side switch. Upon reaching this point,
the high-side switch turns off, preventing high currents from
causing damage. The regulator continues to limit the current
cycle by cycle. After 16 cycles of current limit, the regulator
triggers an over-current fault, causing the regulator to shut
down for about 1.3 ms before attempting a restart.
If the fault was caused by short circuit, the soft-start circuit
attempts to restart and produces an over-current fault after
about 200 s.
The closed-loop peak-current limit, ILIM(PK), is not the same as
the open-loop tested current limit, ILIM(OL), in the Electrical
Characteristics table. This is primarily due to the effect of
propagation delays of the IC current-limit comparator.
Under-Voltage Lockout (UVLO)
When EN is HIGH, the under-voltage lockout keeps the part
from operating until the input supply voltage rises high
enough to properly operate. This ensures no misbehavior of
the regulator during startup or shutdown.
Thermal Shutdown (TSD)
When the die temperature increases, due to a high load
condition and/or a high ambient temperature, the output
switching is disabled until the temperature on the die has
fallen sufficiently. The junction temperature at which the
thermal shutdown activates is nominally 150°C with a
15°C hysteresis.
Minimum Off-Time and Switching Frequency
tOFF(MIN) is 40 ns. This imposes constraints on the maximum
IN
OUT
V
V
that the FAN53600/10 can provide, or the maximum
output voltage it can provide at low VIN while maintaining a
fixed switching frequency in PWM Mode.
When VIN is LOW, fixed switching frequency is maintained as
long as:O
88.01 )( SWMINOFF
IN
OUT ft
V
V
The switching frequency drops when the regulator cannot
provide sufficient duty cycle at 3 MHz to maintain regulation.
This occurs when VOUT >0.85 VIN at high load currents. The
calculation for switching frequency is given by:
MHz
t
fMAXSW
SW 3 ,
1
min )(
(4)
where:
OUTONOUTIN
OFFOUTOUT
MAXSW VRIV RIV
nst140
)(
(5)
where:
OFF
R
=
LNDSON DCRR
_
ON
R
=
LPDSON DCRR
_
.
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN53600 / FAN53610 • Rev. 1.4 12
FAN53600 / FAN53610 — 3 MHz, 600 mA / 1 A Synchronous Buck Regulator
Applications Information
Selecting the Inductor
The output inductor must meet both the required inductance
and the energy handling capability of the application. The
inductor value affects average current limit, the PWM-to-
PFM transition point, output voltage ripple, and efficiency.
The ripple current (∆I) of the regulator is:
SW
OUTIN
IN
OUT fL VV
V
V
I
(6)
The maximum average load current, IMAX(LOAD), is related to
the peak current limit, ILIM(PK), by the ripple current, given by:
2
)()( I
II PKLIMLOADMAX
(7)
The transition between PFM and PWM operation is
determined by the point at which the inductor valley current
crosses zero. The regulator DC current when the inductor
current crosses zero, IDCM, is:
2I
IDCM
(8)
The FAN53600/10 is optimized for operation with L = 1 H,
but is stable with inductances up to 2.2 H (nominal). The
inductor should be rated to maintain at least 80% of its value
at ILIM(PK).
Efficiency is affected by inductor DCR and inductance value.
Decreasing the inductor value for a given physical size
typically decreases DCR; but since ∆I increases, the RMS
current increases, as do the core and skin effect losses:
12
I
I I 2
2
)DC(OUTRMS
(9)
The increased RMS current produces higher losses through
the RDS(ON) of the IC MOSFETs, as well as the inductor DCR.
Increasing the inductor value produces lower RMS currents,
but degrades transient response. For a given physical
inductor size, increased inductance usually results in an
inductor with lower saturation current and higher DCR.
Table 1 shows the effects of inductance higher or lower than
the recommended 1 H on regulator performance.
Output Capacitor
Table 2 suggests 0603 capacitors which may improve
performance in that the effective capacitance is higher. This
improves transient response and output ripple.
Increasing COUT has no effect on loop stability and can
therefore be increased to reduce output voltage ripple or to
improve transient response. Output voltage ripple, ∆VOUT, is:
OUTSW
2
OUTSW
LOUT Cf8 1
D1D2 ESRCf
IV
(10)
Input Capacitor
The 2.2 F ceramic input capacitor should be placed as
close as possible between the VIN pin and GND to minimize
parasitic inductance. If a long wire is used to bring power to
the IC, additional ―bulk‖ capacitance (electrolytic or tantalum)
should be placed between CIN and the power source lead to
reduce ringing that can occur between the inductance of the
power source leads and CIN.
The effective capacitance value decreases as VIN increases
due to DC bias effects.
Table 1. Effects of Changes in Inductor Value (1 µH Recommended Value) on Regulator Performance
Inductor Value
IMAX(LOAD)
∆VOUT
Transient Response
Increase
Increase
Decrease
Degraded
Decrease
Decrease
Increase
Improved
Table 2. Recommended Passive Components and Variation Due to DC Bias
Component
Description
Vendor
Min.
Typ.
Comment
L1
1 H, 2012, 190 m,
0.8 A
Murata LQM21PN1R0MC0
1 H
Not recommended for 1 A load
1 H, 1.4 A, 64 m,
2016
Murata
LQM2MPN1R0MGH
1 H
Utilized to generate graphs,
Figure 4 — Figure 26
CIN
2.2 F, 6.3 V, X5R,
0402
Murata or Equivalent
GRM155R60J225ME15
GRM188R60J225KE19D
1.0 F
2.2 F
Decrease primarily due to DC bias
(VIN) and elevated temperature
COUT
10 F, X5R 0603
Murata or Equivalent
GRM188R60J106ME47D
4.5 F
10 F
Decrease primarily due to DC bias
(VOUT) and elevated temperature.
Output capacitor for VOUT ≥ 2.7 V
© 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN53600 / FAN53610 • Rev. 1.4 13
FAN53600 / FAN53610 — 3 MHz, 600 mA / 1 A Synchronous Buck Regulator
PCB Layout Guidelines
There are only three external components: the inductor and
the input and output capacitors. For any buck switcher IC,
including the FAN53600/10, it is important to place a low-ESR
input capacitor very close to the IC, as shown in Figure 27.
The input capacitor ensures good input decoupling, which
helps reduce noise at the output terminals and ensures that
the control sections of the IC do not behave erratically due to
excessive noise. This reduces switching cycle jitter and
ensures good overall performance. It is important to place the
common GND of CIN and COUT as close as possible to the C2
terminal. There is some flexibility in moving the inductor further
away from the IC; in that case, VOUT should be considered at
the COUT terminal.
Figure 27. PCB Layout Guidance
The following information applies to the WL-CSP package dimensions on the next page:
Product-Specific Dimensions
D
E
X
Y
1.160 ±0.030
0.860 ±0.030
0.230
0.180
SEATING PLANE
0.06 C
0.05 C
C
SIDE VIEWS NOTES:
A. NO JEDEC REGISTRATION APPLIES.
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASMEY14.5M, 2009.
D. DATUM C, THE SEATING PLANE IS DEFINED
BY THE SPHERICAL CROWNS OF THE BALLS.
E. PACKAGE TYPICAL HEIGHT IS 586 MICRONS
±39 MICRONS (547-625 MICRONS).
F. FOR DIMENSIONS D, E, X, AND Y, SEE
PRODUCT DATASHEET.
G. DRAWING FILENAME: MKT-UC006ACrev6.
BOTTOM VIEW
TOP VIEW RECOMMENDED LAND PATTERN
(NSMD PAD TYPE)
E
D
B
A
BALL A1
INDEX AREA
A1
0.03 C
2X
0.03 C
2X
0.208±0.021
0.378±0.018
12
A
B
C
0.40
0.40
0.005 C A B
(X) +/-0.015
(Y) +/-0.015
Ø0.260±0.010
0.40
6X
E
D
F
F0.40
(Ø0.20)
Bottom of Cu Pad
(Ø0.30)
Solder Mask
Opening
F
0.586±0.039
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