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Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. R8C/26 Group, R8C/27 Group SINGLE-CHIP 16-BIT CMOS MCU 1. REJ03B0168-0210 Rev.2.10 Sep 26, 2008 Overview These MCUs are fabricated using a high-performance silicon gate CMOS process, embedding the R8C CPU core, and are packaged in a 32-pin molded-plastic LQFP. It implements sophisticated instructions for a high level of instruction efficiency. With 1 Mbyte of address space, they are capable of executing instructions at high speed. Furthermore, the R8C/27 Group has on-chip data flash (1 KB x 2 blocks). The difference between the R8C/26 Group and R8C/27 Group is only the presence or absence of data flash. Their peripheral functions are the same. 1.1 Applications Electronic household appliances, office equipment, audio equipment, consumer products, automotive, etc. Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 1 of 69 R8C/26 Group, R8C/27 Group 1.2 1. Overview Performance Overview Table 1.1 outlines the Functions and Specifications for R8C/26 Group and Table 1.2 outlines the Functions and Specifications for R8C/27 Group. Table 1.1 CPU Peripheral Functions Functions and Specifications for R8C/26 Group Item Number of fundamental instructions Minimum instruction execution time Operating mode Address space Memory capacity Ports LED drive ports Timers Serial interfaces Clock synchronous serial interface LIN module A/D converter Watchdog timer Interrupts Clock generation circuits Electrical Characteristics Oscillation-stopped detector Voltage detection circuit Power-on reset circuit Supply voltage Current consumption (N, D version) Flash Memory Programming and erasure voltage Programming and erasure endurance Operating Ambient Temperature Package Specification 89 instructions 50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V) (other than K version) 62.5 ns (f(XIN) = 16 MHz, VCC = 3.0 to 5.5 V) (K version) 100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V) 200 ns (f(XIN) = 5 MHz, VCC = 2.2 to 5.5 V) (N, D version) Single-chip 1 Mbyte Refer to Table 1.3 Product Information for R8C/26 Group I/O ports: 25 pins, Input port: 3 pins I/O ports: 8 pins (N, D version) Timer RA: 8 bits x 1 channel Timer RB: 8 bits x 1 channel (Each timer equipped with 8-bit prescaler) Timer RC: 16 bits x 1 channel (Input capture and output compare circuits) Timer RE: With real-time clock and compare match function (For J, K version, compare match function only.) 2 channels (UART0, UART1) Clock synchronous serial I/O, UART 1 channel I2C bus Interface(1) Clock synchronous serial I/O with chip select Hardware LIN: 1 channel (timer RA, UART0) 10-bit A/D converter: 1 circuit, 12 channels 15 bits x 1 channel (with prescaler) Start-on-reset selectable Internal: 15 sources, External: 4 sources, Software: 4 sources, Priority levels: 7 levels 3 circuits * XIN clock generation circuit (with on-chip feedback resistor) * On-chip oscillator (high speed, low speed) High-speed on-chip oscillator has a frequency adjustment function * XCIN clock generation circuit (32 kHz) (N, D version) * Real-time clock (timer RE) (N, D version) XIN clock oscillation stop detection function On-chip On-chip VCC = 3.0 to 5.5 V (f(XIN) = 20 MHz) (other than K version) VCC = 3.0 to 5.5 V (f(XIN) = 16 MHz) (K version) VCC = 2.7 to 5.5 V (f(XIN) = 10 MHz) VCC = 2.2 to 5.5 V (f(XIN) = 5 MHz) (N, D version) Typ. 10 mA (VCC = 5.0 V, f(XIN) = 20 MHz) Typ. 6 mA (VCC = 3.0 V, f(XIN) = 10 MHz) Typ. 2.0 A (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz) Typ. 0.7 A (VCC = 3.0 V, stop mode) VCC = 2.7 to 5.5 V 100 times -20 to 85C (N version) -40 to 85C (D, J version)(2), -40 to 125C (K version)(2) 32-pin molded-plastic LQFP NOTES: 1. I2C bus is a trademark of Koninklijke Philips Electronics N. V. 2. Specify the D, K version if D, K version functions are to be used. Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 2 of 69 R8C/26 Group, R8C/27 Group Table 1.2 1. Overview Functions and Specifications for R8C/27 Group Item Specification Number of fundamental 89 instructions instructions Minimum instruction 50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V) (other than K version) execution time 62.5 ns (f(XIN) = 16 MHz, VCC = 3.0 to 5.5 V) (K version) 100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V) 200 ns (f(XIN) = 5 MHz, VCC = 2.2 to 5.5 V) (N, D version) Operating mode Single-chip Address space 1 Mbyte Memory capacity Refer to Table 1.4 Product Information of R8C/27 Group Peripheral Ports I/O ports: 25 pins, Input port: 3 pins Functions LED drive ports I/O ports: 8 pins (N, D version) Timers Timer RA: 8 bits x 1 channel Timer RB: 8 bits x 1 channel (Each timer equipped with 8-bit prescaler) Timer RC: 16 bits x 1 channel (Input capture and output compare circuits) Timer RE: With real-time clock and compare match function (For J, K version, compare match function only.) Serial interfaces 2 channels (UART0, UART1) Clock synchronous serial I/O, UART Clock synchronous 1 channel serial interface I2C bus Interface(1) Clock synchronous serial I/O with chip select LIN module Hardware LIN: 1 channel (timer RA, UART0) A/D converter 10-bit A/D converter: 1 circuit, 12 channels Watchdog timer 15 bits x 1 channel (with prescaler) Start-on-reset selectable Interrupts Internal: 15 sources, External: 4 sources, Software: 4 sources, Priority levels: 7 levels Clock generation 3 circuits circuits * XIN clock generation circuit (with on-chip feedback resistor) * On-chip oscillator (high speed, low speed) High-speed on-chip oscillator has a frequency adjustment function * XCIN clock generation circuit (32 kHz) (N, D version) * Real-time clock (timer RE) (N, D version) Oscillation-stopped XIN clock oscillation stop detection function detector Voltage detection circuit On-chip Power-on reset circuit On-chip Electrical Supply voltage VCC = 3.0 to 5.5 V (f(XIN) = 20 MHz) (other than K version) Characteristics VCC = 3.0 to 5.5 V (f(XIN) = 16 MHz) (K version) VCC = 2.7 to 5.5 V (f(XIN) = 10 MHz) VCC = 2.2 to 5.5 V (f(XIN) = 5 MHz) (N, D version) Current consumption Typ. 10 mA (VCC = 5.0 V, f(XIN) = 20 MHz) (N, D version) Typ. 6 mA (VCC = 3.0 V, f(XIN) = 10 MHz) Typ. 2.0 A (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz) Typ. 0.7 A (VCC = 3.0 V, stop mode) Flash Memory Programming and VCC = 2.7 to 5.5 V erasure voltage Programming and 10,000 times (data flash) erasure endurance 1,000 times (program ROM) Operating Ambient Temperature -20 to 85C (N version) -40 to 85C (D, J version)(2), -40 to 125C (K version)(2) Package 32-pin molded-plastic LQFP CPU NOTES: 1. I2C bus is a trademark of Koninklijke Philips Electronics N. V. 2. Specify the D, K version if D, K version functions are to be used. Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 3 of 69 R8C/26 Group, R8C/27 Group 1.3 1. Overview Block Diagram Figure 1.1 shows a Block Diagram. I/O ports 8 8 6 Port P0 Port P1 Port P3 1 3 2 Port P4 Port P5 Peripheral functions System clock generation circuit A/D converter (10 bits x 12 channels) Timers Timer RA (8 bits) Timer RB (8 bits) Timer RC (16 bits x 1 channel) Timer RE (8 bits) XIN-XOUT High-speed on-chip oscillator Low-Speed on-chip oscillator XCIN-XCOUT(3) UART or clock synchronous serial I/O (8 bits x 2 channels) I2C bus interface or clock synchronous serial I/O with chip select (8 bits x 1 channel) LIN module (1 channel) Watchdog timer (15 bits) Memory R8C CPU core R0H R1H R0L R1L R2 R3 SB USP ISP INTB A0 A1 FB ROM(1) RAM(2) PC FLG Multiplier NOTES: 1. ROM size varies with MCU type. 2. RAM size varies with MCU type. 3. XCIN, XCOUT can be used only for N or D version. Figure 1.1 Block Diagram Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 4 of 69 R8C/26 Group, R8C/27 Group 1.4 1. Overview Product Information Table 1.3 lists the Product Information for R8C/26 Group and Table 1.4 lists the Product Information for R8C/27 Group. Table 1.3 Product Information for R8C/26 Group Part No. R5F21262SNFP R5F21264SNFP R5F21265SNFP R5F21266SNFP R5F21262SDFP R5F21264SDFP R5F21265SDFP R5F21266SDFP R5F21264JFP R5F21266JFP R5F21264KFP R5F21266KFP R5F21262SNXXXFP R5F21264SNXXXFP R5F21265SNXXXFP R5F21266SNXXXFP R5F21262SDXXXFP R5F21264SDXXXFP R5F21265SDXXXFP R5F21266SDXXXFP R5F21264JXXXFP R5F21266JXXXFP R5F21264KXXXFP R5F21266KXXXFP ROM Capacity 8 Kbytes 16 Kbytes 24 Kbytes 32 Kbytes 8 Kbytes 16 Kbytes 24 Kbytes 32 Kbytes 16 Kbytes 32 Kbytes 16 Kbytes 32 Kbytes 8 Kbytes 16 Kbytes 24 Kbytes 32 Kbytes 8 Kbytes 16 Kbytes 24 Kbytes 32 Kbytes 16 Kbytes 32 Kbytes 16 Kbytes 32 Kbytes RAM Capacity 512 bytes 1 Kbyte 1.5 Kbytes 1.5 Kbytes 512 bytes 1 Kbyte 1.5 Kbytes 1.5 Kbytes 1 Kbyte 1.5 Kbytes 1 Kbyte 1.5 Kbytes 512 bytes 1 Kbyte 1.5 Kbytes 1.5 Kbytes 512 bytes 1 Kbyte 1.5 Kbytes 1.5 Kbytes 1 Kbyte 1.5 Kbytes 1 Kbyte 1.5 Kbytes NOTE: 1. The user ROM is programmed before shipment. Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 5 of 69 Current of Sep. 2008 Package Type PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A Remarks N version D version J version K version N version D version J version K version Factory programming product(1) R8C/26 Group, R8C/27 Group Part No. 1. Overview R 5 F 21 26 6 S N XXX FP Package type: FP: PLQP0032GB-A ROM number Classification N: Operating ambient temperature -20 to 85C (N version) D: Operating ambient temperature -40 to 85C (D version) J: Operating ambient temperature -40 to 85C (J version) K: Operating ambient temperature -40 to 125C (K version) S: Low-voltage version (other no symbols) ROM capacity 2: 8 KB 4: 16 KB 5: 24 KB 6: 32 KB R8C/26 Group R8C/2x Series Memory type F: Flash memory Renesas MCU Renesas semiconductor Figure 1.2 Part Number, Memory Size, and Package of R8C/26 Group Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 6 of 69 R8C/26 Group, R8C/27 Group Table 1.4 1. Overview Product Information for R8C/27 Group Part No. R5F21272SNFP R5F21274SNFP R5F21275SNFP R5F21276SNFP R5F21272SDFP R5F21274SDFP R5F21275SDFP R5F21276SDFP R5F21274JFP R5F21276JFP R5F21274KFP R5F21276KFP R5F21272SNXXXFP R5F21274SNXXXFP R5F21275SNXXXFP R5F21276SNXXXFP R5F21272SDXXXFP R5F21274SDXXXFP R5F21275SDXXXFP R5F21276SDXXXFP R5F21274JXXXFP R5F21276JXXXFP R5F21274KXXXFP R5F21276KXXXFP ROM Capacity Program Data flash ROM 8 Kbytes 1 Kbyte x 2 16 Kbytes 1 Kbyte x 2 24 Kbytes 1 Kbyte x 2 32 Kbytes 1 Kbyte x 2 8 Kbytes 1 Kbyte x 2 16 Kbytes 1 Kbyte x 2 24 Kbytes 1 Kbyte x 2 32 Kbytes 1 Kbyte x 2 16 Kbytes 1 Kbyte x 2 32 Kbytes 1 Kbyte x 2 16 Kbytes 1 Kbyte x 2 32 Kbytes 1 Kbyte x 2 8 Kbytes 1 Kbyte x 2 16 Kbytes 1 Kbyte x 2 24 Kbytes 1 Kbyte x 2 32 Kbytes 1 Kbyte x 2 8 Kbytes 1 Kbyte x 2 16 Kbytes 1 Kbyte x 2 24 Kbytes 1 Kbyte x 2 32 Kbytes 1 Kbyte x 2 16 Kbytes 1 Kbyte x 2 32 Kbytes 1 Kbyte x 2 16 Kbytes 1 Kbyte x 2 32 Kbytes 1 Kbyte x 2 NOTE: 1. The user ROM is programmed before shipment. Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 7 of 69 Current of Sep. 2008 RAM Capacity Package Type 512 bytes 1 Kbyte 1.5 Kbytes 1.5 Kbytes 512 bytes 1 Kbyte 1.5 Kbytes 1.5 Kbytes 1 Kbyte 1.5 Kbytes 1 Kbyte 1.5 Kbytes 512 bytes 1 Kbyte 1.5 Kbytes 1.5 Kbytes 512 bytes 1 Kbyte 1.5 Kbytes 1.5 Kbytes 1 Kbyte 1.5 Kbytes 1 Kbyte 1.5 Kbytes PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A Remarks N version D version J version K version N version Factory programming product(1) D version J version K version R8C/26 Group, R8C/27 Group 1. Overview Part No. R 5 F 21 27 6 S N XXX FP Package type: FP: PLQP0032GB-A ROM number Classification N: Operating ambient temperature -20 to 85C (N version) D: Operating ambient temperature -40 to 85C (D version) J: Operating ambient temperature -40 to 85C (J version) K: Operating ambient temperature -40 to 125C (K version) S: Low-voltage version (other no symbols) ROM capacity 2: 8 KB 4: 16 KB 5: 24 KB 6: 32 KB R8C/27 Group R8C/2x Series Memory type F: Flash memory Renesas MCU Renesas semiconductor Figure 1.3 Part Number, Memory Size, and Package of R8C/27 Group Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 8 of 69 R8C/26 Group, R8C/27 Group 1.5 1. Overview Pin Assignments P1_4/TXD0 P1_3/KI3/AN11/(TRBO) P1_1/KI1/AN9/TRCIOA/TRCTRG VREF/P4_2 P1_2/KI2/AN10/TRCIOB P1_0/KI0/AN8 P3_4/SDA/SCS/(TRCIOC)(2) P3_3/INT3/SSI/TRCCLK Figure 1.4 shows Pin Assignments (Top View). 24 23 22 21 20 19 18 17 16 26 15 27 14 R8C/26 Group R8C/27 Group 28 29 30 13 12 11 PLQP0032GB-A (32P6U-A) (top view) 2 P3_5/SCL/SSCK/(TRCIOD)(2) P3_7/TRAO/SSO/RXD1/(TXD1)(2) 1 3 4 5 6 10 9 7 8 MODE 32 VCC/AVCC 31 VSS/AVSS XIN/XCIN/P4_6 (3) P0_6/AN1 P0_5/AN2/CLK1 P0_4/AN3/TREO P0_3/AN4 P0_2/AN5 P0_1/AN6 P0_0/AN7/(TXD1)(2) 25 RESET XOUT/XCOUT/P4_7 (1, 3) P0_7/AN0 P1_5/RXD0/(TRAIO)/(INT1)(2) P1_6/CLK0/(SSI)(2) P5_3/TRCIOC P5_4/TRCIOD P3_1/TRBO P3_6/(TXD1)/(RXD1)/(INT1)(2) P1_7/TRAIO/INT1 P4_5/INT0/(RXD1)(2) NOTES: 1. P4_7 is an input-only port. 2. Can be assigned to the pin in parentheses by a program. 3. XCIN, XCOUT can be used only for N or D version. 4. Confirm the pin 1 position on the package by referring to the package dimensions. Figure 1.4 Pin Assignments (Top View) Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 9 of 69 R8C/26 Group, R8C/27 Group 1.6 1. Overview Pin Functions Table 1.5 lists Pin Functions. Table 1.5 Pin Functions Type Symbol I/O Type Description Power supply input VCC, VSS I Apply 2.2 to 5.5 V (J, K version are 2.7 to 5.5 V) to the VCC pin. Apply 0 V to the VSS pin. Analog power supply input AVCC, AVSS I Power supply for the A/D converter. Connect a capacitor between AVCC and AVSS. Reset input RESET I Input "L" on this pin resets the MCU. MODE MODE I Connect this pin to VCC via a resistor. XIN clock input XIN I XIN clock output XOUT O These pins are provided for XIN clock generation circuit I/O. Connect a ceramic resonator or a crystal oscillator between the XIN and XOUT pins. To use an external clock, input it to the XIN pin and leave the XOUT pin open. XCIN clock input (N, D version) XCIN I XCIN clock output (N, D version) XCOUT O INT interrupt input INT0, INT1, INT3 I INT interrupt input pins Key input interrupt KI0 to KI3 I Key input interrupt input pins Timer RA These pins are provided for XCIN clock generation circuit I/O. Connect a crystal oscillator between the XCIN and XCOUT pins. To use an external clock, input it to the XCIN pin and leave the XCOUT pin open. TRAO O Timer RA output pin TRAIO I/O Timer RA I/O pin Timer RB TRBO O Timer RB output pin Timer RC TRCCLK I External clock input pin TRCTRG Timer RE Serial interface I2C bus interface I External trigger input pin TRCIOA, TRCIOB, TRCIOC, TRCIOD I/O Sharing output-compare output / input-capture input / PWM / PWM2 output pins TREO O Timer RE output pin CLK0, CLK1 I/O RXD0, RXD1 I Receive data input pin TXD0, TXD1 O Transmit data output pin SCL I/O Clock I/O pin SDA I/O Data I/O pin Clock synchronous SSI serial I/O with chip SCS select SSCK Clock I/O pin I/O Data I/O pin I/O Chip-select signal I/O pin I/O Clock I/O pin SSO I/O Data I/O pin Reference voltage input VREF I Reference voltage input pin to A/D converter A/D converter AN0 to AN11 I Analog input pins to A/D converter I/O port P0_0 to P0_7, P1_0 to P1_7, P3_1, P3_3 to P3_7, P4_5, P5_3, P5_4 I/O Input port P4_2, P4_6, P4_7 I: Input O: Output Rev.2.10 Sep 26, 2008 REJ03B0168-0210 I I/O: Input and output Page 10 of 69 CMOS I/O ports. Each port has an I/O select direction register, allowing each pin in the port to be directed for input or output individually. Any port set to input can be set to use a pull-up resistor or not by a program. P1_0 to P1_7 also function as LED drive ports (N, D version). Input-only ports R8C/26 Group, R8C/27 Group Table 1.6 Pin Number 1. Overview Pin Name Information by Pin Number Control Pin Port 1 P3_5 2 P3_7 3 RESET 4 XOUT/XCOUT(2) VSS/AVSS P4_7 XIN/XCIN(2) VCC/AVCC MODE P4_6 5 6 7 8 9 10 11 P4_5 INT0 P1_7 INT1 P3_6 (INT1)(1) 12 13 14 15 P1_6 16 P1_5 17 18 P3_1 P5_4 P5_3 (RXD1)(1, 3) TRAIO (TXD1)/ (RXD1)(1, 3) TRBO TRCIOD TRCIOC CLK0 VRFF 22 (SSI)(1) (INT1)(1) (TRAIO)(1) P1_3 KI3 (TRBO) AN11 RXD0 P1_4 19 20 21 Interrupt I/O Pin Functions for of Peripheral Modules Clock A/D Serial Synchronous I2C bus Timer Interface Serial I/O with Interface Converter Chip Select (1) SSCK SCL (TRCIOD) RXD1/ TRAO SSO (TXD1)(1, 3) TXD0 P1_2 KI2 TRCIOB AN10 P4_2 P1_1 KI1 TRCIOA/ TRCTRG AN9 P1_0 KI0 23 P3_3 INT3 24 P3_4 25 26 27 28 29 30 31 32 P0_7 P0_6 P0_5 P0_4 P0_3 P0_2 P0_1 P0_0 AN8 TRCCLK SSI (TRCIOC)(1) SCS CLK1 TREO (TXD1)(1, 3) SDA AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 NOTES: 1. This can be assigned to the pin in parentheses by a program. 2. XCIN, XCOUT can be used only for N or D version. 3. For the combination of using pins TXD1 and RXD1, refer to Figure 15.7 Registers PINSR1 and PMR of Hardware Manual (REJ09B0278). Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 11 of 69 R8C/26 Group, R8C/27 Group 2. 2. Central Processing Unit (CPU) Central Processing Unit (CPU) Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a register bank. There are two sets of register bank. b31 b15 R2 R3 b8b7 b0 R0H (high-order of R0) R0L (low-order of R0) R1H (high-order of R1) R1L (low-order of R1) Data registers(1) R2 R3 A0 A1 FB b19 b15 Address registers(1) Frame base register(1) b0 Interrupt table register INTBL INTBH The 4 high order bits of INTB are INTBH and the 16 low order bits of INTB are INTBL. b19 b0 Program counter PC b15 b0 USP User stack pointer ISP Interrupt stack pointer SB Static base register b15 b0 FLG b15 b8 IPL b7 Flag register b0 U I O B S Z D C Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved bit Processor interrupt priority level Reserved bit NOTE: 1. These registers comprise a register bank. There are two register banks. Figure 2.1 CPU Registers Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 12 of 69 R8C/26 Group, R8C/27 Group 2.1 2. Central Processing Unit (CPU) Data Registers (R0, R1, R2, and R3) R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is analogous to R2R0. 2.2 Address Registers (A0 and A1) A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 to be used as a 32-bit address register (A1A0). 2.3 Frame Base Register (FB) FB is a 16-bit register for FB relative addressing. 2.4 Interrupt Table Register (INTB) INTB is a 20-bit register that indicates the start address of an interrupt vector table. 2.5 Program Counter (PC) PC is 20 bits wide and indicates the address of the next instruction to be executed. 2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) The stack pointers (SP), USP, and ISP, are each 16 bits wide. The U flag of FLG is used to switch between USP and ISP. 2.7 Static Base Register (SB) SB is a 16-bit register for SB relative addressing. 2.8 Flag Register (FLG) FLG is an 11-bit register indicating the CPU state. 2.8.1 Carry Flag (C) The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit. 2.8.2 Debug Flag (D) The D flag is for debugging only. Set it to 0. 2.8.3 Zero Flag (Z) The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0. 2.8.4 Sign Flag (S) The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0. 2.8.5 Register Bank Select Flag (B) Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1. 2.8.6 Overflow Flag (O) The O flag is set to 1 when an operation results in an overflow; otherwise to 0. Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 13 of 69 R8C/26 Group, R8C/27 Group 2.8.7 2. Central Processing Unit (CPU) Interrupt Enable Flag (I) The I flag enables maskable interrupts. Interrupt are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0 when an interrupt request is acknowledged. 2.8.8 Stack Pointer Select Flag (U) ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1. The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software interrupt numbers 0 to 31 is executed. 2.8.9 Processor Interrupt Priority Level (IPL) IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7. If a requested interrupt has higher priority than IPL, the interrupt is enabled. 2.8.10 Reserved Bit If necessary, set to 0. When read, the content is undefined. Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 14 of 69 R8C/26 Group, R8C/27 Group 3. 3. Memory Memory 3.1 R8C/26 Group Figure 3.1 is a Memory Map of R8C/26 Group. The R8C/26 group has 1 Mbyte of address space from addresses 00000h to FFFFFh. The internal ROM is allocated lower addresses, beginning with address 0FFFFh. For example, a 16-Kbyte internal ROM area is allocated addresses 0C000h to 0FFFFh. The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each interrupt routine. The internal RAM is allocated higher addresses beginning with address 00400h. For example, a 1-Kbyte internal RAM area is allocated addresses 00400h to 007FFh. The internal RAM is used not only for storing data but also for calling subroutines and as stacks when interrupt requests are acknowledged. Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use and cannot be accessed by users. 00000h 002FFh SFR (Refer to 4. Special Function Registers (SFRs)) 00400h Internal RAM 0XXXh 0FFDCh Undefined instruction Overflow BRK instruction Address match Single step Watchdog timer/oscillation stop detection/voltage monitor 0YYYYh (Reserved) (Reserved) Reset Internal ROM (program ROM) 0FFFFh 0FFFFh FFFFFh NOTE: 1. The blank regions are reserved. Do not access locations in these regions. Internal ROM Part Number R5F21262SNFP, R5F21262SDFP, R5F21262SNXXXFP, R5F21262SDXXXFP Internal RAM Size Address 0YYYYh Size Address 0XXXXh 8 Kbytes 0E000h 512 bytes 005FFh 16 Kbytes 0C000h 1 Kbyte 007FFh 24 Kbytes 0A000h 1.5 Kbytes 009FFh 32 Kbytes 08000h 1.5 Kbytes 009FFh R5F21264SNFP, R5F21264SDFP, R5F21264JFP, R5F21264KFP, R5F21264SNXXXFP, R5F21264SDXXXFP, R5F21264JXXXFP, R5F21264KXXXFP R5F21265SNFP, R5F21265SDFP R5F21265SNXXXFP, R5F21265SDXXXFP R5F21266SNFP, R5F21266SDFP, R5F21266JFP, R5F21266KFP, R5F21266SNXXXFP, R5F21266SDXXXFP, R5F21266JXXXFP, R5F21266KXXXFP Figure 3.1 Memory Map of R8C/26 Group Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 15 of 69 R8C/26 Group, R8C/27 Group 3.2 3. Memory R8C/27 Group Figure 3.2 is a Memory Map of R8C/27 Group. The R8C/27 group has 1 Mbyte of address space from addresses 00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. For example, a 16-Kbyte internal ROM area is allocated addresses 0C000h to 0FFFFh. The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each interrupt routine. The internal ROM (data flash) is allocated addresses 02400h to 02BFFh. The internal RAM area is allocated higher addresses, beginning with address 00400h. For example, a 1-Kbyte internal RAM is allocated addresses 00400h to 007FFh. The internal RAM is used not only for storing data but also for calling subroutines and as stacks when interrupt requests are acknowledged. Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use and cannot be accessed by users. 00000h 002FFh SFR (Refer to 4. Special Function Registers (SFRs)) 00400h Internal RAM 0XXXXh 02400h 0FFDCh Internal ROM (data flash)(1) 02BFFh Undefined instruction Overflow BRK instruction Address match Single step 0YYYYh Watchdog timer/oscillation stop detection/voltage monitor (Reserved) (Reserved) Reset Internal ROM (program ROM) 0FFFFh 0FFFFh FFFFFh NOTES: 1. Data flash block A (1 Kbyte) and B (1 Kbyte) are shown. 2. The blank regions are reserved. Do not access locations in these regions. Internal ROM Part Number R5F21272SNFP, R5F21272SDFP, R5F21272SNXXXFP, R5F21272SDXXXFP R5F21274SNFP, R5F21274SDFP, R5F21274JFP, R5F21274KFP, R5F21274SNXXXFP, R5F21274SDXXXFP, Internal RAM Size Address 0YYYYh Size Address 0XXXXh 8 Kbytes 0E000h 512 bytes 005FFh 16 Kbytes 0C000h 1 Kbyte 007FFh 24 Kbytes 0A000h 1.5 Kbytes 009FFh 32 Kbytes 08000h 1.5 Kbytes 009FFh R5F21274JXXXFP, R5F21274KXXXFP R5F21275SNFP, R5F21275SDFP, R5F21275SNXXXFP, R5F21275SDXXXFP R5F21276SNFP, R5F21276SDFP, R5F21276JFP, R5F21276KFP, R5F21276SNXXXFP, R5F21276SDXXXFP, R5F21276JXXXFP, R5F21276KXXXFP Figure 3.2 Memory Map of R8C/27 Group Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 16 of 69 R8C/26 Group, R8C/27 Group 4. 4. Special Function Registers (SFRs) Special Function Registers (SFRs) An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.7 list the special function registers. Table 4.1 Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh SFR Information (1)(1) Register Symbol After reset Processor Mode Register 0 Processor Mode Register 1 System Clock Control Register 0 System Clock Control Register 1 PM0 PM1 CM0 CM1 00h 00h 01101000b 00100000b Protect Register PRCR 00h Oscillation Stop Detection Register Watchdog Timer Reset Register Watchdog Timer Start Register Watchdog Timer Control Register Address Match Interrupt Register 0 OCD WDTR WDTS WDC RMAD0 Address Match Interrupt Enable Register Address Match Interrupt Register 1 AIER RMAD1 00000100b XXh XXh 00X11111b 00h 00h 00h 00h 00h 00h 00h Count Source Protection Mode Register CSPR 00h 10000000b(2) High-Speed On-Chip Oscillator Control Register 0 High-Speed On-Chip Oscillator Control Register 1 High-Speed On-Chip Oscillator Control Register 2 FRA0 FRA1 FRA2 00h When shipping 00h Clock Prescaler Reset Flag High-Speed On-Chip Oscillator Control Register 4(3) CPSRF FRA4 00h When shipping High-Speed On-Chip Oscillator Control Register 6(3) High-Speed On-Chip Oscillator Control Register 7(3) FRA6 FRA7 When shipping When shipping X: Undefined NOTES: 1. The blank regions are reserved. Do not access locations in these regions. 2. The CSPROINI bit in the OFS register is set to 0. 3. In J, K version these regions are reserved. Do not access locations in these regions. Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 17 of 69 R8C/26 Group, R8C/27 Group Table 4.2 Address 0030h 0031h 0032h 4. Special Function Registers (SFRs) SFR Information (2)(1) Register Symbol After reset Voltage Detection Register 1 (2) Voltage Detection Register 2 (2) VCA1 VCA2 00001000b 0033h 0034h 0035h 0036h Voltage Monitor 1 Circuit Control Register (5) VW1C 0037h 0038h Voltage Monitor 2 Circuit Control Register (5) Voltage Monitor 0 Circuit Control Register (6) VW2C VW0C Timer RC Interrupt Control Register TRCIC XXXXX000b Timer RE Interrupt Control Register TREIC XXXXX000b Key Input Interrupt Control Register A/D Conversion Interrupt Control Register SSU/IIC bus Interrupt Control Register(9) KUPIC ADIC SSUIC/IICIC XXXXX000b XXXXX000b XXXXX000b UART0 Transmit Interrupt Control Register UART0 Receive Interrupt Control Register UART1 Transmit Interrupt Control Register UART1 Receive Interrupt Control Register S0TIC S0RIC S1TIC S1RIC XXXXX000b XXXXX000b XXXXX000b XXXXX000b Timer RA Interrupt Control Register TRAIC XXXXX000b Timer RB Interrupt Control Register INT1 Interrupt Control Register INT3 Interrupt Control Register TRBIC INT1IC INT3IC XXXXX000b XX00X000b XX00X000b INT0 Interrupt Control Register INT0IC XX00X000b * N, D version 00h(3) 00100000b(4) * J, K version 00h(7) 01000000b(8) * N, D version 00001000b * J, K version 0000X000b(7) 0100X001b(8) 00h 0000X000b(3) 0100X001b(4) 0039h 003Fh 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0060h 006Fh 0070h 007Fh X: Undefined NOTES: 1. The blank regions are reserved. Do not access locations in these regions. 2. (N, D version) Software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect this register. (J, K version) Software reset, watchdog timer reset, or voltage monitor 2 reset do not affect this register. 3. The LVD0ON bit in the OFS register is set to 1 and hardware reset. 4. Power-on reset, voltage monitor 0 reset or the LVD0ON bit in the OFS register is set to 0, and hardware reset. 5. (N, D version) Software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect b2 and b3. (J, K version) Software reset, watchdog timer reset, or voltage monitor 2 reset do not affect b2 and b3. 6. (N, D version) Software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect this register. (J, K version) These regions are reserved. Do not access locations in these regions. 7. The LVD1ON bit in the OFS register is set to 1 and hardware reset. 8. Power-on reset, voltage monitor 1 reset, or the LVD1ON bit in the OFS register is set to 0 and hardware reset. 9. Selected by the IICSEL bit in the PMR register. Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 18 of 69 R8C/26 Group, R8C/27 Group Table 4.3 Address 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h 00A1h 00A2h 00A3h 00A4h 00A5h 00A6h 00A7h 00A8h 00A9h 00AAh 00ABh 00ACh 00ADh 00AEh 00AFh 00B0h 00B1h 00B2h 00B3h 00B4h 00B5h 00B6h 00B7h 00B8h 00B9h 00BAh 00BBh 00BCh 00BDh 00BEh 00BFh 4. Special Function Registers (SFRs) SFR Information (3)(1) Register Symbol UART0 Transmit/Receive Mode Register UART0 Bit Rate Register UART0 Transmit Buffer Register U0MR U0BRG U0TB UART0 Transmit/Receive Control Register 0 UART0 Transmit/Receive Control Register 1 UART0 Receive Buffer Register U0C0 U0C1 U0RB UART1 Transmit/Receive Mode Register UART1 Bit Rate Register UART1 Transmit Buffer Register U1MR U1BRG U1TB UART1 Transmit/Receive Control Register 0 UART1 Transmit/Receive Control Register 1 UART1 Receive Buffer Register U1C0 U1C1 U1RB SS Control Register H / IIC bus Control Register 1(2) SS Control Register L / IIC bus Control Register 2(2) SS Mode Register / IIC bus Mode Register(2) SS Enable Register / IIC bus Interrupt Enable Register(2) SS Status Register / IIC bus Status Register(2) SS Mode Register 2 / Slave Address Register(2) SS Transmit Data Register / IIC bus Transmit Data Register(2) SS Receive Data Register / IIC bus Receive Data Register(2) SSCRH / ICCR1 SSCRL / ICCR2 SSMR / ICMR SSER / ICIER SSSR / ICSR SSMR2 / SAR SSTDR / ICDRT SSRDR / ICDRR X: Undefined NOTES: 1. The blank regions are reserved. Do not access locations in these regions. 2. Selected by the IICSEL bit in the PMR register. Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 19 of 69 After reset 00h XXh XXh XXh 00001000b 00000010b XXh XXh 00h XXh XXh XXh 00001000b 00000010b XXh XXh 00h 01111101b 00011000b 00h 00h / 0000X000b 00h FFh FFh R8C/26 Group, R8C/27 Group Table 4.4 Address 00C0h 00C1h 00C2h 00C3h 00C4h 00C5h 00C6h 00C7h 00C8h 00C9h 00CAh 00CBh 00CCh 00CDh 00CEh 00CFh 00D0h 00D1h 00D2h 00D3h 00D4h 00D5h 00D6h 00D7h 00D8h 00D9h 00DAh 00DBh 00DCh 00DDh 00DEh 00DFh 00E0h 00E1h 00E2h 00E3h 00E4h 00E5h 00E6h 00E7h 00E8h 00E9h 00EAh 00EBh 00ECh 00EDh 00EEh 00EFh 00F0h 00F1h 00F2h 00F3h 00F4h 00F5h 00F6h 00F7h 00F8h 00F9h 00FAh 00FBh 00FCh 00FDh 00FEh 00FFh 4. Special Function Registers (SFRs) SFR Information (4)(1) Register Symbol After reset A/D Register AD XXh XXh A/D Control Register 2 ADCON2 00h A/D Control Register 0 A/D Control Register 1 ADCON0 ADCON1 00h 00h Port P0 Register Port P1 Register Port P0 Direction Register Port P1 Direction Register P0 P1 PD0 PD1 00h 00h 00h 00h Port P3 Register P3 00h Port P3 Direction Register Port P4 Register Port P5 Register Port P4 Direction Register Port P5 Direction Register PD3 P4 P5 PD4 PD5 00h 00h 00h 00h 00h Pin Select Register 1 Pin Select Register 2 Pin Select Register 3 Port Mode Register External Input Enable Register INT Input Filter Select Register Key Input Enable Register Pull-Up Control Register 0 Pull-Up Control Register 1 Port P1 Drive Capacity Control Register(2) PINSR1 PINSR2 PINSR3 PMR INTEN INTF KIEN PUR0 PUR1 P1DRR 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h X: Undefined NOTES: 1. The blank regions are reserved. Do not access locations in these regions. 2. In J, K version these regions are reserved. Do not access locations in these regions. Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 20 of 69 R8C/26 Group, R8C/27 Group Table 4.5 Address 0100h 0101h 0102h 0103h 0104h 0105h 0106h 0107h 0108h 0109h 010Ah 010Bh 010Ch 010Dh 010Eh 010Fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h 0119h 011Ah 011Bh 011Ch 011Dh 011Eh 011Fh 0120h 0121h 0122h 0123h 0124h 0125h 0126h 0127h 0128h 0129h 012Ah 012Bh 012Ch 012Dh 012Eh 012Fh 0130h 0131h 0132h 0133h 0134h 0135h 0136h 0137h 0138h 0139h 013Ah 013Bh 013Ch 013Dh 013Eh 013Fh 4. Special Function Registers (SFRs) SFR Information (5)(1) Timer RA Control Register Timer RA I/O Control Register Timer RA Mode Register Timer RA Prescaler Register Timer RA Register Register Symbol TRACR TRAIOC TRAMR TRAPRE TRA 00h 00h 00h FFh FFh LIN Control Register LIN Status Register Timer RB Control Register Timer RB One-Shot Control Register Timer RB I/O Control Register Timer RB Mode Register Timer RB Prescaler Register Timer RB Secondary Register Timer RB Primary Register LINCR LINST TRBCR TRBOCR TRBIOC TRBMR TRBPRE TRBSC TRBPR 00h 00h 00h 00h 00h 00h FFh FFh FFh Timer RE Second Data Register / Counter Data Register Timer RE Minute Data Register / Compare Data Register Timer RE Hour Data Register(2) Timer RE Day of Week Data Register(2) Timer RE Control Register 1 Timer RE Control Register 2 Timer RE Count Source Select Register TRESEC TREMIN TREHR TREWK TRECR1 TRECR2 TRECSR 00h 00h 00h 00h 00h 00h 00001000b Timer RC Mode Register Timer RC Control Register 1 Timer RC Interrupt Enable Register Timer RC Status Register Timer RC I/O Control Register 0 Timer RC I/O Control Register 1 Timer RC Counter TRCMR TRCCR1 TRCIER TRCSR TRCIOR0 TRCIOR1 TRC Timer RC General Register A TRCGRA Timer RC General Register B TRCGRB Timer RC General Register C TRCGRC Timer RC General Register D TRCGRD Timer RC Control Register 2 Timer RC Digital Filter Function Select Register Timer RC Output Master Enable Register TRCCR2 TRCDF TRCOER 01001000b 00h 01110000b 01110000b 10001000b 10001000b 00h 00h FFh FFh FFh FFh FFh FFh FFh FFh 00011111b 00h 01111111b NOTES: 1. The blank regions are reserved. Do not access locations in these regions. 2. In J, K version these regions are reserved. Do not access locations in these regions. Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 21 of 69 After reset R8C/26 Group, R8C/27 Group Table 4.6 4. Special Function Registers (SFRs) SFR Information (6)(1) Address 0140h 0141h 0142h 0143h 0144h 0145h 0146h 0147h 0148h 0149h 014Ah 014Bh 014Ch 014Dh 014Eh 014Fh 0150h 0151h 0152h 0153h 0154h 0155h 0156h 0157h 0158h 0159h 015Ah 015Bh 015Ch 015Dh 015Eh 015Fh 0160h 0161h 0162h 0163h 0164h 0165h 0166h 0167h 0168h 0169h 016Ah 016Bh 016Ch 016Dh 016Eh 016Fh 0170h 0171h 0172h 0173h 0174h 0175h 0176h 0177h 0178h 0179h 017Ah 017Bh 017Ch 017Dh 017Eh 017Fh Register NOTE: 1. The blank regions are reserved. Do not access locations in these regions. Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 22 of 69 Symbol After reset R8C/26 Group, R8C/27 Group Table 4.7 Address 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018Ah 018Bh 018Ch 018Dh 018Eh 018Fh 0190h 0191h 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019Ah 019Bh 019Ch 019Dh 019Eh 019Fh 01A0h 01A1h 01A2h 01A3h 01A4h 01A5h 01A6h 01A7h 01A8h 01A9h 01AAh 01ABh 01ACh 01ADh 01AEh 01AFh 01B0h 01B1h 01B2h 01B3h 01B4h 01B5h 01B6h 01B7h 01B8h 01B9h 01BAh 01BBh 01BCh 01BDh 01BEh 01BFh FFFFh 4. Special Function Registers (SFRs) SFR Information (7)(1) Register Symbol After reset Flash Memory Control Register 4 FMR4 01000000b Flash Memory Control Register 1 FMR1 1000000Xb Flash Memory Control Register 0 FMR0 00000001b Option Function Select Register OFS (Note 2) X: Undefined NOTES: 1. The blank regions are reserved. Do not access locations in these regions. 2. The OFS register cannot be changed by a program. Use a flash programmer to write to it. Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 23 of 69 R8C/26 Group, R8C/27 Group 5. 5. Electrical Characteristics Electrical Characteristics 5.1 N, D Version Table 5.1 Absolute Maximum Ratings Symbol Parameter Rated Value Unit -0.3 to 6.5 V Input voltage -0.3 to VCC + 0.3 V VO Output voltage -0.3 to VCC + 0.3 V Pd Power dissipation 500 mW Topr Operating ambient temperature -20 to 85 (N version) / -40 to 85 (D version) C Tstg Storage temperature -65 to 150 C VCC/AVCC Supply voltage VI Table 5.2 IOH(sum) IOH(peak) Sum of all pins IOH(peak) Min. 2.2 - 0.8 VCC 0 - Standard Typ. - 0 - - - Max. 5.5 - VCC 0.2 VCC -160 Sum of all pins IOH(avg) - - -80 mA Except P1_0 to P1_7 P1_0 to P1_7 Except P1_0 to P1_7 P1_0 to P1_7 Sum of all pins IOL(peak) - - - - - - - - - - -10 -40 -5 -20 160 mA mA mA mA mA - - 80 mA - - - - 0 0 0 0 0 0 0 - - - - - - - - - - - - 125 10 40 5 20 20 10 5 70 20 10 5 - mA mA mA mA MHz MHz MHz kHz MHz MHz MHz kHz - - 20 MHz - - 10 MHz - - 5 MHz Parameter Supply voltage Supply voltage Input "H" voltage Input "L" voltage Peak sum output "H" current Average sum output "H" current Peak output "H" current IOH(avg) Average output "H" current IOL(sum) Peak sum output "L" currents Average sum Sum of all pins IOL(avg) output "L" currents Peak output "L" Except P1_0 to P1_7 currents P1_0 to P1_7 Average output Except P1_0 to P1_7 "L" current P1_0 to P1_7 XIN clock input oscillation frequency IOL(sum) IOL(peak) IOL(avg) f(XIN) f(XCIN) - Topr = 25C Recommended Operating Conditions Symbol VCC/AVCC VSS/AVSS VIH VIL IOH(sum) Condition XCIN clock input oscillation frequency System clock OCD2 = 0 XlN clock selected OCD2 = 1 On-chip oscillator clock selected Conditions 3.0 V VCC 5.5 V 2.7 V VCC < 3.0 V 2.2 V VCC < 2.7 V 2.2 V VCC 5.5 V 3.0 V VCC 5.5 V 2.7 V VCC < 3.0 V 2.2 V VCC < 2.7 V FRA01 = 0 Low-speed on-chip oscillator clock selected FRA01 = 1 High-speed on-chip oscillator clock selected 3.0 V VCC 5.5 V FRA01 = 1 High-speed on-chip oscillator clock selected 2.7 V VCC 5.5 V FRA01 = 1 High-speed on-chip oscillator clock selected 2.2 V VCC 5.5 V NOTES: 1. VCC = 2.2 to 5.5 V at Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified. 2. The average output current indicates the average value of current measured during 100 ms. Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 24 of 69 Unit V V V V mA R8C/26 Group, R8C/27 Group Table 5.3 5. Electrical Characteristics A/D Converter Characteristics Symbol Parameter - Resolution - Absolute accuracy Conditions Standard Min. Typ. Max. Unit Vref = AVCC - - 10 Bits 10-bit mode AD = 10 MHz, Vref = AVCC = 5.0 V - - 3 LSB 8-bit mode AD = 10 MHz, Vref = AVCC = 5.0 V - - 2 LSB 10-bit mode AD = 10 MHz, Vref = AVCC = 3.3 V - - 5 LSB 8-bit mode AD = 10 MHz, Vref = AVCC = 3.3 V - - 2 LSB 10-bit mode AD = 5 MHz, Vref = AVCC = 2.2 V - - 5 LSB 8-bit mode AD = 5 MHz, Vref = AVCC = 2.2 V - - 2 LSB Rladder Resistor ladder Vref = AVCC 10 - 40 k tconv Conversion time 10-bit mode AD = 10 MHz, Vref = AVCC = 5.0 V 3.3 - - s AD = 10 MHz, Vref = AVCC = 5.0 V 2.8 - - s 2.2 - AVCC V 0 - AVCC V 0.25 - 10 MHz 8-bit mode Vref Reference voltage VIA Analog input voltage(2) - A/D operating clock frequency Without sample and hold Vref = AVCC = 2.7 to 5.5 V With sample and hold Vref = AVCC = 2.7 to 5.5 V 1 - 10 MHz Without sample and hold Vref = AVCC = 2.2 to 5.5 V 0.25 - 5 MHz With sample and hold Vref = AVCC = 2.2 to 5.5 V 1 - 5 MHz NOTES: 1. AVCC = 2.2 to 5.5 V at Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified. 2. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in 8-bit mode. P0 P1 P3 30pF P4 P5 Figure 5.1 Ports P0, P1, and P3 to P5 Timing Measurement Circuit Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 25 of 69 R8C/26 Group, R8C/27 Group Table 5.4 Flash Memory (Program ROM) Electrical Characteristics Symbol - 5. Electrical Characteristics Parameter Program/erase endurance(2) Conditions Standard Unit Min. Typ. Max. R8C/26 Group 100(3) - - times R8C/27 Group 1,000(3) - - times s - Byte program time - 50 400 - Block erase time - 0.4 9 s td(SR-SUS) Time delay from suspend request until suspend - - 97 + CPU clock x 6 cycles s - Interval from erase start/restart until following suspend request 650 - - s - Interval from program start/restart until following suspend request 0 - - ns - Time from suspend until program/erase restart - - 3 + CPU clock x 4 cycles s - Program, erase voltage 2.7 - 5.5 V - Read voltage 2.2 - 5.5 V - Program, erase temperature 0 - 60 C - Data hold time(7) 20 - - year Ambient temperature = 55C NOTES: 1. VCC = 2.7 to 5.5 V at Topr = 0 to 60C, unless otherwise specified. 2. Definition of programming/erasure endurance The programming and erasure endurance is defined on a per-block basis. If the programming and erasure endurance is n (n = 100 or 1,000), each block can be erased n times. For example, if 1,024 1-byte writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. However, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed). 4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. It is also advisable to retain data on the erasure endurance of each block and limit the number of erase operations to a certain number. 5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative. 7. The data hold time includes time that the power supply is off or the clock is not supplied. Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 26 of 69 R8C/26 Group, R8C/27 Group Table 5.5 5. Electrical Characteristics Flash Memory (Data flash Block A, Block B) Electrical Characteristics(4) Symbol Parameter Conditions Standard Min. Typ. Max. Unit - Program/erase endurance(2) 10,000(3) - - times - Byte program time (program/erase endurance 1,000 times) - 50 400 s - Byte program time (program/erase endurance > 1,000 times) - 65 - s - Block erase time (program/erase endurance 1,000 times) - 0.2 9 s - Block erase time (program/erase endurance > 1,000 times) - 0.3 - s td(SR-SUS) Time delay from suspend request until suspend - - 97 + CPU clock x 6 cycles s - Interval from erase start/restart until following suspend request 650 - - s - Interval from program start/restart until following suspend request 0 - - ns - Time from suspend until program/erase restart - - 3 + CPU clock x 4 cycles s - Program, erase voltage 2.7 - 5.5 V - Read voltage 2.2 - 5.5 V - Program, erase temperature -20(8) - 85 C - Data hold time(9) 20 - - year Ambient temperature = 55C NOTES: 1. VCC = 2.7 to 5.5 V at Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified. 2. Definition of programming/erasure endurance The programming and erasure endurance is defined on a per-block basis. If the programming and erasure endurance is n (n = 10,000), each block can be erased n times. For example, if 1,024 1-byte writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. However, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed). 4. Standard of block A and block B when program and erase endurance exceeds 1,000 times. Byte program time to 1,000 times is the same as that in program ROM. 5. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. In addition, averaging the erasure endurance between blocks A and B can further reduce the actual erasure endurance. It is also advisable to retain data on the erasure endurance of each block and limit the number of erase operations to a certain number. 6. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 7. Customers desiring program/erase failure rate information should contact their Renesas technical support representative. 8. -40C for D version. 9. The data hold time includes time that the power supply is off or the clock is not supplied. Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 27 of 69 R8C/26 Group, R8C/27 Group 5. Electrical Characteristics Suspend request (maskable interrupt request) FMR46 Clock-dependent time Fixed time Access restart td(SR-SUS) Figure 5.2 Table 5.6 Time delay until Suspend Voltage Detection 0 Circuit Electrical Characteristics Symbol Parameter Condition Vdet0 Voltage detection level - Voltage detection circuit self power consumption td(E-A) Waiting time until voltage detection circuit operation starts(2) Vccmin MCU operating voltage minimum value VCA25 = 1, VCC = 5.0 V Standard Unit Min. Typ. Max. 2.2 2.3 2.4 V - 0.9 - A - - 300 s 2.2 - - V NOTES: 1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = -20 to 85C (N version) / -40 to 85C (D version). 2. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2 register to 0. Table 5.7 Voltage Detection 1 Circuit Electrical Characteristics Symbol Vdet1 Parameter Condition Voltage detection level(4) - Voltage monitor 1 interrupt request generation - Voltage detection circuit self power consumption td(E-A) Waiting time until voltage detection circuit operation starts(3) time(2) VCA26 = 1, VCC = 5.0 V Standard Min. Typ. Max. 2.70 2.85 3.00 Unit V - 40 - s - 0.6 - A - - 100 s NOTES: 1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = -20 to 85C (N version) / -40 to 85C (D version). 2. Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1. 3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2 register to 0. 4. This parameter shows the voltage detection level when the power supply drops. The voltage detection level when the power supply rises is higher than the voltage detection level when the power supply drops by approximately 0.1 V. Table 5.8 Voltage Detection 2 Circuit Electrical Characteristics Symbol Vdet2 Parameter Condition Voltage detection level - Voltage monitor 2 interrupt request generation - Voltage detection circuit self power consumption td(E-A) Waiting time until voltage detection circuit operation starts(3) time(2) VCA27 = 1, VCC = 5.0 V Standard Min. Typ. Max. 3.3 3.6 3.9 Unit V - 40 - s - 0.6 - A - - 100 s NOTES: 1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = -20 to 85C (N version) / -40 to 85C (D version). 2. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2. 3. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2 register to 0. Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 28 of 69 R8C/26 Group, R8C/27 Group Table 5.9 5. Electrical Characteristics Power-on Reset Circuit, Voltage Monitor 0 Reset Electrical Characteristics(3) Symbol Parameter Condition Standard Min. Typ. Unit Max. Vpor1 Power-on reset valid voltage(4) - - 0.1 V Vpor2 Power-on reset or voltage monitor 0 reset valid voltage 0 - Vdet0 V trth External power VCC rise gradient(2) 20 - - mV/msec NOTES: 1. The measurement condition is Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified. 2. This condition (external power VCC rise gradient) does not apply if VCC 1.0 V. 3. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVD0ON bit in the OFS register to 0, the VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the VCA2 register to 1. 4. tw(por1) indicates the duration the external power VCC must be held below the effective voltage (Vpor1) to enable a power on reset. When turning on the power for the first time, maintain tw(por1) for 30 s or more if -20C Topr 85C, maintain tw(por1) for 3,000 s or more if -40C Topr < -20C. Vdet0(3) Vdet0(3) 2.2 V trth trth External Power VCC Vpor2 Vpor1 Sampling time(1, 2) tw(por1) Internal reset signal ("L" valid) 1 x 32 fOCO-S 1 x 32 fOCO-S NOTES: 1. When using the voltage monitor 0 digital filter, ensure that the voltage is within the MCU operation voltage range (2.2 V or above) during the sampling time. 2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit of Hardware Manual for details. 3. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection Circuit of Hardware Manual for details. Figure 5.3 Reset Circuit Electrical Characteristics Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 29 of 69 R8C/26 Group, R8C/27 Group Table 5.10 High-speed On-Chip Oscillator Circuit Electrical Characteristics Symbol fOCO40M 5. Electrical Characteristics Parameter High-speed on-chip oscillator frequency temperature * supply voltage dependence High-speed on-chip oscillator frequency when correction value in FRA7 register is written to FRA1 register(4) - Value in FRA1 register after reset - Oscillation frequency adjustment unit of highspeed on-chip oscillator - Oscillation stability time - Self power consumption at oscillation Condition Standard Unit Min. Typ. Max. VCC = 4.75 to 5.25 V 0C Topr 60C(2) 39.2 40 40.8 MHz VCC = 3.0 to 5.5 V -20C Topr 85C(2) 38.8 40 41.2 MHz VCC = 3.0 to 5.5 V -40C Topr 85C(2) 38.4 40 41.6 MHz VCC = 2.7 to 5.5 V -20C Topr 85C(2) 38 40 42 MHz VCC = 2.7 to 5.5 V -40C Topr 85C(2) 37.6 40 42.4 MHz VCC = 2.2 to 5.5 V -20C Topr 85C(3) 35.2 40 44.8 MHz VCC = 2.2 to 5.5 V -40C Topr 85C(3) 34 40 46 MHz VCC = 5.0 V 10% -20C Topr 85C(2) 38.8 40 40.8 MHz VCC = 5.0 V 10% -40C Topr 85C(2) 38.4 40 40.8 MHz - 36.864 - MHz -3% - 3% % 08h(3) - F7h(3) - Adjust FRA1 register (value after reset) to -1 - +0.3 - MHz - 10 100 s VCC = 5.0 V, Topr = 25C - 400 - A VCC = 5.0 V, Topr = 25C VCC = 3.0 to 5.5 V -20C Topr 85C NOTES: 1. VCC = 2.2 to 5.5 V, Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified. 2. These standard values show when the FRA1 register value after reset is assumed. 3. These standard values show when the corrected value of the FRA6 register is written to the FRA1 register. 4. This enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0% when the serial interface is used in UART mode. Table 5.11 Low-speed On-Chip Oscillator Circuit Electrical Characteristics Symbol Parameter Condition Standard Min. Typ. Max. Unit fOCO-S Low-speed on-chip oscillator frequency 30 125 250 - Oscillation stability time - 10 100 s - Self power consumption at oscillation - 15 - A VCC = 5.0 V, Topr = 25C kHz NOTE: 1. VCC = 2.2 to 5.5 V, Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified. Table 5.12 Power Supply Circuit Timing Characteristics Symbol Parameter Condition Standard Min. Typ. Max. Unit td(P-R) Time for internal power supply stabilization during power-on(2) 1 - 2000 s td(R-S) STOP exit time(3) - - 150 s NOTES: 1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = 25C. 2. Waiting time until the internal power supply generation circuit stabilizes during power-on. 3. Time until system clock supply starts after the interrupt is acknowledged to exit stop mode. Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 30 of 69 R8C/26 Group, R8C/27 Group Table 5.13 Symbol 5. Electrical Characteristics Timing Requirements of Clock Synchronous Serial I/O with Chip Select(1) Parameter Conditions Standard Min. Typ. Unit Max. tSUCYC SSCK clock cycle time 4 - - tCYC(2) tHI SSCK clock "H" width 0.4 - 0.6 tSUCYC tLO SSCK clock "L" width 0.4 - 0.6 tSUCYC tRISE SSCK clock rising time Master - - 1 tCYC(2) Slave - - 1 s tFALL SSCK clock falling time Master - - 1 tCYC(2) - - 1 s tSU SSO, SSI data input setup time 100 - - ns tH SSO, SSI data input hold time 1 - - tCYC(2) tLEAD Slave SCS setup time Slave 1tCYC + 50 - - ns tLAG SCS hold time Slave 1tCYC + 50 - - ns tOD SSO, SSI data output delay time tSA SSI slave access time tOR SSI slave out open time - - 1 tCYC(2) 2.7 V VCC 5.5 V - - 1.5tCYC + 100 ns 2.2 V VCC < 2.7 V - - 1.5tCYC + 200 ns 2.7 V VCC 5.5 V - - 1.5tCYC + 100 ns 2.2 V VCC < 2.7 V - - 1.5tCYC + 200 ns NOTES: 1. VCC = 2.2 to 5.5 V, VSS = 0 V at Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified. 2. 1tCYC = 1/f1(s) Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 31 of 69 R8C/26 Group, R8C/27 Group 5. Electrical Characteristics 4-Wire Bus Communication Mode, Master, CPHS = 1 VIH or VOH SCS (output) VIH or VOH tHI tFALL tRISE SSCK (output) (CPOS = 1) tLO tHI SSCK (output) (CPOS = 0) tLO tSUCYC SSO (output) tOD SSI (input) tSU tH 4-Wire Bus Communication Mode, Master, CPHS = 0 VIH or VOH SCS (output) VIH or VOH tHI tFALL tRISE SSCK (output) (CPOS = 1) tLO tHI SSCK (output) (CPOS = 0) tLO tSUCYC SSO (output) tOD SSI (input) tSU tH CPHS, CPOS: Bits in SSMR register Figure 5.4 I/O Timing of Clock Synchronous Serial I/O with Chip Select (Master) Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 32 of 69 R8C/26 Group, R8C/27 Group 5. Electrical Characteristics 4-Wire Bus Communication Mode, Slave, CPHS = 1 VIH or VOH SCS (input) VIH or VOH tLEAD tHI tFALL tRISE tLAG SSCK (input) (CPOS = 1) tLO tHI SSCK (input) (CPOS = 0) tLO tSUCYC SSO (input) tSU tH SSI (output) tSA tOD tOR 4-Wire Bus Communication Mode, Slave, CPHS = 0 VIH or VOH SCS (input) VIH or VOH tHI tLEAD tFALL tRISE tLAG SSCK (input) (CPOS = 1) tLO tHI SSCK (input) (CPOS = 0) tLO tSUCYC SSO (input) tSU tH SSI (output) tSA tOD tOR CPHS, CPOS: Bits in SSMR register Figure 5.5 I/O Timing of Clock Synchronous Serial I/O with Chip Select (Slave) Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 33 of 69 R8C/26 Group, R8C/27 Group 5. Electrical Characteristics tHI VIH or VOH SSCK VIH or VOH tLO tSUCYC SSO (output) tOD SSI (input) tSU Figure 5.6 tH I/O Timing of Clock Synchronous Serial I/O with Chip Select (Clock Synchronous Communication Mode) Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 34 of 69 R8C/26 Group, R8C/27 Group Table 5.14 5. Electrical Characteristics Timing Requirements of I2C bus Interface(1) tSCL SCL input cycle time tSCLH SCL input "H" width Standard Typ. - 12tCYC + 600(2) - 3tCYC + 300(2) tSCLL SCL input "L" width 500(2) tsf tSP SCL, SDA input fall time SCL, SDA input spike pulse rejection time tBUF SDA input bus-free time 5tCYC(2) - 1tCYC(2) - tSTAH Start condition input hold time 3tCYC(2) - - ns tSTAS Retransmit start condition input setup time 3tCYC(2) - - ns tSTOP Stop condition input setup time 3tCYC(2) - - ns tSDAS Data input setup time - - ns tSDAH Data input hold time 1tCYC + 20(2) 0 - - ns Symbol Parameter Condition Min. 5tCYC + - - Unit Max. - ns - ns - ns - 300 - ns ns - NOTES: 1. VCC = 2.2 to 5.5 V, VSS = 0 V and Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified. 2. 1tCYC = 1/f1(s) VIH SDA VIL tBUF tSTAH tSCLH tSTAS tSP tSTOP SCL P(2) S(1) tsf Sr(3) tSCLL tsr tSCL NOTES: 1. Start condition 2. Stop condition 3. Retransmit start condition Figure 5.7 I/O Timing of I2C bus Interface Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 35 of 69 P(2) tSDAS tSDAH ns R8C/26 Group, R8C/27 Group Table 5.15 Electrical Characteristics (1) [VCC = 5 V] Symbol VOH Parameter Output "H" voltage Except P1_0 to P1_7, XOUT P1_0 to P1_7 XOUT VOL Output "L" voltage Except P1_0 to P1_7, XOUT P1_0 to P1_7 XOUT VT+-VT- 5. Electrical Characteristics Hysteresis Condition IOH = -5 mA IOH = -200 A Drive capacity HIGH Drive capacity LOW Drive capacity HIGH Drive capacity LOW IOL = 5 mA IOL = 200 A Drive capacity HIGH Drive capacity LOW Drive capacity HIGH Drive capacity LOW INT0, INT1, INT3, KI0, KI1, KI2, KI3, TRAIO, RXD0, RXD1, CLK0, CLK1, SSI, SCL, SDA, SSO RESET IIH IIL RPULLUP RfXIN RfXCIN VRAM Input "H" current Input "L" current Pull-up resistance Feedback XIN resistance Feedback XCIN resistance RAM hold voltage VI = 5 V, VCC = 5 V VI = 0 V, VCC = 5 V VI = 0 V, VCC = 5 V During stop mode IOH = -20 mA IOH = -5 mA IOH = -1 mA IOH = -500 A IOL = 20 mA IOL = 5 mA IOL = 1 mA IOL = 500 A Min. VCC - 2.0 VCC - 0.5 VCC - 2.0 VCC - 2.0 VCC - 2.0 VCC - 2.0 - - - - - - 0.1 Standard Typ. - - - - - - - - - - - - 0.5 Max. VCC VCC VCC VCC VCC VCC 2.0 0.45 2.0 2.0 2.0 2.0 - Unit V V V V V V V V V V V V V 0.1 1.0 - V - - - 30 - 50 1.0 5.0 -5.0 167 - A - A k M - 18 - M 1.8 - - V NOTE: 1. VCC = 4.2 to 5.5 V at Topr = -20 to 85C (N version) / -40 to 85C (D version), f(XIN) = 20 MHz, unless otherwise specified. Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 36 of 69 R8C/26 Group, R8C/27 Group Table 5.16 Symbol ICC 5. Electrical Characteristics Electrical Characteristics (2) [Vcc = 5 V] (Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified.) Parameter Condition Power supply current High-speed (VCC = 3.3 to 5.5 V) clock mode Single-chip mode, output pins are open, other pins are VSS High-speed on-chip oscillator mode Low-speed on-chip oscillator mode Low-speed clock mode Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 37 of 69 XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 16 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN = 16 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator on fOCO = 20 MHz Low-speed on-chip oscillator on = 125 kHz No division XIN clock off High-speed on-chip oscillator on fOCO = 20 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator on fOCO = 10 MHz Low-speed on-chip oscillator on = 125 kHz No division XIN clock off High-speed on-chip oscillator on fOCO = 10 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8, FMR47 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz FMR47 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz Program operation on RAM Flash memory off, FMSTP = 1 Min. - Standard Typ. Max. 10 17 Unit mA - 9 15 mA - 6 - mA - 5 - mA - 4 - mA - 2.5 - mA - 10 15 mA - 4 - mA - 5.5 10 mA - 2.5 - mA - 130 300 A - 130 300 A - 30 - A R8C/26 Group, R8C/27 Group Table 5.17 Symbol ICC 5. Electrical Characteristics Electrical Characteristics (3) [Vcc = 5 V] (Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified.) Parameter Condition Power supply current Wait mode (VCC = 3.3 to 5.5 V) Single-chip mode, output pins are open, other pins are VSS Stop mode Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 38 of 69 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (high drive) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (low drive) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off, Topr = 25C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 XIN clock off, Topr = 85C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 Min. - Standard Typ. Max. 25 75 Unit A - 23 60 A - 4.0 - A - 2.2 - A - 0.8 3.0 A - 1.2 - A R8C/26 Group, R8C/27 Group 5. Electrical Characteristics Timing Requirements (Unless Otherwise Specified: VCC = 5 V, VSS = 0 V at Topr = 25C) [VCC = 5 V] Table 5.18 XIN Input, XCIN Input Symbol tc(XIN) tWH(XIN) tWL(XIN) tc(XCIN) tWH(XCIN) tWL(XCIN) Standard Min. Max. 50 - 25 - 25 - 14 - 7 - 7 - Parameter XIN input cycle time XIN input "H" width XIN input "L" width XCIN input cycle time XCIN input "H" width XCIN input "L" width tC(XIN) Unit ns ns ns s s s VCC = 5 V tWH(XIN) XIN input tWL(XIN) Figure 5.8 Table 5.19 XIN Input and XCIN Input Timing Diagram when VCC = 5 V TRAIO Input Symbol tc(TRAIO) tWH(TRAIO) tWL(TRAIO) Standard Min. Max. 100 - 40 - 40 - Parameter TRAIO input cycle time TRAIO input "H" width TRAIO input "L" width tC(TRAIO) tWH(TRAIO) TRAIO input tWL(TRAIO) Figure 5.9 TRAIO Input Timing Diagram when VCC = 5 V Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 39 of 69 Unit ns ns ns VCC = 5 V R8C/26 Group, R8C/27 Group Table 5.20 5. Electrical Characteristics Serial Interface Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) Standard Min. Max. 200 - 100 - 100 - - 50 0 - 50 - 90 - Parameter CLKi input cycle time CLKi input "H" width CLKi input "L" width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time Unit ns ns ns ns ns ns ns i = 0 or 1 VCC = 5 V tC(CK) tW(CKH) CLKi tW(CKL) th(C-Q) TXDi td(C-Q) tsu(D-C) th(C-D) RXDi i = 0 or 1 Figure 5.10 Table 5.21 Serial Interface Timing Diagram when VCC = 5 V External Interrupt INTi (i = 0, 1, 3) Input tW(INH) INTi input "H" width Standard Min. Max. (1) - 250 tW(INL) INTi input "L" width 250(2) Symbol Parameter - Unit ns ns NOTES: 1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater. 2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater. VCC = 5 V tW(INL) INTi input tW(INH) i = 0, 1, 3 Figure 5.11 External Interrupt INTi Input Timing Diagram when VCC = 5 V Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 40 of 69 R8C/26 Group, R8C/27 Group Table 5.22 Electrical Characteristics (3) [VCC = 3 V] Symbol VOH 5. Electrical Characteristics Parameter Output "H" voltage Except P1_0 to P1_7, XOUT P1_0 to P1_7 Output "L" voltage IIH IIL RPULLUP RfXIN RfXCIN VRAM Input "H" current Input "L" current Pull-up resistance Feedback resistance Feedback resistance RAM hold voltage Max. VCC Unit V VCC - 0.5 - VCC V IOH = -1 mA VCC - 0.5 - VCC V IOH = -0.1 mA VCC - 0.5 - VCC V IOH = -50 A VCC - 0.5 - VCC V - - 0.5 V Drive capacity HIGH Drive capacity LOW Drive capacity HIGH Drive capacity LOW IOL = 5 mA - - 0.5 V IOL = 1 mA - - 0.5 V IOL = 0.1 mA - - 0.5 V IOL = 50 A - - 0.5 V INT0, INT1, INT3, KI0, KI1, KI2, KI3, TRAIO, RXD0, RXD1, CLK0, CLK1, SSI, SCL, SDA, SSO 0.1 0.3 - V RESET 0.1 0.4 - V - - - 66 - - 1.8 160 3.0 18 - 4.0 -4.0 500 - - - A - Except P1_0 to P1_7, XOUT P1_0 to P1_7 Hysteresis Standard Typ. - IOH = -5 mA XOUT VT+-VT- IOH = -1 mA Min. VCC - 0.5 Drive capacity HIGH Drive capacity LOW Drive capacity HIGH Drive capacity LOW IOL = 1 mA XOUT VOL Condition VI = 3 V, VCC = 3 V VI = 0 V, VCC = 3 V VI = 0 V, VCC = 3 V XIN XCIN During stop mode A k M M V NOTE: 1. VCC = 2.7 to 3.3 V at Topr = -20 to 85C (N version) / -40 to 85C (D version), f(XIN) = 10 MHz, unless otherwise specified. Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 41 of 69 R8C/26 Group, R8C/27 Group Table 5.23 Symbol ICC 5. Electrical Characteristics Electrical Characteristics (4) [Vcc = 3 V] (Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified.) Parameter Condition Power supply current High-speed (VCC = 2.7 to 3.3 V) clock mode Single-chip mode, output pins are open, other pins are VSS High-speed on-chip oscillator mode Low-speed on-chip oscillator mode Low-speed clock mode Wait mode Stop mode Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 42 of 69 XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator on fOCO = 10 MHz Low-speed on-chip oscillator on = 125 kHz No division XIN clock off High-speed on-chip oscillator on fOCO = 10 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8, FMR47 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz FMR47 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz Program operation on RAM Flash memory off, FMSTP = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (high drive) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (low drive) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off, Topr = 25C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 XIN clock off, Topr = 85C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 Min. - Standard Typ. Max. 6 - Unit mA - 2 - mA - 5 9 mA - 2 - mA - 130 300 A - 130 300 A - 30 - A - 25 70 A - 23 55 A - 3.8 - A - 2.0 - A - 0.7 3.0 A - 1.1 - A R8C/26 Group, R8C/27 Group 5. Electrical Characteristics Timing requirements (Unless Otherwise Specified: VCC = 3 V, VSS = 0 V at Topr = 25C) [VCC = 3 V] Table 5.24 XIN Input, XCIN Input Symbol tc(XIN) tWH(XIN) tWL(XIN) tc(XCIN) tWH(XCIN) tWL(XCIN) Standard Min. Max. 100 - 40 - 40 - 14 - 7 - 7 - Parameter XIN input cycle time XIN input "H" width XIN input "L" width XCIN input cycle time XCIN input "H" width XCIN input "L" width tC(XIN) Unit ns ns ns s s s VCC = 3 V tWH(XIN) XIN input tWL(XIN) XIN Input and XCIN Input Timing Diagram when VCC = 3 V Figure 5.12 Table 5.25 TRAIO Input Symbol tc(TRAIO) tWH(TRAIO) tWL(TRAIO) Standard Min. Max. 300 - 120 - 120 - Parameter TRAIO input cycle time TRAIO input "H" width TRAIO input "L" width tC(TRAIO) tWH(TRAIO) TRAIO input tWL(TRAIO) Figure 5.13 TRAIO Input Timing Diagram when VCC = 3 V Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 43 of 69 Unit ns ns ns VCC = 3 V R8C/26 Group, R8C/27 Group Table 5.26 5. Electrical Characteristics Serial Interface Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) Standard Min. Max. 300 - 150 - 150 - - 80 0 - 70 - 90 - Parameter CLKi input cycle time CLKi input "H" width CLKi Input "L" width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time Unit ns ns ns ns ns ns ns i = 0 or 1 VCC = 3 V tC(CK) tW(CKH) CLKi tW(CKL) th(C-Q) TXDi td(C-Q) tsu(D-C) th(C-D) RXDi i = 0 or 1 Figure 5.14 Table 5.27 Serial Interface Timing Diagram when VCC = 3 V External Interrupt INTi (i = 0, 1, 3) Input INTi input "H" width Standard Min. Max. - 380(1) INTi input "L" width 380(2) Symbol tW(INH) tW(INL) Parameter Unit - ns ns NOTES: 1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater. 2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater. VCC = 3 V tW(INL) INTi input tW(INH) i = 0, 1, 3 Figure 5.15 External Interrupt INTi Input Timing Diagram when VCC = 3 V Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 44 of 69 R8C/26 Group, R8C/27 Group Table 5.28 Electrical Characteristics (5) [VCC = 2.2 V] Symbol VOH 5. Electrical Characteristics Parameter Output "H" voltage Except P1_0 to P1_7, XOUT P1_0 to P1_7 Output "L" voltage IIH IIL RPULLUP RfXIN RfXCIN VRAM Input "H" current Input "L" current Pull-up resistance Feedback resistance Feedback resistance RAM hold voltage Max. VCC V - VCC V IOH = -1 mA VCC - 0.5 - VCC V IOH = -0.1 mA VCC - 0.5 - VCC V IOH = -50 A VCC - 0.5 - VCC V - - 0.5 V Drive capacity HIGH Drive capacity LOW Drive capacity HIGH Drive capacity LOW IOL = 2 mA - - 0.5 V IOL = 1 mA - - 0.5 V IOL = 0.1 mA - - 0.5 V IOL = 50 A - - 0.5 V INT0, INT1, INT3, KI0, KI1, KI2, KI3, TRAIO, RXD0, RXD1, CLK0, CLK1, SSI, SCL, SDA, SSO 0.05 0.3 - V RESET 0.05 0.15 - V - - - 100 - - 1.8 200 5 35 - 4.0 -4.0 600 - - - A - VI = 2.2 V VI = 0 V VI = 0 V XIN XCIN During stop mode NOTE: 1. VCC = 2.2 V at Topr = -20 to 85C (N version) / -40 to 85C (D version), f(XIN) = 5 MHz, unless otherwise specified. Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Unit VCC - 0.5 Except P1_0 to P1_7, XOUT P1_0 to P1_7 Hysteresis Standard Typ. - IOH = -2 mA XOUT VT+-VT- IOH = -1 mA Min. VCC - 0.5 Drive capacity HIGH Drive capacity LOW Drive capacity HIGH Drive capacity LOW IOL = 1 mA XOUT VOL Condition Page 45 of 69 A k M M V R8C/26 Group, R8C/27 Group Table 5.29 Symbol ICC 5. Electrical Characteristics Electrical Characteristics (6) [Vcc = 2.2 V] (Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified.) Parameter Condition Power supply current High-speed (VCC = 2.2 to 2.7 V) clock mode Single-chip mode, output pins are open, other pins are VSS High-speed on-chip oscillator mode Low-speed on-chip oscillator mode Low-speed clock mode Wait mode Stop mode Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 46 of 69 XIN = 5 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 5 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator on fOCO = 5 MHz Low-speed on-chip oscillator on = 125 kHz No division XIN clock off High-speed on-chip oscillator on fOCO = 5 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8, FMR47 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz FMR47 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz Program operation on RAM Flash memory off, FMSTP = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (high drive) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (low drive) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off, Topr = 25C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 XIN clock off, Topr = 85C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 Min. - Standard Typ. Max. 3.5 - Unit mA - 1.5 - mA - 3.5 - mA - 1.5 - mA - 100 230 A - 100 230 A - 25 - A - 22 60 A - 20 55 A - 3.0 - A - 1.8 - A - 0.7 3.0 A - 1.1 - A R8C/26 Group, R8C/27 Group 5. Electrical Characteristics Timing requirements (Unless Otherwise Specified: VCC = 2.2 V, VSS = 0 V at Topr = 25C) [VCC = 2.2 V] Table 5.30 XIN Input, XCIN Input Symbol tc(XIN) tWH(XIN) tWL(XIN) tc(XCIN) tWH(XCIN) tWL(XCIN) Standard Min. Max. 200 - 90 - 90 - 14 - 7 - 7 - Parameter XIN input cycle time XIN input "H" width XIN input "L" width XCIN input cycle time XCIN input "H" width XCIN input "L" width tC(XIN) Unit ns ns ns s s s VCC = 2.2 V tWH(XIN) XIN input tWL(XIN) XIN Input and XCIN Input Timing Diagram when VCC = 2.2 V Figure 5.16 Table 5.31 TRAIO Input Symbol tc(TRAIO) tWH(TRAIO) tWL(TRAIO) Standard Min. Max. 500 - 200 - 200 - Parameter TRAIO input cycle time TRAIO input "H" width TRAIO input "L" width tC(TRAIO) tWH(TRAIO) TRAIO input tWL(TRAIO) Figure 5.17 TRAIO Input Timing Diagram when VCC = 2.2 V Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 47 of 69 Unit ns ns ns VCC = 2.2 V R8C/26 Group, R8C/27 Group Table 5.32 5. Electrical Characteristics Serial Interface Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) Standard Min. Max. 800 - 400 - 400 - - 200 0 - 150 - 90 - Parameter CLKi input cycle time CLKi input "H" width CLKi input "L" width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time Unit ns ns ns ns ns ns ns i = 0 or 1 VCC = 2.2 V tC(CK) tW(CKH) CLKi tW(CKL) th(C-Q) TXDi td(C-Q) tsu(D-C) th(C-D) RXDi i = 0 or 1 Figure 5.18 Table 5.33 Serial Interface Timing Diagram when VCC = 2.2 V External Interrupt INTi (i = 0, 1, 3) Input tW(INH) INTi input "H" width Standard Min. Max. (1) - 1000 tW(INL) INTi input "L" width 1000(2) Symbol Parameter - Unit ns ns NOTES: 1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater. 2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater. VCC = 2.2 V tW(INL) INTi input tW(INH) i = 0, 1, 3 Figure 5.19 External Interrupt INTi Input Timing Diagram when VCC = 2.2 V Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 48 of 69 R8C/26 Group, R8C/27 Group 5.2 5. Electrical Characteristics J, K Version Table 5.34 Absolute Maximum Ratings Symbol VCC/AVCC VI VO Pd Parameter Supply voltage Input voltage Output voltage Power dissipation Topr Operating ambient temperature Tstg Storage temperature Table 5.35 IOH(peak) IOH(avg) IOL(sum) IOL(peak) IOL(avg) f(XIN) - -40 C Topr 85 C 85 C Topr 125 C Rated Value -0.3 to 6.5 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 300 125 -40 to 85 (J version) / -40 to 125 (K version) -65 to 150 Unit V V V mW mW C C Recommended Operating Conditions Symbol VCC/AVCC VSS/AVSS VIH VIL IOH(sum) Condition Parameter Supply voltage Supply voltage Input "H" voltage Input "L" voltage Peak sum output Sum of all pins "H" current IOH(peak) Peak output "H" current Average output "H" current Peak sum output Sum of all pins "L" currents IOL(peak) Peak output "L" currents Average output "L" current XIN clock input oscillation frequency System clock OCD2 = 0 XlN clock selected OCD2 = 1 On-chip oscillator clock selected Conditions 3.0 V VCC 5.5 V (other than K version) 3.0 V VCC 5.5 V (K version) 2.7 V VCC < 3.0 V 3.0 V VCC 5.5 V (other than K version) 3.0 V VCC 5.5 V (K version) 2.7 V VCC < 3.0 V FRA01 = 0 Low-speed on-chip oscillator clock selected FRA01 = 1 High-speed on-chip oscillator clock selected (other than K version) FRA01 = 1 High-speed on-chip oscillator clock selected Min. 2.7 - 0.8 VCC 0 - Standard Typ. - 0 - - - Max. 5.5 - VCC 0.2 VCC -60 - - -10 mA - - -5 mA - - 60 mA - - 10 mA - - 5 mA 0 - 20 MHz 0 0 0 - 16 10 20 MHz MHz MHz 0 0 - - 125 16 10 - MHz MHz kHz - - 20 MHz - - 10 MHz - - - NOTES: 1. VCC = 2.7 to 5.5 V at Topr = -40 to 85C (J version) / -40 to 125C (K version), unless otherwise specified. 2. The average output current indicates the average value of current measured during 100 ms. Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 49 of 69 Unit V V V V mA R8C/26 Group, R8C/27 Group Table 5.36 A/D Converter Characteristics Symbol - - Rladder tconv Vref VIA - 5. Electrical Characteristics Parameter Resolution Absolute accuracy Conditions Vref = AVCC AD = 10 MHz, Vref = AVCC = 5.0 V AD = 10 MHz, Vref = AVCC = 5.0 V AD = 10 MHz, Vref = AVCC = 3.3 V AD = 10 MHz, Vref = AVCC = 3.3 V Vref = AVCC AD = 10 MHz, Vref = AVCC = 5.0 V AD = 10 MHz, Vref = AVCC = 5.0 V 10-bit mode 8-bit mode 10-bit mode 8-bit mode Resistor ladder Conversion time 10-bit mode 8-bit mode Reference voltage Analog input voltage(2) A/D operating Without sample and hold clock frequency With sample and hold Min. - - - - - 10 3.3 2.8 2.7 0 0.25 1 Standard Typ. Max. - 10 - 3 - 2 - 5 - 2 - 40 - - - - - AVCC - AVCC - - 10 10 Unit Bits LSB LSB LSB LSB k s s V V MHz MHz NOTES: 1. AVCC = 2.7 to 5.5 V at Topr = -40 to 85C (J version) / -40 to 125C (K version), unless otherwise specified. 2. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in 8-bit mode. P0 P1 P3 30pF P4 P5 Figure 5.20 Ports P0, P1, and P3 to P5 Timing Measurement Circuit Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 50 of 69 R8C/26 Group, R8C/27 Group Table 5.37 Flash Memory (Program ROM) Electrical Characteristics Symbol - - Parameter Program/erase endurance(2) - Byte program time Block erase time Time delay from suspend request until suspend Interval from erase start/restart until following suspend request Interval from program start/restart until following suspend request Time from suspend until program/erase restart Program, erase voltage Read voltage Program, erase temperature - Data hold time(7) - td(SR-SUS) - - - - - 5. Electrical Characteristics Conditions Min. Standard Typ. - Unit Max. - times R8C/26 Group 100(3) R8C/27 Group 1,000(3) - - - - - times 50 0.4 - s 650 - 400 9 97 + CPU clock x 6 cycles - s 0 - - ns - - s 2.7 2.7 0 20 - 3 + CPU clock x 4 cycles 5.5 5.5 60 - Ambient temperature = 55C - - - s s V V C year NOTES: 1. VCC = 2.7 to 5.5 V at Topr = 0 to 60C, unless otherwise specified. 2. Definition of programming/erasure endurance The programming and erasure endurance is defined on a per-block basis. If the programming and erasure endurance is n (n = 100 or 1,000), each block can be erased n times. For example, if 1,024 1-byte writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. However, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed). 4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. It is also advisable to retain data on the erasure endurance of each block and limit the number of erase operations to a certain number. 5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative. 7. The data hold time includes time that the power supply is off or the clock is not supplied. Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 51 of 69 R8C/26 Group, R8C/27 Group Table 5.38 Flash Memory (Data flash Block A, Block B) Electrical Characteristics(4) Symbol - - - - - td(SR-SUS) - - - - - - - 5. Electrical Characteristics Parameter Conditions Program/erase endurance(2) Byte program time (program/erase endurance 1,000 times) Byte program time (program/erase endurance > 1,000 times) Block erase time (program/erase endurance 1,000 times) Block erase time (program/erase endurance > 1,000 times) Data hold Ambient temperature = 55C Standard Typ. - Unit Max. - times 50 400 s - 65 - s - 0.2 9 s - 0.3 - s - - s 650 - 97 + CPU clock x 6 cycles - s 0 - - ns - - s 2.7 2.7 -40 - 3 + CPU clock x 4 cycles 5.5 5.5 20 - 10,000(3) - Time delay from suspend request until suspend Interval from erase start/restart until following suspend request Interval from program start/restart until following suspend request Time from suspend until program/erase restart Program, erase voltage Read voltage Program, erase temperature time(9) Min. - - 85(8) - V V C year NOTES: 1. VCC = 2.7 to 5.5 V at Topr = -40 to 85C (J version) / -40 to 125C (K version), unless otherwise specified. 2. Definition of programming/erasure endurance The programming and erasure endurance is defined on a per-block basis. If the programming and erasure endurance is n (n = 10,000), each block can be erased n times. For example, if 1,024 1-byte writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. However, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed). 4. Standard of block A and block B when program and erase endurance exceeds 1,000 times. Byte program time to 1,000 times is the same as that in program ROM. 5. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. In addition, averaging the erasure endurance between blocks A and B can further reduce the actual erasure endurance. It is also advisable to retain data on the erasure endurance of each block and limit the number of erase operations to a certain number. 6. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 7. Customers desiring program/erase failure rate information should contact their Renesas technical support representative. 8. 125C for K version. 9. The data hold time includes time that the power supply is off or the clock is not supplied. Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 52 of 69 R8C/26 Group, R8C/27 Group 5. Electrical Characteristics Suspend request (maskable interrupt request) FMR46 Clock-dependent time Fixed time Access restart td(SR-SUS) Figure 5.21 Table 5.39 Time delay until Suspend Voltage Detection 1 Circuit Electrical Characteristics Symbol Parameter Vdet1 Voltage detection level(2, 4) td(Vdet1-A) Voltage monitor 1 reset generation time(5) Voltage detection circuit self power consumption Waiting time until voltage detection circuit operation starts(3) MCU operating voltage minimum value - td(E-A) Vccmin Condition VCA26 = 1, VCC = 5.0 V Min. 2.70 Standard Typ. Max. 2.85 3.0 Unit V - 40 200 s - 0.6 - - 100 A - 2.70 - - V s NOTES: 1. The measurement condition is VCC = 2.7 to 5.5 V and Topr = -40 to 85C (J version) / -40 to 125C (K version). 2. Hold Vdet2 > Vdet1. 3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2 register to 0. 4. This parameter shows the voltage detection level when the power supply drops. The voltage detection level when the power supply rises is higher than the voltage detection level when the power supply drops by approximately 0.1 V. 5. Time until the voltage monitor 1 reset is generated after the voltage passes Vdet1 when VCC falls. When using the digital filter, its sampling time is added to td(Vdet1-A). When using the voltage monitor 1 reset, maintain this time until VCC = 2.0 V after the voltage passes Vdet1 when the power supply falls. Table 5.40 Voltage Detection 2 Circuit Electrical Characteristics Symbol Vdet2 td(Vdet2-A) - td(E-A) Parameter Voltage detection level(2) Voltage monitor 2 reset/interrupt request generation time(3, 5) Voltage detection circuit self power consumption Waiting time until voltage detection circuit operation starts(4) Condition VCA27 = 1, VCC = 5.0 V Min. 3.3 Standard Typ. Max. 3.6 3.9 Unit V - 40 200 s - 0.6 - - 100 A - s NOTES: 1. The measurement condition is VCC = 2.7 to 5.5 V and Topr = -40 to 85C (J version) / -40 to 125C (K version). 2. Hold Vdet2 > Vdet1. 3. Time until the voltage monitor 2 reset/interrupt request is generated after the voltage passes Vdet2. 4. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2 register to 0. 5. When using the digital filter, its sampling time is added to td(Vdet2-A). When using the voltage monitor 2 reset, maintain this time until VCC = 2.0 V after the voltage passes Vdet2 when the power supply falls. Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 53 of 69 R8C/26 Group, R8C/27 Group Power-on Reset Circuit, Voltage Monitor 1 Reset Electrical Characteristics(3) Table 5.41 Symbol Vpor1 5. Electrical Characteristics trth Standard Typ. - Max. 0.1 0 - Vdet1 VCC 3.6 V 20(2) - - mV/msec VCC > 3.6 V 20(2) - 2,000 mV/msec Condition Power-on reset valid voltage(4) Power-on reset or voltage monitor 1 reset valid voltage External power VCC rise gradient Vpor2 Min. - Parameter Unit V V NOTES: 1. The measurement condition is Topr = -40 to 85C (J version) / -40 to 125C (K version), unless otherwise specified. 2. This condition (the minimum value of external power VCC rise gradient) does not apply if Vpor2 1.0 V. 3. To use the power-on reset function, enable voltage monitor 1 reset by setting the LVD1ON bit in the OFS register to 0, the VW1C0 and VW1C6 bits in the VW1C register to 1 respectively, and the VCA26 bit in the VCA2 register to 1. 4. tw(por1) indicates the duration the external power VCC must be held below the effective voltage (Vpor1) to enable a power on reset. When turning on the power for the first time, maintain tw(por1) for 30 s or more if -20C Topr 125C, maintain tw(por1) for 3,000 s or more if -40C Topr < -20C. Vdet1(3) External power VCC Vdet1(3) trth trth 2.0 V td(Vdet1-A) Vpor2 Vpor1 tw(por1) Sampling time(1, 2) Internal reset signal ("L" valid) 1 x 32 fOCO-S 1 x 32 fOCO-S NOTES: 1. When using the voltage monitor 1 digital filter, ensure VCC is 2.0 V or higher during the sampling time. 2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit of Hardware Manual for details. 3. Vdet1 indicates the voltage detection level of the voltage detection 1 circuit. Refer to 6. Voltage Detection Circuit of Hardware Manual for details. Figure 5.22 Reset Circuit Electrical Characteristics Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 54 of 69 R8C/26 Group, R8C/27 Group Table 5.42 High-speed On-Chip Oscillator Circuit Electrical Characteristics Symbol fOCO40M - 5. Electrical Characteristics Parameter High-speed on-chip oscillator frequency temperature * supply voltage dependence Value in FRA1 register after reset Oscillation frequency adjustment unit of highspeed on-chip oscillator Oscillation stability time Self power consumption at oscillation - - - Condition VCC = 4.75 to 5.25 V 0C Topr 60C(2) VCC = 3.0 to 5.5 V -20C Topr 85C(2) VCC = 3.0 to 5.5 V -40C Topr 85C(2) VCC = 3.0 to 5.5 V -40C Topr 125C(2) VCC = 2.7 to 5.5 V -40C Topr 125C(2) Adjust FRA1 register (value after reset) to -1 Min. 39.2 Standard Typ. 40 Max. 40.8 MHz 38.8 40 41.2 MHz 38.4 40 41.6 MHz 38 40 42 MHz 37.6 40 42.4 MHz 08h - - +0.3 F7h - - MHz - 10 400 100 - A VCC = 5.0 V, Topr = 25C - Unit s NOTES: 1. VCC = 2.7 to 5.5 V, Topr = -40 to 85C (J version) / -40 to 125C (K version), unless otherwise specified. 2. These standard values show when the FRA1 register value after reset is assumed. Table 5.43 Low-speed On-Chip Oscillator Circuit Electrical Characteristics Symbol fOCO-S - - Parameter Low-speed on-chip oscillator frequency Oscillation stability time Self power consumption at oscillation Condition VCC = 5.0 V, Topr = 25C Standard Typ. 125 10 15 Min. 40 - - Max. 250 100 - Unit kHz s A NOTE: 1. VCC = 2.7 to 5.5 V, Topr = -40 to 85C (J version) / -40 to 125C (K version), unless otherwise specified. Table 5.44 Power Supply Circuit Timing Characteristics Symbol Parameter td(P-R) Time for internal power supply stabilization during power-on(2) td(R-S) STOP exit time(3) Condition NOTES: 1. The measurement condition is VCC = 2.7 to 5.5 V and Topr = 25C. 2. Waiting time until the internal power supply generation circuit stabilizes during power-on. 3. Time until system clock supply starts after the interrupt is acknowledged to exit stop mode. Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 55 of 69 Min. 1 - Standard Typ. Max. - 2000 - 150 Unit s s R8C/26 Group, R8C/27 Group Table 5.45 Symbol Timing Requirements of Clock Synchronous Serial I/O with Chip Select(1) Parameter tSUCYC SSCK clock cycle time tHI tLO tRISE SSCK clock "H" width SSCK clock "L" width SSCK clock rising time tFALL 5. Electrical Characteristics SSCK clock falling time Conditions Standard Typ. - - Unit Max. - - - - - - - 100 1 - 1 - - tCYC(2) s ns - - tCYC(2) Slave 1tCYC + 50 - - ns Slave 1tCYC + 50 - - ns - - 1 - - - - 1.5tCYC + 100 1.5tCYC + 100 tCYC(2) ns ns Master Slave Master Slave SSO, SSI data input setup time SSO, SSI data input hold time tLEAD SCS setup time tOD SCS hold time SSO, SSI data output delay time tSA tOR SSI slave access time SSI slave out open time - 0.6 0.6 1 1 1 NOTES: 1. VCC = 2.7 to 5.5 V, VSS = 0 V at Topr = -40 to 85C (J version) / -40 to 125C (K version), unless otherwise specified. 2. 1tCYC = 1/f1(s) Rev.2.10 Sep 26, 2008 REJ03B0168-0210 tCYC(2) tSUCYC tSUCYC 0.4 0.4 - tSU tH tLAG Min. 4 Page 56 of 69 tCYC(2) s R8C/26 Group, R8C/27 Group 5. Electrical Characteristics 4-Wire Bus Communication Mode, Master, CPHS = 1 VIH or VOH SCS (output) VIH or VOH tHI tFALL tRISE SSCK (output) (CPOS = 1) tLO tHI SSCK (output) (CPOS = 0) tLO tSUCYC SSO (output) tOD SSI (input) tSU tH 4-Wire Bus Communication Mode, Master, CPHS = 0 VIH or VOH SCS (output) VIH or VOH tHI tFALL tRISE SSCK (output) (CPOS = 1) tLO tHI SSCK (output) (CPOS = 0) tLO tSUCYC SSO (output) tOD SSI (input) tSU tH CPHS, CPOS: Bits in SSMR register Figure 5.23 I/O Timing of Clock Synchronous Serial I/O with Chip Select (Master) Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 57 of 69 R8C/26 Group, R8C/27 Group 5. Electrical Characteristics 4-Wire Bus Communication Mode, Slave, CPHS = 1 VIH or VOH SCS (input) VIH or VOH tLEAD tHI tFALL tRISE tLAG SSCK (input) (CPOS = 1) tLO tHI SSCK (input) (CPOS = 0) tLO tSUCYC SSO (input) tSU tH SSI (output) tSA tOD tOR 4-Wire Bus Communication Mode, Slave, CPHS = 0 VIH or VOH SCS (input) VIH or VOH tHI tLEAD tFALL tRISE tLAG SSCK (input) (CPOS = 1) tLO tHI SSCK (input) (CPOS = 0) tLO tSUCYC SSO (input) tSU tH SSI (output) tSA tOD tOR CPHS, CPOS: Bits in SSMR register Figure 5.24 I/O Timing of Clock Synchronous Serial I/O with Chip Select (Slave) Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 58 of 69 R8C/26 Group, R8C/27 Group 5. Electrical Characteristics tHI VIH or VOH SSCK VIH or VOH tLO tSUCYC SSO (output) tOD SSI (input) tSU Figure 5.25 tH I/O Timing of Clock Synchronous Serial I/O with Chip Select (Clock Synchronous Communication Mode) Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 59 of 69 R8C/26 Group, R8C/27 Group Table 5.46 5. Electrical Characteristics Timing Requirements of I2C bus Interface(1) tSCL SCL input cycle time tSCLH SCL input "H" width Standard Typ. - 12tCYC + 600(2) - 3tCYC + 300(2) tSCLL SCL input "L" width 500(2) tsf tSP SCL, SDA input fall time SCL, SDA input spike pulse rejection time tBUF SDA input bus-free time 5tCYC(2) - 1tCYC(2) - tSTAH Start condition input hold time 3tCYC(2) - - ns tSTAS Retransmit start condition input setup time 3tCYC(2) - - ns tSTOP Stop condition input setup time 3tCYC(2) - - ns tSDAS Data input setup time - - ns tSDAH Data input hold time 1tCYC + 20(2) 0 - - ns Symbol Parameter Condition Min. 5tCYC + - - Unit Max. - ns - ns - ns - 300 - ns ns - NOTES: 1. VCC = 2.7 to 5.5 V, VSS = 0 V at Topr = -40 to 85C (J version) / -40 to 125C (K version), unless otherwise specified. 2. 1tCYC = 1/f1(s) VIH SDA VIL tBUF tSTAH tSCLH tSTAS tSP tSTOP SCL P(2) S(1) tsf Sr(3) tSCLL tsr tSCL NOTES: 1. Start condition 2. Stop condition 3. Retransmit start condition Figure 5.26 I/O Timing of I2C bus Interface Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 60 of 69 P(2) tSDAS tSDAH ns R8C/26 Group, R8C/27 Group Table 5.47 Electrical Characteristics (1) [VCC = 5 V] Symbol VOH Parameter Output "H" voltage Except XOUT XOUT VOL Output "L" voltage Except XOUT XOUT VT+-VT- 5. Electrical Characteristics Hysteresis Condition IOH = -5 mA IOH = -200 A Drive capacity HIGH Drive capacity LOW IOL = 5 mA IOL = 200 A Drive capacity HIGH Drive capacity LOW INT0, INT1, INT3, KI0, KI1, KI2, KI3, TRAIO, RXD0, RXD1, CLK0, CLK1, SSI, SCL, SDA, SSO RESET IIH IIL RPULLUP RfXIN VRAM Input "H" current Input "L" current Pull-up resistance Feedback resistance RAM hold voltage VI = 5 V, VCC = 5V VI = 0 V, VCC = 5V VI = 0 V, VCC = 5V XIN During stop mode IOH = -1 mA IOH = -500 A IOL = 1 mA IOL = 500 A Min. VCC - 2.0 VCC - 0.3 VCC - 2.0 VCC - 2.0 - - - - 0.1 Standard Typ. - - - - - - - - 0.5 Max. VCC VCC VCC VCC 2.0 0.45 2.0 2.0 - Unit V V V V V V V V V 0.1 1.0 - V - - - 30 - 50 1.0 5.0 -5.0 167 - A - A k M 2.0 - - V NOTE: 1. VCC = 4.2 to 5.5 V at Topr = -40 to 85C (J version) / -40 to 125C (K version), f(XIN) = 20 MHz, unless otherwise specified. Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 61 of 69 R8C/26 Group, R8C/27 Group Table 5.48 Symbol ICC 5. Electrical Characteristics Electrical Characteristics (2) [Vcc = 5 V] (Topr = -40 to 85C (J version) / -40 to 125C (K version), unless otherwise specified.) Parameter Condition Power supply current High-speed (VCC = 3.3 to 5.5 V) clock mode Single-chip mode, output pins are open, other pins are VSS High-speed on-chip oscillator mode Low-speed on-chip oscillator mode Wait mode Stop mode Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 62 of 69 XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division Min. - Standard Typ. Max. 10 17 Unit mA XIN = 16 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division - 9 15 mA XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division - 6 - mA XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 - 5 - mA XIN = 16 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 - 4 - mA XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 - 2.5 - mA XIN clock off High-speed on-chip oscillator on fOCO = 20 MHz (J version) Low-speed on-chip oscillator on = 125 kHz No division - 10 15 mA XIN clock off High-speed on-chip oscillator on fOCO = 20 MHz (J version) Low-speed on-chip oscillator on = 125 kHz Divide-by-8 - 4 - mA XIN clock off High-speed on-chip oscillator on fOCO = 10 MHz Low-speed on-chip oscillator on = 125 kHz No division - 5.5 10 mA XIN clock off High-speed on-chip oscillator on fOCO = 10 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 - 2.5 - mA XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8, FMR47 = 1 - 130 300 A XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 - 25 75 A XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 - 23 60 A XIN clock off, Topr = 25C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 - 0.8 3.0 A XIN clock off, Topr = 85C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 - 1.2 - A XIN clock off, Topr = 125C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 - 4.0 - A R8C/26 Group, R8C/27 Group 5. Electrical Characteristics Timing Requirements (Unless Otherwise Specified: VCC = 5 V, VSS = 0 V at Topr = 25C) [VCC = 5 V] Table 5.49 XIN Input Symbol tc(XIN) tWH(XIN) tWL(XIN) Standard Min. Max. 50 - 25 - 25 - Parameter XIN input cycle time XIN input "H" width XIN input "L" width tC(XIN) Unit ns ns ns VCC = 5 V tWH(XIN) XIN input tWL(XIN) Figure 5.27 Table 5.50 XIN Input Timing Diagram when VCC = 5 V TRAIO Input Symbol tc(TRAIO) tWH(TRAIO) tWL(TRAIO) Standard Min. Max. 100 - 40 - 40 - Parameter TRAIO input cycle time TRAIO input "H" width TRAIO input "L" width tC(TRAIO) tWH(TRAIO) TRAIO input tWL(TRAIO) Figure 5.28 TRAIO Input Timing Diagram when VCC = 5 V Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 63 of 69 Unit ns ns ns VCC = 5 V R8C/26 Group, R8C/27 Group Table 5.51 5. Electrical Characteristics Serial Interface Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) Standard Min. Max. 200 - 100 - 100 - - 50 0 - 50 - 90 - Parameter CLKi input cycle time CLKi input "H" width CLKi input "L" width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time Unit ns ns ns ns ns ns ns i = 0 or 1 VCC = 5 V tC(CK) tW(CKH) CLKi tW(CKL) th(C-Q) TXDi td(C-Q) tsu(D-C) th(C-D) RXDi i = 0 or 1 Figure 5.29 Table 5.52 Serial Interface Timing Diagram when VCC = 5 V External Interrupt INTi (i = 0, 1, 3) Input INTi input "H" width Standard Min. Max. - 250(1) INTi input "L" width 250(2) Symbol tW(INH) tW(INL) Parameter - Unit ns ns NOTES: 1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater. 2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater. VCC = 5 V tW(INL) INTi input tW(INH) i = 0, 1, 3 Figure 5.30 External Interrupt INTi Input Timing Diagram when VCC = 5 V Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 64 of 69 R8C/26 Group, R8C/27 Group Table 5.53 Electrical Characteristics (3) [VCC = 3 V] Symbol VOH VOL VT+-VT- IIH IIL RPULLUP RfXIN VRAM 5. Electrical Characteristics Parameter Output "H" voltage Except XOUT XOUT Output "L" voltage Input "H" current Input "L" current Pull-up resistance Feedback resistance RAM hold voltage IOH = -1 mA Drive capacity HIGH Drive capacity LOW IOL = 1 mA Drive capacity HIGH Drive capacity LOW Standard Typ. - - Max. VCC VCC Unit IOH = -0.1 mA Min. VCC - 0.5 VCC - 0.5 IOH = -50 A VCC - 0.5 - VCC V V V - - IOL = 0.1 mA - - 0.5 0.5 V V IOL = 50 A - - 0.5 V INT0, INT1, INT3, KI0, KI1, KI2, KI3, TRAIO, RXD0, RXD1, CLK0,CLK1, SSI, SCL, SDA, SSO 0.1 0.3 - V RESET 0.1 0.4 - V - - - 66 - 2.0 160 3.0 - 4.0 -4.0 500 - - A - Except XOUT XOUT Hysteresis Condition VI = 3 V, VCC = 3V VI = 0 V, VCC = 3V VI = 0 V, VCC = 3V XIN During stop mode A k M V NOTE: 1. VCC = 2.7 to 3.3 V at Topr = -40 to 85C (J version) / -40 to 125C (K version), f(XIN) = 10 MHz, unless otherwise specified. Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 65 of 69 R8C/26 Group, R8C/27 Group Table 5.54 Symbol ICC 5. Electrical Characteristics Electrical Characteristics (4) [Vcc = 3 V] (Topr = -40 to 85C (J version) / -40 to 125C (K version), unless otherwise specified.) Parameter Condition Power supply current High-speed (VCC = 2.7 to 3.3 V) clock mode Single-chip mode, output pins are open, other pins are VSS High-speed on-chip oscillator mode Low-speed on-chip oscillator mode Wait mode Stop mode Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 66 of 69 XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator on fOCO = 10 MHz Low-speed on-chip oscillator on = 125 kHz No division XIN clock off High-speed on-chip oscillator on fOCO = 10 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8, FMR47 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off, Topr = 25C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 XIN clock off, Topr = 85C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 XIN clock off, Topr = 125C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 Min. - Standard Typ. Max. 6 - Unit mA - 2 - mA - 5 9 mA - 2 - mA - 130 300 A - 25 70 A - 23 55 A - 0.7 3.0 A - 1.1 - A - 3.8 - A R8C/26 Group, R8C/27 Group 5. Electrical Characteristics Timing requirements (Unless Otherwise Specified: VCC = 3 V, VSS = 0 V at Topr = 25C) [VCC = 3 V] XIN Input Table 5.55 Symbol tc(XIN) tWH(XIN) tWL(XIN) Standard Min. Max. 100 - 40 - 40 - Parameter XIN input cycle time XIN input "H" width XIN input "L" width tC(XIN) Unit ns ns ns VCC = 3 V tWH(XIN) XIN input tWL(XIN) Figure 5.31 XIN Input Timing Diagram when VCC = 3 V Table 5.56 TRAIO Input Symbol tc(TRAIO) tWH(TRAIO) tWL(TRAIO) Standard Min. Max. 300 - 120 - 120 - Parameter TRAIO input cycle time TRAIO input "H" width TRAIO input "L" width tC(TRAIO) tWH(TRAIO) TRAIO input tWL(TRAIO) Figure 5.32 TRAIO Input Timing Diagram when VCC = 3 V Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 67 of 69 Unit ns ns ns VCC = 3 V R8C/26 Group, R8C/27 Group Table 5.57 5. Electrical Characteristics Serial Interface Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) Standard Min. Max. 300 - 150 - 150 - - 80 0 - 70 - 90 - Parameter CLKi input cycle time CLKi input "H" width CLKi Input "L" width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time Unit ns ns ns ns ns ns ns i = 0 or 1 VCC = 3 V tC(CK) tW(CKH) CLKi tW(CKL) th(C-Q) TXDi td(C-Q) tsu(D-C) th(C-D) RXDi i = 0 or 1 Figure 5.33 Table 5.58 Serial Interface Timing Diagram when VCC = 3 V External Interrupt INTi (i = 0, 1, 3) Input INTi input "H" width Standard Min. Max. - 380(1) INTi input "L" width 380(2) Symbol tW(INH) tW(INL) Parameter Unit - ns ns NOTES: 1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater. 2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater. VCC = 3 V tW(INL) INTi input tW(INH) i = 0, 1, 3 Figure 5.34 External Interrupt INTi Input Timing Diagram when VCC = 3 V Rev.2.10 Sep 26, 2008 REJ03B0168-0210 Page 68 of 69 R8C/26 Group, R8C/27 Group Package Dimensions Package Dimensions Diagrams showing the latest package dimensions and mounting information are available in the "Packages" section of the Renesas Technology website. JEITA Package Code P-LQFP32-7x7-0.80 RENESAS Code PLQP0032GB-A Previous Code 32P6U-A MASS[Typ.] 0.2g HD *1 D 24 17 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 16 25 bp c c1 HE *2 E b1 Reference Dimension in Millimeters Symbol 32 9 1 ZE Terminal cross section 8 ZD c A A1 F A2 Index mark L D E A2 HD HE A A1 bp b1 c c1 L1 y e Rev.2.10 Sep 26, 2008 REJ03B0168-0210 *3 Detail F bp Page 69 of 69 x e x y ZD ZE L L1 Min Nom Max 6.9 7.0 7.1 6.9 7.0 7.1 1.4 8.8 9.0 9.2 8.8 9.0 9.2 1.7 0.1 0.2 0 0.32 0.37 0.42 0.35 0.09 0.145 0.20 0.125 0 8 0.8 0.20 0.10 0.7 0.7 0.3 0.5 0.7 1.0 REVISION HISTORY REVISION HISTORY R8C/26 Group, R8C/27 Group Datasheet R8C/26 Group, R8C/27 Group Datasheet Description Rev. Date 0.10 Nov 14, 2005 - 0.20 Feb 06, 2006 2, 3 Page Summary First edition issued Table 1.1 Functions and Specifications for R8C/26Group and Table 1.2 Functions and Specifications for R8C/27 Group; Minimum instruction execution time and Supply voltage revised 9 Table 1.6 Pin Name Information by Pin Number; "XOUT" "XOUT/XCOUT" and "XIN" "XIN/XCIN" revised 18 Table 4.4 SFR Information (4); 00FEh: "DRR" "P1DRR" revised 19 Table 4.5 SFR Information (5); -0119h: "Timer RE Minute Data Register / Compare Register" "Timer RE Minute Data Register / Compare Data Register" -011Ah: "Timer RE Time Data Register" "Timer RE Hour Data Register" -011Bh: "Timer RE Day Data Register" "Timer RE Day of Week Data Register" revised 22 to 45 5. Electrical Characteristics added 1.00 Nov 08, 2006 All pages "Preliminary" deleted 2 Table 1.1 revised 3 Table 1.2 revised 4 Figure 1.1 revised 5 Table 1.3 revised 6 Table 1.4 revised 7 Figure 1.4 revised 9 Table 1.6 revised 15 Table 4.1; * 001Ch: "00h" "00h, 10000000b" revised * 000Fh: "000XXXXXb" "00X11111b" revised * 0029h: "High-Speed On-Chip Oscillator Control Register 4, FRA4, When shipping" added * 002Bh: "High-Speed On-Chip Oscillator Control Register 6, FRA6, When shipping" added * 0032h: "00h, 01000000b" "00h, 00100000b" revised * 0038h: "00001000b, 01001001b" "0000X000b, 0100X001b" revised * NOTE3 and 4 revised; NOTE6 added 18 Table 4.4; * 00E0h, 00E1h, 00E5h, 00E8h, 00E9h: "XXh" "00h" revised * 00FDh: "XX00000000b" "00h" revised 22 Table 5.2 revised 23 Figure 5.1 title revised 24 Table 5.4 revised 25 Table 5.5 revised 26 Figure 5.2 title revised and Table 5.7 NOTE4 added A-1 REVISION HISTORY Rev. Date 1.00 Nov 08, 2006 1.10 Nov 29, 2006 R8C/26 Group, R8C/27 Group Datasheet Description Page Summary 27 Table 5.9, Figure 5.3 revised and Table 5.10 deleted 28 Table 5.10, Table 5.11 revised 34 Table 5.15 revised 35 Table 5.16 revised 36 Table 5.17 revised 39 Table 5.22 revised 40 Table 5.23 revised 44 Table 5.29 revised 47 Package Dimensions; "Diagrams showing the latest...website." added All pages "J, K version" added 1 1 "J and K versions are under development...notice." added 1.1 revised 2 Table 1.1 revised 3 Table 1.2 revised 4 Figure 1.1 NOTE3 added 5 Table 1.3, Figure 1.2 revised 6 Table 1.4, Figure 1.3 revised 7 Figure 1.4 NOTE3 added 8 Table 1.5 revised 9 Table 1.6 NOTE2 added 13 Figure 3.1 revised 14 Figure 3.2 revised 15 Table 4.1; "0000h to 003Fh" "0000h to 002Fh" revised * NOTE3 added 16 Table 4.2; "0040h to 007Fh" "0030h to 007Fh" revised * 0032h, 0036h: "After reset" is revised * 0038h: NOTE revised * NOTES 2, 5, 6 revised and NOTE 7, 8 added 19 Table 4.5 NOTE2 added 28 Table 5.10 revised 48 to 66 5.2 J, K Version added 1.20 Jan 17, 2007 18 Table 4.4 NOTE2 added 1.30 May 25, 2007 2 Table 1.1 revised 3 Table 1.2 revised 5 Table 1.3 revised 6 Figure 1.2 revised 7 Table 1.4 revised 8 Figure 1.3 revised 9 Figure 1.4 NOTE4 added 15 Figure 3.1 part number revised A-2 REVISION HISTORY Rev. Date 1.30 May 25, 2007 R8C/26 Group, R8C/27 Group Datasheet Description Page Summary 16 Figure 3.2 part number revised 30 Table 5.10 revised 53 Table 5.39 NOTE4 added 55 Table 5.42 revised 1.40a Jun 14, 2007 5, 7 Table 1.3 and Table 1.4 revised 2.00 Mar 01, 2008 1, 49 1.1, 5.2 "J and K versions are ..." deleted 5, 7 Table 1.3, Table 1.4 revised 11 Table 1.6 NOTE3 added 15, 16 17 Table 4.1 "002Ch" added 18 Table 4.2 "0036h"; J, K version "0100X000b" "0100X001b" 24, 49 2.10 Sep 26, 2008 Figure 3.1, Figure 3.2; "Expanded area" deleted Table 5.2, Table 5.35; NOTE2 revised 30 Table 5.10 revised, NOTE4 added - "RENESAS TECHNICAL UP DATE" reflected: TN-16C-A172A/E 26, 51 Table 5.4, Table 5.37 NOTE2, NOTE4 revised 27, 52 Table 5.5, Table 5.38 NOTE2, NOTE5 revised 53 Table 5.39 Parameter: Voltage monitor 1 reset generation time added NOTE5 added Table 5.40 revised 54 Table 5.41 revised Figure 5.22 revised All trademarks and registered trademarks are the property of their respective owners. A-3 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. 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Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. 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