To our custo mers,
Old Company Name in Catalogs and Other Documents
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Renesas Electronics document. W e appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
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Rev.2.10 Sep 26, 2008 Page 1 of 69
REJ03B0168-0210
R8C/26 Group, R8C/27 Group
SINGLE-CHIP 16-BIT CMOS MCU
1. Overview
These MCUs are fabricated using a high-performance silicon gate CMOS process, embedding the R8C CPU core, and
are packaged in a 32-pin molded-plastic LQFP. It implements sophisticated instructions for a high level of instruction
efficiency. With 1 Mbyte of address space, they are capable of executing instructions at high speed.
Furthermore, the R8C/27 Group has on-chip data flash (1 KB × 2 blocks).
The difference between the R8C/26 Group and R8C/27 Group is only the presence or absence of data flash.
Their peripheral functions are the same.
1.1 Applications
Electronic household appliances, office equipment, audio equipment, consumer products, automotive, etc.
REJ03B0168-0210
Rev.2.10
Sep 26, 2008
R8C/26 Group, R8C/27 Group 1. Overview
Rev.2.10 Sep 26, 2008 Page 2 of 69
REJ03B0168-0210
1.2 Performance Overview
Table 1.1 outlines the Functions and Specifications for R8C/26 Group and Table 1.2 outlines the Functions and
Specifications for R8C/27 Group.
NOTES:
1. I2C bus is a trademark of Koninklijke Philips Electronics N. V.
2. Specify the D, K version if D, K version functions are to be used.
Table 1.1 Functions and S pecifications for R8C/26 Group
Item Specification
CPU Number of
fundamental
instructions
89 instructions
Minimum instruction
execution time 50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V) (other than K version)
62.5 ns (f(XIN) = 16 MHz, VCC = 3.0 to 5.5 V) (K version)
100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)
200 ns (f(XIN) = 5 MHz, VCC = 2.2 to 5.5 V) (N, D version)
Operating mode Single-chip
Address spac e 1 Mbyte
Memory capacity Refer to Table 1.3 Prod uct Information for R8C/26 Group
Peripheral
Functions Ports I/O ports: 25 pins, Input port: 3 pins
LED drive ports I/O ports: 8 pins (N, D version)
Timers Timer RA: 8 bits × 1 channel
Timer RB: 8 bits × 1 channel
(Each timer equipped with 8-bit prescaler)
Timer RC: 16 bits × 1 channel
(Input capture and output compare circuits)
Timer RE:
With real-time clock and comp are match function
(For J, K version, compare match function only.)
Serial interfaces 2 channels (UART0, UART1)
Clock synchronous serial I/O, UART
Clock synchronous
serial interface 1 channel
I
2
C bus Interface
(1)
Clock synchronous serial I/O with chip select
LIN module Hardware LIN: 1 channel (timer RA, UART0)
A/D converter 10-bit A/D converter: 1 circuit, 12 channels
Watchdog timer 15 bits × 1 channel (with prescaler)
St art -on-reset select ab l e
Interrupts Internal: 15 sources, External: 4 sources,
Software: 4 sources, Priority levels: 7 levels
Clock generation
circuits 3 circuits
• XIN clock generation circuit (with on-chip feedback resistor)
• On-chip oscillator (hig h speed, low speed)
High-speed on-chip oscillato r has a frequency adjustment function
• XCIN clock generation circuit (32 kHz) (N, D version)
• Real-time clock (timer RE) (N, D version)
Oscillation-stopped
detector XIN clock oscillation stop detection function
Voltage detection
circuit On-chip
Power-on reset circuit On-chip
Electrical
Characteristics Supply voltage VCC = 3.0 to 5.5 V (f(XIN) = 20 MHz) (other than K version)
VCC = 3.0 to 5.5 V (f(XIN) = 16 MHz) (K version)
VCC = 2.7 to 5.5 V (f(XIN) = 10 MHz)
VCC = 2.2 to 5.5 V (f(XIN) = 5 MHz) (N, D version)
Current consumption
(N, D version) Typ. 10 mA (VCC = 5.0 V, f(XIN) = 20 MHz)
Typ. 6 mA (VCC = 3.0 V, f(XIN) = 10 MHz)
Typ. 2.0 µA (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz)
Typ. 0.7 µA (VCC = 3.0 V, stop mode)
Flash Memory Programming and
erasure voltage VCC = 2.7 to 5.5 V
Programming and
erasure endurance 100 times
Operating Ambient Temperature -20 to 85°C (N version)
-40 to 85°C (D, J version)(2), -40 to 125°C (K version)(2)
Package 32-pin molded-plastic LQFP
R8C/26 Group, R8C/27 Group 1. Overview
Rev.2.10 Sep 26, 2008 Page 3 of 69
REJ03B0168-0210
NOTES:
1. I2C bus is a trademark of Koninklijke Philips Electronics N. V.
2. Specify the D, K version if D, K version functions are to be used.
Table 1.2 Functions and S pecifications for R8C/27 Group
Item Specification
CPU Number of fundamental
instructions 89 instructions
Minimum instruction
execution time 50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V) (other than K version)
62.5 ns (f(XIN) = 16 MHz, VCC = 3.0 to 5.5 V) (K version)
100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)
200 ns (f(XIN) = 5 MHz, VCC = 2.2 to 5.5 V) (N, D version)
Operating mode Single-chip
Address space 1 Mbyte
Memory capacity Refer to Table 1.4 Product Information of R8C/ 27 Gr oup
Peripheral
Functions Ports I/O ports: 25 pins, Input port: 3 pins
LED drive por ts I/O port s: 8 pi n s (N, D versi o n)
Timers Timer RA: 8 bits × 1 channel
Timer RB: 8 bits × 1 channel
(Each timer equipped with 8-bit prescaler)
Timer RC: 16 bit s × 1 ch an n el
(Input capture and output compare circuits)
Timer RE:
With real-time clock and compare match function
(For J, K version, compare match function only.)
Serial interfaces 2 chan nels (UART0, UART1)
Clock synchronous serial I/O, UART
Clock synchronous
serial interface 1 channel
I
2
C bus Interface
(1)
Clock synchronous serial I/O with chip select
LIN module Hardware LIN: 1 channel (timer RA, UART0)
A/D converter 10-bit A/D converter: 1 circuit, 12 channels
Watchdog timer 15 bits × 1 channel (with prescaler)
Start-on-reset selectable
Interrupts Internal: 15 sources, External: 4 sources,
Software: 4 sources, Priority levels: 7 levels
Clock generation
circuits 3 circuits
• XIN clock generation circuit (with on-chip feedback resistor)
• On-chip oscillator (high speed, low speed)
High-speed on-chip oscillator has a fre quency adjustment function
• XCIN clock generation circuit (32 kHz) (N, D version)
• Real-time clock (timer RE) (N, D version)
Oscillation-stopped
detector XIN clock oscillation stop detection function
Voltage detection circuit On-chip
Power-on reset circuit On-chip
Electrical
Characteristics Supply voltage VCC = 3.0 to 5.5 V (f(XIN) = 20 MHz) (other than K version)
VCC = 3.0 to 5.5 V (f(XIN) = 16 MHz) (K version)
VCC = 2.7 to 5.5 V (f(XIN) = 10 MHz)
VCC = 2.2 to 5.5 V (f(XIN) = 5 MHz) (N, D version)
Current consumption
(N, D version) Ty p. 10 mA (VCC = 5.0 V, f(XIN) = 20 MHz)
Ty p. 6 mA (VCC = 3.0 V, f(XIN) = 10 MHz)
Typ. 2.0 µA (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz)
Typ. 0.7 µA (VCC = 3.0 V, stop mode)
Flash Memory Programming and
erasure voltage VCC = 2.7 to 5.5 V
Programming and
erasure endurance 10,000 times (data flash)
1,000 times (program ROM)
Operating Ambient Temperature -20 to 85°C (N version)
-40 to 85°C (D, J version)(2), -40 to 125°C (K version)(2)
Package 32-pin molded-plastic LQFP
R8C/26 Group, R8C/27 Group 1. Overview
Rev.2.10 Sep 26, 2008 Page 4 of 69
REJ03B0168-0210
1.3 Block Diagram
Figure 1.1 shows a Block Diagram.
Figure 1.1 Block Diagra m
R8C CPU core
A/D converter
(10 bits × 12 channels)
UART or
clock synchronous serial I/O
(8 bits × 2 channels)
Memory
Watchdog timer
(15 bits)
ROM(1)
RAM(2)
Multiplier
R0H R0L
R1H R2
R3
R1L
A0
A1
FB
SB
USP
ISP
INTB
PC
FLG
I/O ports
NOTES:
1. ROM size varies with MCU type.
2. RAM size varies with MCU type.
3. XCIN, XCOUT can be used only for N or D version.
I2C bus interface or clock synchronous
serial I/O with chip select
(8 b its × 1 channel)
LIN module
(1 channel)
System clock
generation circuit
XIN-XOUT
High-speed on-chip oscillator
Low- Sp ee d o n-c h ip os cilla tor
XCIN-XCOUT(3)
Timers
Timer RA (8 bits)
Timer RB (8 bits)
Timer RC
(16 bits × 1 channel)
Timer RE (8 bits)
8
Port P0
8
Port P1
6
Port P3
1 3
Port P4
2
Port P5
Peripheral functions
R8C/26 Group, R8C/27 Group 1. Overview
Rev.2.10 Sep 26, 2008 Page 5 of 69
REJ03B0168-0210
1.4 Product Information
Table 1.3 lists the Product Information for R8C/26 Group and Table 1.4 lists the Product Information for R8C/27
Group.
NOTE:
1. The user ROM is programmed before shipment.
Table 1.3 Product Information for R8C/26 Group Current of Sep. 2008
Part No. ROM
Capacity RAM
Capacity Package Type Remarks
R5F21262SNFP 8 Kbytes 512 bytes PLQP0 032GB-A N version
R5F21264SNFP 16 Kbytes 1 Kbyte PLQP0032GB-A
R5F21265SNFP 24 Kbytes 1.5 Kbytes PLQP0032GB-A
R5F21266SNFP 32 Kbytes 1.5 Kbytes PLQP0032GB-A
R5F21262SDFP 8 Kbytes 512 bytes PLQP0 032GB-A D version
R5F21264SDFP 16 Kbytes 1 Kbyte PLQP0032GB-A
R5F21265SDFP 24 Kbytes 1.5 Kbytes PLQP0032GB-A
R5F21266SDFP 32 Kbytes 1.5 Kbytes PLQP0032GB-A
R5F21264JFP 16 Kbytes 1 Kbyte PLQP0032GB-A J version
R5F21266JFP 32 Kbytes 1.5 Kbytes PLQP0032GB-A
R5F21264KFP 16 Kbytes 1 Kbyte PLQP0032GB-A K version
R5F21266KFP 32 Kbytes 1.5 Kbytes PLQP0032GB-A
R5F21262SNXXXFP 8 Kbytes 512 bytes PLQP0032GB-A N version Factory
programming
product(1)
R5F21264SNXXXFP 16 Kbytes 1 Kbyte PLQP0032GB-A
R5F21265SNXXXFP 24 Kbytes 1.5 Kbytes PLQP0032GB-A
R5F21266SNXXXFP 32 Kbytes 1.5 Kbytes PLQP0032GB-A
R5F21262SDXXXFP 8 Kbytes 512 bytes PLQP0032GB-A D version
R5F21264SDXXXFP 16 Kbytes 1 Kbyte PLQP0032GB-A
R5F21265SDXXXFP 24 Kbytes 1.5 Kbytes PLQP0032GB-A
R5F21266SDXXXFP 32 Kbytes 1.5 Kbytes PLQP0032GB-A
R5F21264JXXXFP 16 Kbytes 1 Kbyte PLQP0032GB-A J version
R5F21266JXXXFP 32 Kbytes 1.5 Kbytes PLQP0032GB-A
R5F21264KXXXFP 16 Kbytes 1 Kbyte PLQP0032GB-A K version
R5F21266KXXXFP 32 Kbytes 1.5 Kbytes PLQP0032GB-A
R8C/26 Group, R8C/27 Group 1. Overview
Rev.2.10 Sep 26, 2008 Page 6 of 69
REJ03B0168-0210
Figure 1.2 Part Number, Memory Size, and Package of R8C/26 Group
Part No. R 5 F 21 26 6 S N XXX FP
Package type:
FP: PLQP0032GB-A
ROM number
Classification
N: Operating ambient temperature -20 to 85°C (N v ersion)
D: Operating ambient temperature -40 to 85°C (D v ersion)
J: Operating ambient temperature -40 to 85°C (J version)
K: Operating ambient temperature -40 to 125°C (K vers ion)
S: Low-voltage version (other no symbols)
ROM capacity
2: 8 KB
4: 16 KB
5: 24 KB
6: 32 KB
R8C/26 Group
R8C/2x Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
R8C/26 Group, R8C/27 Group 1. Overview
Rev.2.10 Sep 26, 2008 Page 7 of 69
REJ03B0168-0210
NOTE:
1. The user ROM is programmed before shipment.
Table 1.4 Product Information for R8C/27 Group Current of Sep. 2008
Part No. ROM Capacity RAM
Capacity Package Type Remarks
Program
ROM Data flash
R5F21272SNFP 8 Kbytes 1 Kbyte × 2 512 bytes PLQP0032GB-A N version
R5F21274SNFP 16 Kbytes 1 Kbyte × 2 1 Kbyte PLQP0032GB-A
R5F21275SNFP 24 Kbytes 1 Kbyte × 2 1.5 Kbytes PLQP0032GB-A
R5F21276SNFP 32 Kbytes 1 Kbyte × 2 1.5 Kbytes PLQP0032GB-A
R5F21272SDFP 8 Kbytes 1 Kbyte × 2 512 bytes PLQP0032GB-A D version
R5F21274SDFP 16 Kbytes 1 Kbyte × 2 1 Kbyte PLQP0032GB-A
R5F21275SDFP 24 Kbytes 1 Kbyte × 2 1.5 Kbytes PLQP0032GB-A
R5F21276SDFP 32 Kbytes 1 Kbyte × 2 1.5 Kbytes PLQP0032GB-A
R5F21274JFP 16 Kbytes 1 Kbyte × 2 1 Kbyte PLQP0032GB-A J version
R5F21276JFP 32 Kbytes 1 Kbyte × 2 1.5 Kbytes PLQP0032GB-A
R5F21274KFP 16 Kbytes 1 Kbyte × 2 1 Kbyte PLQP0032GB-A K version
R5F21276KFP 32 Kbytes 1 Kbyte × 2 1.5 Kbytes PLQP0032GB-A
R5F21272SNXXXFP 8 Kbytes 1 Kbyte × 2 512 bytes PLQP0032GB-A N version Factory
programming
product(1)
R5F21274SNXXXFP 16 Kbytes 1 Kbyte × 2 1 Kbyte PLQP0032GB-A
R5F21275SNXXXFP 24 Kbytes 1 Kbyte × 2 1.5 Kbytes PLQP0032GB-A
R5F21276SNXXXFP 32 Kbytes 1 Kbyte × 2 1.5 Kbytes PLQP0032GB-A
R5F21272SDXXXFP 8 Kbytes 1 Kbyte × 2 512 bytes PLQP0032GB-A D version
R5F21274SDXXXFP 16 Kbytes 1 Kbyte × 2 1 Kbyte PLQP0032GB-A
R5F21275SDXXXFP 24 Kbytes 1 Kbyte × 2 1.5 Kbytes PLQP0032GB-A
R5F21276SDXXXFP 32 Kbytes 1 Kbyte × 2 1.5 Kbytes PLQP0032GB-A
R5F21274JXXXFP 16 Kbytes 1 Kbyte × 2 1 Kbyte PLQP0032GB-A J version
R5F21276JXXXFP 32 Kbytes 1 Kbyte × 2 1.5 Kbytes PLQP0032GB-A
R5F21274KXXXFP 16 Kbytes 1 Kbyte × 2 1 Kbyte PLQP0032GB-A K version
R5F21276KXXXFP 32 Kbytes 1 Kbyte × 2 1.5 Kbytes PLQP0032GB-A
R8C/26 Group, R8C/27 Group 1. Overview
Rev.2.10 Sep 26, 2008 Page 8 of 69
REJ03B0168-0210
Figure 1.3 Part Number, Memory Size, and Package of R8C/27 Group
Part No. R 5 F 21 27 6 S N XXX FP
Package type:
FP: PLQP0032GB-A
ROM number
Classification
N: Operating ambient temperature -20 to 85°C (N version)
D: Operating ambient temperature -40 to 85°C (D version)
J: Operating ambient temperature -40 to 85°C (J version)
K: Operating ambient temperature -40 to 125°C (K version)
S: Low-voltage version (other no symbols)
ROM capacity
2: 8 KB
4: 16 KB
5: 24 KB
6: 32 KB
R8C/27 Group
R8C/2x Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
R8C/26 Group, R8C/27 Group 1. Overview
Rev.2.10 Sep 26, 2008 Page 9 of 69
REJ03B0168-0210
1.5 Pin Assignments
Figure 1.4 shows Pin Assignments (Top View).
Figure 1.4 Pin Assignments (Top View)
NOTES:
1. P4_7 is an i nput-only port.
2. Can be assigned to the pin in parentheses by a program.
3. XCIN, XCOUT can be used only f or N or D version.
4. Confirm the pin 1 posit ion on the package by refer r ing to the package dimensions.
R8C/26 Group
R8C/27 Group
XIN/XCIN/P4_6(3)
XOUT/XCOUT/P4_7(1, 3)
VSS/AVSS
RESET
VCC/AVCC
P3_7/TRAO/SSO/RXD1/(TXD1)(2)
MODE
P4_5/INT0/(RXD1)(2)
P1_7/TRAIO/INT1
P3_6/(TXD1)/(RXD1)/(INT1)(2)
P3_5/SCL/SSCK/(TRCIOD)(2)
P1_0/KI0/AN8
P1_4/TXD0
VREF/P4_2
P1_3/KI3/AN11/(TRBO)
P3_3/INT3/SSI/TRCCLK
P1_1/KI1/AN9/TRCIOA/TRCTRG
P1_2/KI2/AN10/TRCIOB
P0_3/AN4
P0_2/AN5
P0_1/AN6
P0_0/AN7/(TXD1)(2)
P0_7/AN0
P0_6/AN1
P0_5/AN2/CLK1
P1_5/RXD0/(TRAIO)/(INT1)(2)
P1_6/CLK0/(SSI)(2)
P5_3/TRCIOC
P5_4/TRCIOD
P3_1/TRBO
P3_4/SDA/SCS/(TRCIOC)(2)
P0_4/AN3/TREO 29
28
27
26
25
32
31
30
9
10
11
12
13
14
15
16
24 23 22 21 20 19 18 17
5781234 6
PLQP0032GB-A
(32P6U-A)
(top view)
R8C/26 Group, R8C/27 Group 1. Overview
Rev.2.10 Sep 26, 2008 Page 10 of 69
REJ03B0168-0210
1.6 Pin Functions
Table 1.5 lists Pin Functions.
I: Input O: Output I/O: Input and output
Table 1.5 Pin Functions
Ty pe Symbol I/O Type Description
Power supply input VCC , VSS I Apply 2.2 to 5.5 V (J, K version are 2.7 to 5.5 V) to the VCC
pin. Apply 0 V to the VSS pin.
Analog power
supply input AVCC, AVSS I Power supply for the A/D converter.
Connect a capacitor between AVCC and AVSS.
Reset input RESET I Input “L” on this pin resets the MCU.
MODE MODE I Connect this pin to VCC via a resistor .
XIN clock input XIN I These pins are provided for XIN clock generation circuit I/O.
Connect a ceramic resonator or a crystal oscillator between the
XIN and XOUT pins. To use an external clock, input it to the
XIN pin and leave the XOUT pin open.
XIN clock output XOUT O
XCIN clock input
(N, D version) XCIN I These pins are provided for XCIN clock generation circuit I/O.
Connect a crystal oscillator b etween the XCIN and XCOUT
pins. To use an external clock, input it to the XCIN pin and
leave the XCOUT pin open.
XCIN clock output
(N, D version) XCOUT O
INT interrupt input INT0, INT1, INT3 IINT interrupt input pins
Key input interrupt KI0 to KI3 I Key input interrupt input pins
Timer RA TRAO O Timer RA output pin
TRAIO I/O Timer RA I/O pin
Timer RB TRBO O Timer RB output pin
Timer RC TRCCLK I External clock input pin
TRCTRG I External trigger input pin
TRCIOA, TRCIOB,
TRCIOC, TRCIOD I/O Sharing output-compare output / input-capture input / PWM /
PWM2 output pins
Timer RE TREO O Timer RE output pin
Serial interface CLK0, CLK1 I/O Clock I/O pin
RXD0, RXD1 I Receive data input pin
TXD0, TXD1 O Transmit data output pin
I2C bus interface SCL I/O Clock I/O pin
SDA I/O Data I/O pin
Clock synchronous
serial I/O with chip
select
SSI I/O Data I/O pin
SCS I/O Chip-select signal I/O pin
SSCK I/O Clock I/O pin
SSO I/O Data I/O pin
Reference voltage
input VREF I Reference voltage input pin to A/D converter
A/D converter AN0 to AN11 I Analog input pins to A/D converter
I/O port P0_0 to P0_7,
P1_0 to P1_7,
P3_1, P3_3 to
P3_7,
P4_5,
P5_3, P5_4
I/O CMOS I/O ports. Each port has an I/O se lect dire cti on register,
allowing each pin in the port to be directed for input or output
individually.
Any port set to input can be set to use a pull-up resistor or not
by a program.
P1_0 to P1_7 also function as LED drive ports (N, D version).
Input port P4_2, P4_6, P4_7 I Input-only ports
R8C/26 Group, R8C/27 Group 1. Overview
Rev.2.10 Sep 26, 2008 Page 11 of 69
REJ03B0168-0210
NOTES:
1. This can be assigned to the pin in parentheses by a program.
2. XCIN, XCOUT can be used only for N or D version.
3. For the combination of using pins TXD1 and RXD1, refer to Figure 15.7 Registers PINSR1 and
PMR of Hardware Manual (REJ09B0278).
Table 1.6 Pin Name Information by Pin Number
Pin
Number Control Pin Port
I/O Pin Functions for of Peripheral Modules
Interrupt Timer Serial
Interface
Clock
Synchronous
Serial I/O with
Chip Select
I2C bus
Interface A/D
Converter
1P3_5 (TRCIOD)(1) SSCK SCL
2P3_7 TRAO RXD1/
(TXD1)(1, 3) SSO
3RESET
4XOUT/XCOUT(2) P4_7
5 VSS/AVSS
6XIN/XCIN(2) P4_6
7VCC/AVCC
8MODE
9P4_5 INT0 (RXD1)(1, 3)
10 P1_7 INT1 TRAIO
11 P3_6 (INT1)(1) (TXD1)/
(RXD1)(1, 3)
12 P3_1 TRBO
13 P5_4 TRCIOD
14 P5_3 TRCIOC
15 P1_6 CLK0 (SSI)(1)
16 P1_5 (INT1)(1) (TRAIO)(1) RXD0
17 P1_4 TXD0
18 P1_3 KI3 (TRBO) AN11
19 P1_2 KI2 TRCIOB AN10
20 VRFF P4_2
21 P1_1 KI1 TRCIOA/
TRCTRG AN9
22 P1_0 KI0 AN8
23 P3_3 INT3 TRCCLK SSI
24 P3_4 (TRCIOC)(1) SCS SDA
25 P0_7 AN0
26 P0_6 AN1
27 P0_5 CLK1 AN2
28 P0_4 TREO AN3
29 P0_3 AN4
30 P0_2 AN5
31 P0_1 AN6
32 P0_0 (TXD1)(1, 3) AN7
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2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a
register bank. There are two sets of register bank.
Figure 2.1 CPU Registers
R2
b31 b15 b8b7 b0
Data registers(1)
Address registers(1)
R3 R0H (high-order of R0)
R2
R3
A0
A1
INTBHb15b19 b0
INTBL
FB Frame base register(1)
The 4 high order bits of INTB are INTBH and
the 16 low order bits of INTB are INTBL.
Interrupt table register
b19 b0
USP
Program counter
ISP
SB
User stack pointer
Interrupt stack pointer
Static base register
PC
FLG Flag register
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved bit
Processor interrupt priority level
Reserved bit
C
IPL DZSBOIU
b15 b0
b15 b0
b15 b0
b8 b7
NOTE:
1. These registers comprise a register bank. There are two register banks.
R1H (high-order of R1)
R0L (low-order of R0)
R1L (low-order of R1)
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2.1 Data Registers (R0, R1, R2, and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split
into high-order bits (R 0H) and low-order bit s (R0L) to be used sep aratel y as 8-bit data regist ers. R1H and R 1L are
analogous to R0H and R0L. R2 can be combined with R0 and used a s a 32-bit data regi ster (R2R0). R3R1 is
analogous to R2R0.
2.2 Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also
used for transfer, arithmetic, and logic operations. A1 is analogou s to A0. A1 can be combined with A0 to be used
as a 32-bit address register (A1A0).
2.3 Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC is 20 bits wide and indicates the address of the next instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP, and ISP, are each 16 bits wide. The U flag of FLG is used to switch between
USP and ISP.
2.7 Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8 Flag Register (FLG)
FLG is an 11-bit register indicating the CPU state.
2.8.1 Carry Flag (C)
The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.
2.8.2 Debug Flag (D)
The D flag is for debugging only. Set it to 0.
2.8.3 Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.
2.8.4 Sign Flag (S)
The S flag is set to 1 when an arithmetic operation results in a negative valu e; otherwise to 0.
2.8.5 Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.
2.8.6 Overflow Flag (O)
The O flag is set to 1 when an operation results in an overflow; otherwise to 0.
R8C/26 Group, R8C/27 Group 2. Central Processing Unit (CPU)
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2.8.7 Interrupt Enable Flag (I)
The I flag enables maskable interrupts.
Interrupt are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0
when an interrupt request is acknowledged.
2.8.8 Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor inte rrupt priorit y levels from level 0 to level 7.
If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.8.10 Reserved Bit
If necessary, set to 0. When read, the content is undefined.
R8C/26 Group, R8C/27 Group 3. Memory
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3. Memory
3.1 R8C/26 Group
Figure 3.1 is a Memory Map of R8C/26 Group. The R8C/26 group has 1 Mbyte of address space from addresses
00000h to FFFFFh.
The internal ROM is allocated lower addresses, beginning with address 0 FFFFh. For exam ple, a 16 -Kbyte i nternal
ROM area is allocated addresses 0C000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each
interrupt routine.
The internal RAM is allocated higher addresses beginning with address 00400h. For example, a 1-Kbyte internal
RAM area is allocated addresses 00400h to 007FFh. The internal RAM is used not only for storing data but also for
calling subroutines and as stacks when interrupt requests are acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control
registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use
and cannot be accessed by users.
Figure 3.1 Memory Map of R8C/26 Group
Undefined inst ruction
Overflow
BRK instruct ion
Address mat ch
Single step
Watchdog timer/oscillation stop detection/voltage monitor
(Reserved)
(Reserved)
Reset
00400h
002FFh
00000h
Internal RAM
SFR
(Refer to 4. Special
Function Registers
(SFRs))
0FFFFh
0FFDCh
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
FFFFFh
0FFFFh
0YYYYh Internal ROM
(program ROM)
0XXXh
Part Number Internal ROM Internal RAM
Size Size
R5F21262SNFP, R5F21262SDFP,
R5F21262SNXXXFP, R5F21262SDXXXFP
R5F21264SNFP, R5F21264SDFP,
R5F21264JFP, R5F21264KFP,
R5F21264SNXXXFP, R5F21264SDXXXFP,
R5F21264JXXXFP, R5F21264KXXXFP
R5F21265SNFP, R5F2 1265SDFP
R5F21265SNXXXFP, R5F21265SDXXXFP
R5F21266SNFP, R5F21266SDFP,
R5F21266JFP, R5F21266KFP,
R5F21266SNXXXFP, R5F21266SDXXXFP,
R5F21266JXXXFP, R5F21266KXXXFP
8 Kbyte s
16 Kbytes
24 Kbytes
32 Kbytes
0E000h
0C000h
0A000h
08000h
512 bytes
1 Kbyt e
1.5 Kbytes
1.5 Kbytes
005FFh
007FFh
009FFh
009FFh
Address 0YYYYh Address 0XXXXh
R8C/26 Group, R8C/27 Group 3. Memory
Rev.2.10 Sep 26, 2008 Page 16 of 69
REJ03B0168-0210
3.2 R8C/27 Group
Figure 3.2 is a Memory Map of R8C/27 Group. The R8C/27 group has 1 Mbyte of address space from addresses
00000h to FFFFFh.
The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. For example, a
16-Kbyte internal ROM area is allocated addresses 0C00 0h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each
interrupt routine.
The internal ROM (data flash) is allocated addresses 02400h to 02BFFh.
The internal RAM area is allocated higher addresses, beginning with address 00400h. For example, a 1-Kbyte
internal RAM is allocated addresses 00400h to 007FFh. The internal RAM is used not only for storing data but also
for calling subroutines and as stacks when interrupt requests are acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control
registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use
and cannot be accessed by users.
Figure 3.2 Memory Map of R8C/27 Group
Undefined instruction
Overflow
BRK instruc t io n
Address matc h
Single step
Watchdog timer/oscillation stop detection/voltage monitor
(Reserved)
(Reserved)
Reset
FFFFFh
0FFFFh
0YYYYh
00400h
002FFh
00000h
Internal ROM
(program ROM)
Internal RAM
SFR
(Refer to 4. Special
Function Registers
(SFRs))
0FFFFh
0FFDCh
Internal ROM
(data flash)(1)
NOTES:
1. Data flash block A (1 Kbyte) and B (1 Kbyte) are shown.
2. The blank regions are reserved. Do not access locations in these re gions.
0XXXXh
02400h
02BFFh
Part Number Internal ROM Internal RAM
Size Address 0YYYYh Size Address 0XXXXh
R5F21272SN FP, R5F21272SDFP,
R5F21272SNXXXFP, R5F21272SDXXXFP
R5F21274SNFP, R5F21274SDFP,
R5F21274JFP, R5F21274KFP,
R5F21274SNXXXFP, R5F21274SDXXXFP,
R5F21274JXXXFP, R5F21274KXXXFP
R5F21275SN FP, R5F21275SDFP,
R5F21275SNXXXFP, R5F21275SDXXXFP
R5F21276SN FP, R5F21276SDFP,
R5F21276JFP, R5F21276KFP,
R5F21276SNXXXFP, R5F21276SDXXXFP,
R5F21276JXXXFP, R5F21276KXXXFP
8 Kbytes
16 Kbytes
24 Kbytes
32 Kbytes
0E000h
0C000h
0A000h
08000h
512 bytes
1 Kbyt e
1.5 Kbytes
1.5 Kbytes
005FFh
007FFh
009FFh
009FFh
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4. Special Function Registers (SFRs)
An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.7 list the speci al
function registers.
Table 4.1 SFR Information (1)(1)
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. The CSPROINI bit in the OFS register is set to 0.
3. In J, K version these regions are reserved. Do not access locations in these regions.
Address Register Symbol After reset
0000h
0001h
0002h
0003h
0004h Processor Mode Register 0 PM0 00h
0005h Processor Mode Register 1 PM1 00h
0006h System Clock Control Register 0 CM0 01101000b
0007h System Clock Control Register 1 CM1 00100000b
0008h
0009h
000Ah Protect Register PRCR 00h
000Bh
000Ch Oscillation Stop Det ection Register OCD 00000100b
000Dh Watchdog Timer Reset Register WDTR XXh
000Eh Watchdog Timer Start Register WDTS XXh
000Fh Watchdog Timer Control Register WDC 00X11111b
0010h Address Match Interrupt Register 0 RMAD0 00h
0011h 00h
0012h 00h
0013h Address Match Interrupt Enab le Register AIER 00h
0014h Address Match Interrupt Register 1 RMAD1 00h
0015h 00h
0016h 00h
0017h
0018h
0019h
001Ah
001Bh
001Ch Count Source Protection Mode Register CSPR 00h
10000000b(2)
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h High-Speed On-Chip Oscillator Control Register 0 FRA0 00h
0024h High-Speed On-Chip Oscillator Control Register 1 FRA1 When shipping
0025h High-Speed On-Chip Oscillator Control Register 2 FRA2 00h
0026h
0027h
0028h Clock Prescaler Reset Flag CPSRF 00h
0029h High-Speed On-Chip Oscillator Control Register 4(3) FRA4 When shipping
002Ah
002Bh High-Speed On-Chip Oscillator Control Register 6(3) FRA6 When shipping
002Ch High-Speed On-Chip Oscillator Control Register 7(3) FRA7 When shipping
002Dh
002Eh
002Fh
R8C/26 Group, R8C/27 Group 4. Special Function Registers (SFRs)
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Table 4.2 SFR Information (2)(1)
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. (N, D version) Software reset, watch dog timer reset, voltage monitor 1 reset, or vol tage monitor 2 reset do not affect this r egister.
(J, K version) Software reset , watchdog timer reset, or voltage monitor 2 reset do not affect this register.
3. The LVD0ON bit in the OFS register is set to 1 and hardware reset.
4. Power-on reset, voltage monitor 0 reset or the LVD0ON bit in the OFS register is set to 0, and hardware reset.
5. (N, D version) Software reset, watch dog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect b2 and b3.
(J, K version) Software reset , watchdog timer reset, or voltage monitor 2 reset do not affect b2 and b3.
6. (N, D version) Software reset, watch dog timer reset, voltage monitor 1 reset, or vol tage monitor 2 reset do not affect this r egister.
(J, K version) These regions are reserved. Do not access locations in these regions.
7. The LVD1ON bit in the OFS register is set to 1 and hardware reset.
8. Power-on reset, voltage moni tor 1 reset, or the LVD1ON bit in the OFS register is set to 0 and hardware reset.
9. Selected by the IICSEL bit in the PMR register.
Address Register Symbol After reset
0030h
0031h Voltage Detection Register 1 (2) VCA1 00001000b
0032h Voltage Detection Register 2 (2) VCA2 •N, D version 00h
(3)
00100000b(4)
•J, K version 00h
(7)
01000000b(8)
0033h
0034h
0035h
0036h Voltage Monitor 1 Circuit Control Register (5) VW1C • N, D version 00001000b
• J, K version 0000X000b(7)
0100X001b(8)
0037h Voltage Monitor 2 Circuit Control Register (5) VW2C 00h
0038h Voltage Monitor 0 Circuit Control Register (6) VW0C 0000X000b(3)
0100X001b(4)
0039h
003Fh
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h T i mer RC Interrupt Control Register TRCIC XXXXX000b
0048h
0049h
004Ah Timer RE Interrupt Control Register TREIC XXXXX000b
004Bh
004Ch
004Dh Key Input Interrupt Control Register KUPIC XXXXX000b
004Eh A/D Conversion Interrupt Control Register ADIC XXXXX000b
004Fh SSU/IIC bus Interrupt Control Register(9) SSUIC/IICIC XXXXX000b
0050h
0051h UART0 Transmit In terrupt Control Register S0TIC XXX XX000b
0052h UART0 Receive Interrupt Control Register S0RIC XXXXX000b
0053h UART1 Transmit Interrupt Control Register S1TIC XXXXX000b
0054h UART1 Receive Interrupt Control Register S1RIC XXXXX000b
0055h
0056h Timer RA Interrupt Control Register TRAIC XXXXX000b
0057h
0058h Timer RB Interrupt Control Register TRBIC XXXXX000b
0059h INT1 Interrupt Control Register INT1IC XX00X000b
005Ah INT3 Interrupt Control Register INT3IC XX00X000b
005Bh
005Ch
005Dh INT0 Interrupt Control Register INT0IC XX00X000b
005Eh
005Fh
0060h
006Fh
0070h
007Fh
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Rev.2.10 Sep 26, 2008 Page 19 of 69
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Table 4.3 SFR Information (3)(1)
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. Selected by the IICSEL bit in the PMR register.
Address Register Symbol After reset
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A0h UART0 Transmit/Receive Mode Register U0MR 00h
00A1h UART0 Bit Ra te Register U0BRG XXh
00A2h UART0 Transmit Buffer Register U0TB XXh
00A3h XXh
00A4h UART0 Transmit/Receive Control Register 0 U0C0 00001000b
00A5h UART0 Transmit/Receive Control Register 1 U0C1 00000010b
00A6h UART0 Receive Buffer Register U0RB XXh
00A7h XXh
00A8h UART1 Transmit/Receive Mode Register U1MR 00h
00A9h UART1 Bit Ra te Register U1BRG XXh
00AAh UART1 Transmit Buf fer Register U1TB XXh
00ABh XXh
00ACh UAR T1 Transmit/Receive Control Register 0 U1C0 00001000b
00ADh UAR T1 Transmit/Receive Control Register 1 U1C1 00000010b
00AEh UART1 Receive Buffer Register U1RB XXh
00AFh XXh
00B0h
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h SS Control Register H / IIC bus Control Register 1(2) SSCRH / ICCR1 00h
00B9h SS Control Register L / IIC bus Control Register 2(2) SSCRL / ICCR2 01111101b
00BAh SS Mode Register / IIC bus Mode Regist er(2) SSMR / ICMR 00011000b
00BBh SS Enable Register / IIC bus Interrupt Enable Register(2) SSER / ICIER 00h
00BCh SS Status Register / IIC bus Status Register(2) SSSR / ICSR 00h / 0000X000b
00BDh SS Mode Register 2 / Slave Address Register(2) SSMR2 / SAR 00h
00BEh SS Transmit Data Register / IIC bus Transmit Data Register(2) SSTDR / ICDRT FFh
00BFh SS Receive Data Register / IIC bus Receive Data Register(2) SSRDR / ICDRR FFh
R8C/26 Group, R8C/27 Group 4. Special Function Registers (SFRs)
Rev.2.10 Sep 26, 2008 Page 20 of 69
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Table 4.4 SFR Information (4)(1)
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. In J, K version these regions are reserved. Do not access locations in these regions.
Address Register Symbol After reset
00C0h A/D Register AD XXh
00C1h XXh
00C2h
00C3h
00C4h
00C5h
00C6h
00C7h
00C8h
00C9h
00CAh
00CBh
00CCh
00CDh
00CEh
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h A/D Control Register 2 ADCON2 00h
00D5h
00D6h A/D Control Register 0 ADCON0 00h
00D7h A/D Control Register 1 ADCON1 00h
00D8h
00D9h
00DAh
00DBh
00DCh
00DDh
00DEh
00DFh
00E0h Port P0 Register P0 00h
00E1h Port P1 Register P1 00h
00E2h Port P0 Direction Register PD0 00h
00E3h Port P1 Direction Register PD1 00h
00E4h
00E5h Port P3 Register P3 00h
00E6h
00E7h Port P3 Direction Register PD3 00h
00E8h Port P4 Register P4 00h
00E9h Port P5 Register P5 00h
00EAh Port P4 Direction Register PD4 00h
00EBh Port P5 Direction Register PD5 00h
00ECh
00EDh
00EEh
00EFh
00F0h
00F1h
00F2h
00F3h
00F4h
00F5h Pin Select Register 1 PINSR1 00h
00F6h Pin Select Register 2 PINSR2 00h
00F7h Pin Select Register 3 PINSR3 00h
00F8h Port Mode Register PMR 00h
00F9h External Input Enable Register INTEN 00h
00FAh INT Input Filter Select Register INTF 00h
00FBh Key Input Enable Register KIEN 00h
00FCh Pull-Up Control Register 0 PUR0 00h
00FDh Pull-Up Control Register 1 PUR1 00h
00FEh Port P1 Drive Capacity Control Register(2) P1DRR 00h
00FFh
R8C/26 Group, R8C/27 Group 4. Special Function Registers (SFRs)
Rev.2.10 Sep 26, 2008 Page 21 of 69
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Table 4.5 SFR Information (5)(1)
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. In J, K version these regions are reserved. Do not access locations in these regions.
Address Register Symbol After reset
0100h Timer RA Control Register TRACR 00h
0101h Timer RA I/O Control Register TRAIOC 00h
0102h Timer RA Mode Register TRAMR 00h
0103h Timer RA Prescaler Register TRAPRE FFh
0104h Timer RA Register TRA FFh
0105h
0106h LIN Control Register LINCR 00h
0107h LIN Status Register LINST 00h
0108h Timer RB Control Register TRBCR 00h
0109h Timer RB One-Shot Control Register TRBOCR 00h
010Ah Timer RB I/O Control Register TRBIOC 00h
010Bh Timer RB Mode Register TRBMR 00h
010Ch Timer RB Prescaler Register TRBPRE FFh
010Dh Timer RB Secondary Register TRBSC FFh
010Eh Timer RB Primary Register TRBPR FFh
010Fh
0110h
0111h
0112h
0113h
0114h
0115h
0116h
0117h
0118h Timer RE Second Data Register / Counter Data Register TRESEC 00h
0119h Timer RE Minute Data Register / Compare Data Register TREMIN 00h
011Ah Timer RE Hour Data Register(2) TREHR 00h
011Bh Timer RE Day of Week Data Register(2) TREWK 00h
011Ch Timer RE Control Register 1 TRECR1 00h
011Dh Timer RE Control Register 2 TRECR2 00h
011Eh Timer RE Count Source Select Register TRECSR 00001000b
011Fh
0120h T i mer RC Mode Register TRCMR 01001000b
0121h Timer RC Control Register 1 TRCCR1 00h
0122h T i mer RC Interrupt Enable Register TRCIER 01110000b
0123h Timer RC Status Register TRCSR 01110000b
0124h Timer RC I/O Control Register 0 TRCIOR0 10001000b
0125h Timer RC I/O Control Register 1 TRCIOR1 10001000b
0126h Timer RC Counter TRC 00h
0127h 00h
0128h Timer RC General Register A TRCGRA FFh
0129h FFh
012Ah Timer RC General Register B TRCGRB FFh
012Bh FFh
012Ch Timer RC General Register C TRCGRC FFh
012Dh FFh
012Eh Timer RC General Register D TRCGRD FFh
012Fh FFh
0130h Timer RC Control Register 2 TRCCR2 00011111b
0131h Timer RC Digital Filter Function Select Register TRCDF 00h
0132h Timer RC Output Master Enable Register TRCOER 01111111b
0133h
0134h
0135h
0136h
0137h
0138h
0139h
013Ah
013Bh
013Ch
013Dh
013Eh
013Fh
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Rev.2.10 Sep 26, 2008 Page 22 of 69
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Table 4.6 SFR Information (6)(1)
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Address Register Symbol After reset
0140h
0141h
0142h
0143h
0144h
0145h
0146h
0147h
0148h
0149h
014Ah
014Bh
014Ch
014Dh
014Eh
014Fh
0150h
0151h
0152h
0153h
0154h
0155h
0156h
0157h
0158h
0159h
015Ah
015Bh
015Ch
015Dh
015Eh
015Fh
0160h
0161h
0162h
0163h
0164h
0165h
0166h
0167h
0168h
0169h
016Ah
016Bh
016Ch
016Dh
016Eh
016Fh
0170h
0171h
0172h
0173h
0174h
0175h
0176h
0177h
0178h
0179h
017Ah
017Bh
017Ch
017Dh
017Eh
017Fh
R8C/26 Group, R8C/27 Group 4. Special Function Registers (SFRs)
Rev.2.10 Sep 26, 2008 Page 23 of 69
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Table 4.7 SFR Information (7)(1)
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. The OFS register cannot be changed by a program. Use a flash programmer to write to it.
Address Register Symbol After reset
0180h
0181h
0182h
0183h
0184h
0185h
0186h
0187h
0188h
0189h
018Ah
018Bh
018Ch
018Dh
018Eh
018Fh
0190h
0191h
0192h
0193h
0194h
0195h
0196h
0197h
0198h
0199h
019Ah
019Bh
019Ch
019Dh
019Eh
019Fh
01A0h
01A1h
01A2h
01A3h
01A4h
01A5h
01A6h
01A7h
01A8h
01A9h
01AAh
01ABh
01ACh
01ADh
01AEh
01AFh
01B0h
01B1h
01B2h
01B3h Flash Memory Control Register 4 FMR4 01000000b
01B4h
01B5h Flash Memory Control Register 1 FMR1 1000000Xb
01B6h
01B7h Flash Memory Control Register 0 FMR0 00000001b
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01BFh
FFFFh Option Function Select Register OFS (Note 2)
R8C/26 Group, R8C/27 Group 5. Electrical Characteristics
Rev.2.10 Sep 26, 2008 Page 24 of 69
REJ03B0168-0210
5. Electrical Characteristics
5.1 N, D Version
NOTES:
1. VCC = 2.2 to 5.5 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. The average output current indicates the average value of current measured during 100 ms.
Table 5.1 Absolute Maximum Ratings
Symbol Parameter Condition Rated Value Unit
VCC/AVCC Supply voltage -0.3 to 6.5 V
VIInput voltage -0.3 to VCC + 0.3 V
VOOutput voltage -0.3 to VCC + 0.3 V
PdPower dissipation Topr = 25°C500mW
Topr Operating ambient temperature -20 to 85 (N version) /
-40 to 85 (D version) °C
Tstg Storage temperature -65 to 150 °C
Table 5.2 Recommended Operating Conditions
Symbol Parameter Conditions Standard Unit
Min. Typ. Max.
VCC/AVCC Supply voltage 2.2 −5.5 V
VSS/AVSS Supply voltage −0−V
VIH Input “H” voltage 0.8 VCC −VCC V
VIL Input “L” voltage 0 −0.2 VCC V
IOH(sum) Peak sum output
“H” current Sum of all pins IOH(peak) −−-160 mA
IOH(sum) Average sum
output “H” current Sum of all pins IOH(avg) −−-80 mA
IOH(peak) Peak output “H”
current Except P1_0 to P1_7 −−-10 mA
P1_0 to P1_7 −−-40 mA
IOH(avg) Average output
“H” current Except P1_0 to P1_7 −−-5 mA
P1_0 to P1_7 −−-20 mA
IOL(sum) Peak sum output
“L” currents Sum of all pins IOL(peak) −−160 mA
IOL(sum) Average sum
output “L” currents Sum of all pins IOL(avg) −−80 mA
IOL(peak) Peak output “L”
currents Except P1_0 to P1_7 −−10 mA
P1_0 to P1_7 −−40 mA
IOL(avg) Average output
“L” current Except P1_0 to P1_7 −−5mA
P1_0 to P1_7 −−20 mA
f(XIN) XIN clock input oscillation frequency 3.0 V ≤ VCC ≤ 5.5 V 0 −20 MHz
2.7 V ≤ VCC < 3.0 V 0 −10 MHz
2.2 V ≤ VCC < 2.7 V 0 −5MHz
f(XCIN) XCIN clock input oscillation frequency 2.2 V ≤ VCC ≤ 5.5 V 0 −70 kHz
−System clock OCD2 = 0
XlN clock selected 3.0 V ≤ VCC ≤ 5.5 V 0 −20 MHz
2.7 V ≤ VCC < 3.0 V 0 −10 MHz
2.2 V ≤ VCC < 2.7 V 0 −5MHz
OCD2 = 1
On-chip oscillator clock
selected
FRA01 = 0
Low-speed on-chip
oscillator clock selected
−125 −kHz
FRA01 = 1
High-speed on-chip
oscillator clock selected
3.0 V ≤ VCC ≤ 5.5 V
−−20 MHz
FRA01 = 1
High-speed on-chip
oscillator clock selected
2.7 V ≤ VCC ≤ 5.5 V
−−10 MHz
FRA01 = 1
High-speed on-chip
oscillator clock selected
2.2 V ≤ VCC ≤ 5.5 V
−−5MHz
R8C/26 Group, R8C/27 Group 5. Electrical Characteristics
Rev.2.10 Sep 26, 2008 Page 25 of 69
REJ03B0168-0210
NOTES:
1. AVCC = 2.2 to 5.5 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in
8-bit mode.
Figure 5.1 Ports P0, P1, and P3 to P5 Timing Measurement Circuit
Table 5.3 A/D Converter Characteristics
Symbol Parameter Conditions Standard Unit
Min. Typ. Max.
−Resolution Vref = AVCC −−10 Bits
−Absolute
accuracy 10-bit mode φAD = 10 MHz, Vref = AVCC = 5.0 V −−±3 LSB
8-bit mode φAD = 10 MHz, Vref = AVCC = 5.0 V −−±2 LSB
10-bit mode φAD = 10 MHz, Vref = AVCC = 3.3 V −−±5 LSB
8-bit mode φAD = 10 MHz, Vref = AVCC = 3.3 V −−±2 LSB
10-bit mode φAD = 5 MHz, Vref = AVCC = 2.2 V −−±5 LSB
8-bit mode φAD = 5 MHz, Vref = AVCC = 2.2 V −−±2 LSB
Rladder Resistor ladder Vref = AVCC 10 −40 kΩ
tconv Conversion time 10-bit mode φAD = 10 MHz, Vref = AVCC = 5.0 V 3.3 −−µs
8-bit mode φAD = 10 MHz, Vref = AVCC = 5.0 V 2.8 −−µs
Vref Reference voltage 2.2 −AVCC V
VIA Analog input voltage(2) 0−AVCC V
−A/D operating
clock frequency Without sample and hold Vref = AVCC = 2.7 to 5.5 V 0.25 −10 MHz
With sample and hold Vref = AVCC = 2.7 to 5.5 V 1 −10 MHz
Without sample and hold Vref = AVCC = 2.2 to 5.5 V 0.25 −5MHz
With sample and hold Vref = AVCC = 2.2 to 5.5 V 1 −5MHz
P0
P1
P3
P4
P5
30pF
R8C/26 Group, R8C/27 Group 5. Electrical Characteristics
Rev.2.10 Sep 26, 2008 Page 26 of 69
REJ03B0168-0210
NOTES:
1. VCC = 2.7 to 5.5 V at Topr = 0 to 60°C, unless otherwise specified.
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 100 or 1,000), each block can be erased n times. For example, if 1,024
1-byte writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the
programming/erasure endurance still stands at one.
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. It is also advisable to retain data on the erasure endurance of each block and limit
the number of erase operations to a certain number.
5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
7. The data hold time includes time that the power supply is off or the clock is not supplied.
Table 5.4 Flash Memory (Program ROM) Electrical Characteristics
Symbol Parameter Conditions Standard Unit
Min. Typ. Max.
−Program/erase endurance(2) R8C/26 Group 100(3) −−times
R8C/27 Group 1,000(3) −−times
−Byte program time −50 400 µs
−Block erase time −0.4 9 s
td(SR-SUS) Time delay from suspend request until
suspend −−97 + CPU clock
× 6 cycles µs
−Interval from erase start/restart until
following suspend request 650 −−µs
−Interval from program start/restart until
following suspend request 0−−ns
−Time from suspend until prog ram/erase
restart −−3 + CPU clock
× 4 cycles µs
−Program, erase voltage 2.7 −5.5 V
−Read voltage 2.2 −5.5 V
−Program, erase temperature 0 −60 °C
−Data hold time(7) Ambient temperature = 55°C20 −−year
R8C/26 Group, R8C/27 Group 5. Electrical Characteristics
Rev.2.10 Sep 26, 2008 Page 27 of 69
REJ03B0168-0210
NOTES:
1. VCC = 2.7 to 5.5 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 10,000), each block can be erased n times. For example, if 1,024 1-byte
writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the
programming/erasure endurance still stands at one.
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
4. Standard of block A and block B when program and erase endurance exceeds 1,000 times. Byte program time to 1,000 times
is the same as that in program ROM.
5. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. In addition, averaging the erasure endurance between blocks A and B can further
reduce the actual erasure endurance. It is also advisable to retain data on the erasure endurance of each block and limit the
number of erase operations to a certain number.
6. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
7. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
8. -40°C for D version.
9. The data hold time includes time that the power supply is off or the clock is not supplied.
Table 5.5 Flash Memory (Data flash Block A, Block B) Electrical Characteristics(4)
Symbol Parameter Conditions Standard Unit
Min. Typ. Max.
−Program/erase endurance(2) 10,000(3) −−times
−Byte program time
(program/erase endurance ≤ 1,000 times) −50 400 µs
−Byte program time
(program/erase endurance > 1,000 times) −65 −µs
−Block erase time
(program/erase endurance ≤ 1,000 times) −0.2 9 s
−Block erase time
(program/erase endurance > 1,000 times) −0.3 −s
td(SR-SUS) Time delay from suspend request until
suspend −−97 + CPU clock
× 6 cycles µs
−Interval from erase start/restart until
following suspend request 650 −−µs
−Interval from program start/restart until
following suspend request 0−−ns
−Time from suspend until program/erase
restart −−3 + CPU clock
× 4 cycles µs
−Program, erase voltage 2.7 −5.5 V
−Read voltage 2.2 −5.5 V
−Program, erase temperature -20(8) −85 °C
−Data hold time(9) Ambient temperature = 55°C20 −−year
R8C/26 Group, R8C/27 Group 5. Electrical Characteristics
Rev.2.10 Sep 26, 2008 Page 28 of 69
REJ03B0168-0210
Figure 5.2 Time delay until Suspend
NOTES:
1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = -20 to 85°C (N version) / -40 to 85°C (D version).
2. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2
register to 0.
NOTES:
1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = -20 to 85°C (N version) / -40 to 85°C (D version).
2. Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1.
3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2
register to 0.
4. This parameter shows the voltage detection level when the power supply drops.
The voltage detection level when the power supply rises is higher than the voltage detection level when the power supply
drops by approximately 0.1 V.
NOTES:
1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = -20 to 85°C (N version) / -40 to 85°C (D version).
2. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2.
3. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2
register to 0.
Table 5.6 Voltage Detection 0 Circuit Elec t rica l Ch ara ct eristi cs
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
Vdet0 Voltage detection level 2.2 2.3 2.4 V
−Voltage detection circuit self power consumption VCA25 = 1, VCC = 5.0 V −0.9 −µA
td(E-A) Waiting time until voltage detection circuit operation
starts(2) −−300 µs
Vccmin MCU operating voltage minimum value 2.2 −−V
Table 5.7 Voltage Detection 1 Circuit Elec t rica l Ch ara ct eristi cs
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
Vdet1 Voltage detection level(4) 2.70 2.85 3.00 V
−Voltage monitor 1 interrupt request generation time(2) −40 −µs
−Voltage detection circuit self power consumption VCA26 = 1, VCC = 5.0 V −0.6 −µA
td(E-A) Waiting time until voltage detection circuit operation
starts(3) −−100 µs
Table 5.8 Voltage Detection 2 Circuit Elec t rica l Ch ara ct eristi cs
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
Vdet2 Voltage detection level 3.3 3.6 3.9 V
−Voltage monitor 2 interrupt request generation time(2) −40 −µs
−Voltage detection circuit self power consumption VCA27 = 1, VCC = 5.0 V −0.6 −µA
td(E-A) Waiting time until voltage detection circuit operation
starts(3) −−100 µs
FMR46
Suspend request
(maskable in terrupt request)
Fixed time
td(SR-SUS)
Clock-dependent
time Access restart
R8C/26 Group, R8C/27 Group 5. Electrical Characteristics
Rev.2.10 Sep 26, 2008 Page 29 of 69
REJ03B0168-0210
NOTES:
1. T he measurement condition is Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. This condition (external power VCC rise gradient) does not apply if VCC ≥ 1.0 V.
3. To use the power-on reset functio n, enable voltage monitor 0 reset by setting the LVD0ON bit in the OFS register to 0, the
VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the VCA2 register to 1.
4. tw(por1) indicates the duration the externa l power VCC must be held below the effective voltage (Vpor1) to enable a power on
reset. When turning on the power for the first time, maintain tw(por1) for 30 s or more if -20°C ≤ Topr ≤ 85°C, maintain tw(por1) for
3,000 s or more if -40°C ≤ Topr < -20°C.
Figure 5.3 Reset Circuit Electrical Characteristics
Table 5.9 Power-on Reset Circuit, Voltage Monitor 0 Reset Electrical Characteristics(3)
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
Vpor1 Power-on reset valid voltage(4) −−0.1 V
Vpor2 Power-on reset or voltage monitor 0 reset valid
voltage 0−Vdet0 V
trth External power VCC rise gradient(2) 20 −−mV/msec
NOTES:
1. Wh en using the voltage monitor 0 digital filter, ensure that t he voltage is wit hin the MCU operation voltage
range (2.2 V or above) during the samplin g time.
2. The sampling cl ock can be selected. Ref er to 6. Voltage Detection Circuit of Hardware Manual for details.
3. Vdet0 indi cates the voltage detection level of the voltage det ection 0 circuit. Refer to 6. Voltage Detection
Circuit of Hardwar e Manual for details.
Vdet0(3)
Vpor1
Internal
reset signal
(“L” valid)
tw(por1) Sampling time(1, 2)
Vdet0(3)
1
fOCO-S × 32 1
fOCO-S × 32
Vpor2
2.2 V
External
Power VCC trth trth
R8C/26 Group, R8C/27 Group 5. Electrical Characteristics
Rev.2.10 Sep 26, 2008 Page 30 of 69
REJ03B0168-0210
NOTES:
1. VCC = 2.2 to 5.5 V, Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. These standard values show when the FRA1 register value after reset is assumed.
3. These standard values show when the corrected value of the FRA6 register is written to the FRA1 register.
4. This enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0% when the serial interface is used in
UART mode.
NOTE:
1. VCC = 2.2 to 5.5 V, Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
NOTES:
1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = 25°C.
2. Waiting time until the internal power supply generation circuit stabilizes during power-on.
3. Time until system clock supply starts after the interrupt is acknowledged to exit stop mode.
Table 5.10 High-speed On-Chip Oscillator Circuit Electrical Characteristics
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
fOCO40M High-speed on-chip oscillator frequency
temperature • supply voltage dependence VCC = 4.75 to 5.25 V
0°C ≤ Topr ≤ 60°C(2) 39.2 40 40.8 MHz
VCC = 3.0 to 5.5 V
-20°C ≤ Topr ≤ 85°C(2) 38.8 40 41.2 MHz
VCC = 3.0 to 5.5 V
-40°C ≤ Topr ≤ 85°C(2) 38.4 40 41.6 MHz
VCC = 2.7 to 5.5 V
-20°C ≤ Topr ≤ 85°C(2) 38 40 42 MHz
VCC = 2.7 to 5.5 V
-40°C ≤ Topr ≤ 85°C(2) 37.6 40 42.4 MHz
VCC = 2.2 to 5.5 V
-20°C ≤ Topr ≤ 85°C(3) 35.2 40 44.8 MHz
VCC = 2.2 to 5.5 V
-40°C ≤ Topr ≤ 85°C(3) 34 40 46 MHz
VCC = 5.0 V ± 10%
-20°C ≤ Topr ≤ 85°C(2) 38.8 40 40.8 MHz
VCC = 5.0 V ± 10%
-40°C ≤ Topr ≤ 85°C(2) 38.4 40 40.8 MHz
High-speed on-chip oscillator frequency when
correction value in FRA7 register is written to
FRA1 register(4)
VCC = 5.0 V, Topr = 25°C−36.864 −MHz
VCC = 3.0 to 5.5 V
-20°C ≤ Topr ≤ 85°C-3% −3% %
−Value in FRA1 register after reset 08h(3) −F7h(3) −
−Oscillation frequency adjustment unit of high-
speed on-chip oscillator Adjust FRA1 register
(value after reset) to -1 −+0.3 −MHz
−Oscillation stability time −10 100 µs
−Self power consumption at oscillation VCC = 5.0 V, Topr = 25°C−400 −µA
Table 5.11 Low-speed On-Chip Oscillator Circuit Electrical Characteristics
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
fOCO-S Low-speed on-chip oscillator frequency 30 125 250 kHz
−Oscillation stability time −10 100 µs
−Self power consumption at oscillation VCC = 5.0 V, Topr = 25°C−15 −µA
Table 5.12 Power Supply Circuit Timing Characteristics
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
td(P-R) Time for internal power supply stabilization during
power-on(2) 1−2000 µs
td(R-S) STOP exit time(3) −−150 µs
R8C/26 Group, R8C/27 Group 5. Electrical Characteristics
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REJ03B0168-0210
NOTES:
1. VCC = 2.2 to 5.5 V, VSS = 0 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. 1tCYC = 1/f1(s)
Table 5.13 Timing Requirements of Clock Synchr onous Serial I/O with Chip Select(1)
Symbol Parameter Conditions Standard Unit
Min. Typ. Max.
tSUCYC SSCK clock cycle time 4 −−
tCYC(2)
tHI SSCK clock “H” width 0.4 −0.6 tSUCYC
tLO SSCK clock “L” width 0.4 −0.6 tSUCYC
tRISE SSCK clock rising
time Master −− 1tCYC(2)
Slave −− 1µs
tFALL SSCK clock falling
time Master −− 1tCYC(2)
Slave −− 1µs
tSU SSO, SSI data input setup time 100 −− ns
tHSSO, SSI data input hold time 1 −−
tCYC(2)
tLEAD SCS setup time Slave 1tCYC + 50 −− ns
tLAG SCS hold time Slave 1tCYC + 50 −− ns
tOD SSO, SSI data output delay time −− 1tCYC(2)
tSA SSI slave access time 2.7 V ≤ VCC ≤ 5.5 V −−1.5tCYC + 100 ns
2.2 V ≤ VCC < 2.7 V −−1.5tCYC + 200 ns
tOR SSI slave out open time 2.7 V ≤ VCC ≤ 5.5 V −−1.5tCYC + 100 ns
2.2 V ≤ VCC < 2.7 V −−1.5tCYC + 200 ns
R8C/26 Group, R8C/27 Group 5. Electrical Characteristics
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REJ03B0168-0210
Figure 5.4 I/O Timing of Clock Synchronous Serial I/O with Chip Select (Master)
VIH or VOH
VIH or VOH
tHI
tLO
tHI
tFALL tRISE
tLO tSUCYC
tOD
tH
tSU
SCS (output)
SSCK (output)
(CPOS = 1)
SSCK (output)
(CPOS = 0)
SSO (output)
SSI (input)
4-Wire Bus Communication Mode, Master, CPHS = 1
VIH or VOH
VIH or VOH
tHI
tLO
tHI
tFALL tRISE
tLO tSUCYC
tOD
tH
tSU
SCS (output)
SSCK (output)
(CPOS = 1)
SSCK (output)
(CPOS = 0)
SSO (output)
SSI (input)
4-Wire Bus Communication Mode, Master, CPHS = 0
CPHS, CPOS: Bits in SSMR register
R8C/26 Group, R8C/27 Group 5. Electrical Characteristics
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REJ03B0168-0210
Figure 5.5 I/O Timing of Clock Synchronous Serial I/O with Chip Select (Slave)
VIH or VOH
VIH or VOH
SCS (input)
SSCK (input)
(CPOS = 1)
SSCK (input)
(CPOS = 0)
SSO (input)
SSI (output)
4-Wire Bus Communication Mode, Slave, CPHS = 1
VIH or VOH
VIH or VOH
tHI
tLO
tHI
tFALL tRISE
tLO tSUCYC
tH
tSU
SCS (input)
SSCK (input)
(CPOS = 1)
SSCK (input)
(CPOS = 0)
SSO (input)
SSI (output)
4-Wire Bus Communication Mode, Slave, CPHS = 0
tOD
tLEAD
tSA
tLAG
tOR
tHI
tLO
tHI
tFALL tRISE
tLO tSUCYC
tH
tSU
tOD
tLEAD
tSA
tLAG
tOR
CPHS, CPOS: Bits in SSMR register
R8C/26 Group, R8C/27 Group 5. Electrical Characteristics
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NOTES:
1. VCC = 2.2 to 5.5 V, VSS = 0 V and Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. 1tCYC = 1/f1(s)
Figure 5.7 I/O Timing of I2C bus Interface
Table 5.14 Timing Requ ire me nts of I2C bus Interface(1)
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
tSCL SCL input cycle time 12tCYC + 600(2) −−ns
tSCLH SCL input “H” width 3tCYC + 300(2) −−ns
tSCLL SCL input “L” width 5tCYC + 500(2) −−ns
tsf SCL, SDA input fall time −−300 ns
tSP SCL, SDA input spike pulse rejection time −−
1tCYC(2) ns
tBUF SDA input bus-free time 5tCYC(2) −−ns
tSTAH Start condition input hold time 3tCYC(2) −−ns
tSTAS Retransmit start condition input setup time 3tCYC(2) −−ns
tSTOP Stop condition input setup time 3tCYC(2) −−ns
tSDAS Data input setup time 1tCYC + 20(2) −−ns
tSDAH Data input hold time 0 −−ns
SDA
tSTAH
tSCLL
tBUF
VIH
VIL
tSCLH
SCL
tsr
tsf
tSDAH
tSCL
tSTAS tSP tSTOP
tSDAS
P(2) S(1) Sr(3) P(2)
NOTES:
1. Start condition
2. Stop condition
3. Retransmit start condition
R8C/26 Group, R8C/27 Group 5. Electrical Characteristics
Rev.2.10 Sep 26, 2008 Page 36 of 69
REJ03B0168-0210
NOTE:
1. VCC = 4.2 to 5.5 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), f(XIN) = 20 MHz, unless otherwise specified.
Table 5.15 Electrical Characteristics (1) [V CC = 5 V]
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
VOH Output “H” volt age Except P1_0 to P1_7,
XOUT IOH = −5 mA VCC - 2.0 −VCC V
IOH = -200 µAVCC - 0.5 −VCC V
P1_0 to P1_7 Drive capacity HIGH IOH = -20 mA VCC - 2.0 −VCC V
Drive capacity LOW IOH = -5 mA VCC - 2.0 −VCC V
XOUT Drive capacity HIGH IOH = -1 mA VCC - 2.0 −VCC V
Drive capacity LOW IOH = -500 µAVCC - 2.0 −VCC V
VOL Output “L” voltage Except P1_0 to P1_7,
XOUT IOL = 5 mA −−2.0 V
IOL = 200 µA−−0.45 V
P1_0 to P1_7 Drive capacity HIGH IOL = 20 mA −−2.0 V
Drive capacity LOW IOL = 5 mA −−2.0 V
XOUT Drive capacity HIGH IOL = 1 mA −−2.0 V
Drive capacity LOW IOL = 500 µA−−2.0 V
VT+-VT- Hysteresis INT0, INT1, INT3,
KI0, KI1, KI2, KI3,
TRAIO, RXD0, RXD1,
CLK0, CLK1,
SSI, SCL, SDA, SSO
0.1 0.5 −V
RESET 0.1 1.0 −V
IIH Input “H” current VI = 5 V, VCC = 5 V −−5.0 µA
IIL Input “L” current VI = 0 V, VCC = 5 V −−-5.0 µA
RPULLUP Pull-up resistance VI = 0 V, VCC = 5 V 30 50 167 kΩ
RfXIN Feedback
resistance XIN −1.0 −MΩ
RfXCIN Feedback
resistance XCIN −18 −MΩ
VRAM RAM hold voltage During stop mode 1.8 −−V
R8C/26 Group, R8C/27 Group 5. Electrical Characteristics
Rev.2.10 Sep 26, 2008 Page 37 of 69
REJ03B0168-0210
Table 5.16 Electrical Characteristics (2) [Vcc = 5 V]
(Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.)
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
ICC Power supply current
(VCC = 3.3 to 5.5 V)
Single-chip mode,
output pins are open,
other pins are VSS
High-speed
clock mode XIN = 20 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
−10 17 mA
XIN = 16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
−915mA
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
−6−mA
XIN = 20 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−5−mA
XIN = 16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−4−mA
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−2.5 −mA
High-speed
on-chip
oscillator
mode
XIN clock off
High-speed on-chip oscillator on fOCO = 20 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
−10 15 mA
XIN clock off
High-speed on-chip oscillator on fOCO = 20 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−4−mA
XIN clock off
High-speed on-chip oscillator on fOCO = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
−5.5 10 mA
XIN clock off
High-speed on-chip oscillator on fOCO = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−2.5 −mA
Low-speed
on-chip
oscillator
mode
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8, FMR47 = 1
−130 300 µA
Low-speed
clock mode XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
FMR47 = 1
−130 300 µA
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
Program operation on RAM
Flash memory off, FMSTP = 1
−30 −µA
R8C/26 Group, R8C/27 Group 5. Electrical Characteristics
Rev.2.10 Sep 26, 2008 Page 38 of 69
REJ03B0168-0210
Table 5.17 Electrical Characteristics (3) [Vcc = 5 V]
(Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.)
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
ICC Power supply current
(VCC = 3.3 to 5.5 V)
Single-chip mode,
output pins are open,
other pins are VSS
Wait mode XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−25 75 µA
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−23 60 µA
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (high drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−4.0 −µA
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (low drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−2.2 −µA
Stop mode XIN clock off, Topr = 25°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
−0.8 3.0 µA
XIN clock off, Topr = 85°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
−1.2 −µA
R8C/26 Group, R8C/27 Group 5. Electrical Characteristics
Rev.2.10 Sep 26, 2008 Page 39 of 69
REJ03B0168-0210
Timing Requirements
(Unless Otherwise Specified: VCC = 5 V, VSS = 0 V at Topr = 25°C) [VCC = 5 V]
Figure 5.8 XIN Input and XCIN Input Timing Diagram when VCC = 5 V
Figure 5.9 TRAIO Input Ti ming Diagram when VCC = 5 V
Table 5.18 XIN Input, XCIN Input
Symbol Parameter Standard Unit
Min. Max.
tc(XIN) XIN input cycle time 50 −ns
tWH(XIN) XIN input “H” width 25 −ns
tWL(XIN) XIN input “L” width 25 −ns
tc(XCIN) XCIN input cycle time 14 −µs
tWH(XCIN) XCIN input “H” width 7 −µs
tWL(XCIN) XCIN input “L” width 7 −µs
Table 5.19 TRAIO Input
Symbol Parameter Standard Unit
Min. Max.
tc(TRAIO) TRAIO input cycle time 100 −ns
tWH(TRAIO) TRAIO input “H” width 40 −ns
tWL(TRAIO) TRAIO input “L” width 40 −ns
XIN input
tWH(XIN)
tC(XIN)
tWL(XIN)
VCC = 5 V
TRAIO input
VCC = 5 V
tC(TRAIO)
tWL(TRAIO)
tWH(TRAIO)
R8C/26 Group, R8C/27 Group 5. Electrical Characteristics
Rev.2.10 Sep 26, 2008 Page 40 of 69
REJ03B0168-0210
i = 0 or 1
Figure 5.10 Serial Interface Ti ming Diagram when VCC = 5 V
NOTES:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
Figure 5.11 External Interrupt INTi Input Timing Diagram when VCC = 5 V
Table 5.20 Serial Interface
Symbol Parameter Standard Unit
Min. Max.
tc(CK) CLKi input cycle time 200 −ns
tW(CKH) CLKi input “H” width 100 −ns
tW(CKL) CLKi input “L” width 100 −ns
td(C-Q) TXDi output delay time −50 ns
th(C-Q) TXDi hold time 0 −ns
tsu(D-C) RXDi input setup time 50 −ns
th(C-D) RXDi input hold time 90 −ns
Table 5.21 External Interrupt INTi (i = 0, 1, 3) Input
Symbol Parameter Standard Unit
Min. Max.
tW(INH) INTi input “H” width 250(1) −ns
tW(INL) INTi input “L” width 250(2) −ns
tW(CKH)
tC(CK)
tW(CKL) th(C-Q)
th(C-D)
tsu(D-C)td(C-Q)
CLKi
TXDi
RXDi
i = 0 or 1
VCC = 5 V
INTi input
tW(INL)
tW(INH)
i = 0, 1, 3
VCC = 5 V
R8C/26 Group, R8C/27 Group 5. Electrical Characteristics
Rev.2.10 Sep 26, 2008 Page 41 of 69
REJ03B0168-0210
NOTE:
1. VCC = 2.7 to 3.3 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), f(XIN) = 10 MHz, unless otherwise specified.
Table 5.22 Electrical Characteristics (3) [V CC = 3 V]
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
VOH Output “H” voltage Except P1_0 to P1_7,
XOUT IOH = -1 mA VCC - 0.5 −VCC V
P1_0 to P1_7 Drive capacity
HIGH IOH = -5 mA VCC - 0.5 −VCC V
Drive capacity
LOW IOH = -1 mA VCC - 0.5 −VCC V
XOUT Drive capacity
HIGH IOH = -0.1 mA VCC - 0.5 −VCC V
Drive capacity
LOW IOH = -50 µAVCC - 0.5 −VCC V
VOL Output “L” voltage Except P1_0 to P1_7,
XOUT IOL = 1 mA −−0.5 V
P1_0 to P1_7 Drive capacity
HIGH IOL = 5 mA −−0.5 V
Drive capacity
LOW IOL = 1 mA −−0.5 V
XOUT Drive capacity
HIGH IOL = 0.1 mA −−0.5 V
Drive capacity
LOW IOL = 50 µA−−0.5 V
VT+-VT- Hysteresis INT0, INT1, INT3,
KI0, KI1, KI2, KI3,
TRAIO, RXD0, RXD1,
CLK0, CLK1,
SSI, SCL, SDA, SSO
0.1 0.3 −V
RESET 0.1 0.4 −V
IIH Input “H” current VI = 3 V, VCC = 3 V −−4.0 µA
IIL Input “L” current VI = 0 V, VCC = 3 V −−-4.0 µA
RPULLUP Pull-up resistance VI = 0 V, VCC = 3 V 66 160 500 kΩ
RfXIN Feedback resistance XIN −3.0 −MΩ
RfXCIN Feedback resistance XCIN −18 −MΩ
VRAM RAM hold voltage During stop mode 1.8 −−V
R8C/26 Group, R8C/27 Group 5. Electrical Characteristics
Rev.2.10 Sep 26, 2008 Page 42 of 69
REJ03B0168-0210
Table 5.23 Electrical Characteristics (4) [Vcc = 3 V]
(Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.)
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
ICC Power supply current
(VCC = 2.7 to 3.3 V)
Single-chip mode,
output pins are open,
other pins are VSS
High-speed
clock mode XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
−6−mA
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−2−mA
High-speed
on-chip
oscillator
mode
XIN clock off
High-speed on-chip oscillator on fOCO = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
−59mA
XIN clock off
High-speed on-chip oscillator on fOCO = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−2−mA
Low-speed
on-chip
oscillator
mode
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8, FMR47 = 1
−130 300 µA
Low-speed
clock mode XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
FMR47 = 1
−130 300 µA
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
Program operation on RAM
Flash memory off, FMSTP = 1
−30 −µA
Wait mode XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−25 70 µA
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−23 55 µA
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (high drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−3.8 −µA
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (low drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−2.0 −µA
Stop mode XIN clock off, Topr = 25°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
−0.7 3.0 µA
XIN clock off, Topr = 85°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
−1.1 −µA
R8C/26 Group, R8C/27 Group 5. Electrical Characteristics
Rev.2.10 Sep 26, 2008 Page 43 of 69
REJ03B0168-0210
Timing requirements
(Unless Otherwise Specified: VCC = 3 V, VSS = 0 V at Topr = 25°C) [VCC = 3 V]
Figure 5.12 XIN Input and XCIN Input Timing Diagram when VCC = 3 V
Figure 5.13 TRAIO Input Timing Diagram when VCC = 3 V
Table 5.24 XIN Input, XCIN Input
Symbol Parameter Standard Unit
Min. Max.
tc(XIN) XIN input cycle time 100 −ns
tWH(XIN) XIN input “H” width 40 −ns
tWL(XIN) XIN input “L” width 40 −ns
tc(XCIN) XCIN input cycle time 14 −µs
tWH(XCIN) XCIN input “H” width 7 −µs
tWL(XCIN) XCIN input “L” width 7 −µs
Table 5.25 TRAIO Input
Symbol Parameter Standard Unit
Min. Max.
tc(TRAIO) TRAIO input cycle time 300 −ns
tWH(TRAIO) TRAIO input “H” width 120 −ns
tWL(TRAIO) TRAIO input “L” width 120 −ns
XIN input
tWH(XIN)
tC(XIN)
tWL(XIN)
VCC = 3 V
TRAIO input
VCC = 3 V
tC(TRAIO)
tWL(TRAIO)
tWH(TRAIO)
R8C/26 Group, R8C/27 Group 5. Electrical Characteristics
Rev.2.10 Sep 26, 2008 Page 44 of 69
REJ03B0168-0210
i = 0 or 1
Figure 5.14 Serial Interface Ti ming Diagram when VCC = 3 V
NOTES:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
Figure 5.15 External Interrupt INTi Input Timing Diagram when VCC = 3 V
Table 5.26 Serial Interface
Symbol Parameter Standard Unit
Min. Max.
tc(CK) CLKi input cycle time 300 −ns
tW(CKH) CLKi input “H” width 150 −ns
tW(CKL) CLKi Input “L” width 150 −ns
td(C-Q) TXDi output delay time −80 ns
th(C-Q) TXDi hold time 0 −ns
tsu(D-C) RXDi input setup time 70 −ns
th(C-D) RXDi input hold time 90 −ns
Table 5.27 External Interrupt INTi (i = 0, 1, 3) Input
Symbol Parameter Standard Unit
Min. Max.
tW(INH) INTi input “H” width 380(1) −ns
tW(INL) INTi input “L” width 380(2) −ns
tW(CKH)
tC(CK)
tW(CKL) th(C-Q)
th(C-D)
tsu(D-C)td(C-Q)
CLKi
TXDi
RXDi
VCC = 3 V
i = 0 or 1
INTi input
tW(INL)
tW(INH)
VCC = 3 V
i = 0, 1, 3
R8C/26 Group, R8C/27 Group 5. Electrical Characteristics
Rev.2.10 Sep 26, 2008 Page 45 of 69
REJ03B0168-0210
NOTE:
1. VCC = 2.2 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), f(XIN) = 5 MHz, unless otherwise specified.
Table 5.28 Electrical Characteristics (5) [V CC = 2.2 V]
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
VOH Output “H” voltage Except P1_0 to P1_7,
XOUT IOH = -1 mA VCC - 0.5 −VCC V
P1_0 to P1_7 Drive capacity
HIGH IOH = -2 mA VCC - 0.5 −VCC V
Drive capacity
LOW IOH = -1 mA VCC - 0.5 −VCC V
XOUT Drive capacity
HIGH IOH = -0.1 mA VCC - 0.5 −VCC V
Drive capacity
LOW IOH = -50 µAVCC - 0.5 −VCC V
VOL Output “L” voltage Except P1_0 to P1_7,
XOUT IOL = 1 mA −−0.5 V
P1_0 to P1_7 Drive capacity
HIGH IOL = 2 mA −−0.5 V
Drive capacity
LOW IOL = 1 mA −−0.5 V
XOUT Drive capacity
HIGH IOL = 0.1 mA −−0.5 V
Drive capacity
LOW IOL = 50 µA−−0.5 V
VT+-VT- Hysteresis INT0, INT1, INT3,
KI0, KI1, KI2, KI3,
TRAIO, RXD0, RXD1,
CLK0, CLK1,
SSI, SCL, SDA, SSO
0.05 0.3 −V
RESET 0.05 0.15 −V
IIH Input “H” current VI = 2.2 V −−4.0 µA
IIL Input “L” current VI = 0 V −−-4.0 µA
RPULLUP Pull-up resistance VI = 0 V 100 200 600 kΩ
RfXIN Feedback resistance XIN −5−MΩ
RfXCIN Feedback resistance XCIN −35 −MΩ
VRAM RAM hold voltage During stop mode 1.8 −−V
R8C/26 Group, R8C/27 Group 5. Electrical Characteristics
Rev.2.10 Sep 26, 2008 Page 46 of 69
REJ03B0168-0210
Table 5.29 Electrical Characteristics (6) [Vcc = 2.2 V]
(Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.)
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
ICC Power supply current
(VCC = 2.2 to 2.7 V)
Single-chip mode,
output pins are open,
other pins are VSS
High-speed
clock mode XIN = 5 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
−3.5 −mA
XIN = 5 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−1.5 −mA
High-speed
on-chip
oscillator
mode
XIN clock off
High-speed on-chip oscillator on fOCO = 5 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
−3.5 −mA
XIN clock off
High-speed on-chip oscillator on fOCO = 5 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−1.5 −mA
Low-speed
on-chip
oscillator
mode
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8, FMR47 = 1
−100 230 µA
Low-speed
clock mode XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
FMR47 = 1
−100 230 µA
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
Program operation on RAM
Flash memory off, FMSTP = 1
−25 −µA
Wait mode XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−22 60 µA
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−20 55 µA
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (high drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−3.0 −µA
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (low drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−1.8 −µA
Stop mode XIN clock off, Topr = 25°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
−0.7 3.0 µA
XIN clock off, Topr = 85°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
−1.1 −µA
R8C/26 Group, R8C/27 Group 5. Electrical Characteristics
Rev.2.10 Sep 26, 2008 Page 47 of 69
REJ03B0168-0210
Timing requirements
(Unless Otherwise Specified: VCC = 2.2 V, VSS = 0 V at Topr = 25°C) [VCC = 2.2 V]
Figure 5.16 XIN Input and XCIN Input Timing Diagram when VCC = 2.2 V
Figure 5.17 TRAIO Input Timing Diagram when VCC = 2.2 V
Table 5.30 XIN Input, XCIN Input
Symbol Parameter Standard Unit
Min. Max.
tc(XIN) XIN input cycle time 200 −ns
tWH(XIN) XIN input “H” width 90 −ns
tWL(XIN) XIN input “L” width 90 −ns
tc(XCIN) XCIN input cycle time 14 −µs
tWH(XCIN) XCIN input “H” width 7 −µs
tWL(XCIN) XCIN input “L” width 7 −µs
Table 5.31 TRAIO Input
Symbol Parameter Standard Unit
Min. Max.
tc(TRAIO) TRAIO input cycle time 500 −ns
tWH(TRAIO) TRAIO input “H” width 200 −ns
tWL(TRAIO) TRAIO input “L” width 200 −ns
XIN input
tWH(XIN)
tC(XIN)
tWL(XIN)
VCC = 2.2 V
TRAIO input
tC(TRAIO)
tWL(TRAIO)
tWH(TRAIO)
VCC = 2.2 V
R8C/26 Group, R8C/27 Group 5. Electrical Characteristics
Rev.2.10 Sep 26, 2008 Page 48 of 69
REJ03B0168-0210
i = 0 or 1
Figure 5.18 Serial Interface Ti ming Diagram when VCC = 2.2 V
NOTES:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
Figure 5.19 External Interrupt INTi Input Timing Diagram when VCC = 2.2 V
Table 5.32 Serial Interface
Symbol Parameter Standard Unit
Min. Max.
tc(CK) CLKi input cycle time 800 −ns
tW(CKH) CLKi input “H” width 400 −ns
tW(CKL) CLKi input “L” width 400 −ns
td(C-Q) TXDi output delay time −200 ns
th(C-Q) TXDi hold time 0 −ns
tsu(D-C) RXDi input setup time 150 −ns
th(C-D) RXDi input hold time 90 −ns
Table 5.33 External Interrupt INTi (i = 0, 1, 3) Input
Symbol Parameter Standard Unit
Min. Max.
tW(INH) INTi input “H” width 1000(1) −ns
tW(INL) INTi input “L” width 1000(2) −ns
tW(CKH)
tC(CK)
tW(CKL) th(C-Q)
th(C-D)
tsu(D-C)td(C-Q)
CLKi
TXDi
RXDi
VCC = 2.2 V
i = 0 or 1
INTi input
tW(INL)
tW(INH)
VCC = 2.2 V
i = 0, 1, 3
R8C/26 Group, R8C/27 Group 5. Electrical Characteristics
Rev.2.10 Sep 26, 2008 Page 49 of 69
REJ03B0168-0210
5.2 J, K Version
NOTES:
1. VCC = 2.7 to 5.5 V at Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified.
2. The average output current indicates the average value of current measured during 100 ms.
Table 5.34 Absolute Maximum Ratings
Symbol Parameter Condition Rated Value Unit
VCC/AVCC Supply voltage -0.3 to 6.5 V
VIInput voltage -0.3 to VCC + 0.3 V
VOOutput voltage -0.3 to VCC + 0.3 V
PdPower dissipation -40 °C ≤ Topr ≤ 85 °C300mW
85 °C ≤ Topr ≤ 125 °C125mW
Topr Operating ambient temperature -40 to 85 (J version) /
-40 to 125 (K version) °C
Tstg Storage temperature -65 to 150 °C
Table 5.35 Recommended Operating Conditions
Symbol Parameter Conditions Standard Unit
Min. Typ. Max.
VCC/AVCC Supply voltage 2.7 −5.5 V
VSS/AVSS Supply voltage −0−V
VIH Input “H” voltage 0.8 VCC −VCC V
VIL Input “L” voltage 0 −0.2 VCC V
IOH(sum) Peak sum output
“H” cu rrent Sum of all pins
IOH(peak)
−−-60 mA
IOH(peak) Peak output “H”
current −−-10 mA
IOH(avg) Average output
“H” cu rrent −−-5 mA
IOL(sum) Peak sum output
“L” currents Sum of all pins
IOL(peak)
−−60 mA
IOL(peak) Peak output “L”
currents −−10 mA
IOL(avg) Average output
“L” current −−5mA
f(XIN) XIN clock input oscillation frequency 3.0 V ≤ VCC ≤ 5.5 V (other than K
version) 0−20 MHz
3.0 V ≤ VCC ≤ 5.5 V (K version) 0 −16 MHz
2.7 V ≤ VCC < 3.0 V 0 −10 MHz
−System clock OCD2 = 0
XlN clock selected 3.0 V ≤ VCC ≤ 5.5 V (other than K
version) 0−20 MHz
3.0 V ≤ VCC ≤ 5.5 V (K version) 0 −16 MHz
2.7 V ≤ VCC < 3.0 V 0 −10 MHz
OCD2 = 1
On-chip oscillator
clock selected
FRA01 = 0
Low-speed on-chip oscillator clock
selected
−125 −kHz
FRA01 = 1
High-speed on-chip oscillator clock
selected (other than K version)
−−20 MHz
FRA01 = 1
High-speed on-chip oscillator clock
selected
−−10 MHz
R8C/26 Group, R8C/27 Group 5. Electrical Characteristics
Rev.2.10 Sep 26, 2008 Page 50 of 69
REJ03B0168-0210
NOTES:
1. AVCC = 2.7 to 5.5 V at Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified.
2. When the analog input voltage is over the reference volt age, the A/D conversion result will be 3FFh in 10-bit mode and FFh in
8-bit mode.
Figure 5.20 Ports P0, P1, and P3 t o P5 Timing Measurement Circuit
Table 5.36 A/D Converter Characterist ics
Symbol Parameter Conditions Standard Unit
Min. Typ. Max.
−Resolution Vref = AVCC −−10 Bits
−Absolute
accuracy 10-bit mode φAD = 10 MHz, Vref = AVCC = 5.0 V −−±3 LSB
8-bit mode φAD = 10 MHz, Vref = AVCC = 5.0 V −−±2 LSB
10-bit mode φAD = 10 MHz, Vref = AVCC = 3.3 V −−±5 LSB
8-bit mode φAD = 10 MHz, Vref = AVCC = 3.3 V −−±2 LSB
Rladder Resistor ladder V ref = AVCC 10 −40 kΩ
tconv Conversion time 10-bit mode φAD = 10 MHz, Vref = AVCC = 5.0 V 3.3 −−µs
8-bit mode φAD = 10 MHz, Vref = AVCC = 5.0 V 2.8 −−µs
Vref Reference voltage 2.7 −AVCC V
VIA Analog input voltage(2) 0−AVCC V
−A/D operating
clock frequency Without sample and hold 0.25 −10 MHz
With sample and hold 1 −10 MHz
P0
P1
P3
P4
P5
30pF
R8C/26 Group, R8C/27 Group 5. Electrical Characteristics
Rev.2.10 Sep 26, 2008 Page 51 of 69
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NOTES:
1. VCC = 2.7 to 5.5 V at Topr = 0 to 60°C, unless otherwise specified.
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 100 or 1,000), each block can be erased n times. For example, if 1,024
1-byte writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the
programming/erasure endurance still stands at one.
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. It is also advisable to retain data on the erasure endurance of each block and limit
the number of erase operations to a certain number.
5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
7. The data hold time includes time that the power supply is off or the clock is not supplied.
Table 5.37 Flash Memory (Program ROM) Electrical Characteristics
Symbol Parameter Conditions Standard Unit
Min. Typ. Max.
−Program/erase endurance(2) R8C/26 Group 100(3) −−times
R8C/27 Group 1,000(3) −−times
−Byte program time −50 400 µs
−Block erase time −0.4 9 s
td(SR-SUS) Time delay from suspend request until
suspend −−97 + CPU clock
× 6 cycles µs
−Interval from erase start/restart until
following suspend request 650 −−µs
−Interval from program start/restart until
following suspend request 0−−ns
−Time from suspend until program/erase
restart −−3 + CPU clock
× 4 cycles µs
−Program, erase voltage 2.7 −5.5 V
−Read voltage 2.7 −5.5 V
−Program, erase temperature 0 −60 °C
−Data hold time(7) Ambient temperature = 55°C20 −−year
R8C/26 Group, R8C/27 Group 5. Electrical Characteristics
Rev.2.10 Sep 26, 2008 Page 52 of 69
REJ03B0168-0210
NOTES:
1. VCC = 2.7 to 5.5 V at Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified.
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 10,000), each block can be erased n times. For example, if 1,024 1-byte
writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the
programming/erasure endurance still stands at one.
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
4. Standard of block A and block B when program and erase endurance exceeds 1,000 times. Byte program time to 1,000 times
is the same as that in program ROM.
5. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. In addition, averaging the erasure endurance between blocks A and B can further
reduce the actual erasure endurance. It is also advisable to retain data on the erasure endurance of each block and limit the
number of erase operations to a certain number.
6. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
7. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
8. 125°C for K version.
9. The data hold time includes time that the power supply is off or the clock is not supplied.
Table 5.38 Flash Memory (Data flash Block A, Block B) Electrical Characteristics(4)
Symbol Parameter Conditions Standard Unit
Min. Typ. Max.
−Program/erase endurance(2) 10,000(3) −−times
−Byte program time
(program/erase endurance ≤ 1,000 times) −50 400 µs
−Byte program time
(program/erase endurance > 1,000 times) −65 −µs
−Block erase time
(program/erase endurance ≤ 1,000 times) −0.2 9 s
−Block erase time
(program/erase endurance > 1,000 times) −0.3 −s
td(SR-SUS) Time delay from suspend request until
suspend −−97 + CPU clock
× 6 cycles µs
−Interval from erase start/restart until
following suspend request 650 −−µs
−Interval from program start/restart until
following suspend request 0−−ns
−Time from suspend until program/erase
restart −−3 + CPU clock
× 4 cycles µs
−Program, erase voltage 2.7 −5.5 V
−Read voltage 2.7 −5.5 V
−Program, erase temperature -40 −85(8) °C
−Data hold time(9) Ambient temperature = 55°C20 −−year
R8C/26 Group, R8C/27 Group 5. Electrical Characteristics
Rev.2.10 Sep 26, 2008 Page 53 of 69
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Figure 5.21 Time delay until Susp e nd
NOTES:
1. The measurement condition is VCC = 2.7 to 5.5 V and Topr = -40 to 85°C (J version) / -40 to 125°C (K version).
2. Hold Vdet2 > Vdet1.
3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2
register to 0.
4. This parameter shows the voltage detection level when the power supply drops.
The voltage detection level when the power supply rises is higher than the voltage detection level when the power supply
drops by approximately 0.1 V.
5. Time until the voltage monitor 1 reset is generated after the voltage passes Vdet1 when VCC falls. When using the digital filter,
its sampling time is added to td(Vdet1-A). When using the voltage monitor 1 reset, maintain this time until VCC = 2.0 V after the
voltage passes Vdet1 when the power supply falls.
NOTES:
1. The measurement condition is VCC = 2.7 to 5.5 V and Topr = -40 to 85°C (J version) / -40 to 125°C (K version).
2. Hold Vdet2 > Vdet1.
3. Time until the voltage monitor 2 reset/interrupt request is generated after the voltage passes Vdet2.
4. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2
register to 0.
5. When using the digital filter, its sampling time is added to td(Vdet2-A). When using the voltage monitor 2 reset, maintain this time
until VCC = 2.0 V after the voltage passes Vdet2 when the power supply falls.
Table 5.39 Voltage Detec ti on 1 Circ ui t Elec t ri cal C hara ct eris ti cs
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
Vdet1 Volt age detection level(2, 4) 2.70 2.85 3.0 V
td(Vdet1-A) Voltage monitor 1 reset generation time(5) −40 200 µs
−Voltage detection circuit self power consumption VCA26 = 1, VCC = 5.0 V −0.6 −µA
td(E-A) Waiting time until voltage detection circuit operation
starts(3) −−100 µs
Vccmin MCU operating voltage minimum value 2.70 −−V
Table 5.40 Voltage Detec ti on 2 Circ ui t Elec t ri cal C hara ct eris ti cs
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
Vdet2 Volt age detection level(2) 3.3 3.6 3.9 V
td(Vdet2-A) Voltage monitor 2 reset/interrupt request generation
time(3, 5) −40 200 µs
−Voltage detection circuit self power consumption VCA27 = 1, VCC = 5.0 V −0.6 −µA
td(E-A) Waiting time until voltage detection circuit operation
starts(4) −−100 µs
FMR46
Suspend request
(maskable in terrupt request)
Fixed time
td(SR-SUS)
Clock-dependent
time Access restart
R8C/26 Group, R8C/27 Group 5. Electrical Characteristics
Rev.2.10 Sep 26, 2008 Page 54 of 69
REJ03B0168-0210
NOTES:
1. The measurement condition is Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified.
2. This condition (the minimum value of external power VCC rise gradient) does not apply if Vpor2 ≥ 1.0 V.
3. To use the power-on reset function, enable voltage monitor 1 reset by setting the LVD1ON bit in the OFS register to 0, the
VW1C0 and VW1C6 bits in the VW1C register to 1 respectively, and the VCA26 bit in the VCA2 register to 1.
4. tw(por1) indicates the duration the external power VCC must be held below the effective voltage (Vpor1) to enable a power on
reset. When turning on the power for the first time, maintain tw(por1) for 30 s or more if -20°C ≤ Topr ≤ 125°C, maintain tw(por1) for
3,000 s or more if -40°C ≤ Topr < -20°C.
Figure 5.22 Reset Circuit Electrical Characterist ics
Table 5.41 Power-on Reset Circuit, Voltage Monitor 1 Reset Electrical Characteristics(3)
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
Vpor1 Power-on reset valid voltage(4) −−0.1 V
Vpor2 Power-on reset or voltage monitor 1 reset valid
voltage 0−Vdet1 V
trth External power VCC rise gradient VCC ≤ 3.6 V 20(2) −−mV/msec
VCC > 3.6 V 20(2) −2,000 mV/msec
Vdet1(3)
Vpor1
Internal reset
signal
(“L” valid)
tw(por1)
Vdet1(3)
Vpor2
× 32
1
fOCO-S × 32
1
fOCO-S
2.0 V
trth trth
External
power VCC
NOTES:
1. When using the voltage monitor 1 digital filter, ensure VCC is 2.0 V or hi gher during the sampling time.
2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit of Ha rdware Manual for details.
3. Vdet1 indicates the voltage detection level of the voltage dete ction 1 circuit. Refer to 6. Voltage Det ection
Circuit of Hardware Manual for details.
Sampling time(1, 2)
td(Vdet1-A)
R8C/26 Group, R8C/27 Group 5. Electrical Characteristics
Rev.2.10 Sep 26, 2008 Page 55 of 69
REJ03B0168-0210
NOTES:
1. VCC = 2.7 to 5.5 V, Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified.
2. These standard values show when the FRA1 register value after reset is assumed.
NOTE:
1. VCC = 2.7 to 5.5 V, Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified.
NOTES:
1. The measurement condition is VCC = 2.7 to 5.5 V and Topr = 25°C.
2. Waiting time until the internal power supply generation circuit stabilizes during power-on.
3. Time until system clock supply starts af ter the interrupt is acknowledged to exit stop mode.
Table 5.42 High-speed On-Chip Oscillator Circuit Electrical Characteristics
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
fOCO40M High-speed on-chip oscillator frequency
temperature · supply voltage dependence VCC = 4.75 to 5.25 V
0°C ≤ Topr ≤ 60°C(2) 39.2 40 40.8 MHz
VCC = 3.0 to 5.5 V
-20°C ≤ Topr ≤ 85°C(2) 38.8 40 41.2 MHz
VCC = 3.0 to 5.5 V
-40°C ≤ Topr ≤ 85°C(2) 38.4 40 41.6 MHz
VCC = 3.0 to 5.5 V
-40°C ≤ Topr ≤ 125°C(2) 38 40 42 MHz
VCC = 2.7 to 5.5 V
-40°C ≤ Topr ≤ 125°C(2) 37.6 40 42.4 MHz
−Value in FRA1 register after reset 08h −F7h −
−Oscillation frequency adjustment unit of high-
speed on-chip oscillator Adjust FRA1 register
(value after reset) to -1 −+0.3 −MHz
−Oscillation stability time −10 100 µs
−Self power consumption at oscillation VCC = 5.0 V, Topr = 25°C−400 −µA
Table 5.43 Low-speed On-Chip Oscillator Circuit Electrical Characteristics
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
fOCO-S Low-speed on-chip oscillator frequency 40 125 250 kHz
−Oscillation stability time −10 100 µs
−Self power consumption at oscillation VCC = 5.0 V, Topr = 25°C−15 −µA
Table 5.44 Power Supply Circuit Timing Characteristics
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
td(P-R) Time for internal power supply stabilization during
power-on(2) 1−2000 µs
td(R-S) STOP exit time(3) −−150 µs
R8C/26 Group, R8C/27 Group 5. Electrical Characteristics
Rev.2.10 Sep 26, 2008 Page 56 of 69
REJ03B0168-0210
NOTES:
1. VCC = 2.7 to 5.5 V, VSS = 0 V at Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified.
2. 1tCYC = 1/f1(s)
Table 5.45 Timing Requirements of Clock Synchr onous Serial I/O with Chip Select(1)
Symbol Parameter Conditions Standard Unit
Min. Typ. Max.
tSUCYC SSCK clock cycle time 4 −−
tCYC(2)
tHI SSCK clock “H” width 0.4 −0.6 tSUCYC
tLO SSCK clock “L” width 0.4 −0.6 tSUCYC
tRISE SSCK clock rising
time Master −− 1tCYC(2)
Slave −− 1µs
tFALL SSCK clock falling
time Master −− 1tCYC(2)
Slave −− 1µs
tSU SSO, SSI data input setup time 100 −− ns
tHSSO, SSI data input hold time 1 −−
tCYC(2)
tLEAD SCS setup time Slave 1tCYC + 50 −− ns
tLAG SCS hold time Slave 1tCYC + 50 −− ns
tOD SSO, SSI data output delay time −− 1tCYC(2)
tSA SSI slave access time −−1.5tCYC + 100 ns
tOR SSI slave out open time −−1.5tCYC + 100 ns
R8C/26 Group, R8C/27 Group 5. Electrical Characteristics
Rev.2.10 Sep 26, 2008 Page 57 of 69
REJ03B0168-0210
Figure 5.23 I/O Timing of Clock Synchronous Serial I/O with Chip Select (Master)
VIH or VOH
VIH or VOH
tHI
tLO
tHI
tFALL tRISE
tLO tSUCYC
tOD
tH
tSU
SCS (output)
SSCK (output)
(CPOS = 1)
SSCK (output)
(CPOS = 0)
SSO (output)
SSI (input)
4-Wire Bus Communication Mode, Master, CPHS = 1
VIH or VOH
VIH or VOH
tHI
tLO
tHI
tFALL tRISE
tLO tSUCYC
tOD
tH
tSU
SCS (output)
SSCK (output)
(CPOS = 1)
SSCK (output)
(CPOS = 0)
SSO (output)
SSI (input)
4-Wire Bus Communication Mode, Master, CPHS = 0
CPHS, CPOS: Bits in SSMR register
R8C/26 Group, R8C/27 Group 5. Electrical Characteristics
Rev.2.10 Sep 26, 2008 Page 58 of 69
REJ03B0168-0210
Figure 5.24 I/O Timing of Clock Synchronous Serial I/O with Chip Select (Slave)
VIH or VOH
VIH or VOH
SCS (input)
SSCK (input)
(CPOS = 1)
SSCK (input)
(CPOS = 0)
SSO (input)
SSI (output)
4-Wire Bus Communication Mode, Slave, CPHS = 1
VIH or VOH
VIH or VOH
tHI
tLO
tHI
tFALL tRISE
tLO tSUCYC
tH
tSU
SCS (input)
SSCK (input)
(CPOS = 1)
SSCK (input)
(CPOS = 0)
SSO (input)
SSI (output)
4-Wire Bus Communication Mode, Slave, CPHS = 0
tOD
tLEAD
tSA
tLAG
tOR
tHI
tLO
tHI
tFALL tRISE
tLO tSUCYC
tH
tSU
tOD
tLEAD
tSA
tLAG
tOR
CPHS, CPOS: Bits in SSMR register
R8C/26 Group, R8C/27 Group 5. Electrical Characteristics
Rev.2.10 Sep 26, 2008 Page 60 of 69
REJ03B0168-0210
NOTES:
1. VCC = 2.7 to 5.5 V, VSS = 0 V at Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified.
2. 1tCYC = 1/f1(s)
Figure 5.26 I/O Timing of I2C bus Interface
Table 5.46 Timing Requ ire me nts of I2C bus Interface(1)
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
tSCL SCL input cycle time 12tCYC + 600(2) −−ns
tSCLH SCL input “H” width 3tCYC + 300(2) −−ns
tSCLL SCL input “L” width 5tCYC + 500(2) −−ns
tsf SCL, SDA input fall time −−300 ns
tSP SCL, SDA input spike pulse rejection time −−
1tCYC(2) ns
tBUF SDA input bus-free time 5tCYC(2) −−ns
tSTAH Start condition input hold time 3tCYC(2) −−ns
tSTAS Retransmit start condition input setup time 3tCYC(2) −−ns
tSTOP Stop condition input setup time 3tCYC(2) −−ns
tSDAS Data input setup time 1tCYC + 20(2) −−ns
tSDAH Data input hold time 0 −−ns
SDA
tSTAH
tSCLL
tBUF
VIH
VIL
tSCLH
SCL
tsr
tsf
tSDAH
tSCL
tSTAS tSP tSTOP
tSDAS
P(2) S(1) Sr(3) P(2)
NOTES:
1. Start condition
2. Stop condition
3. Retransmit start condition
R8C/26 Group, R8C/27 Group 5. Electrical Characteristics
Rev.2.10 Sep 26, 2008 Page 61 of 69
REJ03B0168-0210
NOTE:
1. VCC = 4.2 to 5.5 V at Topr = -40 to 85°C (J version) / -40 to 125°C (K version), f(XIN) = 20 MHz, unless otherwise specified.
Table 5.47 Electrical Characteristics (1) [V CC = 5 V]
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
VOH Output “H” voltage Except XOUT IOH = -5 mA VCC - 2.0 −VCC V
IOH = -200 µAVCC - 0.3 −VCC V
XOUT Drive capacity HIGH IOH = -1 mA VCC - 2.0 −VCC V
Drive capacity LOW IOH = -500 µAVCC - 2.0 −VCC V
VOL Output “L” voltage Except XOUT IOL = 5 mA −−2.0 V
IOL = 200 µA−−0.45 V
XOUT Drive capacity HIGH IOL = 1 mA −−2.0 V
Drive capacity LOW IOL = 500 µA−−2.0 V
VT+-VT- Hysteresis INT0, INT1, INT3,
KI0, KI1, KI2, KI3,
TRAIO, RXD0, RXD1,
CLK0, CLK1,
SSI, SCL, SDA, SSO
0.1 0.5 −V
RESET 0.1 1.0 −V
IIH Input “H” current VI = 5 V, VCC = 5V −−5.0 µA
IIL Input “L” current VI = 0 V, VCC = 5V −−-5.0 µA
RPULLUP Pull-up resistance VI = 0 V, VCC = 5V 30 50 167 kΩ
RfXIN Feedback
resistance XIN −1.0 −MΩ
VRAM RAM hold voltage During stop mode 2.0 −−V
R8C/26 Group, R8C/27 Group 5. Electrical Characteristics
Rev.2.10 Sep 26, 2008 Page 62 of 69
REJ03B0168-0210
Table 5.48 Electrical Characteristics (2) [Vcc = 5 V]
(Topr = -40 to 85°C (J versi on) / -40 to 125 °C (K version), unless otherwise specified.)
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
ICC Power supply current
(VCC = 3.3 to 5.5 V)
Single-chip mode,
output pins are open,
other pins are VSS
High-speed
clock mode XIN = 20 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
−10 17 mA
XIN = 16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
−915mA
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
−6−mA
XIN = 20 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−5−mA
XIN = 16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−4−mA
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−2.5 −mA
High-speed
on-chip
oscillator
mode
XIN clock off
High-speed on-chip oscillat or on fOC O = 20 MH z (J vers ion)
Low-speed on-chip oscillator on = 125 kHz
No division
−10 15 mA
XIN clock off
High-speed on-chip oscillat or on fOC O = 20 MH z (J vers ion)
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−4−mA
XIN clock off
High-speed on-chip oscillator on fOCO = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
−5.5 10 mA
XIN clock off
High-speed on-chip oscillator on fOCO = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−2.5 −mA
Low-speed
on-chip
oscillator
mode
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8, FMR47 = 1
−130 300 µA
Wait mode XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−25 75 µA
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−23 60 µA
Stop mode XIN clock off, Topr = 25°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
−0.8 3.0 µA
XIN clock off, Topr = 85°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
−1.2 −µA
XIN clock off, Topr = 125°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
−4.0 −µA
R8C/26 Group, R8C/27 Group 5. Electrical Characteristics
Rev.2.10 Sep 26, 2008 Page 63 of 69
REJ03B0168-0210
Timing Requirements
(Unless Otherwise Specified: VCC = 5 V, VSS = 0 V at Topr = 25°C) [VCC = 5 V]
Figure 5.27 XIN Input Timing Diagram when VCC = 5 V
Figure 5.28 TRAIO Input Timing Diagram when VCC = 5 V
Table 5.49 XIN Input
Symbol Parameter Standard Unit
Min. Max.
tc(XIN) XIN input cycle time 50 −ns
tWH(XIN) XIN input “H” width 25 −ns
tWL(XIN) XIN input “L” width 25 −ns
Table 5.50 TRAIO Input
Symbol Parameter Standard Unit
Min. Max.
tc(TRAIO) TRAIO input cycle time 100 −ns
tWH(TRAIO) TRAIO input “H” width 40 −ns
tWL(TRAIO) TRAIO input “L” width 40 −ns
XIN input
tWH(XIN)
tC(XIN)
tWL(XIN)
VCC = 5 V
TRAIO input
VCC = 5 V
tC(TRAIO)
tWL(TRAIO)
tWH(TRAIO)
R8C/26 Group, R8C/27 Group 5. Electrical Characteristics
Rev.2.10 Sep 26, 2008 Page 64 of 69
REJ03B0168-0210
i = 0 or 1
Figure 5.29 Serial Interface Ti ming Diagram when VCC = 5 V
NOTES:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
Figure 5.30 External Interrupt INTi Input Timing Diagram when VCC = 5 V
Table 5.51 Serial Interface
Symbol Parameter Standard Unit
Min. Max.
tc(CK) CLKi input cycle time 200 −ns
tW(CKH) CLKi input “H” width 100 −ns
tW(CKL) CLKi input “L” width 100 −ns
td(C-Q) TXDi output delay time −50 ns
th(C-Q) TXDi hold time 0 −ns
tsu(D-C) RXDi input setup time 50 −ns
th(C-D) RXDi input hold time 90 −ns
Table 5.52 External Interrupt INTi (i = 0, 1, 3) Input
Symbol Parameter Standard Unit
Min. Max.
tW(INH) INTi input “H” width 250(1) −ns
tW(INL) INTi input “L” width 250(2) −ns
tW(CKH)
tC(CK)
tW(CKL) th(C-Q)
th(C-D)
tsu(D-C)td(C-Q)
CLKi
TXDi
RXDi
i = 0 or 1
VCC = 5 V
INTi input
tW(INL)
tW(INH)
i = 0, 1, 3
VCC = 5 V
R8C/26 Group, R8C/27 Group 5. Electrical Characteristics
Rev.2.10 Sep 26, 2008 Page 65 of 69
REJ03B0168-0210
NOTE:
1. VCC = 2.7 to 3.3 V at Topr = -40 to 85°C (J version) / -40 to 125°C (K version), f(XIN) = 10 MHz, unless otherwise specified.
Table 5.53 Electrical Characteristics (3) [V CC = 3 V]
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
VOH Output “H” voltage Except XOUT IOH = -1 mA VCC - 0.5 −VCC V
XOUT Drive capacity
HIGH IOH = -0.1 mA VCC - 0.5 −VCC V
Drive capacity
LOW IOH = -50 µAVCC - 0.5 −VCC V
VOL Output “L” voltage Except XOUT IOL = 1 mA −−0.5 V
XOUT Drive capacity
HIGH IOL = 0.1 mA −−0.5 V
Drive capacity
LOW IOL = 50 µA−−0.5 V
VT+-VT- Hysteresis INT0, INT1, INT3,
KI0, KI1, KI2, KI3,
TRAIO, RXD0, RXD1,
CLK0,CLK1,
SSI, SCL, SDA, SSO
0.1 0.3 −V
RESET 0.1 0.4 −V
IIH Input “H” current VI = 3 V, VCC = 3V −−4.0 µA
IIL Input “L” current VI = 0 V, VCC = 3V −−-4.0 µA
RPULLUP Pull-up resistance VI = 0 V, VCC = 3V 66 160 500 kΩ
RfXIN Feedback resistance XIN −3.0 −MΩ
VRAM RAM hold voltage During stop mode 2.0 −−V
R8C/26 Group, R8C/27 Group 5. Electrical Characteristics
Rev.2.10 Sep 26, 2008 Page 66 of 69
REJ03B0168-0210
Table 5.54 Electrical Characteristics (4) [Vcc = 3 V]
(Topr = -40 to 85°C (J versi on) / -40 to 125 °C (K version), unless otherwise specified.)
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
ICC Power supply current
(VCC = 2.7 to 3.3 V)
Single-chip mode,
output pins are open,
other pins are VSS
High-speed
clock mode XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
−6−mA
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−2−mA
High-speed
on-chip
oscillator
mode
XIN clock off
High-speed on-chip oscillator on fOCO = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
−59mA
XIN clock off
High-speed on-chip oscillator on fOCO = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−2−mA
Low-speed
on-chip
oscillator
mode
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8, FMR47 = 1
−130 300 µA
Wait mode XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−25 70 µA
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−23 55 µA
Stop mode XIN clock off, Topr = 25°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
−0.7 3.0 µA
XIN clock off, Topr = 85°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
−1.1 −µA
XIN clock off, Topr = 125°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
−3.8 −µA
R8C/26 Group, R8C/27 Group 5. Electrical Characteristics
Rev.2.10 Sep 26, 2008 Page 67 of 69
REJ03B0168-0210
Timing requirements
(Unless Otherwise Specified: VCC = 3 V, VSS = 0 V at Topr = 25°C) [VCC = 3 V]
Figure 5.31 XIN Input Timing Diagram when VCC = 3 V
Figure 5.32 TRAIO Input Timing Diagram when VCC = 3 V
Table 5.55 XIN Input
Symbol Parameter Standard Unit
Min. Max.
tc(XIN) XIN input cycle time 100 −ns
tWH(XIN) XIN input “H” width 40 −ns
tWL(XIN) XIN input “L” width 40 −ns
Table 5.56 TRAIO Input
Symbol Parameter Standard Unit
Min. Max.
tc(TRAIO) TRAIO input cycle time 300 −ns
tWH(TRAIO) TRAIO input “H” width 120 −ns
tWL(TRAIO) TRAIO input “L” width 120 −ns
XIN input
tWH(XIN)
tC(XIN)
tWL(XIN)
VCC = 3 V
TRAIO input
VCC = 3 V
tC(TRAIO)
tWL(TRAIO)
tWH(TRAIO)
R8C/26 Group, R8C/27 Group 5. Electrical Characteristics
Rev.2.10 Sep 26, 2008 Page 68 of 69
REJ03B0168-0210
i = 0 or 1
Figure 5.33 Serial Interface Ti ming Diagram when VCC = 3 V
NOTES:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
Figure 5.34 External Interrupt INTi Input Timing Diagram when VCC = 3 V
Table 5.57 Serial Interface
Symbol Parameter Standard Unit
Min. Max.
tc(CK) CLKi input cycle time 300 −ns
tW(CKH) CLKi input “H” width 150 −ns
tW(CKL) CLKi Input “L” width 150 −ns
td(C-Q) TXDi output delay time −80 ns
th(C-Q) TXDi hold time 0 −ns
tsu(D-C) RXDi input setup time 70 −ns
th(C-D) RXDi input hold time 90 −ns
Table 5.58 External Interrupt INTi (i = 0, 1, 3) Input
Symbol Parameter Standard Unit
Min. Max.
tW(INH) INTi input “H” width 380(1) −ns
tW(INL) INTi input “L” width 380(2) −ns
tW(CKH)
tC(CK)
tW(CKL) th(C-Q)
th(C-D)
tsu(D-C)td(C-Q)
CLKi
TXDi
RXDi
VCC = 3 V
i = 0 or 1
INTi input
tW(INL)
tW(INH)
VCC = 3 V
i = 0, 1, 3
Rev.2.10 Sep 26, 2008 Page 69 of 69
REJ03B0168-0210
R8C/26 Group, R8C/27 Group Package Dimensions
Package Dimensions
Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of
the Renesas Technology website.
2.
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
NOTE)
DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
y
Index mark
*3
F
32
25
24 17
16
9
81
*1
*2
x
b
p
e
H
E
E
D
H
D
Z
D
Z
E
Detail F
L
1
L
A
c
A
2
A
1
Previous CodeJEITA Package Code RENESAS Code
PLQP0032GB-A 32P6U-A
MASS[Typ.]
0.2gP-LQFP32-7x7-0.80
1.0
0.125
0.35
0.7
0.7
0.20
0.20
0.145
0.09
0.420.370.32
MaxNomMin
Dimension in Millimeters
Symbol
Reference
7.17.06.9
D
7.17.06.9
E
1.4
A
2
9.29.08.8
9.29.08.8
1.7
A
0.20.1
0
0.70.50.3
L
x
8°0°
c
0.8
e
0.10
y
H
D
H
E
A
1
b
p
b
1
c
1
Z
D
Z
E
L
1
Terminal cross section
b
1
c
1
bp
c
A - 1
REVISION HISTORY R8C/26 Group, R8C/27 Group Datasheet
Rev. Date Description
Page Summary
0.10 Nov 14, 2005 −First edition issued
0.20 Feb 06, 2006 2, 3 Table 1.1 Functions and Specifications for R8C/26Group and Table 1.2
Functions and Specificatio ns for R8C/27 Group;
Minimum instruction execution time and Supply voltage revised
9 Table 1.6 Pin Name Information by Pin Number;
“XOUT” → “XOUT/XCOUT” and “XIN” → “XIN/XCIN” revised
18 Table 4.4 SFR Informatio n (4 );
00FEh: “DRR” → “P1DRR” revised
19 Table 4.5 SFR Informatio n (5 );
-0119h: “Timer RE Minute Data Register / Compare Register” →
“Timer RE Minute Data Register / Compare Dat a Register”
-011Ah: “Timer RE Time Data Register” →
“Timer RE Hour Data Register”
-011Bh: “Timer RE Day Data Register” →
“Timer RE Day of Week Da ta Register” revised
22 to 45 5. Electrical Characteristics added
1.00 Nov 08, 2006 All pages “Preliminary” deleted
2 Table 1.1 revised
3 Table 1.2 revised
4 Figure 1.1 revised
5 Table 1.3 revised
6 Table 1.4 revised
7 Figure 1.4 revised
9 Table 1.6 revised
15 Table 4.1;
• 001Ch: “00h” → “00h, 10000000b” revised
• 000Fh: “000XXXXXb” → “00X11111b” revised
• 0029h: “High-Speed On-Chip Oscillator Control Register 4, FRA4,
When shipping” added
• 002Bh: “High-Speed On-Chip Oscillator Control Register 6, FRA6,
When shipping” added
•0032h: “00h, 01000000b” → “00h, 00100000b” revised
•0038h: “00001000b, 01001001b” → “0000X000b, 0100X001b” revised
• NOTE3 and 4 revised; NOTE6 added
18 Table 4.4;
• 00E0h, 00E1h, 00E5h, 00E8h, 00E9h: “XXh” → “00h” revised
• 00FDh: “XX00000000b ” → “00h” revised
22 Table 5.2 revised
23 F i g ur e 5. 1 title revised
24 Table 5.4 revised
25 Table 5.5 revised
26 Figure 5.2 title revised and Table 5.7 NOTE 4 added
REVISION HISTORY R8C/26 Group, R8C/27 Group Datasheet
A - 2
REVISION HISTORY R8C/26 Group, R8C/27 Group Datasheet
1.00 Nov 08, 2006 27 Table 5.9, Figure 5.3 revised and Table 5.10 deleted
28 Table 5.10, Table 5.11 revised
34 Table 5.15 rev i sed
35 Table 5.16 rev i sed
36 Table 5.17 rev i sed
39 Table 5.22 rev i sed
40 Table 5.23 rev i sed
44 Table 5.29 rev i sed
47 Package Dimensions; “Diagrams showing the latest...website.” added
1.10 Nov 29, 2006 All pages “J, K version” added
1 1 “J and K versions are under development...notice.” added
1.1 revised
2 Table 1.1 revised
3 Table 1.2 revised
4 Figure 1.1 NOTE3 add e d
5 Table 1.3, Figure 1.2 revised
6 Table 1.4, Figure 1.3 revised
7 Figure 1.4 NOTE3 add e d
8 Table 1.5 revised
9 Table 1.6 NOTE2 added
13 F i g ure 3.1 revised
14 F i g ure 3.2 revised
15 Table 4.1; “0000h to 003Fh” → “0000h to 002Fh” revised
• NOTE3 added
16 Table 4.2; “0040h to 007Fh” → “0030h to 007Fh” revised
• 0032h, 0036h: “After re set” is revised
• 0038h: NOTE revised
• NOTES 2, 5, 6 revised and NOTE 7, 8 added
19 Table 4.5 NOTE2 added
28 Table 5.10 rev i sed
48 to 66 5.2 J, K Version added
1.20 Jan 17, 2007 18 Table 4.4 NOTE2 added
1.30 May 25, 2007 2 Table 1.1 revised
3 Table 1.2 revised
5 Table 1.3 revised
6 Figure 1.2 revised
7 Table 1.4 revised
8 Figure 1.3 revised
9 Figure 1.4 NOTE4 add e d
15 F i g ure 3.1 part number revised
Rev. Date Description
Page Summary
A - 3
REVISION HISTORY R8C/26 Group, R8C/27 Group Datasheet
1.30 May 25, 2007 16 Figure 3.2 part number revised
30 Table 5.10 rev ised
53 Table 5.39 NOTE4 added
55 Table 5.42 rev ised
1.40a Jun 14, 2007 5 , 7 Table 1. 3 an d Table 1.4 revised
2.00 Mar 01, 2008 1, 49 1.1, 5.2 “J and K versions are ...” deleted
5, 7 Table 1.3, Table 1.4 revised
11 Table 1.6 NOTE3 added
15, 16 Figure 3.1, Figure 3.2; “Expanded area” deleted
17 Table 4.1 “002Ch ” added
18 Table 4.2 “0036h” ; J, K versio n “0 10 0 X00 0 b” → “0100X001b”
24, 49 Table 5.2, Table 5.35; NOTE2 revised
30 Table 5.10 revised, NOTE4 added
2.10 Sep 26, 2008 −“RENESAS TECHNICAL UP DATE” reflected: TN-16C-A172A/E
26, 51 Table 5.4, Ta ble 5.37 NO TE2, NOTE4 revised
27, 52 Table 5.5, Ta ble 5.38 NO TE2, NOTE5 revised
53 Table 5.39 Parameter: Voltage monitor 1 reset generation time added
NOTE5 added
Table 5.40 revised
54 Table 5.41 rev ised
Figure 5. 22 rev ised
Rev. Date Description
Page Summary
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