A19-A0.

A19-A0 form a 20-bit address bus. The Address Bus

provides the address for memory data bus exchanges up

address bus enters a high impedance state during reset

channel 1 (TOUT, selected as address output on reset).

/MRD.

active. /MRD is multiplexed with /MREQ on the /MRD

//MREQ pin. The /MRD//MREQ pin is an input during

adapter modes; is tri-state during bus acknowledge if

/MREQ function is selected; and is inactive High if /MRD

Interrupt Edge/Pin MUX Register (xxDFH).

/NMI.

/NMI has a higher priority than /INT and is

of the state of the interrupt enable flip-flops. This signal

forces CPU execution to continue at location 0066H.

/INT0.

This signal is generated by external I/O devices. The

instruction cycle as long as the /NMI and /BUSREQ signals

/INT1, /INT2.

devices. The CPU will honor these requests at the end of

the current instruction cycle as long as the /NMI, /BUSREQ,

and /INT0 signals are inactive. The CPU acknowledges

these interrupt requests with an interrupt acknowledge

cycle. Unlike the acknowledgment for /INT0, during this

cycle neither the /M1 or /IORQ signals become active.

These pins may be programmed to provide an active Low

level on rising or falling edge interrupts. The level of the

/TEND0.

is asserted active during the last write cycle of a DMA

CKA1//TEND0 pin.

/TEND1.

is asserted active during the last write cycle of a DMA

/DREQ0.

CKA0//DREQ0 pin.

/DREQ1.

These pins can act as either inputs, outputs, or as

part of the crystal oscillator circuit. In the Asynchronous

these pins are inputs similar to /CTS and /DCD. In this

mode, transitions on these lines affect the state of the Sync

/Hunt status bits in Read Register 0, but have no other

Port C, bit 4) on the /SYNCA/PC4 pin.

/DCDB.

This pin’s

functionality is similar to /DCDA but applicable to the

channel B receiver. In Z80182/Z8L182 mode 1, /DCDB is

the /DCDB//HRD pin.

/RTSA.

/HTxRDY signal on the CKS//W//REQB//HTxRDY pin.

individual units of the Z182.

Functionally, the on-chip Z182 MPU and ESCC™ are the

same as the discrete devices (Figure 1). Therefore, for a

detailed description of each individual unit, refer to the

Z182 MPU FUNCTIONAL DESCRIPTION

CPU and has the following additional features:

Faster Execution Speed. The Z182 CPU is “fine tuned,”

making execution speed, on average, 10% to 20% faster

than the Z80 CPU.

Enhanced DRAM Refresh Circuit. Z182 CPU’s DRAM

8-bit refresh address. It can be disabled or the refresh

period adjusted, through software control.

addressing space) into 1 Mbyte of physical addressing

an effective common area-banked area scheme.

peripheral. The ESCC functions as a serial-to-parallel,

were made to the CMOS SCC:

The following features are implemented in the ESCC™ for

the Z80182/Z8L182 only:

- Up to 1/4 of the PCLK using external clock source

- Up to 5 Mbits/sec at 20 MHz PCLK (ESCC).

4 bits/character or less)

diagram of the discrete ESCC, which was integrated into the Z182. The /INT line is internally connected to "INTO of the

storing eight data bits and three error bits for each character

stored (Figure 7). Parity error, Framing error and Break

detect bits are stored along with the data bits by copying

their value from three shadow bits that are Write Only bits

are cleared after they are copied to the FIFO memory. In

FIFO mode, to write error bits into the receiver FIFO, the

MPU must first write the Parity, Framing and Break detect

status to the Line Status Register (shadow bits) and then

the interface when that particular location becomes the

either be read by the PC by accessing them in the LSR, or

they may cause an interrupt to the PC interface if so

enabled. The error bits are set by the error status of the byte

at the top of the FIFO, but may only be cleared by reading

performed without reading the LSR, the status bits will be

set if any of the bytes read have the respective error bit set.

Bit 7.

of the part, i.e., an external clock at 66 MHz with 50% duty

Table 17. Transmitter Trigger Level

on the XMIT FIFO. The counter reloads each time there is

a read or write to the XMIT FIFO.

Transmit And Receive Timers