Silego Technology, Inc. Rev 1.05
000-0046722-105 Revised August 29, 2014
GreenPAK 3
Programmable Mixed Signal Array
SLG46722
Block Diagram
Features
• Logic & Mixed Signal Circuits
• Highly Versatile Macro Cells
• Read Back Protection (Read Lock)
• 1.8V (±5%) to 5V (±10%) Supply
• Operating Tempe ra tu r e Range: -40°C to 85°C
• RoHS Compliant / Halogen-Free
• 20-pin STQFN: 2 x 3 x 0.55 mm, 0.4 mm pitch
Applications
• Personal Computers and Servers
• PC Peripherals
• Consumer Electronics
• Data Communications Equipment
• Handheld and Portable Electronics
Pin Configuration
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
2
3
414
15
16
17
GPI
VDD 1
STQFN-20
(Top View)
GPIO
GPIO 5
6GPIO
GPIO
12
13
GPIO 7GND
11
GPIO
GPIO
89
GPIO
10
GPIO
GPIO
18
19
GPIO
20
Pin 6
GPIO
Programmable
Delay
RC Oscillator
Pin 7
GPIO
Pin 1
VDD
Pin 2
GPI
Pin 3
GPIO
Pin 4
GPIO
Pin 5
GPIO
Pin 20
GPIO Pin 19
GPIO Pin 18
GPIO
Pin 8
GPIO Pin 9
GPIO Pin 10
GPIO
Pin 12
GPIO
Pin 11
GND
Pin 17
GPIO
Pin 16
GPIO
Pin 15
GPIO
Pin 14
GPIO
Pin 13
GPIO
FILTER_0 FILTER_1
Additional Logic Functions
Look Up Tables (LUTs)
Counters/Delay Generators
CNT0 CNT1
2-bit
LUT2_1 3-bit
LUT3_3
2-bit
LUT2_2
3-bit
LUT3_0 3-bit
LUT3_2
3-bit
LUT3_1
3-bit
LUT3_5 3-bit
LUT3_7
3-bit
LUT3_6
Combination Function Macrocells
2-bit LUT2_0
or
DFF4
3-bit LUT3_8
or
Pipe Delay
CNT2 CNT3
CNT4 CNT5 CNT6 CNT7
D Flip Flops (DFF) / Latches
DFF0 DFF1 DFF2
DFF3 DFF5 DFF6
2-bit
LUT2_5
2-bit
LUT2_4
3-bit
LUT3_4
3-bit
LUT3_3
4-bit
LUT4_0
3-bit
LUT3_9
000-0046722-105 Page 1 of 79
SLG46722
1.0 Overview
The SLG46722 provides a small, low power component for commonly used mixed-signal functions. The user creates their circuit
design by programming the one time Non-V olatile Memory (NVM) to configure the interconnect logic, the I/O Pins and the macro
cells of the SLG46722. This high ly versatile device allows a wide variety of mixed-sign al functions to be de signed within a ver y
small, low power single integrated circu it. The macro cells in the device include the following:
• Fifteen Combinatorial Look Up Tables (LUTs)
• Five 2-bit LUTs
• Nine 3-bit LUTs
• One 4-bit LUT
• Two Combination Function Macro cell
• One Selectable FF/Latch or 2-bit LUT
• One Selectable Pipe Delay or 3-bit LUT
• Pipe Delay – 16 stage / 3 output
• Eight Counter / Delay Generators (CNT/DLY)
• One 14-bit delay/counter
• One 14-bit delay/counte r with external clock/reset
• Four 8-bit delays/counters
• Two 8-bit delays/counters with external clock/reset
• Six D Flip-Flop / Latches (DFF)
• Pipe Delay – 16 stage/3 output (Part of Combination Function Macrocell)
• Programmable Delay
• Additional Logic Functions – 2 Deglitch Filters
• RC Oscillator (RC OSC)
000-0046722-105 Page 2 of 79
SLG46722
2.0 Pin Description
2.1 Functional and Programming Pin Description
Pin # Pin Name Function Programming Function
1 VDD Power Supply Power Supply
2 GPI General Purpose Input VPP (Programming Voltage)
3 GPIO General Purpose I/O Reset
4 GPIO General Purpose I/O N/A
5 GPIO General Purpose I/O N/A
6 GPIO General Purpose I/O N/A
7 GPIO General Purpose I/O N/A
8 GPIO General Purpose I/O or POR Output N/A
9 GPIO General Purpose I/O N/A
10 GPIO General Purpose I/O N/A
11 GND Ground Ground
12 GPIO General Purpose I/O N/A
13 GPIO General Purpose I/O N/A
14 GPIO General Purpose I/O N/A
15 GPIO General Purpose I/O N/A
16 GPIO General Purpose I/O Programming Mode Control
17 GPIO General Purpose I/O Programming ID Pin
18 GPIO General Purpose I/O Programming SDIO Pin
19 GPIO General Purpose I/O Programming SRDWB Pin
20 GPIO General Purpose I/O or External Clock Programming SCL Pin
000-0046722-105 Page 3 of 79
SLG46722
3.0 User Programmability
The SLG46722 is a user programmable device with One-T ime-Programmable (OTP) memory elements that are able to construct
combinatorial logic elements. Three of the I/O Pins provide a connection for the bit patterns into the OTP on board memory. A
programming development kit allows the user the a bility to create initial device s. Once the design is finali zed, th e programmi ng
code (.gpx file) is forwarded to Silego to integrate into a production process.
Figure 1. Steps to create a custom Silego GreenPAK device
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000-0046722-105 Page 4 of 79
SLG46722
4.0 Ordering Information
Part Number Type
SLG46722V 20-pin STQFN
SLG46722VTR 20-pin STQFN - Tape and Reel (3k units)
000-0046722-105 Page 5 of 79
SLG46722
5.0 Electrical Specifications
5.1 Absolute Maximum Conditions
5.2 Electrical Characteristics (1.8V ±5% VDD)
Parameter Min. Max. Unit
VHIGH to GND -0.3 7 V
Voltage at Input Pin -0.3 7 V
Current at Input Pin -1.0 1.0 mA
Storage Temperature Range -65 150 °C
Junction Temperature -- 150 °C
ESD Protection (Human Body Model) 2000 -- V
ESD Protection (Charged Device Model) 1300 -- V
Moisture Sensitivity Level 1
Symbol Parameter Condition/Note Min. Typ. Max. Unit
VDD Supply Voltage 1.71 1.80 1.89 V
TAOperating Temperature -40 25 85 °C
VPP Programming Voltage 7.25 7.50 7.75 V
VIH HIGH-Level Input Voltage Logic Input 1.100 -- -- V
Logic Input with Schmitt Trigger 1.270 -- -- V
Low-Level Logic Input 0.980 -- -- V
VIL LOW-Level Input Voltage Logic Input -- -- 0.69 0 V
Logic Input with Schmitt Trigger -- -- 0.440 V
Low-Level Logic Input -- -- 0.520 V
IIH HIGH-Level Input Current Logic Input Pins; VIN = 1.8 V -1.0 -- 1.0 μA
IIL LOW-Level Input Current Logic Input Pins; VIN = 0 V -1.0 -- 1.0 μA
VOH HIGH-Level Outp ut Voltage
Push-Pull, IOH = 100 μA, 1X Driver 1.690 1.789 -- V
PMOS OD, IOH = 100 μA, 1X Driver 1.690 1.789 -- V
Push-Pull, IOH = 100 μA, 2X Driver 1.700 1.794 -- V
PMOS OD, IOH = 100 μA, 2X Driver 1.700 1.794 -- V
VOL LOW-Level Output Voltage
Push-Pull, IOL= 100 μA, 1X Driver -- 0.008 0.030 V
Push-Pull, IOL = 100 μA, 2X Driver -- 0.004 0.010 V
Open Drain, IOL = 100 μA, 1X Driver -- 0.005 0.020 V
Open Drain, IOL = 100 μA, 2X Driver -- 0.003 0.010 V
IOH HIGH-Level Outp ut Current
Push-Pull, VOH = VDD - 0.2, 1X Driver 1.066 1.703 -- mA
PMOS OD, VOH = VDD - 0.2, 1X Driver 1.067 1.703 -- mA
Push-Pull, VOH = VDD - 0.2, 2X Driver 2.216 3.406 -- mA
PMOS OD, VOH = VDD - 0.2, 2X Driver 2.220 3.406 -- mA
000-0046722-105 Page 6 of 79
SLG46722
IOL LOW-Level Output Current
Push-Pull, VOL = 0.15 V, 1X Driver 0.917 1.689 -- mA
Push-Pull, VOL = 0.15 V, 2X Driver 1.834 3.378 -- mA
Open Drain, VOL = 0.15 V, 1X Driver 1.375 2.534 -- mA
Open Drain, VOL = 0.15 V, 2X Driver 2.750 5.068 -- mA
Open Drain, VOL = 0.15 V, Su per Drive 5.500 10.136 -- mA
TSU Startup Time -- 1 -- ms
Symbol Parameter Condition/Note Min. Typ. Max. Unit
000-0046722-105 Page 7 of 79
SLG46722
5.3 Electrical Characteristics (3.3V ±10% VDD)
Symbol Parameter Condition/Note Min. Typ. Max. Unit
VDD Supply Voltage 3.0 3.3 3.6 V
TAOperating Temperature -40 25 85 °C
VPP Programming Voltage 7.25 7.50 7.75 V
VIH HIGH-Level Input Voltage Logic Input 1.780 -- -- V
Logic Input with Schmitt Trigger 2.130 -- -- V
Low-Level Logic Input 1.130 -- -- V
VIL LOW-Level Input Voltage Logic Input -- -- 1.21 0 V
Logic Input with Schmitt Trigger -- -- 0.950 V
Low-Level Logic Input -- -- 0.690 V
IIH HIGH-Level Input Current Logic Input Pins; VIN = 3.3 V -1.0 -- 1.0 μA
IIL LOW-Level Input Current Logic Input Pins; VIN = 0 V -1.0 -- 1.0 μA
VOH HIGH-Level Outp ut Voltage
Push-Pull, IOH = 3 mA, 1X Driver 2.735 3.120 -- V
PMOS OD, IOH = 3 mA, 1X Driver 2.735 3.120 -- V
Push-Pull, IOH = 3 mA, 2X Driver 2.870 3.210 -- V
PMOS OD, IOH = 3 mA, 2X Driver 2.870 3.210 -- V
VOL LOW-Level Output Voltage
Push-Pull, IOL= 3 mA, 1X Driver -- 0.130 0.228 V
Push-Pull, IOL = 3 mA, 2X Driver -- 0.060 0.108 V
Open Drain, IOL = 3 mA, 1X Driver -- 0.080 0.147 V
Open Drain, IOL = 3 mA, 2X Driver -- 0.040 0.080 V
IOH HIGH-Level Outp ut Current
Push-Pull, VOH = 2.4 V, 1X Driver 6.045 12.080 -- mA
PMOS OD, VOH = 2.4 V, 1X Driver 6.045 12.080 -- mA
Push-Pull, VOH = 2.4 V, 2X Driver 11.543 24.160 -- mA
PMOS OD, VOH = 2.4 V, 2X Driver 11.522 24.160 -- mA
IOL LOW-Level Output Current
Push-Pull, VOL = 0.4 V, 1X Driver 4.875 8.244 -- mA
Push-Pull, VOL = 0.4 V, 2X Driver 9.750 16.488 -- mA
Open Drain, VOL = 0.4 V, 1X Driver 7.313 12.370 -- mA
Open Drain, VOL = 0.4 V, 2X Driver 14.541 24.740 -- mA
Open Drain, VOL = 0.4 V, Super Drive 25.801 49.480 -- mA
TSU Startup Time -- 1 -- ms
000-0046722-105 Page 8 of 79
SLG46722
5.4 Electrical Characteristics (5 V ±10% VDD)
Symbol Parameter Condition/Note Min. Typ. Max. Unit
VDD Supply Voltage 4.5 5.0 5.5 V
TAOperating Temperature -40 25 85 °C
VPP Programming Voltage 7.25 7.50 7.75 V
VIH HIGH-Level Input Voltage Logic Input 2.640 -- -- V
Logic Input with Schmitt Trigger 3.160 -- -- V
Low-Level Logic Input 1.230 -- -- V
VIL LOW-Level Input Voltage Logic Input -- -- 1.84 0 V
Logic Input with Schmitt Trigger -- -- 1.510 V
Low-Level Logic Input -- -- 0.780 V
IIH HIGH-Level Input Current Logic Input Pins; VIN = 5 V -1.0 -- 1.0 μA
IIL LOW-Level Input Current Logic Input Pins; VIN = 0 V -1.0 -- 1.0 μA
VOH HIGH-Level Outp ut Voltage
Push-Pull, IOH = 5 mA, 1X Driver 4.19 4.78 -- V
PMOS OD, IOH = 5 mA, 1X Driver 4.19 4.78 -- V
Push-Pull, IOH = 5 mA, 2X Driver 4.32 4.89 -- V
PMOS OD, IOH = 5 mA, 2X Driver 4.32 4.89 -- V
VOL LOW-Level Output Voltage
Push-Pull, IOL= 5 mA, 1X Driver -- 0.157 0.270 V
Push-Pull, IOL = 5 mA, 2X Driver -- 0.076 0.130 V
Open Drain, IOL = 5 mA, 1X Driver -- 0.102 0.180 V
Open Drain, IOL = 5 mA, 2X Driver -- 0.051 0.110 V
IOH HIGH-Level Outp ut Current
Push-Pull, VOH = 2.4 V, 1X Driver 22.08 34.04 -- mA
PMOS OD, VOH = 2.4 V, 1X Driver 22.08 34.04 -- mA
Push-Pull, VOH = 2.4 V, 2X Driver 41.76 68.08 -- mA
PMOS OD, VOH = 2.4 V, 2X Driver 41.69 68.08 -- mA
IOL LOW-Level Output Current
Push-Pull, VOL = 0.4 V, 1X Driver 7.215 11.580 -- mA
Push-Pull, VOL = 0.4 V, 2X Driver 13.831 23.160 -- mA
Open Drain, VOL = 0.4 V, 1X Driver 10.820 17.380 -- mA
Open Drain, VOL = 0.4 V, 2X Driver 17.343 34.760 -- mA
Open Drain, VOL = 0.4 V, Super Drive 30.964 69.520 -- mA
TSU Startup Time -- 1 -- ms
000-0046722-105 Page 9 of 79
SLG46722
6.0 Summary of Macro Cell Function
6.1 I/O Pins
• Digital Input (low voltage or normal voltage, with or without Schmitt Trigger)
• Open Drain Outputs
• Push Pull Outputs
• 10 kΩ/100 kΩ/1 MΩ pull-up/pull-down resistors
• 40mA Open Drain Superdrive output
6.2 Connection Matrix
• Digital matrix for circuit connections based on user design
6.3 Combinational Logi c Lo ok Up Tables (LUTs – 15 total)
• Five 2-bit Lookup Tables
• Nine 3-bit Lookup Tables
• One 4-bit Lookup Tables
6.4 Combination Function Macrocell (2 total)
• One Selectable FF/Latch or 2-bit LU T
• One Selectable Pipe Delay or 3-bit LUT
6.5 Delays/Counters (8 total)
• One 14-bit delay/counter: Range 1-16384 clock cycles
• One 14-bit delay/counter with external clock/reset: Range 1-16384 clock cycles
• Four 8-bit delays/counters: Range 1-255 clock cycles
• Two 8-bit delays/counters with external clock/reset: Range 1-255 clock cycles
6.6 Digital Storage Elements (6 total)
• Six D Flip-Flops or Latches
6.7 Pipe Delay (Part of Combination Function Macrocell)
• 16 stage / 3 output
• One 1 stage fixed output
• Two 1-16 stage selectable outputs.
6.8 Programmable Delay
• 125 ns/250 ns/375 ns/500 ns @ 3.3 V
• Includes Edge Detection function
6.9 Additional Logic Functions (2 total)
• Two Deglitch filter macro cells
6.10 RC Oscillator
• 25 kHz and 2 MHz selectable frequency
• First stage divider (4): OSC/1, OSC/2, OSC/4, and OSC/8
• Second stage divider (5): OSC/1, OSC/4, selectable (OSC/8, OSC/12, OSC/24, or OSC/64), OSC/3, and additional OSC/3
(from selectable output)
000-0046722-105 Page 10 of 79
SLG46722
7.0 I/O Pins
The SLG46722 has a total of 18 multi-fu nction I/O pins which can function as either a user define d Input or Output, as well as
serving as a special function (such as outp utting the voltage reference), or serving as a signal for programming of the on-ch ip
Non Volatile Memory (NVM).
Normal Mode pin definitions are as follows:
• Pin 2: general purpose input
• Pin 3: general purpose input or output
• Pin 4: general purpose input or output
• Pin 5: general purpose input or output
• Pin 6: general purpose input or output
• Pin 7: general purpose input or output
• Pin 8: general purpose input or output or POR ou tput
• Pin 9: general purpose input or output
• Pin 10: general purpose input or outp ut
• Pin 12: general purpose input or outp ut
• Pin 13: general purpose input or outp ut
• Pin 14: general purpose input or outp ut
• Pin 15: general purpose input or outp ut
• Pin 16: general purpose input or outp ut
• Pin 17: general purpose input or outp ut
• Pin 18: general purpose input or outp ut
• Pin 19: general purpose input or outp ut
• Pin 20: general purpose input or output or external clock
Programming Mode pin definitions are as follows;
• Pin 1: Vdd power supply
• Pin 2: Vpp programming voltage
• Pin 11: grou nd
• Pin 16: programmi ng mode control
• Pin 17: programming ID pin
• Pin 18: programmi ng SDIO pin
• Pin 19: programmi ng SRDWB pin
• Pin 20: programming SCL pin
Of the 18 user defined I/O pins on the SLG46722, all but one of the pins (Pin 2) can serve as both digital input and digital output.
Pin 2 can only serve as a digital input pin.
7.1 Input Modes
Each I/O pin can be confi gured as a digital input pin with/without buffered Schmitt Trigger, or can also be configured as a low
voltage digital input.
7.2 Output Modes
Pins 3, 4,5, 6, 7, 8, 9, 10, 12, 13, 14, 15, 16, 17, 18, 19 and 20 can all be configured as digital output pins.
7.3 Pull Up/Down Resistors
All I/O pins have the option for user selectable resistors connected to the input structure. The selectable values on these resistors
are 10 kΩ, 100 kΩ and 1 MΩ. In the case of Pin 2, the resistors are fixed to a pull-down configuration. In the case of all other I/O
pins, the internal resistors can be configur ed as either pull-up or pull-downs.
000-0046722-105 Page 1 1 of 79
SLG46722
7.4 I/O Register Settings
7.4.1 PIN 2 Register Settings
7.4.2 PIN 3 Register Settings
Table 1. PIN 2 Register Settings
Signal Function Register Bit
Address Register Definition
PIN 2 Mode Control <845:844> 00: Digital Input with out Schmitt Trigger
01: Digital Input with Schmitt Trigger
10: Low Voltage Digital Input
11: Reserved
PIN 2 Pull Down
Resistor Value
Selection
<847:846> 00: Floating
01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
Table 2. PIN 3 Register Settings
Signal Function Register Bit
Address Register Definition
PIN 3 Mode Control <850:848> 000: Di gital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Reserved
100: Push Pull
101: Open Drain NMOS
110: Open Drain PMOS
111: Reserved
PIN 3 Pull Up/Down
Resistor Value
Selection
<852:851> 00: Floating
01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
PIN 3 Pull Up/Down
Resistor Selection <853> 0: Pull Down Resistor
1: Pull Up Resistor
PIN 3 Driver
Strength Selection <854> 0: 1X
1: 2X
000-0046722-105 Page 12 of 79
SLG46722
7.4.3 PIN 4 Register Settings
7.4.4 PIN 5 Register Settings
Table 3. PIN 4 Register Settings
Signal Function Register Bit
Address Register Definition
PIN 4 Mode Control <857:855> 000: Di gital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Reserved
100: Push Pull
101: Open Drain NMOS
110: Open Drain PMOS
111: Reserved
PIN 4 Pull Up/Down
Resistor Value
Selection
<859:858> 00: Floating
01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
PIN 4 Pull Up/Down
Resistor Selection <860> 0: Pull Down Resistor
1: Pull Up Resistor
PIN 4 Driver
Strength Selection <861> 0: 1X
1: 2X
Table 4. PIN 5 Register Settings
Signal Function Register Bit
Address Register Definition
PIN 5 Mode Control <864:862> 000: Di gital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Reserved
100: Push Pull
101: Open Drain NMOS
110: Open Drain PMOS
111: Reserved
PIN 5 Pull Up/Down
Resistor Value
Selection
<866:865> 00: Floating
01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
PIN 5 Pull Up/Down
Resistor Selection <867> 0: Pull Down Resistor
1: Pull Up Resistor
PIN 5 Driver
Strength Selection <868> 0: 1X
1: 2X
000-0046722-105 Page 13 of 79
SLG46722
7.4.5 PIN 6 Register Settings
7.4.6 PIN 7 Register Settings
Table 5. PIN 6 Register Settings
Signal Function Register Bit
Address Register Definition
PIN 6 Mode Control <871:869> 000: Di gital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Reserved
100: Push Pull
101: Open Drain NMOS
110: Open Drain PMOS
111: Reserved
PIN 6 Pull Up/Down
Resistor Value
Selection
<873:872> 00: Floating
01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
PIN 6 Pull Up/Down
Resistor Selection <874> 0: Pull Down Resistor
1: Pull Up Resistor
PIN 6 Driver
Strength Selection <875> 0: 1X
1: 2X
Table 6. PIN 7 Register Settings
Signal Function Register Bit
Address Register Definition
PIN 7 Mode Control <878:876> 000: Di gital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Reserved
100: Push Pull
101: Open Drain NMOS
110: Open Drain PMOS
111: Reserved
PIN 7 Pull Up/Down
Resistor Value
Selection
<880:879> 00: Floating
01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
PIN 7 Pull Up/Down
Resistor Selection <881> 0: Pull Down Resistor
1: Pull Up Resistor
PIN 7 Driver
Strength Selection <882> 0: 1X
1: 2X
000-0046722-105 Page 14 of 79
SLG46722
7.4.7 PIN 8 Register Settings
7.4.8 PIN 9 Register Settings
Table 7. PIN 8 Register Settings
Signal Function Register Bit
Address Register Definition
PIN 8 Mode Control <885:883> 000: Di gital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Reserved
100: Push Pull
101: Open Drain NMOS
110: Open Drain PMOS
111: Reserved
PIN 8 Pull Up/Down
Resistor Value
Selection
<887:886> 00: Floating
01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
PIN 8 Pull Up/Down
Resistor Selection <888> 0: Pull Down Resistor
1: Pull Up Resistor
PIN 8 Driver
Strength Selection <889> 0: 1X
1: 2X
Table 8. PIN 9 Register Settings
Signal Function Register Bit
Address Register Definition
PIN 9 Mode Control <892:890> 000: Di gital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Reserved
100: Push Pull
101: Open Drain NMOS
110: Open Drain PMOS
111: Reserved
PIN 9 Pull Up/Down
Resistor Value
Selection
<894:893> 00: Floating
01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
PIN 9 Pull Up/Down
Resistor Selection <895> 0: Pull Down Resistor
1: Pull Up Resistor
PIN 9 Driver
Strength Selection <896> 0: 1X
1: 2X
000-0046722-105 Page 15 of 79
SLG46722
7.4.9 PIN 10 Register Settings
7.4.10 PIN 12 Register Settings
Table 9. PIN 10 Register Settings
Signal Function Register Bit
Address Register Definition
PIN 10 Mode
Control <899:897> 000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Reserved
100: Push Pull
101: Open Drain NMOS
110: Open Drain PMOS
111: Reserved
PIN 10 Pull
Up/Down Resistor
Value Selection
<901:900> 00: Floating
01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
PIN 10 Pull
Up/Down Resistor
Selection
<902> 0: Pull Down Resistor
1: Pull Up Resistor
PIN 10 Driver
Strength Selection <903> 0: 1X
1: 2X
PIN 10 Super Drive
(4X, NMOS Open
Drain) Selection
<904> 0: Super Drive Off
1: Super Drive On (if <897:899> = ‘101’)
Table 10. PIN 12 Register Settings
Signal Function Register Bit
Address Register Definition
PIN 12 Mode
Control <907:905> 000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Reserved
100: Push Pull
101: Open Drain NMOS
110: Open Drain PMOS
111: Reserved
PIN 12 Pull
Up/Down Resistor
Value Selection
<909:908> 00: Floating
01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
PIN 12 Pull
Up/Down Resistor
Selection
<910> 0: Pull Down Resistor
1: Pull Up Resistor
PIN 12 Driver
Strength Selection <911> 0: 1X
1: 2X
PIN 12 Super Drive
(4X, NMOS Open
Drain) Selection
<912> 0: Super Drive Off
1: Super Drive On (if <907:905> = ‘101’)
000-0046722-105 Page 16 of 79
SLG46722
7.4.11 PIN 13 Register Settings
7.4.12 PIN 14 Register Settings
Table 11. PIN 13 Register Settings
Signal Function Register Bit
Address Register Definition
PIN 13 Mode
Control <915:913> 000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Reserved
100: Push Pull
101: Open Drain NMOS
110: Open Drain PMOS
111: Reserved
PIN 13 Pull
Up/Down Resistor
Value Selection
<917:916> 00: Floating
01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
PIN 13 Pull
Up/Down Resistor
Selection
<918> 0: Pull Down Resistor
1: Pull Up Resistor
PIN 13 Driver
Strength Selection <919> 0: 1X
1: 2X
Table 12. PIN 14 Register Settings
Signal Function Register Bit
Address Register Definition
PIN 14 Mode
Control <922:920> 000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Reserved
100: Push Pull
101: Open Drain NMOS
110: Open Drain PMOS
111: Reserved
PIN 14 Pull
Up/Down Resistor
Value Selection
<924:923> 00: Floating
01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
PIN 14 Pull
Up/Down Resistor
Selection
<925> 0: Pull Down Resistor
1: Pull Up Resistor
PIN 14 Driver
Strength Selection <926> 0: 1X
1: 2X
000-0046722-105 Page 17 of 79
SLG46722
7.4.13 PIN 15 Register Settings
7.4.14 PIN 16 Register Settings
Table 13. PIN 15 Register Settings
Signal Function Register Bit
Address Register Definition
PIN 15 Mode
Control <929:927> 000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Reserved
100: Push Pull
101: Open Drain NMOS
110: Open Drain PMOS
111: Reserved
PIN 15 Pull
Up/Down Resistor
Value Selection
<931:930> 00: Floating
01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
PIN 15 Pull
Up/Down Resistor
Selection
<932> 0: Pull Down Resistor
1: Pull Up Resistor
PIN 15 Driver
Strength Selection <933> 0: 1X
1: 2X
Table 14. PIN 16 Register Settings
Signal Function Register Bit
Address Register Definition
PIN 16 Mode
Control <936:934> 000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Reserved
100: Push Pull
101: Open Drain NMOS
110: Open Drain PMOS
111: Reserved
PIN 16 Pull
Up/Down Resistor
Value Selection
<938:937> 00: Floating
01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
PIN 16 Pull
Up/Down Resistor
Selection
<939> 0: Pull Down Resistor
1: Pull Up Resistor
PIN 16 Driver
Strength Selection <940> 0: 1X
1: 2X
000-0046722-105 Page 18 of 79
SLG46722
7.4.15 PIN 17 Register Settings
7.4.16 PIN 18 Register Settings
Table 15. PIN 17 Register Settings
Signal Function Register Bit
Address Register Definition
PIN 17 Mode
Control <943:941> 000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Reserved
100: Push Pull
101: Open Drain NMOS
110: Open Drain PMOS
111: Reserved
PIN 17 Pull
Up/Down Resistor
Value Selection
<945:944> 00: Floating
01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
PIN 17 Pull
Up/Down Resistor
Selection
<946> 0: Pull Down Resistor
1: Pull Up Resistor
PIN 17 Driver
Strength Selection <947> 0: 1X
1: 2X
Table 16. PIN 18 Register Settings
Signal Function Register Bit
Address Register Definition
PIN 18 Mode
Control <950:948> 000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Reserved
100: Push Pull
101: Open Drain NMOS
110: Open Drain PMOS
111: Reserved
PIN 18 Pull
Up/Down Resistor
Value Selection
<952:951> 00: Floating
01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
PIN 18 Pull
Up/Down Resistor
Selection
<953> 0: Pull Down Resistor
1: Pull Up Resistor
PIN 18 Driver
Strength Selection <954> 0: 1X
1: 2X
000-0046722-105 Page 19 of 79
SLG46722
7.4.17 PIN 19 Register Settings
7.4.18 PIN 20 Register Settings
Table 17. PIN 19 Register Settings
Signal Function Register Bit
Address Register Definition
PIN 19 Mode
Control <957:955> 000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Reserved
100: Push Pull
101: Open Drain NMOS
110: Open Drain PMOS
111: Reserved
PIN 19 Pull
Up/Down Resistor
Value Selection
<959:958> 00: Floating
01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
PIN 19 Pull
Up/Down Resistor
Selection
<960> 0: Pull Down Resistor
1: Pull Up Resistor
PIN 19 Driver
Strength Selection <961> 0: 1X
1: 2X
Table 18. PIN 20 Register Settings
Signal Function Register Bit
Address Register Definition
PIN 20 Mode
Control <964:962> 000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Reserved
100: Push Pull
101: Open Drain NMOS
110: Open Drain PMOS
111: Reserved
PIN 20 Pull
Up/Down Resistor
Value Selection
<966:965> 00: Floating
01: 10 kΩ Resistor
10: 100 kΩ Resistor
11: 1 MΩ Resistor
PIN 20 Pull
Up/Down Resistor
Selection
<967> 0: Pull Down Resistor
1: Pull Up Resistor
PIN 20 Driver
Strength Selection <968> 0: 1X
1: 2X
000-0046722-105 Page 20 of 79
SLG46722
7.5 GPI IO Structure
7.5.1 GPI IO Structure (for Pin 2)
Figure 2. PIN 2 GPI IO Structure Diagram
PAD
Digital In
S0
S1
S2
S3
Floating
10 kΩ
90 kΩ
900 kΩ
Res_sel[1:0]
00: floating
01: 10 kΩ
10: 100 kΩ
11: 1 MΩ
wosmt_en
smt_en
lv_en Low Voltage
Input
Schmitt Trigger
Input
Non-Schmitt
Trigger Input
Input Mode [1:0]
00: Digital In without Schmitt Trigger, wosmt_en=1
01: Digital In with Schmitt Trigger, smt_en=1
10: Low Voltage Digital In mode, lv_en = 1
11: Reserved
000-0046722-105 Page 21 of 79
SLG46722
7.6 Register OE IO Structure
7.6.1 Register OE IO Structure (for Pins 3, 4, 5, 6, 7, 8, 9, 13, 14, 15, 16, 17, 18, 19, 20)
Figure 3. Register OE IO Structure Diagram
PAD
Digital In
S0
S1
S2
S3
Floating
S0
S1
pull_up_en
10 kΩ
90 kΩ
900 kΩ
Res_sel[1:0]
00: floating
01: 10 kΩ
10: 100 kΩ
11: 1 MΩ
wosmt_en
smt_en
lv_en Low V oltage
Input
Schmitt Trigger
Input
Non-Schmitt
Trigger Input
Mode [2:0]
000: Digital In without Schmitt Trigger, wosmt_en=1, OE = 0
001: Digital In with Schmitt Trigger, smt_en=1, OE = 0
010: Low Voltage Digital In mode, lv_en = 1, OE = 0
011: Reserved
100: push-pull mode, pp_en=1, OE = 1
101: NMOS open drain mode, odn_en=1, OE = 1
110: PMOS open drain mode, odp_en=1, OE = 1
111: Reserved
Digital Out
Digital Out
OE
odn_en
OE
odn_en
Digital Out
OE
2x_en
pp_en
2x_en
odp_en
Digital Out
OE
pp_en
2x_en
odp_en
000-0046722-105 Page 22 of 79
SLG46722
7.7 Register OE IO Structure with Super Driver
7.7.1 Register OE IO Structure with Super Driver (for Pins 10, 12)
Figure 4. Register OE IO with Super Driver Structure Diagram
PAD
Digital In
S0
S1
S2
S3
Floating
S0
S1
pull_up_en
10 kΩ
90 kΩ
900 kΩ
Res_sel[1:0]
00: floating
01: 10 kΩ
10: 100 kΩ
11: 1 MΩ
wosmt_en
smt_en
lv_en Low V oltage
Input
Schmitt Trigger
Input
Non-Schmitt
Trigger Input
Mode [2:0]
000: Digital In without Schmitt Trigger , wosmt_en=1
001: Digital In with Schmitt Trigger, smt_en=1
010: Low Voltage Digital In mode, lv_en = 1
011: Reserved
100: push-pull mode, pp_en=1
101: NMOS open drain mode, odn_en=1
110: PMOS open drain mode, odp_en=1
111: Reserved
Digital Out
Digital Out
OE
odn_en
OE
odn_en
Digital Out
OE
2x_en
pp_en
2x_en
odp_en
Digital Out
OE
pp_en
2x_en
odp_en
Digital Out
OE
odn_en
4x_en
000-0046722-105 Page 23 of 79
SLG46722
8.0 Connection Matrix
The Connection Matrix in the SLG46722 is used to create the internal routing for internal functions of the device once it is
programmed. The registers are programmed from the one-time NVM cell during Test Mode Operation. All of the connection point
for each logic cell withi n the SLG4 6722 has a specific dig ital bit code a ssigned to it that is either set to acti ve “High” or inactive
“Low” based on the design that is created. Once the 1024 register bits within the SLG46722 are programmed a fully custom circuit
will be created.
The Connection Matrix has 64 inputs and 95 outputs. Each of the 64 inputs to the Connection Matrix is hard-wired to a particular
source macrocell, including I/O pins, LUTs, other digital resources and VDD and VSS. The input to a digital macrocell uses a 6-bit
register to select one of these 64 input lines.
For a complete list of the SLG46722’s register table, see Section 18.0 Appendix A - SLG46722 Register Definition.
Figure 5. Connection Matrix
VSS 0
Pin 2 Digital In 1
Pin 3 Digital In 2
Pin 4 Digital In 3
Matrix Input Signal
Functions N
Resetb_core 62
VDD 63
N
Function
Registers
93
Input of Filter_1
reg<563:558>
0
PIN3 Digital Output
Source
reg<5:0>
1
PIN4 Digital Ou tpu t
Source
reg<11:6>
2
PIN5 Digital Output
Source
reg<17:12>
Matrix Inputs
Matrix Outputs
000-0046722-105 Page 24 of 79
SLG46722
8.1 Matrix Input Table
Table 19. Matrix Input Table
NMatrix Input Signal Function Matrix Decode
5 4 3 2 1 0
0 VSS 000000
1 pin2 digital Input 0 0 0 0 0 1
2 pin3 digital Input 0 0 0 0 1 0
3 pin4 digital Input 0 0 0 0 1 1
4 pin5 digital Input 0 0 0 1 0 0
5 pin6 digital Input 0 0 0 1 0 1
6 pin7 digital Input 0 0 0 1 1 0
7 pin8 digital Input 0 0 0 1 1 1
8 pin9 digital Input 0 0 1 0 0 0
9 pin10 digital Input 0 0 1 0 0 1
10 counter/delay_0 output 14 bit 0 0 1 0 1 0
11 counter/delay_1 output 14 bit w/ ext CK, reset 0 0 1 0 1 1
12 counter/delay_2 output 8 bit w/ ext CK, reset 001100
13 counter/delay_3 output 8 bit w/ ext CK, reset 001101
14 counter/delay_4 output 8 bit 0 0 1 1 1 0
15 counter/delay_5 output 8 bit 0 0 1 1 1 1
16 counter/delay_6 output 8 bit 0 1 0 0 0 0
17 counter/delay _7 output 14 bit 0 1 0 0 0 1
18 DFF/LATCH_0 Q output with resetb or setb 0 1 0 0 1 0
19 DFF/LATCH_0 nQ output with resetb or setb 0 1 0 0 1 1
20 DFF/LATCH_1 output with resetb or setb 0 1 0 1 0 0
21 DFF/LATCH_2 output with resetb or setb 0 1 0 1 0 1
22 DFF/LATCH_3 output with resetb or setb 0 1 0 1 1 0
23 DFF/LATCH_5 output 0 1 0 1 1 1
24 DFF/LATCH_6 output 0 1 1 0 0 0
25 LUT4_0 output 0 1 1 0 0 1
26 LUT3_0 output 0 1 1 0 1 0
27 LUT3_1 output 0 1 1 0 1 1
28 LUT3_2 output 0 1 1 1 0 0
29 LUT3_3 output 0 1 1 1 0 1
30 LUT3_4 output 0 1 1 1 1 0
31 LUT3_5 output 0 1 1 1 1 1
32 LUT3_6 output 1 0 0 0 0 0
33 LUT3_7 output 1 0 0 0 0 1
34 LUT3_8 output (1st stage pipe 1 delay output) 1 0 0 0 1 0
35 LUT3_9 output 1 0 0 0 1 1
36 LUT2_0 output (DFF/LATCH_4 output) 1 0 0 1 0 0
37 LUT2_1 output 1 0 0 1 0 1
000-0046722-105 Page 25 of 79
SLG46722
38 LUT2_2 output 1 0 0 1 1 0
39 LUT2_3 output 1 0 0 1 1 1
40 LUT2_4 output 1 0 1 0 0 0
41 LUT2_5 output 1 0 1 0 0 1
42 pipe1 delay output0 1 0 1 0 1 0
43 pipe1 delay output1 1 0 1 0 1 1
44 Edge detect output 1 0 1 1 0 0
45 Programmable delay with edge detector 1 0 1 1 0 1
46 internal oscillator output 1 0 1 1 1 0
47 intern al oscil la t or di vi d ed by 4 ou tput 1 0 1 1 1 1
48 internal oscillator divided by 8, 12, 24, 64 output 1 1 0 0 0 0
49 intern al oscil la t or di vi d ed by 3 ou tput 1 1 0 0 0 1
50 pin12 digital Input 1 1 0 0 1 0
51 pin13 digital Input 1 1 0 0 1 1
52 pin14 digital Input 1 1 0 1 0 0
53 pin15 digital Input 1 1 0 1 0 1
54 pin16 digital Input 1 1 0 1 1 0
55 pin17 digital Input 1 1 0 1 1 1
56 pin18 digital Input 1 1 1 0 0 0
57 pin19 digital Input 1 1 1 0 0 1
58 pin20 digital Input 1 1 1 0 1 0
59 filter_0 output 1 1 1 0 1 1
60 matrix input<48> divide by 3 1 1 1 1 0 0
61 filter_1 output 1 1 1 1 0 1
62 Reset_core as matrix input 1 1 1 1 1 0
63 VDD 111111
Table 19. Matrix Input Table
NMatrix Input Signal Function Matrix Decode
5 4 3 2 1 0
000-0046722-105 Page 26 of 79
SLG46722
8.2 Matrix Output Table
Table 20. Matrix Output Tab le
Register Bit
Address Matrix Output Signal Function Matrix Output
Number
reg<5:0> Matrix Out: PIN3 Digital Output Source 0
reg<11:6> Matrix Out: PIN4 Digital Output Source 1
reg<17:12> Matrix Out: PIN5 Digital Output Source 2
reg<23:18> Matrix Out: PIN6 Digital Output Source 3
reg<29:24> Matrix Out: PIN7 Digital Output Source 4
reg<35:30> Matrix Out: PIN8 Digital Output Source 5
reg<41:36> Matrix Out: PIN9 Digital Output Source 6
reg<47:42> Matrix Out: PIN10 Digital Output Source (Super Drive) 7
reg<53:48> Matrix Out: Input for delay0 or Counter0 external clock 8
reg<59:54> Matrix Out: Input for delay1 or counter1 reset input 9
reg<65:60> Matrix Out: Input for Counter1 external clock or delay1 external clock 10
reg<71:66> Matrix Out: Input for delay2 or counter2 reset input 11
reg<77:72> Matrix Out: Input for Counter2 external clock or delay2 external clock 12
reg<83:78> Matrix Out: Input for delay3 or counter3 reset input 13
reg<89:84> Matrix Out: Input for Counter3 external clock or delay3 external clock 14
reg<95:90> Matrix Out: Input for delay4 or Counter4 external clock 15
reg<101:96> Matrix Out: Input for delay5 or Counter5 external clock 16
reg<107:102> Matrix Out: Input for delay6 or Counter6 external clock 17
reg<113:108> Matri x Out: Input for delay7 or Counter7 external clock 18
reg<119:114> Matrix Out: Clock Input of DFF0 19
reg<125:120> Matrix Out: Data Input of DFF0 20
reg<131:126> Matrix Out: Resetb (Setb) of DFF0 21
reg<137:132> Matri x Out: Clock Input of DFF1 22
reg<143:138> Matrix Out: Data Input of DFF1 23
reg<149:144> Matrix Out: Resetb (Setb) of DFF1 24
reg<155:150> Matri x Out: Clock Input of DFF2 25
reg<161:156> Matrix Out: Data Input of DFF2 26
reg<167:162> Matrix Out: Resetb (Setb) of DFF2 27
reg<173:168> Matri x Out: Clock Input of DFF3 28
reg<179:174> Matrix Out: Data Input of DFF3 29
reg<185:180> Matrix Out: Resetb (Setb) of DFF3 30
reg<191:186> Matri x Out: Clock Input of DFF5 31
reg<197:192> Matrix Out: Data Input of DFF5 32
reg<203:198> Matri x Out: Clock Input of DFF6 33
reg<209:204> Matrix Out: Data Input of DFF6 34
reg<215:210> Matri x Out: In0 of LUT4_0 35
reg<221:216> Matri x Out: In1 of LUT4_0 36
reg<227:222> Matri x Out: In2 of LUT4_0 37
000-0046722-105 Page 27 of 79
SLG46722
reg<233:228> Matri x Out: In3 of LUT4_0 38
reg<239:234> Matri x Out: In0 of LUT3_0 39
reg<245:240> Matri x Out: In1 of LUT3_0 40
reg<251:246> Matri x Out: In2 of LUT3_0 41
reg<257:252> Matri x Out: In0 of LUT3_1 42
reg<263:258> Matri x Out: In1 of LUT3_1 43
reg<269:264> Matri x Out: In2 of LUT3_1 44
reg<275:270> Matri x Out: In0 of LUT3_2 45
reg<281:276> Matri x Out: In1 of LUT3_2 46
reg<287:282> Matri x Out: In2 of LUT3_2 47
reg<293:288> Matri x Out: In0 of LUT3_3 48
reg<299:294> Matri x Out: In1 of LUT3_3 49
reg<305:300> Matri x Out: In2 of LUT3_3 50
reg<311:306> Matrix Out: In0 of LUT3_4 51
reg<317:312> Matri x Out: In1 of LUT3_4 52
reg<323:318> Matri x Out: In2 of LUT3_4 53
reg<329:324> Matri x Out: In0 of LUT3_5 54
reg<335:330> Matri x Out: In1 of LUT3_5 55
reg<341:336> Matri x Out: In2 of LUT3_5 56
reg<347:342> Matri x Out: In0 of LUT3_6 57
reg<353:348> Matri x Out: In1 of LUT3_6 58
reg<359:354> Matri x Out: In2 of LUT3_6 59
reg<365:360> Matri x Out: In0 of LUT3_7 60
reg<371:366> Matri x Out: In1 of LUT3_7 61
reg<377:372> Matri x Out: In2 of LUT3_7 62
reg<383:378> Matrix Out: In0 of LUT3 _8 or Input of Pipe delay 63
reg<389:384> Matrix Out: In1 of LUT3 _8 or Resetb of Pipe delay 64
reg<395:390> Matrix Out: In2 of LUT3_8 or Clock of Pipe delay 65
reg<401:396> Matri x Out: In0 of LUT3_9 66
reg<407:402> Matri x Out: In1 of LUT3_9 67
reg<413:408> Matri x Out: In2 of LUT3_9 68
reg<419:414> Matrix Out: In0 of LUT2 _0 or Clock Input of DFF4 69
reg<425:420> Matrix Out: In1 of LUT2 _0 or Data Input of DFF4 70
reg<431:426> Matri x Out: In0 of LUT2_1 71
reg<437:432> Matri x Out: In1 of LUT2_1 72
reg<443:438> Matri x Out: In0 of LUT2_2 73
reg<449:444> Matri x Out: In1 of LUT2_2 74
reg<455:450> Matri x Out: In0 of LUT2_3 75
reg<461:456> Matri x Out: In1 of LUT2_3 76
Table 20. Matrix Output Tab le
Register Bit
Address Matrix Output Signal Function Matrix Output
Number
000-0046722-105 Page 28 of 79
SLG46722
reg<467:462> Matri x Out: In0 of LUT2_4 77
reg<473:468> Matri x Out: In1 of LUT2_4 78
reg<439:474> Matri x Out: In0 of LUT2_5 79
reg<485:480> Matri x Out: In1 of LUT2_5 80
reg<491:486> Matrix Out: Input for programmabl e delay & edge detector 81
reg<497:492> Matrix Out: Power down for osc 82
reg<503:498> Matri x Out: Pin12 Digital Output Source (Super Drive) 83
reg<509:504> Matrix Out: Pin13 Digital Output Source 84
reg<515:510> Matrix Out: Pin14 Digital Output Source 85
reg<521:516> Matrix Out: Pin15 Digital Output Source 86
reg<527:522> Matrix Out: Pin16 Digital Output Source 87
reg<533:528> Matrix Out: Pin17 Digital Output Source 88
reg<539:534> Matrix Out: Pin18 Digital Output Source 89
reg<545:540> Matrix Out: Pin19 Digital Output Source 90
reg<551:546> Matrix Out: Pin20 Digital Output Source 91
reg<557:552> Matrix Out: Input of filter_0 92
reg<563:558> Matrix Out: Input of filter_1 93
reg<569:564> Reserved 94
Table 20. Matrix Output Tab le
Register Bit
Address Matrix Output Signal Function Matrix Output
Number
000-0046722-105 Page 29 of 79
SLG46722
9.0 Combinatorial Logic
Combinatorial logic is supported via fifteen Lookup Tables (LUTs) within the SLG46722. There are five 2-bit LUTs, nine 3-bit LUTs,
and one 4-bit LUT. The device also includes two Combi nation Functio n Macrocells that can be used as LUTs. For more details,
please see Section 10.0 Combination Function Macro Cells.
Inputs/Outputs for the fifteen LUTs are configured from the conn ection matrix with specific logic functi ons being defined by the
state of NVM bits. The outputs of the LUTs can be configured to any user defined function, including the following standard digital
logic devices (AND, NAND, OR, NOR, XOR, XNOR).
9.1 2-Bit LUT
The five 2-bit LUTs each take in two input signals from the connection matrix and produce a single output, which goes back into
the connection matrix.
Figure 6. 2-bit LUTs
2-bit LUT1 OUT
IN1
IN0
reg <579:576>
From Connection
Matrix Output <71>
From Connection
Matrix Output <72>
To Connection
Matrix Input <37> 2-bit LUT2 OUT
IN1
IN0
reg <583:580>
From Connection
Matrix Output <73>
From Connection
Matrix Output <74>
To Connection
Matrix Input <38>
2-bit LUT3 OUT
IN1
IN0
reg <587 :584>
From Connection
Matrix Output <75>
From Connection
Matrix Output <76>
To Connection
Matrix Input <39> 2-bit LUT4 OUT
IN1
IN0
reg <591:588>
From Connection
Matrix Output <77>
From Connection
Matrix Output <78>
To Connection
Matrix Input <40>
2-bit LUT5 OUT
IN1
IN0
reg <595:592>
From Connection
Matrix Output <79>
From Connection
Matrix Output <80>
To Connection
Matrix Input <41 >
000-0046722-105 Page 30 of 79
SLG46722
Each 2-bit LUT uses a 4-bit register signal to define their outpu t functions;
2-Bit LUT1 is defined by reg<579:576>
2-Bit LUT2 is defined by reg<583:580>
2-Bit LUT3 is defined by reg<587:584>
2-Bit LUT4 is defined by reg<591:588>
2-Bit LUT5 is defined by reg<595:592
The table below shows the register bits for the standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR) that can be
created within each of the four 2-bit LUT lo gic cells.
Ta b le 26. 2-bit LUT S tandard Digital Functions .
Function MSB LSB
AND-2 1000
NAND-2 0 1 1 1
OR-2 1110
NOR-2 0 0 0 1
XOR-2 0110
XNOR-2 1001
Table 21. 2-bit LUT1 Truth Table.
IN1 IN0 OUT
0 0 reg <576>
0 1 reg <577>
1 0 reg <578>
1 1 reg <579>
Table 22. 2-bit LUT2 Truth Table.
IN1 IN0 OUT
0 0 reg <580>
0 1 reg <581>
1 0 reg <582>
1 1 reg <583>
Table 23. 2-bit LUT3 Truth Table.
IN1 IN0 OUT
0 0 reg <584>
0 1 reg <585>
1 0 reg <586>
1 1 reg <587>
Table 24. 2-bit LUT4 Truth Table.
IN1 IN0 OUT
0 0 reg <588>
0 1 reg <589>
1 0 reg <590>
1 1 reg <591>
Table 25. 2-bit LUT5 Truth Table.
IN1 IN0 OUT
0 0 reg <592>
0 1 reg <593>
1 0 reg <594>
1 1 reg <595>
000-0046722-105 Page 31 of 79
SLG46722
9.2 3-Bit LUT
The nine 3-bit LUTs each take in three input signals from the connection matrix and produce a single output, which goes back
into the connection matrix.
Figure 7. 3-bit LUTs
3-bit LUT0 OUT
IN1
IN0
reg <604:597>
From Connection
Matrix Output <39>
From Connecti on
Matrix Output <40> To Connection
Matrix Input <26> 3-bit LUT1 OUT
IN1
IN0
reg <612:605>
From Connection
Matrix Output <42>
From Connection
Matrix Output <43> To Connection
Matrix Input <27>
IN2
From Connection
Matrix Output <41> IN2
From Connection
Matrix Output <44>
3-bit LUT2 OUT
IN1
IN0
reg <620:613>
From Connection
Matrix Output <45>
From Connecti on
Matrix Output <46> To Connection
Matrix Input <28> 3-bit LUT3 OUT
IN1
IN0
reg <628:621>
From Connection
Matrix Output <48>
From Connection
Matrix Output <49> To Connection
Matrix Input <29>
IN2
From Connection
Matrix Output <47> IN2
From Connection
Matrix Output <50>
3-bit LUT4 OUT
IN1
IN0
reg <636:629>
From Connection
Matrix Output <51>
From Connecti on
Matrix Output <52> To Connection
Matrix Input <30> 3-bit LUT5 OUT
IN1
IN0
reg <644:637>
From Connection
Matrix Output <54>
From Connection
Matrix Output <55> To Connection
Matrix Input <31>
IN2
From Connection
Matrix Output <53> IN2
From Connection
Matrix Output <56>
3-bit LUT9 OUT
IN1
IN0
reg <676:669>
From Connection
Matrix Output <66>
From Connecti on
Matrix Output <67> To Connection
Matrix Input<35>
IN2
From Connection
Matrix Output <68>
3-bit LUT6 OUT
IN1
IN0
reg <652:645>
From Connection
Matrix Output <57>
From Connecti on
Matrix Output <58> To Connection
Matrix Input <32> 3-bit LUT7 OUT
IN1
IN0
reg <660:653>
From Connection
Matrix Output <60>
From Connection
Matrix Output <61> To Connection
Matrix Input <33>
IN2
From Connection
MatrixOutput <59> IN2
From Connection
Matrix Output <62>
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SLG46722
Table 27. 3-bit LUT0 Truth Table.
IN2 IN1 IN0 OUT
0 0 0 reg <597>
0 0 1 reg <598>
0 1 0 reg <599>
0 1 1 reg <600>
1 0 0 reg <601>
1 0 1 reg <602>
1 1 0 reg <603>
1 1 1 reg <604>
Table 28. 3-bit LUT1 Truth Table.
IN2 IN1 IN0 OUT
0 0 0 reg <605>
0 0 1 reg <606>
0 1 0 reg <607>
0 1 1 reg <608>
1 0 0 reg <609>
1 0 1 reg <610>
110 reg <611>
1 1 1 reg <612>
Table 29. 3-bit LUT2 Truth Table.
IN2 IN1 IN0 OUT
0 0 0 reg <613>
0 0 1 reg <614>
0 1 0 reg <615>
0 1 1 reg <616>
1 0 0 reg <617>
1 0 1 reg <618>
1 1 0 reg <619>
1 1 1 reg <620>
Table 30. 3-bit LUT3 Truth Table.
IN2 IN1 IN0 OUT
0 0 0 reg <621>
0 0 1 reg <622>
0 1 0 reg <623>
0 1 1 reg <624>
1 0 0 reg <625>
1 0 1 reg <626>
1 1 0 reg <627>
1 1 1 reg <628>
Table 31. 3-bit L UT4 Truth Tab le.
IN2 IN1 IN0 OUT
0 0 0 reg <629>
0 0 1 reg <630>
0 1 0 reg <631>
0 1 1 reg <632>
1 0 0 reg <633>
1 0 1 reg <634>
1 1 0 reg <635>
1 1 1 reg <636>
Table 32. 3-bit L UT5 Truth Tab le.
IN2 IN1 IN0 OUT
0 0 0 reg <637>
0 0 1 reg <638>
0 1 0 reg <639>
0 1 1 reg <640>
1 0 0 reg <641>
1 0 1 reg <642>
1 1 0 reg <643>
1 1 1 reg <644>
Table 33. 3-bit L UT6 Truth Tab le.
IN2 IN1 IN0 OUT
0 0 0 reg <645>
0 0 1 reg <646>
0 1 0 reg <647>
0 1 1 reg <648>
1 0 0 reg <649>
1 0 1 reg <650>
1 1 0 reg <651>
1 1 1 reg <652>
Table 34. 3-bit L UT7 Truth Tab le.
IN2 IN1 IN0 OUT
0 0 0 reg <653>
0 0 1 reg <654>
0 1 0 reg <655>
0 1 1 reg <656>
1 0 0 reg <657>
1 0 1 reg <658>
1 1 0 reg <659>
1 1 1 reg <660>
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SLG46722
Each 3-bit LUT uses a 8-bit register signal to define their outpu t functions;
3-Bit LUT1 is defined by reg<604:597>
3-Bit LUT2 is defined by reg<612:605>
3-Bit LUT3 is defined by reg<620:613>
3-Bit LUT4 is defined by reg<628:621>
3-Bit LUT5 is defined by reg<636:629>
3-Bit LUT6 is defined by reg<644:637>
3-Bit LUT7 is defined by reg<652:645>
3-Bit LUT8 is defined by reg<660:653>
3-Bit LUT9 is defined by reg<676:669>
The table below shows the register bits for the standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR) that can be
created within each of the six3-bit LUT logic cells.
Ta b le 36. 3-bit LUT S tandard Digital Functions .
Function MSB LSB
AND-3 10000000
NAND-3 01111111
OR-3 11111110
NOR-3 00000001
XOR-3 10010110
XNOR-3 01101001
Table 35. 3-bit LUT9 Truth Table.
IN2 IN1 IN0 OUT
0 0 0 reg <669>
0 0 1 reg <670>
0 1 0 reg <671>
0 1 1 reg <672>
1 0 0 reg <673>
1 0 1 reg <674>
1 1 0 reg <675>
1 1 1 reg <676>
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SLG46722
9.3 4-Bit LUT
The one 4-bit LUT takes in four input signals from the connection matrix and produces a single output, which goes back into the
connection matrix.
The 4-bit LUT uses a 16-bit register signal to define the output function;
4-Bit LUT0 is defined by reg<692:677>
The table below shows the register bits for the standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR) that can be
created within the 4-bit LUT logic cell.
Figure 8. 2-bit LUTs
Table 37. 4-bit LUT0 Truth Table.
IN3 IN2 IN1 IN0 OUT
0 0 0 0 reg <677>
0 0 0 1 reg <678>
0 0 1 0 reg <679>
0 0 1 1 reg <680>
0 1 0 0 reg <681>
0 1 0 1 reg <682>
0 1 1 0 reg <683>
0 1 1 1 reg <684>
1 0 0 0 reg <685>
1 0 0 1 reg <686>
1 0 1 0 reg <687>
1 0 1 1 reg <688>
1 1 0 0 reg <689>
1 1 0 1 reg <690>
1 1 1 0 reg <691>
1 1 1 1 reg <692>
Ta b le 38. 4-bit LUT S tandard Digital Functions .
Function MSB LSB
AND-4 1000000000000000
NAND-40111111111111111
OR-4 1111111111111110
NOR-4 0000000000000001
XOR-4 0110100111001110
XNOR-41001011000110001
4-bit LUT9 OUT
IN1
IN0
reg <692:677>
From Connection
Matrix Output <35>
From Connection
Matrix Output <36> To Connection
Matrix Input <25>
IN2
From Connection
Matrix Output <37>
IN3
From Connection
Matrix Output <38>
000-0046722-105 Page 35 of 79
SLG46722
10.0 Combination Function Macro Cells
The SLG46722 has two combination function macrocells that can serve more than one logic or timing function. In each case, they
can serve as a Look Up Table (LUT), or as another logic or timing function. See the list below for the functions that can be
implemented in these macrocells;
• One macrocell that can serve as either 2-bit LUT or as D Flip Flop
• One macrocell that can serve as either 3-bit LUT or as Pipe Delay
Inputs/Outputs for the two combination function macrocells are configured from the connection matrix with specific logic functions
being defined by the state of NVM bits. When used as a LUT to implement combinatorial logic functions, the outputs of the LUTs
can be configured to any user defined function, including the following standard digital logic devices (AND, NAND, OR, NOR,
XOR, XNOR).
10.1 2-Bit LUT or D Flip Flop Macrocells
There is one macrocell that can serve as either a 2-bit LUT or as a D Flip Flop. When used to implement LUT function, the 2-bit
LUT takes in two input signals from the connection matrix and produce a single output, which goes back into the connection
matrix. When used to implement D Fli p Flop function, the two input sig nals from the connection matrix go to the data (d) and
clock (clk) inputs for the Flip Flop, with the output going back to the connection matrix.
10.1.1 2-Bit LUT or D Flip Flop Macrocells Used as 2-Bit LUTs
Figure 9. 2-bit LUT0 or DFF4
DFF4
clk
D
2-bit LUT0 OUT
IN0
IN1
To Connection
Matrix Input <36>
4-bits NVM
From Connection Matrix Out put <70>
1-bit NVM
reg <575:572>
reg <596>
From Connection Mat rix Output <69> Q/nQ
reg <573> Output Select (Q or nQ)
Table 39. 2-bit LUT0 Truth Table.
IN1 IN0 OUT
0 0 reg <572>
0 1 reg <573>
1 0 reg <574>
1 1 reg <575>
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SLG46722
Each Macrocell, when programmed for a LUT function, uses a 4-bit register to define their output function:
2-Bit LUT0 is defined by reg<575:572>
10.1.2 2-Bit LUT or D Flip Flop Macrocells Used as D Flip Flop Register Settings
10.2 3-Bit LUT or Pipe Delay Macrocell
There is one macrocell that can serve as either a 3-bit LUT or as a Pipe Delay.
When used to implement LUT functions, the 3-bit LUT take in three input signals from the connection matrix and produces a single
output, which goes back into the connection matrix.
When used as a pipe delay, there are three inputs signals from the matrix, Input (IN), Clock (CLK) and Reset (RST). The pipe
delay cell is built from 16 D Flip-Flop logic ce lls that provi de the three dela y options, two of which are user sele ctable. The DFF
cells are tied in series where the output (Q) of each delay cell goes to the next DFF cell. The first delay option (OUT2) is fixed at
the output of the first flip-flop stage. The other tw o outputs (OUT 0 and OUT1) pro vide user sel ectable options for 1 – 16 stages
of delay. There are delay output points for each set of the OUT0 and OUT1 outputs to a 4-input mux that is controlled by reg
<664:661> for OUT0 and reg <668:665> for OUT1. The 4-input mux is used to control the selection of the amount of delay.
The overall time of the delay is based on the clock used in the SLG46722 design. Each DFF cell has a time delay of the inverse
of the clock time (either external clock or the RC Oscillator within the SLG46722). The sum of the number of DFF cells used will
be the total time delay of the Pipe Delay logic cell.
Table 40. DFF4 Register Settings
Signal Function Register Bit
Address Register Definition
LUT2_0 or DFF4
Select 596 0: LUT2_0
1: DFF4
DFF4 or Latch
Select 572 0: DFF function
1: Latch function
DFF4 Output Select 573 0: Q output
1: nQ output
DFF4 Initial Polarity
Select 574 0: Low
1: High
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SLG46722
Figure 10. 3-bit LUT8 or Pipe Delay
3-bit LUT8 OUT
IN1
IN0
reg <668 :661>
From Connection
Matrix Output <63>
From Connection
Matrix Output <64>
IN2
From Connection
Matrix Output <65>
16 Flip flop Block
IN
RST
CLK
From Connection
Matrix Output <64>
From Connection
Matrix Output <63>
From Connection
Matrix Output <65>
reg <668:665>
reg <664:661>
To Connection
Matrix Input <43>
To Connection
Matrix Input <42>
To Connection
Matrix Input <34>
OUT1
OUT0
OUT2
reg <978>
0
1
reg <977>
0
1
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SLG46722
10.2.1 3-Bit LUT or Pipe Delay Macrocells Used as 3-Bit LUTs
Each Macrocell, when programmed for a LUT function, uses a 8-bit register to define their output function:
3-Bit LUT8 is defined by reg<668:661>
10.2.2 3-Bit LUT or Pipe Dela y Macrocells Used as Pipe Delay Regi ster Settings
Table 42. Pipe Delay Register Settings
Signal Function Register Bit
Address Register Definition
LUT3_8 or Pipe
Delay Output Select reg<977> 0: LUT3_8
1: 1 Pipe Delay Output
OUT0 select reg<664:661>
OUT1 select reg<668:665>
Pipe delay OUT1
Polarity Select Bit reg<978> 0: Non-inverted
1: Inverted
Table 41. 3-bit LUT8 Truth Table.
IN2 IN1 IN0 OUT
0 0 0 reg <661>
0 0 1 reg <662>
0 1 0 reg <663>
0 1 1 reg <664>
1 0 0 reg <665>
1 0 1 reg <666>
1 1 0 reg <667>
1 1 1 reg <668>
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SLG46722
11.0 Digital Storage Elements (DFFs/Latches)
There are six D Flip Flop / Latches (DFF/Latch logic cells within the SLG46722 available for design. The source and destination
of the inputs and outputs for the DFF/Latches are configured from the connection matrix. All DFF/Latch macrocells have user
selection for initial state. DFF0 has the option to connect bot h the Q and Q Bar outputs to the connection matrix, DFF1, DFF2,
DFF3, DFF5 and DFF6 can only connect the Q output to the matrix. The macrocells DFF0, DFF1, DFF2 and DFF3 have an
additional input from the matrix that can serve as a nSet or nReset function to the ma crocell.
Note that one of the Combinati on Function Macroc ells (LUT 2_0 / DFF4) can a lso operate as a DFF or a 2-bit LUT p lease see
Section 10.1 2-Bit LUT or D Flip Flop Macrocells for the description of this Comb ination Function macrocell.
The operation of the D Flip-Flo p and Latch will follow the functional descrip tions below:
DFF: CLK is rising edge triggere d, then Q = D; otherwise Q will not change
Latch: if CLK = 0, then Q = D
if CLK = 1, then Q will not change
Figure 11. DFF/Latch0
DFF/Latch0
D
reg <693>
From Connection Matrix Output <20>
To Connection Matrix Input <19>
CK
From Connection Matrix Output <19>
Q
Q
To Connection Matrix Input <18>
nRSTZ nSETZ
0
1
From Connection Matrix Output <21>
0
1
reg <694>
reg <695>
Initial Polarity Select
DFF or Latch Select
000-0046722-105 Page 40 of 79
SLG46722
Figure 12. DFF/Latch1
Figure 13. DFF/Latch2
DFF/Latch1
D
reg <696>
From Connection Matrix Output <23>
CK
From Connection Matrix Output <22>
QTo Connection Matrix Input <20>
nRSTZ nSETZ
0
1
From Connection Matrix Output <24>
0
1
reg <698>
reg <699>
Initial Polarity Select
DFF or Latch Select
reg <697>
Output Select (Q or nQ)
DFF/Latch2
D
reg <700>
From Connection Matrix Output <26>
CK
From Connection Matrix Output <25>
QTo Connection Matrix Input <21>
nRSTZ nSETZ
0
1
From Connection Matrix Output <27>
0
1
reg <702>
reg <703>
Initial Polarity Select
DFF or Latch Select
reg <701>
Output Select (Q or nQ)
000-0046722-105 Page 41 of 79
SLG46722
Figure 14. DFF/Latch3
Figure 15. DFF/Latch5
Figure 16. DFF/Latch6
DFF/Latch3
D
reg <709>
From Connection Matrix Output <29>
CK
From Connection Matrix Outp ut <28>
Q/nQ To Connection Matrix Input <22>
nRSTZ nSETZ
0
1
From Connection Matrix Output <30>
0
1
reg <706>
reg <707>
Initial Polarity Select
DFF or Latch Select
reg <705>
Output Select (Q or nQ)
DFF/Latch5
D
reg <708>
From Connection Matrix Output <32>
CK
From Connection Matrix Output <31>
Q/nQ To Connection Matrix Input <23>
reg <710>
Initial Polarity Select
DFF or Latch Select
reg <709>
Output Sele ct (Q or nQ )
DFF/Latch6
D
reg <711>
From Connection Matrix Output <34>
CK
From Connection Matrix Output <33>
Q/nQ To Connection Matrix Input <24>
reg <713>
Initial Polarity Select
DFF or Latch Select
reg <712>
Output Select Q or nQ
000-0046722-105 Page 42 of 79
SLG46722
11.1 Initial Polarity Operations
Figure 17. DFF Polarity Operations
VDD
Data
Clock
POR
nReset (Case 1)
Q with nReset (Case 1)
nReset (Case 2)
Q with nReset (Case 2)
Initial Polarity: High
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SLG46722
12.0 Counters/Delay Generators (CNT/DLY)
There are eight configurable counters/delay generators in the SLG46722. Two of these counters/delay generators are 14-bit
(CNT/DLY 0 and 1), and six of the counters/delay generators are 8-bi t (CNT/DLY 2, 3, 4, 5, 6, 7). For flexibi lity, each of these
macrocells has a large selection of internal and external clock sources, as well as the option to chain from the output of the
previous (N-1) CNT/DLY macrocell, to implement longer count / delay circuits.
Three of the counter/delay generator macrocells (CNT/DLY, 1,2,3) have two inputs from the connection matrix, one for Delay
Input/Reset Input (Delay_In/Reset_In), and one for an external counter/clock source. Five of the counter/delay generator macro-
cells (CNT/DLY 0, 4, 5, 6, 7) have one input from the connection matrix, whi ch has a shared function of e ither a Delay Input or
an external clock input.
Figure 18. CNT/DLY0
CNT/DLY0
Counter_end
clk
To Connection Matrix Input <10>
From Connection
Matrix Output <8>
Count_end_out_x-1
reg <714>
0
1
2
3
4
5
6
7
ext. clock
RC Osc/64
RC Osc/24
RC Osc/12
RC Osc/4
RC Osc
Counter Control Data
reg <731:718>
reg <717:715>
0
1
0
1
Delay_out
Delay_IN/CNT_ext_clk
Delay_IN
CNT clock
Edge Detector
000-0046722-105 Page 44 of 79
SLG46722
Figure 19. CNT/DLY1
Figure 20. CNT/DLY2
CNT/DLY1
Counter_end
clk
To Connection Matrix Input <11>
From Connection
Matrix Output <9>
Count_end_out_x-1
reg <734>
0
1
2
3
4
5
6
7
ext. clock from CM Out <10>
RC Osc/64
RC Osc/24
RC Osc/12
RC Osc/4
RC Osc
Counter Control Data
reg <751:738>
reg <737:735>
0
1
0
1
Delay_out
Delay_IN
Reset_IN
Edge Detector
CNT/DLY2
Counter_end
clk
To Connection Matrix Input <12>
From Connection
Matrix Output <11>
Count_end_out_x-1
reg <754>
0
1
2
3
4
5
6
7
ext. clock from CM Out <12>
RC Osc/64
RC Osc/24
RC Osc/12
RC Osc/4
RC Osc
Counter Control Data
reg <765:758>
reg <757:755>
0
1
0
1
Delay_out
Delay_IN
Reset_IN
Edge Detector
000-0046722-105 Page 45 of 79
SLG46722
Figure 21. CNT/DLY3
Figure 22. CNT/DLY4
CNT/DLY3
Counter_end
clk
To Connection Matrix Input <13>
From Connection
Matrix Output <13>
Count_end_out_x-1
reg <768>
0
1
2
3
4
5
6
7
ext. clock from CM Out <14>
RC Osc/64
RC Osc/24
RC Osc/12
RC Osc/4
RC Osc
Counter Control Data
reg <779:772>
reg <771:769>
0
1
0
1
Delay_out
Delay_IN
Reset_IN
Edge Detector
CNT/DLY4
Counter_end
clk
To Connection Matrix Input <14>
From Connection
Matrix Output <15>
Count_end_out_x-1
reg <782>
0
1
2
3
4
5
6
7
ext. clock
RC Osc/64
RC Osc/24
RC Osc/12
RC Osc/4
RC Osc
Counter Control Data
reg <793:786>
reg <785:783>
0
1
0
1
Delay_out
Delay_IN/CNT_ext_clk
Delay_IN
CNT clock
Edge Detector
000-0046722-105 Page 46 of 79
SLG46722
Figure 23. CNT/DLY5
Figure 24. CNT/DLY6
CNT/DLY5
Counter_end
clk
To Connection Matrix Input <15>
From Connection
Matrix Output <16>
Count_end_out_x-1
reg <796>
0
1
2
3
4
5
6
7
ext. clock
RC Osc/64
RC Osc/24
RC Osc/12
RC Osc/4
RC Osc
Counter Control Data
reg <807:800>
reg <799:797>
0
1
0
1
Delay_out
Delay_IN/CNT_ext_clk
Delay_IN
CNT clock
Edge Detector
CNT/DLY6
Counter_end
clk
To Connection Matrix Input <16>
From Connection
Matrix Output <17>
Count_end_out_x-1
reg <810>
0
1
2
3
4
5
6
7
ext. clock
RC Osc/64
RC Osc/24
RC Osc/12
RC Osc/4
RC Osc
Counter Control Data
reg <821:814>
reg <813:811>
0
1
0
1
Delay_out
Delay_IN/CNT_ext_clk
Delay_IN
CNT clock
Edge Detector
000-0046722-105 Page 47 of 79
SLG46722
Figure 25. CNT/DLY7
CNT/DLY7
Counter_end
clk
To Connection Matrix Input <17>
From Connection
Matrix Output <18>
Count_end_out_x-1
reg <824>
0
1
2
3
4
5
6
7
ext. clock
RC Osc/64
RC Osc/24
RC Osc/12
RC Osc/4
RC Osc
Counter Control Data
reg <841:828>
reg <827:825>
0
1
0
1
Delay_out
Delay_IN/CNT_ext_clk
Delay_IN
CNT clock
Edge Detector
000-0046722-105 Page 48 of 79
SLG46722
12.1 CNT/DLY T iming Diagrams
Figure 26. Delay Mode Timing
Figure 27. Counter Mode Timing
delay_in
RC osc: force power on
(always running)
Delay output
Asynchronous delay variable Asynchronous delay variable
delay = period x (counter data + 2) + variable
variable is from 0 to 1 clock period delay = period x (counter data + 2) + variable
variable is from 0 to 1 clock period
Delay mode (edge select: both, counter data:3)
delay_in
RC osc: auto power on
(powers up from delay in)
Delay output
offset offset
delay = offset + period x (counter data + 2)
offset = approx. 4-22 μs at room temp. delay = offs et + period x (counter data + 2)
offset = approx. 4-22 μs at room temp.
delay_in
CLK
Counter output
Count start in 2 clk after reset
4 clk period pulse
Count mode (count data:3), Counter reset (rising edge detect reset by delay_in input)
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SLG46722
12.2 CNT/DLY0 Register Settings
12.3 CNT/DLY1 Register Settings
12.4 CNT/DLY2 Register Settings
Table 43. CNT/DLY0 Register Settings
Signal Function Register Bit
Address Register Definition
Counter/Delay0
Mode Select reg<714> 0: Delay Mode
1: Counter Mode
Counter/Delay0
Clock Source Select
(external clock is
only for counter
mode)
reg<717:715> 000: Internal OSC Clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
101: External Clock
110: External Clock/8
111: Counter 7 Overflow
Counter0 Control
Data/Delay0 Time
Control
reg<731:718> 1-16384 : (delay time = (counter control data +2) /freq)
Delay0 Mode Select reg<733:732> 00: Delay on both falling and rising edges
01: Delay on falling edge only
10: Delay on rising edge only
11: No delay on either falling or rising edges
Table 44. CNT/DLY1 Register Settings
Signal Function Register Bit
Address Register Definition
Counter/Delay1
Mode Select reg<734> 0: Delay Mode
1: Counter Mode
Counter/Delay1
Clock Source select reg<737:735> 000: Internal OSC Clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
101: External Clock
110: External Clock/8
111: Counter 0 Overflow
Counter1 Control
Data/Delay1 Time
Control
reg<751:738> 1-16384 : (delay time = (counter control data +2) /freq)
Delay1 Mode Select
or asynchronous
counter reset
reg<753:752> 00: Del ay on both fa lling and rising edges (for delay & counter reset)
01: Delay on falling edge only (fo r delay & counter reset)
10: Delay on rising edge only (for delay & counter reset)
11: No delay on either falling or rising edges / high level reset for counter mode
Table 45. CNT/DLY1 Register Settings
Signal Function Register Bit
Address Register Definition
Counter/Delay1
Mode Select reg<754> 0: Delay Mode
1: Counter Mode
000-0046722-105 Page 50 of 79
SLG46722
Counter/Delay1
Clock Source select reg<757:755> 000: Internal OSC Clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
101: External Clock
110: External Clock/8
111: Counter 1 Overflow
Counter1 Control
Data/Delay1 Time
Control
reg<765:758> 1-256: (delay time = (counter control da ta +2) /freq)
Delay1 Mode Select
or asynchronous
counter reset
reg<767:766> 00: Del ay on both fa lling and rising edges (for delay & counter reset)
01: Delay on falling edge only (fo r delay & counter reset)
10: Delay on rising edge only (for delay & counter reset)
11: No delay on either falling or rising edges / high level reset for counter mode
Table 45. CNT/DLY1 Register Settings
Signal Function Register Bit
Address Register Definition
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SLG46722
12.5 CNT/DLY3 Register Settings
12.6 CNT/DLY4 Register Settings
Table 46. CNT/DLY1 Register Settings
Signal Function Register Bit
Address Register Definition
Counter/Delay1
Mode Select reg<768> 0: Delay Mode
1: Counter Mode
Counter/Delay1
Clock Source select reg<771:769> 000: Internal OSC Clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
101: External Clock
110: External Clock/8
111: Counter 0 Overflow
Counter1 Control
Data/Delay1 Time
Control
reg<779:772> 1-256: (delay time = (counter control da ta +2) /freq)
Delay1 Mode Select
or asynchronous
counter reset
reg<781:780> 00: Del ay on both fa lling and rising edges (for delay & counter reset)
01: Delay on falling edge only (fo r delay & counter reset)
10: Delay on rising edge only (for delay & counter reset)
11: No delay on either falling or rising edges / high level reset for counter mode
Table 47. CNT/DLY4 Register Settings
Signal Function Register Bit
Address Register Definition
Counter/Delay4
Mode Select reg<782> 0: Delay Mode
1: Counter Mode
Counter/Delay4
Clock Source Select
(external clock is
only for counter
mode)
reg<785:783> 000: Internal OSC Clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
101: External Clock
110: External Clock/8
111: Counter 3 Overflow
Counter4 Control
Data/Delay4 Time
Control
reg<793:786> 1-256: (delay time = (counter control da ta +2) /freq)
Delay4 Mode Select reg<795:794> 00: Delay on both falling and rising edges
01: Delay on falling edge only
10: Delay on rising edge only
11: No delay on either falling or rising edges
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SLG46722
12.7 CNT/DLY5 Register Settings
12.8 CNT/DLY6 Register Settings
Table 48. CNT/DLY5 Register Settings
Signal Function Register Bit
Address Register Definition
Counter/Delay5
Mode Select reg<796> 0: Delay Mode
1: Counter Mode
Counter/Delay5
Clock Source Select
(external clock is
only for counter
mode)
reg<799:797> 000: Internal OSC Clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
101: External Clock
110: External Clock/8
111: Counter 4 Overflow
Counter5 Control
Data/Delay5 Time
Control
reg<807:800> 1-256: (delay time = (counter control da ta +2) /freq)
Delay5 Mode Select reg<809:808> 00: Delay on both falling and rising edges
01: Delay on falling edge only
10: Delay on rising edge only
11: No delay on either falling or rising edges
Table 49. CNT/DLY6 Register Settings
Signal Function Register Bit
Address Register Definition
Counter/Delay6
Mode Select reg<810> 0: Delay Mode
1: Counter Mode
Counter/Delay6
Clock Source Select
(external clock is
only for counter
mode)
reg<813:811> 000: Internal OSC Clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
101: External Clock
110: External Clock/8
111: Counter 5 Overflow
Counter6 Control
Data/Delay6 Time
Control
reg<821:814> 1-256: (delay time = (counter control da ta +2) /freq)
Delay6 Mode Select reg<823:822> 00: Delay on both falling and rising edges
01: Delay on falling edge only
10: Delay on rising edge only
11: No delay on either falling or rising edges
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SLG46722
12.9 CNT/DLY7 Register Settings
Table 50. CNT/DLY7 Register Settings
Signal Function Register Bit
Address Register Definition
Counter/Delay67
Mode Select reg<824> 0: Delay Mode
1: Counter Mode
Counter/Delay7
Clock Source Select
(external clock is
only for counter
mode)
reg<827:825> 000: Internal OSC Clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
101: External Clock
110: External Clock/8
111: Counter 6 Overflow
Counter6 Control
Data/Delay7 Time
Control
reg<841:828> 1-16384 : (delay time = (counter control data +2) /freq)
Delay7 Mode Select reg<843:842> 00: Delay on both falling and rising edges
01: Delay on falling edge only
10: Delay on rising edge only
11: No delay on either falling or rising edges
000-0046722-105 Page 54 of 79
SLG46722
13.0 Pipe Delay (PD)
The SLG46722 has a pip e delay logic cell that is shared with the LUT3_8 in one of the Combination Function macro cells. The
user can select one of these functions to use in a design, but not both. Please see Section 10.2 3-Bit LUT or Pipe Delay Macrocell
for the description of this Combination Function macrocell.
000-0046722-105 Page 55 of 79
SLG46722
14.0 Programmable Delay / Edge Detector
The SLG46722 has a progra mmable time de lay logic cell avail able that can generate a de lay that is selectable fro m one of four
timings (time1) configured in the GreenP AK Designer. The programmable time delay cell can generate one of four different delay
patterns, rising edge detection, falling edge detection, both edge detection and both edge delay . These four patterns can be further
modified with the addition of delayed edge detection, which adds an extra unit of delay as well as glitch rejection during the delay
period. See the timing diagrams below for further information.
14.1 Programmable Delay Timing Diagram - Edge Detector Output
Figure 28. Programmable Delay
Figure 29. Edge Detector Output
Programmable
Delay OUT
IN
reg <1001:1000>
From Connection Matrix Output <81> To Connection Matrix Input<45>
reg <1003:1002>
reg <1004>
Delayed Edge Detector Output
Edge Mode Selection
Delay Value Selection
time1
Edge Detector
Output
IN
Rising Edge Detector
Falling Edge Detector
Both Edge Detector
Both Edge Delay
time1
time1 can be set by register value
time2 is a fixed value at ~200 ns
000-0046722-105 Page 56 of 79
SLG46722
14.2 Programmable Delay Timing Diagram - Glitch Filtering For Edge Detector Output
Figure 30. Delayed Edge Detector Output
Figure 31. Glitch Filtering for Edge Detector Output
Delayed Edge
Detector Output
Delayed Rising Edge Detector
Delayed Falling Edge Detector
Delayed Both Edge Detector
Delayed Both Edge Delay
time2 time2
time1 can be set by register value (125 ns, 250 ns, 375 ns, 500ns)
time2 is a fixed value at ~200 ns
IN
time1 time1
Edge
Detector Output
Delayed Edge
Detector Output
IN
Rising Edge Detector
Falling Edge Detector
Both Edge Detector
Both Edge Delay
Rising Edge Detector
Falling Edge Detector
Both Edge Detector
Both Edge Delay
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SLG46722
14.3 Programmable De lay Register Settings
Table 51. Programmable Delay Register Settings
Signal Function Register Bit
Address Register Definition
Delay value select
for programmable
delay & edge
detector
(VDD = 3.3V , typical
condition)
reg<1001:1000> 00: 125 ns
01: 250 ns
10: 375 ns
11: 500 ns
Select the edge
mode of
programmable
delay & edge
detector
reg<1003:1002> 00: Rising Edge Detector
01: Falling Edge Detector
10: Both Edge Detector
11: Both Edge Delay
Select edge
detector output
mode
reg<1004> 0: Edge Detector Output
1: Delayed Edge Detector Output
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SLG46722
15.0 Additional Logic Functions
The SLG46722 has two additional logic functions that serve as degli tch filters.
15.1 Deglitch Filter
Figure 32. Deglitch Filter
From Connection Matrix Output <92>
To Connection Matrix Input <59>
From Connection Matrix Output <93>
To Connection Matrix Input <61>
Filter_0
Filter_1
reg <1005>
reg <1006>
C
C
R
R
000-0046722-105 Page 59 of 79
SLG46722
16.0 RC Oscillator (RC Osc)
16.1 RC Oscillator Overview
The SLG46722 has tw o inte rnal RC oscill ators, one that runs at 25 kHz and one that runs at 2 MHz. The user can se lect one of
these fundamental frequencies for the RC OSC Macro cell, or the fundamental frequency can also come from an exte rnal clock
input (Pin 20). There are two divider stages that allow the user flexibility for introducing clock signals on various Connection Matrix
Input lines. The first stage divider allows the selection of /1, /2, /4 or /8 divide down frequency from the fundamental. The second
stage divider has an input of one frequency from the first stage divider, and outputs five different frequencies on Connection Matrix
Input lines <45>, <46>, <47>, <48>, and <49>. See Figure 33 below for details of the frequencies for each of these five Connection
Matrix Inputs.
If PWR DOWN input of oscillator is LOW, the oscillator will be turned on. If PWR DOWN input of oscillator is HIGH the oscillator
will be turned off. The PWR DOWN signal has the highest priority.
16.2 RC OSC Block Diagram
Figure 33. RC OSC Block Diagram
Internal RCO
reg <970>
0: 25 kHz
1: 2 MHz
/ 4
/ 8
/ 12
/ 24
/ 64
/ 3
/ 3
To Connection Matrix Input <46>
To Connection Matrix Input <47>
To Connection Matrix Input <60>
To Connection Matrix Input <49>
0
1
2
3
To Connection Matrix Input <48>
reg <976:975>
DIV /1/2/4/8
reg <973:972>
First Stage
Divider
Second Stage
Divider
Pin 20 Ext. Clock
Ext. Clk Sel reg <974>
0
1
From Connection Matrix Output <82>
PWR DOWN
000-0046722-105 Page 60 of 79
SLG46722
17.0 Power On Reset (POR)
17.1 POR Overview
The Power On Reset (POR) Macrocell will produce a high or “1” signal as an output when the device power supply (VDD) rises
to approximately 1.4 V. The typical internal delay for POR to release POR_IO will be 1 ms + α depending o n the power slope,
because there is adaptive power-up sequence. The next internal signal will be POR_CORE and then POR_IO_DL Y, each of which
is further delayed by approximately 1 µs. The rise of POR_IO_DLY will trigger the I/O pins to exit tri-state, and the device will
become active.
17.2 POR Timing Diagram
Figure 34. POR Timing Diagram
VDD
POR IO
POR CORE
POR_IO_DLY
RST
1.4 V
1 ms + α
1 μs
1 μs
Output PAD Determined by function logic
Tri-state
Initial state determined
by registers s[1:0]
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SLG46722
18.0 Appendix A - SLG46722 Register Definition
Register Bit
Address Signal Function Register Bit Definition
reg<5:0> Matrix Out: PIN3 Digital Output Source
reg<11:6> Matrix Out: PIN4 Digital Output Source
reg<17:12> Matrix Out: PIN5 Digital Output Sou rce
reg<23:18> Matrix Out: PIN6 Digital Output Sou rce
reg<29:24> Matrix Out: PIN7 Digital Output Sou rce
reg<35:30> Matrix Out: PIN8 Digital Output Sou rce
reg<41:36> Matrix Out: PIN9 Digital Output Sou rce
reg<47:42> Matrix Out: PIN10 Digital Output Source (Super Drive)
reg<53:48> Matrix Out: Input for delay0 or Counter0 external clock
reg<59:54> Matrix Out: Input for delay1 or counter1 reset input
reg<65:60> Matrix Out: Input for Counter1 external clock or delay1
external clock
reg<71:66> Matrix Out: Input for delay2 or counter2 reset input
reg<77:72> Matrix Out: Input for Counter2 external clock or delay2
external clock
reg<83:78> Matrix Out: Input for delay3 or counter3 reset input
reg<89:84> Matrix Out: Input for Counter3 external clock or delay3
external clock
reg<95:90> Matrix Out: Input for delay4 or Counter4 external clock
reg<101:96> Matrix Out: Input for delay5 or Counter5 external clock
reg<107:102> Matrix Out: Input for delay6 or Counter6 external clock
reg<113:108> Matrix Out: Input for delay7 or Counter7 external clock
reg<119:114> Matrix Out: Clock Input of DFF0
reg<125:120> Matrix Out: Data Input of DFF0
reg<131:126> Matrix Out: Resetb (Setb) of DFF0
reg<137:132> Matrix Out: Clock Input of DFF1
reg<143:138> Matrix Out: Data Input of DFF1
reg<149:144> Matrix Out: Resetb (Setb) of DFF1
reg<155:150> Matrix Out: Clock Input of DFF2
reg<161:156> Matrix Out: Data Input of DFF2
reg<167:162> Matrix Out: Resetb (Setb) of DFF2
reg<173:168> Matrix Out: Clock Input of DFF3
reg<179:174> Matrix Out: Data Input of DFF3
reg<185:180> Matrix Out: Resetb (Setb) of DFF3
reg<191:186> Matrix Out: Clock Input of DFF5
reg<197:192> Matrix Out: Data Input of DFF5
reg<203:198> Matrix Out: Clock Input of DFF6
reg<209:204> Matrix Out: Data Input of DFF6
reg<215:210> Matrix Out: In0 of LUT4_0
reg<221:216> Matrix Out: In1 of LUT4_0
reg<227:222> Matrix Out: In2 of LUT4_0
reg<233:228> Matrix Out: In3 of LUT4_0
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SLG46722
reg<239:234> Matrix Out: In0 of LUT3_0
reg<245:240> Matrix Out: In1 of LUT3_0
reg<251:246> Matrix Out: In2 of LUT3_0
reg<257:252> Matrix Out: In0 of LUT3_1
reg<263:258> Matrix Out: In1 of LUT3_1
reg<269:264> Matrix Out: In2 of LUT3_1
reg<275:270> Matrix Out: In0 of LUT3_2
reg<281:276> Matrix Out: In1 of LUT3_2
reg<287:282> Matrix Out: In2 of LUT3_2
reg<293:288> Matrix Out: In0 of LUT3_3
reg<299:294> Matrix Out: In1 of LUT3_3
reg<305:300> Matrix Out: In2 of LUT3_3
reg<311:306> Matrix Out: In0 of LUT3_4
reg<317:312> Matrix Out: In1 of LUT3_4
reg<323:318> Matrix Out: In2 of LUT3_4
reg<329:324> Matrix Out: In0 of LUT3_5
reg<335:330> Matrix Out: In1 of LUT3_5
reg<341:336> Matrix Out: In2 of LUT3_5
reg<347:342> Matrix Out: In0 of LUT3_6
reg<353:348> Matrix Out: In1 of LUT3_6
reg<359:354> Matrix Out: In2 of LUT3_6
reg<365:360> Matrix Out: In0 of LUT3_7
reg<371:366> Matrix Out: In1 of LUT3_7
reg<377:372> Matrix Out: In2 of LUT3_7
reg<383:378> Matrix Out: In0 of LUT3_8 or Input of Pipe delay
reg<389:384> Matrix Out: In1 of LUT3_8 or Resetb of Pipe delay
reg<395:390> Matrix Out: In2 of LUT3_8 or Clock of Pipe delay
reg<401:396> Matrix Out: In0 of LUT3_9
reg<407:402> Matrix Out: In1 of LUT3_9
reg<413:408> Matrix Out: In2 of LUT3_9
reg<419:414> Matrix Out: In0 of LUT2_0 or Clock Input of DFF4
reg<425:420> Matrix Out: In1 of LUT2_0 or Data Input of DFF4
reg<431:426> Matrix Out: In0 of LUT2_1
reg<437:432> Matrix Out: In1 of LUT2_1
reg<443:438> Matrix Out: In0 of LUT2_2
reg<449:444> Matrix Out: In1 of LUT2_2
reg<455:450> Matrix Out: In0 of LUT3_2
reg<461:456> Matrix Out: In1 of LUT2_3
reg<467:462> Matrix Out: In0 of LUT2_4
reg<473:468> Matrix Out: In1 of LUT2_4
reg<439:474> Matrix Out: In0 of LUT2_5
reg<485:480> Matrix Out: In1 of LUT2_5
Register Bit
Address Signal Function Register Bit Definition
000-0046722-105 Page 63 of 79
SLG46722
reg<491:486> Matrix Out: Input for programmable delay & edge detec-
tor
reg<497:492> Matrix Out: Power down for osc
reg<503:498> Matrix Out: Pin12 Digital Output Source (Super Drive)
reg<509:504> Matrix Out: Pin13 Digital Output Source
reg<515:510> Matrix Out: Pin14 Digital Output Source
reg<521:516> Matrix Out: Pin15 Digital Output Source
reg<527:522> Matrix Out: Pin16 Digital Output Source
reg<533:528> Matrix Out: Pin17 Digital Output Source
reg<539:534> Matrix Out: Pin18 Digital Output Source
reg<545:540> Matrix Out: Pin19 Digital Output Source
reg<551:546> Matrix Out: Pin20 Digital Output Source
reg<557:552> Matrix Out: Input of filter_0
reg<563:558> Matrix Out: Input of filter_1
reg<569:564> Matrix Out: Reserved
reg<571:570> Reserved
reg<575:572>
LUT2_0 data or
reg<572> DFF 4 or L at c h se le ct 0: DFF function
1: Latch fu nction
reg<573> DFF4 output select 0: Q output
1: nQ output
reg<574> DFF4 initial polarity select 0: Low
1: High
reg<579:576> LUT2_1 data
reg<583:580> LUT2_2 data
reg<587:584> LUT2_3 data
reg<591:588> LUT2_4 data
reg<595:592> LUT2_5 data
reg<596> LUT2_0 or DFF4 select 0: LUT2_0
1: DFF4
reg<604:597> LUT3_0 data
reg<612:605> LUT3_1 data
reg<620:613> LUT3_2 data
reg<628:621> LUT3_3 data
reg<636:629> LUT3_4 data
reg<644:637> LUT3_5 data
reg<652:645> LUT3_6 data
reg<660:653> LUT3_7 data
reg<668:661> LUT3_8 data or pipe number select
reg<664: 661>: OUT0 select
reg<668: 665>: OUT1 select
reg<676:669> LUT3_9 data
reg<692:677> LUT4_0 data
reg<693> DFF0 or Latch Select 0: DFF function
1: Latch fu nction
Register Bit
Address Signal Function Register Bit Definition
000-0046722-105 Page 64 of 79
SLG46722
reg<694> DFF0 rstb/setb select 0: resetb from matrix out
1: setb from matrix out
reg<695> DFF0 Initial polarity select 0: Low
1: High
reg<696> DFF1 or Latch Select 0: DFF function
1: Latch fu nction
reg<697> DFF1 output select (Q or nQ) 0: Q output
1: nQ output
reg<698> DFF1 rstb/setb select 1: setb from matrix out
0: resetb from matrix out
reg<699> DFF1 Initial polarity select 0: Low
1: High
reg<700> DFF2 or Latch Select 0: DFF function
1: Latch fu nction
reg<701> DFF2 output select (Q or nQ) 0: Q output
1: nQ output
reg<702> DFF2 rstb/setb select 1: setb from matrix out
0: resetb from matrix out
reg<703> DFF2 Initial polarity select 0: Low
1: High
reg<704> DFF3 or Latch Select 0: DFF function
1: Latch fu nction
reg<705> DFF3 output select (Q or nQ) 0: Q output
1: nQ output
reg<706> DFF3 rstb/setb select 1: setb from matrix out
0: resetb from matrix out
reg<707> DFF3 Initial polarity select 0: Low
1: High
reg<708> DFF5 or Latch Select 0: DFF function
1: Latch fu nction
reg<709> DFF5 output select (Q or nQ) 0: Q output
1: nQ output
reg<710> DFF5 Initial polarity select 0: Low
1: High
reg<711> DFF6 or Latch Se le ct 0: DFF function
1: Latch fu nction
reg<712> DFF6 output select (Q or nQ) 0: Q output
1: nQ output
reg<713> DFF6 Initial polarity select 0: Low
1: High
reg<714> Counter/Delay0 mode select 0: Delay Mode
1: Counter Mode
reg<717:715> Counter/delay0 Clock Source Select
(external clock is only for counter mode)
000: Internal OSC Clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
101: External Clock
110: External Clock/8
111: Counter 7 Overflow
reg<731:718> Counter0 Control Data/Delay0 Time Control 1-16384: (delay time = (counter control data +2) /freq)
Register Bit
Address Signal Function Register Bit Definition
000-0046722-105 Page 65 of 79
SLG46722
reg<733:732> Delay0 Mode Select 00: Delay on both falling and rising edges
01: Delay on falling edge only
10: Delay on rising edge only
11: No delay on either falling or rising edges
reg<734> Counter/Delay1 mode select 0: Delay Mode
1: Counter Mode
reg<737:735> Counter/delay1 Clock Source select
000: Internal OSC Clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
101: External Clock
110: External Clock/8
111: Counter 0 Overflow
reg<751:738> Counter1 Control Data/Delay1 Time Control 1-16384: (delay time = (counter control data +2) /freq)
reg<753:752> Delay1 Mode Select or asynchronous counter reset
00: Delay on both falling and rising edges (for delay
& counter reset)
01: Delay on falling edge only (for delay & counter
reset)
10: Delay on rising edge only (for delay & counter
reset)
11: No delay on either falling or rising edges / high
level reset for counter mode
reg<754> Counter/Delay2 Mo de selection 0: Delay Mode
1: Counter Mode
reg<757:755> Counter/delay2 Clock Source select
000: Internal OSC Clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
101: External Clock
110: External Clock/8
111: Counter 1 Overflow
reg<765:758> Counter2 Control Data/Delay2 Time Control 1-256: (delay time = (counter contro l data +2) /freq)
reg<767:766> Delay2 Mode Select or asynchronous counter reset
00: Delay on both falling and rising edges (for delay &
counter reset)
01: Delay on falling edge only (for delay & counter re-
set)
10: Delay on rising edge only (for delay & counter re-
set)
11: No delay on either falling or rising edges / high level
reset for counter mode
reg<768> Counter/Delay3 Mo de selection 0: Delay Mode
1: Counter Mode
reg<771:769> Counter/delay3 Clock Source select
000: Internal OSC Clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
101: External Clock
110: External Clock/8
111: Counter 2 Overflow
reg<779:772> Counter3 Control Data/Delay3 Time Control 1-256: (delay time = (counter contro l data +2) /freq)
Register Bit
Address Signal Function Register Bit Definition
000-0046722-105 Page 66 of 79
SLG46722
reg<781:780> Delay3 Mode Select or asynchronous counter reset
00: Delay on both falling and rising edges (for delay
& counter reset)
01: Delay on falling edge only (for delay & counter
reset)
10: Delay on rising edge only (for delay & counter
reset)
11: No delay on either falling or rising edges / high
level reset for counter mode
reg<782> Counter/Delay4 Mo de Selection 0: Delay Mode
1: Counter Mode
reg<785:783> Counter/delay4 Clock Source select
000: Internal OSC Clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
101: External Clock
110: External Clock/8
111: Counter 3 Overflow
reg<793:786> Counter4 Control Data/Delay4 Time Control 1-256: (delay time = (counter contro l data +2) /freq)
reg<795:794> Delay4 Mode Select 00: Delay on both falling and rising edges
01: Delay on falling edge only
10: Delay on rising edge only
11: No delay on either falling or rising edges
reg<796> Counter/Delay5 Mo de Selection 0: Delay Mode
1: Counter Mode
reg<799:797> Counter/delay5 Clock Source select
(external clock is only for counter mode)
000: Internal OSC Clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
101: External Clock
110: External Clock/8
111: Counter 4 Overflow
reg<807:800> Counter5 Control Data/Delay5 Time Control 1-256: (delay time = (counter contro l data +2) /freq)
reg<809:808> Delay5 Mode Select 00: Delay on both falling and rising edges
01: Delay on falling edge only
10: Delay on rising edge only
11: No delay on either falling or rising edges
reg<810> Counter/Delay6 Mo de Selection 0: Delay Mode
1: Counter Mode
reg<813:811> Counter/delay6 Clock Source select
(external clock is only for counter mode)
000: Internal OSC Clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
101: External Clock
110: External Clock/8
111: Counter 5 Overflow
reg<821:814> Counter6 Control Data/Delay6 Time Control 1-256: (delay time = (counter contro l data +2) /freq)
reg<823:822> Delay6 Mode Select 00: Delay on both falling and rising edges
01: Delay on falling edge only
10: Delay on rising edge only
11: No delay on either falling or rising edges
reg<824> Counter/Delay7 Mo de Selection 0: Delay Mode
1: Counter Mode
Register Bit
Address Signal Function Register Bit Definition
000-0046722-105 Page 67 of 79
SLG46722
reg<827:825> Counter/Delay7 Mo de Selection
(external clock is only for counter mode)
000: Internal OSC Clock
001: OSC/4
010: OSC/12
011: OSC/24
100: OSC/64
101: External Clock
110: External Clock/8
111: Counter 6 Overflow
reg<841:828> Counter7 Control Data/Delay7 Time Control 1-16384:(delay time = (counter control data +2)/freq
reg<843:842> Delay7 Mode Select 00: Delay on both falling and rising edges
01: Delay on falling edge only
10: Delay on rising edge only
11: No delay on either falling or rising edges
<845:844> PIN2 mode control 00: Digital Input without Schmitt Trigger
01: Digital Input with Schmitt Trigger
10: Low Voltage Digital Input
11: Reserved
<847:846> PIN2 pull down resistor value selection 00: floating
01: 10K
10: 100K
11: 1M
<850:848> PIN3 mode control
000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Reserved
100: Push Pull
101: Open Drain NMOS
110: Open Drain PMOS
111: Reserved
<852:851> PIN3 pull up/down resistor value selectio n 00: floating
01: 10K
10: 100K
11: 1M
<853> PIN3 pull up/down resisto r select 0: pull down resistor enable
1: pull up resistor enable
<854> PIN3 driver strength selection 0: 1X
1: 2X
<857:855> PIN4 mode control
000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Reserved
100: Push Pull
101: Open Drain NMOS
110: Open Drain PMOS
111: Reserved
<859:889> PIN4 pull up/down resistor value selectio n 00: floating
01: 10K
10: 100K
11: 1M
<860> PIN4 pull up/down resisto r select 0: pull down resistor enable
1: pull up resistor enable
<861> PIN4 driver strength selection 0: 1X
1: 2X
Register Bit
Address Signal Function Register Bit Definition
000-0046722-105 Page 68 of 79
SLG46722
<864:862> PIN5 mode control
000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Reserved
100: Push Pull
101: Open Drain NMOS
110: Open Drain PMOS
111: Reserved
<866:865> PIN5 pull up/down resistor value selectio n 00: floating
01: 10K
10: 100K
11: 1M
<867> PIN5 pull up/down resisto r select 0: pull down resistor enable
1: pull up resistor enable
<868> PIN5 driver strength selection 0: 1X
1: 2X
<871:869> PIN6 mode control
000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Reserved
100: Push Pull
101: Open Drain NMOS
110: Open Drain PMOS
111: Reserved
<873:872> PIN6 pull up/down resistor value selectio n 00: floating
01: 10K
10: 100K
11: 1M
<874> PIN6 pull up/down resisto r select 0: pull down resistor enable
1: pull up resistor enable
<875> PIN6 driver strength selection 0: 1X
1: 2X
<878:876> PIN7 mode control
000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Reserved
100: Push Pull
101: Open Drain NMOS
110: Open Drain PMOS
111: Reserved
<880:879> PIN7 pull up/down resistor value selectio n 00: floating
01: 10K
10: 100K
11: 1M
<881> PIN7 pull up/down resisto r select 0: pull down resistor enable
1: pull up resistor enable
<882> PIN7 driver strength selection 0: 1X
1: 2X
Register Bit
Address Signal Function Register Bit Definition
000-0046722-105 Page 69 of 79
SLG46722
<885:883> PIN8 mode control
000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Reserved
100: Push Pull
101: Open Drain NMOS
110: Open Drain PMOS
111: Reserved
<887:886> PIN8 pull up/down resistor value selectio n 00: floating
01: 10K
10: 100K
11: 1M
<888> PIN8 pull up/down resisto r select 0: pull down resistor enable
1: pull up resistor enable
<889> PIN8 driver strength selection 0: 1X
1: 2X
<892:890> PIN9 mode control
000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Reserved
100: Push Pull
101: Open Drain NMOS
110: Open Drain PMOS
111: Reserved
<894:893> PIN9 pull up/down resistor value selectio n 00: floating
01: 10K
10: 100K
11: 1M
<895> PIN9 pull up/down resisto r select 0: pull down resistor enable
1: pull up resistor enable
<896> PIN9 driver strength selection 0: 1X
1: 2X
<899:897> PIN10 mode control
000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Reserved
100: Push Pull
101: Open Drain NMOS
110: Open Drain PMOS
111: Reserved
<901:900> PIN10 pull up/down resistor value selection 00: floating
01: 10K
10: 100K
11: 1M
<902> PIN10 pull up/down resistor select 0: pull down resistor enable
1: pull up resistor enable
<903> PIN10 driver strength selection 0: 1X
1: 2X
<904> PIN10 super drive(4X, NMOS open drain) selection 0: super drive off
1: super drive on (if <899: 897> = 101)
Register Bit
Address Signal Function Register Bit Definition
000-0046722-105 Page 70 of 79
SLG46722
<907:905> PIN12 mode control
000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Reserved
100: Push Pull
101: Open Drain NMOS
110: Open Drain PMOS
111: Reserved
<909:908> PIN12 pull up/down resistor value selection 00: floating
01: 10K
10: 100K
11: 1M
<910> PIN12 pull up/down resistor select 0: pull down resistor enable
1: pull up resistor enable
<911> PIN12 driver strength selection 0: 1X
1: 2X
<912> PIN12 super drive(4X, NMOS open drain) selection 0: super drive off
1: super drive on (if <907: 905> = 101)
<915:913> PIN13 mode control
000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Reserved
100: Push Pull
101: Open Drain NMOS
110: Open Drain PMOS
111: Reserved
<917:916> PIN13 pull up/down resistor value selection 00: floating
01: 10K
10: 100K
11: 1M
<918> PIN13 pull up/down resistor select 0: pull down resistor enable
1: pull up resistor enable
<919> PIN13 driver strength selection 0: 1X
1: 2X
<922:920> PIN14 mode control
000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Reserved
100: Push Pull
101: Open Drain NMOS
110: Open Drain PMOS
111: Reserved
<924:923> PIN14 pull up/down resistor value selection 00: floating
01: 10K
10: 100K
11: 1M
<925> PIN14 pull up/down resistor select 0: pull down resistor enable
1: pull up resistor enable
<926> PIN14 driver strength selection 0: 1X
1: 2X
Register Bit
Address Signal Function Register Bit Definition
000-0046722-105 Page 71 of 79
SLG46722
<929:927> PIN15 mode control
000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Reserved
100: Push Pull
101: Open Drain NMOS
110: Open Drain PMOS
111: Reserved
<931:930> PIN15 pull up/down resistor value selection 00: floating
01: 10K
10: 100K
11: 1M
<932> PIN15 pull up/down resistor select 0: pull down resistor enable
1: pull up resistor enable
<933> PIN15 driver strength selection 0: 1X
1: 2X
<936:934> PIN16 mode control
000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Reserved
100: Push Pull
101: Open Drain NMOS
110: Open Drain PMOS
111: Reserved
<938:937> PIN16 pull up/down resistor value selection 00: floating
01: 10K
10: 100K
11: 1M
<939> PIN16 pull up/down resistor select 0: pull down resistor enable
1: pull up resistor enable
<940> PIN16 driver strength selection 0: 1X
1: 2X
<943:941> PIN17 mode control
000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Reserved
100: Push Pull
101: Open Drain NMOS
110: Open Drain PMOS
111: Reserved
<945:944> PIN17 pull up/down resistor value selection 00: floating
01: 10K
10: 100K
11: 1M
<946> PIN17 pull up/down resistor select 0: pull down resistor enable
1: pull up resistor enable
<947> PIN17 driver strength selection 0: 1X
1: 2X
Register Bit
Address Signal Function Register Bit Definition
000-0046722-105 Page 72 of 79
SLG46722
<950:948> PIN18 mode control
000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Reserved
100: Push Pull
101: Open Drain NMOS
110: Open Drain PMOS
111: Reserved
<952:951> PIN18 pull up/down resistor value selection 00: floating
01: 10K
10: 100K
11: 1M
<953> PIN18 pull up/down resistor select 0: pull down resistor enable
1: pull up resistor enable
<954> PIN18 driver strength selection 0: 1X
1: 2X
<957:955> PIN19 mode control
000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Reserved
100: Push Pull
101: Open Drain NMOS
110: Open Drain PMOS
111: Reserved
<959:558> PIN19 pull up/down resistor value selection 00: floating
01: 10K
10: 100K
11: 1M
<960> PIN19 pull up/down resistor select 0: pull down resistor enable
1: pull up resistor enable
<961> PIN19 driver strength selection 0: 1X
1: 2X
<964:962> PIN20 mode control
000: Digital Input without Schmitt Trigger
001: Digital Input with Schmitt Trigger
010: Low Voltage Digital Input
011: Reserved
100: Push Pull
101: Open Drain NMOS
110: Open Drain PMOS
111: Reserved
<966:965> PIN20 pull up/down resistor value selection 00: floating
01: 10K
10: 100K
11: 1M
<967> PIN20 pull up/down resistor select 0: pull down resistor enable
1: pull up resistor enable
<968> PIN20 driver strength selection 0: 1X
1: 2X
reg<969> Force RC oscillator on 0: Auto Power on
1: Force Power on
reg<970> RC Oscillator frequency control 0: 25K
1: 2M
reg<971> Reserved
Register Bit
Address Signal Function Register Bit Definition
000-0046722-105 Page 73 of 79
SLG46722
reg<973:972> Internal Oscillator frequency divider control 00: OSC/8
01: OSC/12
10: OSC/24
11: OSC/64
reg<974> External Clock Source Select 0: Internal Oscillator
1: External Clock from Pin20
reg<976:975> Osc clock pre-divider 00: Div1
01: Div2
10: Div4
11: Div8
reg<977> LUT3_8 or pipe delay ou tput select 0: Lut3_8
1: 1 pipe delay output
reg<978> Pipe delay OUT1 polarity select bit 0: non-inverted
1: inverted
reg<979> NVM data read disable 0: Disable (program data can be read)
1: Enable (Program data cannot be read)
reg<980> NVM power down 0: None (or programming enable)
1: Power Down (or programming disable)
reg<981> GPIO quick charge enable 0: Disable
1: Enable
reg<983: 982> Reserved
reg<991:984> Reserved
reg<999:992> 8-bit Pattern ID
reg<1001:1000> Delay valu e select for progra mmable delay & edge de-
tector
(VDD 3.3V, typ)
00: 125 ns
01: 250 ns
10: 375 ns
11: 500 ns
reg<1003:1002> Select the edge mode of programmable delay & edge
detector
00: rising edge detector
01: falling edge detector
10: both edge detector
11: both edge delay
reg<1004> Select edge detector output mode 0: edge detector output
1: delayed edge detector output
reg<1005> Select polarity of filter_0 output 0: non-inverted
1: inverted
reg<1006> Select polarity of filter_1 output 0: non-inverted
1: inverted
reg<1007> Reserved
reg<1013:1008 > Reserved
reg<1014> Reserved
reg<1015> Reserved
reg<1023:1016> Reserved
Register Bit
Address Signal Function Register Bit Definition
000-0046722-105 Page 74 of 79
SLG46722
19.0 Package Top Marking System Definition
Part Code
Datecode Lot
Revision
– Part ID Field: identifies the specific device configuration
– Date Code Field: Coded date of manufacture
– Lot Code: Designates Lot #
– Assembly Site/COO: Specifies Assembly Site/Country of Origin
– Revision Code: Device Revision
XXXXX
DD
LLL
C
RR
COO
000-0046722-105 Page 75 of 79
SLG46722
20.0 Package Drawing and Dimensions
STQFN 20L 2x3mm 0.4P COL Package
JEDEC MO-220, Variation WECE
IC Net Weight: 0.015 g
000-0046722-105 Page 76 of 79
SLG46722
21.0 Tape and Reel Specifications
21.1 Carrier Tape Drawing and Dimensions
Package
Type # of
Pins
Nominal
Package Size
[mm]
Max Units Reel &
Hub Size
[mm]
Leader (min) Trailer (min) Tape
Width
[mm]
Part
Pitch
[mm]
per Reel per Box Pockets Length
[mm] Pockets Length
[mm]
STQFN
20L 2x3
mm 0.4P
COL 20 2 x 3 x 0.55 3,000 3,000 178 / 60 100 400 100 400 8 4
Package
Type
Pocket BTM
Length Pocket BTM
Width Pocket
Depth Index Hole
Pitch Pocket
Pitch Index Hole
Diameter
Index Hole
to Tape
Edge
Index Hole
to Pocket
Center Tape Width
A0 B0 K0 P0 P1 D0 E F W
STQFN 20L
2x3 mm
0.4P COL 2.2 3.15 0.76 4 4 1.5 1.75 3.5 8
Refer to EIA-481 specification
000-0046722-105 Page 77 of 79
SLG46722
22.0 Recommended Land Pattern
23.0 Recommended Reflow Soldering Profile
Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 3.30 mm3 (nominal). More
information can be found at www.jedec.org.
Units: μm
000-0046722-105 Page 78 of 79
SLG46722
24.0 Revision History
Date Version Change
8/29/2014 1.05 Added Emulator Reset description fo r Pin 3
Updated Electrical Characteristics VIH/VIL/VOH/VOL values
Fixed table formatting for some tables
8/06/2014 1.04 Updated Electrical Characteristics VIH/VIL/VOH/VOL values
7/29/2014 1.03 F ixed ESD information
7/9/2014 1.02 Fixed typo on Pin Configuration
Fixed LUT Standard Digital Function Tables
7/7/2014 1.01 Fixed Package Outline Drawing (removed incorrect side view)
7/3/2014 1.0 Production Release
3/18/2014 0.45 Updated block diagrams and timing diagrams for clarity
2/3/2014 0.44 Fixed typos and Cleanup
11/21/2013 0.43 Added ESD Ratings and MSL to Absolute Maximum Conditions
11/20/2013 0.42 Updated Package Outline Drawing
Updated Tape and Reel Specifications
Added Recommended Land pattern
10/9/2013 0.41 Updated VIH for Logic Input
10/2/2013 0.4 Updated VIH/VIL values
9/11/13 0.31 Adjusted RC OSC Block Diagram
7/17/2013 0.3 Added IO Structures
5/7/2013 0.2 Added newsections
Updated Tape and Reel spec
11/14/2012 0.1 Initial release
000-0046722-105 Page 79 of 79
SLG46722
Silego Website & Support
Silego Technology Website
Silego Technology provides onlin e support via ou r website at http://www.silego.com/.This website is used as a means to make
files and information easily available to customers.
For more information regarding Silego Green products, please visit:
http://greenpak.silego.com/
http://greenpak2.silego.com/
http://greenpak3.silego.com/
http://greenfet.silego.com/
http://greenfet2.silego.com/
http://greenclk.silego.com/
Products are also available for purchase directly from Silego at the Silego Online Store at http://store.silego.com/.
Silego Technical Support
Datasheets and errata, application notes and example designs, user guides, and hardware support documents and the latest
software releases are available at the Silego website or can be requested di rectly at info@silego.com.
For specific GreenPAK design or applications questions and support please send e-mail requests to GreenPAK@silego.com
Users of Silego products can receive assistance through several channels:
Online Training
Silego Technology has live training assistance and sales support available at http://www.silego.com/. Please cont act us to sched -
ule a 1 on 1 training session with one of our application engineers.
Contact Your Local Sales Representative
Customers can contact their local sales representative or field application engineer (F AE) for support. Local sales offices are also
available to help customers. More information regarding your local representative is available at the Silego website or send a
request to info@silego.com
Contact Silego Directly
Silego can be contacted directly via e-mail at info@silego.com or user submission form, located at the following URL:
http://support.silego.com/
Other Information
The latest Silego Technology press releases, listing of seminars and events, listings of world wide Silego Technology offices and
representatives are all available at http://www.silego.com/
THIS PRODUCT HAS BEEN DESIGNED AND QUALIFIED FOR THE CONSUMER MARKET. APPLICATIONS OR USES AS CRITICAL COMPONENTS IN LIFE
SUPPORT DEVICES OR SY STEMS ARE NOT AUTHORIZED. SILEGO TECHNOLOGY DOES NOT ASSUME ANY LIAB ILITY ARISING OUT OF SUCH APPLICA-
TIONS OR USES OF ITS PRODUCTS. SILEGO TECHNOLOGY RESERVES THE RIGHT TO IMPROVE PRODUCT DESIG N, FUNCTIONS AND RELI ABILITY
WITHO UT NOTICE.
