NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Features * VDD=VDDQ= 1.5V +0.125V/-0.075V * 2k page size for x16 * 4 internal memory banks * Data-Strobes: Bidirectional, Differential * Programmable CAS Latency: 3, 4 and 5 * Strong and Weak Strength Data-Output Driver * Programmable Additive Latency: 0, 1, 2, 3, 4 and 5 * Auto-Refresh and Self-Refresh * Write Latency = Read Latency -1 * Power Saving Power-Down modes * Programmable Burst Length: 4 and 8 * 7.8 s max. Average Periodic Refresh Interval * Programmable Sequential / Interleave Burst * Packages: * OCD (Off-Chip Driver Impedance Adjustment) 60 Ball BGA for x4 & x8 components 84 Ball BGA for x16 component * ODT (On-Die Termination) * RoHS Compliance * 4 bit prefetch architecture * 1k page size for x4 & x8, Description The 512Mb Double-Data-Rate-2 (DDR2) DRAMs is a highspeed CMOS Double Data Rate 2 SDRAM containing 536,870,912 bits. It is internally configured as a Quad-bank DRAM. The 512Mb chip is organized as either 32Mbit x 4 I/O X4 bank ,16Mbit x 8 I/O x 4 bank or 8Mbit x 16 I/O x 4 bank device. The chip is designed to comply with all key DDR2 DRAM key features: (1) posted CAS with additive latency, (2) write latency = read latency -1, (3) normal and weak strength dataoutput driver, (4) variable data-output impedance adjustment and (5) an ODT (On-Die Termination) function. All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchronous fashion. A 14 bit address bus x 4& x 8 organised components and A 13 bit address bus for x16 components is used to convey row, column, and bank address devices. These devices operate with a single 1.5V +0.125V/-0.075V power supply and are available in BGA packages. An Auto-Refresh and Self-Refresh mode is provided along with various power-saving power-down modes. REV 1.0 04/2008 1 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Pin Configuration - 60 balls 0.8mmx0.8mm Pitch BGA Package (x4/x8) <Top View > See the balls through the package. x4 1 2 3 7 8 9 VDD NC VSS A VSSQ DQS VDDQ NC VSSQ DM B DQS VSSQ NC VDDQ DQ1 VDDQ C VDDQ DQ0 VDDQ NC VSSQ DQ3 D DQ2 VSSQ NC VDDL VREF VSS E VSSDL CK VDD CKE WE F RAS CK ODT BA0 BA1 G CAS CS A10/AP A1 H A2 A0 A3 A5 J A6 A4 A7 A9 K A11 A8 A12 NC L NC A13 NC VSS VDD VDD VSS x8 1 2 3 7 8 9 VDD NU,/RDQS VSS A VSSQ DQS VDDQ DQ6 VSSQ DM/RDQS B DQS VSSQ DQ7 VDDQ DQ1 VDDQ C VDDQ DQ0 VDDQ DQ4 VSSQ DQ3 D DQ2 VSSQ DQ5 VDDL VREF VSS E VSSDL CK VDD CKE WE F RAS CK ODT BA0 BA1 G CAS CS A10/AP A1 H A2 A0 A3 A5 J A6 A4 A7 A9 K A11 A8 A12 NC L NC A13 NC VSS VDD REV 1.0 04/2008 VDD VSS 2 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Pin Configuration - 84 balls 0.8mmx0.8mm Pitch BGA Package (x16) <Top View > See the balls through the package. x 16 1 2 3 7 8 9 VDD NC VSS A VSSQ UDQS VDDQ DQ14 VSSQ UDM B UDQS VSSQ DQ15 VDDQ DQ9 VDDQ C VDDQ DQ8 VDDQ DQ12 VSSQ DQ11 D DQ10 VSSQ DQ13 VDD NC VSS E VSSQ LDQS VDDQ DQ6 VSSQ LDM F LDQS VSSQ DQ7 VDDQ DQ1 VDDQ G VDDQ DQ0 VDDQ DQ4 VSSQ DQ3 H DQ2 VSSQ DQ5 VDDL VREF VSS J VSSDL CK VDD CKE WE K RAS CK ODT BA0 BA1 L CAS CS A10/AP A1 M A2 A0 A3 A5 N A6 A4 A7 A9 P A11 A8 A12 NC R NC NC BA2 VSS VDD REV 1.0 04/2008 VDD VSS 3 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Input/Output Functional Description Symbol Type Function Input Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing). CKE Input Clock Enable: CKE high activates and CKE low deactivates internal clock signals and device input buffers and output drivers. Taking CKE low provides Precharge Power-Down and SelfRefresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit and for Self-Refresh entry. CKE is asynchronous for SelfRefresh exit. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK, ODT and CKE are disabled during Power Down. Input buffers, excluding CKE are disabled during Self-Refresh. CS Input Chip Select: All command are masked when CS is registered high. CS provides for external rank selection on systems with multiple memory ranks. CS is considered part of the command code. RAS, CAS, WE Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. DM (LDM, UDM) Input Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled high coincident with that input data during a Write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. BA0-BA1 Input Bank Address Inputs: BA0 - BA1 define to which bank an Active, Read, Write or Precharge command is being applied. Bank address also determines if the mode register or one of the extended mode registers is to be accessed during a MRS or EMR command cycle. A0 - A12,A13 Input Address Inputs: Provides the row address for Activate commands and the column address and Auto-Precharge bit for Read/Write commands to select one location out of the memory array in the respective bank. A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0 - BA1. The address inputs also provide the op-code during MRS or EMRS command. Row address A13 is used on x4 & x8 components only. DQ Input/Output Data Inputs/Output: Bi-directional data bus. DQS, DQS LDQS, LDQS UDQS, UDQS Input/Output Data Strobe: output with read data, input with write data. Edge aligned with read data, centered in write data. For the x16, LDQS corresponds to the data on DDQ0 - DQ7; UDQS corresponds to the data on DQ8-DQ15. The data strobes LDQS and UDQS may be used in single ended mode or paired with the optional complementary signals LDQS and UDQS to provide differential pair signaling to the system during both reads and writes. A control bit at EMR(1)[A10] control bit enables or disables the complementary data strobe signals. ODT Input On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is applied to each UDQS, UDQS, LDQS, LDQS, UDM and LDM signal. The ODT pin will be ignored if the EMR(1) is programmed to disable ODT. CK, CK NC No Connect: No internal electrical connection is present. VDDQ Supply DQ Power Supply: 1.5V +0.125V/-0.075V VSSQ Supply DQ Ground VDDL Supply DLL Power Supply: 1.5V +0.125V/-0.075V VSSDL Supply DLL Ground VDD Supply Power Supply: 1.5V +0.125V/-0.075V VSS Supply Ground VREF Supply Vref = VDDQ/2 REV 1.0 04/2008 4 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Ordering Information Speed Org. Part Number Package NT5TB128M4CE-3C 128M x 4 NT5TB128M4CE-25C NT5TB64M8CE-3C 64M x 8 60ball BGA 0.8mmx0.8mm Pitch NT5TB64M8CE-25C NT5TB32M16CG-3C 32M x 16 NT5TB32M16CG-25C 84ball BGA 0.8mmx0.8mm Pitch Clock (MHz) CL-tRCD-tRP 333 5-5-5 400 5-5-5 333 5-5-5 400 5-5-5 333 5-5-5 400 5-5-5 Note: It supports very low power DDR2 operation (1.5V) REV 1.0 04/2008 5 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Basic Functionality Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue for a burst length of four or eight in a programmed sequence. Accesses begin with the registration of an Activate command, which is then followed by a Read or Write command. The address bits registered coincident with the activate command are used to select the bank and row to be accesses (BA0 - BA1 select the banks, A0-A13 select the row for x4 & x8 components, A0-A12 select the row for x16 component). The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst access and to determine if the Auto-Precharge command is to be issued. Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command description and device operation. Initialization DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. For DDR2 SDRAMs, both bits BA0 and BA1 must be decoded for Mode/Extended Mode Register Set (MRS/EMR) commands. Users must initialize all four Mode Registers. The registers maybe initialized in any order. The following sequence is required for POWER UP and Initialization. 1. Either one of the following sequence is required for Power-up. 1(a). While applying power and attempt to maintain CKE below 0.2 * VDDQ and ODT at a LOW state (all other inputs may be undefined). The VDD voltage ramp time must be no greater than 200ms from when VDD ramps from 300mV to VDD min; and during the VDD voltage ramp, lVDD-VDDQl<=0.3V. Once the ramping of the supply voltages is complete (when VDDQ crosses VDDQ min). - VDD,VDDL, and VDDQ are driven from a single power converter output, AND - VTT is limited to 0.95 V max, AND - VREF tracks VDDQ/2, VREF must be within +/- 300mV with respect to VDDQ/2 during supply ramp time. - VDDQ>=VREF must be met at all times. or 1(b). While applying power and attempt to maintain CKE below 0.2 * VDDQ and ODT at a LOW state, all other inputs may be undefined, voltage levels at I/Os and outputs must be less than VDDQ during voltage ramp time to avoid DRAM latchup. During the ramping of the supply voltages, VDD>=VDDL>=VDDQ must be maintained and is applicable to both AC and DC levels until the ramping of the supply voltages is complete, which is when VDDQ crosses VDDQ min. Once the ramping of the supply voltages is complete, the supply voltage specifications provided in Recommanded DC operating conditions. - Apply VDD/VDDL before or at the same time as VDDQ, - VDD/VDDL voltage ramp time must be no greater than 200ms from when VDD ramps from 300mV to VDD min. - Apply VDDQ before or at the same time as VTT. - The VDDQ voltage ramp time from when VDD min is achieved on VDD to when VDDQ min is achieved on VDDQ must be no greater than 500ms. (Note: While VDD is ramping, current may be supplied from VDD through the DRAM to VDDQ.) - Vref must track VDDQ/2, Vref must be within +/-300mV with respect to VDDQ/2 during supply ramp time. - VDDQ>=VREF must be met at all times. - Apply VTT. - The VTT voltage ramp time from when VDDQ min is achieved on VDDQ to when VTT min is achieved on VTT must be greater than 500ms. 2. Start clock and maintain stable condition. 3. For the minimum of 200us after stable power (VDD, VDDL, VDDQ, VREF, and VTT are between their minimum and maximum values as states in Recommanded DC operating conditions and stable clock, then apply NOP or Deselcect & take CKE HIGH. 4. Wait minimum of 400ns, then issue Precharge-all command. NOP or Deselect applied during 400ns period. REV 1.0 04/2008 6 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die 5. Issue an EMRS command to EMR(2). (To issue EMRS command to EMR(2), provide LOW to BA0 and HIGH to BA1) 6. Issue an EMRS command to EMR(3). (To issue EMRS command to EMR(3), provide HIGH to BA0 and BA1) 7. Issue EMRS to enable DLL. (To issue "DLL Enable" command, provide LOW to A0 and HIGH to BA0 and LOW to BA1. And A9=A8=A7=LOW must be used when issuing this command.) 8. Issue Mode Register Set command for "DLL reset". (To issue DLL reset command, provide HIGH to A8 and LOW to BA0 ~ BA1) 9. Issue Precharge-All command. 10. Issue 2 or more Auto-Refresh commands. 11. Issue a MRS command with LOW on A8 to initialize device operation. (i.e. to programm operating paramters with out resetting the DLL) 12. At least 200 clocks after step 8, execute OCD Calibration (Off Chip Driver impedance adjustment). If OCD calibration is not used, EMRS to EMR(1) to set OCD Default (A9=A8=A7=HIGH) followed by EMRS to EMR(1) OCD Calibration Mode Exit command (A9=A8=A7=LOW) must be issued with other parameters of EMR(1). 13. The DDR2 SDRAM is now read for normal operation. Example CK, CK CKE ODT "low" NOP Command tMRD tRP 400 ns PRE ALL CMD EMRS Extended Mode Register Set with DLL enable tRP tMRD MRS PRE ALL 1st Auto refresh min. 200 cycles to lock the DLL Mode Register Set with DLL reset tMRD tRFC tRFC 2nd Auto refresh MRS Follow OCD flowchart EMRS EMRS Follow OCD flowchart Register Definition Programming the Mode Register and Extended Mode Registers For application flexibility, burst length, burst type, CAS latency, DLL reset function, write recovery time (WR) are user defined variables and must be programmed with a Mode Register Set (MRS) command. Additionally, DLL disable function, additive CAS latency, driver impedance, ODT (On Die Termination), single-ended strobe and OCD (off chip driver impedance adjustment) are also user defined variables and must be programmed with an Extended Mode Register Set (EMRS) command. Contents of the Mode Register (MR) and Extended Mode Registers (EMR(#)) can be altered by re-executing the MRS and EMRS Commands. Even if the user chooses to modify only a subset of the MRS or EMR(#) variables, all variables within the addressed register must be redefined when the MRS or EMRS commands are issued. MRS, EMRS and DLL Reset do not affect array contents, which means reinitializazion including those can be executed any time after power-up without affecting array contents. Mode Register (MR) The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It contorls CAS latency, burst length, burst sequence, test mode, DLL reset, WR and various vendor specific options to make DDR2 SDRAM useful for various applications. The default value of the mode register is not defined, therefore the mode register must be programmed durin initialization for proper operation. The mode register is written by asserting LOW on CS, RAS, CAS, WE, BA0 and BA1, while controlling the state of address pins A0 ~ A13. The DDR2 SDRAM should be in all bank precharged state with CKE already HIGH prior to writing into the mode register. The mode register set command cycle time (tMRD) is required to complete the write operation to the mode register. The mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharged state. The mode register is divided into various fields REV 1.0 04/2008 7 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die depending on functionality. Burst length is defined by A0 ~ A2 with options of 4 and 8 bit burst length. Burst address sequence type is defined by A3 and CAS latency is defined by A4 ~ A6. A7 is used for test mode and must be set to low for normal MRS operation. A8 is used for DLL reset. A9 ~ A11 are used for write recovery time (WR) definition for Auto-Precharge mode. DDR2 SDRAM mode register set (MRS) A d dress F iled B A 1 B A 0 A 12 A 11 A 10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 B ur st L e n gth M R S m ode BA1 BA0 M R S m o de A2 A1 A0 BL 0 1 0 4 0 1 1 8 0 0 MR 0 1 E M R (1 ) 1 0 E M R (2 ) A3 B urst T yp e 1 1 E M R (3 ) 0 S eq u en tial 1 In te rle av e B u rst T yp e A ctiv e p o w er d o w n ex it tim e A c tiv e p o w er do w n ex it tim e A12 0 F ast ex it (u se tX A R D ) 1 C A S L a te n c y A6 A5 A4 S lo w ex it (u se tX A R D S ) 0 0 0 R eserve d W rite re c o v e ry fo r a u to p re c h a rg e 0 0 1 R eserve d A 11 A10 W R (c ycles) 0 1 0 R eserve d A9 C A S L aten cy 0 0 0 R ese rv ed 0 1 1 3 0 0 1 2 1 0 0 4 0 1 0 3 1 0 1 5 0 1 1 4 1 1 0 R e serv ed 1 0 0 5 1 1 1 R eserve d 1 0 1 R ese rv ed 1 1 0 R ese rv ed 1 1 1 R ese rv ed M ode A7 M o de 0 N o rm al 1 TEST D L L R eset A8 D L L R eset 0 NO 1 YES REV 1.0 04/2008 8 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die EMR(1) Programming A ddress Filed *4 BA 1 BA 0 A 12 A 11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 DLL M R S m ode BA 1 BA 0 M R S m ode A0 D LL Enable 0 Enable 1 D isable 0 MR 0 1 E M R (1) 1 0 EM R(2) 1 1 EM R(3) 0 Full strength Q off 1 Reduced strength 0 D .I.C O utput D river A1 Im pedance Control A 12 Q off*3 0 O utput buffer enabled A6 A2 Rtt (N om inal) 1 O utput buffer disabled 0 0 O D T D isabled 0 1 75 ohm 1 0 150 ohm 1 1 50 ohm R tt DQS A 10 DQS 0 Enable 1 D isable A5 O C D Program A9 A8 A dditive Latency A dditive A4 A3 Latency 0 0 0 0 0 0 1 1 A7 O CD C alibration Program 0 1 0 2 0 1 1 3 0 0 0 O CD Calibration m ode exit; m aintain setting 0 0 1 D rive(1) 1 0 0 4 0 1 0 D rive(0) 1 0 1 5 1 0 0 Adjust m ode *1 1 1 0 R eserved 1 1 1 O CD C alibration default*2 1 1 1 Reserved *1 W hen A djust m ode is issued . A L from previously set value m ust be applied . *2 A fter setting to default, O CD calibration m ode needs to be exited by setting A 9~A 7 to 000. *3 O utput disabled - DQ s, D Q Ss, D Q Ss. This feature is used in conjunction w ith D IM M ID D m easurem ents w hen ID D Q is not desired to be included. *4 A 11 does not used on x16 configuration. REV 1.0 04/2008 9 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die DDR2 SDRAM extended mode register Set (EMR(#) EMR(1) The extended mode register(1) stores the data for enabling or disabling the DLL, output driver strength, additive latency, ODT, DQS disable, OCD program. The default value of the extended mode register(1) is not defined, therefore the extended mode register(1) must be programmed during initialization for proper operation. The extended mode register(1) is written by asserting LOW on CS, RAS, CAS, WE, BA1 and high on BA0, while controlling the state of the address pins. The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register(1). The mode register set command cycle time (tMRD) must be satisfied to complete the write operation to the extended mode register(1). Extended mode register(1) contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in precharge state. A0 is used for DLL enable or disable. A1 is used for enabling a half strength output driver. A3-A5 determine the additive latency, A7-A9 are used for OCD control, A10 is used for DQS disable. A2 and A6 are used for ODT setting. DLL Enable/Disable The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal operation after having the DLL disabled. The DLL is automatically disabled when entering Self-Refresh operation and is automatically re-enabled upon exit of Self-Refresh operation. Any time the DLL is enabled (and subsequently reset), 200 clock cycles must occur before a Read command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters. EMR(2) The Extended mode Register(2) controls refresh related features. The default value of extended mode register(2) is not defined; therefore, extended mode register(2) must be programmed during initialization for proper operation. The extended mode register(2) is written by asserting LOW on CS,RAS,CAS,WE, HIGH on BA1 and LOW on BA0, while controlloing the states of address pins A0~A13. The DDR2 SDRAM should be in all bank percharge with CKE already high prior to writing into the extended mode register(2). The mode register set command cycle time (tMRD) must be satisfied to complete the write operation to the extended mode register(2). Mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the percharge state. REV 1.0 04/2008 10 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die EMR(2) programming BA1 BA0 A12 A11 A10 0* 0 1 BA1 BA0 A9 A8 A7 A6 A7 A4 A3 A2 0* SRF MRS mode A5 A1 A0 PASR*** Address Field Extended Mode Register High Temperature Self-Refresh Rate Enable 0 0 MRS 0 Disable 0 1 EMR(1) 1 Enable** (85C Tcase 95C) 1 0 EMR(2) 1 1 EMR(3) A2 A1 A0 0 0 0 0 0 1 0 1 0 Quarter Array (BA[2:0]=000&001) 0 1 1 1/8th array (BA[2:0] = 000) 1 0 0 3 / 4 array (BA[2:0]=010,011,100,101,110, &111) 1 0 1 Half array (BA[2:0]=100, 101, 110, & 111) 1 1 0 Quarter array (BA[2:0]=110&111) 1 1 1 1/8th array (BA[2:0]=111) Partial Array Self Refresh Full array Half Array (BA[2:0]=000, 001, 010, &011) * The rest bits in EMRS(2) is reserved for future use and all bits in EMRS(2) except A0-A2,A7,BA0, and BA1 must be programmed to 0 when setting EMRS(2) during initialization. ** DDR2 SDRAM Module user can look at module SPD field Byte 49 bit [0]. *** If PASR(Partial Array Self Refresh) is enabled, data located in areas of the array beyond the spec. location will be lost if self refresh is entered. REV 1.0 04/2008 11 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Off-Chip Driver (OCD) Impedance Adjustment DDR2 SDRAM supports driver calibration feature and the flow chart below is an example of the sequence. Every calibration mode command should be followed by "OCD calibration mode exit" before any other command being issued. MRS should be set before entering OCD impedance adjustment and ODT (On Die Termination) should be carefully controlled depending on system environment. MRS should be set before entering OCD impedance adjustment and ODT should be carefully controlled depending on system environment Start EMRS: OCD calibration mode exit EMRS: Drive (1) EMRS: Drive(0) DQ & DQS High; DQSLow DQ & DQS Low; DQS High AL L OK ALL OK Test Test Need Calibration Need Calibration EMRS: OCD calibration mode exit EMRS: OCD calibration mode exit EMRS : EMRS : Enter Adjus t Mode Enter Adjust Mode BL=4 cod e inpu t to all DQs BL =4 code input to all DQs Inc, Dec, or NOP Inc, Dec, or NOP EMRS: OCD calibration mode exit EMRS: OCD calibration mode exit EMRS: OCD calibration mode exit End REV 1.0 04/2008 12 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Extended Mode Register Set for OCD impedance adjustment OCD impedance adjustment can be done using the following EMR(1) mode. In drive mode all outputs are driven out by DDR2 SDRAM operation. In Drive(1) mode, all DQ, UDQS, LDQS signals are driven high and all UDQS, LDQS signals are driven low. In Drive(0) mode, all DQ, UDQS, LDQS signals are driven low and all UDQS, LDQS signals are driven high. In adjust mode, BL = 4 of operation code data must be used. In case of OCD calibration default, output driver characteristics have a nominal impedance value of 18 Ohms during nominal temperature and voltage conditions. Output driver characteristics for OCD calibration default are specified in the following table. OCD applies only to normal full strength output drive setting defined by EMR(1) and if half strength is set, OCD default driver characteristics are not applicable. When OCD calibration adjust mode is used, OCD default output driver characteristics are not applicable. After OCD calibration is completed or driver strength is set to default, subsequent EMR(1) commands not intended to adjust OCD characteristics must specify A7~A9 as '000' in order to maintain the default or calibrated value. Off- Chip-Driver program A9 0 0 0 1 1 A8 0 0 1 0 1 A7 0 1 0 0 1 Operation OCD calibration mode exit Drive(1) DQ, UDQS, LDQS high and UDQS, LDQS low Drive(0) DQ, UDQS, LDQS low and UDQS, LDQS high Adjust mode OCD calibration default OCD impedance adjust To adjust output driver impedance, controllers must issue the ADJUST EMR(1) command along with a 4 bit burst code to DDR2 SDRAM as in the following table. For this operation, Burst Length has to be set to BL = 4 via MRS command before activating OCD and controllers must drive the burst code to all DQs at the same time. DT0 is the table means all DQ bits at bit time 0, DT1 at bit time 1, and so forth. The driver output impedance is adjusted for all DDR2 SDRAM DQs simultaneously and after OCD calibration, all DQs of a given DDR2 SDRAM will be adjusted to the same driver strength setting. The maximum step count for adjustment can be up to 16 and when the limit is reached, further increment or decrement code has no effect. The default setting may be any step within the maximum step count range. When Adjust mode command is issued, AL from previously set value must be applied. Off- Chip-Driver Adjust Program 4 bit burst code inputs to all DQs DT0 DT1 DT2 DT3 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 0 1 0 0 0 1 1 1 0 0 1 0 Other Combinations 0 1 0 0 0 1 0 1 0 Operation Pull-up driver strength NOP (no operation) Pull-down driver strength NOP (no operation) Increase by 1 step NOP Decrease by 1 step NOP NOP Increase by 1 step NOP Decrease by 1 step Increase by 1 step Increase by 1 step Decrease by 1 step Increase by 1 step Increase by 1 step Decrease by 1 step Decrease by 1 step Decrease by 1 step Reserved Reserved For proper operation of adjust mode, WL = RL - 1 = AL + CL -1 clocks and tDS / tDH should be met as the following timing diagram. Input data pattern for adjustment, DT0 - DT3 is fixed and not affected by MRS addressing mode (i.e. sequential or interleave). REV 1.0 04/2008 13 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die OCD Adjust Mode OCD calibration mode exit OCD adjust mode CK CK EMRS CMD NOP NOP NOP NOP DQS WL NOP EMRS NOP WR DQS tDS DQ tDH DT0 DT1 DT2 DT3 DM Drive Mode Drive mode, both Drive(1) and Drive(0), is used for controllers to measure DDR2 SDRAM Driver impedance before OCD impedance adjustment. In this mode, all outputs are driven out tOIT after "enter drive mode" command and all output drivers are turned-off tOIT after "OCD calibration mode exit" command as the following timing diagram. CK, CK CMD EMRS NOP NOP NOP NOP NOP NOP tOIT tOIT DQS_in EMRS DQS high & DQS low for Drive(1), DQS low & DQS high for Drive 0 DQS high for Drive(1) DQS high for Drive(0) DQ_in OCD calibration mode exit Enter Drive Mode REV 1.0 04/2008 14 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die On-Die Termination (ODT) ODT (On-Die Termination) is a feature that allows a DRAM to turn on/off termination resistance for each DQ, UDQS, UDQS, LDQS, LDQS, UDM and LDM signal via the ODT control pin. The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM controller to independently turn on/off termination resistance for any or all DRAM devices. The ODT function can be used for all active and standby modes. ODT is turned off and not supported in Self-Refresh mode. Funtional Prepresentation of ODT VDDQ VDDQ VDDQ sw1 sw2 sw3 Rval1 Rval2 Rval3 DRAM Input Buffer Input Pin Rval1 Rval2 Rval3 sw1 sw2 sw3 VSSQ VSSQ VSSQ Switch sw1, sw2, or sw3 is enabled by the ODT pin. Selection between sw1, sw2, or sw3 is determined by "Rtt (nominal)" in EMR. Termination included on all DQs, DM, UDQS, UDQS, LDQS, LDQS pins. REV 1.0 04/2008 15 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die ODT related timings MRS command to ODT update delay During normal operation the value of the effective termination resistance can be changed with an EMRS command. The update of the Rtt setting is done between tMOD, min and tMOD, max, and CKE must remain HIGH for the entire duration of tMOD window for proper operation. The timings are shown in the following timing diagram. EMRS CMD NOP NOP NOP NOP NOP CK, CK tIS CKE tMOD, max tAOFD Rtt tMOD, min Old setting Updating New setting EMRS command directed to EMR(1), which updates the information in EMR(1)[A6,A2], i.e. Rtt(Nominal) Setting in this diagram is the Register and I/O setting, not what is measured from outside. However, to prevent any impedance glitch on the channel, the following conditions must be met. - tAOFD must be met before issuing the EMRS command. - ODT must remain LOW for the entire duration of tMOD window, until tMOD ,max is met. Now the ODT is ready for normal operation with the new setting, and the ODT may be raised again to turned on the ODT. Following timing diagram shows the proper Rtt update procedure. ntire duration of tMOD window for proper operation. The timings are shown in the following timing diagram. EMRS CMD NOP NOP NOP NOP NOP CK, CK tIS CKE tAOND tMOD, max tAOFD Rtt Old setting New setting EMRS command directed to EMR(1), which updates the information in EMR(1)[A6,A2], i.e. Rtt(Nominal) Setting in this diagram is the Register and I/O setting, not what is measured from outside. REV 1.0 04/2008 16 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die ODT On/Off timings ODT timing for active/standby mode T-1 T-0 T-2 T-3 T-4 T-6 T-5 CK, CK tIS CKE tIS tIS ODT tAOND tAOFD(2. 5 tck) Internal Term Res. Rtt tAON, min tAOF, min tAON, max tAOF, max ODT Timing for Power-down mode T0 T1 T2 T3 T5 T4 T6 CK, CK CKE tIS ODT tIS tAOFPD,max tAOFPD,min DQ Rtt tAONPD,min tAONPD,max REV 1.0 04/2008 17 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Bank Activate Command The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock. The bank addresses BA0 ~ BA1 are used to select the desired bank. The row addresses A0 through A13 have to be applied. The Bank Activate command must be applied before any Read or Write operation can be executed. Immediately after the bank active command, the DDR2 SDRAM can accept a read or write command (with or without Auto-Precharge) on the following clock cycle. If a R/W command is issued to a bank that has not satisfied the tRCDmin specification, then additive latency must be programmed into the device to delay the R/W command which is internally issued to the device. The additive latency value must be chosen to assure tRCDmin is satisfied. Additive latencies of 0, 1, 2, 3, and 4 are supported. Once a bank has been activated it must be precharged before another Bank Activate command can be applied to the same bank. The bank active and precharge times are defined as tRAS and tRP, respectively. The minimum time interval between successive Bank Activate commands to the same bank is determined (tRC). The minimum time interval between Bank Active commands, to any other bank, is the Bank A to Bank B delay time (tRRD). In order to ensure that 4 bank devices do not exceed the instantaneous current supplying capability of 4 bank devices, certain restrictions on operation of the 4 bank devices must be observed. There are two rules. One for restricting the number of sequential ACTcommands that can be issued and another for allowing more time for RAS precharge for a Precharge All command. The rules are list as follow: * 4 bank device sequential Bank Activation Restriction: No more than 4 banks may be activated in a rolling tFAW window. Conveting to clocks is done by dividing tFAW by tCK and rounding up to next integer value. As an example of the rolling window, if (tFAW/tCK) rounds up to 10 clocks, and an activate command is issued in clock N, no more than three further activate commands may be issued in clock N+1 through N+9. * 4 bank device Precharge All Allowance: tRP for a Precharge All command for an 4 Bank device will equal to tRP+tCK, where tRP is the value for a single bank pre-charge. Bank Activate Command Cycle: tRCD = 3, AL = 2, tRP = 3, tRRD = 2, tCCD = 2 T0 T1 T2 T3 T4 Tn Tn+1 Tn+2 Tn+3 CK, CK Internal RAS-CAS delay tRCDmin. Address Bank A Row Addr. Bank A Col. Addr. Bank B Row Addr. Bank B Col. Addr. Bank A Addr. NOP Bank B Addr. Bank A Row Addr. Bank A to Bank B delay tRRD. additive latency AL=2 RAS-RAS delay tRRD. Command Bank A Activate Posted CAS Read A Bank B Activate Read A Begins Posted CAS Read B Bank A Precharge tRC Row Cycle Time (Bank A) 04/2008 Bank B Precharge Bank A Activate tRP Row Precharge Time (Bank A) tRAS Row Active Time (Bank A) REV 1.0 NOP ACT 18 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Read and Write Commands and Access Modes After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting RAS high, CS and CAS low at the clock's rising edge. WE must also be defined at this time to determine whether the access cycle is a read operation (WE high) or a write operation (WE low). The DDR2 SDRAM provides a fast column access operation. A single Read or Write Command will initiate a serial read or write operation on successive clock cycles. The boundary of the burst cycle is restricted to specific segments of the page length. A new burst access must not interrupt the previous 4 bit burst operation in case of BL = 4 setting. However, in case of BL=8 setting, two cases of interrupt by a new burst access are allowed, one reads interrupted by a read, the other writes interrupted by a write with 4 bit burst boundary respectively. The minimum CAS to CAS delay (tCCD) is a minimum of 2 clocks for read or write cycles. Posted CAS Posted CAS operation is supported to make command and data bus efficient for sustainable bandwidths in DDR2 SDRAM. In this operation, the DDR2 SDRAM allows a Read or Write command to be issued immediately after the RAS bank activate command (or any time during the RAS to CAS delay time, tRCD, period). The command is held for the time of the Additive Latency (AL) before it is issued inside the device. The Read Latency (RL) is the sum of AL and the CAS latency (CL). Therefore if a user chooses to issue a Read/Write command before the tRCDmin, then AL greater than 0 must be written into the EMR(1). The Write Latency (WL) is always defined as RL - 1 (Read Latency -1) where Read Latency is defined as the sum of Additive Latency plus CAS latency (RL=AL+CL). If a user chooses to issue a Read command after the tRCDmin period, the Read Latency is also defined as RL = AL + CL. Example of posted CAS operation: Read followed by a write to the same bank: AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL -1) = 4, BL = 4 -1 0 1 Activate Bank A Read Bank A 2 3 4 5 6 7 8 9 10 11 12 CK, CK CMD DQS, DQS Write Bank A AL = 2 WL = RL -1 = 4 CL = 3 >=tRCD RL = AL + CL = 5 DQ Dout0 Dout1 Dout2Dout3 Din0 Din1 Din2 Din3 PostCAS1 REV 1.0 04/2008 19 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Read followed by a write to the same bank: AL = 0, CL = 3, RL = (AL + CL) = 3, WL = (RL -1) = 2, BL = 4 -1 0 1 2 3 4 5 6 7 8 9 10 11 12 CK, CK AL=0 CMD Read Bank A Activate Bank A >=tRCD Write Bank A CL=3 WL = RL - 1 = 2 DQS, DQS DQ RL = AL + CL = 3 Dout0 Dout1 Dout2 Dout3 Din0 Din1 Din2 Din3 PostCAS5 REV 1.0 04/2008 20 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Burst Mode Operation Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). The parameters that define how the burst mode will operate are burst sequence and burst length. The DDR2 SDRAM supports 4 bit and 8 bit burst modes only. For 8 bit burst mode, full interleave address ordering is supported, however, sequential address ordering is nibble based for ease of implementation. The burst type, either sequential or interleaved, is programmable and defined by the address bit 3 (A3) of the MRS. Seamless burst read or write operations are supported. Interruption of a burst read or write operation is prohibited, when burst length = 4 is programmed. For burst interruption of a read or write burst when burst length = 8 is used, see the "Burst Interruption " section of this datasheet. A Burst Stop command is not supported on DDR2 SDRAM devices. Burst Length and Sequence Burst Length Starting Address (A2 A1 A0) Sequential Addressing (decimal) Interleave Addressing (decimal) x 00 0, 1, 2, 3 0, 1, 2, 3 x 01 1, 2, 3, 0 1, 0, 3, 2 x 10 2, 3, 0, 1 2, 3, 0, 1 x 11 3, 0, 1, 2 3, 2, 1, 0 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 011 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 111 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0 4 8 REV 1.0 04/2008 21 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Burst Read Command The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The delay from the start of the command until the data from the first cell appears on the outputs is equal to the value of the read latency (RL). The data strobe output (DQS) is driven low one clock cycle before valid data (DQ) is driven onto the data bus. The first bit of the burst is synchronized with the rising edge of the data strobe (DQS). Each subsequent data-out appears on the DQ pin in phase with the DQS signal in a source synchronous manner. The RL is equal to an additive latency (AL) plus CAS latency (CL). The CL is defined by the Mode Register Set (MRS). The AL is defined by the Extended Mode Register Set (EMR(1)) Basic Burst Read Timing t CH t CL t CK CLK CLK, CLK CLK t DQSCK t AC DQS DQS, DQS DQS t RPRE t RPST t LZ DQ Dout t DQSQmax t QH Dout t HZ Dout Dout t DQSQmax t QH DO-Read Examples: Burst Read Operation: RL = 5 (AL = 2, CL = 3, BL = 4) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD Post CAS READ A NOP NOP NOP NOP NOP NOP NOP NOP <= tDQSCK DQS, DQS AL = 2 DQ CL = 3 RL = 5 Dout A0 Dout A1 Dout A2 Dout A3 BRead523 REV 1.0 04/2008 22 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Burst Read Operation: RL = 3 (AL = 0, CL = 3, BL = 8) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD READ A NOP NOP NOP NOP NOP NOP NOP NOP <= tDQSCK DQS, DQS CL = 3 RL = 3 DQ's Dout A0 Dout A1 Dout A2 Dout A3 Dout A4 Dout A5 Dout A6 Dout A7 BRead303 Burst Read followed by Burst Write : RL = 5, WL = (RL-1) = 4, BL = 4 T0 T1 Tn-1 Tn Tn+1 Tn+2 Tn+3 Tn+4 Tn+5 CK, CK CMD Posted CAS READ A NOP NOP Posted CAS WRITE A NOP NOP NOP NOP NOP tRTW(Read to Write turn around time) DQS, DQS WL = RL - 1 = 4 RL = 5 DQ Dout A0 Dout A1 Dout A2 Dout A3 Din A0 Din A1 Din A2 Din A3 BRBW514 The minimum time from the burst read command to the burst write command is defined by a read-to-write-turnaround time(tRTW), which is 4 clocks in case of BL=4 operation, 6 clocks in case of BL=8 operation. REV 1.0 04/2008 23 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Seamless Burst Read Operation : RL = 5, AL = 2, CL = 3, BL = 4 T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD Post CAS READ A NOP Post CAS READ B NOP NOP NOP NOP NOP NOP DQS, DQS AL = 2 DQ CL = 3 RL = 5 Dout A0 Dout A1 Dout A2 Dout A3 Dout B0 Dout B1 Dout B2 Dout B3 SBR523 The seamless burst read operation is supported by enabling a read command at every other clocks for BL=4 operation, and every 4 clock for BL=8 operation. This operation is allowed regardless of same or different banks as long as the banks are activated. REV 1.0 04/2008 24 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Burst Write Command The Burst Write command is initiated by having CS, CAS and WE low while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. Write latency (WL) is defined by a read latency (RL) minus one and is equal to (AL + CL -1). A data strobe signal (DQS) has to be driven low (preamble) a time tWPRE prior to the WL. The first data bit of the burst cycle must be applied to the DQ pins at the first rising edge of the DQS following the preamble. The tDQSS specification must be satisfied for write cycles. The subsequent burst bit data are issued on successive edges of the DQS until the burst length is completed, which is 4 or 8 bit burst. When the burst has finished, any additional data supplied to the DQ pins will be ignored. The DQ signal is ignored after the burst write operation is complete. The time from the completion of the burst write to bank precharge is named "write recovery time" (WR) . DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS "Enable DQS" mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timing are measured is mode dependent. Basic Burst Write Timing t DQSH t DQSL DQS DQS, DQS DQS t WPST t WPRE Din Din Din Din t DS t DH Example:. Burst Write Operation : RL = 5 (AL = 2, CL = 3), WL = 4, BL = 4 T0 T1 T2 T3 T4 T5 T6 T7 T9 CK, CK CMD Post CAS WRITE A NOP NOP NOP NOP NOP <= tDQSS DQS, DQS REV 1.0 04/2008 NOP Precharge Completion of the Burst Write tWR WL = RL-1 = 4 DQ NOP DIN A0 DIN A1 DIN A2 DIN A3 25 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Burst Write Operation : RL = 3 (AL = 0, CL = 3), WL = 2, BL = 4 T0 T1 T2 T3 T4 T5 T6 T7 T9 CK, CK CMD Post CAS WRITE A NOP NOP NOP NOP NOP Bank A Activate Completion of the Burst Write <= tDQSS DQS, DQS tRP tWR WL = RL-1 = 2 DQ Precharge NOP DIN A0 DIN A1 DIN A2 DIN A3 BW322 Burst Write followed by Burst Read : RL = 5 (AL = 2, CL = 3), WL = 4, tWTR = 2, BL = 4 T0 T1 T2 T3 T4 T5 T6 T7 T9 T8 CK, CK Write to Read = (CL - 1)+ BL/2 +tWTR(2) = 6 CMD NOP NOP NOP NOP Post CAS READ A NOP NOP NOP NOP DQS, DQS AL=2 tWTR WL = RL - 1 = 4 DQ CL=3 DIN A0 DIN A1 DIN A2 DIN A3 RL=5 BWBR The minimum number of clocks from the burst write command to the burst read command is (CL - 1) +BL/2 + tWTR where tWTR is the write-to-read turn-around time tWTR expressed in clock cycles. The tWTR is not a write recovery time (tWR) but the time required to transfer 4 bit write data from the input buffer into sense amplifiers in the array. REV 1.0 04/2008 26 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Seamless Burst Write Operation : RL = 5, WL = 4, BL = 4 T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD Post CAS WRITE A NOP Post CAS WRITE B NOP NOP NOP NOP NOP NOP DQS, DQS WL = RL - 1 = 4 DQ DIN A0 DIN A1 DIN A2 DIN A3 DIN B0 DIN B1 DIN B2 DIN B3 SBR The seamless burst write operation is supported by enabling a write command every BL / 2 number of clocks. This operation is allowed regardless of same or different banks as long as the banks are activated. REV 1.0 04/2008 27 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Write Data Mask One write data mask input (DM) pin for each 8 data bits (DQ) will be supported on DDR2 SDRAMs, consistent with the implementation on DDR SDRAMs. It has identical timings on write operations as the data bits, and though used in a uni-directional manner, is internally loaded identically to data bits to insure matched system timing. DM of x16 bit organization is not used during read cycles. Write Data Mask Timing t DQSH t DQSL DQS DQS, DQS DQS t WPST t WPRE DQ Din Din t DS Din Din t DH DM don't care Burst Write Operation with Data Mask : RL = 3 (AL = 0, CL = 3), WL = 2, tWR = 3 , BL = 4 T0 T1 T2 T3 T4 T5 T6 T7 T9 CK, CK CMD WRITE A NOP NOP NOP NOP NOP NOP Precharge Bank A Activate <= tDQSS DQS, DQS WL = RL-1 = 2 DQ tWR tRP DIN A0 DIN A1 DIN A2 DIN A3 DM DM REV 1.0 04/2008 28 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Burst Interruption Interruption of a read or write burst is prohibited for burst length of 4 and only allowed for burst length of 8 under the following conditions: 1. A Read Burst of 8 can only be interrupted by another Read command. Read burst interruption by a Write or Precharge Command is prohibited. 2. A Write Burst of 8 can only be interrupted by another Write command. Write burst interruption by a Read or Precharge Command is prohibited. 3. Read burst interrupt must occur exactly two clocks after the previous Read command. Any other Read burst interrupt timings are prohibited. 4. Write burst interrupt must occur exactly two clocks after the previous Write command. Any other Read burst interrupt timings are prohibited. 5. Read or Write burst interruption is allowed to any bank inside the DDR2 SDRAM. 6. Read or Write burst with Auto-Precharge enabled is not allowed to be interrupted. 7. Read burst interruption is allowed by a Read with Auto-Precharge command. 8. Write burst interruption is allowed by a Write with Auto-Precharge command. 9. All command timings are referenced to burst length set in the mode register. They are not referenced to the actual burst. For example, Minimum Read to Precharge timing is AL + BL/2 where BL is the burst length set in the mode register and not the actual burst (which is shorter because of interrupt). Minimum Write to Precharge timing is WL + BL/ 2 + tWR, where tWR starts with the rising clock after the un-interrupted burst end and not form the end of the actual burst end. Examples: Read Burst Interrupt Timing Example : (CL = 3, AL = 0, RL = 3, BL = 8) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD READ A NOP READ B NOP NOP NOP NOP NOP NOP DQS, DQS DQ Dout A0 Dout A1 Dout A2 Dout A3 Dout B0 Dout B1 Dout B2 Dout B3 Dout B4 Dout B5 Dout B6 D RBI REV 1.0 04/2008 29 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Write Burst Interrupt Timing Example : ( CL = 3, AL = 0, WL = 2, BL = 8) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD NOP WRITE A NOP NOP NOP WRITE B NOP NOP NOP DQS, DQS DQ Din A0 Din A1 Din A2 Din A3 Din B0 Din B1 Din B2 Din B3 Dout B4 Din B5 Din B6 Din B7 WBI REV 1.0 04/2008 30 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Precharge Command The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is triggered when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The Pre-charge Command can be used to precharge each bank independently or all banks simultaneously. Three address bits A10, BA0, BA1 are used to define which bank to precharge when the command is issued. Bank Selection for Precharge by Address Bit A10 BA1 BA0 Precharge Bank(s) LOW LOW LOW Bank 0 only LOW LOW HIGH Bank 1 only LOW HIGH LOW Bank 2 only LOW HIGH HIGH Bank 3 only LOW LOW LOW Bank 4 only LOW LOW HIGH Bank 5 only LOW HIGH LOW Bank 6 only LOW HIGH HIGH Bank 7 only HIGH Don't Care Don't Care all banks Burst Read Operation Followed by a Precharge Minimum Read to Precharge command spacing to the same bank = AL + BL/2 + max(RTP,2) - 2 clocks. For the earliest possible precharge, the Precharge command may be issued on the rising edge which is "Additive Latency (AL) + BL/2 clocks" after a Read Command, as long as the minimum tRAS timing is satisfied. The minimum Read to Precharge spacing has also to satisfy a minimum analog time from the rising clock edge that initiates the last 4-bit prefetch of a Read to Precharge command. This time is call tRTP (Read to Precharge). For BL=4 this is the time from the actual read ( AL after the Read command) to Precharge command. For BL=8 this is the time from AL + 2 clocks after the Read to the Precharge command. REV 1.0 04/2008 31 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Examples: Burst Read Operation Followed by Precharge: RL = 4 (AL = 1, CL = 3), BL = 4, tRTP <= 2 clocks T0 T1 T2 T3 NOP NOP Precharge T4 T5 T6 T7 T8 CK, CK CMD Post CAS READ A NOP NOP AL + BL/2 clks NOP Bank A Activate NOP >=tRP DQS, DQS AL = 1 CL = 3 RL = 4 DQ Dout A0 >=tRAS Dout A1 Dout A2 Dout A3 CL = 3 >=tRC >=tRTP Burst Read Operation Followed by Precharge: RL = 4 (AL = 1, CL = 3), BL = 8, tRTP <= 2 clocks T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD Post CAS READ A NOP NOP NOP NOP Precharge NOP NOP NOP AL + BL/2 clks DQS, DQS AL = 1 CL = 3 RL = 4 DQ Dout A0 >=tRAS Dout A1 Dout A2 Dout A3 Dout A4 Dout A5 Dout A6 Dout A7 CL = 3 >=tRC >=tRTP first 4-bit prefetch REV 1.0 04/2008 BR-P413(8) second 4-bit prefetch 32 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Burst Read Operation Followed by Precharge: RL = 5 (AL = 2, CL = 3), BL = 4, tRTP <= 2 clocks T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD Post CAS READ A NOP NOP NOP NOP Precharge AL + BL/2 clks NOP Bank A Activate NOP >=tRP DQS, DQS CL = 3 AL = 2 RL = 5 DQ Dout A0 >=tRAS Dout A1 Dout A2 Dout A3 CL = 3 >=tRC >=tRTP BR-P523 Burst Read Operation Followed by Precharge: RL = 6, (AL = 2, CL = 4), BL = 4, tRTP <= 2 clocks T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD Post CAS READ A NOP NOP NOP Precharge A AL + BL/2 clocks NOP NOP Bank A Activate NOP >=tRP DQS, DQS AL = 2 CL = 4 DQ RL = 6 Dout A0 >=tRAS Dout A1 Dout A2 Dout A3 CL = 4 >=tRC >=tRTP REV 1.0 04/2008 BR-P624 33 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Burst Read Operation Followed by Precharge: RL = 4, (AL = 0, CL = 4), BL = 8, tRTP > 2 clocks T0 T1 T2 T3 T4 T5 T6 NOP NOP Precharge T7 T8 CK, CK CMD READ A NOP NOP NOP NOP AL + BL/2 clks + 1 Bank A Activate >=tRP DQS, DQS CL = 4 RL = 4 DQ Dout A0 Dout A1 Dout A2 Dout A3 Dout A4 Dout A5 Dout A6 Dout A7 >=tRAS >=tRTP first 4-bit prefetch REV 1.0 04/2008 BR-P404(8) second 4-bit prefetch 34 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Burst Write followed by Precharge Minimum Write to Precharge command spacing to the same bank = WL + BL/2 + tWR. For write cycles, a delay must be satisfied from the completion of the last burst write cycle until the Precharge command can be issued. This delay is known as a write recovery time (tWR) referenced from the completion of the burst write to the Precharge command. No Precharge command should be issued prior to the tWR delay, as DDR2 SDRAM does not support any burst interrupt by a Precharge command. tWR is an analog timing parameter (see the AC table in this datasheet) and is not the programmed value for tWR in the MRS. Examples: Burst Write followed by Precharge : WL = (RL - 1) = 3, BL = 4, tWR = 3 T 0 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 CK, CK CMD Post CAS WRITE A NOP NOP NOP NOP NOP NOP NOP Precharge A Completion of the Burst Write DQS, DQS >=tWR WL = 3 DIN A0 DQ DIN A1 DIN A2 DIN A3 BW-P3 Burst Write followed by Precharge : WL = (RL - 1) = 4, BL = 4, tWR = 3 T0 T1 T2 T3 T4 T5 T6 T7 T9 CK, CK CMD Post CAS WRITE A NOP NOP NOP NOP NOP NOP Precharge A Completion of the Burst Write DQS, DQS tWR WL = 4 DQ NOP DIN A0 DIN A1 DIN A2 DIN A3 BW-P4 REV 1.0 04/2008 35 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Auto-Precharge Operation Before a new row in an active bank can be opened, the active bank must be precharged using either the Pre-charge Command or the Auto-Precharge function. When a Read or a Write Command is given to the DDR2 SDRAM, the CAS timing accepts one extra address, column address A10, to allow the active bank to auto-matically begin precharge at the earliest possible moment during the burst read or write cycle. If A10 is low when the Read or Write Command is issued, then normal Read or Write burst operation is executed and the bank remains active at the completion of the burst sequence. If A10 is high when the Read or Write Com-mand is issued, then the Auto-Precharge function is enabled. During Auto-Precharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge internally on the rising edge which is CAS Latency (CL) clock cycles before the end of the read burst. Auto-Precharge is also implemented for Write Commands.The precharge operation engaged by the Auto-Precharge command will not begin until the last data of the write burst sequence is properly stored in the memory array. This feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent upon CAS Latency) thus improving system performance for random data access. The RAS lockout circuit internally delays thepprecharge operation until the array restore operation has been completed so that the Auto-Precharge command may be issued with any read or write command. Burst Read with Auto-Precharge If A10 is high when a Read Command is issued, the Read with Auto-Precharge function is engaged. The DDR2 SDRAM starts an Auto-Precharge operation on the rising edge which is (AL + BL/2) cycles later from the Read with AP command if tRAS(min) and tRTP are satisfied. If tRAS(min) is not satisfied at the edge, the start point of Auto-Precharge operation will be delayed until tRAS(min) is satisfied. If tRTP(min) is not satisfied at the edge, the start point of Auto-Precharge operation will be delayed until tRTP(min) is satisfied. In case the internal precharge is pushed out by tRTP, tRP starts at the point where the internal precharge happens (not at the next rising clock edge after this event). So for BL = 4 the minimum time from Read with Auto-Precharge to the next Activate command becomes AL + tRTP + tRP. For BL = 8 the time from Read with Auto-Precharge to the next Activate command is AL + 2 + tRTP + tRP. Note that both parameters tRTP and tRP have to be rounded up to the next integer value. In any event internal precharge does not start earlier than two clocks after the last 4-bit prefetch. A new bank active (command) may be issued to the same bank if the following two conditions are satisfied simultaneously: (1) The RAS precharge time (tRP) has been satisfied from the clock at which the Auto-Precharge begins. (2) The RAS cycle time (tRC) from the previous bank activation has been satisfied. REV 1.0 04/2008 36 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Examples: Burst Read with Auto-Precharge followed by an activation to the Same Bank (tRC Limit) RL = 5 (AL = 2, CL = 3), BL = 4, tRTP <= 2 clocks T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD Posted CAS READ w/AP NOP NOP NOP NOP NOP NOP NOP Bank Activate A10 ="high" AL + BL/2 Auto-Precharge Begins DQS, DQS AL = 2 CL = 3 tRP RL = 5 DQ Dout A0 Dout A1 Dout A2 Dout A3 tRAS tRCmin. BR-AP5231 Burst Read with Auto-Precharge followed by an Activation to the Same Bank (tRAS Limit): RL = 5 ( AL = 2, CL = 3), BL = 4, tRTP <= 2 clocks T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD Posted CAS READ w/AP NOP NOP NOP NOP NOP Bank Activate NOP NOP A10 ="high" tRAS(min) Auto-Precharge Begins DQS, DQS AL = 2 CL = 3 tRP RL = 5 DQ Dout A0 Dout A1 Dout A2 Dout A3 tRC BR-AP5232 REV 1.0 04/2008 37 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Burst Read with Auto-Precharge followed by an Activation to the Same Bank: RL = 4 ( AL = 1, CL = 3), BL = 8, tRTP <= 2 clocks T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD Posted CAS READ w/AP NOP NOP NOP A10 ="high" NOP NOP NOP AL + BL/2 NOP Bank Activate tRP Auto-Precharge Begins DQS, DQS AL = 1 CL = 3 RL = 4 DQ Dout A0 Dout A1 Dout A2 Dout A3 Dout A4 Dout A5 Dout A6 Dout A7 >= tRTP BR-AP413(8)2 second 4-bit prefetch first 4-bit prefetch Burst Read with Auto-Precharge followed by an Activation to the Same Bank: RL = 4 ( AL = 1, CL = 3), BL = 4, tRTP > 2 clocks T0 T1 T2 T3 T4 T5 T6 T7 T8 CK, CK CMD Posted CAS READ w/AP A10 ="high" NOP NOP NOP NOP NOP NOP Bank Activate NOP AL + tRTP + tRP Auto-Precharge Begins DQS, DQS AL = 1 CL = 3 RL = 4 DQ Dout A0 Dout A1 Dout A2 Dout A3 tRP tRTP BR-AP4133 first 4-bit prefetch REV 1.0 04/2008 38 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Burst Write with Auto-Precharge If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is engaged. The DDR2 SDRAM automatically begins precharge operation after the completion of the write burst plus the write recovery time delay (WR), programmed in the MRS register, as long as tRAS is satisfied. The bank undergoing Auto-Precharge from the completion of the write burst may be reactivated if the following two conditions are satisfied. (1) The last data-in to bank activate delay time (tDAL = WR + tRP) has been satisfied. (2) The RAS cycle time (tRC) from the previous bank activation has been satisfied. Examples: Burst Write with Auto-Precharge (tRC Limit) : WL = 2, tDAL = 6 (WR = 3, tRP = 3) , BL = 4 T0 T1 T2 T3 T4 T5 T6 T7 CK, CK CMD WRITE w/AP NOP A10 ="high" NOP NOP NOP NOP NOP Completion of the Burst Write NOP Bank A Activate Auto-Precharge Begins DQS, DQS WR WL = RL-1 = 2 tRP tDAL DQ DIN A0 DIN A1 DIN A2 DIN A3 tRCmin. >=tRASmin. BW-AP223 REV 1.0 04/2008 39 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Burst Write with Auto-Precharge (tWR + tRP Limit) : WL = 4, tDAL = 6 (tWR = 3, tRP = 3), BL = 4 T 3 T 0 T 4 T 5 T 6 NOP NOP T 7 T 8 T 9 T12 CK, CK CMD Posted CAS WRITE w/AP NOP A10 ="high" NOP NOP NOP NOP Bank A Activate Completion of the Burst Write Auto-Precharge Begins DQS, DQS DIN A0 DQ tRP tWR WL = RL-1 = 4 DIN A1 DIN A2 tDAL DIN A3 >=tRC >=tRAS BW-AP423 Precharge & auto precharge clarification To Command Minimum Delay between "From command" to "to command" Units Note Precharge (to same Bank as Read) AL + BL/2 + max(RTP,2) - 2 tCK 1,2 Precharge All AL + BL/2 + max(RTP,2) - 2 tCK 1,2 Precharge ( to same Bank as Read wAP) AL + BL/2 + max(RTP,2) - 2 tCK 1,2 Precharge Al AL + BL/2 + max(RTP,2) - 2 tCK 1,2 Precharge (to same Bank as Write) WL + BL/2 + tWR tCK 2 Precharge Al WL + BL/2 + tWR tCK 2 Precharge (to same bank as Write w/AP) WL + BL/2 + WR tCK 2 Precharge Al WL + BL/2 + WR tCK 2 Precharge (to same bank as Precharge) 1 tCK 2 Precharge Al 1 tCK 2 Precharge 1 tCK 2 Precharge Al 1 tCK 2 From Command Read Read w/AP Write Write w/AP Precharge Precharge All Note: 1) RTP[cycles] = RU{tRTP(ns)/tCK(ns)}, where RI stands for round up. 2) For a given bank, the precharge period should be counted from the latest precharge command, either one bank precharge or precharge all, issued to that bank. The precharge period is satisfied after tRP or tRPa depending on the latest precharge command issued to that bank. REV 1.0 04/2008 40 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Refresh SDRAMs require a refresh of all rows in any rolling 64 ms interval. Each refresh is generated in one of two ways : by an explicit Auto-Refresh command, or by an internally timed event in Self-Refresh mode. Dividing the number of device rows into the rolling 64 ms interval defined the average refresh interval tREFI, which is a guideline to controlles for distributed refresh timing. For example, a 512Mbit DDR2 SDRAM has 8192 rows resulting in a tREFI of 7,8 s. Auto-Refresh Command Auto-Refresh is used during normal operation of the DDR2 SDRAMs. This command is nonpersistent, so it must be issued each time a refresh is required. The refresh addressing is generated by the internal refresh controller. This makes the address bits "Don't Care" during an Auto-Refresh command. The DDR2 SDRAM requires Auto-Refresh cycles at an average periodic interval of tREFI (maximum). When CS, RAS and CAS are held low and WE high at the rising edge of the clock, the chip enters the Auto-Refresh mode. All banks of the SDRAM must be precharged and idle for a minimum of the precharge time (tRP) before the Auto-Refresh Command can be applied. An internal address counter supplies the addresses during the refresh cycle. No control of the external address bus is required once this cycle has started. When the refresh cycle has completed, all banks of the SDRAM will be in the precharged (idle) state. A delay between the AutoRefresh Command and the next Activate Command or subsequent Auto-Refresh Command must be greater than or equal to the Auto-Refresh cycle time (tRFC). To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM, meaning that the maximum absolute interval between any Auto-Refresh command and the next Auto-Refresh command is 9 * tREFI. T0 T1 T2 T3 CK, CK "high" CKE CMD Precharge NOP > = t RFC > = t RFC > = t RP NOP AUTO REFRESH NOP AUTO REFRESH NOP NOP ANY AR REV 1.0 04/2008 41 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Self-Refresh Command The Self-Refresh command can be used to retain data, even if the rest of the system is powered down. When in the Self-Refresh mode, the DDR2 SDRAM retains data without external clocking. The DDR2 SDRAM device has a built-in timer to accommodate Self-Refresh operation. The Self-Refresh Command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock. ODT must be turned off before issuing Self Refresh command, by either driving ODT pin low or using EMR(1) command. Once the command is registered, CKE must be held low to keep the device in Self-Refresh mode. When the DDR2 SDRAM has entered Self-Refresh mode all of the external control signals, except CKE, are disabled. The clock is internally disabled during Self-Refresh Operation to save power. The user may change the external clock frequency or halt the external clock one clock after Self-Refresh entry is registered, however, the clock must be restarted and stable before the device can exit Self-Refresh operation. Once Self-Refresh Exit command is registered, a delay equal or longer than the tXSNR or tXSRD must be satisfied before a valid command can be issued to the device. CKE must remain high for the entire Self-Refresh exit period (tXSNR or tXSRD) for proper operation. NOP or DESELECT commands must be registered on each positive clock edge during the Self-Refresh exit interval. Since the ODT function is not supported during Self-Refresh operation, ODT has to be turned off tAOFD before entering Self-Refresh Mode and can be turned on again when the tXSRD timing is satisfied. T0 T1 T2 T3 T4 T5 Tm Tn Tr CK/CK tRP* tis tis >=tXSRD CKE tis tAOFD >= tXSNR ODT CMD Self Refresh Entry NOP CK/CK may be halted Non-Read Command Read Command CK/CK must be stable * = Device must be in the "All banks idle" state to entering Self Refresh mode. ODT must be turned off prior to entering Self Refresh mode. tXSRD (>=200 tCK) has to be satisfied for a Read or a Read with Auto-Precharge command. tXSNR has to be satisfied for any command except a Read or a Read with Auto-Precharge command, where tXSNR is defined as tRFC + 10ns. The miminum CKE low time is defined by the tCKEmin. timing parameter. Since CKE is an SSTL input, VREF must be maintained during Self Refresh. REV 1.0 04/2008 42 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Power-Down Power-down is synchronously entered when CKE is registered low, along with NOP or Deselect command. CKE is not allowed to go low while mode register or extended mode register command time, or read or write operation is in progress. CKE is allowed to go low while any other operation such as row activation, Precharge, Auto-Precharge or Auto-Refresh is in progress, but power-down IDD specification will not be applied until finishing those operations. The DLL should be in a locked state when power-down is entered. Otherwise DLL should be reset after exiting power-down mode for proper read operation. If power-down occurs when all banks are precharged, this mode is referred to as Precharge Power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as Active Power-down. For Active Power-down two different power saving modes can be selected within the MRS register, address bit A12. When A12 is set to "low" this mode is referred as "standard active power-down mode" and a fast power-down exit timing defined by the tXARD timing parameter can be used. When A12 is set to "high" this mode is referred as a power saving "low power active power-down mode". This mode takes longer to exit from the power-down mode and the tXARDS timing parameter has to be satisfied. Entering power-down deactivates the input and output buffers, excluding CK, CK, ODT and CKE. Also the DLL is disabled upon entering Precharge Power-down or slow exit active power-down, but the DLL is kept enabled during fast exit active powerdown. In power-down mode, CKE low and a stable clock signal must be maintained at the inputs of the DDR2 SDRAM, and all other input signals are "Don't Care". Power-down duration is limited by 9 times tREFI of the device. The power-down state is synchronously exited when CKE is registered high (along with a NOP or Deselect command). A valid, executable command can be applied with power-down exit latency, tXP, tXARD or tXARDS, after CKE goes high. Power-down exit latencies are defined in the AC spec table of this data sheet. Power-Down Entry Active Power-down mode can be entered after an activate command. Precharge Power-down mode can be entered after a precharge, Precharge-All or internal precharge command. It is also allowed to enter power-mode after an Auto-Refresh command or MRS / EMR(1) command when tMRD is satisfied. Active Power-down mode entry is prohibited as long as a Read Burst is in progress, meaning CKE should be kept high until the burst operation is finished. Therefore Active Power-Down mode entry after a Read or Read with Auto-Precharge command is allowed after RL + BL/2 is satisfied. Active Power-down mode entry is prohibited as long as a Write Burst and the internal write recovery is in progress. In case of a write command, active power-down mode entry is allowed when WL + BL/2 + tWTR is satisfied. In case of a write command with Auto-Precharge, Power-down mode entry is allowed after the internal precharge command has been executed, which is WL + BL/2 + WR starting from the write with Auto-Precharge command. In case the DDR2 SDRAM enters the Precharge Power-down mode. REV 1.0 04/2008 43 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Examples: Active Power-Down Mode Entry and Exit after an Activate Command T0 T1 T2 Tn Tn+1 Tn+2 CK, CK CMD NOP Activate NOP Valid Command NOP NOP NOP tIS CKE tIS tXARD or tXARDS *) Act.PD 0 Active Power-Down Exit Active Power-Down Entry Note: Active Power-Down mode exit timing tXARD ("fast exit") or tXARDS ("slow exit") depends on the programmed state in the MRS, address bit A12. Active Power-Down Mode Entry and Exit after a Read Burst: RL = 4 (AL = 1, CL =3), BL = 4 T0 T1 T2 T3 T4 T5 T6 T7 Tn T8 Tn+1 Tn+2 CK, CK CMD READ READ w/AP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP Valid Command tIS CKE RL + BL/2 tIS DQS, DQS AL = 1 DQ tXARD or tXARDS *) CL = 3 RL = 4 Dout A0 Dout A1 Dout A2 Dout A3 Active Power-Down Entry Active Power-Down Exit Act.PD 1 Note: Active Power-Down mode exit timing tXARD ("fast exit") or tXARDS ("slow exit") depends on the programmed state in the MRS, address bit A12. REV 1.0 04/2008 44 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Active Power-Down Mode Entry and Exit after a Write Burst: WL = 2, tWTR = 2, BL = 4 T0 T1 T2 T3 T4 T5 T6 Tn T7 Tn+1 Tn+2 CK, CK CMD WRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP Valid Command NOP tIS CKE WL + BL/2 + tWTR tIS DQS, DQS WL = RL - 1 = 2 tWTR DIN A0 DQ DIN A1 DIN A2 tXARD or tXARDS *) DIN A3 Active Power-Down Entry Active Power-Down Exit Act.PD 2 Note: Active Power-Down mode exit timing tXARD ("fast exit") or tXARDS ("slow exit") depends on the programmed state in the MRS, address bit A12. Precharge Power Down Mode Entry and Exit T0 T1 T2 T3 Tn Tn+1 Tn+2 CK, CK CMD Precharge *) NOP NOP NOP NOP NOP NOP Valid Command NOP tIS CKE tIS tXP tRP Precharge Power-Down Entry Precharge Power-Down Exit *) "Precharge" may be an external command or an internal precharge following Write with AP. REV 1.0 04/2008 PrePD 45 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die No Operation Command The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state. The purpose of the No Operation Command is to prevent the SDRAM from registering any unwanted commands between operations. A No Operation Command is registered when CS is low with RAS, CAS, and WE held high at the rising edge of the clock. A No Operation Command will not terminate a previous operation that is still executing, such as a burst read or write cycle. Deselect Command The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when CS is brought high, the RAS, CAS, and WE signals become don't care. Input Clock Frequency Change During operation the DRAM input clock frequency can be changed under the following conditions: a) During Self-Refresh operation b) DRAM is in Precharge Power-down mode and ODT is completely turned off. The DDR2-SDRAM has to be in Precharged Power-down mode and idle. ODT must be allready turned off and CKE must be at a logic "low" state. After a minimum of two clock cycles after tRP and tAOFD have been satisfied the input clock frequency can be changed. A stable new clock frequency has to be provided, before CKE can be changed to a "high" logic level again. After tXP has been satisfied a DLL RESET command via EMR(1) has to be issued. During the following DLL re-lock period of 200 clock cycles, ODT must remain off. After the DLL-re-lock period the DRAM is ready to operate with the new clock frequency. Example: Input frequency change during Precharge Power-Down mode T0 T1 T2 T3 T4 Tx Tx+1 Ty Ty+1 Ty+2 Tz Ty+3 K NOP NOP NOP NOP NOP NOP NOP NOP tRP tAOFD NOP tXP Minimum 2 clocks required before changing the frequency Frequency Change occurs here Stable new clock before power-down exit DLL RESET NOP Valid Command 200 clocks ODT is off during DLL RESET Frequ.Ch. REV 1.0 04/2008 46 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Asynchronous CKE Low Event DRAM requires CKE to be maintained "high" for all valid operations as defined in this data sheet. If CKE asynchronously drops "low" during any valid operation DRAM is not guaranteed to preserve the contents of the memory array. If this event occurs, the memory controller must satisfy a time delay ( tdelay ) before turning off the clocks. Stable clocks must exist at the input of DRAM before CKE is raised "high" again. The DRAM must be fully re-initialized as described the the initialization sequence (section 2.2.1, step 4 thru 13). DRAM is ready for normal operation after the initialization sequence. See AC timing parametric table for tdelay specification. Asynchronous CKE Low Event stable clocks CK, CK tdelay CKE CKE drops low due to an asynchronous reset event REV 1.0 04/2008 Clocks can be turned off after this point 47 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Truth Table Command Truth Table CKE Previous Cycle Current Cycle CS (Extended) Mode Register Set H H L L L L BA Auto-Refresh H H L L L H X X X X 1 Self-Refresh Entry H L L L L H X X X X 1,8 Self-Refresh Exit L H H X X X X X X X 1,7,8 Single Bank Precharge H H L L H L BA X L X 1,2 Precharge all Banks H H L L H L X X H X 1 Bank Activate H H L L H H BA Write H H L H L L BA Column L Column 1,2,3 Write with Auto-Precharge H H L H L L BA Column H Column 1,2,3 Read H H L H L H BA Column L Column 1,2,3 Read with Auto-Precharge H H L H L H BA Column H Column 1,2,3 No Operation H X L H H H X X X X 1 Device Deselect H X H X X X X X X X 1 Power Down Entry H X X X H L X X X X 1,4 L H H H H X X X X X X X 1,4 L H H H Power Down Exit L RAS CAS WE BA0 A13-A11 A10 BA1 Function H A9 - A0 OP Code Notes 1, 2 Row Address 1,2 1. All DDR2 SDRAM commands are defined by states of CS, WE, RAS, CAS, and CKE at the rising edge of the clock. 2. Bank addresses (BAx) determine which bank is to be operated upon. For (E)MRS BxA selects an (Extended) Mode Register. 3. Burst reads or writes at BL = 4 cannot be terminated. See sections "Reads interrupted by a Read" and "Writes interrupted by a Write" insection for details. 4. The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh requirements outlined . 5. The state of ODT does not affect the states decribed in this table. The ODT function is not available during Self Refresh. 6. "X" means "H or L (but a defined logic level)". 7. Self refresh exit is asynchronous. 8. Vref must be maintained during Self Refresh operation. REV 1.0 04/2008 48 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Clock Enable (CKE) Truth Table for Synchronous Transistions CKE Current State2 Command (N) 3 Previous Cycle 1 (N-1) Current Cycle 1 (N) RAS, CAS, WE, CS L L L Action (N) 3 Notes X Maintain Power-Down 11, 13, 15 H DESELECT or NOP Power-Down Exit 4, 8, 11, 13 L L X Maintain Self Refresh 11, 15, 16 L H DESELECT or NOP Self Refresh Exit 4, 5, 9, 16 H L DESELECT or NOP Active Power-Down Entry 4,8,10,11,13 H L DESELECT or NOP Precharge Power-Down Entry 4,8,10,11,13 AUTOREFRESH Self Refresh Entry 6, 9, 11,13 Power-Down Self Refresh Bank(s) Active All Banks Idle Any State other than listed above 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. H L H H Refer to the Command Truth Table 7 CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge. Current state is the state of the DDR2 SDRAM immediately prior to clock edge N. Command (N) is the command registered at clock edge N, and Action (N) is a result of Command (N). All states and sequences not shown are illegal or reserved unless explicitely described elsewhere in this document. On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occuring during the tXSNR period. Read commands may be issued only after tXSRD (200 clocks) is satisfied. Self Refresh mode can only be entered from the All Banks Idle state. Must be a legal command as defined in the Command Truth Table. Valid commands for Power-Down Entry and Exit are NOP and DESELECT only. Valid commands for Self Refresh Exit are NOP and DESELCT only. Power-Down and Self Refresh can not be entered while Read or Write operations, (Extended) mode Register operations, Precharge or Refresh operations are in progress. See section 2.8 "Power Down" and section 2.7.2 "Self Refresh Command" for a detailed list of restrictions. Minimum CKE high time is 3 clocks, minimum CKE low time is 3 clocks. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. The Power-Down Mode does not perform any refresh operations. The duration of Power-Down Mode is therefor limited by the refresh requirements. CKE must be maintained high while the device is in OCD calibration mode. "X" means "don't care (including floating around VREF)" in Self Refresh and Power Down. However ODT must be driven high or low in Power Down if the ODT function is enabled (Bit A2 or A6 set to "1" in EMR(1)). Vref must be maintained during Self Refresh operation. Data Mask (DM) Truth Table Name (Function) DM DQs Notes Write Enable L Valid 1 Write Inhibit H X 1 1. Used to mask write data; provided coincident with the corresponding data. REV 1.0 04/2008 49 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Operating Conditions Absolute Maximum Ratings Symbol Rating Units Notes Voltage on VDD pin relative to VSS -1.0 to +1.8 V 1,3 VDDQ Voltage on VDDQ pin relative to VSS -0.5 to +1.8 V 1,3 VDDL Voltage on VDDL pin relative to VSS -0.5 to +1.8 V 1,3 Voltage on any pin relative to VSS -0.5 to +1.8 V 1 Storage Temperature -55 to + 100 oC 1, 2 VDD VIN, VOUT TSTG Parameter 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. 3. When VDD, VDDQ, and VDDL are less than 500mV, Vref may be equal to or less than 300mV. DRAM Component Operating Temperature Range Symbol TOPER Parameter Operating Temperature Rating Units Notes 0 to 95 oC 1, 2 Note: 1. Operating temperature is the case surface temperature on the center/top side of the DRAM. 2. The operation temperature range are the temperature where all DRAM specification will be supported. Outside of this temperature range, even if it is still within the limit of stress condition, some deviation on portion of operation specification may be required. During operation, the DRAM case temperature must be maintained between 0-85 degree C under all other specification parameter. However, in some applications, it is desirable to operate the DRAM up to 95 degree C case temperature. Therefore, two spec may exist. Supporting 0-85C with full JEDEC AC & DC spec. This is the minimum requirements for all operating temperature options. This is an optional feature and not required. Supporting 0-85C and being able to extend to 95C with doubling auto-refresh command in frequency to a 32ms period (tRFI=3.9us) Currently the period Self-Refresh interval is hard coded within the DRAM to a vendor specific value. There is a migration plan to support higher temperature Self-Refresh entry via the control of EMR(2) bit A7. REV 1.0 04/2008 50 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die AC & DC Operating Conditions DC Operating Conditions Recommended DC Operating Conditions Rating Symbol Parameter Units Notes 1.625 V 1 1.5 1.625 V 5 1.425 1.5 1.625 V 1,5 Input Reference Voltage 0.49 * VDDQ 0.5 * VDDQ 0.51 * VDDQ V 2, 3 Termination Voltage VREF(DC) 35 VREF VREF(DC) + 35 mV 4 Min. Typ. Max. Supply Voltage 1.425 1.5 VDDDL Supply Voltage for DLL 1.425 VDDQ Supply Voltage for Output VREF VDD VTT 1. VDDQ tracks with VDD, VDDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDDL tied together. 2. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ. 3. Peak to peak ac noise on VREF may not exceed +/- 2% VREF (dc). 4. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in die dc level of VREF. 5. VDDQ tracks with VDD, VDDL tracks with VDD. AC parameters are measured with VDD, VDDQ, and VDDL tied together. ODT DC Electrical Characteristrics: Parameter / Condition Symbol min. nom. max. Units Notes Rtt eff. impedance value for EMR(1)(A6,A2)=0,1; 75 ohm Rtt1(eff) 60 80 98 ohms 1 Rtt eff. impedance value for EMR(1)(A6,A2)=0,1; 150 ohm Rtt2(eff) 120 160 195 ohms 1 Rtt eff. impedance value for EMR(1)(A6,A2)=1,1; 50 ohm Rtt3(eff) 40 55 65 ohms 1 Deviation of VM with respect to VDDQ / 2 delta VM -6 +6 % 2 1) Measurement Definition for Rtt(eff): Apply VIHac and VILac to test pin seperately, then measure current I(VIHac) and I(VILac) respectively. Rtt(eff) = (VIHac - VILac) /( I(VIHac) - I(VILac)) 2) Measurement Defintion for VM: Measure voltage (VM) at test pin (midpoint) with no load: delta VM =(( 2* VM / VDDQ) - 1 ) x 100% REV 1.0 04/2008 51 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die DC & AC Logic Input Levels DDR2 SDRAM pin timing are specified for either single ended or differential mode depending on the setting of the EMR(1) "Enable DQS" mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timing are measured is mode dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is guaranteed by design and characterisation. In single ended mode, the UDQS (LDQS) signals are internally disabled and don't care. Single-ended DC & AC Logic Input Levels DDR2-667 (-3C) Symbol DDR2-800 (-25C) Parameter VIH (dc) DC input logic high VIL (dc) DC input low VIH (ac) AC input logic high VIL (ac) AC input low Units Min. Max. Min. Max. VREF + 125 VDDQ * VREF + 125 VDDQ * mV -300 VREF - 125 -300 VREF - 125 mV VREF + 200 VDDQ * VREF + 200 VDDQ * mV -300 VREF - 200 -300 VREF - 200 mV * VDDQ + 250mV is permitted, provided that 1.8V is not exceeded. Single-ended AC Input Test Conditions Symbol VREF VSWING(max) Condition Input reference voltage Input signal maximum peak to peak swing Value Units Notes 0.5 * VDDQ V 1, 2 1.0 V 1, 2 1. This timing and slew rate definition is valid for all single-ended signls execpt tis, tih, tds, tdh. 2. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test. 3. The input signal minimum slew rate is to be maintained over the range from VIL(dc)max to VIH(ac)min for rising edges and the range from VIH(dc)min to VIL(ac)max for falling edges as shown in the below figure. 4. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the negative transitions. REV 1.0 04/2008 52 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Differential DC and AC Input and Output Logic Levels Symbol Parameter min. max. Units Notes VID(ac) AC differential input voltage 500 VDDQ * mV 1 VIX(ac) AC differential cross point input voltage 0.5 * VDDQ - 150 0.5 * VDDQ + 150 mV 2 VOX(ac) AC differential cross point output voltage 0.5 * VDDQ - 105 0.5 * VDDQ + 105 mV 3 Notes: 1) VID(ac) specifices the allowable DC execution of each input of differential pair such as CK, CK, LDQS, LDQS, UDQS, and UDQS. 2) VIX(ac) specifices the input differential voltage lVTR-VCPl required for switching, where VTR is the true input (such as CK, LDQS, or UDQS) level and VCP is the complementary input (such CK, LDQS, or UDQS ) level. The minimum value is equal to VIH(DC) - VIL(DC). 3) The typical value of VOX(AC) is expected to be about 0.5VDDQ of the transmitting device and VOX(AC) is expected to track variations in VDDQ. VOX(AC) indicates the voltage at which differential signals must cross. * VDDQ + 250mV is permitted, provided that 1.8V is not exceeded. VDDQ VTR Crossing Point VID VIX or VOX VCP VSSQ SSTL18_3 Output Buffer Levels Output DC Current Drive Symbol Value Units Notes IOH(dc) Output Minimum Source DC Current, nominal Parameter -13.4 mA 1, 2, 4 IOL(dc) Output Minimum Sink DC Current, nominal 13.4 mA 2, 3, 4 Note: 1. For IOH(DC); VDDQ = 1.425V, VOUT = 1.145V. (VOUT - VDDQ)/IOH must be less than 21 ohms for values of VOUT between VDDQ and VDDQ - 280mV. 2. For IOL(DC); VDDQ = 1.425V, VOUT = 280mV. VOUT /IOL must be less than 21 ohms for values of VOUT between 0V and 280mV. 3. The DC value of Vref applied to the receiving device is set to VTT. 4. The values of IOH(DC) and IOL(DC) are based on the conditions given in Note 1 and 2. they are used to test device drive current capability to ensure VIH(min) plus a noise margin and VIL(max) minus a noise margin are delivered to an SSTL_18 receiver. The actual current values are derived by shifting the desired driver operating point (see output IV curves) along a 21 ohms load line to define a convenient driver current for measurement. REV 1.0 04/2008 53 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die OCD Default Setting Table Description Pull-up / Pull down mismatch Output Impedance step size for OCD calibration Output Slew Rate min. nominal max. Unit See "Full Strength Pull-Down Driver Characteristics" 0 - 1.5 0.8 - 5.0 Notes Ohms 1,2 Ohms 1,2,3 V / ns 1,4,5 Note: 1. Absolute specifications: 0 C <= Tc <= 95 C; VDDQ=+1.525V+/-0.1V, VDD=+1.525V+/-0.1V. 2. Impedance measurement conditions for output source DC current: VDDQ=1.425V; VOUT =1.145V; (VOUTVDDQ)/IOH must be less than 23.4ohms for values of VOUT between VDDQ and VDDQ - 280mV. Impedance measurement condition for output sink DC current: VDDQ=1.425V; VOUT=280mV; VOUT/IOL must less than 23.4ohms for values of VOUT between 0V and 280mV. 3. Mismatch is absolute value between pull-up and pull-down; both are measured at the same temperature and voltage. 4. Output slew rate for falling and rising edges is measured between VTT -250mV and VTT+250mV for single ended signals. For differential signals (DQS, DQS), output slew rate is measured between DQS - DQS = 500mV and DQS - DQS = +500mV. Output slew rate is guranteed by design, but is not necessarily tested in the production. 5. The absolute value of the slew rate as measured from VIL(DC)max to VIH(DC)min is equal to or greater than the slew rate as measured from VIL(AC)max to VIH(AC)min. This is guranateed by design and characterization. REV 1.0 04/2008 54 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Input / Output Capacitance Symbol CCK CDCK CI DDR2-800 (-25C) Parameter Input capacitance, CK and CK Input capacitance delta, CK and CK Input capacitance, all other input-only pins DDR2-667 (-3C) Units min. max. min. max. 1.0 2.0 1.0 2.0 pF - 0.25 - 0.25 pF 1.0 1.75 1.0 2.0 pF - 0.25 - 0.25 pF CDI Input capacitance delta, all other input-only pins CIO Input/output capacitance, DQ, DM, UDQS, UDQS, LDQS, LDQS 2.5 3.5 2.5 3.5 pF CDIO Input/output capacitance delta, DQ, DM, UDQS, UDQS, LDQS, LDQS - 0.5 - 0.5 pF Power & Ground Clamp V-I Characteristics Power and Ground clamps are provided on address (A0~A13, BA0, BA1), RAS, CAS, CS, WE, CKE, and ODT pins. The V-I characterisitcs for pins with clamps is shown in the following table : Voltage across clamp (V) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 REV 1.0 04/2008 Minimum Power Clamp Current (mA) Minimum Ground Clamp Current (mA) 0 0 0 0 0 0 0 0 0.1 1.0 2.5 4.7 6.8 9.1 11.0 13.5 16.0 0 0 0 0 0 0 0 0 0.1 1.0 2.5 4.7 6.8 9.1 11.0 13.5 16.0 55 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die IIDD Specifications and Measurement Conditions IDD Specifications Symbol Parameter/Condition DDR2-800 DDR2-667 max. max. I/O Unit Notes IDD0 Operating Current x4/x8 x16 92 89 80 78 mA 1, 2 IDD1 Operating Current x4/x8 x16 82 105 71 92 mA 1, 2 all 6 6 mA 1, 2 IDD2N Precharge Standby Current x4/x8 x16 50 50 43 44 mA 1, 2 IDD2Q Precharge Quiet Standby Current: x4/x8 x16 38 39 34 35 mA 1, 2 MRS(12)=0 x4/x8 x16 23 21 21 19 mA 1, 2 MRS(12)=1 x4/x8 x16 10 7 9 7 mA 1, 2 IDD3N Active Standby Current x4/x8 x16 46 47 41 42 mA 1, 2 IDD4R Operating Current Burst Read x4/x8 x16 116 138 101 120 mA 1, 2 IDD4W Operating Current Burst Write x4/x8 x16 94 119 79 83 mA 1, 2 IDD5 Auto-Refresh Current (tRFC=tREFI) x4/x8 x16 8 8 8 7 mA 1, 2 IDD6 Self-Refresh Current for standard products all 6 6 mA 1, 2 IDD7 Operating Current x4/x8 x16 159 214 133 181 mA 1 IDD2P Precharge Power-Down Current Active PowerIDD3P Down Standby Current Note: 1. IDD specifications are tested after the device is properly initialized. IDD parameters are specified with ODT disabled. 2. Input slew rate = 1 V/ns. REV 1.0 04/2008 56 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die IDD Measurement Conditions Symbol Parameter/Condition IDD0 Operating Current - One bank Active - Precharge tCK =tCK(IDD).; tRC = tRC(IDD); tRAS = tRAS(IDD); CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are SWITCHING; Data bus inputs are SWITCHING; IDD1 Operating Current - One bank Active - Read - Precharge IOUT = 0 mA; BL = 4, tCK = tCK(IDD), AL=0; tCK=tCK(IDD); tRAS=tRASmin(IDD); tRCD = tRCDmin; CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING, Data pattern is same as IDD4W. IDD2P Precharge Power-Down Current: All banks idle; CKE is LOW; tCK = tCK(IDD); Other control and address inputs are STABLE, Data Bus inputs are FLOATING. IDD2N Precharge Standby Current: All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK(IDD).; Other control and address bus inputs are SWICHTING; Data bus inputs are SWITCHING. IDD2Q Precharge Quiet Standby Current:All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK(IDD)b; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING. IDD3P(0) Active Power-Down Current: All banks open; tCK = tCK(IDD).;CKE is LOW; Other control and address inputs are STABLE; Data Bus inputs are FLOATING. MRS A12 bit is set to "0"( Fast Power-down Exit); IDD3P(1) Active Power-Down Current: All banks open; tCK = tCK(IDD);CKE is LOW; Other control and address inputs are STABLE; Data Bus inputs are FLOATING. MRS A12 bit is set to "1"( Slow Power-down Exit); IDD3N Active Standby Current: All banks open; tCK = tCK(IDD); tRAS = tRASmax(IDD); tRP = tRP(IDD)., CKE is HIGH; CS is HIGH between valid commands; Other control and address inputs are SWITCHING; Data Bus inputs are SWITCHING. IDD4R Operating Current - Burst Read: All banks open; Continuous burst reads; IOUT=0mA; BL = 4; AL = 0, CL = CL(IDD); tCK = tCK(IDD); tRAS = tRAS(IDD), tRP = tRP(IDD), CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data pattern is same as IDD4W. IDD4W Operating Current - Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL(IDD); tCK = tCK(IDD); tRAS = tRAS(IDD), tRP = tRP(IDD);CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data Bus inputs are SWITCHING. IDD5B Burst Auto-Refresh Current: tCK = tCK(IDD); Refresh command every tRFC = tRFC(IDD) interval; CKE is HIGH, CS is HIGH between valid commands; Other control and adress inputs are SWITCHING; Data bus inputs are SWITCHING. IDD6 Self-Refresh Current: CKE <= 0.2V; CK and CK at 0V; Other control and address inputs are FLOATING; Data Bus inputs are FLOATING. IDD7 Operating Bank Interleave Read Current: 1. All bank interleaving reads; IOUT = 0 mA, BL =4, CL = CL(IDD), AL = tRCD(IDD) - 1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD); tRRD = tRRD(IDD); tRCD = 1*tCK(IDD), CKE = HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTS; Data pattern is same as IDD4R; All banks are being interleaved at minimum tRC(IDD) without violating tRRD(IDD) and tFAW(IDD) using a burst length of 4. Control and address bus inputs are STABLE during DESELECTs. Iout = 0mA 2. Timing pattern with 1KB page size: - DDR2 -667 : A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D Timing pattern with 2KB page size: - DDR2 -667 : A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D 3. Legend : A=Activate, RA=Read with Auto-Precharge, D=DESELECT 1. IDD specifications are tested after the device is properly initialized. 2. IDD parameters are specified with ODT disabled. 3. Data Bus consists of DQ, DM, DQS, DQS, LDQS, LDQS, UDQS and UDQS. IDD values must be met with all combinitions of EMRS bits 10 and 11. 4. Definitions for IDD : LOW is defined as VIN <= VILAC(max); HIGH is defined as VIN >= VIHAC(min.); STABLE is defined as inputs are stable at a HIGH or LOW level FLOATING is defined as inputs are VREF = VDDQ / 2 SWITCHING is defined as: Inputs are changing between HIGH and LOW every other clock (once per two clocks) for adress and control signals, and inputs changing between HIGH and LOW every other clock (once per two clocks) for DQ signals not including mask or strobes 5. Input slew rate is specified by AC Parametric Test Condition 6. For DDR2-667/800 testing; tCK in the Conditions should be interpreted as tCK(avg) REV 1.0 04/2008 57 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die IDD testing parameters DDR2-800 5-5-5 (-25C) Speed DDR2-667 5-5-5 (-3C) Unit CL(IDD) 5 5 tCK tRDC(IDD) 12.5 15 ns tRC(IDD) 57.5 60 ns tRRD(IDD)-1KB 7.5 7.5 ns tRRD(IDD)-2KB 10 10 ns tFAW(IDD)-1KB 35 37.5 ns tFAW(IDD)-2KB 45 50 ns ns tCK(IDD) 2.5 3 tRASmin(IDD) 45 45 ns tRASmax(IDD) 70000 70000 ns tRP(IDD) 12.5 15 ns tRFC(IDD) 105 105 ns Refresh parameters Parameter Symbol 512Mb Unit Auto-Refresh to Active / Auto-Refresh command period tRFC 105 ns Average periodic Refresh interval tREFI 0C<=Tcase<=85C 7.8 85C<Tcase<=95C 3.9 s DDR2 SDRAM standard speed bins and tCK/tCK(avg), tRCD, tRP, tRAS, and tRC for corresponding bin Speed bin CL - tRCD - tRP REV 1.0 04/2008 DDR2-800 5-5-5 (-25C) DDR2-667 5-5-5 (-3C) Unit Parameter min max min max tRCD 12.5 - 15 - ns ns tRP 12.5 - 15 - tRC 57.5 - 60 - ns tRAS 45 70000 45 70000 ns tCK(avg) @ CL=4 3.75 8 3.75 8 ns tCK(avg) @ CL=5 2.5 8 3 8 ns 58 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Electrical Characteristics & AC Timing - Absolute Specification Timing Parameter by Speed Grade Symbol Unit min max min max 0.48 0.52 0.48 0.52 tCK tCL(AVG) CK LOW pulse width 0.48 0.52 0.48 0.52 tCK tDQSS Write command to DQS associated clock edge DQS latching transition to associated clock edges RL-1 RL-1 tCK -0.25 +0.25 -0.25 +0.25 tCK tDSS DQS falling edge to CK setup time 0.2 - 0.2 - tCK tDSH DQS falling edge hold time from CK 0.2 - 0.2 - tCK tDQSL,H DQS input low (high) pulse width 0.35 - 0.35 - tCK tWPRE Write preamble 0.35 - 0.35 - tCK tWPST Write postamble 0.40 0.60 0.40 0.60 tCK tIS Address and control input setup time 175 - 200 - ps tIH Address and control input hold time 250 - 275 - ps tIPW Address and control input pulse width (each input) 0.6 - 0.6 - tCK tDS DQ and DM input setup time differential strobe 50 - 100 - ps tDH DQ and DM input hold time 125 - 175 - ps DQ and DM input pulse width (each input) 0.35 - 0.35 - tCK DQ output access time from CK / CK -400 +400 -450 +450 ps DQS output access time from CK / CK -350 350 -400 +400 ps - tACmax - tACmax ps tLZ(DQS) DQS(/DQS) low-impedence time from CK / CK tACmin tACmax tACmin tACmax ps tLZ(DQ) DQ low-impedence time from CK / CK 2tACmin tACmax 2tACmin tACmax ps tDQSQ DQS-DQ skew for DQS & associated DQ signals - 200 - 240 ps tDIPW tAC tDQSCK tHZ 04/2008 DDR2-667 (-3C) tCH(AVG) CK HIGH pulse width WL REV 1.0 DDR2-800 (-25C) Parameter differential strobe Data-out high-impedence time from CK / CK tHP Clock half pulse width min (tCL, tCH) - min (tCL, tCH) - ps tQHS Data hold skew factor - 300 - 340 ps tQH Data output hold time from DQS tHP-tQHS - tHP-tQHS - ps tRPRE Read preamble 0.9 1.1 0.9 1.1 tCK tRPST Read postamble 0.4 0.6 0.4 0.6 tCK tRRD Active bank A to Active bank B command period 10 - 10 - ns tFAW Four Activate Window 45 - 50 - ns tCCD CAS to CAS command delay 2 - 2 - tCK tWR Write recovery time 15 - 15 - ns tDAL Auto-Precharge write recovery + precharge time WR+tRP - WR+tRP - tCK 59 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Symbol min max min Unit max Internal Write to Read command delay 7.5 - 7.5 - ns tRTP Internal Read to Precharge command delay 7.5 - 7.5 - ns tCKE CKE minimum pulse width (HIGH and LOW pulse width) 3 - 3 - tCK tXSNR Exit Self-Refresh to non-Read command tRFC+10 - tRFC+10 - ns tXSRD Exit Self-Refresh to Read command 200 - 200 - tCK Exit precharge power-down to any non-read command 2 - 2 - tCK tXARD Exit active power down to read command 2 - 2 - tCK tXARDS Exit active power-down to Read command (slow exit, lower power) 8 - AL - 7 - AL - tCK tAOND ODT turn-on delay 2 2 2 2 tCK tAON tAONPD ODT turn-on t (max) t (max) tAC(min) AC tAC(min) AC +0.7 +0.7 ODT turn-on (Power-Down mode) tAC(min) 2tCK+tAC tAC(min) 2tCK+tAC ns +2 +2 (max)+1 (max)+1 ns tAOFD ODT turn-off delay tAOF ODT turn-off tAC(min) tAC(max) t (max) tAC(min) AC +0.6 +0.6 ns tAOFPD ODT turn-off (Power-Down mode) 2.5tCK+ 2.5tCK+ tAC(min) t (min) tAC(max) AC tAC(max) +2 +2 +1 +1 ns tANPD ODT to power down entry latency 3 tAXPD ODT power down exit latency 8 tMRD Mode register set command cycle time 2 - 2 - tCK tMOD MRS command to ODT update delay 0 12 0 12 ns tOIT OCD drive mode output delay 0 12 0 12 ns tIS+tCK +tIH - tIS+tCK +tIH - ns tDELAY 04/2008 Parameter DDR2-667 (-3C) tWTR tXP REV 1.0 DDR2-800 (-25C) 2.5 Minimum time clocks remain ON after CKE asynchronously drops LOW 2.5 - 2.5 3 2.5 - 8 tCK tCK tCK 60 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die General notes, which may apply for all AC parameters Genernal Note 1 : DDR2 SDRAM AC timing reference load The figure represents the timing reference load used in defining the relevant timing parameters of the device. It is not intended to either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions, generally a coaxial transmission line terminated at the tester electronics. VDDQ DUT DQ DQS DQS RDQS RDQS O u tp u t V T T = V D D Q /2 25ohm s T im in g re fe re n c e p o in t The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output timing reference voltage level for differential signals is the crosspoint of the true ( e.g. DQS) and the complement (e.g. DQS) signal. Gernal Note 2 : Slew Rate Measurement Levels Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for single ended signals. For differential signals (e.g. DQS / DQS) output slew rate is measured between DQS - DQS = - 500 mV and DQS - DQS = + 500 mV. Output slew rate is guaranteed by design, but is not necessarily tested on each device. VID is the magnitude of the difference between the input voltage on CK and the input voltage on CK, or between DQS and DQS for differential strobe. Input slew rate for single ended signals is measured from Vref(dc) to VIH(ac),min for rising edges from vref(dc) to VIL(ac),max for falling edges. For differential signals (eg. CK - CK) slew rate for rising edges is measured from CK - CK = -250mV to CK - CK =+500V (+250mV to -500mV for falling edges). Genernal Note 3 : DDR2 SDRAM output slew rate test load Output slew rate is characterized under the test conditions in below figure. VDDQ DUT DQ DQS DQS RDQS RDQS O u tput V T T = V D D Q /2 25ohm s T est po in t REV 1.0 04/2008 61 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Genernal Note 4 : Differential data strobe DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS "Enable DQS" mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is guaranteed by design and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied externally to VSS through a 20 ohms to 10K ohms resistor to insure proper operation. Genernal Note 5 : AC timings are for linear signal transitions. Genernal Note 6 : All voltages are referenced to VSS. Genernal Note 7 : These parameters guarantee device behavior, but they are not necessarily tested on each device. They may be guaranteed by device design or tester correlation. Genernal Note 8 : Tests for AC timing, IDD, and electrial (AC and DC) characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. REV 1.0 04/2008 62 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Input and Data Setup and Hold Time Timing Definition for Input Setup (tIS) and Hold Time (tIH) Address and control input setup time (tIS) is referenced from the input signal crossing at the VIH(ac) level for a rising signal and VIL(ac) for a falling signal applied to the device under test. Address and control input hold time (tIH) is referenced from the input signal crossing at the VIL(dc) level for a rising signal and VIH(dc) for a falling signal applied to the device under test CK CK t IS t t IH IS t IH VDDQ VIH(ac) min VIH(dc) min VREF VIL(dc) max VIL(ac) max VSS Timing Definition for Data Setup (tDS) and Hold Time (tDH) DQS Differential Input Waveform DQS Single-ended Input Waveform DQS V REF t DS t DH t t DS DH VDDQ VIH(ac) min VIH(dc) min VREF VIL(dc) max VIL(ac) max VSS 1. Data input setup time with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the VIH(ac) level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL(ac) level tothe differential data strobe crosspoint for a falling signal applied to the device under test. Input waveform timing with single-endeddata strobe enabled MR[bit10]=1, is referenced from the input signal crossing at the VIH(ac) level to the data strobe crossing Vref for a rising signal, and from the input signal crossing at the VIL(ac) level to the single-ended data strobe crossing Vref for a falling signal applied to the device under test. 2. Data input hold time with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the VIL(dc) level to the differential data strobe crosspoint for a rising signal and VIH(dc) to the differential data strobe crosspoint for a falling signal applied to the device under test. Input waveform timing with single-ended data strobe enabled MR[bit10]=1, is referenced from the input signal crossing at the VIL(dc) level to the single-ended data strobe crossing Vref for a rising signal and VIH(dc) to the single-ended data strobe crossing Vref for a falling signal applied to the device under test REV 1.0 04/2008 63 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Slew Rate Definition for Input and Data Setup and Hold Times Setup (tIS & tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIH(dc)min and the first crossing of VIH(ac)min. Setup (tIS & tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIL(dc)max and the first crossing of VIL(ac)max, (fig. A) If the actual signal is always earlier than the nominal slew rate line between shaded `dc to ac region', use nominal slew rate for derating value. If the actual signal is later than the nominal slew rate line anywhere between shaded `dc to ac region', the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value.(fig.B) Hold (tIH & tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the first crossing of Vref. Hold (tIH & tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(dc)min and the first crossing of Vref.(fig. A). If the actual signal is always later than the nominal slew rate line between shaded `dc to Vref region', use nominal slew rate for derating value. If the actual signal is earlier than the nominal slew rate line anywhere between shaded `dc to Vref region', the slew rate of a tangent line to the actual signal from the dc level to Vref level is used for derating value.(fig.B) t t S t H S t t H dc to ac region S t t H S t H VDDQ VDDQ VIH(ac) min VIH(ac) min dc to ac region VIH(dc) min VIH(dc) min dc to Vref region dc to Vref region VREF VREF dc to Vref region dc to Vref region VIL(dc) max dc to ac region Delta TFS Delta TRH Delta TRS Delta TFS VIH(dc)min - VIL(ac)min Setup Slew Rate = Delta TRS VREF - VIL(dc)max Hold Slew Rate = Delta TRH VIH(dc)min - VREF Hold Slew Rate = Delta TFH VIL(ac) max VIL(ac) max VSS VSS Delta TFS Delta TFH VIL(dc)max - VIL(ac)max Setup Slew Rate = falling signal rising signal rising signal falling signal 04/2008 Delta TRH Delta TRS Delta TFH tangent line [VIL(dc)max - VIL(ac)max] Setup Slew Rate = Delta TFS tangent line [VIH(dc)min - VIL(ac)min] Setup Slew Rate = Delta TRS tangent line [REF - VIL(dc)max] Hold Slew Rate = Hold Slew Rate = Delta TRH tangent line [VIH(dc)min - VREF] Fig. A REV 1.0 VIL(dc) max dc to ac region Delta TFH falling signal rising signal rising signal falling signal Fig. B 64 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Input Setup (tIS) and Hold (tIH) Time DeratingTable CK, CK Differential Slew Rate (DDR2-667/800) Command / Address Slew rate 2.0 V/ns 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.25 0.2 0.15 0.1 1.5 V/ns 1.0 V/ns D tIS D tIH D tIS D tIH D tIS D tIH +15+143 +133 +120 +100 +67 0 -5 -13 -22 -34 -60 -100 -168 -200 -325 -517 -1000 +94 +89 +83 +75 +45 +21 0 -14 -31 -54 -83 -125 -188 -292 -375 -500 -708 -1125 +180 +173 +163 +150 +!60 +97 +30 +25 +17 +8 -4 -30 -70 -138 -170 -295 -487 -970 +124 +119 +113 +!05 +75 +51 +30 +16 -1 -24 -53 -95 -158 -262 -345 -470 -678 -1095 +210 +203 +193 +180 +160 +127 +60 +55 +47 +38 +36 0 -40 -108 -140 -265 -457 -940 +154 +149 +143 +135 +105 +81 +60 +46 +29 +6 -23 -65 -128 -232 -315 -440 -648 -1065 1. All units in ps. 2. For all input signals the total tIS (input setup time) and tIH (input hold time) required is calculated by adding the individual datasheet value to the derating value listed in the previous table. Data Setup (tDS) and Hold Time (tDH) Derating Table DQS, DQS Differential Slew Rate (DDR2- 667/800) DQ Slewrate (V/ns) 4.0 V/ns 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 0.4 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns D D D D D D D D D D D D D D D D D D tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH 100 63 100 63 100 63 112 75 124 87 136 99 148 111 160 123 172 135 67 42 67 42 67 42 79 54 91 66 103 78 115 90 127 102 139 114 0 0 0 0 0 0 12 12 24 24 36 36 48 48 60 60 72 72 -5 -14 -5 -14 -5 -14 7 -2 19 10 31 22 43 34 55 46 67 58 -13 -31 -13 -31 -13 -31 -1 -19 11 -7 23 5 35 17 47 29 59 41 -22 -54 -22 -54 -22 -54 -10 -42 2 -30 14 -18 26 -6 38 6 50 18 -34 -83 -34 -83 -34 -83 -22 -71 -10 -59 2 -47 14 -35 26 -23 38 -11 -60 -125 -60 -125 -60 -125 -48 -113 -36 -101 -24 -89 -12 -77 0 -65 12 -53 -100 -188 -100 -188 -100 -188 -88 -176 -76 -164 -64 -152 -52 -140 -40 -128 -28 -116 1. All units in ps. 2. For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the individual datasheet value to the derating value listed in the previous table. REV 1.0 04/2008 65 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Overshoot and Undershoot Specification AC Overshoot / Undershoot Specification for Address and Control Pins DDR2-800 (-25C) DDR2-667 (-3C) Units Maximum peak amplitude allowed for overshoot area 0.45 0.45 V Maximum peak amplitude allowed for undershoot area 0.45 0.45 V Maximum overshoot area above VDD 0.66 0.8 V.ns Maximum undershoot area below VSS 0.66 0.8 V.ns Parameter Maximum Amplitude Volts (V) Overshoot Area VDD VSS Maximum Amplitude Undershoot Area Time (ns) AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins DDR2-800 (-25C) DDR2-667 (-3C) Units Maximum peak amplitude allowed for overshoot area 0.45 0.45 V Maximum peak amplitude allowed for undershoot area 0.45 0.45 V Maximum overshoot area above VDDQ 0.23 0.23 V.ns Maximum undershoot area below VSSQ 0.23 0.23 V.ns Parameter Maximum Amplitude Volts (V) Overshoot Area VDDQ VSSQ Maximum Amplitude Undershoot Area Time (ns) REV 1.0 04/2008 66 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Revision Log Rev Date 0.1 01/2008 Preliminary Edition 1.0 04/2008 Official Release Edition REV 1.0 04/2008 Modification 67 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die Package Dimensions (x16; 84 balls; 0.8mmx0.8mm Pitch; BGA Package) BOTTOM VIEW TOP VIEW 6.4 10 +/- 0.1 Pin A1 Index 0.8 11.2 12.5 +/- 0.1 0.8 Pin A1 Index Min. 0.25 Max. 0.40 Min. 0.40 Max. 0.50 Max. 1.20 Min. 0.10 Units: mm REV 1.0 04/2008 Max. 0.20 84Balls Min. 0.10 68 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5TB128M4CE NT5TB64M8CE NT5TB32M16CG 512Mb DDR2 SDRAM C-Die (R) Nanya Technology Corporation. All rights reserved. Printed in Taiwan, R.O.C., 2007 The following are trademarks of NANYA TECHNOLOGY CORPORATION in R.O.C, or other countries, or both NANYA logo. Other company, product and service names may be trademarks or service marks of others. NANYA TECHNOLOGY CORPORATION (NTC) reserves the right to make changes without notice. NTC warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with NTC's standard warranty. Testing and other quality control techniques are utilize to the extent NTC deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage ("Critical Applications"). NTC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTEND, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. Inclusion of NTC products in such applications is understood to be fully at the risk of the customer. Use of NTC products in such applications requires the written approval of an appropriate NTC officer. Question concerning potential risk applications should be directed to NTC through a local sales office. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards should be provided by customer to minimize the inherent or procedural hazards. NTC assumes no liability of applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does NTC warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of NTC covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. NANYA TECHNOLOGY CORPORATION HWA YA Technology Park 669, FU HSING 3rd Rd., Kueishan, Taoyuan, Taiwan, R.O.C. The NANYA TECHNOLOGY CORPORATION home page can be found at http:\\www.nanya.com REV 1.0 04/2008 69 (c) NANYA TECHNOLOGY CORP. All rights reserved. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.