LCS708HG - Power Integrations

LCS700-708

HiperLCS™ Family

www.powerint.com February 2012

Integrated LLC Controller, High-Voltage

Power MOSFETs and Drivers

Product Highlights

Features

• LLC half-bridge power stage incorporating controller, high and

low-side gate drives, and high-voltage power MOSFETs

• Eliminates up to 30 external components

• High maximum operating frequency of 1 MHz

• Nominal steady-state operation up to 500 kHz

• Dramatically reduces magnetics size and allows use of

SMD ceramic output capacitors

• Precise duty symmetry balances output rectiﬁer current,

improving efﬁciency

• 50% ±0.3% typical at 300 kHz

• Comprehensive fault handling and current limiting

• Programmable brown-in/out thresholds and hysteresis

• Undervoltage (UV) and overvoltage (OV) protection

• Programmable over-current protection (OCP)

• Short-circuit protection (SCP)

• Over-temperature protection (OTP)

• Programmable dead-time for optimized design

• Programmable burst mode maintains regulation at no-load and

improves light load efﬁciency

• Programmable soft-start time and delay before soft-start

• Accurate programmable minimum and maximum frequency

limits

• Single package designed for high-power and high-frequency

• Reduces assembly cost and reduces PCB layout loop areas

• Simple single clip attachment to heat sink

• Exposed thermal pad (H package only) connected to

ground potential – no insulators required between package

and heat sink

• Staggered pin arrangement for simple PC board routing

and high-voltage creepage requirements

• Paired with HiperPFS PFC product gives complete, high

efﬁciency, low part count PSU solutions

Applications

• High-efﬁciency power supplies (80 PLUS Silver, Gold and

Platinum)

• LCD TV power supplies

• LED street and area lighting

• Printer power supplies

• Audio ampliﬁer

Figure 1. Typical Application Circuit – LCD TV and PC Main Power Supply.

Description

The HiperLCS is an integrated LLC power stage incorporating a

multi-function controller, high-side and low-side gate drivers,

plus two power MOSFETs in a half-bridge conﬁguration. Figure 1

shows a simpliﬁed schematic of a HiperLCS based power stage

where the LLC resonant inductor is integrated into the transformer.

The variable frequency controller provides high efﬁciency by

switching the power MOSFETs at zero voltage (ZVS), eliminating

switching losses.

LLC Feedback Circuit

HiperLCS

VREF

DT/BF

RFMAX

RBURST

VCC

VCCH

HV DC

Input OV/UV

G S1/S2

PI-6159-060211

Standby

Supply

CONTROL

B+

RTN

B-

Output Power Table

Product Maximum Practical Power1

LCS700HG/LG 110 W

LCS701HG/LG 170 W

LCS702HG/LG 220 W

LCS703HG/LG 275 W

LCS705HG 350 W

LCS708HG 440 W

Table 1. Output Power Table.

Notes:

1. Maximum practical power is the power the part can deliver when properly

mounted to a heat sink and a maximum heat sink temperature of 90 °C.

Rev. C 02/12

LCS700-708

www.powerint.com

Figure 2. Block Diagram.

PI-5755-060111

VREF

OV/UV VSDH/

VSDL

VOVH/

VOVL

LLC_ON

LLC_CLK

VISF

VISS

VREF

FEEDBACK (FB)

DT/BF

3.4 V

REGULATOR

UVLO

VCC DRAIN (D)

VCCH

SOURCE (S1/S2)

GROUND (G)

DEAD-TIME

GENERATOR

OUTPUT

CONTROL

LOGIC

DEBOUNCE

3 LLC CLOCK

CYCLES

OVER-

TEMPERATURE

PROTECTION

7 CONSECUTIVE

LLC CLOCK

CYCLES

DEBOUNCE

3 LLC CLOCK

CYCLES

LLC

CLOCK

LEVEL

SHIFT

UVLO

SOFT-START DELAY

131,072 LLC

CLOCK CYCLES

DT/BF

RESISTOR

SENSOR

Bursting

Thresholds

Control

Rev. C 02/12

LCS700-708

www.powerint.com

Pin Functional Description

VCC Pin

IC power pin. In a typical application, VCC is connected to the

12 V system standby supply via a 5 W resistor. This resistor

helps provide ﬁltering and improves noise immunity.

Note: The system standby supply return should be connected to

the B- bus and not to the GROUND pin.

VREF Pin

3.4 VREF pin. An internal voltage reference network used as a

voltage source for FEEDBACK pin and DT/BF pin pull-up

resistor.

GROUND (G) Pin

G is the return node for all analog small signals. All small signal

pin bypass capacitors must be returned to this pin through short

traces, with the exception of the D-S high-voltage bypass

capacitor, and the VCCH bypass capacitor. It is internally

connected to the SOURCE pins to provide a star connection.

Do not connect the GROUND pin to the SOURCE pins,

nor to the B- bus, in the PCB layout.

OV/UV Pin

Overvoltage/Undervoltage pin. B+ is sensed by this pin through

a resistor divider. The OV/UV pin implements brown-in,

brown-out, and overvoltage lockout with hysteresis. Pulling this

pin down to ground will implement a remote-off function.

FEEDBACK (FB) Pin

Current fed into this pin determines LLC switching frequency;

higher current programs higher switching frequency. The pin

V-I characteristic resembles a diode to ground during normal

switching. An RC network between the VREF pin and

FEEDBACK pin determines the minimum operating frequency,

start-up frequency, soft-start time, and delay before start-up.

DEAD-TIME/BURST FREQUENCY (DT/BF) Pin

A resistor divider from VREF to ground programs dead-time,

maximum switching frequency at start-up, and burst-mode

threshold frequencies.

CURRENT-SENSE (IS) Pin

The CURRENT-SENSE pin is used for sensing transformer

primary current, to detect overload and fault conditions, through

a current sense resistor or a capacitive divider plus sense resistor

circuit. It resembles a reverse diode to ground, and does not

require a rectiﬁer circuit for preventing negative pulses from

reaching the pin, provided the reverse current is limited to <5 mA.

SOURCE (S1), (S2) Pins

SOURCE pins of internal low-side MOSFET. These should be

connected together on the PCB, and connected to the B- from

the PFC bulk capacitor or input high-voltage DC return.

HB Pin

This is the output of the half-bridge connected MOSFETs

(Source of high-side MOSFET, Drain of low-side MOSFET), to

be connected to the LLC power train (transformer primary and

series resonant capacitor).

VCCH Pin

Floating bootstrap supply pin for the LLC high-side driver. This

pin is referenced to the HB pin, which in turn is internally

connected to the SOURCE pin of the high-side MOSFET. A

bypass/storage capacitor between VCCH and HB pins, and a

boot strap diode with a series resistor from the standby supply,

are required. The storage capacitor is refreshed every time the

lower MOSFET turns on or its body diode conducts.

DRAIN (D) Pin

DRAIN pin of the internal high-side MOSFET. This connects to

the B+ from the PFC bulk capacitor or input high-voltage DC bus.

Figure 3. Pin Numbering and Designation.

PI-5636a-020212

H Package (eSIP-16C)

(Front View)

H Package

(eSIP-16C)

(Back View)

L Package (eSIP-16K)

(Front View. No Exposed Pad on the Backside)

VCC

VREF

OV/UV

DT/BF

VCCH

VCC

VREF

OV/UV

DT/BF

Exposed Pad (Backside)

Internally Connected to

GROUND Pin (see eSIP-16C

Package Drawing)

Exposed Metal (Both H and L

Packages) (On Package Edge)

Internally Connected

VCCH

Pin 1 I.D.

Rev. C 02/12

LCS700-708

www.powerint.com

Figure 4. 150 W Laser-Jet Printer Power Supply.

HiperLCS

LCS702HG

VREF

DT/BF

VCC

VCCH

OV/UV

2.2 Ω

UF4005

R14

7.5 kΩ

R13

86.6 kΩ

C19

3.3 nF

200 V

C17

2.2 nF

200 V

R11

24 Ω

R12

220 Ω

U2A

LTV817A

STPS30L60CT

U2B

LTV817A

24 V

RTN

R10

7.68 kΩ

4.7 Ω

R18

10 kΩ

R23

47 Ω

R17

22 kΩ

C16

470 μF

35 V

C15

10 μF

35 V

22 nF

630 V

C14

10 μF

35 V

150 nH

330 nF

50 V

4.7 nF

200 V

R20

1.2 kΩ

R21

4.7 kΩ

R19

143 kΩ

36.5 kΩ

7.68 kΩ

1 FL1

EEL25.4

FL2,3

FL4

4.7 nF

200 V

1 μF

25 V C5

4.7 nF

200 V

1 μF

25 V

C20

47 μF

35 V

220 nF

50 V

1N4148

1 nF

200 V

C12

47 pF

1 kV

C11

6.2 nF

1.6 kV

C13

2.2 nF

250 VAC

LM431AIM3DR

C10

330 nF

50 V

R15

1 kΩ

R16

1.5 kΩ

20 kΩ

976 kΩ

S1/S2

380 V

PI-6160-062011

VCC

+12 V

CONTROL

B+

B-

Rev. C 02/12

LCS700-708

www.powerint.com

HiperLCS Basic Operation

The HiperLCS is designed for half-bridge LLC converters, which

are high-efﬁciency resonant, variable frequency converters. The

HiperLCS is an LLC controller chip with built-in drivers and

half-bridge MOSFETs.

LLC converters require a ﬁxed dead-time between switching

half-cycles. The dead-time, maximum frequency at start-up,

and burst threshold frequencies, are programmed with a resistor

divider on the DT/BF pin from the VREF to the GROUND pins.

The FEEDBACK (FB) pin is the frequency control input for the

feedback loop. Frequency is proportional to FEEDBACK pin

current. The FEEDBACK pin V-I characteristic resembles a

diode to ground.

Burst Mode

If the frequency commanded by the FEEDBACK pin current

exceeds the upper burst threshold frequency (fSTOP, ISTOP)

programmed by the resistor divider on the DT/BF pin, the output

MOSFETs will turn off, and will resume switching when the current

drops below the value which corresponds to the frequency

equal to the lower burst threshold frequency (fSTA RT, ISTART ). As a

ﬁrst approximation, burst mode control resembles a hysteretic

controller where the frequency ramps from fSTART to fSTOP, stops

and repeats. An external component network connected from

the VREF pin to the FEEDBACK pin determines the minimum

and start-up FEEDBACK pin currents, and thus the minimum

and start-up switching frequencies. A soft-start capacitor in

this network determines soft-start timing.

The VREF pin provides a nominal 3.4 V as a reference for this

FEEDBACK pin external network and other functions. Maximum

current from this pin must be ≤4 mA.

The Dead-Time/Burst Frequency (DT/BF) pin also has a diode-to-

ground V-I characteristic. A resistor divider from VREF to GROUND

programs dead-time, maximum start-up switching frequency (fMAX),

and the burst threshold frequencies. The current ﬂowing from the

resistor divider to the DT/BF pin determines fMAX. The ratio of the

resistors selects from 3 discrete, burst threshold frequency ratios,

which are ﬁxed fractions of fMAX.

The OV/UV pin senses the high-voltage B+ input through a

resistor divider. It implements brown-in, brown-out, and OV

with hysteresis. The ratios of these voltages are ﬁxed; the user

must select the resistor divider ratio such that the brown-in

voltage is below the minimum nominal bulk (input) voltage

regulation set-point to ensure start-up, and the OV (lower)

restart voltage is above the maximum nominal bulk voltage

set-point, to ensure that the LCS will restart after a voltage swell

event that triggers the OV upper threshold. If different brown-in

to brown-out to OV ratios are required, external circuitry needs

to be added to the resistor divider.

VCC Pin UVLO

The VCC pin has an internal UVLO function with hysteresis. The

HiperLCS will not start until the voltage exceeds the VCC start

threshold VUVLO(+). HiperLCS will turn off when the VCC drops to

the VCC Shutdown Threshold VUVLO(-).

VCCH Pin UVLO

The VCCH pin is the supply pin for the high-side driver. It also

has a UVLO function similar to the VCC pin, with a threshold

lower than the VCC pin. This is to allow for a VCCH voltage that

is slightly lower than VCC because the VCCH pin is fed by a

bootstrap diode and series current-limiting resistor from the

VCC supply.

Start-Up and Auto-Restart

Before start-up the FEEDBACK pin is internally pulled up to the

VREF pin to discharge the soft-start capacitor and to keep the

output MOSFETs off. When start-up commences the internal

pull-up transistor turns off, the soft-start capacitor charges, the

outputs begin switching at fMAX, the FEEDBACK pin current

diminishes, the switching frequency drops, and the PSU output

rises. When the output reaches the voltage set-point, the

optocoupler will conduct, closing the loop and regulating the output.

Whenever the VCC pin is powered up, the DT/BF pin goes into

high impedance mode for 500 ms in order to sense the voltage

divider ratio and select the Burst Threshold. This setting is

stored until the next VCC recycle. The DT/BF pin then goes into

normal mode, resembling a diode to ground, and the sensed

current continuously sets the fMAX frequency. The burst threshold

frequencies are ﬁxed fractions of fMAX. The internal oscillator

runs the internal counters at fMAX whenever the FEEDBACK pin

internal pull-up is on.

When a fault is detected on the IS, OV/UV, or VCC pin (UVLO),

the internal FEEDBACK pin pull-up transistor turns on for

131,072 clock cycles, to discharge the soft-start capacitor

completely, then a restart is attempted. The ﬁrst power-up after

a VCC recycle only waits 1024 cycles, including the condition

where the OV/UV pin rises above the brown-in voltage for the

ﬁrst time, after VCC is powered up.

Remote-Off

Remote-off can be invoked by pulling down the OV/UV pin to

ground, or by pulling up the IS pin to >0.9 V. Both will invoke a

131,072 cycle restart cycle. VCC can also be pulled down to

shut the device off, but when it is pulled up, the FEEDBACK pin

is pulled up to the VREF pin to discharge the soft-start capacitor

for only 1024 fMAX clock cycles. If this scheme is used, the

designer must ensure that the time the VCC is pulled down,

plus 1024 cycles, is sufﬁcient to discharge the soft-start

capacitor, or if not, that the resulting lower starting frequency is

high enough so as not to cause excessive primary currents that

may cause the over-current protection to trip.

Current Sense

The IS pin senses the primary current. It resembles a reverse

diode to the GROUND pin. It is tolerant of negative voltages

provided the negative current is limited to <5 mA. Therefore it

must be connected to the current sense resistor (or primary

capacitive voltage divider + sense resistor) via a series current

limiting resistor of >220 W. Thus it can accept an AC waveform

and does not need a rectiﬁer or peak detector circuit. If the IS

pin senses a nominal positive peak voltage of 0.5 V for 7

consecutive cycles, an auto-restart will be invoked. The IS pin

also has a second, higher threshold at nominally 0.9 V, which

will invoke an auto-restart with a single pulse. The minimum

Rev. C 02/12

LCS700-708

www.powerint.com

pulse width requirement for detection of both voltage thresholds

is nominally 30 ns. i.e. the thresholds have to be exceeded for

>30 ns for proper detection.

Over-Temperature Shutdown

The HiperLCS has latching OTP. VCCH must be cycled to

resume operation once the unit drops down below the OTP

threshold.

Basic Layout Guidelines

The HiperLCS is a high-frequency power device and requires

careful attention to circuit board layout in order to achieve

maximum performance.

The bypass capacitors need to be positioned and laid out

carefully to minimize trace lengths to the pins they serve. SMD

components are recommended for minimum component and

trace stray inductance.

Table 2 describes the recommended bypass capacitor values

for pins that require ﬁltering/bypassing. The table lists the pins

in the order of most to least sensitive. The bypass capacitor of

the pin at the top of the list being the most sensitive, receives

higher priority in bypass capacitor positioning to minimize trace

lengths, than the bypass capacitor of the pin below it. Noise

entering the two most sensitive pins on the list, namely the

FEEDBACK and DT/BF pins, will cause duty cycle, and dead-

time imbalance, respectively.

Figure 5 and Figure 6 show two alternate schemes for routing

ground traces for optimum performance. Figure 5 shows a

layout footprint for the LCS with oval pads. These allow a trace

to be passed between pins 3 and 5, directly connecting the

ground systems for the bypass capacitors located on each side

of the IC.

Figure 6 shows an LCS layout footprint with round pads that do

not allow traces to be routed between them due to insufﬁcient

space. In this case, a jumper (JP1, a 1206 size 0 W resistor) is

used to connect the ground systems together and allow a

connection for pin 3 to be routed under JP1 to the optocoupler.

Transformer T1 is a source of both high di/dt signals and dv/dt

noise. The ﬁrst can couple magnetically to sensitive circuitry,

while the second can inject noise via electrostatic coupling.

Electrostatic noise coupling can be reduced by grounding the

transformer core, but it is not economically feasible to reduce

the stray magnetic ﬁeld around the transformer without drastically

reducing its efﬁciency. Sensitive traces and components (such

as the optocoupler) should be located away from the transformer

to avoid noise pickup.

Pin Returned to Pin Recommended Value Notes

FEEDBACK (FB) GROUND 4.7 nF (at 250 kHz) Increase value proportionally for lower nominal frequency (e.g. 10

nF at 100 kHz). Forms a pole with FEEDBACK pin input

impedance which is part of feedback loop characteristic. Must

not introduce excessive phase shift at expected gain

crossover frequency. Noise entering FEEDBACK pin will cause

duty cycle imbalance.

DEAD-TIME/BURST

FREQUENCY (DT/BF)

GROUND 4.7 nF Time constant of this capacitor and the source

impedance of the resistors connected to DT/BF pin

must be <100 ms. Noise entering DT/BF pin will cause

dead time imbalance.

CURRENT SENSE (IS) GROUND 1 nF (at 250 kHz) Value changes proportionally with nominal LLC stage

operating frequency. Forms an RC low pass ﬁlter with

recommended 220 W series resistor. Must not attenuate

AC signal of primary current sense.

VCC GROUND 1 mF ceramic

VREF GROUND 1 mF ceramic

VCCH HB 0.1 mF - 0.47 mFBootstrap capacitor. Provides instantaneous current

for high-side driver for turning on high-side MOSFET.

Time constant formed with boost-strap current limiting

resistor (in series with bootstrap diode), delays VCCH

UVLO for a few switching cycles at start-up and during

burst mode operation for the ﬁrst switching cycles

DRAIN

(DC Bus)

S1, S2 10-22 nF SMD ceramic

minimum, plus 22-100 nF

through-hole

Total of 22 nF per amp of nominal primary RMS current.

SMD part must be located directly at the IC and

connected close, with short traces. This prevents

ringing of D-S during hard-switching (loss of ZVS)

transients. It also reduces high-frequency EMI.

OV/UV GROUND 4.7 nF

Table 2. Bypass Capacitor Table in Order of Importance.

Rev. C 02/12

LCS700-708

www.powerint.com

Figure 5. Placement of Bypass Capacitors on Signal Pins of IC.

Figure 6. Alternate Layout for LCS Footprint using Round Pads with Jumper Connecting

Two Grounds Highlighted.

Figure 7 shows a an example of preferred routing for the

optocoupler and traces connected to the FEEDBACK pin. The

optocoupler is spaced away from the transformer, reducing

noise pickup. The optocoupler output trace (from pin 3) is also

routed to increase the distance between it and “active”

components and traces, such as T1 and the hot side of

capacitor C12. Resistor R20 is located close to U1 rather than

optocoupler U2, so that any noise picked up on the optocoupler

trace is ﬁltered by the combination of R20 and C4 before it gets

to the FEEDBACK pin on U1. C4 is placed directly adjacent to

the FEEDBACK pin of U1 (pin 4).

VCCH is connected to the standby supply through a high-

voltage ultrafast diode and a 2.2 W resistor connected in series.

This diode resistor network charges the VCCH bypass/storage

capacitor whenever the internal LLC low-side MOSFET is on.

The resistor limits the peak instantaneous charging current.

See R6 and D1 in Figure 8.

G Pin

Rev. C 02/12

LCS700-708

www.powerint.com

Figure 8. Placement of VCCH Capacitor.

Figure 7. Preferred Routing of Optocoupler and Traces to FEEDBACK Pin.

Small Signal Bypass Capacitors

Please refer to Figure 5 Note the location of the small signal

bypass capacitors (highlighted) for the FEEDBACK, DT/BF, IS,

VREF, OV/UV and VCC pins, which allow short traces to their

pin connections and to the GROUND pin. Note that there is no

connection between the GROUND pin and the SOURCE pin or

the B- bus on the printed circuit board.

VCCH Bypass Capacitor

Please refer to Figure 8. Note the location of the VCCH

capacitor (highlighted) which allows short connections to the

HB pin and the VCCH pin.

Drain to Source High-Voltage Bypass Capacitor

Please refer to Figure 9. Note the location of the B+ to B- high-

voltage bypass capacitors (highlighted) placed at the IC, minimizing

the PCB trace length to the D and S pins.

Rev. C 02/12

LCS700-708

www.powerint.com

Bootstrap Circuit and HB Node Layout

Please refer to Figure 10. Note the location of the bootstrap diode,

capacitor, resistor, and the HB trace routing. The objective is to

keep them away from the small signal components and traces,

such as the feedback optocoupler. Do not unnecessarily

increase the area of the PCB traces on this node, because it will

increase the dv/dt (capacitive) coupling to low-voltage circuits.

Heat Sink Grounding – (H Package Only)

The exposed metal in the back of the HiperLCS package is

internally connected to the GROUND pin. If the HiperLCS has a

dedicated heat sink and there is no electrical insulator between

the device and the heat sink, the heat sink should be ﬂoating and

not electrically connected anywhere else. If the heat sink is

shared with other devices in the system, and the heat sink

requires grounding to minimize EMI, a thin insulator is strongly

recommended under the HiperLCS, for improved noise, surge,

and system-level ESD immunity. The resulting increase in thermal

resistance must be considered in the thermal design.

Transformer Secondary

The transformer secondary pins, output diodes, and main output

capacitors should be positioned close together and routed with

short thick traces. This is critical for secondary current symmetry

and to minimize output diode inverse voltage stress. The use of

ceramic capacitors allows placement between the transformer

secondary pins and the output rectiﬁer, producing a very tight

layout. See Figure 11. The secondary winding halves should be

inter-twined together before they are wound on the bobbin. This

minimizes the leakage inductance between them and greatly

improves current symmetry and minimizes output diode inverse

voltage stress. For a 2-output design the half-windings of a given

output need to be intertwined.

Figure 9. Placement of B+ and B- High-Voltage Bypass Capacitors.

SOURCE

DRAIN

Rev. C 02/12

LCS700-708

www.powerint.com

Figure 11. Placement of Capacitors Between Transformer Secondary Pins and

the Output Rectiﬁer to minimize and Equalize Loop Areas.

Figure 10. Placement of Boot Strap Diode, Capacitor, Resistor and the High-Voltage Trace Routing.

Center

Tap

Secondary

Output

Capacitors Rectiﬁer

Transformer

Primary

High-Side

Rev. C 02/12

LCS700-708

www.powerint.com

Key Design Details

The LLC converter is a variable frequency resonant converter.

As input voltage decreases, the frequency must decrease in

order to maintain output regulation. To a lesser extent, as load

reduces the frequency must increase. When the converter is

operating at the series resonant frequency, the frequency changes

very little with load. The minimum operating frequency required

occurs at brownout (minimum input voltage), at full load.

Operating Frequency Selection

For lowest cost, and smallest transformer size with the least

amount of copper, the recommended nominal operating frequency

is ~250 kHz. This allows the use of low-cost ceramic output

capacitors in place of electrolytic capacitors, especially at

higher output voltages (≥12 V). If the core and bobbin used

exhibits too much leakage inductance for 250 kHz, operation at

180 kHz also results in excellent performance. For optimal

efﬁciency at 250 kHz, AWG #44 (0.05 mm) Litz is recommended

for the primary, and AWG #42 (0.07 mm) for the secondary

winding. Thicker gauge lower cost Litz can be used at the

expense of increased copper loss and lower efﬁciency. Litz

gauge (AWG #38 or 0.1 mm) is optimal for very low frequencies

(60-70 kHz), requires much larger transformers and greater

lengths of Litz wire.

For nominal operating frequencies even as low as 130 kHz, the

use of PC44 or equivalent core material is recommended for

reduced losses. For a given transformer design, shifting the

frequency up (by substituting a smaller resonant capacitor), will

reduce core loss (due to reduced AC ﬂux density BAC) and

increase copper loss. Core loss is a stronger function of ﬂux

density than of frequency. The increased frequency increases

copper loss due to eddy current losses.

Nominal operating frequencies >300 kHz start to lose signiﬁcant

efﬁciency due to increased eddy current losses in the copper,

and due to the fact that a more signiﬁcant percentage of time is

spent on the primary slew time (ZVS transition time) which

erodes the percentage of time that power is transferred to the

secondary.

Resonant Tank and Transformer Design

Please refer to the Application Note AN-55 for guidance on

using the PIXls HiperLCS spreadsheet which assists in the

entire design process.

Primary Inductance

The optimal powertrain design for the HiperLCS uses a primary

inductance that results in minimal loss of ZVS at any steady-

state condition. Some loss of ZVS during non-steady-state

conditions is acceptable. Reducing primary inductance

produces higher magnetizing current which increases the range

of ZVS operation, but the increased magnetizing current

increases losses and reduces efﬁciency.

The calculation of the primary inductance to be used for a

ﬁrst-pass design is based on device size, rated load, minimum

input voltage, and desired operating frequency. It is provided in

the PIXls spreadsheet. LPRI is the primary inductance of an

integrated transformer (high leakage inductance), or in the case

of the use of an external series inductance, the sum of this

inductance and the transformer primary inductance.

Leakage Inductance

The parameter KRATIO is a function of leakage inductance:

RATIO

RES

PRI

The recommended KRATIO is from 2.5 - 7. This determines the

acceptable range of leakage inductance.

LRES is the leakage inductance in an integrated transformer; if a

separate series inductor is used, it is the sum of this inductance

and the leakage inductance of the transformer.

A low KR ATIO (high leakage inductance) may not be capable of

regulation at the minimum input voltage, and may show

increased transformer copper losses due to the leakage ﬂux. A

high KRATIO (low leakage inductance) will have high peak and

RMS currents at low-line, and require a lower primary inductance

to achieve ZVS operation over a suitably wide range, which

increases the resonant circulating current, reducing efﬁciency.

The core and bobbin designs available to the designer may limit

the adjustability of leakage inductance. Fortunately, excellent

performance can be achieved over a relatively wide range of

leakage inductance values.

The KR ATIO directly affects the frequency range that the LLC needs

to operate in order to maintain regulation over the input voltage

range. Increasing KRATIO increases this frequency range,

lowering fMIN.

A low fMIN is only a potential problem for low frequency designs

which typically run at higher nominal BAC. This may allow the

core to reach saturation when operating at fMIN. Operating at

fMIN occurs when the input voltage is at a minimal (input

brown-out).

For a design with a separate resonant inductor, running the

inductance on the low side of the range (KRATIO = 7), minimizes

the size and cost of the inductor.

Adjusting Leakage Inductance

Sectioned bobbins (separated primary and secondary) are

commonly used for LLC converters. Increasing or decreasing

both primary and secondary turns (while maintaining turns ratio)

will change the leakage inductance proportionally to the square

of primary turns.

If the leakage inductance is too high, one possible solution is to

use a 3-section bobbin, where the secondary is in the middle

section, and the primary winding is split into 2 halves connected

in series.

Lastly, if the leakage inductance is too low an external inductor

may be added.

Rev. C 02/12

LCS700-708

www.powerint.com

Resonant Frequency

The series resonant frequency is a function of LRES and CRES, the

resonant capacitor. For any given value of LRES, the value of

CRES can be adjusted for the desired series resonant frequency

fRES. For best efﬁciency the resonant frequency is set close to

the target operating frequency at nominal input voltage.

Operating Frequency and Frequency Ratio

The operating to resonant frequency ratio fRATIO is deﬁned as:

RATIO

RES

fRATIO = 1 signiﬁes the converter is operating at the series

resonant frequency.

The main determinant of fR ATIO is the transformer turns ratio.

Increasing primary turns lowers fRATIO for a given input and

output voltage.

The recommended fRATIO at nominal input voltage is 0.92 – 0.97.

Operating at resonance often yields the highest efﬁciency for

the resonant powertrain if output rectiﬁer selection is ignored.

However, operating slightly below resonance (which puts the

rectiﬁers in discontinuous conduction mode), allows the use of

lower voltage diodes or synchronous MOSFETs, which have

lower losses, increasing overall efﬁciency. This is because at

high-line, when the converter needs to operate above resonance,

the rectiﬁers operate less deeply in continuous mode, reducing

the magnitude of their current commutation, reducing their stray

inductance voltage spikes. (The stray inductance is comprised

of the leakage inductance between secondary phases and the

stray inductance in the connections to the rectiﬁers and output

capacitors).

Conversely, operating at a very low fRATIO (<0.8) results in higher

RMS and peak currents. In some cases, this may result in an

optimal design because it allows the use of lower voltage rating,

lower VF rectiﬁer as they do not operate in continuous conduction

mode even at high-line, results in no voltage spikes enabling a

lower voltage rating.

An LLC half-bridge converter will operate at resonance when

this equation is true:

OUT

Where nEQ is the transformer equivalent circuit turns ratio. Note

that the nEQ of an integrated transformer is lower than its

physical turns ratio NPRI / NSEC. The secondary turns is that of

each half-secondary. VOUT in the above equation is equal to

output voltage + diode drop. The divisor “2” is due to the

half-bridge conﬁguration – each half-cycle conducts half the

input voltage to each secondary half.

Note that if the resonant capacitor or inductance value is

changed, both switching frequency and resonant frequency

change, but fR ATIO changes little.

For a given design, the input voltage at which the LLC operates

at resonance is VINPUT(RESONANCE). Below this voltage, the LLC

operates at a lower frequency (below resonance). Thus for the

recommended fRATIO ≈ 0.95 at nominal input voltage, VINPUT(RESONANCE)

will be slightly higher than the nominal voltage.

For a design with a variable nominal input voltage (e.g. no PFC

pre-regulator), it is recommended that the initial turns ratio be set

so that VINPUT(RESONANCE) is at about halfway between maximum and

minimum input voltage. For a design with a variable output voltage

(e.g. constant current regulated output), it is recommended that

the initial turns ratio be set to operate the LLC at resonance at a

point halfway between minimum and maximum output voltages.

Dead-Time Selection

The vast majority of designs using HiperLCS, regardless of power

and operating frequency, work very well with a dead-time of

between 290 and 360 ns. Designs that require a low VBROWNOUT

tend to require shorter dead-times.

The dead-time setting is a compromise between low-line / full

load (low frequency), and minimum-load / high-line (high-

frequency) conditions. Low-line / full load operation has short

optimal dead-times, while minimum load / high-line has long

optimal dead-times.

A dead-time setting that is longer than optimal for low-line / full

load operation, exhibiting partial loss of ZVS, is acceptable if the

condition does not occur during steady-state operation – i.e.

appears only during transient conditions, such as hold-up time.

Operation with loss of ZVS during steady-state operation leads

to high internal power dissipation and should be avoided.

A dead-time setting that is shorter than optimal for high-line /

minimum-load operation, will tend to cause the feedback sign

to invert and force the HiperLCS to enter burst mode. This is

acceptable if the resulting burst mode operation is acceptable

(i.e. repetition rate does not produce audible noise and if the

large signal transients, wherein the HiperLCS enters and exits

burst mode, is acceptable). Note that with a PFC pre-regulated

front end, a load dump (e.g. 100% to 1% load step) will exhibit a

transient input voltage condition only temporarily (e.g. Input

voltage to LLC stage will increase from 380 V to 410 V and

relatively slowly return to 380 V). Note also that the Burst

Threshold frequency setting is another variable available to the

designer to tune burst mode.

OV/UV Pin

The HiperLCS OV/UV pin which monitors the input (B+) voltage,

has a brown-out shutdown threshold (VSD(L)) of nominally 79% of

the brown-in (turn-on) threshold (VSD(H)), which in turn, is nominally

2.4 V. The overvoltage (OV) lockout shutdown threshold (VOV(H))

is nominally 131% of the brown-in start-up threshold, and the

OV restart point (VOV(L)) at nominally 126%. The ratios of these

thresholds are ﬁxed and selected for maximum utility in a design

with a PFC pre-regulator front-end with a ﬁxed output voltage

set-point. The resistor divider ratio has to be selected so that

brown-in point is always below the PFC output set-point, and

so that the OV restart (lower) threshold, is always above it,

including component tolerances.

During hold-up time, the voltage will drop from the nominal

value, down to the brown-out threshold, whereby the HiperLCS

will stop switching.

Rev. C 02/12

LCS700-708

www.powerint.com

If the input voltage is variable (e.g. no PFC pre-regulator), and

the variation is greater than 24%, the OV threshold should be

increased with external circuitry on the resistor divider. External

circuitry is also needed if VBROWNOUT needs to be reduced below

the default ratio.

In the example in the left-hand side of Figure 14 the resistor

divider is set so that brown-in threshold is 376 V, just under the VPFC

set-point of 385 V. The OV shutdown threshold is 495 V, which

gives adequate margin against the device max VDS rating of 530 V.

This minimizes required minimum LLC gain, and minimizes the

peak current at brown-out. In the example on the right of Figure

14, the OV restart threshold is set to 418 V, just above VPFC. This

maximizes hold-up time for a given bulk capacitor value.

The OV/UV pin has an integrated 5 MW pull-down to detect

pin-open fault conditions.

The recommended pull-down resistor value for the OV/UV pin

divider is 20 kW - 22 kW. A very large resistor value will cause

the pin pull-down current to affect accuracy, and a small value

will increase power loss.

DT/BF Pin

The DT/BF pin senses the voltage divider ratio by entering into a

high-impedance mode for 500 ms after VCC is applied. It

senses the pin voltage, before the HiperLCS starts switching.

See Figure 15.

There are 3 discrete Burst Threshold settings that can be

selected. (This determines the burst start and stop switching

frequencies, see Table 3).

For proper selection, set the ratio of RBURST to RFMAX as per Table 3.

Table 3. Burst Threshold Selection Table.

The Burst Threshold setting is stored until VCC is powered down.

After the Burst Threshold detection, the DT/BF pin operates in

normal mode, sinking current, resembling a diode to ground,

with a Thevenin equivalent circuit of nominally 0.66 V and

1.1 k W. The current from the resistor divider into the pin,

determines the dead-time and the maximum frequency fMAX.

The relationship between dead-time and fMAX is ﬁxed and

approximated by:

Time-

fkHz Dead ns

27 0000

MAX=

The relationship between DT/BF pin current and fMAX, and

switching frequency vs. FEEDBACK pin current (which has the

same characteristic), is show in Figure 16.

The burst mode start and stop frequency thresholds are ﬁxed

fractions of fMAX, which depend on the Burst Threshold setting,

as set by the resistor divider ratio on the DT/BF pin.

Table 4. Burst Start and Stop Frequencies as Ratios of fMAX.

Figure 14. OV/UV Pin Voltage Thresholds, at Minimum and Maximum Divider Ratios, for 385 V Nominal Input Voltage.

495 V VOVH

376 V VSDH

298 V VSDL

475 V VOVL

OV/UV pin resistor divider chosen

for minimum required LLC gain

200 V

Time Time

385 V

436 V VOVH

331 V VSDH

262 V VSDL

418 V VOVL

OV/UV pin resistor divider chosen

for minimum hold-up capacitance

200 V

385 V

PI-6154-051811

RFMAX

RBURST

GND

VREF

DT/BF

PI-6460-051811

Figure 15. DT/BF Pin Divider.

Burst Threshold RBURST / RFMAX

119

2 9

35.67

Burst Threshold

Setting fSTART/fMAX fSTOP/fMAX

17/16 8/16

26/16 7/16

35/16 6/16

Rev. C 02/12

LCS700-708

www.powerint.com

For example, if BT2 is selected, and fMAX is 800 kHz, then fSTART

= 300 kHz, and fSTOP = 350 kHz. If during normal operation the

load is reduced and the frequency rises to 350 kHz, the switching

will stop. This causes the output voltage to drop and the

feedback loop to decrease the FEEDBACK pin current. When

the current decreases to a value which corresponds to 300 kHz,

switching will commence, and the cycle will repeat. During

start-up mode, however, the outputs can switch at a frequency

between fSTOP and fMAX (250 kHz and 800 kHz in the above

example). Start-up mode is exited once the switching frequency

drops below fSTOP, and the HiperLCS will subsequently enter

burst mode if the feedback loop attempts to produce a

switching frequency >fSTOP.

fMAX is the frequency at which the internal counters run when the

HiperLCS is in the off-state of the auto-restart cycle, or in the

power-up delay before switching.

The minimum recommended dead-time is 275 ns, and thus the

maximum fMAX setting is 1 MHz.

To simplify the selection of RFMAX, see the selection curves in Figure 17.

Figure 16. FEEDBACK Pin and DT/BF Pin Current vs. Frequency.

PI-6150-052011

6004002000 800 1000

150

100

200

250

300

350

400

450

Frequency (kHz)

Current (μA)

250 300 350 400 500450

Dead-Time (ns)

RFMAX (kΩ)

13.0

12.0

11.0

9.0

10.0

8.0

7.0

6.0

5.0

PI-6458-051911

BT1

BT2

BT3

Figure 17. RFMAX vs. Dead-Time, for the 3 Different Burst Threshold Settings.

Figure 18. fSTART (Lower Burst Threshold Frequency) vs. Dead-Time Setting for

Different Burst Threshold Settings (BT1, BT2, BT3).

250 300 350 400 500450

Dead-Time (ns)

fSTART (kHz)

500

450

350

400

300

250

200

150

PI-6457-051911

BT1

BT2

BT3

The fSTOP to fSTART ratio is ﬁxed, and dependent on the Burst

Threshold setting (see Table 5).

Table 5. Ratio of fSTOP /fSTART vs. Burst Threshold Selection.

As a ﬁrst approximation, during burst mode, the frequency

ramps from fSTART to fSTOP; then switching stops, and then the cycle

repeats.

FEEDBACK Pin

The FEEDBACK pin is the voltage regulation FEEDBACK pin. It

has a nominal Thevenin equivalent circuit of 0.65 V and 2.5 kW.

In normal operation, it sinks current. During the off-period of

auto-restart, and during the clocked delay before start-up, it pulls

up internally to VREF in order to discharge the soft-start capacitor.

The current entering the pin determines switching frequency.

Higher current yields higher frequency and thus reduces LLC

output voltage. In a typical application an optocoupler connected

to the VREF pin pulls up on the FEEDBACK pin, via a resistor

network. The optocoupler is conﬁgured to source increasing

FEEDBACK pin current, as the output rises. The resistor network

between the optocoupler, FEEDBACK pin, and VREF pin,

determine the minimum and maximum FEEDBACK pin current

(and thus the minimum and maximum operating frequency), that

the optocoupler can command as it goes from cutoff to saturation.

This network also contains the soft-start timing capacitor, CSTART

(Figure 19).

The minimum frequency as set by this network must be lower

than the frequency required by the powertrain at minimum input

voltage. In Figure 19 this is determined by the sum of RFMIN and

RSTART. The FEEDBACK pin current is determined by these two

resistors when the optocoupler is cut off. CSTART can be ignored

during normal operation. Do not confuse RSTART, which determines

Burst Threshold

Setting fSTOP / fSTART

11.14

21.17

31.20

Rev. C 02/12

LCS700-708

www.powerint.com

start-up frequency, and fSTART, which is the burst mode start

(lower) threshold frequency.

The FEEDBACK pin current at start-up is determined by the value

of RSTART because the voltage on CSTART will be zero. For minimum

start-up peak currents, this current should match or slightly

exceed the DT/BF pin current so that start-up switching frequency

begins at fMAX. The resulting value of RSTART will be approximately

10% lower than the value of the pull-up resistor on the DT/BF pin.

The frequency will slide down as CSTART charges. If RSTART is

smaller than that which provides start-up at fMAX, it will create an

additional delay before start-up switching. Please see the PIXls

HiperLCS spreadsheet.

Resistor RLOAD provides a load on the optocoupler, and speeds

up the large signal transient response during burst mode. The

recommended value is ~4.7 kW. Diode D1 prevents RLOAD from

loading RFMIN when the optocoupler is cut off. Diode D1 can be

omitted and a combination of resistor values found to achieve the

desired fMIN but the resulting tolerances will be poor. Resistor

ROPTO will improve the ESD and surge immunity of the PSU. It

also improves burst mode output ripple voltage. Its maximum

value must be such that the FEEDBACK pin current is equal to

the DT/BF pin current when the optocoupler is in saturation and

the FEEDBACK pin is at 2.0 V (please see PIXls HiperLCS

spreadsheet). This is to ensure that if the HiperLCS does not exit

start-up mode, because the feedback loop did not allow the

switching frequency to drop below fSTOP, then it can regulate at

light load by bursting at fMAX. Note however bursting at fMAX can

lead to high internal dissipation due to loss of ZVS and should be

avoided. See Figure 20.

Capacitor CSTA RT should be sized at the minimum possible value

that exhibits a 7 consecutive-cycle peak current at start-up that is

just below the peak current measured at brown-out and full load.

A larger value will slow down start-up and will make it more likely

that fSTOP is not reached. This can prevent exiting start-up mode

when the HiperLCS is powered up at high-line and minimum load,

and may subsequently cause the HiperLCS to burst at fMAX

instead of between fSTA RT and fSTOP.

Figure 19. Feedback Network Shown with Additional Load Resistor.

~850 kHz

10 μs / div

IPRI 850 ns / div

Severe Loss of ZVS

Bursting Duty ≈ 50%

PI-6463-060711

VHB

Figure 20. Bursting at fMAX Causes High Internal Dissipation Due to Loss of

ZVS and Should be Avoided.

RFMIN

RSTART

ROPTO

RLOAD

3.4 V

U1B

CSTART

CFB

4.7 nF

GND

VREF

PI-6118-051711

Figure 21. VREF to FB External Resistance vs. Frequency.

In order to calculate RFMIN and RSTA RT, use the following equation

which describes nominal resistance from FEEDBACK pin to

VREF pin, vs. frequency:

R3574

FB LOGf0604101193

=#+

Where RFB is in kW and f is in kHz.

To calculate the minimum RSTART, which produces start-up at fMAX,

use the above equation with f = fMAX from the equation relating

dead-time and fMAX.

To set fMIN, use the above equation with f = fMIN × 0.93. Where

0.93 is to ensure that, despite the worst case frequency tolerance

of -7%, the frequency can go below fMIN, guaranteeing regulation

at VBROWNOUT.

Using the resulting calculated value for RFB, calculate RFMIN:

RRR

FMIN FB START

The sum of RFMIN and RSTART determines fMIN.

50 10020 200 500 1000

100

300

)

Frequency (kHz)

PI-6151-060911

Rev. C 02/12

LCS700-708

www.powerint.com

It should be noted that the 4.7 nF decoupling capacitor, CFB

(see Figure 19), in conjunction with the 2.5 kW input resistance

presented by the FEEDBACK pin, form a pole in the LLC

transfer function. This can add signiﬁcant phase lag to the

feedback loop. A typical value for a 250 kHz design with a

3 kHz crossover frequency is 4.7 nF. To prevent loop instability,

the value of the 4.7 nF capacitor should not be increased

arbitrarily. At the other extreme, insufﬁcient FEEDBACK pin

bypass capacitance or poor layout may cause duty cycle

asymmetry.

Start-Up and Auto-Restart

At start-up and during the off-state of the auto-restart cycle, the

FEEDBACK pin is internally pulled up to the VREF pin. This

keeps the output MOSFETs off and discharges the soft-start

capacitor, in preparation for soft-start.

At start-up, this state remains for 1024 clock cycles at frequency

fMAX. During the off-state of auto-restart, or if the OV/UV or IS pin

is triggered while the VCC remains above its UVLO threshold, this

state remains for 131,072 clock cycles.

After 1024 or 131,072 cycles (as the case may be), the HiperLCS

turns off the internal pull-up transistor, the soft-start capacitor

begins to charge, the output MOSFETs switch at fMAX, current in

the FEEDBACK pin diminishes, the frequency begins to drop,

and the PSU output rises.

For example, for fMAX = 800 kHz, the start-up delay after VCC

power-up is 1.3 ms. If IS, or the OV/UV pin are tripped, auto-

restart is invoked, with a restart delay of 164 ms.

The FEEDBACK pin has a current limit equal to the current

ﬂowing into the DT/BF pin. This limits the maximum current that

charges the soft-start capacitor at start-up. If RSTART is smaller

than that which allows the FEEDBACK pin current to match the

DT/BF pin current at start-up, an additional delay is introduced.

CSTART will charge at the current limit, and switching will only

commence when the FEEDBACK pin voltage drops below 2.0 V.

Thus the designer can add an additional start-up delay if desired.

As the soft-start capacitor continues to charge, the current

through RSTART and thus the FEEDBACK pin decreases, reducing

switching frequency. The output voltage climbs; and when the

feedback loop closes, the optocoupler conducts and starts

controlling the switching frequency thus the output voltage.

Remote-Off

Remote-off can be invoked by pulling down the OV/UV pin to

ground, or by pulling up the IS pin to >0.9 V. Both will invoke a

131,072 cycle restart cycle. VCC can also be pulled down to shut

the device off, but when it is pulled up, the FEEDBACK pin is

pulled up to the VREF pin to discharge the soft-start capacitor for

only 1024 fMAX clock cycles. If this scheme is used, the designer

must ensure that the time the VCC is pulled down, plus 1024

cycles, is sufﬁcient to discharge the soft-start capacitor, or if not,

that the resulting lower starting frequency is high enough so as

not to cause excessive primary currents that may cause the

over-current protection to trip.

IS Pin

The IS pin has 2 thresholds: nominally 0.5 V and 0.9 V. The IS

pin can tolerate small negative voltages and currents, and thus

does not need a peak detector or rectiﬁer circuit. The pin has a

reverse-biased diode to ground equivalent circuit, and can

tolerate a maximum negative current of 5 mA. The primary

current is sampled by a primary, B- referenced current sense

resistor, or by a capacitor current divider + current sense resistor

combination circuit. In order to limit the negative current to 5 mA,

a current limiting resistor between the sense resistor and the IS

pin is necessary, with a minimum value of 220 W. Using the

minimum value maximizes the IS pin bypass capacitor value

and thus pin noise rejection, for a given RC pole frequency.

The IS pin will invoke a restart if it sees 7 consecutive pulses

>0.5 V. It will also invoke a restart if a single pulse exceeds 0.9 V.

The minimum pulse detection time is nominally 30 ns – i.e. the

pulses must be higher than the threshold voltage for >30 ns.

The “capacitive divider” circuit in Figure 23 reduces power

dissipation and improves efﬁciency over a simple current sense

resistor circuit. The two capacitors, main resonant capacitor

C11, and sense capacitor C12, form a current divider. The

portion of the primary current routed through C12 is

11 12

Consequently, the voltage at the IS pin is equal to

11 12

12 11

where IP is the primary current ﬂowing from the HB pin through

the transformer primary. The current in the sense capacitor

passes through sense resistor R11. Resistor R11 is the main

means for tuning current limit. The signal on R11, an AC

voltage, passes through low-pass ﬁlter R12 and C7, to the IS

pin. Note that R11 is returned to the GROUND pin and not to

SOURCE pin.

PI-6471-052411

2.521.510 0.5 3 3.5 4 4.5 5

-6

-2

-4

Time (ms)

Amps (A)

Volts (V)

-8

-10

Primary Current

Output Voltage

Figure 22. Typical Start-up Waveform. Observe Initial Current Spike ‘A’ to Ensure

it is Below the 1-Cycle Current Limit. A Higher fMAX Reduces it. Size

the Soft-Start Capacitor so that the Peak of ‘B’ is just Below the Peak

Current at VBROWNOUT at Full Load.

Rev. C 02/12

LCS700-708

www.powerint.com

The recommended series resistor value of 220 W and the bypass

capacitor form a low-pass ﬁlter, and its time constant must not

cause signiﬁcant attenuation of the current sense signal at the

nominal operating frequency. The effect of the attenuation is

greatest for the ﬁrst pulse in the start-up current waveform, and

can also affect proper shutdown during short-circuit testing,

which typically trips the 7-cycle current limit. Place a close-

coupled probe across the IS pin bypass capacitor and compare

the waveform to the primary current.

Burst Mode Operation and Tuning

Burst mode will produce a typical waveform such as in Figure 24.

During the burst pulse train, the switching frequency rises from

fSTART to fSTOP.

If the initial output ripple spike at the beginning of the burst

pulse train is ignored, the output ripple somewhat resembles a

sawtooth. See the output ripple waveform in Figure 24. When

the HiperLCS is switching, the output rises. When it stops

switching, the output falls. The top of the sawtooth is where the

burst pulse train ends, because the feedback loop has commanded

a frequency = fSTOP. The bottom of the sawtooth is where the

burst pulse train begins, because the feedback loop has

commanded a frequency = fSTART. As such, the burst mode

control resembles a hysteretic controller, where the top and

bottom of the sawtooth are ﬁxed by the feedback loop gain.

The downward slope of the sawtooth is merely the output

capacitors discharging into the load, with dv/dt:

Where I = load current. C is the total output capacitance.

The upward slope of the sawtooth is dependent on the difference

between the current delivered by the powertrain, and the current

drawn by the load. For a given design, the upward slope

increases with input voltage.

The burst repetition rate (frequency) then increases with load.

When the load reaches a point where the powertrain can

regulate at a frequency <fSTOP, the bursting will stop. When the

load current decreases (from heavy load), frequency increases,

and when it reaches fSTOP, bursting will commence.

In a typical design, fSTART must be chosen to be at least 20-40%

higher than the nominal switching frequency. Figure 18 shows

the relationship between fSTART and dead-time, and Table 5 the

ratio of fSTOP to fSTART vs. Burst Threshold setting number). In

some cases the designer may choose to change dead-time

slightly in order to change fSTART and fSTOP. Some designs may

only enter burst mode at zero load and an input voltage above

nominal.

1 nF

C11

6.8 nF

1 kV

HB Pin

LLC

Transformer

IS Pin

GROUND

S Pin

C12

47 pF

1 kV

PI-6161-051711

R11

24 Ω

R12

220 Ω

Figure 23. Capacitive Divider Current Sense Circuit.

Figure 24. Typical Waveform of Burst Mode. 24 V / 150 W HiperLCS Design at

Zero Load. The Initial Spike (circled) Size is Dependent on Post-Filter

Electrolytic Capacitor ESR.

PI-6468-062811

050 100

100

400

300

200

Time (ms)

HB Voltage (V)

Output Ripple Voltage (V)

24.0

23.9

24.1

Burst Repetition Rate

Figure 25. Zoom in of First Few Switching Cycles of Burst Pulse Train of Figure 24.

The First 2 Cycles Show That the High-Side Driver has not Turned

on yet. The Switching Frequency of the First Few Cycles is fSTART,

335 kHz in This Case. The Ringing on the Output is from the

Output Filter.

PI-6469-062811

025 50

100

400

300

200

Time (μs)

HB Voltage (V)

Output Ripple Voltage (V)

24.0

23.9

24.1

Rev. C 02/12

LCS700-708

www.powerint.com

PI-6470-062811

050 100

100

400

300

200

Time (μs)

HB Voltage (V)

-5

Output Ripple Voltage (V)

24.0

23.9

24.1

Figure 26. Zoom in of Last Few Switching Cycles of Burst Pulse Train of Figure 24.

The Switching Frequency of the Last Few Cycles is fSTOP, 383 kHz in

This Case (arrow). The Ringing in VHB After Switching Stops, is the

Primary Inductance Ringing with the MOSFET Capacitance.

Higher fSTART will decrease the load threshold at which bursting

begins, increase the input voltage threshold and decrease the

output ripple in burst mode, but will increase the burst repetition

rate, which may introduce audible noise in some combinations

of line and load. The choice of fSTART will affect the large signal

transient response where the HiperLCS goes in and out of burst

mode.

Rev. C 02/12

LCS700-708

www.powerint.com

Parameter Symbol

Conditions

SOURCE = 0 V; TJ = -40 °C to 125 °C

VCC = 12 V, VCCH = 12 V

(Unless Otherwise Speciﬁed)

Min Typ Max Units

Half-Bridge

OFF-State Current IDSS

Measured from D to

HB or from HB to S

TJ = 100 °C, VCC =

12 V, VCCH = 12 V,

VD = 424 V

LCS700 60

LCS701 60

LCS702 65

LCS703 80

LCS705 120

LCS708 200

ON-State Resistance RDS(ON)

Measured from D to

HB or from HB to S

VCC = 12 V, VCCH =

12 V, TJ = 25 °C

LCS700, I = 0.8 A 1.53 1.82

LCS701, I = 1.2 A 1.00 1.24

LCS702, I = 1.6 A 0.74 0.92

LSC703, I = 2.0 A 0.60 0.73

LCS705, I = 3.0 A 0.40 0.49

LCS708, I = 4.8 A 0.26 0.31

Thermal Resistance

Junction to Case Thermal Resistance(1,3):

LCS700 (qJC)...................................... ...... 7.6 °C/W

LCS701 (qJC).............................. ............. 7.0 °C/W

LCS702 (qJC)...........................................6.6 °C/W

LCS703 (qJC) ......................................6.2 °C/W

LCS705 (qJC)............................... ............5.9 °C/W

LCS708 (qJC)............................... ............5.5 °C/W

Junction to heat sink Thermal Resistance(1,2):

LCS700 (qJH)............................... .......... 10.1 °C/W

LCS701 (qJH)...................................... ......9.5 °C/W

LCS702 (qJH)............................... ............ 9.1 °C/W

LCS703 (qJH)............................... ............8.7 °C/W

LCS705 (qJH)............................... ............8.4 °C/W

LCS708 (qJH)............................... ............8.0 °C/W

Hottest Junction to OT Sensor Thermal Offset(1,2,4):

LCS700 (ΔTJ-OT)........................................ 4.6 °C/W

LCS701 (ΔTJ-OT)............................... ........4.0 °C/W

LCS702 (ΔTJ-OT)................................ .......3.5 °C/W

LCS703 (ΔTJ-OT) ..................................3.2 °C/W

LCS705 (ΔTJ-OT)................................ .......2.8 °C/W

LCS708 (ΔTJ-OT)................................ .......2.5 °C/W

Notes:

1. Both power switches each dissipating half the total power.

2. Mounted to an aluminum heat sink with uniform coverage of

Thermalloy thermal paste. Mounting clip with normal force

>30 N applied to the center of the package.

3. Junction to case thermal resistance is based on hottest

junction, case temperature measured at center of package

back surface.

4. Temperature difference between hottest junction and over-

temperature sensor.

5. Thermal resistance values are preliminary and subject to change.

Absolute Maximum Ratings

Instantaneous Repetitive D or HB Current(5) ..............................

.................................. VCC, VCCH = 11.5 V, 25 °C

LCS700................................ ........................ 5.2 A

LCS701............................. ............................ 7.7 A

LCS702.............................. ........................ 10.3 A

LCS703 ................................................. 12.9 A

LCS705............................... ....................... 19.3 A

LCS708............................... ....................... 30.9 A

Instantaneous Repetitive D or HB Current(5) ...............................

................................. VCC, VCCH = 11.5 V, 125 °C

LCS700............................... ......................... 4.2 A

LCS701............................ ............................ 6.2 A

LCS702.............................. .......................... 8.3 A

LCS703 ................................................. 10.4 A

LCS705............................... ....................... 15.6 A

LCS708...................................... ................. 24.9 A

DRAIN Pin Voltage D(1) .........................................-1.3 V to 530 V

Half-bridge Voltage, HB(1)............................... -1.3 V to D + 0.5 V

Half-bridge Voltage Slew Rate, HB ............................. ....... 10 V/ns

SUPPLY Pin Voltage, VCC(1), VCCH(2).........................-0.3 V to 15 V

G Pin Voltage(1) .................................................... -0.3 V to 0.3 V

IS Pin Voltage(3) ...................................... ...... -0.65 to VREF + 0.3 V

DT/BF and FEEDBACK Pin Voltages(3) ....... -0.3 to VREF + 0.3 V

OV/UV Pin Voltage(3) ....................................-0.3 to VCC + 0.3 V

Pin Current (VREF, OV/UV, DT/BF, FEEDBACK, IS)....... .±100 mA

Junction Temperature ......................................-40 °C to 150 °C

Storage Temperature ...................................... -65 °C to 150 °C

Lead Temperature(4) ......................................................... 260 °C

ESD Rating (JESD22-A114-B, HBM) ....................................2 kV

Notes:

1. Voltage referenced to S.

2. Voltage referenced to HB.

3. Voltage referenced to G.

4. 1/16 inch from case for 5 seconds.

5. One-cycle peak current can exceed repetitive maximum current

for t < 460 ns if TJ < 100 °C and drain voltage ≤ 400 VDC.

Rev. C 02/12

LCS700-708

www.powerint.com

Parameter Symbol

Conditions

SOURCE = 0 V; TJ = -40 °C to 125 °C

VCC = 12 V, VCCH = 12 V

(Unless Otherwise Speciﬁed)

Min Typ Max Units

Half-Bridge (cont.)

ON-State Resistance RDS(ON)

Measured from D to

HB or from HB to S

VCC = 12 V, VCCH =

12 V, TJ = 100 °C

LCS700, I = 0.8 A 2.15 2.63

LCS701, I = 1.2 A 1.42 1.78

LCS702, I = 1.6 A 1.05 1.33

LCS703, I = 2.0 A 0.85 1.06

LCS705, I = 3.0 A 0.58 0.71

LCS708, I = 4.8 A 0.36 0.45

Half-Bridge

Capacitance CHB

Effective half-bridge

capacitance.

VHB swinging from

0 V to 400 V or

400 V to 0 V,

See Note A

TJ = 0 to 100 °C

LCS700 134

LCS701 201

LCS702 268

LCS703 335

LCS705 503

LCS708 804

Diode Forward

Voltage VFWD

Measured from HB

to D or from S to HB

TJ = 125 °C

LCS700, I = 0.8 A 1.15

LCS701, I = 1.2 A 1.15

LCS702, I = 1.6 A 1.15

LSC703, I = 2.0 A 1.15

LCS705, I = 3.0 A 1.15

LCS708, I = 4.8 A 1.15

Power Supply

VCC Supply

Voltage Range VCC

See Note C

TJ = 0 to 100 °C 11.4 12 15 V

VCCH Supply

Voltage Range VCCH

See Note C

TJ = 0 to 100 °C 11.4 12 15 V

Start-Up Current ICC(OFF)

Undervoltage lockout state: VCC = 8 V

TJ = 0 to 100 °C 0.85 1 mA

Inhibit Current ICC(INHIBIT) VCC = 12 V, OV/UV < VSD(L), TJ = 0 to 100 °C 1.35 1.7 mA

VCC Operating

Current ICC(ON)

Typical at VCC = 12 V

Maximum at VCC =

15 V Measured at

300 kHz, HB Open

and VD = 15 V

TJ = 0 to 100 °C

LCS700 4.0 5.2

LCS701 4.4 5.8

LCS702 4.9 6.5

LCS703 5.4 7.1

LCS705 6.6 8.8

LCS708 8.8 11.8

VCCH Operating

Current ICCH(ON)

Typical at VCCH = 12 V

Maximum at VCCH =

15 V Measured at

300 kHz, HB Open

and VD = 15 V

TJ = 0 to 100 °C

LCS700 3.4 4.6

LCS701 3.9 5.2

LCS702 4.3 5.8

LSC703 4.7 6.4

LCS705 5.8 7.9

LCS708 7.8 10.7

VCC Supply Undervoltage Lockout

VCC Start Threshold VUVLO(+)

Device exits UVLO state when VCC exceeds

UVLO+, TJ = 0 to 100 °C 10 10.7 11.4 V

VCC Shutdown

Threshold VUVLO(-)

Device enters UVLO state when VCC falls

below UVLO+, TJ = 0 to 100 °C 9.1 9.8 10.5 V

VCC Start-Up/

Shutdown Hysteresis VUVLO(HYST) TJ = 0 to 100 °C 0.70 0.90 1.20 V

Rev. C 02/12

LCS700-708

www.powerint.com

Parameter Symbol

Conditions

SOURCE = 0 V; TJ = -40 °C to 125 °C

VCC = 12 V, VCCH = 12 V

(Unless Otherwise Speciﬁed)

Min Typ Max Units

VCCH Supply Undervoltage Lockout

VCCH Start Threshold VUVLO(H+)

Driver exits UVLO state when VCCH exceeds

UVLOH+, TJ = 0 to 100 °C 8.2 8.5 8.9 V

VCCH Shutdown

Threshold VUVLO(H-)

Driver enters UVLO state when VCCH falls

below UVLOH-, TJ = 0 to 100 °C 7.4 7.5 8.1 V

VCCH Start-Up/

Shutdown Hysteresis VUVLO(H)HYST TJ = 0 to 100 °C 0.65 0.75 1.00 V

High-Voltage Supply Undervoltage/Overvoltage Enable

OV/UV Overvoltage

Shutdown Threshold VOV(H)

Overvoltage assertion threshold

TJ = 0 to 100 °C 129 131 133 % of

VSD(H)

OV/UV Overvoltage

Recovery Threshold VOV(L)

Overvoltage de-assertion threshold

TJ = 0 to 100 °C 124 126 128 % of

VSD(H)

OV/UV Undervoltage

Start Threshold VSD(H)

Undervoltage de-assertion threshold

TJ = 0 to 100 °C 2.35 2.40 2.45 V

OV/UV Undervoltage

Shutdown Threshold VSD(L)

Undervoltage assertion threshold

TJ = 0 to 100 °C 77 79 81 % of

VSD(H)

OV/UV Pin

Input Resistance RIN(OVUV)

OV/UV pin resistance to G

TJ = 0 to 100 °C 3.0 5.0 6.6 MW

Reference

Reference Voltage VREF IREF = 4 mA, TJ = 0 to 100 °C 3.25 3.40 3.50 V

Current Source

Capability of VREF Pin IREF TJ = 0 to 100 °C 4 mA

VREF Capacitance CREF Required external coupling on VREF pin 1 mF

LLC Oscillator

Frequency Range FRANGE TJ = 0 to 100 °C 25 1000 kHz

Accuracy of Minimum

Frequency Limit

FMIN(ACC)

RFB = 37.9 kW to VREF , 180 kHz

TJ = 0 to 100 °C -5.0 5.0

FMIN(ACL)

RFB = 154 kW to VREF , 50 kHz

TJ = 0 to 100 °C -7.5 7.5

Accuracy of Maximum

Frequency Limit FMAX(ACC)

IFB = IDT/BF, RFMAX = 12.5 kW,

FMAX = 510 kHz, TJ = 0 to 100 °C -7.5 7.5 %

Duty Balance DLLC

Duty symmetry of the half-bridge wave-

form, CFB = 4.7 nF, CDT/BF = 4.7 nF, 250 kHz.

Use recommended layout, TJ = 0 to 100 °C

49 51 %

Dead-TimeBtD

RFMAX = 7 kW, RBURST = 39.6 kW

TJ = 0 to 100 °C 330 ns

DT/BF Control

Current Range IDT/BF TJ = 0 to 100 °C 30 430 mA

IFB Threshold to Stop

LLC Switching

ISTOP1

Threshold applies after exiting soft-start

mode for burst setting BT1, TJ = 0 to 100 °C 49.8

% of IDT/BF

ISTOP2

Threshold applies after exiting soft-start

mode for burst setting BT2, TJ = 0 to 100 °C 43.9

ISTOP3

Threshold applies after exiting soft-start

mode for burst setting BT3, TJ = 0 to 100 °C 37.1

Rev. C 02/12

LCS700-708

www.powerint.com

Parameter Symbol

Conditions

SOURCE = 0 V; TJ = -40 °C to 125 °C

VCC = 12 V, VCCH = 12 V

(Unless Otherwise Speciﬁed)

Min Typ Max Units

LLC Oscillator (cont.)

IFB Threshold

Hysteresis IBURST(HYST)

ISTART is IBURST(HYST) below ISTOP

TJ = 0 to 100 °C 5 6.25 8 % of IDT/BF

DT/BF Voltage to

Program Burst Setting

VBT1

Required VDT/BF at start-up to enable burst

setting BT1, TJ = 0 to 100 °C 93.5 95 96.3

% of VREF

VBT2

Required VDT/BF at start-up to enable burst

setting BT2, TJ = 0 to 100 °C 88.5 90 91.3

VBT3

Required VDT/BF at start-up to enable burst

setting BT3, TJ = 0 to 100 °C 83.5 85 86.3

Time Constant for the

Combination of RFMAX,

RBURST and the Decoup-

ling Cap on DT/BF

RCDT/BF

This time constant must be less than the

speciﬁed maximum to ensure correct

setting of burst mode.

TJ = 0 to 100 °C

100 ms

Feedback Current

Maximum IFB

Determines the maximum control

frequency that can be set by IFB

TJ = 0 to 100 °C

100 %IDT/BF

Feedback Control

Current Range IFB

IFB is limited by the current into DT/BF

TJ = 0 to 100 °C 15 430 mA

Feedback Virtual

Voltage VFB

FB input appears as RIN(FB) in series with

VFB, 30 mA < IFB < IDT/BF

TJ = 0 to 100 °C

0.65 V

Feedback Input

Resistance RIN(FB)

FB input appears as RIN(FB) in series with

VFB, 30 mA < IFB < IDT/BF

TJ = 0 to 100 °C

2.5 kW

Feedback Input

Resistance During

Soft-Start

RFB(SS)

FB input appears as RFB(SS) in series with

VREF during the soft-start delay interval or

when OV/UV < VSD or OV/UV > VOV

TJ = 0 to 100 °C

750 W

Over-Current Protection

Fast Over-Current

Fault Voltage

Threshold4

VIS(F) TJ = 0 to 100 °C 0.855 0.905 0.955 V

Slow Over-Current

Fault Voltage

Threshold

VIS(S)

7 LLC clock cycle debounce

TJ = 0 to 100 °C 0.455 0.505 0.555 V

Over-Current Fault

Pulse Width tIS

Minimum time VIS exceeds VIS(F)/VIS(S) per

cycle to trigger fault protection

TJ = 0 to 100 °C

30 ns

Over-Temperature Protection

Over-Temperature

Shutdown ThresholdATOT 140 °C

NOTES:

A. Guaranteed by design.

B. Typical apparent dead-time at the HB pin under resonant ZVS conditions.

C. VCC/VCCH operating range to achieve power capabilities speciﬁed in data sheet power table.

Rev. C 02/12

LCS700-708

www.powerint.com

PI-6183-022912

400 5003002001000 600 700 800

100

300

400

900

Frequency (kHz)

Power (mW)

200

600

500

700

800

LCS700

LCS701

LCS702

LCS703

LCS705

LCS708

PI-6184-112910

200 250150100500 300 350 400

200

400

800

1000

1200

Half-Bridge Voltage (V)

Capacitance (pF)

600

LCS700

LCS701

LCS702

LCS703

LCS705

LCS708

PI-6181-022912

400 5003002001000 600 700 800

Frequency (kHz)

Current (mA)

LCS700

LCS701

LCS702

LCS703

LCS705

LCS708

PI-6182-022912

400 5003002001000 600 700 800

Frequency (kHz)

Current (mA)

LCS700

LCS701

LCS702

LCS703

LCS705

LCS708

Figure 27. VCC Current vs. Frequency.

Figure 29. Control Power vs. Frequency.

Figure 28. VCCH Current vs. Frequency.

Figure 30. Half-Bridge Small Signal Capacitance vs. Half-Bridge Voltage.

Rev. C 02/12

LCS700-708

www.powerint.com

PI-5639-031011

Notes:

1. Dimensioning and tolerancing per ASME Y14.5M-1994.

2. Dimensions noted are determined at the outermost

extremes of the plastic body exclusive of mold flash,

tie bar burrs, gate burrs, and interlead flash, but

including any mismatch between the top and bottom

of the plastic body. Maximum mold protrusion is 0.007

[0.18] per side.

3. Dimensions noted are inclusive of plating thickness.

4. Does not include interlead flash or protrusions.

5. Controlling dimensions in inches (mm).

0.628 (15.95) Ref.

0.019 (0.48) Ref.

0.060 (1.52) Ref.

10° Ref.

All Around

0.021 (0.53)

0.019 (0.48)

0.048 (1.22)

0.046 (1.17)

0.027 (0.70)

0.023 (0.58)

0.038 (0.97)

0.076 (1.93)

0.118 (3.00)

0.029 Dia Hole

0.062 Dia Pad

0.020 (0.50)

0.016 (0.41)

Ref.

Detail A

0.118 (3.00)

0.140 (3.56)

0.120 (3.05)

0.081 (2.06)

0.077 (1.96)

13×

0.016 (0.41)

0.011 (0.28)

0.020 M 0.51 M C

0.290 (7.37)

Ref.

0.047 (1.19)

0.038 (0.97) 0.056 (1.42) Ref.

1 3 4 5 6 7 8 9 10 11 13 14 16

0.653 (16.59)

0.647 (16.43)

0.325 (8.25)

0.320 (8.13)

Pin 1 I.D.

0.214 (5.44)

Ref.

0.076 (1.93)

0.012 (0.30) Ref.

0.210 (5.33)

Ref.

0.207 (5.26)

0.187 (4.75)

13×

0.024 (0.61)

0.019 (0.48)

0.010 M 0.25 M C A B

0.519 (13.18)

Ref.

FRONT VIEW SIDE VIEW BACK VIEW

Detail A (Scale = 9×)

PCB FOOT PRINT

END VIEW

eSIP-16C (H Package)

Dimensions in inches, (mm).

All dimensions are for reference.

Rev. C 02/12

LCS700-708

www.powerint.com

PI-6454-020212

Notes:

1. Dimensioning and tolerancing per ASME Y14.5M-1994.

2. Dimensions noted are determined at the outermost

extremes of the plastic body exclusive of mold flash,

tie bar burrs, gate burrs, and interlead flash, but

including any mismatch between the top and bottom

of the plastic body. Maximum mold protrusion is 0.007

[0.18] per side.

3. Dimensions noted are inclusive of plating thickness.

4. Does not include interlead flash or protrusions.

5. Controlling dimensions in inches (mm).

0.038 (0.97)

0.076 (1.93)

0.094 (2.40)

0.029 Dia Hole

0.062 Dia Pad

FRONT VIEW SIDE VIEW BACK VIEW

Detail A (N.T.S.)

PCB FOOT PRINT

END VIEW

eSIP-16K (L Package)

0.628 (15.95) Ref.

0.019 (0.48) Ref.

0.060 (1.52) Ref.

10° Ref.

All Around

0.021 (0.53)

0.019 (0.48)

0.048 (1.22)

0.046 (1.17)

Dimensions in inches, (mm).

All dimensions are for reference.

0.653 (16.59)

0.647 (16.43)

0.325 (8.25)

0.320 (8.13)

Pin 1 I.D.

0.038 (0.97)

Typ. 9 Places

0.056 (1.42) Ref.

468101316

5791114

0.128 (3.26)

0.122 (3.10)

0.081 (2.06)

0.077 (1.96)

Detail A

0.094 (2.40)

0.047 (1.19) Ref.

0.050 (1.26) Ref.

0.144 (3.66) Ref.

0.290 (7.37)

Ref.

13×

0.016 (0.41)

0.011 (0.28)

0.020 M 0.51 M C

30.076 (1.93)

Typ. 3 Pieces

0.173 (4.39)

0.163 (4.14)

0.079 (1.99)

0.069 (1.74)

13×

0.024 (0.61)

0.019 (0.48)

0.010 M 0.25 M C A B

0.027 (0.70)

0.023 (0.58)

0.020 (0.50)

R0.012 (0.30)

Typ., Ref.

Rev. C 02/12

LCS700-708

www.powerint.com

Part Ordering Information

• Hiper Product Family

• LCS Series Number

• Package Identier

H Plastic eSIP-16C

L Plastic eSIP-16K

• Pin Finish

G Halogen Free and RoHS Compliant

• Tape & Reel and Other Options

Blank Standard Conﬁgurations

LCS 700 H G - TL

Rev. C 02/12

LCS700-708

www.powerint.com

Revision Notes Date

B Initial Release 06/20/11

C Added L Bend Parts 02/12

For the latest updates, visit our website: www.powerint.com

Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power

Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES

NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED

WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS.

Patent Information

The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered

by one or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A

complete list of Power Integrations patents may be found at www.powerint.com. Power Integrations grants its customers a license under

certain patent rights as set forth at http://www.powerint.com/ip.htm.

Life Support Policy

POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR

SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein:

1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii)

whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in signiﬁcant

injury or death to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause

the failure of the life support device or system, or to affect its safety or effectiveness.

The PI logo, TOPSwitch, TinySwitch, LinkSwitch, DPA-Switch, PeakSwitch, CAPZero, SENZero, LinkZero, HiperPFS, HiperTFS, HiperLCS,

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