M65609E
Rev. B – February 5, 2001 1
Preliminary
Introduction
The M65609E is a very low power CMOS static RAM
organized as 131072 × 8 bits.
Atmel Wireless & Microcontrollers brings the solution
to applications where fast computing is as mandatory as
low consumption, such as aerospace electronics,
portable instruments, or embarked systems.
Utilizing an array of six transistors (6T) memory cells,
the M65609E combines an extremely low standby
supply current (Typical value = 20 µA) with a fast
access time at 35 ns over the full military temperature
range. The high stability of the 6T cell provides
excellent protection against soft errors due to noise.
The M65609E is processed according to the methods of
the latest revision of the MIL STD 883 (class B or S),
ESA SCC 9000 or QML.
It is produced on the same process as the MH1RT sea of
gates series.
Features
DOperating voltage: 3.3 V
DAccess time: 35, 70 ns
DVery low power consumption
active : 200 mW (Max)
standby : 70 µW (Typ)
data retention: 50 µW (typ)
DWide temperature Range : –55 To +125°C
D400 Mils width package
DTTL compatible inputs and outputs
DAsynchronous
DDesigned on 0.35 micron process
DLatch up immune
D200 Krads capability
DSEU LET better than 3 MeV
Interface
Block Diagram
9
10
128 K 8 Very Low Power CMOS SRAM Rad Tolerant
M65609E
Rev. B – February 5, 2001
2
Preliminary
Pin Configuration
Pin Names
A0–A16 Address inputs
I/O0–I/O7 Data Input/Output
CS1Chip select 1
CS2Chip select 2
WWrite Enable
OE Output Enable
VCC Power
GND Ground
Truth Table
CS1CS2W OE INPUTS/
OUTPUTS MODE
H X X X Z Deselect/
Power-down
X L X X Z Deselect/
Power Down
L H H L Data Out Read
L H L X Data In Write
L H H H Z Output Disable
L = low, H = high, X = H or L, Z = high impedance.
32 pins Flatpack 400 MILS
VCC
A4
I/02
A7
I/01
A3
A6
A8
A0
A1
CS2
I/05
A2
W
I/06
GND
A5
A16
I/03
A15
A12
I/04
A13
A14
A9
A10
I/08
A11
OE
I/07
GND
CSI
M65609E
Rev. B – February 5, 2001 3
Preliminary
Electrical Characteristics
Absolute Maximum Ratings
Supply voltage to GND potential : - 0.5 V + 5 V. . . . . . . . . . . . . . . .
DC input voltage : GND – 0,3 V to VCC + 0,3. . . . . . . . . . . . . . . . .
DC output voltage high Z state : GND – 0,3 V to VCC + 0,3. . . . . .
Storage temperature : –65 °C to + 150 °C. . . . . . . . . . . . . . . . . . . . . .
Output current into outputs (low) : 20 mA. . . . . . . . . . . . . . . . . . . . . .
Electro statics discharge voltage : > 2 001 V. . . . . . . . . . . . . . . . . . .
(MIL STD 883D method 3015.3)
Operating Range
OPERATING VOLTAGE OPERATING TEMPERATURE
Military 3.3 V ± 10 % – 55 _C to + 125 _C
Recommended DC Operating Conditions
PARAMETER DESCRIPTION MINIMUM TYPICAL MAXIMUM UNIT
Vcc Supply voltage 3 3.3 3.6 V
Gnd Ground 0.0 0.0 0.0 V
VIL Input low voltage GND – 0.3 0.0 0.8 V
VIH Input high voltage 2.2 –VCC + 0.3 V
Capacitance
PARAMETER DESCRIPTION MINIMUM TYPICAL MAXIMUM UNIT
Cin (1) Input low voltage – – 8 pF
Cout (1) Output high volt – – 8 pF
Note : 1. Guaranteed but not tested.
DC Parameters
PARAMETER DESCRIPTION MINIMUM TYPICAL MAXIMUM UNIT
IIX (2) Input leakage current – 1 –1µA
IOZ (2) Output leakage current – 1 –1µA
VOL (3) Output low voltage – – 0.4 V
VOH (4) Output high voltage 2.4 – –
Notes : 2. Gnd < Vin < Vcc, Gnd < Vout < Vcc Output Disabled.
3. Vcc min. IOL = 1 mA.
4. Vcc min. IOH = 0.5 mA.
M65609E
Rev. B – February 5, 2001
4
Preliminary
Consumption
SYMBOL DESCRIPTION 65609E
– 35 UNIT VALUE
ICCSB (5) Standby supply current 2.5 mA max
ICCSB1 (6) Standby supply current 2 mA max
ICCOP (7) Dynamic operating current 65 mA max
Notes : 5. CS1 ≥ VIH or CS2 ≤ VIL and CS1 ≤ VIL.
6. CS1 ≥ Vcc – 0.3 V or, CS2 < Gnd + 0.3 V and CS1 ≤ 0.2 V
7. F = 1/TAVAV, Iout = 0 mA, W = OE = VIH, Vin = Gnd/Vcc, Vcc max.
M65609E
Rev. B – February 5, 2001 5
Preliminary
Write Cycle
SYMBOL PARAMETER 65609E
– 35 UNIT VALUE
TAVAW Write cycle time 35 ns min
TAVWL Address set-up time 10 ns min
TAVWH Address valid to end of write 28 ns min
TDVWH Data set-up time 23 ns min
TE1LWH CS1 low to write end 28 ns min
TE2HWH CS2 high to write end 28 ns min
TWLQZ Write low to high Z (11) 15 ns max
TWLWH Write pulse width 28 ns min
TWHAX Address hold from to end of write +3 ns min
TWHDX Data hold time 0 ns min
TWHQX Write high to low Z (11) 0 ns min
Read Cycle
SYMBOL PARAMETER 65609E
– 35 UNIT VALUE
TAVAV Read cycle time 35 ns min
TAVQV Address access time 35 ns max
TAVQX Address valid to low Z 5 ns min
TE1LQV Chip-select1 access time 35 ns max
TE1LQX CS1 low to low Z (11) 3 ns min
TE1HQZ CS1 high to high Z (11) 20 ns max
TE2HQV Chip-select2 access time 35 ns max
TE2HQX CS2 high to low Z (11) 3 ns min
TE2LQZ CS2 low to high Z (11) 20 ns max
TGLQV Output Enable access time 12 ns max
TGLQX OE low to low Z (11) 0 ns min
TGHQZ OE high to high Z (11) 10 ns max
Notes : 11. Parameters guaranteed, not tested, with output loading 5 pF. (see fig. 1.b.).
M65609E
Rev. B – February 5, 2001
6
Preliminary
Write Cycle 1. W Controlled. OE High During Write
TAVAW
Write Cycle 2. W Controlled. OE Low
TAVAW
M65609E
Rev. B – February 5, 2001 7
Preliminary
Write Cycle 3. CS1 or CS2 Controlled.
TAVAW
Note : 12. The internal write time of the memory is defined by the overlap of CS1 Low and CS2 HIGH and W LOW. Both signals must be
actived to initiate a write and either signal can terminate a write by going in actived. The data input setup and hold timing should be
referenced to the actived edge of the signal that terminates the write.
Data out is high impedance if OE = VIH.
M65609E
Rev. B – February 5, 2001
8
Preliminary
Read Cycle nb 1
Read Cycle nb 2
Read Cycle nb 3
M65609E
Rev. B – February 5, 2001 9
Preliminary
Ordering Information
M = Military –55°to +125°C
S = Space –55°to +125°C
DJ = Flat Package 32 pins 400 mils
0 = die
128K × 8
STATIC RAM
blank = MHS standards
/883 = MIL-STD 883 Class B or S
SB/SC = SCC 9000 level B/C
M– 65609ES DJ V
TEMPERATURE RANGE PACKAGE DEVICE SPEED FLOW*
– 35
V = Very low power
GRADE
/883
35 ns
70 ns
* For ordering in QML quality level, use the QML PIN according to SMD number (to be defined).
The information contained herein is subject to change without notice. No r esponsibility is assumed by Atmel W ireless & Microcontrollers for using this
publication and/or circuits described herein : nor for any possible infringements of patents or other rights of thir d parties which may result from its use.
