CY25403/CY25423/CY25483
Three PLL Programmable Clock Generator
with Spread Spectrum
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 001-12564 Rev. *F Revised July 18, 201 1
Features
■Three fully integrated phase-locked loops (PLLs)
■Input frequency range
❐External crystal: 8 to 48 MHz
❐External reference: 8 to 166 MHz clock
■Reference clock input voltage range
❐1.8 V for CY25403/CY25423/CY25483
■Wide operating output frequency range
❐3 to 166 MHz
■Programmable spread spectrum with center and down spread
option and lexmark and linear modulation profiles
■VDD supply voltage options:
❐2.5 V, 3.0 V, and 3.3 V for CY25403/CY25423/CY25483
■Selectable output clock voltages independent of VDD supply:
❐2.5 V, 3.0 V, and 3.3 V for CY25403/CY25423/CY25483
■Frequency select feature with option to select four different
frequencies
■Power-down, output enable, and SS ON/OFF controls
■Low jitter, high accuracy outputs
■Ability to synthesize nonstandard frequencies with Fractional-N
capability
■Three clock outputs with programmable drive strength
■Glitch-free outputs while frequency switching
■8-pin SOIC package
■Commercial and Industrial temperature ranges
Benefits
■Multiple high performance PLLs allow synthesis of unrelated
frequencies
■Nonvolatile programming for personalization of PLL
frequencies, spread spectrum characteristics, drive strength,
crystal load capacitance, and output frequencies
■Application specific programmable EMI reduction using Spread
Spectrum for clocks
■Programmable PLLs for system frequency margin tests
■Meets critical timing requirements in complex system designs
■Suitability for PC, consumer, portable, and networking
applications
■Capable of Zero PPM frequency synthesis error
■Uninterrupted system operation during clock frequency switch
■Application compatibility in standard and low power systems
Block Diagram
OSC PLL1
PLL3
(SS)
CLK3
(SS)
CLK2
(No SS
)
CLK1
(SS)
Crossbar
Switch
FS1
SSON
XOUT
XIN/
EXCLKIN
PD#/OE
PLL 2
(SS)
FS0
MUX
and
Control
Logic
Output
Dividers
and
Drive
Strength
Control
CY25403/CY25423/CY25483
Document #: 001-12564 Rev. *F Page 2 of 14
Contents
General Description .........................................................4
Configurable PLLs .......................................................4
Input Reference Clocks ...............................................4
VDD Power Supply Options .............. ... .......................4
Spread Spectrum Control ............................................4
Frequency Select ........................................................4
Glitch-Free Frequency Switch .....................................4
PD#/OE Mode ..................... ... .............. ... .............. ......4
Output Drive Strength ..................................................4
Generic Configuration and Custom Frequency ...........4
Absolute Maximum Conditions .......................................5
DC Electrical Specificati on s ............. ... .. .............. ... .........6
AC Electrical Specificati on s ............. ... .. .............. ... .........7
Recommended Crystal Sp ecification
for SMD Package ..............................................................7
Recommended Crystal Specification
for Thru-Hole Package .....................................................8
Test and Measurement Setup ..........................................8
Voltage and Timing Definiti ons .................. .. .............. ... ..8
Ordering Information ........................................................9
Possible Configurations ........... ............... .. ... .............. ..9
Ordering Code Definitions .........................................10
Package Drawing and Dimensions ...............................10
Acronyms ........................................................................ 11
Document Conventions ..................... ... .............. ... ........12
Units of Measure .............................. ... .............. ... .. ...12
Sales, Solutions, and Legal Information ......................14
Worldwide Sales and Design Support .......................14
Products .................................................................... 14
PSoC Solutions ............... ... ... .............. ... .. .............. ...14
CY25403/CY25423/CY25483
Document #: 001-12564 Rev. *F Page 3 of 14
Table 1. Device Selector Guide
Figure 1. Pin Diagram - CY25403/CY25423/CY25483 8-Pin SOIC
Table 2. Pin Definition - CY25403/CY25423/CY25483 (2.5 V, 3.0 V, or 3.3 V Supply)
Device Crysta l In put EXCKLKIN Input VDD
CY25403/CY25423/CY25483 Yes 1.8 V LVCMOS 2.5V, 3.0V, 3.3V
Pin Number Name IO Description
1 XIN/EXCLKIN Input Crystal input or 1.8 V external clock input
2V
DD Power Power supply: 2.5 V, 3.0 V, or 3.3 V
3 CLK1 Output Programmable clock output with spread spectrum
4 CLK2/FS0 Output/Input Multifunction programmable pin: programmable clock output with no spread spectrum
or frequency select pin
5 PD#/OE/FS1 Input Multifunction programmable pin: power-down, output enable, or frequency select pin
6 CLK3/SSON Output/Input Multifunction programmable pin: programmable clock output with spread spectrum or
spread spectrum ON/OFF control pin
7 GND Power Power supply ground
8 XOUT Output Crystal output
VDD CY25403
1
2
3
4
8
7
6
5
XOUT
GND
CLK3/SSON
PD#/OE/FS1
XIN/
EXCLKIN
CLK1
CLK2/FS0
CY25403/CY25423/CY25483
Document #: 001-12564 Rev. *F Page 4 of 14
General Description
Configurable PLLs
The CY25403/CY25423 /CY25483 have three programmable
PLLs that can be used to generate output freque ncies ranging
from 3 to 166 MHz. The advantage of having three PLLs is that
a single device generates up to three independent frequencies
from a single crystal.
Input Reference Clocks
The input reference clock can be either a crystal or a clock signal,
for CY25403/CY25423/CY25483. The input frequency range for
crystal (XIN) is 8 MHz to 48 MHz and that for external reference
clock (EXCLKIN) is 8 MHz to 166 MHz. The voltage range of the
reference clock input CY25403/CY25423/CY25483 is 1.8 V. This
gives user an option for this device to be compatible for different
input clock voltage levels in the system.
VDD Power Supply Options
These devices have programmable power supply options. The
CY25403/CY25423/CY25483 is a high voltage part that can be
programmed to operate at any voltage 2.5 V, 3.0 V, or 3.3 V.
Output Source Selection
These devices have programmable input sources for each of its
clock outputs. There are four available clock sources and these
clock sources are: XIN/EXCLKIN, PLL1, PLL2, and PLL3.
Output clock source selection is done by using four out of four
crossbar switch. Thus, any one of these four available clock
sources can be arbitrarily selected for the clock outputs. This
gives user a flexibility to have up to three indepe ndent clock
outputs.
Spread Spectrum Control
Two of the three PLLs (PLL2 and PLL3) have spread spectrum
capability for EMI reduction in the system. The device uses a
Cypress proprietary PLL and spread spectrum clock (SSC)
technology to synthesize and modulate the frequency of the PLL.
The spread spectrum feature can be turned on or off using a
multifunction control pin (CLK3/SSON). It can be programmed to
either center spread range from ±0.12 5% to ±2.50% or down
spread range from –0.25% to –5.0% with Lexmark or Linear
profile.
Frequency Select
Each PLL can be programmed for up to four different
frequencies. There are two multifunction programmable pins,
CLK2/FS0 and PD#/OE/FS1 which if programmed as frequency
select inputs, can be used to select among these arbitrarily
programmed frequency settings. Each output has
programmable output divider options.
Glitch-Free Frequency Switch
When the frequency select pin, FS(1:0) is used to switch
frequency, the outputs are glitch-free provided frequency is
switched using output dividers. This featur e enables
uninterrupte d system operation while clock frequency is being
switched.
PD#/OE Mode
Multifunction pin PD#/OE/FS1 (Pin 5) can be programmed to
operate as either frequency select (FS1), power-down (PD#) or
output enable (OE) mode. PD# is a low-true input. If activated it
shuts off the entire chip, resulting in minimum power
consumption for the device. Setting this signal high brings the
device in the operational mode with default register settings.
When this pin is programmed as output enable (OE), clock
outputs can be enabled or disabled using OE (pin 5). Individual
clock outputs can be programmed to be sensitive to this OE pin.
Output Drive Strength
The DC drive strength of the individual clock output can be
programmed for different values. Table 3 shows the typical rise
and fall times for different drive strength settings.
Generic Configuration and Custom Frequency
There is a generic set of output frequencies available from the
factory that can be used for the device evaluation purposes. The
device, CY25403/CY25423/CY25483 can be custom
programmed to any desired frequencies and listed features. For
customer specific programming, please contact local Cypress
Field Application Engineer (FAE) or sales
representative.
Table 3. Output Drive Streng th
Output Drive Strength Rise/Fall Time (ns)
(Typical Value)
Low 6.8
Mid Low 3.4
Mid High 2.0
High 1.0
CY25403/CY25423/CY25483
Document #: 001-12564 Rev. *F Page 5 of 14
Absolute Maximum Conditions
Parameter Description Condition Min Max Unit
VDD Supply voltage for CY25403/CY25423/CY25483 – –0.5 4.5 V
VIN Input voltage for CY25403/CY25423/CY25483 Relative to VSS –0.5 VDD+0.5 V
TSTemperature, Storage Non Functional –65 +150 °C
ESDHBM ESD protection (human body model) JEDEC EIA/JESD22-A114-E 2000 Volts
UL-94 Flammability rating V-0 at 1/8 in. – 10 ppm
MSL Moisture sensitivity level SOIC package –3 –
Recommended Operating Conditions
Parameter Description Min Typ Max Unit
VDD VDD operating voltage for CY25403/CY25423/CY25483 2.25 – 3.60 V
TAC Commercial ambient temperature 0 – +70 °C
TAI Industrial ambient temperature –40 -- +85 °C
CLOAD Maximum load capacitance – – 15 pF
tPU Power-up time for all VDD to reach minimum speci fi e d voltag e
(power ramps must be monotonic) 0.05 – 500 ms
CY25403/CY25423/CY25483
Document #: 001-12564 Rev. *F Page 6 of 14
DC Electrical Specifications
Parameter Description Conditions Min Typ Max Unit
VOL Output low voltage IOL = 2 mA, drive strength = [00] – – 0.4 V
IOL = 3 mA, drive strength = [01]
IOL = 7 mA, drive strength = [10]
IOL = 12 mA, drive strength = [11]
VOH Output high voltage IOH = –2 mA, drive strength = [00] V DD -
0.4 –– V
IOH = –3 mA, drive strength = [01]
IOH = –7 mA, drive strength = [10]
IOH = –12 mA, drive strength = [11]
VIL1 Input low voltage of PD#/OE, FS0, FS1
and SSON – – 0.2*VDD V
VIL2 Input low voltage of EXCLKIN – – 0.18 V
VIH1 Input high voltage of PD#/OE, FS0, FS1
and SSON 0.8*VDD –– V
VIH2 Input high voltage of EXCLKIN for
CY25403/CY25423/CY25483 1.62 – 2.2 V
IIL Input low current, PD#/OE/FS1 VIN = 0 V – – 10 µA
IIH Input high current, PD#/OE/FS1 VIN = VDD – – 10 µA
IILDN Input low current, SSON and FS0 pin s VIN = 0 V
(Internal pull-down resistor = 160k typ .) – – 10 µA
IIHDN Input high current, SSON and FS0 pins VIN = VDD
(Internal pull-down resistor = 160k typ .) 14 – 36 µA
RDN Pull-down resistor of CLK1, CLK2/FS0
and CLK3/SSON pins Output clocks in off state by setting
PD# = Low 100 160 250 k
IDD[1,2 ] Supply current for
CY25403/CY25423/CY25483 PD# = High, No load – 22 – mA
IDDS[1] Standby current PD# = Low – 3 – µA
CIN[1] Input capacitance SSON, PD#/OE/FS1 and FS0 pins – – 7 pF
Notes
1. Guaranteed by design but not 100% test ed.
2. Configuration dependent.
CY25403/CY25423/CY25483
Document #: 001-12564 Rev. *F Page 7 of 14
AC Electrical Specifications
Parameter Description Conditions Min Typ Max Unit
FIN (crystal) Crystal frequency, XIN – 8 – 48 MH
z
FIN (clock) Input clock frequency (EXCLKIN) – 8 – 166 MH
z
FCLK Output clock frequency – 3 – 166 MH
z
DC Output duty cycle, all clocks except ref
out Duty Cycle is defined in Figure 3 on page 8;
t1/t2, measured at 50% of VDD 45 50 55 %
DC Ref out duty cycle Ref In Min 45%, Max 55% 40 – 60 %
TRF1[3] Output rise/fall time Measured from 20% to 80% of VDD, as
shown in Figure 4 on page 8, CL = 15 p F,
drive strength [00]
–6.8–ns
TRF2[3] Output rise/fall time Measured from 20% to 80% of VDD, as
shown in Figure 4 on page 8, CL = 15 p F,
drive strength [01]
–3.4–ns
TRF3[3] Output rise/fall time Measured from 20% to 80% of VDD, as
shown in Figure 4 on page 8, CL = 15 p F,
drive strength [10]
–2.0–ns
TRF4[3] Output rise/fall time Measured from 20% to 80% of VDD, as
shown in Figure 4 on page 8, CL = 15 p F,
drive strength [11]
–1.0–ns
TCCJ[3, 4] Cycle-to-cycle jitter (peak) Configuration dependent. See
Table Configuration Example for C-C Jitter – 100 – ps
TLOCK[3] PLL lock time Measured from 90% of the applied power
supply lev e l –13ms
Configuration Examp le for C-C Jitter
Ref. Frequency
(MHz)
CLK1 Output CLK2 Output CLK3 Output
Freq. (MHz) C-C Jitter Typ
(ps) Freq. (MHz) C-C Jitter Ty p
(ps) Freq. (MHz) C-C Jitter Typ
(ps)
14.3181 8.0 134 166 103 48 92
19.2 74.25 99 166 94 8 91
27 48 67 27 109 166 103
48 48 93 27 123 166 137
Recommended Crystal Specification for SMD Package
Parameter Description Range 1 Range 2 Range 3 Unit
Fmin Minimum fre quency 8 14 28 MHz
Fmax Maximum frequency 14 28 48 MHz
R1 Motional resistance (ESR) 135 50 30
C0 Shunt capacitance 4 4 2 pF
CL Parallel load capacitance 18 14 12 pF
DL(max) Maximum crystal drive level 300 300 300 µW
CY25403/CY25423/CY25483
Document #: 001-12564 Rev. *F Page 8 of 14
Test and Measurement Setup
Figure 2. Test and Measurement Setup
Voltage and Timing Definitions
Figure 3. Duty Cycle Definition
Figure 4. Rise Time = TRF, Fall Time = TRF
Notes
3. Guaranteed by design but not 100% tested.
4. Configuration dependent.
Recommended Crystal Specification for Thru-Hole Package
Parameter Description Range 1 Range 2 Range 3 Unit
Fmin Minimum frequency 8 14 24 MHz
Fmax Maximum frequency 14 24 32 MHz
R1 Motional resistance (ESR) 90 50 30
C0 Shunt capacitance 7 7 7 p F
CL Parallel load capacitance 18 12 12 pF
DL(max) Maximum crystal drive level 1000 1000 1000 µW
Clock
Output
V
DD
50% of V
DD
0V
t
1
t
2
Clock
Output
T
RF TRF
V DD
80% of V
DD
20% of V
DD
0V
CY25403/CY25423/CY25483
Document #: 001-12564 Rev. *F Page 9 of 14
Ordering Information
Some product offerings are factory programmed customer specific devices with customized part numbers. The Possible
Configurations table shows the available device types, but not complete part numbers. Contact your local Cypress FAE of Sales
Representative for more information
Possible Configurations
Part Number Type Package Supply Voltage Production Flow
Pb-free
CY25403SXC Field Programmable 8-pin SOIC 2.5 V, 3.0 V, or 3.3 V Commercial, 0 °C to 70 °C
CY25403SXCT F ield Programmable 8-pin SOIC -Tape and Reel 2.5 V, 3.0 V, or 3.3 V Commercial, 0 °C to 70 °C
CY25423SXC Field Programmable 8-pin SOIC 1.8 V Commercial, 0 °C to 70 °C
CY25423SXCT Field Programmable 8-pin SOIC -Tape and Reel 1.8 V Commercial, 0 °C to 70 °C
CY25483SXC Field Programmable 8-pin SOIC 2.5 V, 3.0 V, or 3.3 V Commercial, 0 °C to 70 °C
CY25483SXCT F ield Programmable 8-pin SOIC -Tape and Reel 2.5 V, 3.0 V, or 3.3 V Commercial, 0 °C to 70 °C
CY25403SXI Field Programmable 8-pin SOIC 2.5 V, 3.0 V, or 3.3 V Industrial, –40 °C to +85 °C
CY25403SXIT Field Programmable 8-pin SOIC -Tape and Reel 2.5 V, 3.0 V, or 3.3 V Industrial, –40 °C to +85 °C
CY25423SXI Field Programmable 8-pin SOIC 1.8 V Industrial, –40 °C to +85 °C
CY25423SXIT Field Programmable 8-pin SOIC -Tape and Ree l 1.8 V Industrial, –40 °C to +85 °C
CY25483SXI Field Programmable 8-pin SOIC 2.5 V, 3.0 V, or 3.3 V Industrial, –40 °C to +85 °C
CY25483SXIT Field Programmable 8-pin SOIC -Tape and Reel 2.5 V, 3.0 V, or 3.3 V Industrial, –40 °C to +85 °C
Programmer
CY3675-CLKMAKER1 Programming Kit
CY3675-SOIC8A Socket Adapter Board, for programming CY25402, CY25403, CY25422,
CY25423, CY25482, and CY25483
Part Number[5] Type VDD(V) Production Flow
Pb-free
CY25403/CY25423/CY254
83SXC-xxx 8-pin SOIC Supply Voltage: 2.5 V, 3.0 V, or 3.3 V Commercial, 0 °C to 70 °C
CY25403/CY25423/CY254
83SXC-xxxT 8-pin SOIC -Tape and Reel Supply Voltage: 2.5 V, 3.0 V, or 3.3 V Commercial, 0 °C to 70 °C
CY25403/CY25423/CY254
83SXI-xxx 8-pin SOIC Supply Voltage: 2.5 V, 3.0 V, or 3.3 V Industrial, –40 °C to +85 °C
CY25403/CY25423/CY254
83SXI-xxxT 8-pin SOIC -Tape and Reel Supply Voltage: 2.5 V, 3.0 V, or 3.3 V Industrial, –40 °C to +85 °C
Notes
5. xxx indicates factory programmed parts based on customer specific configuration. For more details, contact your local Cypress FAE or Sales Representative.
CY25403/CY25423/CY25483
Document #: 001-12564 Rev. *F Page 10 of 14
Ordering Code Definitions
Package Drawing and Dimensions
Figure 5. 8-Pin (150-Mil ) SOIC S8
Package Type: (T = Tape and Reel)
Customer specific identification code
Temperatu re code (C=Commercial or I=Industrial)
8-Pin SOIC package
Marketing Code: CY25403/23/83 = Device Number
SX C/I - xxx T
CY254x3
51-85066 *E
CY25403/CY25423/CY25483
Document #: 001-12564 Rev. *F Page 11 of 14
Acronyms
Acronym Description
DL drive level
DNU do not use
DUT device under test
EIA Electronic Industries Alliance
EMI electromagnetic in terference
ESD electrostatic discharge
FAE field application engineer
FS frequency select
JEDEC joint electron devices
engineering council
LVCMOS low voltage complementary
metal oxide semiconductor
OE output enable
OSC oscillator
PD power-down
PLL phase-locked loop
PPM parts per million
SS spread spectrum
SSC spread spectrum clock
SSON spread spectrum on
CY25403/CY25423/CY25483
Document #: 001-12564 Rev. *F Page 12 of 14
Document Conventions
Units of Measure
Symbol Unit of Measure
C degree Celsius
mA milliamperes
MHz megahertz
ms milliseconds
ns nanoseconds
pF picofarad
ps picoseconds
Vvolts
µA microamperes
CY25403/CY25423/CY25483
Document #: 001-12564 Rev. *F Page 13 of 14
Document History Page
Document Title: CY25403/CY25423/CY25483 Three PLL Progr ammab le Clock Generator with Spread Spectrum
Document Number: 001-12564
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 690296 See ECN RGL New Data Sheet
*A 815788 See ECN RGL Minor Change: To post on web
*B 1428744 See ECN RGL/AESA Changed data sheet format to match generic part, CY2544/46
Added new device and specification for high ref. input voltage part,
CY7C1512KV18
Removed Preliminary from Title page
Replaced CLK2 with REFOUT
*C 2748211 08/10/09 TSAI Posting to external web.
*D 2899300 03/25/10 CXQ Updated Ordering Information. Added note regarding Possible Configurations
in Ordering Informati on section.
Added Possible Configurations table for “xxx’ parts.
Updated Package Drawing and Dimensions
*E 289856 8 06/02/10 CXQ Updated Ordering Information and template.
*F 3319132 07/18/11 BASH Updated to latest template
Updated Package Drawing and Dimensions
Added Units of Measure
Added Contents
Document #: 001-12564 Rev. *F Revised July 18, 2011 Page 14 of 14
CY25403/CY25423/CY25483
© Cypress Semico nducto r Co rpor ation , 20 07-2 011. The infor mation cont ai ned he rein is subj ect to chang e wit hou t notice. Cypr ess Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypre ss prod uc ts are n ot war r ant ed no r inte nd ed to be used fo r
medical, life supp or t, l if e savin g, cr it ical control or saf ety ap pl ic at io ns, unless pursuant to a n express written ag re em en t with Cypress. Furthermor e, Cyp ress doe s not author iz e its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypr ess products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protect ion (Unit ed States and fore ign),
United S t ates copyright laws and international treaty provis ions. Cyp ress he reby gr ant s to l icense e a pers onal, no n-excl usive , non-tr ansfer able license to copy, use, modify, create derivative works of ,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product t o be used only in conju nction with a Cypress
integrated circui t as specified in the applicab le agreement. Any r eproduction, mod ification, translati on, compilatio n, or represent ation of this Sour ce Code except a s specified abo ve is prohibit ed without
the express written permis sion of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTA BILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials describ ed herein. Cy press does n ot
assume any liabil ity ar ising ou t of the a pplic ation or use o f any pr oduct or circ uit descri bed herein . Cypress d oes not a uthor ize its p roducts fo r use as critical componen ts in life-su pport systems whe re
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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